x ANOH* een ese Military & Space Products Honeywell 5.12 MEGABIT MEMORY MODULE HX84050 RADIATION e Fabricated with RICMOS IV Silicon on Insulator (SOl) 0.75 um Process (L,, = 0.6 um) * Total Dose Hardness through 1x10 rad (SiO,) * Neutron Hardness through 1x10'4 cm? Dynamic and Static Transient Upset Hardness through 1x10 rad (Si)/s * Dose Rate Survivability through 1x10"? rad(Si)/s * Soft Error Rate of <1x10 upsets/bit-day Latchup Free OTHER Read/Write Cycle Times <$ 17 ns (Typical) < 25 ns (-55 to 125C) Asynchronous Operation * CMOS or TTL Compatible I/O * Single 5 V + 10% Power Supply * Low Operating Power * 200-Lead Quad Flat Pack (2.1 in. x 2.1 in.) GENERAL DESCRIPTION A major emphasis in Honeywell's packaging program is the use of multichip modules (MCMs). Use of multichip mod- ules will result in higher density packaging of integrated circuits (ICs) and components, lower weight and volume associated with size reduction, higher performance due to a decrease in interconnect length, and additional improve- ment with new material systems. Honeywell has had a leading role in the development and application of multichip modules for the last 13 years. In conjunction with the basic technology, we have also developed the required tools and methodology for the design of MCMs, materials/processes for assembly of MCMs, test capability tor MIL STD screen- ing, and the test capability for identifying known good die (KGD) for testing of assembled MCMs. The MCM is organized into two separate 64K x 40 memory banks. Each memory bank contains two 32K x 40 blocks, using five SRAMs each. The two banks of memory are connected to different busses, making them logically and physically separate within each bank. Only one block is enabled and consuming power at any given time. The die are packaged in a 200 pin 2.1" x 2.1" co-fired substrate ceramic flat package. Solid State Electronics Center * 12001 State Highway 55, Plymouth, MN 55441 (800) 323-8295 http:/Awww.ssec.honeywell.comHX84050 FUNCTIONAL DIAGRAMS 64K x 40 Memory Bank A 64K x 40 Memory Bank B A_DATA(39:0} B_DATA(39:0) 32K x 40 Memory Btock 32K x 40 Memory Block 0 S2Kx8 32K x 40 Memory Block 1 32K x 40 Memory Block 1 Figure 1. 2x 64K x 40 (Top Level Diagram) OATA (39: 0) BANK A, BLOCK 0 ADDRESS (14 0} BERLEERTSEZZZ Figure 2. 32K x 40 Memory Block Functional Diagram A:3-7,12,14-16 3 Row : 90.768 x8 Decoder jemory . Array <> | Column Decoder <e} ncs } >-+__ tc _ Data Input/Output DQ:0-7 ___ 8 ~_weecs-ce | *CS*CEe 1 = enabled \_NWE *CS CE + OE Signal ' {1 J = = high) Signal All controls must be enabled for a signal to pass. (#: number of buffers, default = 1) Figure 3. 32K x 8 SRAM Functional Diagram NWE Lt A:0-2, 8-11, 13 8 2HX84050 SIGNAL DEFINITIONS Signal definitions for an individual SRAM within the five chip 32K x 40 memory block are shown below. A: 0-14 Address input pins (A) which select a particular eight bit word within the memory array. A: 0-3 (Column Select) A: 4-11 (Row Select) A: 12-14 (Block Select) DQ:0-7 Bi-directional data pins which serve as data outputs during a read operation and as data inputs during a write operation. NCS Negative chip select, when at a low level, allows normal read or write operation. When at a high level it defaults the SRAM to a pre-charge condition and holds the data output drivers in a high impedance state. All input signals except NCS and CE are disabled. The dynamic and DC IDD chip current contribution trom all other input circuits caused by input pins transitioning and/or at VDD or VSS is eliminated. If the NCS signal is not used it must be connected to VSS. NWE Negative write enable, when at a low level activates a write operation and holds the data output drivers in a high impedance state. When at a high level it allows normal read operation. NOE Negative output enable, when at a high level holds the data output drivers in a high impedance state. When at a low level, the data output driver state is defined by NCS, NWE and CE. If the NOE signal is not used it must be connected to VSS. CE Chip enable, when at a high level, allows normal operation. When at a low level it forces the array to a pre- charge condition, holds the data output drivers in a high impedance state and disables all the input buffers except CE and NCS. The dynamic and DC IDD chip current contribution from all other input circuits caused by input pins transitioning and/or not at VDD or VSS levels is eliminated. If the CE signal is not used it must be connected to VDD. TRUTH TABLE CE NCS NWE NOE MODE DQ H L H L Read Data Out Notes: H L L X Write Data In X: VieVIH or VIL . XX: VSSsVisVDD X H XX XX Deselected| High 2 NOEsH: High Z output state maintained L xX XX XX Disabled High Z for NCS=X, CE=X, NWE=XHX84050 RADIATION CHARACTERISTICS Total lonizing Radiation Dose The memory module will meet all stated functional and electrical specifications over the entire operating tempera- ture range after the specified total ionizing radiation dose. All electrical and timing performance parameters will re- main within specifications after rebound at VDD = 5.5 V and T =125C extrapolated to ten years of operation. Total dose hardness is assured by wafer level testing of process monitor transistors and RAM product using 10 keV X-ray and Co60 radiation sources. Transistor gate threshold shift correlations have been made between 10 keV X-rays applied at a dose rate of 1x10* rad(SiO,)/min at T = 25C and gamma rays (Cobalt 60 source) to ensure that wafer level X-ray testing is consistent with standard military radiation test environments. Transient Pulse lonizing Radiation The memory module is capable of writing, reading, and retaining stored data during and after exposure to a tran- sient ionizing radiation pulse of <1 ws duration up to 1x10 rad(Si)/s, when applied under recommended operating conditions. The memory module will meet any functional or electrical specification after exposure to a radiation pulse of < 50 ns duration up to 1x10"' rad(Si)/s, when applied under recom- mended operating conditions. Note that the current con- ducted during the pulse by the RAM inputs, outputs, and power supply may significantly exceed the normal operat- ing levels. The application design must accommodate these effects. RADIATION HARDNESS RATINGS (1) Neutron Radiation The memory module will meet any functional or timing speci- fication after a total neutron fluence of up to 1x10"* cm? applied under recommended operating or storage conditions. This assumes an equivalent neutron energy of 1 MeV. Soft Error Rate The memory module is capable of soft error rate (SER) performance of <1x10" upsets/bit-day, under recommended operating conditions. This hardness level is defined by the Adams 10% worst case cosmic ray environment. Latchup The memory module will not latch up due to any of the above radiation exposure conditions when applied under recom- mended operating conditions. Fabrication with the SIMOX substrate material provides oxide isolation between adjacent PMOS and NMOS transistors and eliminates any potential SCR lIatchup structures. Sufficient transistor body tie con- nections to the p- and n-channel substrates are made to ensure no source/drain snapback occurs. Parameter Limits (2) Units Test Conditions > 6 i Ta=25C, VDD=S5.5V. Total Dose 21x10 rad(SiO,) X-ray or'C060 Transient Dose Rate Upset 21x10 rad(Si)/s Pulse width <1 ps i i ili j Pul: h Transient Dose Rate Survivability 21x10" rad(Si)/s vOBe yin 50 Ds, X X-ray, . ; , 10% Soft Error Rate <1x10" upsets/bit-day ayaa Coe 1M Neutron Fluence 21x10" N/cm? U Mev equivalent a energy, (1) Device will not latch up due to any of the specified radiation exposure conditions. (2) Operating conditions (unless otherwise specified): VDD=4.5 V to 5.5 V, TA=-55C to 125C.HX84050 ABSOLUTE MAXIMUM RATINGS (1) Rating Symbol Parameter Min Max Units VDD Positive Supply Voitage (2) -0.5 7.0 Vv VPIN Voltage on Any Pin (2) -0.5 VDD+0.5 Vv VOZ Output Voltage Applied to High Z State (VIN and VOUT) -0.3 VDD+0.3 Vv TSTORE Storage Temperature (Zero Bias) -65 150 C TSOLDER Soldering Temperature (10 sec) +288 C PD Total Package Power Dissipation (3) 5.6 Ww OUT DC or Average Output Current mA VPROT ESD Input Protection Voltage 2000 Vv OJC Thermal Resistance (Jct-to-Case) (4) 4.0 C/W TJ Junction Temperature 175 C (1) Stresses in excess of those listed above may result in permanent damage. These are stress ratings only, and operation at these levels is not implied. Frequent or extended exposure to absoiute maximum conditions may affect device reliability. (2) Ail voltages are reteranced to VSS (VSS = ground) unless otherwise specified. (3) Maxirnum power dissipation with 20 chips utilized at 50 percent (each bank is maximally utilized, alternating between blocks). (4) Assumes a uniform temperature on the bottom surface of the package, and a uniform power distribution over the top surtace of the die and all die at equal power level. RECOMMENDED OPERATING CONDITIONS Description Symbol Parameter - Units Min Typ Max VDD | Supply Voltage (referenced to VSS) 4.5 5.0 5.5 Vv TC Case OperatingTemperature -55 25 125 C CAPACITANCE (1) Worst Case Symbol Parameter Min | Max Units Test Conditions CIN1 Input Capacitance for CE and NCS Inputs 50 pF VIN=VDD or VSS, f=1 MHz CIN2 Input Capacitance for Address 100 pF VIN=VDD or VSS, f=1 MHz NOE and NWE Inputs COUT Output Capacitance 26 pF VIN=VDD or VSS, f=1 MHz (1) This parameter is tested during initial design characterization only. (2) Worst case operating conditions: TA= -55C to +125C, past total dose at 25C.HX84050 READ CYCLE AC TIMING CHARACTERISTICS (1) Worst Case (3) Symbol! Parameter Typical -55 to 125C Units (1) (2) Min = Max TAVAVR]| Address Read Cycle Time 30 ns TAVQV | Address Access Time 30 ns TAVQX | Address Change to Output Invalid Time 3 ns TSLQV Chip Select Access Time 30 ns TSLOX Chip Select Output Enable Time 5 ns TSHQZ | Chip Select Output Disable Time 16 ns TEHQV | Chip Enable Access Time 30 ns TEHQX | Chip Enable Output Enable Time 5 ns TELQZ Chip Enabie Output Disable Time 16 ns TGLOV Output Enable Access Time 14 ns TGLQX | Output Enable Output Enable Time 0 ns TGHQZ | Output Enable Output Disable Time 16 ns (1) Test conditions: input switching leveis VILVIH=0.5V/VDD-0.5V (CMOS), VIL/VIH=0V/3V (TTL), input rise and fall times <1 ns/V, input and output timing reference lavels shown in the Tester AC Timing Characteristics table, capacitive output loading C, >50 pF, or equivalent capacitive output loading C,=5 pF for TSHQZ, TELQZ TGHQZ. For C, >50 pF, derate access times by 0.02 ns/pF (typical). (2) Typical operating conditions: VOD=5.0 V, TA=25C, pre-radiation. (3) Worst case operating conditions: VDD=4.5 V to 5.5 V, post total dose at 25C. TAVAVR ADDRESS X | Tavav Taxax Tstav NCS Tstax TsHaz HIGH TEHOX TEHOQV ce tam TGLav TMM TELaz ToHaz Titi (NWE = high)HX84050 WRITE CYCLE AC TIMING CHARACTERISTICS (1) Worst Case (3) Symbol Parameter Typical -55 to 125C Units (1) (2) Min Max TAVAVW| Write Cycle Time 30 ns TWLWH | Write Enable Write Pulse Width 20 ns TSLWH | Chip Select to End of Write Time 25 ns TDVWH | Data Valid to End of Write Time 20 ns TAVWH | Address Valid to End of Write Time 25 ns TWHDX | Data Hold Time after End of Write Time 3 ns TAVWL | Address Valid Setup to Start of Write Time 5 ns TWHAX | Address Valid Hold after End of Write Time 0 ns TWLQZ | Write Enable to Output Disable Time 16 ns TWHOX | Write Disable to Output Enabie Time 5 ns TWHWL | Write Disable to Write Enable Pulse Width 5 ns TEHWH | Chip Enable to End of Write Time 25 ns (1) Test conditions: input switching levels VIL/VIH=0.5V/VDD-0.5V (CMOS), VIL/VIH=0V/3V (TTL), input rise and fall times <1 ns/V, input and output timing reference levels shown in the Taster AC Timing Characteristics table, capacitive output loading >50 pF, or equivalent capacitive load of 5 pF for TWLQZ. (2) Typical operating conditions: VOD=5.0 V, TA=25C, pre-radiation. (3) Worst case operating conditions: VDD=4.5 V to 5.5 V, -55 to 125C, post total dose at 25C. TAVAVW j- | sooness Y TAVWH TWHAX TAVWL TWHWL TWLWH NWE / Twraz TWHaXx DATA OUT HIGH IMPEDANCE 1 TOVWH TWwHox | | DATA IN DATA VALID TSLWH TEHWH CE ELLY \HX84050 DC ELECTRICAL CHARACTERISTICS Symbol | Parameter _ Mt Care @) | units | Test Conditions VDD=CE=5 SV, NCS=NOE=NWE=OV, ICC1 | Operating Supply Current S25 | MA | 620MHz VDD=NCS=NOE=CE-NWE=5 5V, Icc2 | Supply Current (Deselected 30 | ma | OMe ICC3 _| Supply current (Standby) 30. | mA | VDD=NCS=CE=55V, f=0.0MHz 1CC4 | Supply Current (Disabled) 30. | mA | VDD=55V, NCS=CE=0V, 1=20 MHz IcC5 | Supply current (Disabled, Idle) 30. | mA | VDD=55V, NCS=CE=0V, f=0.0 MHz ICC6 | Data Retention Current 10. | mA | VDD=NCS-NOE=CE=NWE=2.5V VDD=NOE=CE=NWE=5.5V, lit Input Current, Low -100 +100 HA NCS=VIL<0V . VDD=CE=VIH=S5V, tH Inout Current, High -100 +100 HA NCS=NOE=NWE=OV VDD=NOE=CE=NWE=5.5V loZL _| Output Leakage Current, Low 200 | +200 | wa | iCo-vorcov IOZH | Output Leakage Current, High 200 | +200 | pA NODNWE OY vi [bow Level input Votage Range CMOS: 03 [S800 y | Voosasv vin. | Mish Level Input Votlage Range CMOS O7 PP | vpD+03) Vv | vDD=5.5v VDD=CE=NWE=4.5V, NCS=NOE=0 VOL | Output Low Volatage 0.4 VO VDD=CE=NWE=4.5V, NCS=NNOE=0 VOH | Output High Voltage 42 v |\oowe (1) Typical operating conditions: VDD= 5.0 V,TA=25C, pre-radiation. (2) Worst case operating conditions: VDD=4.5 V to 5.5 V, TA=-55C to +125C, post total dose at 25C. DUT output Tester Equivalent Load Circuit 2.9V 249 C,_ 250 pF* Vref1 of > Vret2 9 Valid high output Valid low output "C, = 5 pF for TWLQZ, TSHQZ, TELQZ, and TGHQZHX84050 DYNAMIC ELECTRICAL CHARACTERISTICS Read Cycle The RAM is asynchronous in operation, allowing the read cycle to be controlled by address, chip select (NCS), or chip enable (CE) (refer to Read Cycle timing diagram). To perform a valid read operation, both chip select and output enable (NOE) must be low and chip enable and write enable (NWE) must be high. The output drivers can be controlled independently by the NOE signal. Consecutive read cycles can be executed with NCS held continuously low, and with CE held continuously high, and toggling the addresses. For an address activated read cycle, NCS and CE must be valid prior to or coincident with the activating address edge transition(s). Any amount of toggling or skew between ad- dress edge transitions is permissible; however, data outputs will become valid TAVQV time following the latest occurring address edge transition. The minimum address activated read cycle time is TAVAV. When the RAM is operated at the minimum address activated read cycle time, the data out- puts will remain valid on the RAM I/O until TAXQX time following the next sequential address transition. To control a read cycle with NCS, all addresses and CE must be valid prior to or coincident with the enabling NCS edge transition. Address or CE edge transitions can occur later than the specified setup times to NCS, however, the valid data access time will be delayed. Any address edge transition, which occurs during the time when NCS is low, will initiate a new read access, and data outputs will not become valid until TAVQV time following the address edge transition. Data outputs will enter a high impedance state TSHQ2Z time following a disabling NCS edge transition. To control a read cycle with CE, ail addresses and NCS must be valid prior to or coincident with the enabling CE edge transition. Address or NCS edge transitions can occur later than the specified setup times to CE; however, the valid data access time will be delayed. Any address edge transition which occurs during the time when CE is high will initiate a new read access, and data outputs will not become valid until TAVQV time following the address edge transition. Data outputs will enter a high impedance state TELQZ time following a disabling CE edge transition. Write Cycle The write operation is synchronous with respect to the address bits, and control is governed by write enable (NWE), chip select (NCS), or chip enable (CE) edge transitions (refer to Write Cycle timing diagrams). To per- form a write operation, both NWE and NCS must be low, and CE must be high. Consecutive write cycles can be performed with NWE or NCS held continuously low, or CE held continuously high. At least one of the control signals must transition to the opposite state between consecutive write operations. The write mode can be controlied via three different control signals: NWE, NCS, and CE. All three modes of control are similar except the NCS and CE controlled modes actually disable the RAM during the write recovery pulse. NCS differs from CE in that it does not disable the input buffers; however, both CE and NCS fully disable the RAM decode logic for power savings. Only the NWE controlled mode is shown in the table and diagram on the previous page for simplicity; however, each mode of control provides the same write cycle timing characteristics. Thus, some of the parameter names referenced below are not shown in the write cycle table or diagram, but indicate which control pin is in control as it switches high or low. To write data into the RAM, NWE and NCS must be held low and CE must be held high for at least TWLWH/TSLSH/ TEHEL time. Any amount of edge skew between the signals can be tolerated, and any one of the control signals can initiate or terminate the write operation. For consecu- tive write operations, write pulses must be separated by the minimum specified WHWL/TSHSL/TELEH time. Address inputs must be valid at least TAVWL/TAVSL/TAVEH time before the enabling NWE/NCS/CE edge transition, and must remain valid during the entire write time. A valid data overlap of write pulse width time of TDVWH/TDVSH/TDVEL, and an address valid to end of write time of TAVWH/ TAVSH/TAVEL also must be provided for during the write operation. Hold times for address inputs and data inputs with respect to the disabling NWE/NCS/CE edge transition must be a minimum of TWHAX/TSHAX/TELAX time and TWHDX/TSHDX/TELDX time, respectively. The minimum write cycle time is TAVAV.HX84050 TESTER AC TIMING CHARACTERISTICS sign 2 34V-.- 9 240. High Z = 2.9V TTL VO Configuration CMOS I/O Configuration av VDD-0.5 V Input eee ee eee - VDD/2 Levels* OV ....:3 O5V .... Output VOD-04V \: + VOD-0.4V ,. Sense Da ne DP Levels B4AV---, High Z 24Vv.--3 High Z = 2.9V * input rise and fall times <1 ns/V QUALITY AND RADIATION HARDNESS ASSURANCE Honeywell maintains a high level of product integrity through process control, utilizing statistical process control, a com- plete Total Quality Assurance System, a computer data base process performance tracking system, and a radia- tion hardness assurance strategy. The radiation hardness assurance strategy starts with a technology that is resistant to the effects of radiation. Radiation hardness is assured on every wafer by irradiating test structures as well as SRAM product, and then monitor- ing key parameters which are sensitive to ionizing radia- tion. Conventional MIL-STD-883 TM 5005 Group E testing, which includes total dose exposure with Cobalt 60, may also be performed as required. This Total Quality approach ensures our Customers of a reliable product by engineering in reliability, starting with process development and con- tinuing through product qualification and screening. SCREENING LEVELS Honeywell offers several levels of device screening to meet your system needs. Engineering Devices are available with varying degrees of limited performance and screening for breadboarding and/or evaluation testing. Hi-Rel Level B and S devices undergo additional screening per the require- ments of MIL-STD-883. As a QML supplier, Honeywell also offers QML Class Q and V devices per MIL-PRF-38535 and are available per the applicable Standard Military Drawing (SMD). QML devices offer ease of procurement by eliminat- ing the need to create detailed specifications and offer benefits of improved quality and cost savings through stan- dardization. RELIABILITY Honeywell understands the stringent reliability requirements that space and defense systems require and has extensive experience in reliability testing on programs of this nature. This experience is derived from comprehensive testing of VLSI processes. Reliability attributes of the RICMOS pro- cess were characterized by testing specially designed irradi- ated and non-irradiated test structures from which specific failure mechanisms were evaluated. These specific mecha- nisms included, but were not limited to, hot carriers, elec- tromigration and time dependent dielectric breakdown. This data was then used to make changes to the design models and process to ensure more reliable products. In addition, the reliability of the RICMOS process and product in.a military environment was monitored by testing irradiated and non-irradiated circuits in accelerated dy- namic life test conditions. Packages are qualified for prod- uct use after undergoing Groups B & D testing as outlined inMIL-STD-883, TM 5005, Class S. The product is qualified by following a screening and testing flow to meet the customer's requirements. Quality conformance testing is performed as an option on all production lots to ensure the ongoing reliability of the product. 10HX84050 PACKAGING The memory MCM is offered in a custom 200-lead ceramic bounce. These capacitors effectively attach to the internal quad flat pack. The package is constructed of multilayer package power and ground planes. This design minimizes ceramic (Al,O,) and features internal power and ground resistance and inductance of the bond wire and package, planes. both of which are critical in a transient radiation environment. Ceramic chip capacitors (20) are mounted inside the pack- age to maximize supply noise decoupling and avoid ground 200-LEAD QUAD FLAT PACK PIN LIST Pin] Signal Name | Pin Type | Pin] Signal Name | Pin Type Pin | Signat Name | Pin Type | Pin | Signal Name | Pin Type | Pin| Signal Name Pin Type 1 VSS PwiGnd | 41 | 8 DATA(O8) | Tri-State | 81 | B_LDATA(22) | Tri-State | 121 B_DATA(38) | Tr-State | 161] A_DATA(27) | Tri-State 2 | A_ADRS(04) input 42 | B_DATA(09) | Tri-State | 82 vss PwriGnd [122 B_DATA(39) Tri-State | 162 vob Pwr/Gnd 3 | A_ADRS(03} Input 43 | B_ADRS(00) Input 83 VOD Pwr/Gnd | 123 B_NCSO Input | 163 vss Pwr/Gnd 4 | A_ADRS(02) Input 44 vss Pwr/Gnd | 64 | B_DATA(23) | Tri-State [124 VDD Pwr/Gnd | 164] A_DATA(26) | Tri-State 5 | A_ADRS(01) Input 45 VoD Pwr/Gnd | 85 | B_DATA(24) | Tri-State ]125 vss PwriGnd | 165] A_DATA(25) | Tri-State 6 VoD Pwr/Gnd | 46] B_ADRS(01) input 86 | B_DATA(25) | Tri-State ]126 vss Pwri/Gnd | 166] A_DATA(24) | Tri-State 7 vss Pwr/Gnd | 47 | B_AORS(02) Input 87 | B_DATA(26) | Tri-State [127 VDD Pwr/Gnd [167] A_DATA(23) | Tri-State 8 | A_ADRS(00) Input 48 | B_ADAS(03) input 88 vss Pwr/Gnd [128 B_NCSO Input 9 168 vod Pwr/Gnd 9 | A_DATA(O9) | Tri-State | 49 |] B_ADRS(04) Input ag VDD Pwi/Gnd |129 | A_DATA(39) | Tri-State | 169 vss Pwr/Gnd 10 | A_DATA(08) | Tri-State | 50 vss Pwi/Gnd | 90 | B_DATA(27) | Tri-State ]130 | A_DATA(38) | Tri-State | 170] A_DATA(22) | Tri-State 11 | A_DATA(O7) | Tri-State | 51 VSS PwiGnd | 91 | B_DATA(28) | Tri-State [131 | A_DATA(37) | Tri-State | 171] A_DATA(21) Tri-State 12 VDD Pwi/Gnd | 52 VDD Pwr/Gnd | 92 | B_LOATA(29) | Tri-State | 132 VSs Pwr/Gnd [172] A_DATA(20) | Tri-State 1g vss Pwr/Gnd | 53] B_ADRS(05) Input 93 | B_ADAS(09) tnput 133 voD PwiGnd | 173 A_NOE Input 14] A_DATA(O6) ] Tri-State | 54] B_ADRS(06) input 94 vss Pwr/Gnd [134] A_DATA(36) | Tri-State | 174 VDD Pwr/Gnd 15 | A_DATA(O5) | Tri-State | 55] 8 ADAS(07) Input 95 VDD Pwr/Gnd 1135] A_DATA(35) | Tri-State [175 vss Pwr/Gnd 16] A_DATA(04) | Tri-State | 56 VDD PwiGnd | 96 | B_ADRS(10) input $136 | A_DATA(34) | Tri-State | 176 vss Pwr/Gnd 17] A_DATA(03) | Tri-State | 57 vss Pwr/Gnd | 97 | B_ADRS(11) Input 1137] A_DATA(33) | Tri-State | 177 VDD Pwr/Gnd 18 vod Pwr/Gnd | 58} B_ADRS(08) Input 98 | B_ADRS(12) Input 1138 vss Pwr/Gnd | 178 A_NWE input 19 vss Pwr/Gnd | 59] B_DATA(10) | Tri-State | 99 VOD Pwr/Gnd [139 VOD PwriGnd [179] A_DATA(19) | Tri-State 201 A_DATA(02) | Tri-State | 60 | B_DATA(11) | Tri-State |] 100 vss PwriGnd [140 |] A_DATA(32) | Tri-State ] 180] A_DATA(18) | Tri-State 21] A_DATA(O1) | Tri-State | 61 B_DATA(12) Tri-State [101 vss Pwr/Gnd [141 | A_DATA(31) | Tri-State 1181] A_DATA(17) | Tri-State 22] A_DATA(OO) | Tri-State | 62 VDD Pwi/Gnd | 102 VDD PwriGnd [142 7 A_DATA(30) | Tri-State | 182 vss Pwr/Gnd 23] A_NCS1 Input | 63 vss PwriGnd | 103 B_CEO Input [143] A_ADRS(14) Input | 183 VOD Pwr/Gnd 24 VO0 Pwi/Gnd | 64] B_DATA(13) ] Tri-State [104 B_CE1 Input 144 vss Pwr/Gnd | 184] A_DATA(16) | Tri-State 25 VSS Pwr/Gnd | 65 | B_DATA(14) | Tri-State [105 | B_AORS(13) Input 145 vod Pwi/Gnd 1185] A_DATA(15) | Tri-State 26 vss Pwr/Gnd | 66 | B_DATA(15) | Tri-State | 106 VOD Pwr/Gnd [146 [| A_ADAS(13) Input | 186 A_DATA(14) | Tri-State 27 VDD Pwr/Gnd | 67] B_DATA(16) | Tri-State | 107 vss PwriGnd [147 A_CE1 input 1187] A_DATA(13) | Tri-State 28 B_NCS1 Input 68 VDD Pwr/Gnd [108 | B_ADAS(14} Input 4148 A_CEO Input 7188 vss Pwr/Gnd 29] B_DATA(0Q) | Tri-State | 69 vss Pwr/Gnd [109] B_DATA(30) | Tri-State [149 VDD Pwr/Gnd | 189 VDD Pwr/Gnd 30 | B_DATA(O1) | Tri-State | 70 | B_DATA(17) | Tri-State [110 | B_LOATA(31) | Tri-State [150 vss PwiGnd [190] A_DATA(12) | Tri-State 31 | B_DATA(02) | Tri-State | 71 B_DATA(18) Tri-State [111] B_DATA(32) | Tri-State 1151 vss Pwi/Gnd 1191] A_DATA(11) | Tri-State 32 vss Pwr/Gnd [ 72] B_DATA(19) | Tri-State [112 VDD PwriGnd 1152 vob Pwr/Gnd | 192] A_DATA(10) | Tri-State 33 VDO Pwi/Gnd | 73 B_NWE input 113 vss PwriGnd [153] A_ADRS(12) input 193] A_ADRS(08) Input 34 | B_OATA(03) | Tri-State | 74 VDD PwriGnd [114] 8_DATA(33) | Tri-State [154] A_ADRS(11) Input 194 vss Pwr/Gnd 35 | B_DATA(04) | Tri-State | 75 vss Pwi/Gnd [115] B_DATA(34) | Tri-State 1155 | A_ADRS(10) Input 195 voo Pwr/Gnd 36 | B_DATA(OS) | Tri-State | 76 vss Pwr/Gnd [116] B_OATA(35) | Tri-State [156 VDD Pwri/Gnd | 196] A_ADRS(07) Input 37 | B_DATA(06) | Tri-State | 77 VOD PwiiGnd [117] B_OATA(36) | Tri-State | 157 vss Pwr/Gnd } 197] A_ADRS(06) input 38 VSS PwiGnd | 78 B_NOE Input 118 voD Pwr/Gnd | 158 | A_ADRS(09) Input | 1987 A_AORS(05) input 39 VDD Pwr/Gnd | 79} B_DATA(2G) | Tri-State [119 vss Pwi/Gnd | 159 A_DATA(29) Tri-State | 199 VoD Pwr/Gnd 40] B_DATA(O7) ] Tri-State | 86] B_DATA(21) | Tri-State [120 | B_DATA(37) | Tri-State | 160 | A_DATA(28) | Tri-State | 200 vss Pwr/Gnd 11HX84050 200-LEAD QUAD FLAT PACK Dimensions in inches 0.183 1] 0.149.015 0.0352.005 0.010 +.002 - 0.001 0.006 +.002 -0.001 0.008 REF 2.1002.021 2.1002.021 0.035 3.500+.035 *nNOFMOCT OTH Py 0.2002.005 CERAMIC BODY CERAMIC TIE BAR ORDERING INFORMATION (1) H X 84050 S H Cc | PARTNUMBER SCREEN LEVEL INPUT BUFFER TYPE xX=SOl Q=QML Class Q HARDNESS T=TTL Level SOURCE S=Level S R=2x108 rad(SiO,) H=HONEYWELL B=Level B ; E=Engr Device (2) F=3x105 rad(SiO,) H=1x10* rad(SiO,) N=No Level Guaranteed (1) Orders may be faxed to 612-954-2051. For technical assistance, contact our Customer Logistics Department at 612-954-2888. (2) Engineering Device description: Parameters are tested trom -55 to 125C, 24 hr bum-in, no radiation guaranteed. Contact Factory with other needs. To learn more about Honeywell Solid State Electronics Center, visit our web site at http//www.ssec.honeywell.com Honeywell reserves the right to make changes to any products or technology herein to improve reliability, function or design. Honeywell does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under Its patent rights nor the rights of others. 900172 4/96 Honeywell Helping You Control Your World