MCP3425A1TE/CH - Microchip Technology, Inc.

MCP3425

Features

• 16-bit ΔΣ ADC in a SOT-23-6 package

• Differential input operation

• Self calibration of Internal Offset and Gain per

each conversion

• On-board Voltage Reference:

- Accuracy: 2.048V ± 0.05%

• On-board Programmable Gain Amplifier (PGA):

- Gains of 1,2, 4 or 8

• On-board Oscillator

• INL: 10 ppm of FSR (FSR = 4.096V/PGA)

• Programmable Data Rate Options:

- 15 SPS (16 bits)

- 60 SPS (14 bits)

- 240 SPS (12 bits)

• One-Shot or Continuous Conversion Op tions

• Low current consumption:

- 145 µA typical

(VDD= 3V, Continuous Conversion)

• One-Shot Conversion (1 SPS) with VDD = 3V:

- 9.7 µA typical with 16 bit mode

- 2.4 µA typical with 14 bit mode

- 0.6 µA typical with 12 bit mode

• Supports I2C Serial Interface:

- Standard, Fast and High Speed Modes

• Single Supply Operation: 2.7V to 5.5V

• Extended Temperature Range: -40°C to 125°C

Typical Applications

• Portable Instrumentation

• Weigh Scales and Fuel Gauges

• Temperature Sensing with RTD, Thermistor, and

Thermocouple

• Bridge Sensing for Pressure, Strain, and Force.

Package Types

Description

The MCP3425 is a single channel low-noise, high

accuracy ΔΣ A/D converter with differential inputs and

up to 16 bits of resolution in a small SOT -23-6 package.

The on-board precision 2.048V reference voltage

enables an input range of ±2.048V differentially

(Δvoltage = 4.096V). The device uses a two-wire I2C

compatible serial interface and operates from a single

2.7V to 5.5V power supply.

The MCP3425 device performs conver sion at rates of

15, 60, or 240 samples per second (SPS) depending

on the user controllable configuration bit settings using

the two-wire I2C serial interface. This device has an on-

board programmable gain amplifier (PGA). The user

can select the PGA gain of x1, x2, x4, or x8 before the

analog-to-digital conversion takes place. This allows

the MCP3425 device to convert a smaller input signal

with high resolution. The device has two conversion

modes: (a) Continuous mode and (b) One-Sh ot mode.

In One-Shot mode, the device enters a low current

standby mode automatically after one conversion. This

reduces current consumption greatly during idle peri-

ods.

The MCP3425 device can be used for various high

accuracy analog-to-digital data conversion applications

where design simplicity, low power, and small footprint

are major considerations.

Block Diagram

VIN+

VSS

SCL

VIN-

VDD

SDA

Top View

SOT-23-6

VSS VDD

VIN+

VIN-

SCL SDA

Voltage Reference

Clock

(2.048V)

I2C Interface

Gain = 1, 2, 4, or 8 VREF

ΔΣ ADC

Converter

PGA Oscillator

16-Bit Analog-to-Digital Converter

with I2C Interface and On-Board Reference

MCP3425

1.0 ELECTRICAL

CHARACTERISTICS

1.1 Absolute Maximum Ratings†

VDD...................................................................................7.0V

All inputs and outputs w.r.t VSS ............... –0.3V to VDD+0.3V

Differential Input Voltage ......................................|VDD - VSS|

Output Short Circuit Current .................................Continuous

Current at Input Pins ................ ....................................±2 mA

Current at Output and Supply Pins ............................±10 mA

Storage Temperature.....................................-65°C to +150°C

Ambient Temp. with power applied ...............-55°C to +125°C

ESD protection on all pins ................ ≥ 6kV HBM, ≥ 400V MM

Maximum Junction Temperature (TJ)..........................+150°C

†Notice: Stresses above those listed under “Maximum Rat-

ings” may cause permanent damage to the device. This is a

stress rating only and functional operation of the device at

those or any other conditions above those indicated in the

operational listings of this specification is not implied.

Exposure to maximum rating conditions for extended per iods

may affect device reliability.

ELECTRICAL CHARACTERISTICS

Electrical Specifications: Unless otherwise specified, all parameters apply for TA = -40°C to +85°C, VDD = +5.0V, VSS = 0V,

VIN+ = VIN- = VREF/2. All ppm units use 2*VREF as full-scale range.

Parameters Sym Min Typ Max Units Conditions

Analog Inputs

Differential Input Range — ±2.048/PGA — V VIN = VIN+ - VIN-

Common-Mode Voltage Range

(absolute) (Note 1) VSS-0.3 — VDD+0.3 V

Differential Input Impedance

(Note 2) ZIND (f) — 2.25/PGA — MΩDuring normal mode operation

Common Mode input

Impedance ZINC (f) — 25 — MΩPGA = 1, 2, 4, 8

System Performance

Resolution and No Missing

Codes (Note 8) 12 — — Bits DR = 240 SPS

14 — — Bits DR = 60 SPS

16 — — Bits DR = 15 SPS

Data Rate (Note 3) DR 176 240 328 SPS S1,S0 = ‘00’, (12 bits mode)

44 60 82 SPS S1,S0 = ‘01’, (14 bits mode)

11 15 20.5 SPS S1,S0 = ‘10’, (16 bits mode)

Output Noise — 2.5 — µVRMS TA = 25°C, DR = 15 SPS,

PGA = 1, VIN = 0

Integral Nonlinearity (Note 4) INL — 10 — ppm of

FSR DR = 15 SPS

(Note 6)

Internal Reference Voltage VREF — 2.048 — V

Gain Error (Note 5) — 0.1 — % PGA = 1, DR = 15 SPS

PGA Gain Error Match (Note 5) — 0.1 — % Between any 2 PGA gains

Gain Error Drift (Note 5)— 15 — ppm/°C PGA=1, DR = 15 SPS

Note 1: Any input voltage below or greater than this voltage causes leakage current through the ESD diodes at the input pins.

This parameter is ensured by characterization and not 100% tested.

2: This input impedance is due to 3.2 pF internal input sampling capacitor.

3: The total conversion speed includes auto-calibration of offset and gain.

4: INL is the difference between the endpoints line and the measured code at the center of the quantization band.

5: Includes all errors from on-board PGA and VREF.

6: Full Scale Range (FSR) = 2 x 2.048/PGA = 4.096/PGA.

7: This parameter is ensured by characterization and not 100% tested.

8: This parameter is ensured by design and not 100% tested.

MCP3425

Offset Error VOS — 30 — µV Tested at PGA = 1

VDD = 5.0V and DR = 15 SPS

Offset Drift vs. Temperature — 300 — nV/°C VDD = 5.0V

Common-Mode Rejection — 100 — dB at DC and PGA =1,

— 105 — dB at DC and PGA =8,

TA = +25°C

Gain vs. VDD — 5 — ppm/V TA = +25°C, VDD = 2.7V to 5.5V,

PGA = 1

Power Supply Rejection at DC — 95 — dB TA = +25°C, VDD = 2.7V to 5.5V,

PGA = 1

Power Requirements

Voltage Range VDD 2.7 — 5.5 V

Supply Current during

Conversion IDDA — 155 190 µA VDD = 5.0V

— 145 — µA VDD = 3.0V

Supply Current during Standby

Mode IDDS —0.1 0.5µA

I2C Digital Inputs and Digital Outputs

High level input voltage VIH 0.7 VDD —V

DD V

Low level input voltage VIL — — 0.3VDD V

Low level output voltage VOL —— 0.4VI

OL = 3 mA, VDD = +5.0V

Hysteresis of Schmitt Trigger

for inputs (Note 7) VHYST 0.05VDD ——Vf

SCL = 100 kHz

Supply Current when I2C bus

line is active IDDB —— 10µA

Input Leakage Current IILH —— 1 µAV

IH = 5.5V

IILL -1 — — µA VIL = GND

Pin Capacitance and I2C Bus Capacitance

Pin capacitance CPIN — — 10 pF

I2C Bus Capacitance Cb— — 400 pF

Thermal Characteristics

Specified Temperature Range TA-40 — +85 °C

Operating Temperature Range TA-40 — +125 °C

Storage Temperature Range TA-65 — +150 °C

ELECTRICAL CHARACTERISTICS (CONTINUED)

Electrical Specifications: Unless otherwise specified, all parameters apply for TA = -40°C to +85°C, VDD = +5.0V, VSS = 0V,

VIN+ = VIN- = VREF/2. All ppm units use 2*VREF as full-scale range.

Parameters Sym Min Typ Max Units Conditions

Note 1: Any input voltage below or greater than this voltage causes leakage current through the ESD diodes at the input pins.

This parameter is ensured by characterization and not 100% tested.

2: This input impedance is due to 3.2 pF internal input sampling capacitor.

3: The total conversion speed includes auto-calibration of offset and gain.

4: INL is the difference between the endpoints line and the measured code at the center of the quantization band.

5: Includes all errors from on-board PGA and VREF.

6: Full Scale Range (FSR) = 2 x 2.048/PGA = 4.096/PGA.

7: This parameter is ensured by characterization and not 100% tested.

8: This parameter is ensured by design and not 100% tested.

MCP3425

2.0 TYPICAL PERFORMANCE CURVES

Note: Unless otherwise indicated, TA = -40°C to +85°C, VDD = +5.0V, VSS = 0V, VIN+ = VIN- = VREF/2.

FIGURE 2-1: INL vs. Supply Voltage

(VDD).

FIGURE 2-2: INL vs. Temperature.

FIGURE 2-3: Offset Error vs.

Temperature.

FIGURE 2-4: Noise vs. Input Voltage.

FIGURE 2-5: Total Error vs. Input Voltage.

FIGURE 2-6: Gain Error vs. Temperature.

Note: The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provide d for informational purposes only. T he performance characteristics listed herein

are not tested or guaranteed. In so me graphs or tables, the data presented may be outside the specifie d

operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

0.001

0.002

0.003

0.004

0.005

2.533.544.555.5

VDD (V)

Integral Nonlinearity (% FSR)

PGA = 1

PGA = 4 PGA = 8

PGA = 2

0.001

0.002

0.003

0.004

0.005

-60 -40 -20 0 20 40 60 80 100 120 140

Temperature (oC)

INL (FSR %)

2.7V

-60

-40

-20

-60 -40 -20 0 20 40 60 80 100 120 140

Temperature (°C )

Offset Error (µV)

PGA = 1

PGA = 8

PGA = 4

PGA = 2

-100% -50% 0% 50% 100%

Input Voltage (% of Full Scale)

Noise (µV, rms)

PGA = 1

PGA = 8

PGA = 4

PGA = 2

-3.0

-2.0

-1.0

0.0

1.0

2.0

3.0

-100 -75 -50 -25 0 25 50 75 100

Input Voltage (% of Full-Scale)

Total Error (mV)

PGA = 1

PGA = 2

PGA = 8

PGA = 4

-0.4

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

-60 -40 -20 0 20 40 60 80 100 120 140

Temperature (°C)

Gain Error (% of FSR)

VDD = 5.0V

PGA = 1

PGA = 2

PGA = 8

PGA = 4

MCP3425

Note: Unless otherwise indicated, TA = -40°C to +85°C, VDD = +5.0V, VSS = 0V, VIN+ = VIN- = VREF/2.

FIGURE 2-7: IDDA vs. Temperature.

FIGURE 2-8: IDDS vs. Temperature.

FIGURE 2-9: IDDB vs. Temperature.

FIGURE 2-10: OSC Drift vs. Temperature.

FIGURE 2-11: Frequency Response.

100

120

140

160

180

200

220

-60 -40 -20 0 20 40 60 80 100 120 140

Temperature (oC)

IDDA (µA)

VDD = 5V

VDD = 2.7V

100

200

300

400

500

600

-60 -40 -20 0 20 40 60 80 100 120 140

Temperature (oC)

IDDS (nA)

VDD

= 2.7V

VDD = 5V

-60 -40 -20 0 20 40 60 80 100 120 140

Temperature (oC)

IDDB

(µA)

VDD = 5V

= 4.5V

VDD = 3.3V

VDD = 2.7V

-1

-60 -40 -20 0 20 40 60 80 100 120 140

Temperature (°C)

Oscillator Drift (%)

VDD = 5.0V

VDD = 2.7V

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0.1 1 10 100 1000 10000

Input Signal Frequency (Hz)

Magnitude (dB)

Data Rate = 15 SPS

10k1k

MCP3425

3.0 PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 3-1.

TABLE 3-1: PIN FUNCTION TABLE

3.1 Analog Inputs (VIN+, VIN-)

VIN+ and VIN- are differential signal input pins. The

MCP3425 device accepts a fully differential analog

input signal which is connected on the VIN+ and VIN-

input pins. The differential voltage that is converted is

defined by VIN = (VIN+ - VIN-) where VIN+ is the voltage

applied at the VIN+ pin and V IN- is the voltage applied

at the VIN- pin. The input signal level is amplified by the

programmable gain amplifier (PGA) before the

conversion. The differential input voltage should not

exceed an absolute of (VREF/PGA) for accurate

measurement, where VREF is the internal reference

voltage (2.048V) and PGA is the PGA gain setting. The

converter output code will saturate if the input range

exceeds (VREF/PGA).

The absolute voltage range on each of the differential

input pins is from VSS-0.3V to VDD+0.3V. Any voltage

above or below this range will cause leak age currents

through the Electrostatic Discharge (ESD) diodes at

the input pins. This ESD current can cause unexpected

performance of the device. The common mode of the

analog inputs should be chosen such that both the

differential analog input range and the absolute voltage

range on each pin are within the specified operating

range defined in Section 1.0 “Electrical

Characteristics” and Section 4.0 “Description of

Device Op er a t ion”.

3.2 Supply Voltage (VDD, VSS)

VDD is the power supply pin for the device. This pin

requires an appropriate bypass capacitor of about

0.1 µF (ceramic) to ground. An additional 10 µF

capacitor (tantalum) in parallel is also recommended

to further attenuate high frequency noise present in

some application boards. The supply voltage (VDD)

must be maintained in the 2.7V to 5.5V range for spec-

ified operation.

VSS is the ground pin and the current return path of the

device. The user must connect the VSS pin to a ground

plane through a low impedance connection. If an

analog ground path is availabl e in the appl ication PCB

(printed circuit board), it is highly recommended that

the VSS pin be tied to the analog ground path or

isolated within an analog ground plane of the circuit

board.

3.3 Serial Clock Pin (SCL)

SCL is the serial clock pin of the I2C interface. The

MCP3425 acts only as a slave and the SCL pin

accepts only external serial clocks. The input data

from the Master device is shifted into the SDA pin on

the rising edges of the SCL clock and output from the

MCP3425 occurs at the falling edges of the SCL clock.

The SCL pin is an open-drain N-channel driver.

Therefore, it needs a pul l-up resisto r from the VDD line

to the SCL pin. Refer to Section 5.3 “I2C Serial Com-

munications” for more details of I2C Serial Interface

communication.

3.4 Serial Data Pin (SDA)

SDA is the serial data pin of the I2C interface. The SDA

pin is used for input and output data. In read mode, the

conversion result is read fr om the SDA pin (output). In

write mode, the device configuration bits are written

(input) though the SDA pin. The SDA pin is an open-

drain N-channel driver. Therefore, it needs a pull-up

resistor from the VDD line to the SDA pin. Except for

start and stop conditions, the data on the SDA pin must

be stable during the high period of the clock. T he high

or low state of the SDA pin can only change when the

clock signal on the SCL pin is low . Refer to Section 5.3

“I2C Serial Communications” for more details of I2C

Serial Interface communication.

Pin No Sym Function

IN+ Non-Inverting Analog Input Pin

SS Ground Pin

3SCL

Serial Clock Input Pin of the I2C Interface

4SDA

Bidirectional Serial Data Pin of the I2C Interface

DD Positive Supply Voltage Pin

IN- Inverting Analog Input Pin

MCP3425

4.0 DESCRIPTION OF DEVICE

OPERATION

4.1 General Overview

The MCP3425 is a low-powe r, 16-Bit Delta-Sigma A/D

converter with an I2C serial interface. The device

contains an on-board voltage reference (2.048V),

programmable gain amplifier (PGA), and internal

oscillator. The user can select 12, 14, or 16 bit

conversion by setting the configuration register bits.

The device can be operated in Continuous Conversion

or One-Shot Conversion mode. In the Continuous

Conversion mode, the device converts the inputs

continuously. While in the One-Shot Conversion mode,

the device converts the input one time and stays in the

low-power standby mode until it receives another

command for a new conversion. During the standby

mode, the device consumes less than 0.1 µA typical.

4.2 Power-On-Reset (POR)

The device contains an internal Power-On-Reset

(POR) circuit that monitors power supply voltage (VDD)

during operation. This circuit ensures correct device

start-up at system power-up and power-down events.

The POR has built-in hysteresis and a timer to give a

high degree of immunity to potential ripples and noises

on the power supply. A 0.1 µF decoupling capacitor

should be mounted as close as possible to the VDD pin

for additional transient immunity.

The threshold voltage is set at 2.2V with a tolerance of

approximately ±5%. If the supply voltage falls below

this threshold, the device will be held in a reset

condition. The typical hysteresis value is approximately

200 mV.

The POR circuit is shut-down during the low-power

standby mode. Once a power-up event has occurred,

the device requires additional delay time (approxi-

mately 300 µs) before a conversion can take place.

During this time, all internal analog circuitries are

settled before the first conversion occurs. Figure 4-1

illustrates the conditions for power-up and power-down

events under typical start-up conditions.

When the device powers up, it automatically resets

and sets the configuration bits to default settings. The

default configuration bit conditions are a PGA gain of

1 V/V and a conversion speed of 240 SPS in

Continuous Conversion mode. When the device

receives an I2C General Call Reset command, it

performs an internal reset similar to a Power-On-Reset

event.

FIGURE 4-1: POR Operation.

4.3 Internal Voltage Reference

The device contains an on-board 2.048V voltage

reference. This reference voltage is for internal use

only and not directly measurable. The specifications of

the reference voltage are part of the device’s gain and

drift specifications. Therefore, there is no separate

specification for the on-board reference.

4.4 Analog Input Channel

The differential analog input channel has a switched

capacitor structure. The internal sampling capacitor

(3.2 pF) is charged and discharged to process a

conversion. The chargi ng and discharging of the input

sampling capacitor creates dynamic input currents at

the VIN+ and VIN- input pins, which is inversely

proportional to the internal sampling capacitor and

internal frequency. The current is also a function of the

differential input voltages. Care must be taken in setting

the common-mode voltage and input voltage ranges so

that the input limits do not exceed the ranges specified

in Section 1.0 “Electrical Characteristics”.

4.5 Digital Output Code

The digital output code produced by the MCP3425 is a

function of PGA gain, input signal, and internal

reference voltage. In a fixed setting, the digital output

code is proportional to the vo ltage difference between

the two analog inputs.

The output data format is a binary two’s complement.

With this code scheme, the MSB can be considered a

sign indicator. When the MSB is a logic ‘0’, i t indicates

a positive value. When the MSB is a logic ‘1’, it

indicates a negative value. The following is an example

of the output code:

(a) for a negative full-scale input voltage: 100...000

(b) for a zero differential input voltage: 000...000

The MSB is always transmitted first throu gh the serial

port. The number of data bits for each conversion is 16,

14, or 12 bits depending on the conversion mode selec-

tion.

VDD

2.2V

2.0V 300 µS

Reset Start-up Normal Operation Reset Time

MCP3425

The output codes will not roll-over if the input voltage

exceeds the maximum input range. In this case, the

code will be locked at 0111...11 for all voltages

greater than +(VREF - 1 LSB) and 1000...00 for

voltages less than -VREF. Table 4-2 shows an example

of output codes of various input levels using 16 bit

conversion mode. Table 4-3 shows an example of

minimum and maximum codes for each data rate

option.

The output code is given by:

EQUATION 4-1:

The LSB of the code is given by:

EQUATION 4-2:

TABLE 4-1: LSB SIZE OF VARIOUS BIT

CONVERSION MODES

TABLE 4-2: EXAMPLE OF OUTPUT CODE

FOR 16 BITS

TABLE 4-3: MINIMUM AND MAXIMUM

CODES

4.6 Self-Calibration

The device performs a self-calibration of offset and

gain for each conversion. This provides reliable

conversion resu lts from conv ersion -to-co nversion over

variations in temperature as well as power supply

fluctuations.

4.7 Input Impedance

The MCP3425 uses a switched-capacitor input stage

using a 3.2 pF sampling capacitor. This capacitor is

switched (charged and discharged) at a rate of the

sampling frequency that is generated by the on-board

clock. The differential mode impedance varies with the

PGA settings. The typical differential input impedance

during a normal mode operatio n is given by:

Since the sampling capacitor is only switching to the

input pins during a conversion process, the above input

impedance is only valid during conversion periods. In a

low power standby mode, the above impedance is not

presented at the input pi ns. Therefore, only a leakage

current due to ESD diode is presented at the input pins.

The conversion accuracy can be affected by the input

signal source impedance when any external circuit is

connected to the input pins. The source impedance

adds to the internal impedance and directly affects the

time required to charge the internal sampling capacitor.

Therefore, a large input source impedance connected

to the input pins can increase the system performance

errors such as offset, gain, and integral nonlinearity

(INL) errors. Ideally, the input source impedance

should be zero. This can be achievable by using an

operational amplifier with a closed-loop output

impedance of tens of ohms.

Bit Resolutions LSB (V)

12 bits 1 mV

14 bits 250 µV

16 bits 62.5 µV

Input Voltage (V) Digital Code

≥VREF 0111111111111111

VREF - 1 LSB 0111111111111111

2LSB 0000000000000010

1LSB 0000000000000001

00000000000000000

-1 LSB 1111111111111111

-2 LSB 1111111111111110

- VREF 1000000000000000

< -VREF 1000000000000000

Output Code Max Code 1+()

VIN+V

IN-–()

2.048V

---------------------------------------

×=

LSB 2 2.048V

--------------------------=

Where:

N = number of bits

Number

of Bits Data Rate Minimum

Code Maximum

Code

12 240 SPS -2048 2047

14 60 SPS -8192 8191

16 15 SPS -32768 32767

Note: Maximum n-bit code = 2n-1 - 1

Minimum n-bit code = -1 x 2n-1

ZIN(f) = 2.25 M

/PGA

MCP3425

4.8 Aliasing and Anti-aliasing Filter

Aliasing occurs when the input signal contains time-

varying signal components with frequency greater than

half the sample rate. In the aliasing conditions, the

device can output unexpected output codes. For

applications that are operating in electrical noise

environments, the time-varying signal noise or high

frequency interference components can be easily

added to the input signals and cause aliasing. Although

the MCP3425 device has an internal first order sinc

filter, its’ filter response may not give enough

attenuation to all al iasing signal components. To avoid

the aliasing, an external anti-aliasing filter, which can

be accomplished with a simple RC low-pass filter, is

typically used at the input pins. The low-pass filter cuts

off the high frequency noise components and provides

a band-limited input signal to the MCP3425 input pins.

MCP3425

5.0 USING THE MCP3425 DEVICE

5.1 Operating Modes

The user operates the device by setting up the device

configuration register and reads the conversion data

using serial I2C interface commands. The MCP3425

operates in two modes: (a) Continuous Conversion

Mode or (b) One-Shot Conversion Mode (single

conversion). The selection is made by setting the O/C

bit in the Configuratio n Register. Refer to Section 5.2

“Configuration Register” for more information.

5.1.1 CONTINUOUS CONVERSION

MODE (O/C BIT = 1)

The MCP3425 device performs a Continuous

Convers ion if th e O/C bit is set t o logic “high”. Once the

conversion is completed, the result is placed at the

output data register. The device immediately begins

another conversion and overwrites the output data

The device also clears the data read y flag (RDY bit = 0)

when the conversion is completed. The device sets the

ready flag bit (RDY bit = 1), if the latest conversion

result has been read by the Maste r.

5.1.2 ONE-SHOT CONVERSION MODE

(O/C BIT = 0)

Once the One-Shot Conversion (single conversion)

Mode is selected, the device performs a conversion,

updates the Output Data register, clears the data ready

flag (RDY = 0), and then enters a low power standby

mode. A new One-Shot Conversion is started again

when the device receives a new write command with

RDY = 1.

This One-Sh ot Conversion Mode is recommended for

low power operating applications. During the low

current standby mode, the device consumes less than

1 µA typical. For example, if the device converts only

one time per second with 16 bit resolution, the total cur-

rent draw is only about o ne fourth of the draws in con-

tinuous mode. In this example, the device consumes

approximately 9.7 µA (= ~145 µA/15 SPS), if the

device performs only one conversion per second

(1 SPS) in 16-bit conversion mode with 3V power

supply.

MCP3425

5.2 Configuration Register

The MCP3425 has an 8-bit wide configura tion register

to select for: PGA gain, conversion rate, and conver-

sion mode. This register allows the user to ch ange th e

operating condition of the device and check the status

of the device operation. The user can rewrite the

configuration byte any time during the device

operation. Register 5-1 shows the configuration

R/W-1 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0

RDY C1 C0 O/C S1 S0 G1 G0

1 * 0 * 0 * 1 * 0 * 0 * 0 * 0 *

bit 7 bit 0

* Default Configuration after Power-On Reset

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 RDY: Ready Bit

This bit is the data ready flag. In read mode, this bit indicates if the output register has been updated

with a new convers ion. In One-Shot Conversion mode, writing this bit to “1” initiates a new conversion.

Reading RDY bit with the read command:

1 = O utput register has not been updated.

0 = O utput register has been updated with the latest conversion data.

Writing RDY bit with the write command:

Continuous Conversion mode: No effect

One-Shot Conversion mode:

1 = I nitiate a new conversion.

0 = No effect.

bit 6-5 C1-C0: Channel Selection Bits

These are the Channel Selection bits, but not used in the MCP3425 device.

bit 4 O/C: Conversion Mode Bit

1 = Continuous Conversion Mode. Once this bit is selected, the device performs data conversions

continuously.

0 = One-Shot Conversion Mode. The device performs a single conversion and enters a low power

standby mode until it receives another write/read command.

bit 3-2 S1-S0: Sample Rate Selection Bit

00 = 240 SPS (12 bits),

01 = 60 SPS (14 bits),

10 = 15 SPS (16 bits)

bit 1-0 G1-G0: PGA Gain Selector Bits

00 = 1 V/V,

01 = 2 V/V,

10 = 4 V/V,

11 = 8 V/V

MCP3425

In read mode, the RDY bit in the configuration byte

indicates the state of the conversion: (a) RDY = 1

indicates that the data bytes that have just been read

were not updated from the previous conversion. (b)

RDY = 0 indicates that the data bytes that have just

been read were updated.

If the configuration byte is read repeatedly by clocking

continuously after the first read, the state of the RDY bit

indicates whether the device is ready with new

conversion data. See Figure 5-2. For example,

RDY =0 means new co nversion dat a is ready for read-

ing. In this case , the user can se nd a stop bit to ex it the

current read operation and send a new read command

to read out updated con version data. See Figures 5-2

and 5-2 for reading conversion data. The user can

rewrite the configuration byte any time for a new

setting. Tables 5-1 and 5-2 show the examples of the

configuration bit operation.

5.3 I2C Serial Communications

The MCP3425 device communicates with Master

(microcontroller) through a serial I2C (Inter-Integrated

Circuit) interface and supports standard (100 kbits/

sec), fast (400 kbits/sec) and high-speed (3.4 Mbits/

sec) modes. The serial I2C is a bidirectional 2-wire data

bus communication protocol using open-drain SCL and

SDA lines.

The MCP3425 can only be addressed as a slave. Once

addressed, it can receive configu ration bits or transmit

the latest conversion results. The serial clock pin (SCL)

is an input only and the serial data pin (SDA) is

bidirectional. An example of a hardware connection

diagram is shown in Figure 6-1.

The Master starts communication by sending a START

bit and terminates the communication by sending a

STOP bit. The first byte after the START bit is always

the address byte of the device, which includes the

device code, the address bits, and the R/W bit. The

device code for the MCP3425 device is 1101. The

address bits (A2, A1, A0) are pre-programmed at the

factory . In general, the address bits are specified by the

customer when they order the device. The three

address bits are programmed to “000” at the factory, if

they are not specified by the customer. Figure 5-1

shows the details of the MCP3425 address byte.

During a low power standby mode, SDA and SCL pins

remain at a floating condition.

More details of the I2C bus characteristic is described

in Section 5.6 “I2C Bus Characteristics”.

5.3.1 DEVICE ADDRESSING

The address byte is the first byte received following the

START condition from the Master device. The

MCP3425 device code is 1101. The device code is

followed by three address bits (A2, A1, A0) which are

programmed at the factory. The three address bits

allow up to eight MCP3425 devices on th e same data

bus lin e. The (R/W) bit determines if the Master device

wants to read the conversion data or write to the

Configuration register. If the (R/W) bit is set (read

mode), the MCP3425 outputs the conversion data in

the following clocks. If the (R/W) bit is cleared (write

mode), the MCP3425 expects a configuration byte in

the following clocks. When the MCP3425 receives the

correct address byte, it outputs an acknowledge bit

after the R/W bit. Figure 5-1 shows the MCP3425

address byte. See Figure 5-2 for the read operation

and Figure 5-3 for the write operation of the device.

TABLE 5-1: CONFIGURATION BITS FOR

WRITING

R/W O/C RDY Operation

0 0 0 No effect if all other bits remain

the same - operation continues

with the previous settings

0 0 1 Initiate One-Shot Conversion

0 1 0 Initiate Continuous Conversion

0 1 1 Initiate Continuous Conversion

TABLE 5-2: CONFIGURATION BITS FOR

READING

R/W O/C RDY Operation

1 0 0 New conversion data in One-

Shot conversion mode has been

just read. The RDY bit remains

low until set by a new write

command.

1 0 1 One-Shot Conversion is in

progress, The conversion data is

not updated yet. The RDY bit

stays high.

1 1 0 New conversion data in Continu-

ous Conversion mode has been

just read. The RDY bit changes

to high after this read.

1 1 1 T he conversion data in Continu-

ous Conversion mode was

already read. The latest conver-

sion data is not ready. The RDY

bit stays high until a new

conversion is completed.

MCP3425

FIGURE 5-1: MCP3425 Address Byte.

5.3.2 READING DATA FROM THE DEVICE

When the Master sends a read command (R/W = 1),

the MCP3425 outputs the conversion data bytes and

configuration byte. Each byte consists of 8 bits with

one acknowledge (ACK) bit. The ACK bit after the

address byte is issued by the MCP3425 and the ACK

bits after each conversion data bytes are issued by the

Master.

When the device receives a read command, it outputs

two data bytes followed by a configuration register. In

16 bit-conversion mode, the MSB of the first d ata byte

is the MSB (D15) of the conve rsion dat a . In 14 -bit con -

version mode, the first two bits in the first data byte can

be ignored (they are the MSB of the conversion da ta),

and the 3rd bit (D13) is the MSB of the conversion data.

In 12-bit conversion mode, the first four bits can be

ignored (they are the MSB of the conversion data), and

the 5th bit (D11) of the byte repre sents the MSB of the

conversion data. Table 5-3 shows an example of the

conversion data output of each conversion mode.

The configuration byte follows the output data byte.

The device outputs the configuration byte as long as

the SCL pulses are received. The device terminates

the current outputs when it receives a Not-Acknowl-

edge (NAK), a repeated start or a stop bit at any time

during the output bit stream. It is not required to read

the configu ration byt e. However, the user may read the

configuration byte to check the RDY bit condition to

confirm whether the just received data bytes are

updated conversion data. The user may continuously

send clock (SCL) to repe atedly read the configuration

bytes to check the RDY bit status.

Figures 5-2 and 5-2 show the timing diagrams of the

reading.

5.3.3 WRITING A CONFIGURATION BYTE

TO THE DEVICE

When the Master sends an address byte with th e R/W

bit low (R/W = 0), the MCP3425 expects one

configuration byte following the address. Any byte sent

after this second byte will be ignored. The user can

change the operating mode of the device by writing the

configurati o n re gi st er bi ts.

If the device receives a write command with a new

configuration setting, the device immed iately begins a

new conversion and updates the conversion data.

Start bit Read/Write bit

Address Byte

R/W ACK

1101XXX

Device Code Address Bits (Note 1)

Address

Acknowledge bit

Address

Note 1: S pecified by customer and programmed at the

factory. If not specified by the customer,

programmed to ‘000’.

TABLE 5-3: EXAMPLE OF CONVERSION DATA OUTPUT OF EACH CONVERSION MODE

Conversion

Mode Conversion Data Output

16-bits MD14~D8 (1st data byte) - D7 ~ D0 (2nd data byte) - Configuration byte

14-bits MMMD12~D8 (1st data byte) - D7 ~ D0 (2nd data byte) - Configuration byte

12-bits MMMMMD10D9D8 (1st data byte) - D7 ~ D0 (2nd data byte) - Configuration byte

Note: M is MSB of the data byte.

MCP3425

FIGURE 5-2: Timing Dia gram For Reading From The MCP3425.

1 1 0 1 A2 A1 A0

ACK by

MCP3425

Start Bit by

Master

2nd Byte

Middle Data Byte

ACK by

Master ACK by

Master

15 D

14 D

13 D

12 D

11 D

10 D

1st Byte

MCP3425 Address Byte 3rd Byte

Lower Data Byte 4th Byte

Configuration Byte

(Optional)

NAK by

Master Stop Bit by

Master

(Optional)

Nth Repeated Byte:

Configuration Byte

Note: – MCP3425 device code is 1101.

– Address Bits A2- A0 = 000 are programmed at the factory unless customer requests specific codes.

– Stop bit or NAK bit can be issued any time during reading.

– In 14 - bit mode: D15 and D14 are repeated MSB and can be ignored .

– In 12 - bit mode: D15 - D12 are repeated MSB and can be ignored.

199

SCL

SDA

RDY O/C

R/W

RDY O/C

MCP3425

FIGURE 5-3: Timing Diigram For Writing To The MCP3425.

5.4 General Call

The MCP3425 acknowledges th e general call address

(0x00 in the first byte). The meaning of the general call

address is always specified in the second byte. Refer

to Figure 5-4. The MCP3425 supports the following

general calls:

5.4.1 GENERAL CALL RESET

The general call reset occurs if the second byte is

‘00000110’ (06h). At the acknowledgement of this

byte, the device will abort current conversion and

perform an internal reset similar to a power-on-reset

(POR).

5.4.2 GENERAL CALL CONVERSION

The general call conversion occurs if the second byte

is ‘00001000’ (08h). All devices on the bus initiate a

conversion simultaneously. For the MCP3425 device,

the configuration will be set to the One-Shot Conver-

sion mode and a sing le conversion will be performed.

The PGA and data rate settings are unchanged with

this general call.

FIGURE 5-4: General Call Address

Format.

For more information on the general call, or other I2C

modes, please refer to the Phillips I2C specification.

191

Stop Bit by

1101A2A1

R/W ACK by

MCP3425 RDY

C1 C0

O/C

S1 S0 G1 G0

1st Byte: 2nd Byte:

Master

ACK by

MCP3425

MCP3425 Address Byte Configuration Byte

Start Bit by

Master

with Write command

Note: – Stop bit can be issued any time during writing.

– MCP3425 device code is 1101.

– Address Bits A2- A0 = 000 are programmed at factory unless customer requests different codes.

SCL

SDA

Note: The I2C specification does not allow to use

“00000000” (00h) in the second byte.

LSB

First Byte

ACK

00000000A Axxxxxxx

(General Call Address) Second Byte

ACK

MCP3425

5.5 High-Speed (HS) Mode

The I2C specification requires that a hig h-speed mode

device must be ‘activated’ to operate in high-speed

mode. This is done by sending a special address byte

of 00001XXX following the START bit. The XXX bits are

unique to the High-S peed (HS) mode Master . This byte

is referred to as the High-Speed (HS) Master Mode

Code (HSMMC). The MCP3425 device does not

acknowledge this byte. However, upon receiving this

code, the MCP3425 switches on its HS mode filters

and communicates up to 3.4 MHz on SDA and SCL.

The device will switch out of the HS mode on the next

STOP condition.

For more information on the HS mode, or other I2C

modes, please refer to the Phillips I2C specification.

5.6 I2C Bus Characteristics

The I2C specification defines the following bus

protocol:

• Data transfer may be initiated only when the bus

is not busy.

• During data transfer, the data line must remain

stable whenever the clock line is HIGH. Changes

in the data line while the clock line is HIGH will be

interpreted as a START or STOP condition.

Accordingly, the following bus conditions have been

defined using Figure 5-5.

5.6.1 BUS NOT BUSY (A)

Both data and clock lines remain HIGH.

5.6.2 START DATA TRANSFER (B)

A HIGH to LOW transition of the SDA line while the

clock (SCL) is HIGH determines a START condition. All

commands must be preceded by a START condition.

5.6.3 STOP DATA TRANSFER (C)

A LOW to HIGH transition of the SDA line while the

clock (SCL) is HIGH determines a STOP condition. All

operations can be ended with a STOP condition.

5.6.4 DATA VALID (D)

The state of the data line represents valid data when,

after a START condition, th e data line is stable for the

duration of the HIGH period of the clock signal.

The data on the line must be changed during the LOW

period of the clock signal. There is one clock pulse per

bit of data.

Each data transfer is initiated with a START condition

and terminated with a STOP condition.

5.6.5 ACKNOWLEDGE

The Master (microcontroller) and the slave (MCP3425)

use an acknowledge pulse as a hand shake of

communication for each b yte. The ninth clock pulse of

each byte is used for the acknowledgement. The

acknowledgement is achieved by pulling-down the

SDA line “LOW” during the 9th clock pulse. The clock

pulse is always provided by the Master (microcontrol-

ler) and the acknowledgement is issued by the

receiving device of the byte (Note: The transmitting

device must release the SDA line (“HIGH”) during the

acknowledge pulse.). For example, the slave

(MCP3425) issues the acknowledgement (bring down

the SDA line “LOW”) after the end of each receiving

byte, and the master (microcontroller) issues the

acknowledgement when it reads data from the Slave

(MCP3425).

When the MCP3425 is addressed, it generates an

acknowledge after receiving each byte successfully.

The Master device (microcontroller) must provide an

extra clock pulse (9th pulse of each byte) for the

acknowledgement from the MCP3425 (slave).

The MCP3425 (slave) p ulls-down the SDA line during

the acknowledge clock pulse in such a way that the

SDA line is stable low during the high period of the

acknowledge clock pulse.

During reads, the Master (microcontroller) can

terminate the current read operation by not providing

an acknowledge bit on the last byte that has been

clocked out from the MCP3425. In this case, the

MCP3425 releases the SDA line to allow the master

(microcontroller) to generate a STOP or repeated

START condition.

FIGURE 5-5: Data Transfer Sequence on the Ser ial Bus.

SCL

SDA

(A) (B) (D) (D) (A)(C)

START

CONDITION ADDRESS OR

ACKNOWLEDGE

VALID

DATA

ALLOWED

TO CHANGE

STOP

CONDITION

MCP3425

TABLE 5-4: I2C SERIAL TIMING SPECIFICATIONS

Electrical Specifications: Unless otherwise specified, all limits are specified for TA = -40 to +85°C, V DD = +2.7V, +3.3V or +5.0V,

VSS = 0V, VIN+ = VIN- = VREF/2.

Parameters Sym Min Typ Max Units Conditions

Standard Mode

Clock frequency fSCL 0 — 100 kHz

Clock high time THIGH 4000 — — ns

Clock low time TLOW 4700 — — ns

SDA and SCL rise time (Note 1) TR— — 1000 ns From VIL to VIH

SDA and SCL fall time (Note 1) TF— — 300 ns From VIH to VIL

START condition hold time THD:STA 4000 — — ns After this period, the first clock

pulse is generated.

Repeated START condition

setup time TSU:STA 4700 — — ns Only relevant for repeated Start

condition

Data hold time (Note 3) THD:DAT 0 — 3450 ns

Data input setup time TSU:DAT 250 — — ns

STOP condition setup time TSU:STO 4000 — — ns

STOP condition hold time THD:STD 4000 — — ns

Output valid from clock

(Notes 2 and 3) TAA 0 — 3750 ns

Bus free time TBUF 4700 — — ns T ime between ST ART and STOP

conditions.

Fast Mode

Clock frequency TSCL 0 — 400 kHz

Clock high time THIGH 600 — — ns

Clock low time TLOW 1300 — — ns

SDA and SCL rise time (Note 1) TR20 + 0.1Cb — 300 ns From VIL to VIH

SDA and SCL fall time (Note 1) TF20 + 0.1Cb — 300 ns From VIH to VIL

START condition hold time THD:STA 600 — — ns After this period, the first clock

pulse is generated

Repeated START condition

setup time TSU:STA 600 — — ns Only relevant for repeated Start

condition

Data hold time (Note 4) THD:DAT 0 — 900 ns

Data input setup time TSU:DAT 100 — — ns

STOP condition setup time TSU:STO 600 — — ns

STOP condition hold time THD:STD 600 — — ns

Output valid from clock

(Notes 2 and 3) TAA 0 — 1200 ns

Bus free time TBUF 1300 — — ns T ime between ST ART and STOP

conditions.

Input filter spike suppression

(Note 5) TSP 0 — 50 ns SDA and SCL pins

Note 1: This parameter is ensured by characterization and not 100% tested.

2: This specification is not a part of the I2C specification. This specification is equivalent to the Data Hold Time (THD:DAT)

plus SDA Fall (or rise) time: TAA = THD:DAT + TF (OR TR).

3: If this parameter is too short, it can create an unintended Start or Stop condition to other devices on the bus line. If this

parameter is too long, Clock Low time (TLOW) can be affected.

4: For Data Input: This parameter must be longer than tSP. If this parameter is too long, the Data Input Setup (TSU:DAT) or

Clock Low time (TLOW) can be affected.

For Data Output: This parameter is characterized, and tested indirectly by testing TAA parameter.

5: This parameter is ensured by characterization and not 100% tested. This parameter is not available for Standard Mode.

MCP3425

High-Speed Mode

Clock frequency fSCL 0—3.4

1.7 MHz

MHz Cb = 100 pF

Cb = 400 pF

Clock high time THIGH 60

120 ——ns

ns Cb = 100 pF

Cb = 400 pF

Clock low time TLOW 160

320 ——nsC

b = 100 pF

Cb = 400 pF

SCL rise time (Note 1) TR——40

80 ns From VIL to VIH,Cb = 100 pF

Cb = 400 pF

SCL fall time (Note 1) TF——40

80 ns From VIH to VIL,Cb = 100 pF

Cb = 400 pF

SDA rise time (Note 1) TR: DAT ——80

160 ns From VIL to VIH,Cb = 100 pF

Cb = 400 pF

SDA fall time (Note 1) TF: DATA ——80

160 ns From VIH to VIL,Cb = 100 pF

Cb = 400 pF

START condition hold time THD:STA 160 — — ns After this period, the first clock

pulse is generated

Repeated START condition

setup time TSU:STA 160 — — ns Only relevant for repeated Start

condition

Data hold time (Note 4) THD:DAT 0

0—70

150 ns Cb = 100 pF

Cb = 400 pF

Data input setup time TSU:DAT 10 — — ns

STOP condition setup time TSU:STO 160 — — ns

STOP condition hold time THD:STD 160 — — ns

Output valid from clock

(Notes 2 and 3) TAA — — 150

310 ns Cb = 100 pF

Cb = 400 pF

Bus free time TBUF 160 — — ns Time between ST ART and ST OP

conditions.

Input filter spike suppression

(Note 5) TSP 0 — 10 ns SDA and SCL pins

TABLE 5-4: I2C SERIAL TIMING SPECIFICATIONS (CONTINUED)

Electrical Specifications: Unless otherwise specified, all limits are specified for TA = -40 to +85°C, V DD = +2.7V, +3.3V or +5.0V,

VSS = 0V, VIN+ = VIN- = VREF/2.

Parameters Sym Min Typ Max Units Conditions

Note 1: This parameter is ensured by characterization and not 100% tested.

2: This specification is not a part of the I2C specification. This specification is equivalent to the Data Hold Time (THD:DAT)

plus SDA Fall (or rise) time: TAA = THD:DAT + TF (OR TR).

3: If this parameter is too short, it can create an unintended Start or Stop condition to other devices on the bus line. If this

parameter is too long, Clock Low time (TLOW) can be affected.

4: For Data Input: This parameter must be longer than tSP. If this parameter is too long, the Data Input Setup (TSU:DAT) or

Clock Low time (TLOW) can be affected.

For Data Output: This parameter is characterized, and tested indirectly by testing TAA parameter.

5: This parameter is ensured by characterization and not 100% tested. This parameter is not available for Standard Mode.

MCP3425

FIGURE 5-6: I2C Bus Timing Data.

SCL

SDA

TSU:STA

TSP THD:STA

TLOW

THIGH

THD:DAT

TAA

TSU:DAT

TSU:STO

TBUF 0.7 VDD

0.3 VDD

MCP3425

6.0 BASIC APPLICATION

CONFIGURATION

The MCP3425 device can be used for various precision

analog-to-digital converter applications. The device

operates with very simple connections to the

application circuit. The following sections discuss the

examples of the device connections and applications.

6.1 Connecting to the Application

Circuits

6.1.1 INPUT VOLTAGE RANGE

The fully differential input signals can be connected to

the V

+ and V

- input pins. The input range should be

within absolute common mode input voltage range:

- 0.3V to V

+ 0.3V. Outside this limit, the ESD

protection di ode at the input pin begins to conduct and

the error due to input leakage current increases rapidly.

Within this limit, the differential input V

(= V

+-V

is boosted by the PGA before a conversion takes place.

The MCP3425 can not accept negative input voltages

on the input pins. Figure 6-1 and Figure 6-2 show

typical connection ex amples for diffe rential inputs an d a

single-ended input, respectively. For the single-ended

input, the input signal is applied

to one of the input pins

(typically connected to the VIN+ pin) while the other

input pin (typically VIN- pin) is grounded. The input

signal range of the single-ended configuration is from

0V to 2.048V. All device characteristics hold for the

single-ended configuration, but this configuration loses

one bit resolution because the input can only stand in

positive half scale.

Refer to

Section 1.0 “Electrical

Characteristics”

6.1.2 BYPASS CAPACITORS ON VDD PIN

For accurate measurement, the application circuit

needs a clean supply voltage and must block any noise

signal to the MCP3425 device. Figure 6-1 shows an

example of using two bypass capacitors (a 10 µF

tantalum capacitor and a 0.1 µF ceramic capacitor) in

parallel on the VDD line. These ca pacitors are he lpful to

filter out any high frequency noises on the VDD line and

also provide the momentary bursts of extra currents

when the device needs from the supply. These

capa citor s shou ld be p lac ed a s clo se to th e VDD pin as

possible (within one inch). If the application circuit h as

separate digital and analog power supplies, the VDD

and VSS of the MCP3425 should reside on th e analog

plane.

6.1.3 CONNECTING TO I2C BUS USING

PULL-UP RESISTORS

The SCL and SDA pins of the MCP3425 are open-drain

configurations. These pins require a pull-up resistor as

shown in Figure 6-1. The value of these pull-up

resistors depends on the operating speed (standard,

fast, and high speed) and loading capacitance of the

I2C bus line. Higher value of pull-up resistor consumes

less power, but increases the signal transition time

(higher RC time constant) on the bus. Therefore, it can

limit the bus operating speed. The lower value of

resistor, on the other hand, consumes higher power,

but allows higher operating speed. If the bus line has

higher capacitance due to long bus line or high number

of devices connected to the bus, a smaller pull-up

resistor is needed to compensate the long RC time

constant. The pull-up resistor is typically chosen

between 1 kΩ and 10 kΩ ranges for standard and fast

modes, and less than 1 kΩ for high speed mode in high

loading capacitance environments.

FIGURE 6-1: T ypical Connection Example

for Differential Inputs.

FIGURE 6-2: T ypical Connection Example

for Single-Ended Input.

The number of devices connected to the bu s is limited

only by the maximum bus capacitance of 400 p F. The

bus loading capacitance affects on the bus operating

speed. For example, the highest bus op erating speed

for the 400 pF bus capacitance is 1.7 MHz, and

3.4 MHz for 100 pF. Figure 6-3 shows an example of

multiple device connections.

MCP3425

VIN+VIN-

VDD

VSS

SCL SDL 10 µF0.1 µF RR

Input Signals VDD VDD

TO MCU

(MASTER)

Note: R is the pull-up resistor.

MCP3425

VIN+VIN-

VDD

VSS

SCL SDL 10 µF0.1 µF RR

Input Signals VDD VDD

TO MCU

(MASTER)

Note: R is the pull-up resistor.

MCP3425

FIGURE 6-3: Example of Multiple Device

Connection on I2C Bus.

6.2 Device Connection Test

The user can test the presence of the MCP3425 on the

I2C bus line without performing an input data conver-

sion. This test can be achieved by checking an

acknowledge response from the MCP3425 after send-

ing a read or write command. Here is an example using

Figure 6-4:

(a) Set the R/W bit “HIGH” in the address byte.

(b) The MCP3425 will then acknowledge by pulling

SDA bus LOW during the ACK clock and then release

the bus back to the I2C Master.

from the Master and I2C communication can continue.

FIGURE 6-4: I2C Bus Connection Test.

6.3 Application Examples

The MCP3425 device can b e used in a broad range of

sensor and data acquisition applications.

Figure 6-5 shows an example of battery voltage

measurement. The circuit u ses a voltage divider if the

battery voltage is greater than the device’s internal

reference voltage (2.048V). The voltage divider circuit

is not needed if the input voltage is less than the

device’s internal reference voltage (2.048V). The user

can adjust the variable resistor (R2) to calibrate the

input voltage to be less than the device’s reference volt-

age (2.046V). The I 2C pull-up resistor (Rpull-up) values

are in the range of 5 kΩ to 10 kΩ for standard and high

speed modes (100 kHz, 400 kHz), and less than 1 kΩ

for fast mode (3.4 MHz). Since the ADC conversion is

performed by using its internal reference voltage

(2.048V), the conversion result is not affected by the

VDD changes or Battery voltage changes within its

operating voltage range (2.7V - 5.5V).

FIGURE 6-5: Example of Battery Voltage

Measurement.

SDA SCL

(24LC01)

Microcontroller

EEPROM

MCP3425

(TC74)

Temperature

Sensor

(PIC16F876)

123456789

SCL

SDA 1101A2A1A0 1

Start

Bit

Address Byte

Address bits

Device bits R/W

Start

Bit

MCP3425

ACK

Response

700 kΩ

Resistor

MCP3425

VIN+VIN-

VDD

VSS

SCL SDL 10 µF0.1 µF Rpull-up

VDD

TO MCU

(MASTER)

4.2V

To Load

Battery

Rpull-up

Voltage

Divider

MCP3425

Figure 6-6, shows an example of interfacing with a

bridge sensor for pressure measurement.

FIGURE 6-6: Example of Pressure

Measurement.

In this circuit example, the sensor full scale range is

±7.5 mV with a common mode input voltage of VDD / 2.

This configuration will provide a full 14-bit resolution

across the sensor output rang e. The alternative circuit

for this amount of accuracy would involve an analog

gain stage prior to a 16-bit ADC.

Figure 6-7 shows an example of temperature

measurement using a thermistor. This example can

achieve a linear response over a 50°C temperature

range. This can be implemented using a standard

resistor with 1% tolerance in series with the thermistor.

The value of the resistor is selected to be equal to the

thermistor value at the mid-point of the desired

temperature range.

FIGURE 6-7: Example of Temperature

Measurement.

NPP301

MCP3425

VIN+VIN-

VDD

VSS

SCL SDL 10 µF0.1 µF

Rpull-up

VDD VDD

TO MCU

(MASTER)

VDD

10 kΩ

Resistor

10 kΩ

Thermistor

MCP3425

VIN+VIN-

VDD

VSS

SCL SDL 10 µF0.1 µF

Rpull-up

VDD VDD

TO MCU

(MASTER)

VDD

MCP3425

7.0 PACKAGING INFORMATION

7.1 Package Marking Information

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanumeric traceability code

Pb-free JEDEC designator for Matte Tin (Sn)

*This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

6-Lead SOT-23

XXNN

Example

CQ25

Part Number Address

Option Code

MCP3425A0T-E/CH A0 (000) CQNN

MCP3425A1T-E/CH A1 (001) CRNN

MCP3425A2T-E/CH A2 (010) CSNN

MCP3425A3T-E/CH A3 (011) CTNN

MCP3425A4T-E/CH A4 (100) Note 1

MCP3425A5T-E/CH A5 (101) Note 1

MCP3425A6T-E/CH A6 (110) Note 1

MCP3425A7T-E/CH A7 (111) Note 1

Note 1: Contact Microchip Technology for these

address option devices.

MCP3425

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1RWHV

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 'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0

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2XWVLGH/HDG3LWFK H %6&

2YHUDOO+HLJKW $  ± 

0ROGHG3DFNDJH7KLFNQHVV $  ± 

6WDQGRII $  ± 

2YHUDOO:LGWK (  ± 

0ROGHG3DFNDJH:LGWK (  ± 

2YHUDOO/HQJWK '  ± 

)RRW/HQJWK /  ± 

)RRWSULQW /  ± 

)RRW$QJOH  ± 

/HDG7KLFNQHVV F  ± 

/HDG:LGWK E  ± 

PIN1IDBY

LASER MARK

123

A2 c

0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &%

MCP3425

APPENDIX A: REVISION HISTORY

Revision A (December 2007)

• Original Release of this Document.

MCP3425

NOTES:

MCP3425

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Device: MCP3425: Single Channel ΔΣ A/D Converter

Address Options: XX A2 A1 A0

A0 *=000

A1=001

A2=010

A3=011

* Default option. Contact Microchip factory for other

address options

Tape and Reel: T = Tape and Reel

Temperature Range: E = -40°C to +125°C

Package: CH = Plastic Small Outline Transistor (SOT-23-6),

6-lead

Examples:

a) MCP3425A0T-E/CH: Tape and Reel,

Single Channel ΔΣ A/D

Converter,

SOT-23-6 package,

Address Option = A0.

b) MCP3425A 1T-E/CH : Tape and Reel,

Single Channel ΔΣ A/D

Converter,

SOT-23-6 package,

Address Option = A1.

c) MCP3425A2T -E/CH: Tape and Reel,

Single Channel ΔΣ A/D

Converter,

SOT-23-6 package,

Address Option = A2.

d) MCP3425A3T -E/CH: Tape and Reel,

Single Channel ΔΣ A/D

Converter,

SOT-23-6 package,

Address Option = A3.

PART NO. XXX

Address Temperature

Range

Device

/XX

Package

Options

Tape and

Reel

MCP3425

NOTES:

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defen d, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC,

PICmicro, PICST ART, PRO MA TE, rfPIC and SmartShunt are

registered trademarks of Microchip Technology Incorporated

in the U.S.A. and other countries.

AmpLab, FilterLab, Linear Active Thermistor, Migratable

Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The

Embedded Control Solutions Company are registered

trademarks of Microchip Technology Incorporated in the

U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,

ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,

In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi,

MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit,

PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,

PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select

Mode, Smart Serial, SmartTel, Total Endurance, UNI/O,

WiperLock and ZENA are trademarks of Microchip

Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip T echnology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Dat a

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerne d about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection featur es of our

products. Attempts to break Microchip’ s code protection feature may be a violation of the Digit al Millennium Copyright Act. If such acts

allow unauthorized access to you r software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:200 2 certif ication for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping

devices, Serial EEPROMs, microperi pherals, nonvola tile memo ry and

analog product s. In addition, Microchip ’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

AMERICAS

Corporate Office

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

http://support.microchip.com

Web Address:

www.microchip.com

Atlanta

Duluth, GA

Tel: 678-957-9614

Fax: 678-957-1455

Boston

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Tel: 774-760-0087

Fax: 774-760-0088

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Tel: 630-285-0071

Fax: 630-285-0075

Dallas

Addison, TX

Tel: 972-818-7423

Fax: 972-818-2924

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Farmington Hills, MI

Tel: 248-538-2250

Fax: 248-538-2260

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Kokomo, IN

Tel: 765-864-8360

Fax: 765-864-8387

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Tel: 949-462-9523

Fax: 949-462-9608

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Santa Clara, CA

Tel: 408-961-6444

Fax: 408-961-6445

Toronto

Mississauga, Ontario,

Canada

Tel: 905-673-0699

Fax: 905-673-6509

ASIA/PACIFIC

Asia Pacific Office

Suites 3707-14, 37th Floor

Tower 6, The Gateway

Harbour City, Kowloon

Hong Kong

Tel: 852-2401-1200

Fax: 852-2401-3431

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Tel: 61-2-9868-6733

Fax: 61-2-9868-6755

China - Beijing

Tel: 86-10-8528-2100

Fax: 86-10-8528-2104

China - Chengdu

Tel: 86-28-8665-5511

Fax: 86-28-8665-7889

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Tel: 86-591-8750-3506

Fax: 86-591-8750-3521

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Fax: 852-2401-3431

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Tel: 86-25-8473-2460

Fax: 86-25-8473-2470

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Tel: 86-532-8502-7355

Fax: 86-532-8502-7205

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Tel: 86-21-5407-5533

Fax: 86-21-5407-5066

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Tel: 86-24-2334-2829

Fax: 86-24-2334-2393

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Tel: 86-755-8203-2660

Fax: 86-755-8203-1760

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Tel: 86-757-2839-5507

Fax: 86-757-2839-5571

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Tel: 86-27-5980-5300

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India - Bangalore

Tel: 91-80-4182-8400

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Fax: 82-2-558-5932 or

82-2-558-5934

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Fax: 886-3-572-6459

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Tel: 886-7-536-4818

Fax: 886-7-536-4803

Taiwan - Taipei

Tel: 886-2-2500-6610

Fax: 886-2-2508-0102

Thailand - Bangkok

Tel: 66-2-694-1351

Fax: 66-2-694-1350

EUROPE

Austria - Wels

Tel: 43-7242-2244-39

Fax: 43-7242-2244-393

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Fax: 45-4485-2829

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WORLDWIDE SALES AND SERVICE

10/05/07