March 2008 Rev 4 1/77
1
M28W640FCT
M28W640FCB
64 Mbit (4Mbx16, Boot Block)
3V Supply Flash memory
Feature summary
■Supply voltage
–V
DD = 2.7V to 3.6V Core Power Supply
–V
DDQ= 1.65V to 3.6V for Input/Output
–V
PP = 12V for fast Program (optional)
■Access times: 70, 85, 90,100ns
■Programming time:
– 10µs typical
– Double Word Programming Option
– Quadruple Word Programming Option
■Common Flash Interface
■Memory blocks
– Parameter Blocks (Top or Bottom location)
– Main Blocks
■Block locking
– All blocks locked at Power Up
– Any combination of blocks can be locked
–WP
for Block Lock-Down
■Security
– 128 bit user Programmable OTP cells
– 64 bit unique device identifier
■Automatic standby mode
■Program and Erase Suspend
■100,000 program/erase cycles per block
■Electronic signature
– Manufacturer code: 20h
– Top device code, M28W640FCT: 8848h
– Bottom device code, M28W640FCB: 8849h
■Packages
– ECOPACK® compliant
TSOP48 (N)
12 x 20mm
FBGA
TFBGA48 (ZB)
6.39 x 10.5mm
www.numonyx.com
Contents M28W640FCT, M28W640FCB
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Contents
1 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1 Address inputs (A0-A21) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2 Data Input/Output (DQ0-DQ15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3 Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.4 Output Enable (G) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.5 Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.6 Write Protect (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.7 Reset (RP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.8 VDD supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.9 VDDQ supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.10 VPP Program supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.11 VSS Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3 Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1 Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2 Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3 Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.4 Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.5 Automatic Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.6 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4 Command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1 Read Memory Array command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.2 Read Status Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.3 Read electronic signature command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.4 Read CFI Query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.5 Block Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.6 Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.7 Double Word Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.8 Quadruple Word Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
M28W640FCT, M28W640FCB Contents
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4.9 Clear Status Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.10 Program/Erase Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.11 Program/Erase Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.12 Protection Register Program command . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.13 Block Lock command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.14 Block Unlock command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.15 Block Lock-Down command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5 Block locking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.1 Reading a Block’s Lock status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.2 Locked state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.3 Unlocked state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.4 Lock-Down state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.5 Locking Operations during Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . 28
6 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.1 Program/Erase Controller status (bit 7) . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.2 Erase Suspend status (bit 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.3 Erase status (bit 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.4 Program status (bit 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.5 VPP status (bit 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.6 Program Suspend status (bit 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.7 Block Protection status (bit 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.8 Reserved (bit 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
8 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
9 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
10 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Appendix A Block address tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Appendix B Common Flash Interface (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Contents M28W640FCT, M28W640FCB
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Appendix C Flowcharts and pseudo codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Appendix D Command Interface and Program/Erase Controller State . . . . . . . 72
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
M28W640FCT, M28W640FCB List of tables
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List of tables
Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 2. Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 3. Command codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 4. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 5. Read Electronic signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 6. Read Block Lock signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 7. Read Protection Register and Lock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 8. Program, Erase Times and Program/Erase endurance cycles. . . . . . . . . . . . . . . . . . . . . . 26
Table 9. Block Lock status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 10. Protection status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 11. Status Register bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 12. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 13. Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 14. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 15. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 16. Read AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 17. Write AC characteristics, Write enable controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 18. Write AC characteristics, Chip enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 19. Power-Up and Reset AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 20. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, package mechanical data. . . . 44
Table 21. TFBGA48 6.39x10.5mm - 8x6 ball array, 0.75mm pitch, package mechanical data . . . . . 45
Table 22. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 23. Daisy Chain ordering scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 24. Top Boot Block Addresses, M28W640FCT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 25. Bottom Boot Block Addresses, M28W640FCB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 26. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 27. CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 28. CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 29. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 30. Primary Algorithm-specific Extended Query table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 31. Security code area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 32. Write State machine Current/Next . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 33. Write State machine Current/Next . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 34. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
List of figures M28W640FCT, M28W640FCB
6/77
List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 2. TSOP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 3. TFBGA connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 4. Block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 5. Protection Register memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 6. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 7. AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 8. Read AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 9. Write AC waveforms, Write enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 10. Write AC waveforms, Chip enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 11. Power-Up and Reset AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 12. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, package outline . . . . . . . . . . . 44
Figure 13. TFBGA48 6.39x10.5mm - 8x6 ball array, 0.75mm pitch, bottom view package outline . . . 45
Figure 14. TFBGA48 daisy chain - package connections (top view through package) . . . . . . . . . . . . 46
Figure 15. TFBGA48 daisy chain - PCB connections proposal (top view through package). . . . . . . . 47
Figure 16. Program flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 17. Double Word Program flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 18. Quadruple Word Program flowchart and pseudo code. . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 19. Program Suspend & Resume flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 20. Erase flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 21. Erase Suspend & Resume flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 22. Locking Operations flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 23. Protection Register Program flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . 71
M28W640FCT, M28W640FCB Summary description
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1 Summary description
The M28W640FCT and M28W640FCB are 64 Mbit (4 Mbit x 16) non-volatile Flash
memories that can be erased electrically at block level and programmed in-system on a
Word-by-Word basis using a 2.7V to 3.6V VDD supply for the circuitry and a 1.65V to 3.6V
VDDQ supply for the Input/Output pins. An optional 12V VPP power supply is provided to
speed up customer programming.
The devices feature an asymmetrical blocked architecture. They have an array of 135
blocks: 8 Parameter Blocks of 4 KWord and 127 Main Blocks of 32 KWord. The
M28W640FCT has the Parameter Blocks at the top of the memory address space while the
M28W640FCB locates the Parameter Blocks starting from the bottom. The memory maps
are shown in Figure 4: Block addresses.
The M28W640FCT and M28W640FCB feature an instant, individual block locking scheme
that allows any block to be locked or unlocked with no latency, enabling instant code and
data protection. All blocks have three levels of protection. They can be locked and locked-
down individually preventing any accidental programming or erasure. There is an additional
hardware protection against program and erase. When VPP ≤ VPPLK all blocks are protected
against program or erase. All blocks are locked at Power Up.
Each block can be erased separately. Erase can be suspended in order to perform either
read or program in any other block and then resumed. Program can be suspended to read
data in any other block and then resumed. Each block can be programmed and erased over
100,000 cycles.
The device includes a 192 bit Protection Register to increase the protection of a system
design. The Protection Register is divided into a 64 bit segment and a 128 bit segment. The
64 bit segment contains a unique device number written by Numonyx, while the second one
is one-time-programmable by the user. The user programmable segment can be
permanently protected. Figure 5, shows the Protection Register Memory Map.
Program and Erase commands are written to the Command Interface of the memory. An on-
chip Program/Erase Controller takes care of the timings necessary for program and erase
operations. The end of a program or erase operation can be detected and any error
conditions identified. The command set required to control the memory is consistent with
JEDEC standards.
The memory is offered in TSOP48 (12 × 20mm) and TFBGA48 (6.39 × 10.5mm, 0.75mm
pitch) packages and is supplied with all the bits erased (set to ’1’).
In order to meet environmental requirements, Numonyx offers the M28W640FCT and
M28W640FCB in ECOPACK® packages. These packages have a Lead-free second level
interconnect. The category of second Level Interconnect is marked on the package and on
the inner box label, in compliance with JEDEC Standard JESD97.
The maximum ratings related to soldering conditions are also marked on the inner box label.
Summary description M28W640FCT, M28W640FCB
8/77
Figure 1. Logic diagram
Table 1. Signal names
A0-A21 Address Inputs
DQ0-DQ15 Data Input/Output
EChip Enable
GOutput Enable
WWrite Enable
RP Reset
WP Write Protect
VDD Core Power supply
VDDQ Power supply for Input/Output
VPP Optional supply voltage for Fast Program & Erase
VSS Ground
NC Not Connected Internally
AI09903
22
A0-A21
WDQ0-DQ15
VDD
M28W640FCT
M28W640FCB
E
VSS
16
G
RP
WP
VDDQ VPP
M28W640FCT, M28W640FCB Summary description
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Figure 2. TSOP connections
DQ3
DQ9
DQ2
A6
DQ0
W
A3
DQ6
A8
A9
DQ13
A17
A10 DQ14
A2
DQ12
DQ10
DQ15
VDD
DQ4
DQ5
A7
DQ7
VPP
WP
AI09904b
M28W640FCT
M28W640FCB
12
1
13
24 25
36
37
48
DQ8
A20
A19
A1
A18
A4
A5
DQ1
DQ11
G
A12
A13
A16
A11
VDDQ
A15
A14
VSS
E
A0
RP
VSSQ
A21
Summary description M28W640FCT, M28W640FCB
10/77
Figure 3. TFBGA connections (top view through package)
AI04380b
C
B
A
87654321
E
D
F
A4
A7VPP
A8A11
A13
A0EDQ8DQ5DQ14A16
VSSQ
DQ0DQ9DQ3DQ6
DQ15
VDDQ
DQ1DQ10VDD
DQ7VSS
DQ2
A2
A5A17WA10
A14
A1A3A6A9A12A15
RP A18
DQ4
DQ13 G
DQ12
DQ11
WP A19
A20
A21
M28W640FCT, M28W640FCB Summary description
11/77
Figure 4. Block addresses
1. Also see Appendix A, Tables 24 and 25 for a full listing of the Block Addresses.
Figure 5. Protection Register memory map
AI09905
4 KWords
3FFFFF
3FF000
32 KWords
00FFFF
008000
32 KWords
007FFF
000000
M28W640FCT
Top Boot Block Addresses
4 KWords
3F8FFF
3F8000
32 KWords
3F0000
3F7FFF
Total of 8
4 KWord Blocks
Total of 127
32 KWord Blocks
4 KWords
3FFFFF
3F8000
32 KWords
32 KWords
000FFF
000000
M28W640FCB
Bottom Boot Block Addresses
4 KWords
3F7FFF
00FFFF
32 KWords
3F0000
008000
Total of 127
32 KWord Block
s
Total of 8
4 KWord Blocks
007FFF
007000
AI05520b
User Programmable OTP
Unique device number
Protection Register Lock 1 0
8Ch
85h
84h
81h
80h
PROTECTION REGISTER
Signal descriptions M28W640FCT, M28W640FCB
12/77
2 Signal descriptions
See Figure 1: Logic diagram and Table 1: Signal names, for a brief overview of the signals
connected to this device.
2.1 Address inputs (A0-A21)
The Address Inputs select the cells in the memory array to access during Bus Read
operations. During Bus Write operations they control the commands sent to the Command
Interface of the internal state machine.
2.2 Data Input/Output (DQ0-DQ15)
The Data I/O outputs the data stored at the selected address during a Bus Read operation
or inputs a command or the data to be programmed during a Write Bus operation.
2.3 Chip Enable (E)
The Chip Enable input activates the memory control logic, input buffers, decoders and
sense amplifiers. When Chip Enable is at VILand Reset is at VIH the device is in active
mode. When Chip Enable is at VIH the memory is deselected, the outputs are high
impedance and the power consumption is reduced to the stand-by level.
2.4 Output Enable (G)
The Output Enable controls data outputs during the Bus Read operation of the memory.
2.5 Write Enable (W)
The Write Enable controls the Bus Write operation of the memory’s Command Interface.
The data and address inputs are latched on the rising edge of Chip Enable, E, or Write
Enable, W, whichever occurs first.
2.6 Write Protect (WP)
Write Protect is an input that gives an additional hardware protection for each block. When
Write Protect is at VIL, the Lock-Down is enabled and the protection status of the block
cannot be changed. When Write Protect is at VIH, the Lock-Down is disabled and the block
can be locked or unlocked. (refer to Table 7: Read Protection Register and Lock Register).
M28W640FCT, M28W640FCB Signal descriptions
13/77
2.7 Reset (RP)
The Reset input provides a hardware reset of the memory. When Reset is at VIL, the
memory is in reset mode: the outputs are high impedance and the current consumption is
minimized. After Reset all blocks are in the Locked state. When Reset is at VIH, the device is
in normal operation. Exiting reset mode the device enters read array mode, but a negative
transition of Chip Enable or a change of the address is required to ensure valid data outputs.
2.8 VDD supply voltage
VDD provides the power supply to the internal core of the memory device. It is the main
power supply for all operations (Read, Program and Erase).
2.9 VDDQ supply voltage
VDDQ provides the power supply to the I/O pins and enables all Outputs to be powered
independently from VDD. VDDQ can be tied to VDD or can use a separate supply.
2.10 VPP Program supply voltage
VPP is both a control input and a power supply pin. The two functions are selected by the
voltage range applied to the pin. The Supply Voltage VDD and the Program Supply Voltage
VPP can be applied in any order.
If VPP is kept in a low voltage range (0V to 3.6V) VPP is seen as a control input. In this case
a voltage lower than VPPLK gives an absolute protection against program or erase, while
VPP > VPP1 enables these functions (see Table 15: DC characteristics, for the relevant
values). VPP is only sampled at the beginning of a program or erase; a change in its value
after the operation has started does not have any effect on Program or Erase, however for
Double or Quadruple Word Program the results are uncertain.
If VPP is in the range 11.4V to 12.6V it acts as a power supply pin. In this condition VPP must
be stable until the Program/Erase algorithm is completed (see Ta bl e 1 7 and Ta bl e 1 8 ).
2.11 VSS Ground
VSS is the reference for all voltage measurements.
Note: Each device in a system should have VDD, VDDQ and VPP decoupled with a 0.1µF
capacitor close to the pin. See Figure 7: AC measurement load circuit. The PCB track
widths should be sufficient to carry the required VPP program and erase currents.
Bus operations M28W640FCT, M28W640FCB
14/77
3 Bus operations
There are six standard bus operations that control the device. These are Bus Read, Bus
Write, Output Disable, Standby, Automatic Standby and Reset. See Table 2: Bus operations,
for a summary.
Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the
memory and do not affect bus operations.
3.1 Read
Read Bus operations are used to output the contents of the Memory Array, the Electronic
Signature, the Status Register and the Common Flash Interface. Both Chip Enable and
Output Enable must be at VIL in order to perform a read operation. The Chip Enable input
should be used to enable the device. Output Enable should be used to gate data onto the
output. The data read depends on the previous command written to the memory (see
Command Interface section). See Figure 8: Read AC waveforms, and Table 16: Read AC
characteristics, for details of when the output becomes valid.
Read mode is the default state of the device when exiting Reset or after power-up.
3.2 Write
Bus Write operations write Commands to the memory or latch Input Data to be
programmed. A write operation is initiated when Chip Enable and Write Enable are at VIL
with Output Enable at VIH. Commands, Input Data and Addresses are latched on the rising
edge of Write Enable or Chip Enable, whichever occurs first.
See Figure 9 and Figure 10, Write AC Waveforms, and Ta b l e 1 7 and Ta bl e 1 8 , Write AC
Characteristics, for details of the timing requirements.
3.3 Output Disable
The data outputs are high impedance when the Output Enable is at VIH.
3.4 Standby
Standby disables most of the internal circuitry allowing a substantial reduction of the current
consumption. The memory is in stand-by when Chip Enable is at VIH and the device is in
read mode. The power consumption is reduced to the stand-by level and the outputs are set
to high impedance, independently from the Output Enable or Write Enable inputs. If Chip
Enable switches to VIH during a program or erase operation, the device enters Standby
mode when finished.
M28W640FCT, M28W640FCB Bus operations
15/77
3.5 Automatic Standby
Automatic Standby provides a low power consumption state during Read mode. Following a
read operation, the device enters Automatic Standby after 150ns of bus inactivity even if
Chip Enable is Low, VIL, and the supply current is reduced to IDD1. The data Inputs/Outputs
will still output data if a bus Read operation is in progress.
3.6 Reset
During Reset mode when Output Enable is Low, VIL, the memory is deselected and the
outputs are high impedance. The memory is in Reset mode when Reset is at VIL. The power
consumption is reduced to the Standby level, independently from the Chip Enable, Output
Enable or Write Enable inputs. If Reset is pulled to VSS during a Program or Erase, this
operation is aborted and the memory content is no longer valid.
Table 2. Bus operations(1)
1. X = VIL or VIH, VPPH = 12V ± 5%
Operation E G W RP WP VPP DQ0-DQ15
Bus Read VIL VIL VIH VIH X Don't Care Data Output
Bus Write VIL VIH VIL VIH XV
DD or VPPH Data Input
Output Disable VIL VIH VIH VIH X Don't Care Hi-Z
Standby VIH XXV
IH X Don't Care Hi-Z
Reset X X X VIL X Don't Care Hi-Z
Command interface M28W640FCT, M28W640FCB
16/77
4 Command interface
All Bus Write operations to the memory are interpreted by the Command Interface.
Commands consist of one or more sequential Bus Write operations. An internal
Program/Erase Controller handles all timings and verifies the correct execution of the
Program and Erase commands. The Program/Erase Controller provides a Status Register
whose output may be read at any time during, to monitor the progress of the operation, or
the Program/Erase states. See Table 3: Command codes, for a summary of the commands
and see Appendix D, Table 32: Write State machine Current/Next, for a summary of the
Command Interface.
The Command Interface is reset to Read mode when power is first applied, when exiting
from Reset or whenever VDD is lower than VLKO. Command sequences must be followed
exactly. Any invalid combination of commands will reset the device to Read mode. Refer to
Table 4: Commands, in conjunction with the text descriptions below.
4.1 Read Memory Array command
The Read command returns the memory to its Read mode. One Bus Write cycle is required
to issue the Read Memory Array command and return the memory to Read mode.
Subsequent read operations will read the addressed location and output the data. When a
device Reset occurs, the memory defaults to Read mode.
4.2 Read Status Register command
The Status Register indicates when a program or erase operation is complete and the
success or failure of the operation itself. Issue a Read Status Register command to read the
Status Register’s contents. Subsequent Bus Read operations read the Status Register at
any address, until another command is issued. See Table 11: Status Register bits, for details
on the definitions of the bits.
The Read Status Register command may be issued at any time, even during a
Program/Erase operation. Any Read attempt during a Program/Erase operation will
automatically output the content of the Status Register.
4.3 Read electronic signature command
The Read Electronic Signature command reads the Manufacturer and Device Codes and
the Block Locking Status, or the Protection Register.
The Read Electronic Signature command consists of one write cycle, a subsequent read will
output the Manufacturer Code, the Device Code, the Block Lock and Lock-Down Status, or
the Protection and Lock Register. See Tables 5, 6 and 7 for the valid address.
M28W640FCT, M28W640FCB Command interface
17/77
4.4 Read CFI Query command
The Read Query Command is used to read data from the Common Flash Interface (CFI)
Memory Area, allowing programming equipment or applications to automatically match their
interface to the characteristics of the device. One Bus Write cycle is required to issue the
Read Query Command. Once the command is issued subsequent Bus Read operations
read from the Common Flash Interface Memory Area. See Appendix B: Common Flash
Interface (CFI), Tables 26, 27, 28, 29, 30 and 31 for details on the information contained in
the Common Flash Interface memory area.
Table 3. Command codes
Hex Code Command
01h Block Lock confirm
10h Program
20h Erase
2Fh Block Lock-Down confirm
30h Double Word Program
40h Program
50h Clear Status Register
56h Quadruple Word Program
60h Block Lock, Block Unlock, Block Lock-Down
70h Read Status Register
90h Read Electronic Signature
98h Read CFI Query
B0h Program/Erase Suspend
C0h Protection Register Program
D0h Program/Erase Resume, Block Unlock confirm
FFh Read Memory Array
Command interface M28W640FCT, M28W640FCB
18/77
4.5 Block Erase command
The Block Erase command can be used to erase a block. It sets all the bits within the
selected block to ’1’. All previous data in the block is lost. If the block is protected then the
Erase operation will abort, the data in the block will not be changed and the Status Register
will output the error.
Two Bus Write cycles are required to issue the command.
●The first bus cycle sets up the Erase command.
●The second latches the block address in the internal state machine and starts the
Program/Erase Controller.
If the second bus cycle is not Write Erase Confirm (D0h), Status Register bits b4 and b5 are
set and the command aborts.
Erase aborts if Reset turns to VIL. As data integrity cannot be guaranteed when the Erase
operation is aborted, the block must be erased again.
During Erase operations the memory will accept the Read Status Register command and
the Program/Erase Suspend command, all other commands will be ignored. Typical Erase
times are given in Table 8: Program, Erase Times and Program/Erase endurance cycles.
See Appendix C, Figure 20: Erase flowchart and pseudo code, for a suggested flowchart for
using the Erase command.
4.6 Program command
The memory array can be programmed word-by-word. Two bus write cycles are required to
issue the Program Command.
●The first bus cycle sets up the Program command.
●The second latches the Address and the Data to be written and starts the
Program/Erase Controller.
During Program operations the memory will accept the Read Status Register command and
the Program/Erase Suspend command. Typical Program times are given in Tabl e 8 :
Program, Erase Times and Program/Erase endurance cycles.
Programming aborts if Reset goes to VIL. As data integrity cannot be guaranteed when the
program operation is aborted, the block containing the memory location must be erased and
reprogrammed.
See Appendix C, Figure 16: Program flowchart and pseudo code, for the flowchart for using
the Program command.
M28W640FCT, M28W640FCB Command interface
19/77
4.7 Double Word Program command
This feature is offered to improve the programming throughput, writing a page of two
adjacent words in parallel.The two words must differ only for the address A0. Programming
should not be attempted when VPP is not at VPPH.
Three bus write cycles are necessary to issue the Double Word Program command.
●The first bus cycle sets up the Double Word Program Command.
●The second bus cycle latches the Address and the Data of the first word to be written.
●The third bus cycle latches the Address and the Data of the second word to be written
and starts the Program/Erase Controller.
Read operations output the Status Register content after the programming has started.
Programming aborts if Reset goes to VIL. As data integrity cannot be guaranteed when the
program operation is aborted, the block containing the memory location must be erased and
reprogrammed.
See Appendix C, Figure 17: Double Word Program flowchart and pseudo code for the
flowchart for using the Double Word Program command.
4.8 Quadruple Word Program command
This feature is offered to improve the programming throughput, writing a page of four
adjacent words in parallel.The four words must differ only for the addresses A0 and A1.
Programming should not be attempted when VPP is not at VPPH.
Five bus write cycles are necessary to issue the Quadruple Word Program command.
●The first bus cycle sets up the Quadruple Word Program Command.
●The second bus cycle latches the Address and the Data of the first word to be written.
●The third bus cycle latches the Address and the Data of the second word to be written.
●The fourth bus cycle latches the Address and the Data of the third word to be written.
●The fifth bus cycle latches the Address and the Data of the fourth word to be written
and starts the Program/Erase Controller.
Read operations output the Status Register content after the programming has started.
Programming aborts if Reset goes to VIL. As data integrity cannot be guaranteed when the
program operation is aborted, the block containing the memory location must be erased and
reprogrammed.
See Appendix C, Figure 18: Quadruple Word Program flowchart and pseudo code, for the
flowchart for using the Quadruple Word Program command.
4.9 Clear Status Register command
The Clear Status Register command can be used to reset bits 1, 3, 4 and 5 in the Status
Register to ‘0’. One bus write cycle is required to issue the Clear Status Register command.
The bits in the Status Register do not automatically return to ‘0’ when a new Program or
Erase command is issued. The error bits in the Status Register should be cleared before
attempting a new Program or Erase command.
Command interface M28W640FCT, M28W640FCB
20/77
4.10 Program/Erase Suspend command
The Program/Erase Suspend command is used to pause a Program or Erase operation.
One bus write cycle is required to issue the Program/Erase command and pause the
Program/Erase controller.
During Program/Erase Suspend the Command Interface will accept the Program/Erase
Resume, Read Array, Read Status Register, Read Electronic Signature and Read CFI
Query commands. Additionally, if the suspend operation was Erase then the Program,
Double Word Program, Quadruple Word Program, Block Lock, Block Lock-Down or
Protection Program commands will also be accepted. The block being erased may be
protected by issuing the Block Protect, Block Lock or Protection Program commands. When
the Program/Erase Resume command is issued the operation will complete. Only the blocks
not being erased may be read or programmed correctly.
During a Program/Erase Suspend, the device can be placed in a pseudo-standby mode by
taking Chip Enable to VIH. Program/Erase is aborted if Reset turns to VIL.
See Appendix C, Figure 19: Program Suspend & Resume flowchart and pseudo code, and
Figure 21: Erase Suspend & Resume flowchart and pseudo code, for flowcharts for using
the Program/Erase Suspend command.
4.11 Program/Erase Resume command
The Program/Erase Resume command can be used to restart the Program/Erase Controller
after a Program/Erase Suspend operation has paused it. One Bus Write cycle is required to
issue the command. Once the command is issued subsequent Bus Read operations read
the Status Register.
See Appendix C, Figure 19: Program Suspend & Resume flowchart and pseudo code, and
Figure 21: Erase Suspend & Resume flowchart and pseudo code, for flowcharts for using
the Program/Erase Resume command.
4.12 Protection Register Program command
The Protection Register Program command is used to Program the 128 bit user One-Time-
Programmable (OTP) segment of the Protection Register. The segment is programmed 16
bits at a time. When shipped all bits in the segment are set to ‘1’. The user can only program
the bits to ‘0’.
Two write cycles are required to issue the Protection Register Program command.
●The first bus cycle sets up the Protection Register Program command.
●The second latches the Address and the Data to be written to the Protection Register
and starts the Program/Erase Controller.
Read operations output the Status Register content after the programming has started.
The segment can be protected by programming bit 1 of the Protection Lock Register (see
Figure 5: Protection Register memory map). Attempting to program a previously protected
Protection Register will result in a Status Register error. The protection of the Protection
Register is not reversible.
The Protection Register Program cannot be suspended.
M28W640FCT, M28W640FCB Command interface
21/77
4.13 Block Lock command
The Block Lock command is used to lock a block and prevent Program or Erase operations
from changing the data in it. All blocks are locked at power-up or reset.
Two Bus Write cycles are required to issue the Block Lock command.
●The first bus cycle sets up the Block Lock command.
●The second Bus Write cycle latches the block address.
The lock status can be monitored for each block using the Read Electronic Signature
command. Ta bl e 1 0 shows the protection status after issuing a Block Lock command.
The Block Lock bits are volatile, once set they remain set until a hardware reset or power-
down/power-up. They are cleared by a Blocks Unlock command. Refer to the section, Block
Locking, for a detailed explanation.
Command interface M28W640FCT, M28W640FCB
22/77
4.14 Block Unlock command
The Block Unlock command is used to unlock a block, allowing the block to be programmed
or erased. Two Bus Write cycles are required to issue the Block Unlock command.
●The first bus cycle sets up the Block Unlock command.
●The second Bus Write cycle latches the block address.
The lock status can be monitored for each block using the Read Electronic Signature
command. Ta bl e 1 0 shows the protection status after issuing a Block Unlock command.
Refer to the section, Block Locking, for a detailed explanation.
4.15 Block Lock-Down command
A locked block cannot be Programmed or Erased, or have its protection status changed
when WP is low, VIL. When WP is high, VIH, the Lock-Down function is disabled and the
locked blocks can be individually unlocked by the Block Unlock command.
Two Bus Write cycles are required to issue the Block Lock-Down command.
●The first bus cycle sets up the Block Lock command.
●The second Bus Write cycle latches the block address.
The lock status can be monitored for each block using the Read Electronic Signature
command. Locked-Down blocks revert to the locked (and not locked-down) state when the
device is reset on power-down. Ta b l e 1 0 shows the protection status after issuing a Block
Lock-Down command. Refer to the section, Block Locking, for a detailed explanation.
M28W640FCT, M28W640FCB Command interface
23/77
Table 4. Commands(1)
Commands
Cycles
Bus Write operations
1st Cycle 2nd Cycle 3rd Cycle 4th Cycle 5th Cycle
Op. Add Data Op. Add Data Op. Add Data Op. Add Data Op. Add Data
Read Memory
Array 1+ Write X FFh Read RA RD
Read Status
Register 1+ Write X 70h Read X SRD
Read
Electronic
Signature
1+ Write X 90h Read SA(2) IDh
Read CFI
Query 1+ Write X 98h Read QA QD
Erase 2 Write X 20h Write BA D0h
Program 2 Write X 40h or
10h Write PA PD
Double Word
Program(3) 3 Write X 30h Write PA1 PD1 Write PA2 PD2
Quadruple
Word
Program(4)
5 Write X 56h Write PA1 PD1 Write PA2 PD2 Write PA3 PD3 Write PA4 PD4
Clear Status
Register 1 Write X 50h
Program/Erase
Suspend 1Write X B0h
Program/Erase
Resume 1Write X D0h
Block Lock 2 Write X 60h Write BA 01h
Block Unlock 2 Write X 60h Write BA D0h
Block Lock-
Down 2 Write X 60h Write BA 2Fh
Protection
Register
Program
2 Write X C0h Write PRA PRD
1. X = Don't Care,RA=Read Address,RD=Read Data, SRD=Status Register Data, ID=Identifier (Manufacture and Device
Code), QA=Query Address, QD=Query Data, BA=Block Address, PA=Program Address, PD=Program Data,
PRA=Protection Register Address, PRD=Protection Register Data.
2. The signature addresses are listed in Tables 5, 6 and 7.
3. Program Addresses 1 and 2 must be consecutive Addresses differing only for A0.
4. Program Addresses 1,2,3 and 4 must be consecutive Addresses differing only for A0 and A1.
Command interface M28W640FCT, M28W640FCB
24/77
Table 5. Read Electronic signature(1)
1. RP = VIH.
Code Device E G W A0 A1 A2-A7 A8-A21 DQ0-DQ7 DQ8-
DQ15
Manufacture
Code VIL VIL VIH VIL VIL 0 Don't Care 20h 00h
Device Code
M28W640
FCT VIL VIL VIH VIH VIL 0 Don't Care 48h 88h
M28W640
FCB VIL VIL VIH VIH VIL 0 Don't Care 49h 88h
Table 6. Read Block Lock signature
Block Status E G W A0 A1 A2-A7 A8-A11 A12-A21 DQ0 DQ1 DQ2-
DQ15
Locked Block VIL VIL VIH VIL VIH 0Don't
Care
Block
Address 1 0 00h
Unlocked
Block VIL VIL VIH VIL VIH 0Don't
Care
Block
Address 0 0 00h
Locked-
Down Block VIL VIL VIH VIL VIH 0Don't
Care
Block
Address X (1)
1. A Locked-Down Block can be locked "DQ0 = 1" or unlocked "DQ0 = 0"; see Block Locking section.
1 00h
M28W640FCT, M28W640FCB Command interface
25/77
Table 7. Read Protection Register and Lock Register
Word E G W A0-A7 A8-A21 DQ0 DQ1 DQ2 DQ3-
DQ7
DQ8-
DQ15
Lock VIL VIL VIH 80h Don't
Care 0OTP Prot.
data 0 00h 00h
Unique
ID 0 VIL VIL VIH 81h Don't
Care ID data ID data ID data ID data ID data
Unique
ID 1 VIL VIL VIH 82h Don't
Care ID data ID data ID data ID data ID data
Unique
ID 2 VIL VIL VIH 83h Don't
Care ID data ID data ID data ID data ID data
Unique
ID 3 VIL VIL VIH 84h Don't
Care ID data ID data ID data ID data ID data
OTP 0 VIL VIL VIH 85h Don't
Care OTP data OTP data OTP data OTP
data
OTP
data
OTP 1 VIL VIL VIH 86h Don't
Care OTP data OTP data OTP data OTP
data
OTP
data
OTP 2 VIL VIL VIH 87h Don't
Care OTP data OTP data OTP data OTP
data
OTP
data
OTP 3 VIL VIL VIH 88h Don't
Care OTP data OTP data OTP data OTP
data
OTP
data
OTP 4 VIL VIL VIH 89h Don't
Care OTP data OTP data OTP data OTP
data
OTP
data
OTP 5 VIL VIL VIH 8Ah Don't
Care OTP data OTP data OTP data OTP
data
OTP
data
OTP 6 VIL VIL VIH 8Bh Don't
Care OTP data OTP data OTP data OTP
data
OTP
data
OTP 7 VIL VIL VIH 8Ch Don't
Care OTP data OTP data OTP data OTP
data
OTP
data
Command interface M28W640FCT, M28W640FCB
26/77
Table 8. Program, Erase Times and Program/Erase endurance cycles
Parameter Test Conditions
M28W640FCT, M28W640FCB
Unit
Min Typ Max
Word Program VPP = VDD 10 200 µs
Double Word Program VPP = 12V ±5% 10 200 µs
Quadruple Word Program VPP = 12V ±5% 10 200 µs
Main Block Program VPP = 12V ±5% 0.16/0.08 (1)
1. Typical time to program a Main or Parameter Block using the Double Word Program and the Quadruple
Word Program commands respectively.
5s
VPP = VDD 0.32 5 s
Parameter Block Program VPP = 12V ±5% 0.02/0.01 (1) 4s
VPP = VDD 0.04 4 s
Main Block Erase VPP = 12V ±5% 1 10 s
VPP = VDD 110s
Parameter Block Erase VPP = 12V ±5% 0.4 10 s
VPP = VDD 0.4 10 s
Program/Erase Cycles
(per Block) 100,000 cycles
M28W640FCT, M28W640FCB Block locking
27/77
5 Block locking
The M28W640FCT and M28W640FCB feature an instant, individual block locking scheme
that allows any block to be locked or unlocked with no latency. This locking scheme has
three levels of protection.
●Lock/Unlock - this first level allows software-only control of block locking.
●Lock-Down - this second level requires hardware interaction before locking can be
changed.
●VPP ≤ VPPLK - the third level offers a complete hardware protection against program and
erase on all blocks.
The protection status of each block can be set to Locked, Unlocked, and Lock-Down.
Ta bl e 1 0 , defines all of the possible protection states (WP
, DQ1, DQ0), and Appendix C,
Figure 22, shows a flowchart for the locking operations.
5.1 Reading a Block’s Lock status
The lock status of every block can be read in the Read Electronic Signature mode of the
device. To enter this mode write 90h to the device. Subsequent reads at the address
specified in Ta b l e 6 , will output the protection status of that block. The lock status is
represented by DQ0 and DQ1. DQ0 indicates the Block Lock/Unlock status and is set by the
Lock command and cleared by the Unlock command. It is also automatically set when
entering Lock-Down. DQ1 indicates the Lock-Down status and is set by the Lock-Down
command. It cannot be cleared by software, only by a hardware reset or power-down.
The following sections explain the operation of the locking system.
5.2 Locked state
The default status of all blocks on power-up or after a hardware reset is Locked (states
(0,0,1) or (1,0,1)). Locked blocks are fully protected from any program or erase. Any
program or erase operations attempted on a locked block will return an error in the Status
Register. The Status of a Locked block can be changed to Unlocked or Lock-Down using the
appropriate software commands. An Unlocked block can be Locked by issuing the Lock
command.
5.3 Unlocked state
Unlocked blocks (states (0,0,0), (1,0,0) (1,1,0)), can be programmed or erased. All unlocked
blocks return to the Locked state after a hardware reset or when the device is powered-
down. The status of an unlocked block can be changed to Locked or Locked-Down using the
appropriate software commands. A locked block can be unlocked by issuing the Unlock
command.
Block locking M28W640FCT, M28W640FCB
28/77
5.4 Lock-Down state
Blocks that are Locked-Down (state (0,1,x))are protected from program and erase
operations (as for Locked blocks) but their protection status cannot be changed using
software commands alone. A Locked or Unlocked block can be Locked-Down by issuing the
Lock-Down command. Locked-Down blocks revert to the Locked state when the device is
reset or powered-down.
The Lock-Down function is dependent on the WP input pin. When WP=0 (VIL), the blocks in
the Lock-Down state (0,1,x) are protected from program, erase and protection status
changes. When WP=1 (VIH) the Lock-Down function is disabled (1,1,1) and Locked-Down
blocks can be individually unlocked to the (1,1,0) state by issuing the software command,
where they can be erased and programmed. These blocks can then be relocked (1,1,1) and
unlocked (1,1,0) as desired while WP remains high. When WP is low , blocks that were
previously Locked-Down return to the Lock-Down state (0,1,x) regardless of any changes
made while WP was high. Device reset or power-down resets all blocks , including those in
Lock-Down, to the Locked state.
5.5 Locking Operations during Erase Suspend
Changes to block lock status can be performed during an erase suspend by using the
standard locking command sequences to unlock, lock or lock-down a block. This is useful in
the case when another block needs to be updated while an erase operation is in progress.
To change block locking during an erase operation, first write the Erase Suspend command,
then check the status register until it indicates that the erase operation has been
suspended. Next write the desired Lock command sequence to a block and the lock status
will be changed. After completing any desired lock, read, or program operations, resume the
erase operation with the Erase Resume command.
If a block is locked or locked-down during an erase suspend of the same block, the locking
status bits will be changed immediately, but when the erase is resumed, the erase operation
will complete.
Locking operations cannot be performed during a program suspend. Refer to Appendix D,
Command Interface and Program/Erase Controller State, for detailed information on which
commands are valid during erase suspend.
Table 9. Block Lock status
Item Address Data
Block Lock Configuration
xx002
LOCK
Block is Unlocked DQ0=0
Block is Locked DQ0=1
Block is Locked-Down DQ1=1
M28W640FCT, M28W640FCB Block locking
29/77
Table 10. Protection status
Current Protection Status(1)
(WP, DQ1, DQ0)
1. The lock status is defined by the write protect pin and by DQ1 (‘1’ for a locked-down block) and DQ0 (‘1’ for
a locked block) as read in the Read Electronic Signature command with A1 = VIH and A0 = VIL.
Next Protection Status(1)
(WP, DQ1, DQ0)
Current State Program/Erase
Allowed
After Block
Lock
Command
After Block
Unlock
Command
After Block
Lock-Down
Command
After WP
transition
1,0,0 yes 1,0,1 1,0,0 1,1,1 0,0,0
1,0,1(2)
2. All blocks are locked at power-up, so the default configuration is 001 or 101 according to WP status.
no 1,0,1 1,0,0 1,1,1 0,0,1
1,1,0 yes 1,1,1 1,1,0 1,1,1 0,1,1
1,1,1 no 1,1,1 1,1,0 1,1,1 0,1,1
0,0,0 yes 0,0,1 0,0,0 0,1,1 1,0,0
0,0,1(2) no 0,0,1 0,0,0 0,1,1 1,0,1
0,1,1 no 0,1,1 0,1,1 0,1,1 1,1,1 or 1,1,0 (3)
3. A WP transition to VIH on a locked block will restore the previous DQ0 value, giving a 111 or 110.
Status Register M28W640FCT, M28W640FCB
30/77
6 Status Register
The Status Register provides information on the current or previous Program or Erase
operation. The various bits convey information and errors on the operation. To read the
Status register the Read Status Register command can be issued, refer to Read Status
Register Command section. To output the contents, the Status Register is latched on the
falling edge of the Chip Enable or Output Enable signals, and can be read until Chip Enable
or Output Enable returns to VIH. Either Chip Enable or Output Enable must be toggled to
update the latched data.
Bus Read operations from any address always read the Status Register during Program and
Erase operations.
The bits in the Status Register are summarized in Table 11: Status Register bits. Refer to
Ta bl e 1 1 in conjunction with the following text descriptions.
6.1 Program/Erase Controller status (bit 7)
The Program/Erase Controller Status bit indicates whether the Program/Erase Controller is
active or inactive. When the Program/Erase Controller Status bit is Low (set to ‘0’), the
Program/Erase Controller is active; when the bit is High (set to ‘1’), the Program/Erase
Controller is inactive, and the device is ready to process a new command.
The Program/Erase Controller Status is Low immediately after a Program/Erase Suspend
command is issued until the Program/Erase Controller pauses. After the Program/Erase
Controller pauses the bit is High .
During Program, Erase, operations the Program/Erase Controller Status bit can be polled to
find the end of the operation. Other bits in the Status Register should not be tested until the
Program/Erase Controller completes the operation and the bit is High.
After the Program/Erase Controller completes its operation the Erase Status, Program
Status, VPP Status and Block Lock Status bits should be tested for errors.
6.2 Erase Suspend status (bit 6)
The Erase Suspend Status bit indicates that an Erase operation has been suspended or is
going to be suspended. When the Erase Suspend Status bit is High (set to ‘1’), a
Program/Erase Suspend command has been issued and the memory is waiting for a
Program/Erase Resume command.
The Erase Suspend Status should only be considered valid when the Program/Erase
Controller Status bit is High (Program/Erase Controller inactive). Bit 7 is set within 30µs of
the Program/Erase Suspend command being issued therefore the memory may still
complete the operation rather than entering the Suspend mode.
When a Program/Erase Resume command is issued the Erase Suspend Status bit returns
Low.
M28W640FCT, M28W640FCB Status Register
31/77
6.3 Erase status (bit 5)
The Erase Status bit can be used to identify if the memory has failed to verify that the block
has erased correctly. When the Erase Status bit is High (set to ‘1’), the Program/Erase
Controller has applied the maximum number of pulses to the block and still failed to verify
that the block has erased correctly. The Erase Status bit should be read once the
Program/Erase Controller Status bit is High (Program/Erase Controller inactive).
Once set High, the Erase Status bit can only be reset Low by a Clear Status Register
command or a hardware reset. If set High it should be reset before a new Program or Erase
command is issued, otherwise the new command will appear to fail.
6.4 Program status (bit 4)
The Program Status bit is used to identify a Program failure. When the Program Status bit is
High (set to ‘1’), the Program/Erase Controller has applied the maximum number of pulses
to the byte and still failed to verify that it has programmed correctly. The Program Status bit
should be read once the Program/Erase Controller Status bit is High (Program/Erase
Controller inactive).
Once set High, the Program Status bit can only be reset Low by a Clear Status Register
command or a hardware reset. If set High it should be reset before a new command is
issued, otherwise the new command will appear to fail.
6.5 VPP status (bit 3)
The VPP Status bit can be used to identify an invalid voltage on the VPP pin during Program
and Erase operations. The VPP pin is only sampled at the beginning of a Program or Erase
operation. Indeterminate results can occur if VPP becomes invalid during an operation.
When the VPP Status bit is Low (set to ‘0’), the voltage on the VPP pin was sampled at a valid
voltage; when the VPP Status bit is High (set to ‘1’), the VPP pin has a voltage that is below
the VPP Lockout Voltage, VPPLK, the memory is protected and Program and Erase
operations cannot be performed.
Once set High, the VPP Status bit can only be reset Low by a Clear Status Register
command or a hardware reset. If set High it should be reset before a new Program or Erase
command is issued, otherwise the new command will appear to fail.
6.6 Program Suspend status (bit 2)
The Program Suspend Status bit indicates that a Program operation has been suspended.
When the Program Suspend Status bit is High (set to ‘1’), a Program/Erase Suspend
command has been issued and the memory is waiting for a Program/Erase Resume
command. The Program Suspend Status should only be considered valid when the
Program/Erase Controller Status bit is High (Program/Erase Controller inactive). Bit 2 is set
within 5µs of the Program/Erase Suspend command being issued therefore the memory
may still complete the operation rather than entering the Suspend mode.
When a Program/Erase Resume command is issued the Program Suspend Status bit
returns Low.
Status Register M28W640FCT, M28W640FCB
32/77
6.7 Block Protection status (bit 1)
The Block Protection Status bit can be used to identify if a Program or Erase operation has
tried to modify the contents of a locked block.
When the Block Protection Status bit is High (set to ‘1’), a Program or Erase operation has
been attempted on a locked block.
Once set High, the Block Protection Status bit can only be reset Low by a Clear Status
Register command or a hardware reset. If set High it should be reset before a new
command is issued, otherwise the new command will appear to fail.
6.8 Reserved (bit 0)
Bit 0 of the Status Register is reserved. Its value must be masked.
Note: Refer to Appendix C: Flowcharts and pseudo codes, for using the Status Register.
Table 11. Status Register bits(1)
1. Logic level '1' is High, '0' is Low.
Bit Name Logic Level Definition
7 P/E.C. Status '1' Ready
'0' Busy
6 Erase Suspend Status '1' Suspended
'0' In progress or Completed
5 Erase Status '1' Erase Error
'0' Erase Success
4 Program Status '1' Program Error
'0' Program Success
3V
PP Status '1' VPP Invalid, Abort
'0' VPP OK
2 Program Suspend Status '1' Suspended
'0' In Progress or Completed
1 Block Protection Status '1' Program/Erase on protected Block,
Abort
'0' No operation to protected blocks
0 Reserved
M28W640FCT, M28W640FCB Maximum rating
33/77
7 Maximum rating
Stressing the device above the rating listed in the Absolute Maximum Ratings table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. Refer also to the Numonyx SURE Program
and other relevant quality documents.
Table 12. Absolute maximum ratings
Symbol Parameter
Value
Unit
Min Max
TAAmbient Operating Temperature (1)
1. Depends on range.
– 40 85 °C
TBIAS Temperature Under Bias – 40 125 °C
TSTG Storage Temperature – 55 155 °C
VIO Input or Output voltage – 0.6 VDDQ+0.6 V
VDD, VDDQ Supply voltage – 0.6 4.1 V
VPP Program voltage – 0.6 13 V
DC and AC parameters M28W640FCT, M28W640FCB
34/77
8 DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristics Tables that
follow, are derived from tests performed under the Measurement Conditions summarized in
Table 13: Operating and AC measurement conditions. Designers should check that the
operating conditions in their circuit match the measurement conditions when relying on the
quoted parameters.
Figure 6. AC measurement I/O waveform
Table 13. Operating and AC measurement conditions
Parameter
M28W640FCT, M28W640FCB
70 85 90 10
Units
Min Max Min Max Min Max Min Max
VDD supply voltage 2.7 3.6 2.7 3.6 2.7 3.6 2.7 3.6 V
VDDQ supply voltage
(VDDQ ≤ VDD)2.7 3.6 2.7 3.6 2.7 3.6 1.65 3.6 V
Ambient Operating
Temperature –40 85 –40 85 –40 85 –40 85 °C
Load capacitance (CL)50 50 50 50pF
Input Rise and Fall Times 5 5 5 5 ns
Input pulse voltages 0 to VDDQ 0 to VDDQ 0 to VDDQ 0 to VDDQ V
Input and Output Timing
Ref. voltages VDDQ/2 VDDQ/2 VDDQ/2 VDDQ/2 V
AI00610
VDDQ
0V
VDDQ/2
M28W640FCT, M28W640FCB DC and AC parameters
35/77
Figure 7. AC measurement load circuit
Table 14. Capacitance(1)
1. Sampled only, not 100% tested.
Symbol Parameter Test Condition Min Max Unit
CIN Input capacitance VIN = 0V 6 pF
COUT Output capacitance VOUT = 0V 12 pF
AI00609C
VDDQ
CL
CL includes JIG capacitance
25kΩ
DEVICE
UNDER
TEST
0.1µF
VDD
0.1µF
VDDQ
25kΩ
DC and AC parameters M28W640FCT, M28W640FCB
36/77
Table 15. DC characteristics
Symbol Parameter Test condition Min Typ Max Unit
ILI Input Leakage Current 0V≤ VIN ≤ VDDQ ±1 µA
ILO Output Leakage Current 0V≤ VOUT ≤VDDQ ±10 µA
IDD Supply Current (Read) E = VSS, G = VIH,
f = 5MHz 918mA
IDD1
Supply Current (Stand-by or
Automatic Stand-by)
E = VDDQ ± 0.2V,
RP = VDDQ ± 0.2V 15 50 µA
IDD2 Supply Current (Reset) RP = VSS ± 0.2V 15 50 µA
IDD3 Supply Current (Program)
Program in progress
VPP = 12V ± 5% 510mA
Program in progress
VPP = VDD
10 20 mA
IDD4 Supply Current (Erase)
Erase in progress
VPP = 12V ± 5% 520mA
Erase in progress
VPP = VDD
10 20 mA
IDD5
Supply Current
(Program/Erase Suspend)
E = VDDQ ± 0.2V,
Erase suspended 15 50 µA
IPP
Program Current
(Read or Stand-by) VPP > VDD 400 µA
IPP1
Program Current
(Read or Stand-by) VPP ≤ VDD 15µA
IPP2 Program Current (Reset) RP = VSS ± 0.2V 1 5 µA
IPP3 Program Current (Program)
Program in progress
VPP = 12V ± 5% 110mA
Program in progress
VPP = VDD
15µA
IPP4 Program Current (Erase)
Erase in progress
VPP = 12V ± 5% 310mA
Erase in progress
VPP = VDD
15µA
VIL Input Low voltage –0.5 0.4 V
VDDQ ≥ 2.7V –0.5 0.8 V
VIH Input High voltage VDDQ –0.4 VDDQ +0.4 V
VDDQ ≥ 2.7V 0.7 VDDQ VDDQ +0.4 V
VOL Output Low voltage
IOL = 100µA,
VDD = VDD min,
VDDQ = VDDQ min
0.1 V
VOH Output High voltage
IOH = –100µA,
VDD = VDD min,
VDDQ = VDDQ min
VDDQ –0.1 V
M28W640FCT, M28W640FCB DC and AC parameters
37/77
VPP1
Program voltage (Program or
Erase operations) 1.65 3.6 V
VPPH
Program voltage (Program or
Erase operations) 11.4 12.6 V
VPPLK
Program voltage (Program
and Erase lock-out) 1V
VLKO
VDD supply voltage (Program
and Erase lock-out) 2V
Table 15. DC characteristics (continued)
Symbol Parameter Test condition Min Typ Max Unit
DC and AC parameters M28W640FCT, M28W640FCB
38/77
Figure 8. Read AC waveforms
Table 16. Read AC characteristics
Symbol Alt Parameter
M28W640FCT, M28W640FCB
Unit
70 85 90 10
tAVAV tRC
Address Valid to Next Address
Valid Min 70 85 90 100 ns
tAVQV tACC Address Valid to Output Valid Max 70 85 90 100 ns
tAXQX (1)
1. Sampled only, not 100% tested.
tOH
Address Transition to Output
Tr a n s i t i on Min0000ns
tEHQX (1) tOH
Chip Enable High to Output
Tr a n s i t i on Min0000ns
tEHQZ (1) tHZ Chip Enable High to Output Hi-Z Max 20 20 25 25 ns
tELQV (2)
2. G may be delayed by up to tELQV - tGLQV after the falling edge of E without increasing tELQV
tCE Chip Enable Low to Output Valid Max 70 85 90 100 ns
tELQX (1) tLZ
Chip Enable Low to Output
Tr a n s i t i on Min0000ns
tGHQX
(1) tOH
Output Enable High to Output
Tr a n s i t i on Min0000ns
tGHQZ (1) tDF Output Enable High to Output Hi-Z Max 20 20 25 25 ns
tGLQV (2) tOE
Output Enable Low to Output
Valid Max20203035ns
tGLQX (1) tOLZ
Output Enable Low to Output
Tr a n s i t i on Min0000ns
DQ0-
DQ15
AI04387
VALID
A0-A21
E
tAXQX
tAVAV
VALID
tAVQV
tELQV
tELQX
tGLQV
tGLQX
ADDR. VALID
CHIP ENABLE
OUTPUTS
ENABLED DATA VALID STANDBY
G
tGHQX
tGHQZ
tEHQX
tEHQZ
M28W640FCT, M28W640FCB DC and AC parameters
39/77
Figure 9. Write AC waveforms, Write enable controlled
E
G
W
DQ0-DQ15 COMMAND CMD or DATA STATUS REGISTER
VPP
VALIDA0-A21
tAVAV
tQVVPL
tAVWH tWHAX
PROGRAM OR ERASE
tELWL tWHEH
tWHDX
tDVWH
tWLWH
tWHWL
tVPHWH
SET-UP COMMAND CONFIRM COMMAND
OR DATA INPUT
STATUS REGISTER
READ
1st POLLING
tELQV
AI04388
tWPHWH
WP
tWHGL
tQVWPL
tWHEL
DC and AC parameters M28W640FCT, M28W640FCB
40/77
Table 17. Write AC characteristics, Write enable controlled
Symbol Alt Parameter
M28W640FCT,
M28W640FCB Unit
70 85 90 10
tAVAV tWC Write Cycle Time Min 70 85 90 100 ns
tAVWH tAS Address Valid to Write Enable High Min 45 45 50 50 ns
tDVWH tDS Data Valid to Write Enable High Min 45 45 50 50 ns
tELWL tCS
Chip Enable Low to Write Enable
Low Min 0 0 0 0 ns
tELQV Chip Enable Low to Output Valid Min 70 85 90 100 ns
tQVVPL(1)
(2)
1. Sampled only, not 100% tested.
2. Applicable if VPP is seen as a logic input (VPP < 3.6V).
Output Valid to VPP Low Min 0 0 0 0 ns
tQVWPL Output Valid to Write Protect Low Min 0 0 0 0 ns
tVPHWH (1) tVPS VPP High to Write Enable High Min 200 200 200 200 ns
tWHAX tAH
Write Enable High to Address
Transition Min 0 0 0 0 ns
tWHDX tDH
Write Enable High to Data
Transition Min 0 0 0 0 ns
tWHEH tCH
Write Enable High to Chip Enable
High Min 0 0 0 0 ns
tWHEL
Write Enable High to Chip Enable
Low Min 25 25 30 30 ns
tWHGL
Write Enable High to Output
Enable Low Min 20 20 30 30 ns
tWHWL
tWP
H
Write Enable High to Write Enable
Low Min 25 25 30 30 ns
tWLWH tWP
Write Enable Low to Write Enable
High Min 45 45 50 50 ns
tWPHWH
Write Protect High to Write Enable
High Min 45 45 50 50 ns
M28W640FCT, M28W640FCB DC and AC parameters
41/77
Figure 10. Write AC waveforms, Chip enable controlled
E
G
DQ0-DQ15 COMMAND CMD or DATA STATUS REGISTER
VPP
VALIDA0-A21
tAVAV
tQVVPL
tAVEH tEHAX
PROGRAM OR ERASE
tWLEL tEHWH
tEHDX
tDVEH
tELEH
tEHEL
tVPHEH
POWER-UP AND
SET-UP COMMAND
CONFIRM COMMAND
OR DATA INPUT
STATUS REGISTER
READ
1st POLLING
tELQV
AI04389
W
tWPHEH
WP
tEHGL
tQVWPL
DC and AC parameters M28W640FCT, M28W640FCB
42/77
Table 18. Write AC characteristics, Chip enable controlled
Symbol Alt Parameter
M28W640FCT, M28W640FCB
Unit
70 85 90 10
tAVAV tWC Write Cycle Time Min 70 85 90 100 ns
tAVEH tAS
Address Valid to Chip Enable
High Min 45 45 50 50 ns
tDVEH tDS Data Valid to Chip Enable High Min 45 45 50 50 ns
tEHAX tAH
Chip Enable High to Address
Transition Min0000ns
tEHDX tDH
Chip Enable High to Data
Transition Min0000ns
tEHEL tCPH
Chip Enable High to Chip Enable
Low Min 25 25 30 30 ns
tEHGL
Chip Enable High to Output
Enable Low Min 25 25 30 30 ns
tEHWH tWH
Chip Enable High to Write Enable
High Min0000ns
tELEH tCP
Chip Enable Low to Chip Enable
High Min 45 45 50 50 ns
tELQV Chip Enable Low to Output Valid Min 70 85 90 100 ns
tQVVPL
(1)(2)
1. Sampled only, not 100% tested.
2. Applicable if VPP is seen as a logic input (VPP < 3.6V).
Output Valid to VPP Low Min0000ns
tQVWPL Data Valid to Write Protect Low Min 0 0 0 0 ns
tVPHEH (1) tVPS VPP High to Chip Enable High Min 200 200 200 200 ns
tWLEL tCS
Write Enable Low to Chip Enable
Low Min0000ns
tWPHEH
Write Protect High to Chip
Enable High Min 45 45 50 50 ns
M28W640FCT, M28W640FCB DC and AC parameters
43/77
Figure 11. Power-Up and Reset AC waveforms
Table 19. Power-Up and Reset AC characteristics
Symbol Parameter Test Condition
M28W640FCT,
M28W640FCB Unit
70 85 90 10
tPHWL
tPHEL
tPHGL
Reset High to Write Enable Low,
Chip Enable Low, Output Enable
Low
During
Program
and Erase
Min50505050µs
others Min 30 30 30 30 ns
tPLPH(1)(2)
1. The device Reset is possible but not guaranteed if tPLPH < 100ns
2. Sampled only, not 100% tested.
Reset Low to Reset High Min 100 100 100 100 ns
tVDHPH(3)
3. It is important to assert RP in order to allow proper CPU initialization during power up or reset.
Supply Voltages High to Reset
High Min50505050µs
AI03537b
tPHWL
tPHEL
tPHGL
RP
W, E, G
VDD, VDDQ
tVDHPH
tPHWL
tPHEL
tPHGL
tPLPH
Power-Up Reset
Package mechanical M28W640FCT, M28W640FCB
44/77
9 Package mechanical
Figure 12. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, package outline
1. Drawing is not to scale.
Table 20. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, package
mechanical data
Symbol
millimeters inches
Typ Min Max Typ Min Max
A 1.200 0.0472
A1 0.100 0.050 0.150 0.0039 0.0020 0.0059
A2 1.000 0.950 1.050 0.0394 0.0374 0.0413
B 0.220 0.170 0.270 0.0087 0.0067 0.0106
C 0.100 0.210 0.0039 0.0083
CP 0.100 0.0039
D1 12.000 11.900 12.100 0.4724 0.4685 0.4764
E 20.000 19.800 20.200 0.7874 0.7795 0.7953
E1 18.400 18.300 18.500 0.7244 0.7205 0.7283
e 0.500 – – 0.0197 – –
L 0.600 0.500 0.700 0.0236 0.0197 0.0276
L1 0.800 0.0315
α3° 0° 5° 3° 0° 5°
TSOP-G
B
e
DIE
C
LA1 α
E1
E
A
A2
1
24
48
25
D1
L1
CP
M28W640FCT, M28W640FCB Package mechanical
45/77
Figure 13. TFBGA48 6.39x10.5mm - 8x6 ball array, 0.75mm pitch, bottom view
package outline
1. Drawing is not to scale.
Table 21. TFBGA48 6.39x10.5mm - 8x6 ball array, 0.75mm pitch, package
mechanical data
Symbol
millimeters inches
Typ Min Max Typ Min Max
A 1.200 0.0472
A1 0.260 0.0102
A2 1.000 0.0394
b 0.400 0.350 0.450 0.0157 0.0138 0.0177
D 6.390 6.290 6.490 0.2516 0.2476 0.2555
D1 5.250 – – 0.2067 – –
ddd 0.100 0.0039
E 10.500 10.400 10.600 0.4134 0.4094 0.4173
E1 3.750 – – 0.1476 – –
e 0.750 – – 0.0295 – –
FD 0.570 – – 0.0224 – –
FE 3.375 – – 0.1329 – –
SD 0.375 – – 0.0148 – –
SE 0.375 – – 0.0148 – –
E1E
D1
D
A2
A1
A
BGA-Z34
ddd
e
e
SD
SE
b
FE
FD
BALL "A1"
Package mechanical M28W640FCT, M28W640FCB
46/77
Figure 14. TFBGA48 daisy chain - package connections (top view through package)
AI04390
C
B
A
87654321
E
D
F
M28W640FCT, M28W640FCB Package mechanical
47/77
Figure 15. TFBGA48 daisy chain - PCB connections proposal (top view through
package)
AI04391
C
B
A
87654321
E
D
F
START
POINT
END
POINT
Part numbering M28W640FCT, M28W640FCB
48/77
10 Part numbering
Table 22. Ordering information scheme
Example: M28W640FCT 90 N 6 E
Device type
M28
Operating voltage
W = VDD = 2.7V to 3.6V; VDDQ = 1.65V to 3.6V
Device function
640FC = 64 Mbit (4 Mb x16), Boot Block
Array matrix
T = Top Boot
B = Bottom Boot
Speed
70 = 70ns
85 = 85ns
90 = 90ns
10 = 100ns
Package
N = TSOP48: 12 x 20 mm
ZB = TFBGA48: 6.39 x 10.5mm, 0.75 mm pitch
Temperature range
1 = 0 to 70 °C
6 = –40 to 85 °C
Option
E = ECOPACK® Package, Standard Packing
F = ECOPACK® Package, Tape & Reel Packing
M28W640FCT, M28W640FCB Part numbering
49/77
1. Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of available
options (Speed, Package, etc.) or for further information on any aspect of this device, please contact the
Numonyx Sales Office nearest to you.
Table 23. Daisy Chain ordering scheme
Example: M28W640FC -ZB T
Device type
M28W640FC
Daisy chain
-ZB = TFBGA48: 6.39 x 10.5mm, 0.75 mm pitch
Option
E = ECOPACK® Package, Standard Packing
F = ECOPACK® Package, Tape & Reel Packing, 24mm
Block address tables M28W640FCT, M28W640FCB
50/77
Appendix A Block address tables
Table 24. Top Boot Block Addresses, M28W640FCT
# Size (KWord) Address range
0 4 3FF000-3FFFFF
1 4 3FE000-3FEFFF
2 4 3FD000-3FDFFF
3 4 3FC000-3FCFFF
4 4 3FB000-3FBFFF
5 4 3FA000-3FAFFF
6 4 3F9000-3F9FFF
7 4 3F8000-3F8FFF
8 32 3F0000-3F7FFF
9 32 3E8000-3EFFFF
10 32 3E0000-3E7FFF
11 32 3D8000-3DFFFF
12 32 3D0000-3D7FFF
13 32 3C8000-3CFFFF
14 32 3C0000-3C7FFF
15 32 3B8000-3BFFFF
16 32 3B0000-3B7FFF
17 32 3A8000-3AFFFF
18 32 3A0000-3A7FFF
19 32 398000-39FFFF
20 32 390000-397FFF
21 32 388000-38FFFF
22 32 380000-387FFF
23 32 378000-37FFFF
24 32 370000-377FFF
25 32 368000-36FFFF
26 32 360000-367FFF
27 32 358000-35FFFF
28 32 350000-357FFF
29 32 348000-34FFFF
30 32 340000-347FFF
31 32 338000-33FFFF
M28W640FCT, M28W640FCB Block address tables
51/77
32 32 330000-337FFF
33 32 328000-32FFFF
34 32 320000-327FFF
35 32 318000-31FFFF
36 32 310000-317FFF
37 32 308000-30FFFF
38 32 300000-307FFF
39 32 2F8000-2FFFFF
40 32 2F0000-2F7FFF
41 32 2E8000-2EFFFF
42 32 2E0000-2E7FFF
43 32 2D8000-2DFFFF
44 32 2D0000-2D7FFF
45 32 2C8000-2CFFFF
46 32 2C0000-2C7FFF
47 32 2B8000-2BFFFF
48 32 2B0000-2B7FFF
49 32 2A8000-2AFFFF
50 32 2A0000-2A7FFF
51 32 298000-29FFFF
52 32 290000-297FFF
53 32 288000-28FFFF
54 32 280000-287FFF
55 32 278000-27FFFF
56 32 270000-277FFF
57 32 268000-26FFFF
58 32 260000-267FFF
59 32 258000-25FFFF
60 32 250000-257FFF
61 32 248000-24FFFF
62 32 240000-247FFF
63 32 238000-23FFFF
64 32 230000-237FFF
65 32 228000-22FFFF
66 32 220000-227FFF
Table 24. Top Boot Block Addresses, M28W640FCT (continued)
# Size (KWord) Address range
Block address tables M28W640FCT, M28W640FCB
52/77
67 32 218000-21FFFF
68 32 210000-217FFF
69 32 208000-20FFFF
70 32 200000-207FFF
71 32 1F8000-1FFFFF
72 32 1F0000-1F7FFF
73 32 1E8000-1EFFFF
74 32 1E0000-1E7FFF
75 32 1D8000-1DFFFF
76 32 1D0000-1D7FFF
77 32 1C8000-1CFFFF
78 32 1C0000-1C7FFF
79 32 1B8000-1BFFFF
80 32 1B0000-1B7FFF
81 32 1A8000-1AFFFF
82 32 1A0000-1A7FFF
83 32 198000-19FFFF
84 32 190000-197FFF
85 32 188000-18FFFF
86 32 180000-187FFF
87 32 178000-17FFFF
88 32 170000-177FFF
89 32 168000-16FFFF
90 32 160000-167FFF
91 32 158000-15FFFF
92 32 150000-157FFF
93 32 148000-14FFFF
94 32 140000-147FFF
95 32 138000-13FFFF
96 32 130000-137FFF
97 32 128000-12FFFF
98 32 120000-127FFF
99 32 118000-11FFFF
100 32 110000-117FFF
101 32 108000-10FFFF
Table 24. Top Boot Block Addresses, M28W640FCT (continued)
# Size (KWord) Address range
M28W640FCT, M28W640FCB Block address tables
53/77
102 32 100000-107FFF
103 32 0F8000-0FFFFF
104 32 0F0000-0F7FFF
105 32 0E8000-0EFFFF
106 32 0E0000-0E7FFF
107 32 0D8000-0DFFFF
108 32 0D0000-0D7FFF
109 32 0C8000-0CFFFF
110 32 0C0000-0C7FFF
111 32 0B8000-0BFFFF
112 32 0B0000-0B7FFF
113 32 0A8000-0AFFFF
114 32 0A0000-0A7FFF
115 32 098000-09FFFF
116 32 090000-097FFF
117 32 088000-08FFFF
118 32 080000-087FFF
119 32 078000-07FFFF
120 32 070000-077FFF
121 32 068000-06FFFF
122 32 060000-067FFF
123 32 058000-05FFFF
124 32 050000-057FFF
125 32 048000-04FFFF
126 32 040000-047FFF
127 32 038000-03FFFF
128 32 030000-037FFF
129 32 028000-02FFFF
130 32 020000-027FFF
131 32 018000-01FFFF
132 32 010000-017FFF
133 32 008000-00FFFF
134 32 000000-007FFF
Table 24. Top Boot Block Addresses, M28W640FCT (continued)
# Size (KWord) Address range
Block address tables M28W640FCT, M28W640FCB
54/77
Table 25. Bottom Boot Block Addresses, M28W640FCB
#Size (KWord) Address Range
134 32 3F8000-3FFFFF
133 32 3F0000-3F7FFF
132 32 3E8000-3EFFFF
131 32 3E0000-3E7FFF
130 32 3D8000-3DFFFF
129 32 3D0000-3D7FFF
128 32 3C8000-3CFFFF
127 32 3C0000-3C7FFF
126 32 3B8000-3BFFFF
125 32 3B0000-3B7FFF
124 32 3A8000-3AFFFF
123 32 3A0000-3A7FFF
122 32 398000-39FFFF
121 32 390000-397FFF
120 32 388000-38FFFF
119 32 380000-387FFF
118 32 378000-37FFFF
117 32 370000-377FFF
116 32 368000-36FFFF
115 32 360000-367FFF
114 32 358000-35FFFF
113 32 350000-357FFF
112 32 348000-34FFFF
111 32 340000-347FFF
110 32 338000-33FFFF
109 32 330000-337FFF
108 32 328000-32FFFF
107 32 320000-327FFF
106 32 318000-31FFFF
105 32 310000-317FFF
104 32 308000-30FFFF
103 32 300000-307FFF
102 32 2F8000-2FFFFF
101 32 2F0000-2F7FFF
100 32 2E8000-2EFFFF
M28W640FCT, M28W640FCB Block address tables
55/77
99 32 2E0000-2E7FFF
98 32 2D8000-2DFFFF
97 32 2D0000-2D7FFF
96 32 2C8000-2CFFFF
95 32 2C0000-2C7FFF
94 32 2B8000-2BFFFF
93 32 2B0000-2B7FFF
92 32 2A8000-2AFFFF
91 32 2A0000-2A7FFF
90 32 298000-29FFFF
89 32 290000-297FFF
88 32 288000-28FFFF
87 32 280000-287FFF
86 32 278000-27FFFF
85 32 270000-277FFF
84 32 268000-26FFFF
83 32 260000-267FFF
82 32 258000-25FFFF
81 32 250000-257FFF
80 32 248000-24FFFF
79 32 240000-247FFF
78 32 238000-23FFFF
77 32 230000-237FFF
76 32 228000-22FFFF
75 32 220000-227FFF
74 32 218000-21FFFF
73 32 210000-217FFF
72 32 208000-20FFFF
71 32 200000-207FFF
70 32 1F8000-1FFFFF
69 32 1F0000-1F7FFF
68 32 1E8000-1EFFFF
67 32 1E0000-1E7FFF
66 32 1D8000-1DFFFF
65 32 1D0000-1D7FFF
Table 25. Bottom Boot Block Addresses, M28W640FCB (continued)
#Size (KWord) Address Range
Block address tables M28W640FCT, M28W640FCB
56/77
64 32 1C8000-1CFFFF
63 32 1C0000-1C7FFF
62 32 1B8000-1BFFFF
61 32 1B0000-1B7FFF
60 32 1A8000-1AFFFF
59 32 1A0000-1A7FFF
58 32 198000-19FFFF
57 32 190000-197FFF
56 32 188000-18FFFF
55 32 180000-187FFF
54 32 178000-17FFFF
53 32 170000-177FFF
52 32 168000-16FFFF
51 32 160000-167FFF
50 32 158000-15FFFF
49 32 150000-157FFF
48 32 148000-14FFFF
47 32 140000-147FFF
46 32 138000-13FFFF
45 32 130000-137FFF
44 32 128000-12FFFF
43 32 120000-127FFF
42 32 118000-11FFFF
41 32 110000-117FFF
40 32 108000-10FFFF
39 32 100000-107FFF
38 32 0F8000-0FFFFF
37 32 0F0000-0F7FFF
36 32 0E8000-0EFFFF
35 32 0E0000-0E7FFF
34 32 0D8000-0DFFFF
33 32 0D0000-0D7FFF
32 32 0C8000-0CFFFF
31 32 0C0000-0C7FFF
30 32 0B8000-0BFFFF
Table 25. Bottom Boot Block Addresses, M28W640FCB (continued)
#Size (KWord) Address Range
M28W640FCT, M28W640FCB Block address tables
57/77
29 32 0B0000-0B7FFF
28 32 0A8000-0AFFFF
27 32 0A0000-0A7FFF
26 32 098000-09FFFF
25 32 090000-097FFF
24 32 088000-08FFFF
23 32 080000-087FFF
22 32 078000-07FFFF
21 32 070000-077FFF
20 32 068000-06FFFF
19 32 060000-067FFF
18 32 058000-05FFFF
17 32 050000-057FFF
16 32 048000-04FFFF
15 32 040000-047FFF
14 32 038000-03FFFF
13 32 030000-037FFF
12 32 028000-02FFFF
11 32 020000-027FFF
10 32 018000-01FFFF
9 32 010000-017FFF
8 32 008000-00FFFF
7 4 007000-007FFF
6 4 006000-006FFF
5 4 005000-005FFF
4 4 004000-004FFF
3 4 003000-003FFF
2 4 002000-002FFF
1 4 001000-001FFF
0 4 000000-000FFF
Table 25. Bottom Boot Block Addresses, M28W640FCB (continued)
#Size (KWord) Address Range
Common Flash Interface (CFI) M28W640FCT, M28W640FCB
58/77
Appendix B Common Flash Interface (CFI)
The Common Flash Interface is a JEDEC approved, standardized data structure that can be
read from the Flash memory device. It allows a system software to query the device to
determine various electrical and timing parameters, density information and functions
supported by the memory. The system can interface easily with the device, enabling the
software to upgrade itself when necessary.
When the CFI Query Command (RCFI) is issued the device enters CFI Query mode and the
data structure is read from the memory. Tables 26, 27, 28, 29, 30 and 31 show the
addresses used to retrieve the data.
The CFI data structure also contains a security area where a 64 bit unique security number
is written (see Table 31: Security code area). This area can be accessed only in Read mode
by the final user. It is impossible to change the security number after it has been written by
Numonyx. Issue a Read command to return to Read mode.
Table 26. Query Structure Overview(1)
1. Query data are always presented on the lowest order data outputs.
Offset Sub-section Name Description
00h Reserved Reserved for algorithm-specific information
10h CFI Query Identification String Command set ID and algorithm data offset
1Bh System Interface Information Device timing & voltage information
27h Device Geometry Definition Flash device layout
PPrimary Algorithm-specific Extended Query
table
Additional information specific to the
Primary Algorithm (optional)
AAlternate Algorithm-specific Extended
Query table
Additional information specific to the
Alternate Algorithm (optional)
M28W640FCT, M28W640FCB Common Flash Interface (CFI)
59/77
Table 27. CFI Query Identification String(1)
1. Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘0’.
Offset Data Description Value
00h 0020h Manufacturer code Numonyx
01h 8848h
8849h Device code To p
Bottom
02h-0Fh reserved Reserved
10h 0051h "Q"
11h 0052h Query Unique ASCII String "QRY" "R"
12h 0059h "Y"
13h 0003h Primary Algorithm Command Set and Control Interface ID code 16
bit ID code defining a specific algorithm
Intel
compatibl
e
14h 0000h
15h 0035h Address for Primary Algorithm extended Query table (see Ta b l e 2 9 )P = 35h
16h 0000h
17h 0000h Alternate Vendor Command Set and Control Interface ID code
second vendor - specified algorithm supported (0000h means none
exists)
NA
18h 0000h
19h 0000h Address for Alternate Algorithm extended Query table
(0000h means none exists) NA
1Ah 0000h
Common Flash Interface (CFI) M28W640FCT, M28W640FCB
60/77
Table 28. CFI Query System Interface Information
Offset Data Description Value
1Bh 0027h
VDD Logic Supply Minimum Program/Erase or Write voltage
bit 7 to 4BCD value in volts
bit 3 to 0BCD value in 100 mV
2.7V
1Ch 0036h
VDD Logic Supply Maximum Program/Erase or Write voltage
bit 7 to 4BCD value in volts
bit 3 to 0BCD value in 100 mV
3.6V
1Dh 00B4h
VPP [Programming] Supply Minimum Program/Erase voltage
bit 7 to 4HEX value in volts
bit 3 to 0BCD value in 100 mV
11.4V
1Eh 00C6h
VPP [Programming] Supply Maximum Program/Erase voltage
bit 7 to 4HEX value in volts
bit 3 to 0BCD value in 100 mV
12.6V
1Fh 0004h Typical time-out per single word program = 2n µs 16µs
20h 0004h Typical time-out for Double/Quadruple Word Program = 2n µs 16µs
21h 000Ah Typical time-out per individual block erase = 2n ms 1s
22h 0000h Typical time-out for full chip erase = 2n ms NA
23h 0005h Maximum time-out for Word program = 2n times typical 512µs
24h 0005h Maximum time-out for Double/Quadruple Word Program = 2n times
typical 512µs
25h 0003h Maximum time-out per individual block erase = 2n times typical 8s
26h 0000h Maximum time-out for chip erase = 2n times typical NA
M28W640FCT, M28W640FCB Common Flash Interface (CFI)
61/77
Table 29. Device Geometry Definition
Offset
Word
Mode
Data Description Value
27h 0017h Device size = 2n in number of bytes 8 Mbyte
28h
29h
0001h
0000h Flash Device Interface code description x16
Async.
2Ah
2Bh
0003h
0000h Maximum number of bytes in multi-byte program or page = 2n 8
2Ch 0002h
Number of Erase Block Regions within the device.
It specifies the number of regions within the device containing
contiguous Erase Blocks of the same size.
2
M28W640FCT
2Dh
2Eh
007Eh
0000h
Region 1 Information
Number of identical-size erase block = 007Eh+1 127
2Fh
30h
0000h
0001h
Region 1 Information
Block size in Region 1 = 0100h * 256 byte 64 Kbyte
31h
32h
0007h
0000h
Region 2 Information
Number of identical-size erase block = 0007h+1 8
33h
34h
0020h
0000h
Region 2 Information
Block size in Region 2 = 0020h * 256 byte 8 Kbyte
M28W640FCB
2Dh
2Eh
0007h
0000h
Region 1 Information
Number of identical-size erase block = 0007h+1 8
2Fh
30h
0020h
0000h
Region 1 Information
Block size in Region 1 = 0020h * 256 byte 8 Kbyte
31h
32h
007Eh
0000h
Region 2 Information
Number of identical-size erase block = 007Eh=1 127
33h
34h
0000h
0001h
Region 2 Information
Block size in Region 2 = 0100h * 256 byte 64 Kbyte
Common Flash Interface (CFI) M28W640FCT, M28W640FCB
62/77
Table 30. Primary Algorithm-specific Extended Query table
Offset
P = 35h (1) Data Description Value
(P+0)h = 35h 0050h
Primary Algorithm extended Query table unique ASCII string
“PRI”
"P"
(P+1)h = 36h 0052h "R"
(P+2)h = 37h 0049h "I"
(P+3)h = 38h 0031h Major version number, ASCII "1"
(P+4)h = 39h 0030h Minor version number, ASCII "0"
(P+5)h = 3Ah 0066h Extended Query table contents for Primary Algorithm. Address
(P+5)h contains less significant byte.
bit 0Chip Erase supported(1 = Yes, 0 = No)
bit 1Suspend Erase supported(1 = Yes, 0 = No)
bit 2Suspend Program supported(1 = Yes, 0 = No)
bit 3Legacy Lock/Unlock supported(1 = Yes, 0 = No)
bit 4Queued Erase supported(1 = Yes, 0 = No)
bit 5Instant individual block locking supported(1 = Yes, 0 = No)
bit 6Protection bits supported(1 = Yes, 0 = No)
bit 7Page mode read supported(1 = Yes, 0 = No)
bit 8Synchronous read supported(1 = Yes, 0 = No)
bit 31 to 9Reserved; undefined bits are ‘0’
No
Ye s
Ye s
No
No
Ye s
Ye s
No
No
(P+6)h = 3Bh 0000h
(P+7)h = 3Ch 0000h
(P+8)h = 3Dh 0000h
(P+9)h = 3Eh 0001h
Supported Functions after Suspend
Read Array, Read Status Register and CFI Query are always
supported during Erase or Program operation
bit 0Program supported after Erase Suspend (1 = Yes, 0 = No)
bit 7 to 1Reserved; undefined bits are ‘0’ Ye s
(P+A)h = 3Fh 0003h Block Lock Status
Defines which bits in the Block Status Register section of the
Query are implemented.
Address (P+A)h contains less significant byte
bit 0Block Lock Status Register Lock/Unlock bit active(1 = Yes, 0
= No)
bit 1Block Lock Status Register Lock-Down bit active (1 = Yes, 0
= No)
bit 15 to 2Reserved for future use; undefined bits are ‘0’
Ye s
Ye s
(P+B)h = 40h 0000h
(P+C)h = 41h 0030h
VDD Logic Supply Optimum Program/Erase voltage (highest
performance)
bit 7 to 4HEX value in volts
bit 3 to 0BCD value in 100 mV
3V
(P+D)h = 42h 00C0h
VPP Supply Optimum Program/Erase voltage
bit 7 to 4HEX value in volts
bit 3 to 0BCD value in 100 mV
12V
(P+E)h = 43h 0001h Number of Protection register fields in JEDEC ID space.
"00h," indicates that 256 protection bytes are available 01
M28W640FCT, M28W640FCB Common Flash Interface (CFI)
63/77
(P+F)h = 44h 0080h Protection Field 1: Protection Description
This field describes user-available One Time Programmable
(OTP) Protection register bytes. Some are pre-programmed with
device unique serial numbers. Others are user programmable.
bits 0–15 point to the Protection register Lock byte, the section’s
first byte.
The following bytes are factory pre-programmed and user-
programmable.
bit 0 to 7 Lock/bytes JEDEC-plane physical low address
bit 8 to 15Lock/bytes JEDEC-plane physical high address
bit 16 to 23 "n" such that 2n = factory pre-programmed bytes
bit 24 to 31 "n" such that 2n = user programmable bytes
80h
(P+10)h =
45h 0000h 00h
(P+11)h =
46h 0003h 8 byte
(P+12)h =
47h 0004h 16 byte
(P+13)h =
48h Reserved
1. See Table 27, offset 15 for P pointer definition
Table 31. Security code area
Offset Data Description
80h 00XX Protection Register Lock
81h XXXX
64 bits: unique device number
82h XXXX
83h XXXX
84h XXXX
85h XXXX
128 bits: User Programmable OTP
86h XXXX
87h XXXX
88h XXXX
89h XXXX
8Ah XXXX
8Bh XXXX
8Ch XXXX
Table 30. Primary Algorithm-specific Extended Query table (continued)
Offset
P = 35h (1) Data Description Value
Flowcharts and pseudo codes M28W640FCT, M28W640FCB
64/77
Appendix C Flowcharts and pseudo codes
Figure 16. Program flowchart and pseudo code
1. Status check of b1 (Protected Block), b3 (VPP Invalid) and b4 (Program Error) can be made after each program operation
or after a sequence.
2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.
Write 40h or 10h
AI03538b
Start
Write Address
& Data
Read Status
Register
YES
NO
b7 = 1
YES
NO
b3 = 0
NO
b4 = 0
VPP Invalid
Error (1, 2)
Program
Error (1, 2)
program_command (addressToProgram, dataToProgram) {:
writeToFlash (any_address, 0x40) ;
/*or writeToFlash (any_address, 0x10) ; */
do {
status_register=readFlash (any_address) ;
/* E or G must be toggled*/
} while (status_register.b7== 0) ;
if (status_register.b3==1) /*VPP invalid error */
error_handler ( ) ;
YES
End
YES
NO
b1 = 0 Program to Protected
Block Error (1, 2)
writeToFlash (addressToProgram, dataToProgram) ;
/*Memory enters read status state after
the Program Command*/
if (status_register.b4==1) /*program error */
error_handler ( ) ;
if (status_register.b1==1) /*program to protect block error */
error_handler ( ) ;
}
M28W640FCT, M28W640FCB Flowcharts and pseudo codes
65/77
Figure 17. Double Word Program flowchart and pseudo code
1. Status check of b1 (Protected Block), b3 (VPP Invalid) and b4 (Program Error) can be made after each program operation
or after a sequence.
2. If an error is found, the Status Register must be cleared before further Program/Erase operations.
3. Address 1 and Address 2 must be consecutive addresses differing only for bit A0.
Write 30h
AI03539b
Start
Write Address 1
& Data 1 (3)
Read Status
Register
YES
NO
b7 = 1
YES
NO
b3 = 0
NO
b4 = 0
VPP Invalid
Error (1, 2)
Program
Error (1, 2)
YES
End
YES
NO
b1 = 0 Program to Protected
Block Error (1, 2)
Write Address 2
& Data 2 (3)
double_word_program_command (addressToProgram1, dataToProgram1,
addressToProgram2, dataToProgram2)
{
writeToFlash (any_address, 0x30) ;
writeToFlash (addressToProgram1, dataToProgram1) ;
/*see note (3) */
writeToFlash (addressToProgram2, dataToProgram2) ;
/*see note (3) */
/*Memory enters read status state after
the Program command*/
do {
status_register=readFlash (any_address) ;
/* E or G must be toggled*/
} while (status_register.b7== 0) ;
if (status_register.b3==1) /*VPP invalid error */
error_handler ( ) ;
if (status_register.b4==1) /*program error */
error_handler ( ) ;
if (status_register.b1==1) /*program to protect block error */
error_handler ( ) ;
}
Flowcharts and pseudo codes M28W640FCT, M28W640FCB
66/77
Figure 18. Quadruple Word Program flowchart and pseudo code
1. Status check of b1 (Protected Block), b3 (VPP Invalid) and b4 (Program Error) can be made after each program operation
or after a sequence.
2. If an error is found, the Status Register must be cleared before further Program/Erase operations.
3. Address 1 to Address 4 must be consecutive addresses differing only for bits A0 and A1.
Write 56h
AI06233
Start
Write Address 1
& Data 1 (3)
Read Status
Register
YES
NO
b7 = 1
YES
NO
b3 = 0
NO
b4 = 0
VPP Invalid
Error (1, 2)
Program
Error (1, 2)
YES
End
YES
NO
b1 = 0 Program to Protected
Block Error (1, 2)
Write Address 2
& Data 2 (3)
quadruple_word_program_command (addressToProgram1, dataToProgram1,
addressToProgram2, dataToProgram2,
addressToProgram3, dataToProgram3,
addressToProgram4, dataToProgram4)
{
writeToFlash (any_address, 0x56) ;
writeToFlash (addressToProgram1, dataToProgram1) ;
/*see note (3) */
writeToFlash (addressToProgram2, dataToProgram2) ;
/*see note (3) */
writeToFlash (addressToProgram3, dataToProgram3) ;
/*see note (3) */
writeToFlash (addressToProgram4, dataToProgram4) ;
/*see note (3) */
/*Memory enters read status state after
the Program command*/
do {
status_register=readFlash (any_address) ;
/* E or G must be toggled*/
} while (status_register.b7== 0) ;
if (status_register.b3==1) /*VPP invalid error */
error_handler ( ) ;
if (status_register.b4==1) /*program error */
error_handler ( ) ;
if (status_register.b1==1) /*program to protect block error */
error_handler ( ) ;
}
Write Address 3
& Data 3 (3)
Write Address 4
& Data 4 (3)
M28W640FCT, M28W640FCB Flowcharts and pseudo codes
67/77
Figure 19. Program Suspend & Resume flowchart and pseudo code
Write 70h
AI03540b
Read Status
Register
YES
NO
b7 = 1
YES
NO
b2 = 1
Program Continues
Write D0h
Read data from
another address
Start
Write B0h
Program Complete
Write FFh
Read Data
program_suspend_command ( ) {
writeToFlash (any_address, 0xB0) ;
writeToFlash (any_address, 0x70) ;
/* read status register to check if
program has already completed */
do {
status_register=readFlash (any_address) ;
/* E or G must be toggled*/
} while (status_register.b7== 0) ;
if (status_register.b2==0) /*program completed */
{ writeToFlash (any_address, 0xFF) ;
read_data ( ) ; /*read data from another block*/
/*The device returns to Read Array
(as if program/erase suspend was not issued).*/
}
else
{ writeToFlash (any_address, 0xFF) ;
read_data ( ); /*read data from another address*/
writeToFlash (any_address, 0xD0) ;
/*write 0xD0 to resume program*/
}
}
Write FFh
Flowcharts and pseudo codes M28W640FCT, M28W640FCB
68/77
Figure 20. Erase flowchart and pseudo code
1. If an error is found, the Status Register must be cleared before further Program/Erase operations.
Write 20h
AI03541b
Start
Write Block
Address & D0h
Read Status
Register
YES
NO
b7 = 1
YES
NO
b3 = 0
YES
b4, b5 = 1
VPP Invalid
Error (1)
Command
Sequence Error (1)
NO
NO
b5 = 0 Erase Error (1)
End
YES
NO
b1 = 0 Erase to Protected
Block Error (1)
YES
erase_command ( blockToErase ) {
writeToFlash (any_address, 0x20) ;
writeToFlash (blockToErase, 0xD0) ;
/* only A12-A20 are significannt */
/* Memory enters read status state after
the Erase Command */
} while (status_register.b7== 0) ;
do {
status_register=readFlash (any_address) ;
/* E or G must be toggled*/
if (status_register.b3==1) /*VPP invalid error */
error_handler ( ) ;
if ( (status_register.b4==1) && (status_register.b5==1) )
/* command sequence error */
error_handler ( ) ;
if (status_register.b1==1) /*program to protect block error */
error_handler ( ) ;
if ( (status_register.b5==1) )
/* erase error */
error_handler ( ) ;
}
M28W640FCT, M28W640FCB Flowcharts and pseudo codes
69/77
Figure 21. Erase Suspend & Resume flowchart and pseudo code
Write 70h
AI03542b
Read Status
Register
YES
NO
b7 = 1
YES
NO
b6 = 1
Erase Continues
Write D0h
Read data from
another block
or
Program/Protection Program
or
Block Protect/Unprotect/Lock
Start
Write B0h
Erase Complete
Write FFh
Read Data
Write FFh
erase_suspend_command ( ) {
writeToFlash (any_address, 0xB0) ;
writeToFlash (any_address, 0x70) ;
/* read status register to check if
erase has already completed */
do {
status_register=readFlash (any_address) ;
/* E or G must be toggled*/
} while (status_register.b7== 0) ;
if (status_register.b6==0) /*erase completed */
{ writeToFlash (any_address, 0xFF) ;
read_data ( ) ;
/*read data from another block*/
/*The device returns to Read Array
(as if program/erase suspend was not issued).*/
}
else
{ writeToFlash (any_address, 0xFF) ;
read_program_data ( );
/*read or program data from another address*/
writeToFlash (any_address, 0xD0) ;
/*write 0xD0 to resume erase*/
}
}
Flowcharts and pseudo codes M28W640FCT, M28W640FCB
70/77
Figure 22. Locking Operations flowchart and pseudo code
Write
01h, D0h or 2Fh
AI04364
Read Block
Lock States
YES
NO
Locking
change
confirmed?
Start
Write 60h locking_operation_command (address, lock_operation) {
writeToFlash (any_address, 0x60) ; /*configuration setup*/
if (readFlash (address) ! = locking_state_expected)
error_handler () ;
/*Check the locking state (see Read Block Signature table )*/
writeToFlash (any_address, 0xFF) ; /*Reset to Read Array mode*/
}
Write FFh
Write 90h
End
if (lock_operation==LOCK) /*to protect the block*/
writeToFlash (address, 0x01) ;
else if (lock_operation==UNLOCK) /*to unprotect the block*/
writeToFlash (address, 0xD0) ;
else if (lock_operation==LOCK-DOWN) /*to lock the block*/
writeToFlash (address, 0x2F) ;
writeToFlash (any_address, 0x90) ;
M28W640FCT, M28W640FCB Flowcharts and pseudo codes
71/77
Figure 23. Protection Register Program flowchart and pseudo code
1. Status check of b1 (Protected Block), b3 (VPP Invalid) and b4 (Program Error) can be made after each program operation
or after a sequence.
2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.
Write C0h
AI04381
Start
Write Address
& Data
Read Status
Register
YES
NO
b7 = 1
YES
NO
b3 = 0
NO
b4 = 0
VPP Invalid
Error (1, 2)
Program
Error (1, 2)
protection_register_program_command (addressToProgram, dataToProgram) {:
writeToFlash (any_address, 0xC0) ;
do {
status_register=readFlash (any_address) ;
/* E or G must be toggled*/
} while (status_register.b7== 0) ;
if (status_register.b3==1) /*VPP invalid error */
error_handler ( ) ;
YES
End
YES
NO
b1 = 0 Program to Protected
Block Error (1, 2)
writeToFlash (addressToProgram, dataToProgram) ;
/*Memory enters read status state after
the Program Command*/
if (status_register.b4==1) /*program error */
error_handler ( ) ;
if (status_register.b1==1) /*program to protect block error */
error_handler ( ) ;
}
Command Interface and Program/Erase Controller State M28W640FCT, M28W640FCB
72/77
Appendix D Command Interface and Program/Erase
Controller State
.
Table 32. Write State machine Current/Next(1)
Current
State
SR
bit
7
Data When
Read
Command Input (and Next State)
Read
Array
(FFh)
Program
Setup
(10/40h)
Erase
Setup
(20h)
Erase
Confirm
(D0h)
Prog/Ers
Suspend
(B0h)
Prog/Ers
Resume
(D0h)
Read
Status
(70h)
Clear
Status
(50h)
Read Array “1” Array Read
Array Prog.Setup Ers.
Setup Read Array Read
Sts.
Read
Array
Read
Status “1” Status Read
Array
Program
Setup
Erase
Setup Read Array Read
Status
Read
Array
Read
Elect.Sg. “1” Electronic
Signature
Read
Array
Program
Setup
Erase
Setup Read Array Read
Status
Read
Array
Read CFI
Query “1” CFI Read
Array
Program
Setup
Erase
Setup Read Array Read
Status
Read
Array
Lock Setup “1” Status Lock Command Error Lock
(complete)
Lock Cmd
Error
Lock
(complete)
Lock Command
Error
Lock Cmd
Error “1” Status Read
Array
Program
Setup
Erase
Setup Read Array Read
Status
Read
Array
Lock
(complete) “1” Status Read
Array
Program
Setup
Erase
Setup Read Array Read
Status
Read
Array
Prot. Prog.
Setup “1” Status Protection Register Program
Prot. Prog.
(continue) “0” Status Protection Register Program continue
Prot. Prog.
(complete) “1” Status Read
Array
Program
Setup
Erase
Setup Read Array Read
Status
Read
Array
Prog.
Setup “1” Status Program
Program
(continue) “0” Status Program (continue) Prog. Sus
Read Sts Program (continue)
Prog. Sus
Status “1” Status
Prog.
Sus
Read
Array
Program Suspend to
Read Array
Program
(continue)
Prog. Sus
Read
Array
Program
(continue)
Prog.
Sus
Read
Sts
Prog.
Sus
Read
Array
Prog. Sus
Read Array “1” Array
Prog.
Sus
Read
Array
Program Suspend to
Read Array
Program
(continue)
Prog. Sus
Read
Array
Program
(continue)
Prog.
Sus
Read
Sts
Prog.
Sus
Read
Array
Prog. Sus
Read
Elect.Sg.
“1” Electronic
Signature
Prog.
Sus
Read
Array
Program Suspend to
Read Array
Program
(continue)
Prog. Sus
Read
Array
Program
(continue)
Prog.
Sus
Read
Sts
Prog.
Sus
Read
Array
M28W640FCT, M28W640FCB Command Interface and Program/Erase Controller State
73/77
Prog. Sus
Read CFI “1” CFI
Prog.
Sus
Read
Array
Program Suspend to
Read Array
Program
(continue)
Prog. Sus
Read
Array
Program
(continue)
Prog.
Sus
Read
Sts
Prog.
Sus
Read
Array
Program
(complete) “1” Status Read
Array
Program
Setup
Erase
Setup Read Array Read
Status
Read
Array
Erase
Setup “1” Status Erase Command Error Erase
(continue)
Erase
CmdError
Erase
(continue)
Erase Command
Error
Erase
Cmd.Error “1” Status Read
Array
Program
Setup
Erase
Setup Read Array Read
Status
Read
Array
Erase
(continue) “0” Status Erase (continue) Erase Sus
Read Sts Erase (continue)
Erase Sus
Read Sts “1” Status
Erase
Sus
Read
Array
Program
Setup
Erase
Sus
Read
Array
Erase
(continue)
Erase Sus
Read
Array
Erase
(continue)
Erase
Sus
Read
Sts
Erase
Sus
Read
Array
Erase Sus
Read Array “1” Array
Erase
Sus
Read
Array
Program
Setup
Erase
Sus
Read
Array
Erase
(continue)
Erase Sus
Read
Array
Erase
(continue)
Erase
Sus
Read
Sts
Erase
Sus
Read
Array
Erase Sus
Read
Elect.Sg.
“1” Electronic
Signature
Erase
Sus
Read
Array
Program
Setup
Erase
Sus
Read
Array
Erase
(continue)
Erase Sus
Read
Array
Erase
(continue)
Erase
Sus
Read
Sts
Erase
Sus
Read
Array
Erase Sus
Read CFI “1” CFI
Erase
Sus
Read
Array
Program
Setup
Erase
Sus
Read
Array
Erase
(continue)
Erase Sus
Read
Array
Erase
(continue)
Erase
Sus
Read
Sts
Erase
Sus
Read
Array
Erase
(complete) “1” Status Read
Array
Program
Setup
Erase
Setup Read Array Read
Status
Read
Array
1. Cmd = Command, Elect.Sg. = Electronic Signature, Ers = Erase, Prog. = Program, Prot = Protection, Sus = Suspend.
Table 32. Write State machine Current/Next(1) (continued)
Current
State
SR
bit
7
Data When
Read
Command Input (and Next State)
Read
Array
(FFh)
Program
Setup
(10/40h)
Erase
Setup
(20h)
Erase
Confirm
(D0h)
Prog/Ers
Suspend
(B0h)
Prog/Ers
Resume
(D0h)
Read
Status
(70h)
Clear
Status
(50h)
Command Interface and Program/Erase Controller State M28W640FCT, M28W640FCB
74/77
.
Table 33. Write State machine Current/Next(1)
Current
State
Command Input (and Next State)
Read
Elect.Sg.
(90h)
Read CFI
Query
(98h)
Lock
Setup
(60h)
Prot.
Prog.
Setup
(C0h)
Lock
Confirm
(01h)
Lock
Down
Confirm
(2Fh)
Unlock
Confirm
(D0h)
Read Array Read
Elect.Sg.
Read CFI
Query Lock Setup Prot. Prog.
Setup Read Array
Read
Status
Read
Elect.Sg.
Read CFI
Query Lock Setup Prot. Prog.
Setup Read Array
Read
Elect.Sg.
Read
Elect.Sg.
Read CFI
Query Lock Setup Prot. Prog.
Setup Read Array
Read CFI
Query
Read
Elect.Sg.
Read CFI
Query Lock Setup Prot. Prog.
Setup Read Array
Lock Setup Lock Command Error Lock (complete)
Lock Cmd
Error
Read
Elect.Sg.
Read CFI
Query Lock Setup Prot. Prog.
Setup Read Array
Lock
(complete)
Read
Elect.Sg.
Read CFI
Query Lock Setup Prot. Prog.
Setup Read Array
Prot. Prog.
Setup Protection Register Program
Prot. Prog.
(continue) Protection Register Program (continue)
Prot. Prog.
(complete)
Read
Elect.Sg.
Read CFI
Query Lock Setup Prot. Prog.
Setup Read Array
Prog.
Setup Program
Program
(continue) Program (continue)
Prog.
Suspend
Read
Status
Prog.
Suspend
Read
Elect.Sg.
Prog.
Suspend
Read CFI
Query
Program Suspend Read Array Program
(continue)
Prog.
Suspend
Read Array
Prog.
Suspend
Read
Elect.Sg.
Prog.
Suspend
Read CFI
Query
Program Suspend Read Array Program
(continue)
Prog.
Suspend
Read
Elect.Sg.
Prog.
Suspend
Read
Elect.Sg.
Prog.
Suspend
Read CFI
Query
Program Suspend Read Array Program
(continue)
Prog.
Suspend
Read CFI
Prog.
Suspend
Read
Elect.Sg.
Prog.
Suspend
Read CFI
Query
Program Suspend Read Array Program
(continue)
M28W640FCT, M28W640FCB Command Interface and Program/Erase Controller State
75/77
Program
(complete)
Read
Elect.Sg.
Read
CFIQuery Lock Setup Prot. Prog.
Setup Read Array
Erase
Setup Erase Command Error Erase
(continue)
Erase
Cmd.Error
Read
Elect.Sg.
Read CFI
Query Lock Setup Prot. Prog.
Setup Read Array
Erase
(continue) Erase (continue)
Erase
Suspend
Read
Ststus
Erase
Suspend
Read
Elect.Sg.
Erase
Suspend
Read CFI
Query
Lock Setup Erase Suspend Read Array Erase
(continue)
Erase
Suspend
Read Array
Erase
Suspend
Read
Elect.Sg.
Erase
Suspend
Read CFI
Query
Lock Setup Erase Suspend Read Array Erase
(continue)
Erase
Suspend
Read
Elect.Sg.
Erase
Suspend
Read
Elect.Sg.
Erase
Suspend
Read CFI
Query
Lock Setup Erase Suspend Read Array Erase
(continue)
Erase
Suspend
Read CFI
Query
Erase
Suspend
Read
Elect.Sg.
Erase
Suspend
Read CFI
Query
Lock Setup Erase Suspend Read Array Erase
(continue)
Erase
(complete)
Read
Elect.Sg.
Read CFI
Query Lock Setup Prot. Prog.
Setup Read Array
1. Cmd = Command, Elect.Sg. = Electronic Signature, Prog. = Program, Prot = Protection.
Table 33. Write State machine Current/Next(1) (continued)
Current
State
Command Input (and Next State)
Read
Elect.Sg.
(90h)
Read CFI
Query
(98h)
Lock
Setup
(60h)
Prot.
Prog.
Setup
(C0h)
Lock
Confirm
(01h)
Lock
Down
Confirm
(2Fh)
Unlock
Confirm
(D0h)
Revision history M28W640FCT, M28W640FCB
76/77
Revision history
Table 34. Document revision history
Date Version Revision details
24-May-2004 0.1 First Issue
23-Aug-2004 0.2 Figure 2: TSOP connections and Figure 3: TFBGA connections (top
view through package) updated.
08-Apr-2005 1.0
Datasheet maturity changed to PRELIMINARY DATA.
TSOP48 Package Mechanical Data updated in Table 20: TSOP48 - 48
lead Plastic Thin Small Outline, 12 x 20mm, package mechanical data.
21-Aug-2006 2
Document status promoted from Preliminary Data to full Datasheet.
tGLQV value changed for 100ns speed class (codified as 10 in part
numbering scheme) in Table 16: Read AC characteristics.
Blank and T options removed from below Option in Ta bl e 2 2 and
Ta bl e 2 3 .
Packages are ECOPACK® compliant.
23-Oct-2006 3 The 0.13µm technology was removed from the device options of
Table 22: Ordering information scheme.
26-Mar-2008 4 Applied Numonyx branding.
M28W640FCT, M28W640FCB
77/77
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