LT1766/LT1766-5
1
1766fc
TYPICAL APPLICATION
DESCRIPTION
5.5V to 60V 1.5A, 200kHz
Step-Down Switching Regulator
5V Buck Converter
FEATURES
APPLICATIONS
n Wide Input Range: 5.5V to 60V
n 1.5A Peak Switch Current
n Constant 200kHz Switching Frequency
n Saturating Switch Design: 0.2Ω
n Peak Switch Current Rating Maintained Over
Full Duty Cycle Range
n Low Effective Supply Current: 2.5mA
n Low Shutdown Current: 25μA
n 1.2V Feedback Reference Voltage (LT1766)
n 5V Fixed Output (LT1766-5)
n Easily Synchronizable
n Cycle-by-Cycle Current Limiting
n Small 16-Pin SSOP and Thermally Enhanced
TSSOP Packages
The LT
®
1766/LT1766-5 are 200kHz monolithic buck switch-
ing regulators that accept input voltages up to 60V. A high
effi ciency 1.5A, 0.2Ω switch is included on the die along
with all the necessary oscillator, control and logic circuitry.
A current mode control architecture delivers fast transient
response and excellent loop stability.
Special design techniques and a new high voltage process
achieve high effi ciency over a wide input range. Effi ciency
is maintained over a wide output current range by using the
output to bias the circuitry and by utilizing a supply boost
capacitor to saturate the power switch. Patented circuitry
maintains peak switch current over the full duty cycle range.
A shutdown pin reduces supply current to 25μA and the
device can be externally synchronized from 228kHz to
700kHz with logic-level inputs.
The LT1766/LT1766-5 are available in a 16-pin fused-lead
SSOP package or a TSSOP package with exposed backside
for improved thermal performance.
n High Voltage, Industrial and Automotive
n Portable Computers
n Battery-Powered Systems
n Battery Chargers
n Distributed Power Systems
Effi ciency vs Load Current
BOOST
VIN
6
2
10
12
10MQ060N
15.4k
VOUT
5V
1A
4
15
14
11
220pF
0.022μF
*
†FOR INPUT VOLTAGES BELOW 7.5V, SOME RESTRICTIONS MAY APPLY
TDK C4532X7R2A225K
1, 8, 9, 16
LT1766
SHDN
SYNC
SW
BIAS
FB
VC
GND
0.33μF
100μF 10V
SOLID
TANTALUM
47μH
1N4148W
4.99k
1766 TA01
2.2μF†
100V
CERAMIC
VIN*
5.5V TO 60V
+
2.2k
ONOFF
LOAD CURRENT (A)
0
EFFICIENCY (%)
80
90
100
1.00
1766 TA02
70
60
50 0.25 0.50 0.75 1.25
VIN = 12V
VIN = 42V
VOUT = 5V
L = 47μH
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the property
of their respective owners. Protected by U.S. Patents, including 6498466, 6531909.
LT1766/LT1766-5
2
1766fc
ABSOLUTE MAXIMUM RATINGS
(Note 1)
Input Voltage (VIN) .................................................. 60V
BOOST Pin Above SW .............................................. 35V
BOOST Pin Voltage ................................................. 68V
SYNC, SENSE Voltage (LT1766-5) ............................. 7V
SHDN Voltage ............................................................ 6V
BIAS Pin Voltage ..................................................... 30V
FB Pin Voltage/Current (LT1766) ................... 3.5V/2mA
Operating Junction Temperature Range
LT1766EFE/LT1766EFE-5/LT1766EGN/
LT1766EGN-5 (Note 8,10) ....................–40°C to 125°C
LT1766IFE/LT1766IFE-5/
LT1766IGN/LT1766IGN-5 (Note 8,10) ..–40°C to 125°C
LT1766HFE ..........................................–40°C to 140°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec) .................. 300°C
FE PACKAGE
16-LEAD PLASTIC TSSOP
1
2
3
4
5
6
7
8
TOP VIEW
16
15
14
13
12
11
10
9
GND
SW
NC
VIN
NC
BOOST
NC
GND
GND
SHDN
SYNC
NC
FB/SENSE
VC
BIAS
GND
17
GND
θJA = 45°C, θJC (PIN 17) = 10°C/W
EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB
GN PACKAGE
16-LEAD PLASTIC SSOP
1
2
3
4
5
6
7
8
TOP VIEW
16
15
14
13
12
11
10
9
GND
SW
NC
VIN
NC
BOOST
NC
GND
GND
SHDN
SYNC
NC
FB/SENSE
VC
BIAS
GND
θJA = 85°C, θJC (PIN 8) = 25°C/W
FOUR CORNER PINS SOLDERED TO GROUND PIN
PIN CONFIGURATION
LT1766/LT1766-5
3
1766fc
ELECTRICAL CHARACTERISTICS
The l denotes specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TJ = 25°C.
VIN = 15V, VC = 1.5V, SHDN = 1V, BOOST open circuit, SW open circuit, unless otherwise noted.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Reference Voltage (VREF) (LT1766) 5.5V ≤ VIN ≤ 60V
VOL + 0.2 ≤ VC ≤ VOH – 0.2 l
1.204
1.195
1.219 1.234
1.243
V
V
SENSE Voltage (LT1766-5) 5.5V ≤ VIN ≤ 60V
VOL + 0.2V ≤ VC ≤ VOH – 0.2V l
4.94
4.90
5 5.06
5.10
V
V
SENSE Pin Resistance (LT1766-5) 9.5 13.8 19 kΩ
FB Input Bias Current (LT1766) l–0.5 –1.5 μA
Error Amp Voltage Gain (Notes 2, 9) 200 400 V/V
Error Amp gmdl (VC) = ±10μA (Note 9)
l
1500
1000
2000 3000
4200
μMho
μMho
VC to Switch gm1.7 A/V
EA Source Current FB = 1V or VSENSE = 4.1V l125 225 400 μA
EA Sink Current FB = 1.4V or VSENSE = 5.7V l100 225 450 μA
VC Switching Threshold Duty Cycle = 0 0.9 V
VC High Clamp SHDN = 1V 2.1 V
Switch Current Limit VC Open, Boost = VIN + 5V, FB = 1V or VSENSE = 4.1V l1.5 2 3 A
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LT1766EFE#PBF LT1766EFE#TRPBF 1766EFE 16-Lead Plastic TSSOP 0°C to 125°C
LT1766IFE#PBF LT1766IFE#TRPBF 1766IFE 16-Lead Plastic TSSOP –40°C to 125°C
LT1766HFE#PBF LT1766HFE#TRPBF 1766HFE 16-Lead Plastic TSSOP –40°C to 140°C
LT1766EFE-5#PBF LT1766EFE-5#TRPBF 1766EFE-5 16-Lead Plastic TSSOP 0°C to 125°C
LT1766IFE-5#PBF LT1766IFE-5#TRPBF 1766IFE-5 16-Lead Plastic TSSOP –40°C to 125°C
LT1766EGN#PBF LT1766EGN#TRPBF 1766 16-Lead Plastic SSOP 0°C to 125°C
LT1766IGN#PBF LT1766IGN#TRPBF 1766I 16-Lead Plastic SSOP –40°C to 125°C
LT1766EGN-5#PBF LT1766EGN-5#TRPBF 17665 16-Lead Plastic SSOP 0°C to 125°C
LT1766IGN-5#PBF LT1766IGN-5#TRPBF 1766I5 16-Lead Plastic SSOP –40°C to 125°C
LEAD BASED FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LT1766EFE LT1766EFE#TR 1766EFE 16-Lead Plastic TSSOP 0°C to 125°C
LT1766IFE LT1766IFE#TR 1766IFE 16-Lead Plastic TSSOP –40°C to 85°C
LT1766HFE LT1766HFE#TR 1766HFE 16-Lead Plastic TSSOP –40°C to 140°C
LT1766EFE-5 LT1766EFE-5#TR 1766EFE-5 16-Lead Plastic TSSOP 0°C to 125°C
LT1766IFE-5 LT1766IFE-5#TR 1766IFE-5 16-Lead Plastic TSSOP –40°C to 125°C
LT1766EGN LT1766EGN#TR 1766 16-Lead Plastic SSOP 0°C to 125°C
LT1766IGN LT1766IGN#TR 1766I 16-Lead Plastic SSOP –40°C to 125°C
LT1766EGN-5 LT1766EGN-5#TR 17665 16-Lead Plastic SSOP 0°C to 125°C
LT1766IGN-5 LT1766IGN-5#TR 1766I5 16-Lead Plastic SSOP –40°C to 125°C
Consult LTC Marketing for parts specifi ed with wider operating temperature ranges.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifi cations, go to: http://www.linear.com/tapeandreel/
(LT1766E/LT1766I Grade)
LT1766/LT1766-5
4
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PARAMETER CONDITIONS MIN TYP MAX UNITS
Reference Voltage (VREF) 5.5V ≤ VIN ≤ 60V
VOL + 0.2 ≤ VC ≤ VOH – 0.2 l
1.204
1.175
1.219 1.234
1.265
V
V
FB Input Bias Current l–0.5 –1.5 μA
Error Amp Voltage Gain (Notes 2, 9) 200 400 V/V
Error Amp gmdl (VC) = ±10μA (Note 9)
l
1500
900
2000 3000
4200
μMho
μMho
VC to Switch gm1.7 A/V
EA Source Current FB = 1V or VSENSE = 4.1V l125 225 400 μA
EA Sink Current FB = 1.4V or VSENSE = 5.7V l100 225 450 μA
VC Switching Threshold Duty Cycle = 0 0.9 V
VC High Clamp SHDN = 1V 2.1 V
Switch Current Limit VC Open, Boost = VIN + 5V, FB = 1V or VSENSE = 4.1V l0.75 2 3 A
Switch On Resistance ISW = 0.75A, Boost = VIN + 5V (Note 7)
l
0.2 0.3
0.8
Ω
Ω
Maximum Switch Duty Cycle FB = 1V or VSENSE = 4.1V
l
93
90
96 %
%
Switch Frequency VC Set to Give DC = 50%
l
184
135
200
200
216
228
kHz
kHz
(LT1766H Grade)
The l denotes specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TJ = 25°C.
VIN = 15V, VC = 1.5V, SHDN = 1V, BOOST open circuit, SW open circuit, unless otherwise noted.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Switch On-Resistance ISW = 1.5A, Boost = VIN + 5V (Note 7)
l
0.2 0.3
0.4
Ω
Ω
Maximum Switch Duty Cycle FB = 1V or VSENSE = 4.1V
l
93
90
96 %
%
Switch Frequency VC Set to Give DC = 50%
l
184
172
200
200
216
228
kHz
kHz
fSW Line Regulation 5.5V ≤ VIN ≤ 60V l0.05 0.15 %/V
fSW Frequency Shifting Threshold Df = 10kHz 0.8 V
Minimum Input Voltage (Note 3) l4.6 5.5 V
Minimum Boost Voltage (Note 4) ISW ≤ 1.5A l1.8 3 V
Boost Current (Note 5) Boost = VIN + 5V, ISW = 0.5A
Boost = VIN + 5V, ISW = 1.5A
l
l
12
45
25
70
mA
mA
Input Supply Current (IVIN) (Note 6) VBIAS = 5V 1.4 2.2 mA
Bias Supply Current (IBIAS) (Note 6) VBIAS = 5V 2.9 4.2 mA
Shutdown Supply Current SHDN = 0V, VIN ≤ 60V, SW = 0V, VC Open
l
25 75
200
μA
μA
Lockout Threshold VC Open l2.3 2.42 2.53 V
Shutdown Thresholds VC Open, Shutting Down
VC Open, Starting Up
l
l
0.15
0.25
0.37
0.45
0.6
0.6
V
V
Minimum SYNC Amplitude l1.5 2.2 V
SYNC Frequency Range 228 700 kHz
SYNC Input Resistance 20 kΩ
ELECTRICAL CHARACTERISTICS
The l denotes specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TJ = 25°C.
VIN = 15V, VC = 1.5V, SHDN = 1V, BOOST open circuit, SW open circuit, unless otherwise noted.
(LT1766E/LT1766I Grade)
LT1766/LT1766-5
5
1766fc
ELECTRICAL CHARACTERISTICS
PARAMETER CONDITIONS MIN TYP MAX UNITS
fSW Line Regulation 5.5V ≤ VIN ≤ 60V l0.05 0.15 %/V
fSW Frequency Shifting Threshold Df = 10kHz 0.8 V
Minimum Input Voltage (Note 3) l4.6 5.5 V
Minimum Boost Voltage (Note 4) ISW ≤ 0.75A l1.8 3 V
Boost Current (Note 5) Boost = VIN + 5V, ISW = 0.5A
Boost = VIN + 5V, ISW = 0.75A
l
l
12
45
40
100
mA
mA
Input Supply Current (IVIN) (Note 6) VBIAS = 5V 1.4 2.2 mA
Bias Supply Current (IBIAS) (Note 6) VBIAS = 5V 2.9 4.2 mA
Shutdown Supply Current SHDN = 0V, VIN ≤ 60V, SW = 0V, VC Open
l
25 120
500
μA
μA
Lockout Threshold VC Open l2.3 2.42 2.68 V
Shutdown Thresholds VC Open, Shutting Down
VC Open, Starting Up
l
l
0.15
0.25
0.37
0.45
0.9
0.9
V
V
Minimum SYNC Amplitude l1.5 2.2 V
SYNC Frequency Range 228 700 kHz
SYNC Input Resistance 20 kΩ
(LT1766H Grade)
The l denotes specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TJ = 25°C.
VIN = 15V, VC = 1.5V, SHDN = 1V, BOOST open circuit, SW open circuit, unless otherwise noted.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Gain is measured with a VC swing equal to 200mV above the low
clamp level to 200mV below the upper clamp level.
Note 3: Minimum input voltage is not measured directly, but is guaranteed
by other tests. It is defi ned as the voltage where internal bias lines are still
regulated so that the reference voltage and oscillator remain constant.
Actual minimum input voltage to maintain a regulated output will depend
upon output voltage and load current. See Applications Information.
Note 4: This is the minimum voltage across the boost capacitor needed to
guarantee full saturation of the internal power switch.
Note 5: Boost current is the current fl owing into the BOOST pin with the
pin held 5V above input voltage. It fl ows only during switch on time.
Note 6: Input supply current is the quiescent current drawn by the input
pin when the BIAS pin is held at 5V with switching disabled. Bias supply
current is the current drawn by the BIAS pin when the BIAS pin is held
at 5V. Total input referred supply current is calculated by summing input
supply current (IVIN) with a fraction of bias supply current (IBIAS):
I
TOTAL = IVIN + (IBIAS)(VOUT/VIN)
with VIN = 15V, VOUT = 5V, IVIN = 1.4mA, IBIAS = 2.9mA, ITOTAL = 2.4mA.
Note 7: Switch on-resistance is calculated by dividing VIN to SW voltage
by the forced current. See Typical Performance Characteristics for the
graph of switch voltage at other currents.
Note 8: The LT1766EGN, LT1766EGN-5, LT1766EFE and LT1766EFE-5
are guaranteed to meet performance specifi cations from 0°C to 125°C
junction temperature. Specifi cations over the –40°C to 125°C operating
junction temperature range are assured by design, characterization and
correlation with statistical process controls. The LT1766IGN, LT1766IGN-5,
LT1766IFE and LT1766IFE-5 are guaranteed over the full –40°C to 125°C
operating junction temperature range. The LT1766HGN and LT1766HFE are
guaranteed over the full –40°C to 140°C operating junction temperature
range.
Note 9: Transconductance and voltage gain refer to the internal amplifi er
exclusive of the voltage divider. To calculate gain and transconductance,
refer to the SENSE pin on fi xed voltage parts. Divide the values shown by
the ratio VOUT/1.219.
Note 10: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 140°C when overtemperature protection is active.
Continuous operation above the specifi ed maximum operating junction
temperature may impair device reliability.
Note 11: High junction temperatures degrade operating lifetimes.
Operating lifetime at junction temperatures between 125°C and 140°C is
derated to 1000 hours.
LT1766/LT1766-5
6
1766fc
DUTY CYCLE (%)
1.0
SWITCH PEAK CURRENT (A)
1.5
2.0
2.5
20 40
TYPICAL
60 80
1766 G01
1000
GUARANTEED MINIMUM
T
A
= 25°C
JUNCTION TEMPERATURE (°C)
–50
FEEDBACK VOLTAGE (V)
CURRENT (μA)
1.224
1.229
1.234
25 75
1766 G02
1.219
1.214
–25 0 50 100 125 150
1.209
1.204
1.5
2.0
1.0
0.5
0
VOLTAGE
CURRENT
JUNCTION TEMPERATURE (°C)
–50
250
200
150
100
12
6
025 75
1766 G03
–25 0 50 100 150125
CURRENT (μA)
CURRENT REQUIRED TO FORCE SHUTDOWN
(FLOWS OUT OF PIN). AFTER SHUTDOWN,
CURRENT DROPS TO A FEW μA
AT 2.38V STANDBY THRESHOLD
(CURRENT FLOWS OUT OF PIN)
TYPICAL PERFORMANCE CHARACTERISTICS
Switch Peak Current Limit SHDN Pin Bias Current
Shutdown Supply Current
Lockout and Shutdown
Thresholds Shutdown Supply Current
Error Amplifi er Transconductance
FB Pin Voltage and Current
Error Amplifi er Transconductance
JUNCTION TEMPERATURE (°C)
–50
SHDN PIN VOLTAGE (V)
50 100
1766 G04
025 75
2.4
2.0
1.6
1.2
0.8
0.4
0–25 150125
LOCKOUT
START-UP
SHUTDOWN
INPUT VOLTAGE (V)
0
INPUT SUPPLY CURRENT (μA)
1766 G05
10 20 30 40 50 60
40
35
30
25
20
15
10
5
0
VSHDN = 0V
TA = 25°C
SHUTDOWN VOLTAGE (V)
0
0
INPUT SUPPLY CURRENT (μA)
50
100
150
200
250
300
0.1 0.2 0.3 0.4
1766 G06
0.5
VIN = 60V
VIN = 15V
TA = 25°C
JUNCTION TEMPERATURE (°C)
TRANSCONDUCTANCE (μmho)
1766 G07
2500
2000
1500
1000
500
0
–50 50 100
025 75–25 150125
FREQUENCY (Hz)
GAIN (μMho)
PHASE (DEG)
3000
2500
2000
1500
1000
500
200
150
100
50
0
–50
100 10k 100k 10M
1766 G08
1k 1M
GAIN
PHASE
ERROR AMPLIFIER EQUIVALENT CIRCUIT
ROUT
200k
COUT
12pF
VC
RLOAD = 50Ω
VFB 2 • 10
–3
)(
TA = 25°C
V
FB
(V)
0
SWITICHING FREQUENCY (kHz)
OR FB CURRENT (μA)
300
400
600
500
1766 G09
200
100
00.5 1.0 1.5
SWITCHING
FREQUENCY
FB PIN
CURRENT
T
A
= 25°C
Frequency Foldback
LT1766/LT1766-5
7
1766fc
PIN FUNCTIONS
TYPICAL PERFORMANCE CHARACTERISTICS
Switching Frequency BOOST Pin Current
Minimum Input Voltage with 5V
Output
Switch Voltage Drop
JUNCTION TEMPERATURE (°C)
–50
FREQUENCY (kHz)
50 100
1766 G10
025 75
230
220
210
200
190
180
170 –25 150125
LOAD CURRENT (A)
0
INPUT VOLTAGE (V)
1766 G11
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
7.5
7.0
6.5
6.0
5.5
5.0
MINIMUM INPUT
VOLTAGE TO START
MINIMUM INPUT
VOLTAGE TO RUN
T
A
= 25°C
SWITCH CURRENT (A)
0 0.5 1 1.5
BOOST PIN CURRENT (mA)
1766 G12
45
40
35
30
25
20
15
10
5
0
T
A
= 25°C
JUNCTION TEMPERATURE (°C)
–50
1.5
1.7
2.1
25 75
1766 G13
1.3
1.1
–25 0 50 100 150125
0.9
0.7
1.9
THRESHOLD VOLTAGE (V)
SWITCH CURRENT (A)
0 0.5 1 1.5
SWITCH VOLTAGE (mV)
1766 G14
450
400
350
300
250
200
150
100
50
0
T
J
= 125°C
T
J
= 150°C
T
J
= 25°C
T
J
= –40°C
JUNCTION TEMPERATURE (°C)
–50
SWITCH MINIMUM ON TIME (ns)
400
500
600
25 75
1766 G15
300
200
–25 0 50 100 150125
100
0
VC Pin Shutdown Threshold
Switch Minimum On-Time
vs Temperature
GND (Pins 1, 8, 9, 16, 17): The GND pin connections act
as the reference for the regulated output, so load regula-
tion will suffer if the ground end of the load is not at the
same voltage as the GND pins of the IC. This condition will
occur when load current or other currents fl ow through
metal paths between the GND pins and the load ground.
Keep the paths between the GND pins and the load ground
short and use a ground plane when possible. The GND
pin also acts as a heat sink and should be soldered to a
large copper plane to reduce thermal resistance. For the
FE package, the exposed pad should be soldered to the
copper ground plane underneath the device. (See Applica-
tions Information—Layout Considerations.)
SW (Pin 2): The switch pin is the emitter of the on-chip
power NPN switch. This pin is driven up to the input pin
voltage during switch on-time. Inductor current drives the
switch pin negative during switch off-time. Negative volt-
age is clamped with the external catch diode. Maximum
negative switch voltage allowed is –0.8V.
NC (Pins 3, 5, 7, 13): No Connection.
LT1766/LT1766-5
8
1766fc
PIN FUNCTIONS
BLOCK DIAGRAM
VIN (Pin 4): This is the collector of the on-chip power NPN
switch. VIN powers the internal control circuitry when a
voltage on the BIAS pin is not present. High dI/dt edges
occur on this pin during switch turn on and off. Keep
the path short from the VIN pin through the input bypass
capacitor, through the catch diode back to SW. All trace
inductance on this path will create a voltage spike at switch
off, adding to the VCE voltage across the internal NPN.
BOOST (Pin 6): The BOOST pin is used to provide a drive
voltage, higher than the input voltage, to the internal bipolar
NPN power switch. Without this added voltage, the typical
switch voltage loss would be about 1.5V. The additional
BOOST voltage allows the switch to saturate and voltage
loss approximates that of a 0.2Ω FET structure, but with
much smaller die area.
BIAS (Pin 10): The BIAS pin is used to improve effi ciency
when operating at higher input voltages and light load cur-
rent. Connecting this pin to the regulated output voltage
forces most of the internal circuitry to draw its operating
current from the output voltage rather than the input supply.
This architecture increases effi ciency especially when the
input voltage is much higher than the output. Minimum
output voltage setting for this mode of operation is 3V.
VC (Pin 11) The VC pin is the output of the error amplifi er
and the input of the peak switch current comparator. It is
normally used for frequency compensation, but can also
serve as a current clamp or control loop override. VC sits
at about 0.9V for light loads and 2.1V at maximum load.
It can be driven to ground to shut off the regulator, but if
driven high, current must be limited to 4mA.
FB/SENSE (Pin 12): The feedback pin is used to set the
output voltage using an external voltage divider that gener-
ates 1.22V at the pin for the desired output voltage. The
5V fi xed output voltage parts have the divider included on
the chip and the FB pin is used as a SENSE pin, connected
directly to the 5V output. Three additional functions are
performed by the FB pin. When the pin voltage drops below
0.6V, switch current limit is reduced and the external SYNC
function is disabled. Below 0.8V, switching frequency is
also reduced. See Feedback Pin Functions in Applications
Information for details.
SYNC (Pin 14): The SYNC pin is used to synchronize the
internal oscillator to an external signal. It is directly logic
compatible and can be driven with any signal between 10%
and 90% duty cycle. The synchronizing range is equal to
initial operating frequency up to 700kHz. See Synchroniz-
ing in Applications Information for details.
SHDN (Pin 15): The SHDN pin is used to turn off the
regulator and to reduce input drain current to a few mi-
croamperes. This pin has two thresholds: one at 2.38V to
disable switching and a second at 0.4V to force complete
micropower shutdown. The 2.38V threshold functions
as an accurate undervoltage lockout (UVLO); sometimes
used to prevent the regulator from delivering power until
the input voltage has reached a predetermined level.
If the SHDN pin functions are not required, the pin can
either be left open (to allow an internal bias current to lift
the pin to a default high state) or be forced high to a level
not to exceed 6V.
The LT1766 is a constant frequency, current mode buck
converter. This means that there is an internal clock and
two feedback loops that control the duty cycle of the power
switch. In addition to the normal error amplifi er, there is a
current sense amplifi er that monitors switch current on a
cycle-by-cycle basis. A switch cycle starts with an oscillator
pulse which sets the RS fl ip-fl op to turn the switch on. When
switch current reaches a level set by the inverting input of
the comparator, the fl ip-fl op is reset and the switch turns
off. Output voltage control is obtained by using the output
of the error amplifi er to set the switch current trip point.
This technique means that the error amplifi er commands
current to be delivered to the output rather than voltage.
A voltage fed system will have low phase shift up to the
resonant frequency of the inductor and output capacitor,
then an abrupt 180° shift will occur. The current fed system
LT1766/LT1766-5
9
1766fc
BLOCK DIAGRAM
will have 90° phase shift at a much lower frequency, but
will not have the additional 90° shift until well beyond
the LC resonant frequency. This makes it much easier to
frequency compensate the feedback loop and also gives
much quicker transient response.
Most of the circuitry of the LT1766 operates from an internal
2.9V bias line. The bias regulator normally draws power
from the regulator input pin, but if the BIAS pin is connected
to an external voltage higher than 3V, bias power will be
drawn from the external source (typically the regulated
–
+
–+
–
+
–
+
∑
VIN
2.9V BIAS
REGULATOR
200kHz
OSCILLATOR
FREQUENCY
FOLDBACK
SW
FB
GND
1, 8, 9, 16, 17
1766 F01
SLOPE COMP
ANTISLOPE COMP
BIAS INTERNAL
V
CC
SYNC
0.4V
5.5μA
CURRENT
COMPARATOR
R
LIMIT
R
SENSE
ERROR
AMPLIFIER
g
m
= 2000μMho
Q2
FOLDBACK
CURRENT
LIMIT
CLAMP
BOOST
R
S
FLIP-FLOP
DRIVER
CIRCUITRY
S
R
Q1
POWER
SWITCH
1.22V
4
10
14
SHDN 15
6
2
12
11
V
C
LOCKOUT
COMPARATOR
SHUTDOWN
COMPARATOR
2.38V
×1
Q3
V
C(MAX)
CLAMP
output voltage). This will improve effi ciency if the BIAS
pin voltage is lower than regulator input voltage.
High switch effi ciency is attained by using the BOOST
pin to provide a voltage to the switch driver which is
higher than the input voltage, allowing switch to be satu-
rated. This boosted voltage is generated with an external
capacitor and diode. Two comparators are connected to the
shutdown pin. One has a 2.38V threshold for undervoltage
lockout and the second has a 0.4V threshold for complete
shutdown.
Figure 1. LT1766 Block Diagram
LT1766/LT1766-5
10
1766fc
APPLICATIONS INFORMATION
FEEDBACK PIN FUNCTIONS
The feedback (FB) pin on the LT1766 is used to set output
voltage and provide several overload protection features.
The fi rst part of this section deals with selecting resistors
to set output voltage and the remaining part talks about
foldback frequency and current limiting created by the FB
pin. Please read both parts before committing to a fi nal
design. The 5V fi xed output voltage part (LT1766-5) has
internal divider resistors and the FB pin is renamed SENSE,
connected directly to the output.
The suggested value for the output divider resistor (see
Figure 2) from FB to ground (R2) is 5k or less, and a
formula for R1 is shown below. The output voltage error
caused by ignoring the input bias current on the FB pin
is less than 0.25% with R2 = 5k. A table of standard 1%
values is shown in Table 1 for common output voltages.
Please read the following if divider resistors are increased
above the suggested values.
RRV
OUT
12122
122
=−
()
.
.
Table 1
OUTPUT
VOLTAGE
(V)
R2
(kΩ)
R1
(NEAREST 1%)
(kΩ)
% ERROR AT OUTPUT
DUE TO DISCREET 1%
RESISTOR STEPS
34.997.32 +0.32
3.3 4.99 8.45 –0.43
54.9915.4 –0.30
64.7518.7 +0.38
84.4724.9 +0.20
10 4.32 30.9 –0.54
12 4.12 36.5 +0.24
15 4.12 46.4 –0.27
More Than Just Voltage Feedback
The feedback pin is used for more than just output voltage
sensing. It also reduces switching frequency and current
limit when output voltage is very low (see the Frequency
Foldback graph in Typical Performance Characteristics).
This is done to control power dissipation in both the IC
and in the external diode and inductor during short-cir-
cuit conditions. A shorted output requires the switching
regulator to operate at very low duty cycles, and the
average current through the diode and inductor is equal
to the short-circuit current limit of the switch (typically 2A
for the LT1766, folding back to less than 1A). Minimum
switch on-time limitations would prevent the switcher
from attaining a suffi ciently low duty cycle if switching
frequency were maintained at 200kHz, so frequency is
reduced by about 5:1 when the feedback pin voltage drops
below 0.8V (see Frequency Foldback graph). This does
not affect operation with normal load conditions; one
simply sees a gear shift in switching frequency during
start-up as the output voltage rises.
In addition to lower switching frequency, the LT1766 also
operates at lower switch current limit when the feedback
pin voltage drops below 0.6V. Q2 in Figure 2 performs
this function by clamping the VC pin to a voltage less than
its normal 2.1V upper clamp level. This
foldback current
limit
greatly reduces power dissipation in the IC, diode
and inductor during short-circuit conditions. External syn-
chronization is also disabled to prevent interference with
foldback operation. Again, it is nearly transparent to the user
under normal load conditions. The only loads that may be
affected are current source loads which maintain full load
current with output voltage less than 50% of fi nal value.
In these rare situations the feedback pin can be clamped
above 0.6V with an external diode to defeat foldback cur-
rent limit.
Caution:
clamping the feedback pin means that
frequency shifting will also be defeated, so a combination
of high input voltage and dead shorted output may cause
the LT1766 to lose control of current limit.
The internal circuitry which forces reduced switching
frequency also causes current to fl ow out of the feedback
pin when output voltage is low. The equivalent circuitry is
shown in Figure 2. Q1 is completely off during normal op-
eration. If the FB pin falls below 0.8V, Q1 begins to conduct
current and reduces frequency at the rate of approximately
1.4kHz/μA. To ensure adequate frequency foldback (under
worst-case short-circuit conditions), the external divider
Thevinin resistance must be low enough to pull 115μA out
of the FB pin with 0.44V on the pin (RDIV ≤ 3.8k).
The net
result is that reductions in frequency and current limit are
affected by output voltage divider impedance. Although
LT1766/LT1766-5
11
1766fc
APPLICATIONS INFORMATION
divider impedance is not critical, caution should be used if
resistors are increased beyond the suggested values and
short-circuit conditions occur with high input voltage.
High
frequency pickup will increase and the protection accorded
by frequency and current foldback will decrease.
CHOOSING THE INDUCTOR
For most applications, the output inductor will fall into
the range of 15μH to 100μH. Lower values are chosen to
reduce physical size of the inductor. Higher values allow
more output current because they reduce peak current
seen by the LT1766 switch, which has a 1.5A limit. Higher
values also reduce output ripple voltage.
When choosing an inductor you will need to consider
output ripple voltage, maximum load current, peak induc-
tor current and fault current in the inductor. In addition,
other factors such as core and copper losses, allowable
component height, EMI, saturation and cost should also
be considered. The following procedure is suggested
as a way of handling these somewhat complicated and
confl icting requirements.
Output Ripple Voltage
Figure 3 shows a typical output ripple voltage wave-
form for the LT1766. Ripple voltage is determined by
ripple current (ILP-P) through the inductor and the high
frequency impedance of the output capacitor. The fol-
lowing equations will help in choosing the required
inductor value to achieve a desirable output ripple volt-
age level. If output ripple voltage is of less importance,
the subsequent suggestions in Peak Inductor and Fault
Current and EMI will additionally help in the selection of
the inductor value.
Peak-to-peak output ripple voltage is the sum of a triwave
(created by peak-to-peak ripple current (ILP-P) times ESR)
and a square wave (created by parasitic inductance (ESL)
and ripple current slew rate). Capacitive reactance is as-
sumed to be small compared to ESR or ESL.
V I ESR ESL dI
dt
RIPPLE LP P
=
()()
+
()
-
Figure 2. Frequency and Current Limit Foldback
–
+
1.2V
BUFFER
V
SW
L1
V
C
GND
TO SYNC CIRCUIT
1766 F02
TO FREQUENCY
SHIFTING
R3
1k
R4
2k
R1
C1
R2
5k
OUTPUT
5V
ERROR
AMPLIFIER
FB
1.4V Q1
LT1766
Q2
+
Figure 3. LT1766 Ripple Voltage Waveform
2.5μs/DIV
40mV/DIV
V
OUT
AT I
OUT
= 1A
V
OUT
AT I
OUT
= 0.1A
INDUCTOR CURRENT
AT I
OUT
= 1A
INDUCTOR CURRENT
AT I
OUT
= 0.1A
0.5A/DIV
V
IN
= 40V
V
OUT
= 5V
L = 47μH
C = 100μF, 10V, 0.1Ω
1766 F03
LT1766/LT1766-5
12
1766fc
If maximum load current is 0.5A, for instance, a 0.5A
inductor may not survive a continuous 2A overload con-
dition. Dead shorts will actually be more gentle on the
inductor because the LT1766 has frequency and current
limit foldback.
Peak switch and inductor current can be signifi cantly higher
than output current, especially with smaller inductors
and lighter loads, so don’t omit this step. Powdered iron
cores are forgiving because they saturate softly, whereas
ferrite cores saturate abruptly. Other core materials fall
somewhere in between. The following formula assumes
continuous mode of operation, but errs only slightly on
where:
ESR = equivalent series resistance of the output
capacitor
ESL = equivalent series inductance of the output
capacitor
dI/dt = slew rate of inductor ripple current = VIN/L
Peak-to-peak ripple current (ILP-P) through the inductor
and into the output capacitor is typically chosen to be
between 20% and 40% of the maximum load current. It
is approximated by:
IVVV
VfL
LP P OUT IN OUT
IN
-=
()( )
()()()
–
Example: with VIN = 40V, VOUT = 5V, L = 47μH, ESR = 0.1Ω
and ESL = 10nH, output ripple voltage can be approximated
as follows:
IA
dI
dt
VA
mV
RIPPLE
P-P
P-P
=
()
−
()
()
()()
=
==
=
()()
+
()()
()
=+=
−
−
−
540 5
40 47 10 200 10 0 465
40
47 10 10 0 85
0 465 0 1 10 10 10 0 85
0 0465 0 0085 55
63
6
6
96
••
.
••.
..• .
..
To reduce output ripple voltage further requires an increase
in the inductor value or a reduction in the capacitor ESR.
The latter can effect loop stability since the ESR forms
a useful zero in the overall loop response. Typically the
inductor value is adjusted with the trade-off being a
physically larger inductor with the possibility of increased
component height and cost. Choosing a smaller inductor
with lighter loads may result in discontinuous operation
but the LT1766 is designed to work well in both continuous
or discontinuous mode.
Peak Inductor Current and Fault Current
To ensure that the inductor will not saturate, the peak
inductor current should be calculated knowing the
maximum load current. An appropriate inductor should
then be chosen. In addition, a decision should be made
whether or not the inductor must withstand continuous
fault conditions.
APPLICATIONS INFORMATION
Table 2
VENDOR/
PART NO.
VALUE
(μH)
IDC
(AMPS)
DCR
(OHMS)
HEIGHT
(mm)
Coiltronics
CTX15-1P 15 1.4 0.087 4.2
CTX15-1 15 1.1 0.08 4.2
CTX33-2P 33 1.3 0.126 6
CTX33-2 33 1.4 0.106 6
UP2-330 33 2.4 0.099 5.9
UP2-470 47 1.9 0.146 5.9
UP2-680 68 1.7 0.19 5.9
UP2-101 100 1.4 0.277 5.9
Sumida
CDRH6D28-150M 15 1.4 0.076 3
CDRH6D38-150M 15 1.6 0.062 4
CDRH6D28-330M 33 0.97 0.122 3
CDRH104R-330M 33 2.1 0.069 3.8
CDRH125-330M 33 2.1 0.044 6
CDRH104R-470M 47 2.1 0.095 3.8
CDRH125-470M 47 1.8 0.058 6
CDRH6D38-680M 68 0.75 0.173 4
CDRH104R-680M 68 1.5 0.158 3.8
CDRH125-680M 68 1.5 0.093 6
CDRH104R-101M 100 1.35 0.225 3.8
CDRH125-101M 100 1.3 0.120 6
Coilcraft
DT3316P-153 15 1.8 0.06 5
DT3316P-333 33 1.3 0.09 5
DT3316P-473 47 1 0.11 5
LT1766/LT1766-5
13
1766fc
APPLICATIONS INFORMATION
the high side for discontinuous mode, so it can be used
for all conditions.
IIIIVVV
VfL
PEAK OUT LP P OUT
OUT IN OUT
IN
=+ =+
()( )
()( )()()
() –
-
22
EMI
Decide if the design can tolerate an open core geometry like
a rod or barrel, which have high magnetic fi eld radiation,
or whether it needs a closed core like a toroid to prevent
EMI problems. This is a tough decision because the rods
or barrels are temptingly cheap and small and there are
no helpful guidelines to calculate when the magnetic fi eld
radiation will be a problem.
Additional Considerations
After making an initial choice, consider additional factors
such as core losses and second sourcing, etc. Use the
experts in Linear Technology’s Applications department
if you feel uncertain about the fi nal choice. They have
experience with a wide range of inductor types and can tell
you about the latest developments in low profi le, surface
mounting, etc.
Maximum Output Load Current
Maximum load current for a buck converter is limited
by the maximum switch current rating (IP). The current
rating for the LT1766 is 1.5A. Unlike most current mode
converters, the LT1766 maximum switch current limit
does not fall off at high duty cycles. Most current mode
converters suffer a drop off of peak switch current for
duty cycles above 50%. This is due to the effects of slope
compensation required to prevent subharmonic oscilla-
tions in current mode converters. (For detailed analysis,
see Application Note 19.)
The LT1766 is able to maintain peak switch current limit
over the full duty cycle range by using patented circuitry*
to cancel the effects of slope compensation on peak switch
current without affecting the frequency compensation it
provides.
Maximum load current would be equal to maximum switch
current
for an infi nitely large inductor
, but with fi nite
inductor size, maximum load current is reduced by one-
half peak-to-peak inductor current (ILP-P). The following
formula assumes continuous mode operation, implying
that the term on the right is less than one-half of IP
.
I
OUT(MAX) =
Continuous Mode
I–
I
2= I
PLP-P P−+
()
−
()
()()( )
VVVVV
LfV
OUT F IN OUT F
IN
–
2
For VOUT = 5V, VIN = 8V, VF(D1) = 0.63V, f = 200kHz and
L = 20μH:
I
A
OUT MAX
()
−
=− +
()
−
()
()()
()
=− =
15 5 0 63 8 5 0 63
2 20 10 200 10 8
15 021 129
63
..–.
••
.. .
Note that there is less load current available at the higher
input voltage because inductor ripple current increases.
At VIN = 15V, duty cycle is 33% and for the same set of
conditions:
I
A
OUT MAX()..–.
••
.. .
=− +
()
−
()
()()
()
=− =
−
15 5 0 63 15 5 0 63
2 20 10 200 10 15
15 044 106
63
To calculate actual peak switch current with a given set
of conditions, use:
II
IVVVVV
LfV
SW PEAK OUT P
OUT OUT F IN OUT F
IN
()
=+
=+ +−
()
()()( )
I
2
L-P
() –
2
Reduced Inductor Value and Discontinuous Mode
If the smallest inductor value is of most importance to a
converter design, in order to reduce inductor size/cost,
discontinuous mode may yield the smallest inductor solu-
tion. The maximum output load current in discontinuous
mode, however, must be calculated and is defi ned later
in this section.
*Patent # 6, 498, 466
LT1766/LT1766-5
14
1766fc
Discontinuous mode is entered when the output load
current is less than one-half of the inductor ripple current
(ILP-P). In this mode, inductor current falls to zero before
the next switch turn on (see Figure 8). Buck converters
will be in discontinuous mode for output load current
given by:
I
OUT
Discontinuous Mode
The inductor value in a buck converter is usually chosen
large enough to keep inductor ripple current (ILP-P) low;
this is done to minimize output ripple voltage and maximize
output load current. In the case of large inductor values,
as seen in the equation above, discontinuous mode will
be associated with light loads.
When choosing small inductor values, however, discon-
tinuous mode will occur at much higher output load cur-
rents. The limit to the smallest inductor value that can be
chosen is set by the LT1766 peak switch current (IP) and
the maximum output load current required, given by:
I
OUT(MAX)
Discontinuous Mode
Example: For VIN = 15V, VOUT = 5V, VF = 0.63V, f = 200kHz
and L = 10μH.
I
OUT(MAX)
Discontinuous
Mode
I
OUT(MAX) = 0.639A
Discontinuous Mode
What has been shown here is that if high inductor ripple
current and discontinuous mode operation can be tolerated,
small inductor values can be used. If a higher output load
current is required, the inductor value must be increased.
If IOUT(MAX) no longer meets the discontinuous mode
criteria, use the IOUT(MAX) equation for continuous mode;
the LT1766 is designed to operate well in both modes of
operation, allowing a large range of inductor values to
be used.
Short-Circuit Considerations
The LT1766 is a current mode controller. It uses the VC
node voltage as an input to a current comparator which
turns off the output switch on a cycle-by-cycle basis as
this peak current is reached. The internal clamp on the VC
node, nominally 2V, then acts as an output switch peak
current limit. This action becomes the switch current limit
specifi cation. The maximum available output power is then
determined by the switch current limit.
A potential controllability problem could occur under
short-circuit conditions. If the power supply output is
short circuited, the feedback amplifi er responds to the
low output voltage by raising the control voltage, VC,
to its peak current limit value. Ideally, the output switch
would be turned on, and then turned off as its current
exceeded the value indicated by VC. However, there is fi nite
response time involved in both the current comparator and
turn-off of the output switch. These result in a minimum
on-time, tON(MIN). When combined with the large ratio of
VIN to (VF + I • R), the diode forward voltage plus inductor
I • R voltage drop, the potential exists for a loss of control.
Expressed mathematically the requirement to maintain
control is:
ft VIR
V
ON F
IN
••
≤+
where:
f = Switching frequency
t
ON = Switch minimum on-time
V
F = Diode forward voltage
V
IN = Input voltage
I • R = Inductor I • R voltage drop
If this condition is not observed, the current will not be
limited at IPK, but will cycle-by-cycle ratchet up to some
higher value. Using the nominal LT1766 clock frequency
of 200KHz, a VIN of 40V and a (VF + I • R) of say 0.7V, the
maximum tON to maintain control would be approximately
90ns, an unacceptably short time.
The solution to this dilemma is to slow down the oscil-
lator when the FB pin voltage is abnormally low thereby
indicating some sort of short-circuit condition. Oscillator
frequency is unaffected until FB voltage drops to about
2/3 of its normal value. Below this point the oscillator
<+()(––)
()( )()()
VVVVV
VfL
OUT F IN OUT F
IN
2
=
=
()( )
+
I
IfLV
VVVVV
P
PIN
OUT F IN OUT F
2
2
2
2
()( )
()( )( )
()(––)
ILP-P
=+
(.)•(•)( )()
(.)(––.)
–
1 5 200 10 10 15
25063155063
235
APPLICATIONS INFORMATION
LT1766/LT1766-5
15
1766fc
capacitors fail during very high
turn-on
surges, which
do not occur at the output of regulators. High
discharge
surges, such as when the regulator output is dead shorted,
do not harm the capacitors.
Unlike the input capacitor, RMS ripple current in the output
capacitor is normally low enough that ripple current rating
is not an issue. The current waveform is triangular with
a typical value of 125mARMS. The formula to calculate
this is:
Output capacitor ripple current (RMS):
IVVV
LfV
RIPPLE RMS OUT IN OUT
IN
()
=
()
−
()
()()( )
029.
Ceramic Capacitors
Higher value, lower cost ceramic capacitors are now
becoming available. They are generally chosen for their
good high frequency operation, small size and very low
ESR (effective series resistance). Their low ESR reduces
output ripple voltage but also removes a useful zero in the
loop frequency response, common to tantalum capaci-
tors. To compensate for this, a resistor RC can be placed
in series with the VC compensation capacitor, CC. Care
must be taken however, since this resistor sets the high
frequency gain of the error amplifi er, including the gain at
the switching frequency. If the gain of the error amplifi er
is high enough at the switching frequency, output ripple
voltage (although smaller for a ceramic output capacitor)
may still affect the proper operation of the regulator. A
fi lter capacitor, CF
, in parallel with the RC/CC network is
suggested to control possible ripple at the VC pin. An All
Ceramic solution is possible for the LT1766 by choos-
ing the correct compensation components for the given
application.
Example: For VIN = 8V to 40V, VOUT = 3.3V at 1A, the
LT1766 can be stabilized, provide good transient response
and maintain very low output ripple voltage using the
following component values: (refer to the fi rst page of
this data sheet for component references) C3 = 2.2μF,
RC = 4.7k, CC = 15nF, CF = 220pF and C1 = 47μF. See
Application Note 19 for further detail on techniques for
proper loop compensation.
frequency decreases roughly linearly down to a limit
of about 40kHz. This lower oscillator frequency during
short-circuit conditions can then maintain control with
the effective minimum on time.
It is recommended that for [VIN/(VOUT + VF)] ratios > 10,
a soft-start circuit should be used to control the output
capacitor charge rate during start-up or during recovery
from an output short circuit, thereby adding additional
control over peak inductor current. See Buck Converter
with Adjustable Soft-Start later in this data sheet.
OUTPUT CAPACITOR
The output capacitor is normally chosen by its effective
series resistance (ESR), because this is what determines
output ripple voltage. To get low ESR takes
volume
, so
physically smaller capacitors have high ESR. The ESR
range for typical LT1766 applications is 0.05Ω to 0.2Ω.
A typical output capacitor is an AVX type TPS, 100μF at
10V, with a guaranteed ESR less than 0.1Ω. This is a “D”
size surface mount solid tantalum capacitor. TPS capaci-
tors are specially constructed and tested for low ESR, so
they give the lowest ESR for a given volume. The value
in microfarads is not particularly critical, and values from
22μF to greater than 500μF work well, but you cannot
cheat mother nature on ESR. If you fi nd a tiny 22μF solid
tantalum capacitor, it will have high ESR, and output ripple
voltage will be terrible. Table 2 shows some typical solid
tantalum surface mount capacitors.
Table 3. Surface Mount Solid Tantalum Capacitor ESR
and Ripple Current
E Case Size ESR (MAX, Ω ) RIPPLE CURRENT (A)
AVX TPS, Sprague 593D 0.1 to 0.3 0.7 to 1.1
D Case Size
AVX TPS, Sprague 593D 0.1 to 0.3 0.7 to 1.1
C Case Size
AVX TPS 0.2 (typ) 0.5 (typ)
Many engineers have heard that solid tantalum capacitors
are prone to failure if they undergo high surge currents. This
is historically true, and type TPS capacitors are specially
tested for surge capability, but surge ruggedness is not
a critical issue with the
output
capacitor. Solid tantalum
APPLICATIONS INFORMATION
LT1766/LT1766-5
16
1766fc
INPUT CAPACITOR
Step-down regulators draw current from the input supply in
pulses. The rise and fall times of these pulses are very fast.
The input capacitor is required to reduce the voltage ripple
this causes at the input of LT1766 and force the switching
current into a tight local loop, thereby minimizing EMI.
The RMS ripple current can be calculated from:
IIVVVV
RIPPLE RMS OUT OUT IN OUT IN
()
=
()
–/
2
Ceramic capacitors are ideal for input bypassing. At 200kHz
switching frequency, the energy storage requirement of the
input capacitor suggests that values in the range of 2.2μF
to 20μF are suitable for most applications. If operation is
required close to the minimum input required by the output
of the LT1766, a larger value may be required. This is to
prevent excessive ripple causing dips below the minimum
operating voltage resulting in erratic operation.
Depending on how the LT1766 circuit is powered up you
may need to check for input voltage transients.
The input voltage transients may be caused by input volt-
age steps or by connecting the LT1766 converter to an
already powered up source such as a wall adapter. The
sudden application of input voltage will cause a large surge
of current in the input leads that will store energy in the
parasitic inductance of the leads. This energy will cause the
input voltage to swing above the DC level of input power
source and it may exceed the maximum voltage rating of
input capacitor and LT1766.
The easiest way to suppress input voltage transients is
to add a small aluminum electrolytic capacitor in parallel
with the low ESR input capacitor. The selected capacitor
needs to have the right amount of ESR in order to criti-
cally dampen the resonant circuit formed by the input lead
inductance and the input capacitor. The typical values of
ESR will fall in the range of 0.5Ω to 2Ω and capacitance
will fall in the range of 5μF to 50μF.
If tantalum capacitors are used, values in the 22μF to 470μF
range are generally needed to minimize ESR and meet
ripple current and surge ratings. Care should be taken to
ensure the ripple and surge ratings are not exceeded. The
AVX TPS and Kemet T495 series are surge rated. AVX
recommends derating capacitor operating voltage by 2:1
for high surge applications.
CATCH DIODE
Highest effi ciency operation requires the use of a Schottky
type diode. DC switching losses are minimized due to its
low forward voltage drop, and AC behavior is benign due
to its lack of a signifi cant reverse-recovery time. Schottky
diodes are generally available with reverse-voltage ratings
of up to 60V and even 100V, and are price competitive
with other types.
The use of so-called ultrafast recovery diodes is generally
not recommended. When operating in continuous mode,
the reverse-recovery time exhibited by ultrafast diodes will
result in a slingshot type effect. The power internal switch
will ramp up VIN current into the diode in an attempt to
get it to recover. Then, when the diode has fi nally turned
off, some tens of nanoseconds later, the VSW node volt-
age ramps up at an extremely high dV/dt, perhaps 5 to
even 10V/ns! With real world lead inductances, the VSW
node can easily overshoot the VIN rail. This can result in
poor RFI behavior and if the overshoot is severe enough,
damage the IC itself.
The suggested catch diode (D1) is an International Rectifi er
10MQ060N Schottky. It is rated at 1.5A average forward
current and 60V reverse voltage. Typical forward voltage
is 0.63V at 1A. The diode conducts current only during
switch off time. Peak reverse voltage is equal to regulator
input voltage. Average forward current in normal operation
can be calculated from:
IIVV
V
DAVG OUT IN OUT
IN
()
–
=
()
This formula will not yield values higher than 1.5A with
maximum load current of 1.5A. The only reason to
consider a larger diode is the worst-case condition of a
high input voltage and shorted output. With a shorted
condition, diode current will increase to a typical value
of 2A, determined by peak switch current limit. This is
safe for short periods of time, but it would be prudent to
check with the diode manufacturer if continuous operation
under these conditions must be tolerated.
APPLICATIONS INFORMATION
LT1766/LT1766-5
17
1766fc
APPLICATIONS INFORMATION
BOOST PIN
For most applications, the boost components are a 0.33μF
capacitor and a 1N4148W diode. The anode is typically
connected to the regulated output voltage to generate a
voltage approximately VOUT above VIN to drive the output
stage. However, the output stage discharges the boost ca-
pacitor during the on time of the switch. The output driver
requires at least 3V of headroom throughout this period
to keep the switch fully saturated. If the output voltage is
less than 3.3V, it is recommended that an alternate boost
supply is used. The boost diode can be connected to the
input, although, care must be taken to prevent the 2× VIN
boost voltage from exceeding the BOOST pin absolute
maximum rating. The additional voltage across the switch
driver also increases power loss, reducing effi ciency. If
available, and independent supply can be used with a local
bypass capacitor.
A 0.33μF boost capacitor is recommended for most ap-
plications. Almost any type of fi lm or ceramic capacitor
is suitable, but the ESR should be <1Ω to ensure it can
be fully recharged during the off time of the switch. The
capacitor value is derived from worst-case conditions of
4700ns on time, 42mA boost current and 0.7V discharge
ripple. The boost capacitor value could be reduced under
less demanding conditions, but this will not improve cir-
cuit operation or effi ciency. Under low input voltage and
low load conditions, a higher value capacitor will reduce
discharge ripple and improve start-up operation.
SHUTDOWN FUNCTION AND UNDERVOLTAGE
LOCKOUT
Figure 4 shows how to add undervoltage lockout (UVLO)
to the LT1766. Typically, UVLO is used in situations where
the input supply is
current limited
, or has a relatively high
source resistance. A switching regulator draws constant
power from the source, so source current increases as
source voltage drops. This looks like a negative resistance
load to the source and can cause the source to current limit
or latch low under low source voltage conditions. UVLO
prevents the regulator from operating at source voltages
where these problems might occur.
Threshold voltage for lockout is about 2.38V. A 5.5μA
bias current fl ows
out
of the pin at this threshold. The
internally generated current is used to force a default high
state on the shutdown pin if the pin is left open. When
low shutdown current is not an issue, the error due to this
current can be minimized by making RLO 10k or less. If
shutdown current is an issue, RLO can be raised to 100k,
but the error due to initial bias current and changes with
temperature should be considered.
Rk
RRV V
VR A
LO
HI LO IN
LO
=
()
=−
()
−
()
10
238
238 55
to 100k 25k suggested
.
..μ
V
IN = Minimum input voltage
–
+
–
+
2.38V
0.4V
GND
V
SW
LT1766
INPUT
R
FB
L1
C1
R
HI
1766 F04
OUTPUT
SHDN
STANDBY
IN
TOTAL
SHUTDOWN
5.5μA
R
LO
C2
+
Figure 4. Undervoltage Lockout
LT1766/LT1766-5
18
1766fc
Keep the connections from the resistors to the shutdown
pin short and make sure that interplane or surface ca-
pacitance to the switching nodes are minimized. If high
resistor values are used, the shutdown pin should be
bypassed with a 1000pF capacitor to prevent coupling
problems from the switch node. If hysteresis is desired
in the undervoltage lockout point, a resistor, RFB, can
be added to the output node. Resistor values can be
calculated from:
RRV VV V
RA
RRV V
HI
LO IN OUT
LO
FB HI OUT
=−+
()
+
[]
−
()
=
()
()
238 1
238 55
./
..
/
ΔΔ
Δ
μ
25k suggested for RLO
V
IN = Input voltage at which switching stops as input
voltage descends to trip level
ΔV = Hysteresis in input voltage level
Example: output voltage is 5V, switching is to stop if input
voltage drops below 12V and should not restart unless input
rises back to 13.5V. ΔV is therefore 1.5V and VIN = 12V.
Let RLO = 25k.
R
k
kA
kk
Rk k
HI
FB
=−+
()
+
[]
μ
()
=
()
=
=
()
=
25 12 2 38 1 5 5 1 1 5
238 25 55
25 10 41
224 116
116 5 1 5 387
../ .
.– .
.
.
/.
SYNCHRONIZING
The SYNC input must pass from a logic level low, through
the maximum synchronization threshold with a duty cycle
between 10% and 90%. The input can be driven directly
from a logic level output. The synchronizing range is equal
to
initial
operating frequency up to 700kHz. This means
that
minimum
practical sync frequency is equal to the
worst-case
high
self-oscillating frequency (228kHz), not
the typical operating frequency of 200kHz. Caution should
be used when synchronizing above 265kHz because at
higher sync frequencies the amplitude of the internal slope
compensation used to prevent subharmonic switching is
reduced. This type of subharmonic switching only occurs
at input voltages less than twice output voltage. Higher
inductor values will tend to eliminate this problem. See
Frequency Compensation section for a discussion of an
entirely different cause of subharmonic switching before
assuming that the cause is insuffi cient slope compensa-
tion. Application Note 19 has more details on the theory
of slope compensation.
At power-up, when VC is being clamped by the FB pin (see
Figure 2, Q2), the sync function is disabled. This allows
the frequency foldback to operate in the shorted output
condition. During normal operation, switching frequency is
controlled by the internal oscillator until the FB pin reaches
0.6V, after which the SYNC pin becomes operational. If no
synchronization is required, this pin should be connected
to ground.
LAYOUT CONSIDERATIONS
As with all high frequency switchers, when considering
layout, care must be taken in order to achieve optimal
electrical, thermal and noise performance. For maxi-
mum effi ciency, switch rise and fall times are typically
in the nanosecond range. To prevent noise both radiated
and conducted, the high speed switching current path,
shown in Figure 5, must be kept as short as possible.
This is implemented in the suggested layout of Figure 6.
Shortening this path will also reduce the parasitic trace
inductance of approximately 25nH/inch. At switch off, this
parasitic inductance produces a fl yback spike across the
LT1766 switch. When operating at higher currents and
input voltages, with poor layout, this spike can generate
voltages across the LT1766 that may exceed its absolute
1766 F05
5V
L1
VIN
LT1766
D1 C1C3
HIGH
FREQUENCY
CIRCULATING
PATH
LOAD
Figure 5. High Speed Switching Path
APPLICATIONS INFORMATION
LT1766/LT1766-5
19
1766fc
APPLICATIONS INFORMATION
maximum rating. A ground plane should always be used
under the switcher circuitry to prevent interplane coupling
and overall noise.
The VC and FB components should be kept as far away as
possible from the switch and boost nodes. The LT1766
pinout has been designed to aid in this. The ground for
these components should be separated from the switch
current path. Failure to do so will result in poor stability
or subharmonic like oscillation.
Board layout also has a signifi cant effect on thermal
resistance. Pins 1, 8, 9 and 16, GND, are a continuous
copper plate that runs under the LT1766 die. This is the
best thermal path for heat out of the package. Reducing
the thermal resistance from Pins 1, 8, 9 and 16 onto the
board will reduce die temperature and increase the power
capability of the LT1766. This is achieved by providing as
much copper area as possible around these pins. Add-
ing multiple solder fi lled feedthroughs under and around
these four corner pins to the ground plane will also help.
Similar treatment to the catch diode and coil terminations
will reduce any additional heating effects. For the FE pack-
age, the exposed pad (Pin 17) should be soldered to the
copper ground plane underneath the device.
PARASITIC RESONANCE
Resonance or ringing may sometimes be seen on the
switch node (see Figure 7). Very high frequency ringing
following switch rise time is caused by switch/diode/input
capacitor lead inductance and diode capacitance. Schottky
diodes have very high “Q” junction capacitance that can
ring for many cycles when excited at high frequency. If
total lead length for the input capacitor, diode and switch
path is 1 inch, the inductance will be approximately 25nH.
At switch off, this will produce a spike across the NPN
output device in addition to the input voltage. At higher
currents this spike can be in the order of 10V to 20V
or higher with a poor layout, potentially exceeding the
abso
lute max switch voltage. The path around switch,
catch diode and input capacitor must be kept as short as
possible to ensure reliable operation. When looking at this,
Figure 6. Suggested Layout
GND GND SHDN
SYNC
GND
BOOST
V
IN
SW
PLACE FEEDTHROUGH AROUND
GROUND PINS (4 CORNERS) FOR
GOOD THERMAL CONDUCTIVITY
LT1766
C3
C1
D1 C2
D2
R2
R1
1766 F06
C
FB
C
F
R
C
C
C
L1
MINIMIZE LT1766
C3-D1 LOOP
GND
GND
BIAS
FB
V
C
CONNECT TO
GROUND PLANE
KELVIN SENSE
V
OUT
KEEP FB AND V
C
COMPONENTS
AWAY FROM HIGH FREQUENCY,
HIGH CURRENT COMPONENTS
FOR THE FE PACKAGE, THE
EXPOSED PAD (PIN 17) SHOULD
BE PROPERLY SOLDERED TO
THE GROUND PLANE.
NOTE: BOOST AND BIAS
COPPER TRACES ARE ON
A SEPARATE LAYER FROM
THE GROUND PLANE
GND
V
OUT
V
IN
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
LT1766/LT1766-5
20
1766fc
APPLICATIONS INFORMATION
a >100MHz oscilloscope must be used, and waveforms
should be observed on the leads of the package. This
switch off spike will also cause the SW node to go below
ground. The LT1766 has special circuitry inside which
mitigates this problem, but negative voltages over 0.8V
lasting longer than 10ns should be avoided. Note that
100MHz oscilloscopes are barely fast enough to see the
details of the falling edge overshoot in Figure 7.
A second, much lower frequency ringing is seen during
switch off-time if load current is low enough to allow the
inductor current to fall to zero during part of the switch
off-time (see Figure 8). Switch and diode capacitance
resonate with the inductor to form damped ringing at 1MHz
to 10 MHz. This ringing is not harmful to the regulator
and it has not been shown to contribute signifi cantly to
EMI. Any attempt to damp it with a resistive snubber will
degrade effi ciency.
THERMAL CALCULATIONS
Power dissipation in the LT1766 chip comes from four
sources: switch DC loss, switch AC loss, boost circuit cur-
rent, and input quiescent current. The following formulas
show how to calculate each of these losses. These formulas
assume continuous mode operation, so they should not
be used for calculating effi ciency at light load currents.
Switch loss:
PRI V
VtIVf
SW
SW OUT OUT
IN
EFF OUT IN
=
()( )
+
()()()
2
12(/ )
Boost current loss:
PVI
V
BOOST OUT OUT
IN
=
()
236/
Quiescent current loss:
PV V
Q IN OUT
=
()
+
()
0 0015 0 003..
R
SW = Switch resistance (≈0.3) hot
t
EFF = Effective switch current/voltage overlap time
= (tr + tf + tIr + tIf)
t
r = (VIN/1.2)ns
t
f = (VIN/1.7)ns
t
Ir = tIf = (IOUT/0.05)ns
f = Switch frequency
Example: with VIN = 40V, VOUT = 5V and IOUT = 1A:
Figure 8. Discontinuous Mode Ringing
1μs/DIVV
IN
= 40V
V
OUT
= 5V
L = 47μH
10V/DIV SWITCH NODE
VOLTAGE
INDUCTOR
CURRENT
AT I
OUT
= 0.1A
0.2A/DIV
1766 F08
Figure 7. Switch Node Resonance
50ns/DIV 1766 F07
2V/DIV
SW RISE SW FALL
P
W
PW
PW
SW
BOOST
Q
=
()()()
+
()
()
()( )
()
=+ =
=
()
()
=
=+=
−
03 1 5
40 97 10 1 2 1 40 200 10
004 0388 043
5136
40 002
40 0 0015 5 0 003 0 08
2
93
2
.•/ •
.. .
/.
(. ) (. ) .
Total power dissipation in the IC is given by:
P
TOT = PSW + PBOOST + PQ
= 0.43W + 0.02W + 0.08W = 0.53W
LT1766/LT1766-5
21
1766fc
Thermal resistance for the LT1766 packages is infl uenced
by the presence of internal or backside planes.
SSOP (GN16) package: With a full plane under the GN16
package, thermal resistance will be about 85°C/W.
TSSOP (exposed pad) package: With a full plane under
the TSSOP package, thermal resistance will be about
45°C/W.
To calculate die temperature, use the proper thermal
resistance number for the desired package and add in
worst-case ambient temperature:
T
J = TA + (θJA • PTOT)
When estimating ambient, remember the nearby catch
diode and inductor will also be dissipating power:
PVV V I
V
DIODE F IN OUT LOAD
IN
=( )( – )( )
V
F = Forward voltage of diode (assume 0.63V at 1A)
PW
DIODE ==
(. )( – )() .
063 40 5 1
40 055
P
INDUCTOR = (ILOAD)2 (RL)
R
L = Inductor DC resistance (assume 0.1Ω)
P
INDUCTOR (1)2 (0.1) = 0.1W
Only a portion of the temperature rise in the external inductor
and diode is coupled to the junction of the LT1766. Based
on empirical measurements the thermal effect on LT1766
junction temperature due to power dissipation in the external
inductor and catch diode can be calculated as:
ΔTJ(LT1766) ≈ (PDIODE + PINDUCTOR)(10°C/W)
Using the example calculations for LT1766 dissipation, the
LT1766 die temperature will be estimated as:
T
J = TA + (θJA • PTOT) + [10 • (PDIODE + PINDUCTOR)]
With the GN16 package (θJA = 85°C/W), at an ambient
temperature of 60°C:
T
J = 60 + (85 • 0.53) + (10 • 0.65) = 112°C
With the TSSOP package (θJA = 45°C/W), at an ambient
temperature of 60°C:
T
J = 60 + (45 • 0.53) + (10 • 0.65) = 90°C
Die temperature can peak for certain combinations of VIN,
VOUT and load current. While higher VIN gives greater
switch AC losses, quiescent and catch diode losses, a
lower VIN may generate greater losses due to switch DC
losses. In general, the maximum and minimum VIN levels
should be checked with maximum typical load current
for calculation of the LT1766 die temperature. If a more
accurate die temperature is required, a measurement of
the SYNC pin resistance (to GND) can be used. The SYNC
pin resistance can be measured by forcing a voltage no
greater than 0.5V at the pin and monitoring the pin cur-
rent over temperature in an oven. This should be done
with minimal device power (low VIN and no switching
(VC = 0V)) in order to calibrate SYNC pin resistance with
ambient (oven) temperature.
Note: Some of the internal power dissipation in the IC,
due to BOOST pin voltage, can be transferred outside
of the IC to reduce junction temperature, by increasing
the voltage drop in the path of the boost diode D2 (see
Figure 9). This reduction of junction temperature inside
the IC will allow higher ambient temperature operation for
a given set of conditions. BOOST pin circuitry dissipates
power given by:
PVI V
V
DISS BOOST OUT SW C
IN
()
•( / )•
=36 2
Typically VC2 (the boost voltage across the capacitor C2)
equals Vout. This is because diodes D1 and D2 can be
considered almost equal, where:
V
C2 = VOUT – VFD2 – (–VFD1) = VOUT
Hence the equation used for boost circuitry power dissi-
pation given in the previous Thermal Calculations section
is stated as:
PVI V
V
DISS BOOST OUT SW OUT
IN
() •( / )•
=36
Here it can be seen that boost power dissipation increases
as the square of VOUT
. It is possible, however, to reduce VC2
below VOUT to save power dissipation by increasing the
voltage drop in the path of D2. Care should be taken that
VC2 does not fall below the minimum 3.3V boost voltage
required for full saturation of the internal power switch.
APPLICATIONS INFORMATION
LT1766/LT1766-5
22
1766fc
APPLICATIONS INFORMATION
For an FE package with thermal resistance of 45°C/W,
ambient temperature savings would be, T(ambient) savings
= 0.116W • 45°C/W = 5c. For a GN Package with thermal
resistance of 85°C/W, ambient temperature savings would
be T/(ambient) savings = 0.116 • 85°C/W = 10c. The 7V
zener should be sized for excess of 0.116W operation. The
tolerances of the zener should be considered to ensure
minimum VC2 exceeds 3.3V + VDROOP
.
Input Voltage vs Operating Frequency Considerations
The absolute maximum input supply voltage for the
LT1766 is specifi ed at 60V. This is based solely on internal
semiconductor junction breakdown effects. Due to internal
power dissipation, the actual maximum VIN achievable in
a particular application may be less than this.
A detailed theoretical basis for estimating internal power
loss is given in the section, Thermal Considerations. Note
that AC switching loss is proportional to both operating
frequency and output current. The majority of AC switching
loss is also proportional to the
square
of input voltage.
For example, while the combination of VIN = 40V, VOUT
= 5V at 1A and fOSC = 200kHz may be easily achievable,
simultaneously raising VIN to 60V and fOSC to 700kHz is
not possible. Nevertheless, input voltage
transients
up to
60V can usually be accommodated, assuming the result-
ing increase in internal dissipation is of insuffi cient time
duration to raise die temperature signifi cantly.
A second consideration is controllability. A potential limita-
tion occurs with a high step-down ratio of VIN to VOUT
, as
this requires a correspondingly narrow minimum switch
on time. An approximate expression for this (assuming
continuous mode operation) is given as follows:
Min t VV
Vf
ON OUT F
IN OSC
=+
()
where:
V
IN = Input voltage
V
OUT = Output voltage
V
F = Schottky diode forward drop
f
OSC = Switching frequency
A potential controllability problem arises if the LT1766 is
called upon to produce an on time shorter than it is able
to produce. Feedback loop action will lower then reduce
For output voltages of 5V, VC2 is approximately 5V. During
switch turn on, VC2 will fall as the boost capacitor C2 is
dicharged by the BOOST pin. In the previous BOOST Pin
section, the value of C2 was designed for a 0.7V droop in
VC2 = VDROOP
. Hence, an output voltage as low as 4V would
still allow the minimum 3.3V for the boost function using
the C2 capacitor calculated. If a target output voltage of
12V is required, however, an excess of 8V is placed across
the boost capacitor which is not required for the boost
function but still dissipates additional power.
What is required is a voltage drop in the path of D2 to
achieve minimal power dissipation while still maintaining
minimum boost voltage across C2. A zener, D4, placed in
series with D2 (see Figure 9), drops voltage to C2.
Example : the BOOST pin power dissipation for a 20V input
to 12V output conversion at 1A is given by:
PW
BOOST
==
12 1 36 12
20 02
•( / )• .
If a 7V zener D4 is placed in series with D2, then power
dissipation becomes :
PW
BOOST ==
12 1 36 5
20 0 084
•( / )• .
BOOST
VIN
D1
R1
VOUT
CF
CC
LT1766
SHDN
SYNC
SW
BIAS
FB
VC
GND
C2
C1
L1
D2
R2
1766 F09
C3
VIN
D2 D4
+
RC
Figure 9. Boost Pin, Diode Selection
LT1766/LT1766-5
23
1766fc
APPLICATIONS INFORMATION
the VC control voltage to the point where some sort of
cycle-skipping or odd/even cycle behavior is exhibited.
In summary:
1. Be aware that the simultaneous requirements of high
VIN, high IOUT and high fOSC may not be achievable in
practice due to internal dissipation. The Thermal Con-
siderations section offers a basis to estimate internal
power. In questionable cases a prototype supply should
be built and exercised to verify acceptable operation.
2. The simultaneous requirements of high VIN, low VOUT and
high fOSC can result in an unacceptably short minimum
switch on-time. Cycle skipping and/or odd/even cycle
behavior will result although correct output voltage is
usually maintained.
FREQUENCY COMPENSATION
Before starting on the theoretical analysis of frequency
response, the following should be remembered—the
worse the board layout, the more diffi cult the circuit will
be to stabilize. This is true of almost all high frequency
analog circuits, read the Layout Considerations section
fi rst. Common layout errors that appear as stability prob-
lems are distant placement of input decoupling capacitor
and/or catch diode, and connecting the VC compensation
to a ground track carrying signifi cant switch current. In
addition, the theoretical analysis considers only fi rst order
non-ideal component behavior. For these reasons, it is
important that a fi nal stability check is made with produc-
tion layout and components.
The LT1766 uses current mode control. This alleviates
many of the phase shift problems associated with the
inductor. The basic regulator loop is shown in Figure 10.
The LT1766 can be considered as two gm blocks, the error
amplifi er and the power stage.
Figure 11 shows the overall loop response. At the VC
pin, the frequency compensation components used are:
RC = 2.2k, CC = 0.022μF and CF = 220pF. The output
capacitor used is a 100μF, 10V tantalum capacitor with
typical ESR of 100mΩ.
The ESR of the tantalum output capacitor provides a use-
ful zero in the loop frequency response for maintaining
stability. This ESR, however, contributes signifi cantly to
the ripple voltage at the output (see Output Ripple Volt-
age in the Applications Section). It is possible to reduce
capacitor size and output ripple voltage by replacing the
tantalum output capacitor with a ceramic output capaci-
tor because of its very low ESR. The zero provided by the
tantalum output capacitor must now be reinserted back
into the loop. Alternatively there may be cases where,
even with the tantalum output capacitor, an additional
zero is required in the loop to increase phase margin for
improved transient response.
A zero can be added into the loop by placing a resistor,
RC, at the VC pin in series with the compensation capaci-
tor, CC or by placing a capacitor, CFB, between the output
and the FB pin.
FREQUENCY (Hz)
GAIN (dB)
80
60
40
20
0
–20
–40
PHASE (DEG)
180
150
120
90
60
30
0
1766 F11
GAIN
PHASE
10
VIN = 42V
VOUT = 5V
ILOAD = 500mA
COUT = 100μF, 10V, 0.1Ω
1k 10k 1M100 100k
RC = 2.2k
CC = 22nF
CF = 220pF
Figure 11. Overall Loop Response
–
+
1.22V
V
SW
V
C
LT1766
GND
1766 F10
R1
OUTPUT
ESR
C
F
C
C
R
C
R
O
200k
ERROR
AMPLIFIER
FB
R2
C1
R
LOAD
CURRENT MODE
POWER STAGE
g
m
= 2mho
g
m
=
2000μmho
+
TANTALUM
C
FB
CERAMIC
ESL
C1
Figure 10. Model for Loop Response
LT1766/LT1766-5
24
1766fc
When using RC, the maximum value has two limitations.
First, the combination of output capacitor ESR and RC
may stop the loop rolling off altogether. Second, if the
loop gain is not rolled off suffi ciently at the switching
frequency, output ripple will peturb the VC pin enough to
cause unstable duty cycle switching similar to subharmonic
oscillations. If needed, an additional capacitor, CF , can be
added across the RC/CC network from the VC pin to ground
to further suppress VC ripple voltage.
With a tantalum output capacitor, the LT1766 already in-
cludes a resistor, RC and fi lter capacitor, CF , at the VC pin
(see Figures 10 and 11) to compensate the loop over the
entire VIN range (to allow for stable pulse skipping for high
VIN-to-VOUT ratios ≥10). A ceramic output capacitor can
still be used with a simple adjustment to the resistor RC
for stable operation. (See Ceramic Capacitors section for
stabilizing LT1766). If additional phase margin is required,
a capacitor, CFB, can be inserted between the output and FB
pin but care must be taken for high output voltage applica-
tions. Sudden shorts to the output can create unacceptably
large negative transients on the FB pin.
For VIN-to-VOUT ratios <10, higher loop bandwidths are
possible by readjusting the frequency compensation
components at the VC pin.
When checking loop stability, the circuit should be op-
erated over the applications’s full voltage, current and
temperature range. Proper loop compensation may be
obtained by emperical methods as described in detail in
Application Notes 19 and 76.
CONVERTER WITH BACKUP OUTPUT REGULATOR
In systems with a primary and backup supply, for example,
a battery-powered device with a wall adapter input, the
output of the LT1766 can be held up by the backup supply
with the LT1766 input disconnected. In this condition, the
SW pin will source current into the VIN pin. If the SHDN pin
is held at ground, only the shut down current of 25μA will
be pulled via the SW pin from the second supply. With the
SHDN pin fl oating, the LT1766 will consume its quiescent
operating current of 1.5mA. The VIN pin will also source
current to any other components connected to the input
line. If this load is greater than 10mA or the input could
be shorted to ground, a series Schottky diode must be
added, as shown in Figure 12. With these safeguards,
the output can be held at voltages up to the VIN absolute
maximum rating.
BUCK CONVERTER WITH ADJUSTABLE SOFT-START
Large capacitive loads or high input voltages can cause
high input currents at start-up. Figure 13 shows a circuit
that limits the dv/dt of the output at start-up, controlling
the capacitor charge rate. The buck converter is a typical
confi guration with the addition of R3, R4, CSS and Q1.
As the output starts to rise, Q1 turns on, regulating switch
current via the VC pin to maintain a constant dv/dt at the
output. Output rise time is controlled by the current through
CSS defi ned by R4 and Q1’s VBE. Once the output is in
regulation, Q1 turns off and the circuit operates normally.
R3 is transient protection for the base of Q1.
5V, 1A
REMOVABLE
INPUT
C2
0.33μF
C
F
220pF
R3
54k
D1
10MQ060N
1766 F12
C3
2.2μF
R
C
2.2k
C
C
0.022μF
D3
10MQ060N
D2
1N4148W
L1
47μH
C1
100μF
10V
ALTERNATE
SUPPLY
R4
25k
R1
15.4k
R2
4.99k
BOOST
V
IN
LT1766
SHDN
SYNC
SW
BIAS
FB
V
C
GND +
Figure 12. Dual Source Supply with 25μA Reverse Leakage
APPLICATIONS INFORMATION
LT1766/LT1766-5
25
1766fc
RiseTime RC V
V
SS OUT
BE
=
()( )( )
4
Using the values shown in Figure 10,
Rise Time ms=
()( )
()
=
47 10 15 10 5
07 5
39
••
.
–
The ramp is linear and rise times in the order of 100ms are
possible. Since the circuit is voltage controlled, the ramp
rate is unaffected by load characteristics and maximum
output current is unchanged. Variants of this circuit can
be used for sequencing multiple regulator outputs.
DUAL OUTPUT SEPIC CONVERTER
The circuit in Figure 14 generates both positive and nega-
tive 5V outputs with a single piece of magnetics. The two
inductors shown are actually just two windings on a stan-
dard Coiltronics inductor. The topology for the 5V output
is a standard buck converter. The – 5V topology would be
a simple fl yback winding coupled to the buck converter
if C4 were not present. C4 creates a SEPIC (single-ended
primary inductance converter) topology which improves
regulation and reduces ripple current in L1. Without C4,
the voltage swing on L1B compared to L1A would vary
due to relative loading and coupling losses. C4 provides a
low impedance path to maintain an equal voltage swing in
L1B, improving regulation. In a fl yback converter, during
switch on-time, all the converter’s energy is stored in L1A
only, since no current fl ows in L1B. At switch off, energy
V
OUT1
5V
(SEE DN100
FOR MAX I
OUT
)
V
OUT2
–5V
†
* L1 IS A SINGLE CORE WITH TWO WINDINGS
COILTRONICS #CTX50-3A
†
IF LOAD CAN GO TO ZERO, AN OPTIONAL
PRELOAD OF 1k TO 5k MAY BE USED TO
IMPROVE LOAD REGULATION
D1, D3: 10MQ060N
V
IN
7.5V
TO 60V
GND
1766 F14
C2
0.33μF
C
F
220pF D1
C1
100μF
10V
TANT
C5
100μF
10V
TANT
C3
2.2μF
100V
CER
C4
100μF
10V
TANT
D2
1N4148W
D3
L1A*
50μH
L1B*
R1
15.4k
R2
4.99k
++
+
R
C
2.2k
C
C
0.022μF
BOOST
V
IN
LT1766
SHDN
SYNC
SW
FB
V
C
GND
Figure 14. Dual Output SEPIC Converter
OUTPUT
5V
1A
INPUT
40V
1766 F13
C2
0.33μF
C1
100μF
C
SS
15nF
C
F
220pF
D1
C3
2.2μF
50V
CER
D2
1N4148W
L1
47μH
R1
15.4k
R3
2k
C
C
0.022μF
R2
4.99k
R4
47k
Q1
BOOST BIAS
V
IN
LT1766
SHDN
SYNC
SW
FB
V
C
GND
+
R
C
2.2k
Figure 13. Buck Converter with Adjustable Soft-Start
is transferred by magnetic coupling into L1B, powering
the –5V rail. C4 pulls L1B positive during switch on-time,
causing current to fl ow, and energy to build in L1B and
C4. At switch off, the energy stored in both L1B and C4
supply the –5V rail. This reduces the current in L1A and
changes L1B current waveform from square to triangular.
For details on this circuit, including maximum output cur-
rents, see Design Note 100.
POSITIVE-TO-NEGATIVE CONVERTER
The circuit in Figure 15 is a positive-to-negative topology
using a grounded inductor. It differs from the standard
approach in the way the IC chip derives its feedback signal
because the LT1766 accepts only positive feedback signals.
The ground pin must be tied to the regulated negative
output. A resistor divider to the FB pin then provides the
proper feedback voltage for the chip.
The following equation can be used to calculate maximum
load current for the positive-to-negative converter:
I
IVV
VVfL
VV
VV VV
MAX
PIN OUT
OUT IN OUT IN
OUT IN OUT F
=+
⎡
⎣
⎢⎤
⎦
⎥
++
–()( )
()()()
()(–.)
(–.)()
203
03
APPLICATIONS INFORMATION
LT1766/LT1766-5
26
1766fc
APPLICATIONS INFORMATION
I
P = Maximum rated switch current
V
IN = Minimum input voltage
V
OUT = Output voltage
V
F = Catch diode forward voltage
0.3 = Switch voltage drop at 1.5A
Example: with VIN(MIN) = 5.5V, VOUT = 12V, L = 18μH,
VF = 0.63V, IP = 1.5A: IMAX = 0.280A.
OUTPUT DIVIDER
Refer to Applications Information Feedback Pin Functions
to calculate R1 and R2 for the (negative) output voltage
(from Table 1).
mode formula to calculate minimum inductor needed. If
load current is higher, use the continuous mode formula.
Output current where continuous mode is needed:
IVI
VV VV V
CONT IN P
IN OUT IN OUT F
>+++
()()
()( )
22
4
Minimum inductor discontinuous mode:
LVI
fI
MIN OUT OUT
P
=2
2
()()
()( )
Minimum inductor continuous mode:
LVV
fV V I I VV
V
MIN IN OUT
IN OUT P OUT OUT F
IN
=
++
+
⎛
⎝
⎜⎞
⎠
⎟
⎡
⎣
⎢⎤
⎦
⎥
()( )
()( ) – ()
21
For a 40V to –12V converter using the LT1766 with peak
switch current of 1.5A and a catch diode of 0.63V:
IA
CONT >+++
=
()(.)
()( .)
.
40 1 5
440124012063 0 573
22
For a load current of 0.25A, this says that discontinuous
mode can be used and the minimum inductor needed is
found from:
LH
MIN ==μ
212 025
200 10 1 5 13 3
32
()(.)
(•)(.) .
In practice, the inductor should be increased by about
30% over the calculated minimum to handle losses and
variations in value. This suggests a minimum inductor of
18μH for this application.
Ripple Current in the Input and Output Capacitors
Positive-to-negative converters have high ripple current
in the input capacitor. For long capacitor lifetime, the RMS
value of this current must be less than the high frequency
ripple current rating of the capacitor. The following formula
will give an
approximate
value for RMS ripple current.
This
formula assumes continuous mode and large inductor
value
. Small inductors will give somewhat higher ripple
current, especially in discontinuous mode. The exact
formulas are very complex and appear in Application
OUTPUT**
–12V, 0.25A
INPUT
†
5.5V TO
48V
1766 F15
C2
0.33μF
C
C
R
C
D1
10MQO60N
R1
44.2k
C1
100μF
25V
TANT
C3
2.2μF
100V
CER
D2
†
1N4148W
L1*
18μH
C
F
BOOST
LT1766
V
IN
V
SW
FB
GND V
C
R2
4.99k
* INCREASE L1 TO 30μH OR 60μH FOR HIGHER CURRENT APPLICATIONS.
SEE APPLICATIONS INFORMATION
** MAXIMUM LOAD CURRENT DEPENDS ON MINIMUM INPUT VOLTAGE
AND INDUCTOR SIZE. SEE APPLICATIONS INFORMATION
†
FOR V
IN
> 44V AND V
OUT
= –12V, ADDITIONAL VOLTAGE DROP IN THE
PATH OF D2 IS REQUIRED TO ENSURE BOOST PIN MAXIMUM RATING IS
NOT EXCEEDED. SEE APPLICATIONS INFORMATION (BOOST PIN VOLTAGE)
+
Figure 15. Positive-to-Negative Converter
Inductor Value
The criteria for choosing the inductor is typically based on
ensuring that peak switch current rating is not exceeded.
This gives the lowest value of inductance that can be
used, but in some cases (lower output load currents) it
may give a value that creates unnecessarily high output
ripple voltage.
The diffi culty in calculating the minimum inductor size
needed is that you must fi rst decide whether the switcher
will be in continuous or discontinuous mode at the critical
point where switch current reaches 1.5A. The fi rst step is
to use the following formula to calculate the load current
above which the switcher must use continuous mode. If
your load current is less than this, use the discontinuous
LT1766/LT1766-5
27
1766fc
Note 44, pages 29 and 30. For our purposes here a fudge
factor (ff) is used. The value for ff is about 1.2 for higher
load currents and L ≥15μH. It increases to about 2.0 for
smaller inductors at lower load currents.
Input Capacitor I ff I V
V
RMS OUT OUT
IN
=()( )
ff = 1.2 to 2.0
The output capacitor ripple current for the positive-to-
negative converter is similar to that for a typical buck
regulator—it is a triangular waveform with peak-to-peak
value equal to the peak-to-peak triangular waveform of the
inductor. The low output ripple design in Figure 15 places
the input capacitor between VIN and the regulated negative
output. This placement of the input capacitor signifi cantly
reduces the size required for the output capacitor (versus
placing the input capacitor between VIN and ground).
The peak-to-peak ripple current in both the inductor and
output capacitor (assuming continuous mode) is:
IP-P
P-P
=
==
+
++
=
DC V
fL
DC Duty Cycle VV
VVV
I RMS I
IN
OUT F
OUT IN F
COUT
•
•
()
12
The output ripple voltage for this confi guration is as low
as the typical buck regulator based predominantly on the
inductor’s triangular peak-to-peak ripple current and the
ESR of the chosen capacitor (see Output Ripple Voltage
in Applications Information).
Diode Current
Average
diode current is equal to load current.
Peak
diode
current will be considerably higher.
Peak diode current:
Continuous Mode
IVV
V
VV
LfV V
Discontinuous Mode IV
Lf
OUT IN OUT
IN
IN OUT
IN OUT
OUT OUT
=
+++
=
()()()
()()( )
()( )
()()
2
2
Keep in mind that during start-up and output overloads,
average diode current may be much higher than with nor-
mal loads. Care should be used if diodes rated less than
1A are used, especially if continuous overload conditions
must be tolerated.
BOOST Pin Voltage
To ensure that the BOOST pin voltage does not exceed its
absolute maximum rating of 68V with respect to device
GND pin voltage, care should be taken in the generation of
boost voltage. For the conventional method of generating
boost voltage, shown in Figure 1, the voltage at the BOOST
pin during switch on time is approximately given by:
V
BOOST (GND pin) = (VIN – VGNDPIN) + VC2
where:
V
C2 = (D2+) – VD2 – (D1+) + VD1
= voltage across the boost capacitor
For the positive-to-negative converter shown in Figure 15,
the conventional Buck output node is grounded (D2+) = 0V
and the catch diode (D1+) is connected to the negative
output = VOUT = –12V. Absolute maximum ratings should
also be observed with the GND pin now at –12V. It can be
seen that for VD1 = VD2:
V
C2 = (D2+) – (D1+) = |VOUT| = 12V
The maximum VIN voltage allowed for the device (GND
pin at –12V) is 48V.
The maximum VIN voltage allowed without exceeding the
BOOST pin voltage absolute maximum rating is given by:
V
IN(MAX) = Boost (Max) + (VGNDPIN) – VC2
V
IN(MAX) = 68 + (–12) – 12 = 44V
To increase usable VIN voltage, VC2 must be reduced. This
can be achieved by placing a zener diode VZ1 (anode at
C2+) in series with D2.
Note: A maximum limit on VZ1 must be observed to
ensure a minimum VC2 is maintained on the boost
capacitor; referred to as VBOOST(MIN) in the Electrical
Characteristics.
APPLICATIONS INFORMATION
LT1766/LT1766-5
28
1766fc
PACKAGE DESCRIPTION
FE Package
16-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663)
Exposed Pad Variation BB
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
FE16 (BB) TSSOP 0204
0.09 – 0.20
(.0035 – .0079)
0o – 8o
0.25
REF
0.50 – 0.75
(.020 – .030)
4.30 – 4.50*
(.169 – .177)
1.10
(.0433)
MAX
0.05 – 0.15
(.002 – .006)
0.65
(.0256)
BSC 0.195 – 0.30
(.0077 – .0118)
TYP
MILLIMETERS
(INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
RECOMMENDED SOLDER PAD LAYOUT
0.45 p0.05
0.65 BSC
4.50 p0.10
6.60 p0.10
1.05 p0.10
2.94
(.116)
3.58
(.141)
SEE NOTE 4
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
134
5678
10 9
4.90 – 5.10*
(.193 – .201)
16 1514 13 12 11
2.94
(.116)
2
3.58
(.141)
6.40
(.252)
BSC
GN16 (SSOP) 0204
.016 – .050
(0.406 – 1.270)
.015 p .004
(0.38 p 0.10) s 45o
0o – 8o TYP
.007 – .0098
(0.178 – 0.249)
.0532 – .0688
(1.35 – 1.75)
.008 – .012
(0.203 – 0.305)
TYP
.004 – .0098
(0.102 – 0.249)
.0250
(0.635)
BSC
12
345678
.229 – .244
(5.817 – 6.198)
.150 – .157**
(3.810 – 3.988)
16 15 14 13
.189 – .196*
(4.801 – 4.978)
12 11 10 9
.009
(0.229)
REF
.254 MIN
RECOMMENDED SOLDER PAD LAYOUT
.150 – .165
.0250 BSC.0165 p.0015
.045 p.005
* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
INCHES
(MILLIMETERS)
NOTE:
1. CONTROLLING DIMENSION: INCHES
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
LT1766/LT1766-5
29
1766fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
C 03/10 Removed LT1766HGN from Order Information 2
(Revision history begins at Rev C)
LT1766/LT1766-5
30
1766fc
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2001
LT/TP 0310 REV C • PRINTED IN USA
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VIN: 3V to 25V, VOUT(MIN): 1.20V, IQ: 2.5mA,
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LT1956 60V, 1.2A (IOUT), 500kHz, High Effi ciency
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VIN: 5.5V to 60V, VOUT(MIN): 1.20V, IQ: 2.5mA,
ISD: 25μA, TSSOP16/E
LT1976 60V, 1.2A (IOUT), 200kHz, Micropower (IQ = 100μA), High Effi ciency
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VIN: 3.3V to 60V, VOUT(MIN): 1.20V, IQ: 100μA,
ISD: <1μA, TSSOP16/E
LT3010 80V, 50mA, Low Noise Linear Regulator VIN: 1.5V to 80V, VOUT(MIN): 1.28V, IQ: 30μA,
ISD: <1μA, MS8E
LTC3412 2.5A (IOUT), 4MHz, Synchronous Step-Down DC/DC Converter VIN: 2.5V to 5.5V, VOUT(MIN): 0.8V, IQ: 60μA,
ISD: <1μA, TSSOP16E
LTC3414 4A (IOUT), 4MHz, Synchronous Step-Down DC/DC Converter VIN: 2.3V to 5.5V, VOUT(MIN): 0.8V, IQ: 64μA,
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