Rev. 1.6 12/15 Copyright © 2015 by Silicon Laboratories Si5338
Si5338
I2C-PROGRAMMABLE ANY-FREQUENCY, ANY-OUTPUT
QUAD CLOCK GENERATOR
Features
Applications
Description
The Si5338 is a high-performance, low-jitter clock generator capable of
synthesizing any frequency on each of the device's four output drivers. This timing
IC is capable of replacing up to four different frequency crystal oscillators or
operating as a frequency translator. Using its patented MultiSynth™ technology,
the Si5338 allows generation of four independent clocks with 0 ppm precision.
Each output clock is independ ently configurable to support various si gnal formats
and supply voltages. The Si5338 provides low-jitter frequency synthesis in a
space-saving 4 x 4 mm QFN package. The device is programmable via an I2C/
SMBus-compatible serial interface and supports operation from a 1.8, 2.5, or
3.3 V core supply. I2C device prog ramming is made easy with the ClockBuilder™
Desktop software available at www.silabs.com/ClockBuilder. Measuring PCIe
clock jitter is quick and easy with the Silicon Labs PCIe Clock Jitter Tool.
Download it for free at www.silabs.com/pcie-learningcenter.
Low power MultiSynth™ technology
enables independent, any-frequ ency
synthesis on four differential output
drivers
PCIe Gen 1/2/3/4 Common Clock and
Gen 3 SRNS compliant
Highly-configurable output drivers with
up to four differential outputs, eight
single-ended clock outputs, or a
combination of both
Low phase jitter of 0.7 ps RMS typ
High precision synthesis allows true
zero ppm frequency accuracy on all
outputs
Flexible input reference:
External crystal: 8 to 30 MHz
CMOS input: 5 to 200 MHz
SSTL/HSTL input: 5 to 350 MHz
Diff erential input: 5 to 710 MHz
Independently configurable outputs
support any frequency or format:
LVPECL/LVDS: 0.16 to 710 MHz
HCSL: 0.16 to 250 MHz
CMOS: 0.16 to 200 MHz
SSTL/HSTL: 0.16 to 350 MHz
Independent output voltage per driver:
1.5, 1.8, 2.5, or 3.3 V
Single supply core with excellent
PSRR: 1.8, 2.5 , 3.3 V
Independent frequency increment/
decrement feature enables
glitchless frequency adjustments in
1 ppm steps
Independent phase adjustment on
each of the output drivers with an
accuracy of <20 ps steps
Highly configurable spread
spectrum (SSC) on any output:
Any frequency from 5 to 350 MHz
Any spread from 0.5 to 5.0%
Any modulation rate from 33 to
63 kHz
External feedback mode allows
zero-delay mode
Loss of lock and loss of signal
alarms
I2C/SMBus compatible interface
Easy to use programming software
Small size: 4 x 4 mm, 24-QFN
Low power: 45 mA core supply typ
Wide temperature range: –40 to
+85 °C
Ethernet switch/router
PCIe Gen1/2/3/4
Broadcast video/audi o timing
Processor and FPGA clocking
Any-frequency clock conversion
MSAN/DSLAM/PON
Fibre Channel, SAN
Telecom line cards
1 GbE and 10 GbE
Ordering Information:
See page 42.
Pin Assignments
IN1
CLK2B
CLK2A
VDDO2
VDDO1
CLK1B
CLK1A
VDD VDD
SCL
CLK3A
CLK3B
INTR
SDA
VDDO0
CLK0B
CLK0A
RSVD_GND
VDDO3
GND
GND
Pad
5
4
3
2
1
613
10
987
IN2
IN3
IN4
IN5
IN6
Top View
11 12
15
14
16
17
18
192021
222324
Si5338
2 Rev. 1.6
Functional Block Diagram
Phase
Frequency
Detector
Loop
Filter VCO
CLK0A
÷P2
VDDO1
VDDO2
VDDO3
VDDO0
MultiSynth
÷M0
I2C_LSB/PDEC/FDEC
OEB/PINC/FINC
CLK0B
CLK1A
CLK1B
CLK2A
CLK2B
CLK3A
CLK3B
÷P1
IN3
IN2
IN1
÷R1
MultiSynth
÷M1
MultiSynth
÷M2
MultiSynth
÷M3
IN6
IN4
IN5
Osc
MultiSynth
÷N
Control NVM
(OTP)
÷R0
÷R2
÷R3
Synthesis
Stage 1
(PLL)
Synthesis
Stage 2 Output
Stage
P1DIV_IN
Control & Memory
SCL
SDA
INTR
VDD
ref
fb
RAM
P2DIV_IN
noclk
noclk
Si5338
Rev. 1.6 3
TABLE OF CONTENTS
Section Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2. Typical Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.2. Input Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.3. Synthesis Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.4. Output Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.5. Configuring the Si5338 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.6. Status Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.7. Output Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.8. Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.9. Reset Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.10. Features of the Si5338 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4. Applications of the Si5338 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.1. Free-Running Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.2. Synchronous Frequency Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.3. Configurable Buffer and Level Translator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5. I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6. Si5338 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
8. Device Pinout by Part Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
9. Package Outline: 24-Lead QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
10. Recommended PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
11. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
11.1. Si5338 Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
11.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
12. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
13. Device Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Si5338
4 Rev. 1.6
1. Electrical Specifications
Table 1. Recommended Operating Conditions
(VDD = 1.8 V –5% to +10%, 2. 5 V ±10%, or 3.3 V ±10%, TA= –40 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Ambient Temperature TA–40 25 85 °C
Core Supply Voltage VDD
2.97 3.3 3.63 V
2.25 2.5 2.75 V
1.71 1.8 1.98 V
Output Buffer Supply
Voltage VDDOn 1.4 — 3.63 V
Note: All minimum and maximu m spec ifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted.
Table 2. Absolute Maximum Ratings1
Parameter Symbol Test Condition Value Unit
DC Supply Voltage VDD –0.5 to 3.8 V
Storage Temperature Range TSTG –55 to 150 °C
ESD Tolerance HBM
(100 pF, 1.5 k)2.5 kV
ESD Tolerance CDM 550 V
ESD Tolerance MM 175 V
Latch-up Tolerance JESD78 Compliant
Junction Temperature TJ150 °C
Peak Soldering Reflow Temperature2260 °C
Notes:
1. Permanent device damage may occur if the absolute maximum ratings are exceeded. F unctional operation should be
restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
2. Refer to JEDEC J-STD-020 standard for more information.
Si5338
Rev. 1.6 5
Table 3. DC Characteristics
(VDD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, TA= –40 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Core Supply Current IDD 100 MHz on all outputs,
25 MHz refclk —4560mA
Core Supply Current
(Buffer Mode) IDDB 50 MHz refclk — 12 — mA
Output Buffer Supply Current IDDOx
LVPECL, 710 MHz — — 30 mA
LVDS, 710 MHz — — 8 mA
HCSL, 250 MHz
2pF load ——20mA
CML, 350 MHz — 12 — mA
SSTL, 350 MHz — — 19 mA
CMOS, 50 MHz
15 pF load1—6 9mA
CMOS, 200 MHz1,2
3.3 V VDD0 —1318mA
CMOS, 200 MHz1,2
2.5 V —1014mA
CMOS, 200 MHz1,2
1.8 V —710mA
HSTL, 350 MHz — — 19 mA
Notes:
1. Single CMOS driver active.
2. Measured into a 5” 50 trace with 2 pF load.
Table 4. Thermal Characteristics
Parameter Symbol Test Condition Value Unit
Thermal Resistance
Junction to Ambient JA Still Air 37 °C/W
Thermal Resistance
Junction to Case JC Still Air 10 °C/W
Si5338
6 Rev. 1.6
Table 5. Performance Characteristics
(VDD = 1.8 V –5% to +10%, 2. 5 V ±10%, or 3.3 V ±10%, TA= –40 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Unit
PLL Acquisition Time tACQ ——25 ms
PLL Tracking Range fTRACK 5000 20000 — ppm
PLL Loop Bandwidth fBW —1.6— MHz
MultiSynth Frequency
Synthesis Resolution fRES Output frequency < Fvco/8 0 0 1 ppb
CLKIN Loss of Signal Detect
Time tLOS —2.6 5 µs
CLKIN Loss of Signal Release
Time tLOSRLS 0.01 0.2 1 µs
PLL Loss of Lock Detect Time tLOL —510ms
POR to Output Clock Valid
(Pre-programmed Devices) tRDY —— 2 ms
Input-to-Output Propagation
Delay tPROP Buffer Mode
(PLL Bypass) —2.5 4 ns
Output-Output Skew tDSKEW Rn divider = 11——100 ps
POR to I2C Ready ——15 ms
Programmable Initial
Phase Offset POFFSET –45 — +45 ns
Phase Increm ent/Decrement
Accuracy PSTEP ——20 ps
Phase Increm ent/Decrement
Range PRANGE –45 — +45 ns
MultiSynth range for phase
increment/decrement fPRANGE 5—Fvco/8
2MHz
Phase Increm ent/Decrement
Update Time PUPDATE Pin control2,3
MultiSynth output >18 MHz 667 — — ns
Notes:
1. Outputs at integer-related frequencies and using the same driver format. See "3.10.3. Programmable Initial Phase
Offset" on page 27.
2. The maximum step size is only limited by the register lengths; however, the MultiSynth output frequency must be kept
between 5 MHz and Fvco/8.
3. Update rate via I2C is also limited by the time it takes to perform a write operation.
4. Default value is 0.5% down spread.
5. Default value is ~31.5 k Hz.
Si5338
Rev. 1.6 7
Phase Increm ent/Decrement
Update Time PUPDATE Pin control2,3
MultiSynth output <18 MHz
Number of periods of
MultiSynth output frequency
—1012Periods
Frequency Increment/
Decrement Step Size fSTEP R divider not used 1 — See
Note 2ppm
MultiSynth range for frequency
increment/decrement fRANGE R divider not used 5 — Fvco/8 MHz
Frequency Increment/
Decrement Update Time fUPDATE Pin control2,3
MultiSynth output >18 MHz ——667 ns
Frequency Increment/
Decrement Update Time fUPDATE Pin control2,3
MultiSynth output <18 MHz
Number of periods of
MultiSynth output frequency
—1012Periods
Spread Spectrum PP
Frequency Deviation SSDEV MultiSynth Output < ~Fvco/8 0.1 — 5.04%
Spread Spectrum Modulation
Rate SSDEV MultiSynth Output < ~Fvco/8 30 — 635kHz
Table 5. Performance Characteristics (Continued)
(VDD = 1.8 V –5% to +10%, 2. 5 V ±10%, or 3.3 V ±10%, TA= –40 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. Outputs at integer-related frequencies and using the same driver format. See "3.10.3. Programmable Initial Phase
Offset" on page 27.
2. The maximum step size is only limited by the register lengths; however, the MultiSynth output frequency must be kept
between 5 MHz and Fvco/8.
3. Update rate via I2C is also limited by the time it takes to perform a write operation.
4. Default value is 0.5% down spread.
5. Default value is ~31.5 k Hz.
Si5338
8 Rev. 1.6
Table 6. Input and Output Clock Characteristics
(VDD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, TA= –40 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Input Clock (AC Coupled Differential Input Clocks on Pins IN1/2, IN5/6)1
Frequency fIN 5—710MHz
Differential Voltage
Swing VPP 710 MHz input 0.4 — 2.4 VPP
Rise/Fall Time2tR/tF20%–80% — — 1.0 ns
Duty Cycle DC < 1 ns tr/tf 40 — 60 %
Duty Cycle DC
(PLL bypass)3< 1 ns tr/tf 45 — 55 %
Input Impedance1RIN 10 — — k
Input Capacitance CIN —3.5—pF
Input Clock (DC-Coupled Single -Ended Input Clock on Pins IN3/4)
Frequency fIN CMOS 5 — 200 MHz
Input Voltage VI–0.1 — 3.73 V
Input Voltage Swing 200 MHz 0.8 — VDD+10% Vpp
Rise/Fall Time4tR/tF10%–90% — — 4 ns
Rise/Fall Time4tR/tF20%–80% — — 2.3 ns
Duty Cycle5DC < 4 ns tr/tf 40 — 60 %
Input Capacitance CIN —2.0—pF
Output Clocks (Differential)
Frequency6fOUT LVPECL, LVDS,
CML 0.16 — 350 MHz
367 — 473.33 MHz
550 — 710 MHz
HCSL 0.16 — 250 MHz
Notes:
1. Use an external 100 resistor to prov ide load termination for a differential clock. See Figure 3.
2. For best jitter performance, keep the midpoint differential input slew rate on pins 1,2,5,6 faster than 0.3 V/ns.
3. Minimum input frequency in clo ck bu ffer mode (PLL bypass) is 5 MHz. Operation to 1 MHz is also supported in buffer
mode, but loss-of-signal (LOS) status is not functional.
4. For best jitter performance, keep the mid point input single ended slew rate on pins 3 or 4 faster than 1 V/ns.
5. Not in PLL bypass mode.
6. Only two unique frequencies above 350 MHz can be simultaneously output, Fvco/4 and Fvco/6. See "3.3. Synthesis
Stages" on page 19.
7. CML output format requires ac-coupling of the differential outputs to a differential 100 load at th e receiver.
8. Includes effect of internal series 22 resistor.
Si5338
Rev. 1.6 9
LVPECL Output
Voltage VOC common mode — VDDO–
1.45 V —V
VSEPP peak-to-peak sin-
gle-ended swing 0.55 0.8 0.96 VPP
LVDS Outp ut Voltage
(2.5/3.3 V) VOC common mode 1.125 1.2 1.275 V
VSEPP Peak-to-Peak
Single-Ended
Swing
0.25 0.35 0.45 VPP
LVDS Output
Voltage (1.8 V) VOC Common Mode 0.8 0.875 0.95 V
VSEPP Peak-to-Peak
Single-Ended
Swing
0.25 0.35 0.45 VPP
HCSL Output Voltage VOC Common Mode 0.35 0.375 0.400 V
VSEPP Peak-to-Peak
Single-Ended
Swing
0.575 0.725 0.85 VPP
CML Output Voltage VOC Common Mode — See Note 7—V
VSEPP Peak-to-Peak
Single-Ended
Swing
0.67 0.860 1.07 VPP
Rise/Fall Time tR/tF20%–80% — — 450 ps
Duty Cycle5DC 45 — 55 %
Output Clocks (Single-Ended)
Frequency fOUT CMOS 0.16 — 200 MHz
SSTL, HSTL 0.16 — 350 MHz
CMOS 20%–80%
Rise/Fall Time tR/tF2 pF load — 0.45 0.85 ns
CMOS 20%–80%
Rise/Fall Time tR/tF15 pF load — — 2.0 ns
Table 6. Input and Output Clock Characteristics (Continued)
(VDD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, TA= –40 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. Use an external 100 resistor to prov ide load termination for a differential clock. See Figure 3.
2. For best jitter performance, keep the midpoint differential input slew rate on pins 1,2,5,6 faster than 0.3 V/ns.
3. Minimum input frequency in clo ck bu ffer mode (PLL bypass) is 5 MHz. Operation to 1 MHz is also supported in buffer
mode, but loss-of-signal (LOS) status is not functional.
4. For best jitter performance, keep the mid point input single ended slew rate on pins 3 or 4 faster than 1 V/ns.
5. Not in PLL bypass mode.
6. Only two unique frequencies above 350 MHz can be simultaneously output, Fvco/4 and Fvco/6. See "3.3. Synthesis
Stages" on page 19.
7. CML output format requires ac-coupling of the differential outputs to a differential 100 load at th e receiver.
8. Includes effect of internal series 22 resistor.
Si5338
10 Rev. 1.6
CMOS Output
Resistance —50—
SSTL Output
Resistance —50—
HSTL Output
Resistance —50—
CMOS Output Volt-
age8VOH 4 mA load VDDO – 0.3 — V
VOL 4 mA load — 0.3 V
SSTL Output Voltage VOH SSTL-3
VDDOx = 2.97 to
3.63 V
0.45xVDDO+0.41 — — V
VOL — — 0.45xVDDO
–0.41 V
VOH SSTL-2
VDDOx = 2.25 to
2.75 V
0.5xVDDO+0.41 — — V
VOL — — 0.5xVDDO–
0.41 V
VOH SSTL-18
VDDOx = 1.71 to
1.98 V
0.5xVDDO+0.34 — V
VOL — — 0.5xVDDO–
0.34 V
HSTL Output Voltag e VOH VDDO = 1.4 to
1.6 V 0.5xVDDO+0.3 — — V
VOL — — 0.5xVDDO –
0.3 V
Duty Cycle5DC 45 — 55 %
Table 6. Input and Output Clock Characteristics (Continued)
(VDD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, TA= –40 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. Use an external 100 resistor to prov ide load termination for a differential clock. See Figure 3.
2. For best jitter performance, keep the midpoint differential input slew rate on pins 1,2,5,6 faster than 0.3 V/ns.
3. Minimum input frequency in clo ck bu ffer mode (PLL bypass) is 5 MHz. Operation to 1 MHz is also supported in buffer
mode, but loss-of-signal (LOS) status is not functional.
4. For best jitter performance, keep the mid point input single ended slew rate on pins 3 or 4 faster than 1 V/ns.
5. Not in PLL bypass mode.
6. Only two unique frequencies above 350 MHz can be simultaneously output, Fvco/4 and Fvco/6. See "3.3. Synthesis
Stages" on page 19.
7. CML output format requires ac-coupling of the differential outputs to a differential 100 load at th e receiver.
8. Includes effect of internal series 22 resistor.
Si5338
Rev. 1.6 11
Table 7. Control Pins
(VDD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, TA= –40 to 85 °C)
Parameter Symbol Condition Min Typ Max Unit
Input Control Pins (IN3, IN4)
Input Voltage Low VIL –0.1 — 0.3 x VDD V
Input Voltage High VIH 0.7 x VDD —3.73V
Input Capacitance CIN —— 4pF
Input Resist ance RIN —20—k
Output Control Pins (INTR)
Output Voltage Low VOL ISINK =3mA 0 — 0.4 V
Rise/Fall Time 20–80% tR/tFCL< 10 pf, pull up 1k— — 10 ns
Table 8. Crystal Specifications for 8 to 11 MHz
Parameter Symbol Min Typ Max Unit
Crystal Frequency fXTAL 8—11MHz
Load Capacitance (on- chip differential) cL (supported)* 11 12 13 pF
cL (recommended) 17 18 19 pF
Crystal Output Capacitance cO—— 6pF
Equivalent Series Resistance rESR ——300
Crystal Max Drive Level dL100 — — µW
*Note: See "AN360: Crystal Selection Guide for Si533x and Si5355/56 Devices" for how to adjust the registers to
accommodate a 12 p F crystal CL.
Table 9. Crystal Specifications for 11 to 19 MHz
Parameter Symbol Min Typ Max Unit
Crystal Frequency fXTAL 11 — 19 MHz
Load Capacitance (on- chip differential) cL (supported)* 11 12 13 pF
cL (recommended) 17 18 19 pF
Crystal Output Capacitance cO—— 5pF
Equivalent Series Resistance rESR ——200
Crystal Max Drive Level dL100 — — µW
*Note: See "AN360: Crystal Selection Guide for Si533x and Si5355/56 Devices" for how to adjust the registers to
accommodate a 12 p F crystal CL.
Si5338
12 Rev. 1.6
Table 10. Crystal Specifications for 19 to 26 MHz
Parameter Symbol Min Typ Max Unit
Crystal Frequency fXTAL 19 26 MHz
Load Capacitance (on-chip differential) cL (supported)* 11 12 13 pF
cL (recommended) 17 18 19 pF
Crystal Output Capacitance cO5pF
Equivalent Series Resistance rESR 100
Crystal Max Drive Level dL100 µW
*Note: See "AN360: Crystal Selection Guide for Si533x and Si53 55/56 Devices" for how to adjust the registers to
accommodate a 12 pF crystal CL.
Table 11. Crystal Specifications for 26 to 30 MHz
Parameter Symbol Min Typ Max Unit
Crystal Frequency fXTAL 26 30 MHz
Load Capacitance (on-chip differential) cL (supported)* 11 12 13 pF
cL (recommended) 17 18 19 pF
Crystal Output Capacitance cO5pF
Equivalent Series Resistance rESR 75
Crystal Max Drive Level dL100 µW
*Note: See "AN360: Crystal Selection Guide for Si533x and Si5355/56 Devices" for how to adjust the registers to
accommodate a 12 pF crystal CL.
Si5338
Rev. 1.6 13
Table 12. Jitter Sp ecifications1,2,3
(VDD = 1.8 V –5% to +10%, 2. 5 V ±10%, or 3.3 V ±10%, TA= –40 to 85 °C)
Parameter S y mbo l Test Condition Min Typ Max Unit
GbE Random Jitter
(12kHz–20MHz)
4JGbE CLKIN = 25 MHz
All CLKn at 125 MHz5— 0.7 1 ps RMS
GbE Random Jitter
(1.875–20 MHz) RJGbE CLKIN = 25 MHz
All CLKn at 125 MHz5— 0.38 0.79 ps RMS
OC-12 Random Jitte r
(12 kHz–5 MHz) JOC12 CLKIN = 19.44 MHz
All CLKn at
155.52 MHz5— 0.7 1 ps RMS
PCI Express 1.1 Common
Clocked Total Jitter6— 20.1 33.6 ps pk-pk
PCI Express 2.1 Common
Clocked
RMS Jitter6, 10 kHz to
1.5 MHz — 0.15 1.47 ps RMS
RMS Jitter6, 1.5 MHz to
50 MHz — 0.58 0.75 ps RMS
PCI Express 3.0 Common
Clocked RMS Jitter6— 0.15 0.45 ps RMS
PCIe Gen 3 Separate
Reference No Spread,
SRNS
PLL BW of 2–4 or
2–5 MHz,
CDR = 10 MHz — 0.11 0.32 ps RMS
PCIe Gen 4,
Common Clock
PLL BW of 2–4 or
2–5 MHz,
CDR = 10 MHz — 0.15 0.45 ps RMS
Period Jitter JPER N = 10,000 cycles7— 10 30 ps pk-pk
Notes:
1. All jitter measurements apply for LVDS/HCSL/LVPECL/CML output format with a low noise differential input clock and
are made with an Agilent 90804 oscilloscop e. All RJ measurements use RJ/DJ separation.
2. For best jitter performance, keep the single ended clock input slew rates at Pins 3 and 4 more than 1.0 V/ns and the
differential clock input slew rates more than 0.3 V/ns.
3. All jitter data in this table is based upon all output formats being differential. When single-ended outputs are used, there
is the potential that the output jitter may increase due to the nature of single-ended outputs. If your configuration
implements any single-ended output and any output is required to have jitter less than 3 ps rms, contact Silicon Labs
for support to validate your configuration and ensure the best jitter performance. In many configurations, CMOS
outputs have little to no effect upon jitter.
4. DJ for PCI and GbE is < 5 ps pp
5. Output MultiSynth in Integer mode.
6. All output clocks 100 MHz HCSL format. Jitter is from the PCIE jitter filter combination that produces the highest jitter.
See AN562 for details. Jitter is measured with the Intel Clock Jitter Tool, Ver. 1.6.4.
7. Input frequency to the Phase Detector between 25 and 40 MHz and any output frequency > 5MHz.
8. Measured in accordance with JEDEC standard 65.
9. Rj is multiplied by 14; estimate the pp jitter from Rj over 212 rising edges.
10. Gen 4 specifications based on the PCI-Express Base Specification 4.0 rev. 0.5.
11. Download the Silicon Labs PCIe Clock Jitter Tool at www.silabs.com/pcie-learningcenter.
Si5338
14 Rev. 1.6
Cycle-Cycle Ji tter JCC
N = 10,000 cycles
Output MultiSynth
operated in integer or
fractional m ode 7
— 9 29 ps pk8
Random Jitter
(12kHz–20MHz) RJOutput and feedback
MultiSynth in integer or
fractional m ode 7— 0.7 1.5 ps RMS
Deterministic Jitter DJ
Output MultiSynth
operated in fractional
mode7—315ps pk-pk
Output MultiSynth
operated in integer
mode7—210ps pk-pk
Total Jitter
(12kHz–20MHz) TJ=D
J+14xRJ
(See Note 9)
Output MultiSynth
operated in fractional
mode7— 13 36 ps pk-pk
Output MultiSynth
operated in integer
mode7— 12 20 ps pk-pk
Table 12. Jitter Sp ecifications1,2,3 (Continued)
(VDD = 1.8 V –5% to +10%, 2. 5 V ±10%, or 3.3 V ±10%, TA= –40 to 85 °C)
Parameter S y mbo l Test Condition Min Typ Max Unit
Notes:
1. All jitter measurements apply for LVDS/HCSL/LVPECL/CML output format with a low noise differential input clock and
are made with an Agilent 90804 oscilloscop e. All RJ measurements use RJ/DJ separation.
2. For best jitter performance, keep the single ended clock input slew rates at Pins 3 and 4 more than 1.0 V/ns and the
differential clock input slew rates more than 0.3 V/ns.
3. All jitter data in this table is based upon all output formats being differential. When single-ended outputs are used, there
is the potential that the output jitter may increase due to the nature of single-ended outputs. If your configuration
implements any single-ended output and any output is required to have jitter less than 3 ps rms, contact Silicon Labs
for support to validate your configuration and ensure the best jitter performance. In many configurations, CMOS
outputs have little to no effect upon jitter.
4. DJ for PCI and GbE is < 5 ps pp
5. Output MultiSynth in Integer mode.
6. All output clocks 100 MHz HCSL format. Jitter is from the PCIE jitter filter combination that produces the highest jitter.
See AN562 for details. Jitter is measured with the Intel Clock Jitter Tool, Ver. 1.6.4.
7. Input frequency to the Phase Detector between 25 and 40 MHz and any output frequency > 5MHz.
8. Measured in accordance with JEDEC standard 65.
9. Rj is multiplied by 14; estimate the pp jitter from Rj over 212 rising edges.
10. Gen 4 specifications based on the PCI-Express Base Specification 4.0 rev. 0.5.
11. Download the Silicon Labs PCIe Clock Jitter Tool at www.silabs.com/pcie-learningcenter.
Si5338
Rev. 1.6 15
Table 13. Jitter Specifications, Clock Buffer Mode (PLL Bypass)*
(VDD = 1.8 V –5% to +10%, 2. 5 V ±10%, or 3.3 V ±10%, TA= –40 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Additive Phase Jitter
(12kHz–20MHz) tRPHASE
0.7 V pk-pk differential input
clock at 622.08 MHz with
70 ps rise/fall time — 0.165 — ps RMS
Additive Phase Jitter
(50kHz–80MHz) tRPHASEWB
0.7 V pk-pk differential input
clock at 622.08 MHz with
70 ps rise/fall time — 0.225 — ps RMS
*Note: All outputs are in Clock Buffer mode (PLL Bypass).
Table 14. Typical Phase Noise Performance
Offset Frequency 25 MHz XTAL
to 156.25 MHz 27 MHz Ref In
to 148.3517 MHz 19.44 MHz Ref In
to 155.52 MHz Units
100 Hz –90 –87 –110 dBc/Hz
1 kHz –120 –117 –116 dBc/Hz
10 kHz –126 –123 –123 dBc/Hz
100 kHz –132 –130 –128 dBc/Hz
1 MHz –132 –132 –128 dBc/Hz
10 MHz –145 –145 –145 dBc/Hz
Si5338
16 Rev. 1.6
Table 15. I2C Specifications (SCL,SDA)1
Parameter S ymbol Test Condition Standard Mode Fast Mode Unit
Min Max Min Max
LOW Level
Input Voltage VILI2C –0.5 0.3 x VDDI2
C –0.5 0.3 x VDDI2C2V
HIGH Level
Input Voltage VIHI2C 0.7 x VDDI2
C
3.63 0.7 x VDDI2C23.63 V
Hysteresis of
Schmitt Trigger
Inputs
VHYS N/A N/A 0.1 — V
LOW Level Out-
put Voltage
(open drain or
open collector)
at 3 mA Sink
Current
VOLI2C2 V
DDI2C2= 2.5/3.3 V 0 0.4 0 0.4 V
VDDI2C2= 1.8 V N/A N/A 0 0.2 x VDDI2C V
Input Current II2C –10 10 –10 10 µA
Capacit ance for
each I/O Pin CI2C V
IN = –0. 1 to VDDI2C —4 — 4pF
I2C Bus Time-
out — Timeout Enabled 25 35 25 35 ms
Data Rate Standard Mode 100 400 kbps
Hold Time
(Repeated)
START
Condition
tHD:STA 4.0 — 0.6 — s
Set-Up T i me for
a Repeated
START Condi-
tion
tSU:STA 4.7 — 0.6 — s
Data Hold
Time3,4 tHD:DAT 100 — 100 — ns
Data Set-Up
Time tSU:DAT 250 — 150 — ns
Notes:
1. Refer to NXP’s UM10204 I2C-bus specification and user manual, Revision 03, for further details:
www.nxp.com/acrobat_download/usermanuals/UM10204_3.pdf.
2. I2C pullup voltages (VDDI2C) of 1.71 to 3.63 V are supported. Must write register 27[7] = 1 if the I2C bus voltage is less
than 2.5 V to maintain compatibility with the I2C bus standard.
3. Hold time is defined as the time that data should hold its logical value after clock has transitioned to a logic low.
4. Guaranteed by characterization.
Si5338
Rev. 1.6 17
2. Typical Application Circuits
Si5338C
16 15 1120247
VDDOA
VDDOB
VDDOC
VDDOD
VDD
VDD
23
GND
GND
PAD23 PAD
+3.3 V
0.1 uF Power Supply
Decoupling Capa citors
(1 per VDD or VDDOx pin)
1
2
27 MHz
XTAL IN1
IN2
Optional XTAL for
Free-run Applications
I2C Bus
I2C Address = 111 0000 or 111 0001
+3.3 V
1k1k1k
8INTR
19
12 SDA
SCL
4I2C_LSB
3IN3
5
6
IN5
IN6
Single-ended or
Differential Inputs
for Synchronous
Applications 100
27 MHz
74.25 MHz
74.25/1.001 MHz
148.5 MHz
148.5/1.001 MHz
SD/HD/3G-SDI
Video/Audio
Format Converter
10
9
CLK3A
CLK3B
14
CLK2A 13
CLK2B
18
CLK1A 17
CLK1B
CLK0A
CLK0B
22
21
SDI
Serializer
Video
Processor
SD/HD/3G
SDI IN SD/HD/3G
SDI OUT
100
x
IN3
x
x
SDI
Deserializer
x
Audio
Processor
Audio Out
Si5338C
16 15 1120247
VDDOA
VDDOB
VDDOC
VDDOD
VDD
VDD
23
GND
GND
PAD23 PAD
+3.3 V
0.1 uF Power Supply
Decoupling Capacitors
(1 per VDD or VDDOx pin)
1
2
25 MHz
XTAL IN1
IN2
I2C Bus
I2C Address = 111 0000 or 111 0001
+3.3V
1k1k1k
8INTR
19
12 SDA
SCL
4I2C_LSB
3IN3
5
6
IN5
IN6
10
9
14
13
18
17
22
21
x
Storage Area
Network
37.5/75/120/150 MHz
100 MHz
x
Ethernet
Fiber
Channel
PCIe
Switch
Network
Processor
SAS2
4/8 Port
Controller
disk
disk
disk
disk
SAS2
4/8 Port
Controller
66 MHz
x
x
106.25 MHz
74.25 MHz, 74.25/1.001 MHz
148.5 MHz, 148.5/1.001 MHz
24.576 MHz / 6.144 MHz
100 MHz
CLK3A
CLK3B
CLK2A
CLK2B
CLK1A
CLK1B
CLK0A
CLK0B
Si5338
18 Rev. 1.6
3. Functional Description
Figure 1. Si5338 Block Diagram
3.1. Overview
The Si5338 is a high-performance, low-jitter clock
generator capable of synthesizing four independent
user-programmable clock frequencies up to 350 MHz
and select frequencies up to 710 MHz. The device
supports free-run operation using an external crystal, or
it can lock to an external clock for generating
synchronous clocks. The output drivers support four
differential clocks or eight single-ended clocks or a
combination of both. The output drivers are configurable
to support common signal formats, such as LVPECL,
LVDS, HCSL, CMOS, HSTL, and SSTL. Separate
output supply pins allow supply voltages of 3.3, 2.5, 1.8,
and 1.5 V to support the multi-format output driver. The
core voltage supply accepts 3.3, 2.5, or 1.8 V and is
independent from the output supplies.
Using its two-stage synthesis architecture and patented
high-resolution MultiSynth technology, the Si5338 can
generate four independent frequencies from a single
input frequency. In addition to clock generation, the
inputs can bypass the synthesis stage enabling the
Si5338 to be use d as a high- performance clo ck buf fer o r
a combination of a buffer and generator.
For applications that need fine frequency adjustments,
such as clock margining, each of the synthesized
frequencies can be incremented or decremented in
user-defined steps as low as 1 ppm per step.
Output-to-output phase delays are also adjustable in
user-defined steps with an error of <20 ps to
compensate for PCB trace delays or for fine tuning of
setup and hold mar gin s.
A zero-delay mode is also available to help minimize
input-to-output delay. Spread spectrum is available on
each of the clock outputs for EMI-sensitive applications,
such as PCI Express.
Configuration and control of the Si5338 is mainly
handled through the I2C/SMBus interface. Some
features, such as output enable and frequ ency or pha se
adjustments, can optionally be pin controlled. The
device has a maskable interrupt pin that can be
monitored for loss of lock or loss of input signal
conditions.
The device also provides the option of storing a user-
definable clock configuration in its non-volatile memory
(NVM), which becomes the default clock configuration
at power-up.
3.1.1. ClockBuilder™ Desktop Software
To simplify device configuration, Silicon Labs provides
ClockBuilder Desktop software, which can operate
stand alone or in conjunction with the Si5338 EVB.
When the software is connected to an Si5338 EVB it will
control both the supply volt ages to the Si5 338 as well as
the entire clock path within the Si5338. Clockbuilder
Desktop can also measure the current delivered by the
EVB regulators to each supply voltage of the Si5338. A
Si5338 configuration can be written to a text file to be
used by any system to configure the Si5338 via I2C.
ClockBuilder Desktop can be downloaded from
www.silabs.com/ClockBuilder and runs on Windows XP,
Windows Vista, and Windows 7.
Phase
Frequency
Detector
Loop
Filter VCO
CLK0A
÷P2
VDDO1
VDDO2
VDDO3
VDDO0
M u ltiSyn th
÷M0
I2C_LSB/PDEC/FDEC
OEB/PINC/FINC
CLK0B
CLK1A
CLK1B
CLK2A
CLK2B
CLK3A
CLK3B
÷P1
IN3
IN2
IN1
÷R1
Mu ltiSynth
÷M1
Mu ltiSynth
÷M2
M u ltiSyn th
÷M3
IN6
IN4
IN5
Osc
MultiS y nth
÷N
Control NVM
(OTP)
÷R0
÷R2
÷R3
Input
Stage Synthesis
Stage 1
(PLL)
Synthesis
Stage 2 Output
Stage
CLKIN
C o ntro l & Mem o ry
SCL
SDA
INTR
VDD
ref
fb
RAM
FDBK
Si5338
Rev. 1.6 19
3.2. Input Stage
The input stage supports four inputs. Two are used as
the clock inputs to the synthesis stage, and the other
two are used as feedback inputs for zero delay or
external feedback mode. In cases where external
feedback is not required, all four inputs are available to
the synthesis stage. The referenc e selector selects one
of the inputs as the reference to the synthesis stage.
The input configuration is selectable through the IC
interface. The input MUXes are set automatically in
ClockBuilder Desktop (see “3.1.1. ClockBuilder™
Desktop Software”). For information on setting the input
MUXs manually, see the Si5338 Reference Manual:
Configuring the Si5338 without ClockBuilder Desktop.
Figure 2. Input Stage
IN1/IN2 and IN5/IN6 are differential inputs capable of
accepting clock rates from 5 to 710 MHz. The
differential inputs are capable of interfacing to multiple
signals, such as LVPECL, LVDS, HSCT, HCSL, and
CML. Differential signals must be ac-coupled as shown
in Figure 3. A termination resistor of 100 placed close
to the input pins is also required. Refer to Table 6 for
signal voltage limits.
Figure 3. Interfacing Differential and Single-
Ended Signals to the Si5338
IN3 and IN4 accept single-ended signals from 5 MHz to
200 MHz. The single-ended inputs are internally ac-
coupled; so, they can accept a wide variety of signals
without requiring a specific dc level. The input signal
only needs to meet a minimum voltage swing and must
not exceed a maximum VIH or a minimum VIL. Refer to
Table 6 for signal voltage limits. A typical single-ended
connection is shown in Figure 3. For additional
termination options, refer to “AN408: Termination
Options for Any-Frequency, Any-Output Clock
Generators and Clock Buffers—Si5338, Si5334,
Si5330”.
For free-run operation, the internal oscillator can
operate from a low-fr equen cy fu nd ame ntal mode cryst al
(XTAL) with a resonant frequency between 8 and
30 MHz. A crystal can easily be connected to pins IN1
and IN2 without external components as shown in
Figure 4. See Tables 8–11 for crystal specifications that
are guaranteed to work with the Si5338.
Figure 4. Connecting an XTAL to the Si5338
Refer to “AN360: Crystal Selection Guide for Si533x/5x
Devices” for information on the crystal selection.
3.2.1. Loss-of-Signal (LOS) Alarm Detectors
There are two LOS detectors: LOS_CLKIN and
LOS_FDBK. These detectors are tied to the outputs of
the P1 and P2 frequency dividers, which are always
enabled. See "3.6. Status Indicators" on page 24 for
details on the alarm indicators. These alarms are used
during programming to ensure that a valid input clock is
detected. The input MUXs are set automatically in
ClockBuilder Desktop (see the Si5338 Reference
Manual to set manually).
3.3. Synthesis Stages
Next-generation timing applications require a wide
range of frequencies that are often non-integer related.
Traditional clock architectures address this by using
multiple single PLL ICs, often at the expense of BOM
complexity and power. The Si5338 uses patented
MultiSynth technology to dramatically simplify timing
architectures by integrating the frequency synthesis
capability of four Phase-Locked Loops (PLLs) in a
single device, greatly reducing size and power
requirements versus traditional solutions.
÷P2
÷P1
IN3
IN2
IN1
IN6
IN4
IN5
Osc
P1DIV_IN
To Synthesis Stage
P2DIV_IN
noclk
noclk
IN 2 / IN6
IN 1 / IN5
100
50
50
0.1 uF
0.1 uF
IN 3 / IN4
50
Rs
IN2
IN1
XTAL Osc To synthesis stage
or output selectors
Si5338
20 Rev. 1.6
Synthesis of the output clocks is performed in two
stages, as shown in Figure 5. The first stage consists of
a high-frequency analog phase-locked loop (PLL) that
multiplies the input stage to a frequency within the
range of 2.2 to 2.84 GHz. Multiplication of the input
frequency is accomplished using a proprietary and
highly precise MultiSynth feedback divider (N), which
allows the PLL to generate any frequency within its
VCO range with much less jitter than typical fract ion al N
PLL.
Figure 5. Synthesis Stages
The second stage of synthesis consists of the output
MultiSynth dividers (MSx). Based on a fractional N
divider, the MultiSynth divider shown in Figure 6
switches seamlessly between the two closest integer
divider values to produce the exact output clock
frequency with 0 ppm error.
To eliminate phase error generated by this process, the
MultiSynth block calculates the r elative phase dif ference
between the clock produced by the fractional-N divider
and the desired output clock and dynamically adjusts
the phase to match the ideal clock waveform. This no vel
approach makes it possible to generate any output
clock frequency without sacrificing jitter performance.
This architecture allows the output of each MultiSynth to
produce any frequency from 5 to Fvco/8 MHz. To
support higher frequency operation, the MultiSynth
divider can be bypassed . In bypass mode, integer divide
ratios of 4 and 6 are supported. This allows for output
frequencies of Fvco/4 and Fvco/6 MHz, which translates
to 367–473.33 MHz and 550–710 MHz respectively.
Because each MultiSynth uses the same VCO output,
there are output frequency limitations when output
frequencies greater than Fvco/8 are desired.
For example, if 375 MHz is needed at the output of
MultiSynth0, the VCO frequency would need to be
2.25 GHz. Now, all the other MultiSynths can produce
any frequency from 5 MHz up to a maximum frequency
of 2250/8 = 281.25 MHz. MultiSynth1,2,3 could also
produce Fvco/4 = 562.5 MHz or Fvco/6 = 375 MHz. Only
two unique frequencies above Fvco/8 can be output:
Fvco/6 and Fvco/4.
Figure 6. Silicon Labs’ MultiSynth Technology
Phase
Frequency
Detector
Loop
Filter VCO
Mu ltiSy n th
÷MS0
Mu ltiSyn th
÷MS1
Mu ltiSyn th
÷MS2
Mu ltiSy n t h
÷MS3
Mu ltiSy n t h
÷N
Synthesis
Stage 1
(APLL)
Synthesis
Stage 2
ref
fb
From Input Stage
To Output Stage
2.2-2.84 GHz
Fractional-N
Divider Phase
Adjust
Phase Error
Calculator
Divider Select
(DIV1, DIV2)
fVCO fOUT
MultiSynth
Si5338
Rev. 1.6 21
3.4. Output Stage
The output stage consists of output selectors, output
dividers, and programmable output drivers as shown in
Figure 7.
Figure 7. Output Stage
The output selectors select the clock source for the
output drivers. By default, each output driver is
connected to its own MultiSynth block (e.g. MS0 to
CLK0, MS1 to CLK1, etc), but other combinations are
possible by reconfiguring the device. The PLL can be
bypassed by connecting the input stage signals (osc,
ref, refdiv, fb, or fbdiv) directly to the output divider.
Bypassing an input directly to an output will not allow
phase alignment of that output to other outputs. Each of
the output drivers can also connect to the first
MultiSynth block (MS0) ena bling a fan -out function. This
allows the Si5338 to act as a clock generator, a fanout
buffer, or a combination of both in the same package.
The output dividers (R0, R1, R2, R3) allow another
stage of clock division.These dividers are configurable
as divide by 1 (default), 2, 4, 8, 16, or 32. When an Rn
does not equal 1, the phase alignment function for that
output will not work.
The output drivers are configurable to support common
signal formats, such as LVPECL, LVDS, HCSL, CMOS,
HSTL, and SSTL. Sep arate output supply pin s (VDDOn)
are provided for each output buffer.
The volta ge on these su pply pi ns can be 3.3, 2.5, 1.8, or
1.5 V as needed for the possible output formats.
Additionally, the outputs can be configured to stop high,
low, or tri-state when the PLL has lo st lock. If the Si5338
is used in a zero delay mode, the output that is fed back
must be set for always on, which will override any
output disable signal.
Each of the outputs can also be enabled or disabled
through the I2C port. A single pin to enable/disable all
outputs is available in the Si5338K/L/M.
3.5. Configuring the Si5338
The Si5338 is a highly-flexible clock generator that is
entirely configurable through its I2C interface. The
device’s default configuration is stored in non-volatile
memory (NVM) as shown in Figure 8. The NVM is a
one-time programmable memory (OTP), which can
store a custom user co nf igu ra tio n at p ow er -u p. T his is a
useful feature for applications that need a clock present
at power-up (e.g., for prov iding a clock to a processor).
Figure 8. Si5338 Memory Configuration
During a power cycle or a power-on reset (POR), the
contents of the NVM are copied into random access
memory (RAM), which set s the de vice configur ation that
will be used during operation. Any changes to the
device configuration after power-up are made by
reading and writing to registers in the RAM space
through the I2C interface. ClockBuilder Desktop (see
"3.1.1. ClockBuilder™ Desktop Software" on page 18)
can be used to easily configure register map files that
can be written into RAM (see “3.5.2. Creating a New
Configuration for RAM” for details). Alternatively, the
register map file can be created manually with the help
of the equations in the Si5338 Reference Manual.
Two versions of the Si5338 are available. First,
standard, non-customized Si5338 devices are available
in which the RAM can be configured in-circuit via I2C
(example part number Si5338C-A-GM). Alternatively,
standard Si5338 devices can be field-programmed
using the Si5338/56-PROG-EVB field programmer.
Second, custom factory-programmed Si5338 devices
are available that include a user-specified startup
frequency configuration (example part number
Si5338C-Axxxxx-GM). See "12. Ordering Information"
on page 42 for details.
CLK0A
VDDO1
VDDO2
VDDO3
VDDO0
CLK0B
CLK1A
CLK1B
CLK2A
CLK2B
CLK3A
CLK3B
÷R1
÷R0
÷R2
÷R3
Output
Stage
From Synthesis Stage
or Input Stage
Power-Up/POR
I2C
RAM
NVM
(OTP)
Default
Config
Si5338
22 Rev. 1.6
3.5.1. Ordering a Custom NVM Configuration
The Si5338 is orderable with a factory-programmed custom NVM configuration. This is the simplest way of using
the Si5338 since it generates the desired output frequencies at power-up or after a power-on reset (POR). This
default configuration can be reconfigured in RAM through the I2C interface after power-up (see “3.5.2. Creatin g a
New Configuration for RAM”).
Custom 7-bit I2C addresses may also be requested. Note that for the A/B/C devices, the I2C LS bit address is the
logical “or” of the I2C address LS bit in Register 27 and the state of the I2C_LSB pin . If I2C_LSB pin functionality is
required, custom I2C addresses may only be even numbers. For all other variants of the device, custom I2C
addresses may be even or odd numbers. See the Si5338 Reference Manual: Configuring the Si5338 without
ClockBuilder Desktop for more details.
The first step in ordering a custom device is generating an NVM file which defines the input and output clock
frequencies and signal formats. This is easily done using the ClockBuilder Desktop software (see "3.1.1.
ClockBuilder™ Desktop Software" on page 18). This GUI based software generates an NVM file, which is used by
the factory to manufacture custom parts. Each custom part is marked with a unique part number identifying the
specific configuration (e.g., Si5338C-A00100-GM). Consult your local sales representative for more details on
ordering a custom Si5338.
3.5.2. Creating a New Configuration for RAM
Any Si5338 device can be configured by writing to registers in RAM through the I2C interface. A non-factory
programmed device must be configured in this manner.
The first step is to determine all the re gister values for the required co nfiguration. This can be accomp lished by one
of two methods.
1. Create a device configuration (register map) using ClockBuilder Desktop (v3.0 or later; see "3.1.1.
ClockBuilder™ Desktop Software" on page 18).
a. Configure the freq uency plan.
b. Configure the output driver format and supply voltage.
c. Configure frequency and/or phase inc/dec (if desired).
d. Configure spread spectr um (if desired).
e. Configure for zero-delay mode (if desired, see "3.10.6. Zero-Delay Mode" on page 28).
f. If needed go to the Advanced tab and make additional configurations.
g. Save the configuration using the Options > Save Register Map File or Options > Save C code Header.
2. Create a device configuration, register by register, using the Si5338 Reference Manual.
3.5.3. Writing a Custom Configuration to RAM
Writing a new configuration (register map) to the RAM consists of pausing the LOL state-machine, writing new
values to the IC accounting for the write-allowed mask (see the Si5338 Refer ence Manual, “ 10. Si5338 Re gisters”),
validating the input clock or crystal, locking the PLL to the input with the new configuration, restarting the LOL
state-machine, and calibrating the VCO for robust operation across temperature. The flow chart in Figure 9
enumerates the details:
Note: The write-allowed mask specifies which bits must be read and modified before writing the entire register byte (a.k.a.
read-modify-write). “AN42 8: Jump Start: In-System, Flash-Based Programming for Silicon Labs’ Timing Products” illus-
trates the procedure defined in Section 3.5.2 with ANSI C code.
Si5338
Rev. 1.6 23
Figure 9. I2C Programming Procedure
Register
Map
Use ClockBuilder
Desktop v3.0 or later
Pause LOL
Set DIS_LOL = 1; reg241[7]
Write new configuration to device
accounting for the write-allowed mask
(See Si5338 Reference Manual)
Validate input clock status
Disable Outputs
Set OEB_ALL = 1; reg230[4]
NO
YES
Input clocks are
validated with the
LOS alarms. See
Register 218 to
determine which LOS
should be monitored
Configure PLL for locking
Set FCAL_OVRD _EN = 0; reg49[7]
Initiate Locking of PLL
Set SOFT_RESET = 1; reg246[1]
Wait 25 ms
Restart LOL
Set DIS_LOL = 0; reg241[7]
Set reg 241 = 0x65
Is input clock valid?
Confirm PLL lock status
NO
YES
PLL is locked when
PLL_LOL, SYS_CAL, and
all other alarms are
cleared Copy registers as follows:
237[1:0] to 47[1:0]
236[7:0] to 46[7:0]
235[7:0] to 45[7:0]
Set 47[7:2] = 000101b
Copy FCAL values to
active registers
Set PLL to use FCAL values
Set FCAL_OVRD_EN = 1; reg49[7]
Is PLL locked?
If using down-spread:
Set MS_RESET=1: reg 226[2]=1
Wait 1 ms
Set MS_RESET=0: reg 226[2]=0
Enable Outputs
Set OEB_ALL = 0; reg230[4]
Si5338
24 Rev. 1.6
3.5.4. Writing a Custom Configuration to NVM
An alternative to or dering an Si5338 with a custom NVM
configuration is to use the field programming kit
(Si5338/56-PROG-EVB) to write directly to the NVM of
a “blank” Si5338. Since NVM is an OTP memory, it can
only be written once. The default configuration can be
reconfigured by writing to RAM through the I 2C interface
(see “3.5.2. Creating a New Configuration for RAM”).
3.6. Status Indicators
A logic-high interrupt pin (INTR) is available to indicate
a loss of signal (LOS) condition, a PLL loss of lock
(PLL_LOL) condition, or that the PLL is in process of
acquiring lock (SYS_CAL). PLL_LOL is held high when
the input frequency drifts beyond the PLL tracking
range. It is held low during all other times and during a
POR or soft_reset. SYS_CAL is held high during a POR
or SOFT reset so that no chattering occurs during the
locking process. As shown in Figure 10, a status
register at address 218 is available to help identify the
exact event that caused the interrupt pin to become
active. Register 247 is the sticky version of Register
218, and Register 6 is the interrupt mask for Register
218.
Figure 10. Status Register
Figure 11 shows a typical connection with the required
pull-up resistor to VDD.
3.6.1. Using the INTR Pin in Systems with I2C
The INTR output pin is not la tched and thus it should not
be a polled input to an MCU but an edge-triggered
interrupt. An MCU can process an interrupt event by
reading the sticky register 247 to see what event
caused the interrupt. The same register can be cleared
by writing zeros to the bits that were set. Individual
interrupt bits can be masked by register 6[4:0].
3.6.2. Using the INTR Pin in Systems without I2C
The INTR pin also provides a useful function in systems
that require a pin-controlled fault indicator. Pre-setting
the interrupt mask register allows the INTR pin to
become an indicator for a specific event, such as LOS
and/or LOL. Therefore, the INTR pin can be used to
indicate a single fault event or even multiple event s.
Figure 11. INTR Pin with Required Pull-Up
3.7. Output Enable
There are two methods of enabling and disabling the
output drivers: Pin control, and I2C control.
3.7.1. Enabling Outputs Using Pin Control
The Si5338K/L /M de vices pro vide an Outpu t Enable p in
(OEB) as shown in Figure 12. Pulling this pin high will
turn all outputs off. The state of the individual drivers
when turned off is controllable. If an individual output is
set to always on, then the OEB pin will not have an
effect on that driver. Drive state options and always on
are explained in “3.7.2. Enabling Outputs through the
I2C Interface”.
Figure 12. Output Enable Pin (Si5338K/L/M)
3.7.2. Enabling Outputs through the I2C Interface
Output enable can be controlled through the I2C
interface. As shown in Figure 13, register 230[3:0]
allows control of each individual output driver. Register
230[4] controls all drivers at once. When register 230[4]
is set to disable all outputs, the individual output
enables will have no effect. Registers 110[7:6], 114[7:6],
118[7:6], and 112[7:6] control the output disabled state
as tri-state, low, high, or always on. If always on is set,
that output will always be on regardless of any other
register or chip state. In addition, the always on mode
must be selected for an output that is fed back in a Zero
Delay application.
218
System Calibration
(L ock Acq uisitio n)
Sys
Cal
0
PLL_LOL
1234567
Loss Of Signal
Clock Input
Loss Of Signal
Feedback Input
Loss Of Lock
LOS_FDBK LOS_CLKIN
INTR
VDD
1k Control NVM
(OTP)
Control & Memory
RAM
OEB
Control NVM
(OTP)
Control & Memory
RAM
0 = Enabled
1 = Disabled
Si5338
Rev. 1.6 25
Figure 13. Output Enable Control Registers
3.8. Power Consumption
The Si5338 Power consumption is a function of
Supply voltage
Frequency of output Clocks
Number of output Clocks
Format of output Clocks
Because of internal voltage regulation, the current from
the core VDD is independent of the VDD voltage and
hence the plot shown in Figure 14 can be used to
estimate the VDD core (pins 7 and 24) current.
The current from the output supply voltages can be
estimated from the values provided in Table 3, “DC
Characteristics,” on page 5. To get the most accurate
value for VDD currents, the Si5338-EVB with
Clockbuilder software should be used. To do this, go to
the “Power” tab of the Clockbuilder and press
“Measure”. In this manner, a specific configuration can
be implemented on the EVB and the actual current for
each supply voltage measured. When doing this it is
critical that the output drivers have the proper load
impedance for the selected format.
When testing for output driver current with HSTL and
SSTL, it is required to have load circuitry as shown in
“AN408: Termination Options for Any-Frequency, Any-
Output Clock Generators and Clock Buffers”. The
Si5338 EVB has layout pads that can be used for this
purpose. When testing for output driver current with
LVPECL the same layout pads can be used to
implement the LVPECL bias resistor of 130 (2.5 V
VDDx) or 200 (3.3 V VDDx). See the schematic in the
Si5338-EVB data sheet and AN408 for additional
information.
230 OEB
0
0
OEB
1
OEB
2
OEB
3
OEB
All
1234567
0 = enable
1 = disable
110
01234567
CLK0 OEB
State
114
01234567
CLK1 OEB
State
118
01234567
CLK2 OEB
State
122
01234567
CLK3 OEB
State
00 = disabled tri-state
01 = disabled low
10 = disabled high
11 = always enabled
B its re s e rv e d
Bits used by other functions
Si5338
26 Rev. 1.6
Figure 14. Core VDD Supply Average Current vs Output Frequency
30
35
40
45
50
55
60
65
70
75
80
0 50 100 150 200 250 300 350 400
Typical VDD Core Current (ma)
Output Frequency (MHz)
4 Active Outputs, Fractional Output MS
4 Active Outputs, Integer Output MS
3 Active Outputs, Fractional Output MS
3 Active Outputs, Integer Output MS
2 Active Outputs, Fractional Output MS
2 Active Outputs, Integer Output MS
1 Active Output, Fractional Output MS
1 Active Output, Integer Output MS
Si5338
Rev. 1.6 27
3.9. Reset Options
There are two types of resets on the Si5338, POR and
soft reset. A POR reset automatically occurs whenever
the supply voltage on the VDD is applied.
The soft reset is forced by writing 0x02 to register 246.
This bit is not self-clearing, and thus it m ay read back as
a 1 or a 0. A soft reset will not download any pre-
programmed NVM and will not change any register
values in RAM.
The soft reset performs the following sequence:
1. All outputs turn off except if programmed to be
always on.
2. Internal calibrations are done and MultiSynths are
initialized.
a. Outputs that are synchronous are phase
aligned (if Rn = 1).
3. 25 ms is allowed for the PL L to lock (no delay occurs
when FCAL_OVRD_EN = 1).
4. Turn on all outputs that were turned off in step 1.
3.10. Features of the Si5338
The Si5338 offers several features and functions that
are useful in many timing applications. The following
paragraphs describe in detail the main features and
typical applications. All of these features can be easily
configured using the ClockBuilder Desktop. See "3.1.1.
ClockBuilder™ Desktop Software" on page 18.
3.10.1. Frequency Increment/Decrement
Each of the output clock frequencies can be
independently stepped up or down in predefined steps
as low as 1 ppm per step and with a resolution of
1 ppm. Setting of the step size and control of the
frequency increment or decrement is accomplished
through the I2C interface. Alternatively, the Si5338 can
be ordered with optional frequency increment (FINC)
and frequency decrement (FDEC) pins for pin-
controlled applications. Note that FINC and FDEC pins
only affect CLK0. Frequency increment and decrement
of all other channels must be performed by I2C writes to
the appropriate registers. See Table 17 on page 37 for
ordering information of pin-controlled devices. When
phase is decremented, the MultiSyn th output clock edge
will happen sooner which will create a single half cycle
that is shorter than expected for the MultiSynth output
clock frequency. Care must be taken to insure that a
single phase decrement does not produce a half cycle
that is less than 4/fvco or an unwanted glitch in the
MultiSynth output may occur.
The frequency increment and decrement feature is
useful in applications requiring a variable clock
frequency (e.g., CPU speed control, FIFO overflow
management, etc.) or in applications where frequency
margining (e.g., fout ±5%) is necessary for design
verification and manufacturing test. Frequency
increment or decrement can be applied as fast as
1.5 MHz when it is done by pin control. When under I2C
control, the frequency increment and decrement update
rate is limited by the I2C bus speed. The magnitude of
the frequency step has 0 ppm error. Frequency steps
are seamless and glitchless.
If a frequency increment/decrement command causes
the MultiSynth output frequency to exceed the
maximum/minimum limits, then a glitch on the output is
likely to occur. The max frequency of a MultiSynth
output that is using frequency increment/decrement is
Fvco/8, and the minimum frequency is 5 MHz.
3.10.2. Output Phase Increment/Decrement
The Si5338 has a digitally-controlled glitchless phase
increment and decrement feature that allows adjusting
the phase of each output clock in relation to the other
output clocks. The phase of each output clock can be
adjusted with an accuracy of 20 ps over a range of
±45 ns. Setting of the step size and control of the phase
increment or decrement is accomplished through the
I2C interface. Alternatively, the Si5338 can be ordered
with optional phase increment (PINC) and phase
decrement (PDEC) pins for pin-controlled applications.
In pin controlled applications the phase increment and
decrement update rate is as fast as 1.5 MHz. In I2C
applications, the maximum update rate is limited by the
speed of the I2C. See Table 17 for ordering information
of pin-controlled devices. When phase is decremented,
the MultiSynth output clock edge will happen sooner,
which will create a single half cycle that is shorter than
expected for the MultiSynth output clock frequency.
Care must be taken to insure that a single phase
decrement does not produce a half cycle that is less
than 4/fvco or an unwanted glitch in the MultiSynth
output may occur.
The phase increment and decrement feature provides a
useful method for fine tuning setup and hold timing
margins or adjustin g for mi smatched PCB tr ace le ngths.
3.10.3. Programmable Initial Phase Offset
Each output clock can be set for its initial phase offset
up to ±45 ns. In order for the initial phase offset to be
applied correctly at power up, the VDDOx output supply
voltage must cross 1.2 V before the VDD (pins 7,24)
core power supply voltage crosses 1.45 V. This applies
to the each driver output individually. A soft_reset will
also guarantee that the programm ed Initial Pha se Of fset
is applied correctly. The initial phase offset only works
on outputs that have their R divider set to 1.
Si5338
28 Rev. 1.6
3.10.4. Output Synchronization
Upon power up or a soft_reset the Si5338 synchronizes
the output clocks. With normal output po lari ty (no o utput
clock inversion), the Si5338 synchronizes the output
clocks to the falling, not rising edge. Synchronization at
the rising edge can be done by inverting all the clocks
that are to be synchronized.
3.10.5. Output R Divider
When the requested output frequency of a channel is
below 5 MHz, the Rn (n = 0,1,2,3) divider needs to be
set and enabled. This is automatically done in register
maps generated by the ClockBuilder Desktop. When
the Rn divider is active the step size range of the
frequency increment and decrement function will
decrease by the Rn divide ratio. The Rn divider can be
set to {1, 2, 4, 8, 16, 32}.
Non-unity settings of R0 will affect the Finc/Fdec step
size at the MultiSynth0 output. For example, if the
MultiSynth0 output step size is 2.56 MHz and R0 = 8,
the step size at the output of R0 will be 2.56 MHz
divided by 8 = .32 MHz. When the Rn divider is set to
non-unity, the initial phase of fset of the CLKn ou tput with
respect to other CLKn outpu ts is not guaranteed.
3.10.6. Zero- Delay Mode
The Si5338 supports an optional zero delay mode of
operation for applications that require minimal input-to-
output delay. In this mode, one of the device output
clocks is fed back to the feedback input pin (IN4 or IN5/
IN6) to implement an external feedback path which
nullifies the delay between the reference input and the
output clocks. Figure 15 shows the Si5338 in a typical
zero-delay configuration. It is generally recommended
that Clk3 be LVDS and that the feedback input be pins 5
and 6. For the differential input configuration to pins 5
and 6, see Figure 3 on page 19. The zero-delay mode
combined with the phase increment/decrement feature
allows unprecedented flexibility in generating clocks
with precise edge alignment.
Figure 15. Si5338 in Zero Delay Clock
Generator Mode
3.10.7. Spread Spectrum
To help reduce electromagnetic interference (EMI), the
Si5338 supports spread spectrum modulation. The
output clock frequencies can be modulated to spread
energy across a broader range of frequencies, lowering
system EMI. The Si5338 implements spread spectrum
using its patented MultiSynth technology to achieve
previously unattainable precision in both modulation
rate and spreading magnitude as shown in Figure 16.
Through I2C control, the Spread spectrum can be
applied to any output clock, any clock frequency, and
any spread amount from ±0.1% to ±2.5% center spread
and –0.1% to –5% down spread.
The spreading rate is limited to 30 to 63 kHz.
The Spread Spectrum is generated digit ally in the outp ut
MultiSynths which means that the Spread Spectrum
parameters are virtually independent of process,
voltage and temperature variations. Since the Spread
Spectrum is created in the output MultiSynths, through
I2C each output channel can have independent Spread
Spectrum parameters. Without the use of I2C (NVM
download only) the only supported Spread Spectrum
parameters are for PCI Express compliance composing
100 MHz clock, 31.5 kHz spreading frequency with the
choice of the spre ad in g.
Rev A devices provide native support for b oth down and
center spread. Center spread is supported in rev B
devices by up-shifting the nominal frequency and using
down-spread register parameters. Consult the Si5338
Reference Manual for details.
Note: If you currently use center spread on a revision A a nd
would like to migrate to a revision B device, you must
generate a new registe r map using either ClockBuilder
Desktop or the equations in the Si5338 Reference
Manual. Center spread configurations for Revisions A
and B are not compatible.
Clk0
MS2
MS3
R2
R3
P2
Si5338
PLL
R0
R1
MS1
MS0
P1
Clk
Input Clk1
Clk2
Clk3
Si5338
Rev. 1.6 29
Figure 16. Configurable Spread Spectrum
4. Applications of the Si5338
Because of its flexible architecture, the Si5338 can be
configured to serve sever al functions in the timing path.
The following sections describe some common
applications.
4.1. Free-Running Clock Generator
Using the internal oscillator (Osc) and an inexpensive
external crystal (XTAL), the Si5338 can be configured
as a free-running clock generator for replacing high-end
and long-lead-time crystal oscillators found on many
printed circuit boards (PCBs). Replacing several crystal
oscillators with a single IC solution helps consolidate the
bill of materials (BOM), reduces the number of
suppliers, and reduces the number of long-lead-time
components on the PCB. In addition, since crystal
oscillators tend to be the least reliable aspect of many
systems, the overall FIT rate improves with the
elimination of each oscillator.
Up to four independent clock frequencies can be
generated at any rate within its supported frequency
range and with any of suppo rted outp ut types. Featu res,
such as frequency increment and decrement and phase
adjustments on a per-output basis, provide
unprecedented flexibility for PCB designs. Figure 17
shows the Si5338 configured as a free-running clock
generator.
Figure 17. Si5338 as a Free-Running Clock
Generator
-80
-70
-60
-50
-40
-30
-20
-10
0
10
20
-10% -8% -6% -4% -2% 0% 2% 4% 6% 8% 10%
Relat i ve Frequenc y
Power Spectrum (dBm)
+/- 0%
+/- 1%
+/- 2.5%
+/- 5%
MS0 R0
Osc
Si5338
F0
F1
F2
F3
XTAL
MS1 R1
MS2
MS3
R2
R3
PLL
ref
Si5338
30 Rev. 1.6
4.2. Synchronous Frequency Translation
In other cases, it is useful to generate an output
frequency that is synchronous (or phase-locked) to
another clock frequency. The Si5338 is the ideal choice
for generating up to four clocks with different
frequencies with a fixed phase relationship to an input
reference. Because of its highly precise frequency
synthesis, the Si5338 can generate all four output
frequencies with 0 ppm error to the input reference. The
Si5338 is an ideal choice for applications that have
traditionally required multiple stages of frequency
synthesis to achieve complex frequency translations.
Examples are in broadcast video (e.g., 148.5 MHz to
148.351648351648 MHz), WAN/LAN applications (e.g.
155.52 MHz to 156.25 MHz), and Forward Error
Correction (FEC) applications (e.g., 156.25 MHz to
161.1328125 MHz). Using the input re ference selectors,
the Si5338 can select from one of four inputs (IN1/IN2,
IN3, IN4, and IN5/IN6). Figure 18 shows the Si5338
configured as a synchronous clock generator.
Frequencies and multiplication ratios may be entered
into ClockBuilder Desktop using fractional notation to
ensure that the exact scaling ratios can be achieved.
Figure 18. Si5338 as a Synchronous Clock
Generator or Frequency Translator
4.3. Configurable Buffer and Level Transla-
tor
Using the output selectors, the synthesis stage can be
entirely bypassed allowing the Si5338 to act as a
configurable clock buffer/divider with level translation
and selectable inputs. Because of its highly selectable
configuration, virtually any combination is possible. The
configurable output drivers allow four differential
outputs, eight single-ended outputs, or a combination of
both. Figure 19 shows the Si5338 configured as a
flexible clock buffer.
Figure 19. Si5338 as a Configurable Clock
Buffer/Divider with Level Translation
4.3.1. Combination Free-Running and Synchronous
Clock Generator
Another application of the Si5338 is in generating both
free-running and synchronous clocks in one device.
This is accomplished by configuring the input and
output selectors for the desired split configuration. An
example of such an application is shown in Figure 20.
Figure 20. Si5338 In a Free-Running and
Synchronous Clock Generator Application
MS0 R0
Si5338 F0
F1
F2
F3
MS1 R1
MS2
MS3
R2
R3
P1
P2
PLL
ref
Fin
R0
Si5338
R1
R2
R3
Fin
Fin * 1
R0
Fin * 1
R1
Fin *1
R2
Fin * 1
R3
R0 F0
F1
F2
F3
R1
MS2
MS3
R2
R3
P2
Si5338
Osc
XTAL
PLL
ref
Fin
Si5338
Rev. 1.6 31
5. I2C Interface
Configuration and operation of the Si5338 is controlled
by reading and writing to the RAM space using the I2C
interface. The device operates in slave mode with 7-bit
addressing and can operate in Standard-Mode
(100 kbps) or Fast-Mode (400 kbps) and supports burst
data transfer with auto address increments.
The I2C bus consists of a bidirectional serial data line
(SDA) and a serial clock input (SCL) as shown in
Figure 21. Both the SDA and SCL pins must be
connected to the VDD supply via an external pull-up as
recommended by the I2C specification.
Figure 21. I2C and Control Signals
The 7-bit device (slave) address of the Si5338 consists
of a 6-bit fixed address plus a user-s electable LSB bit as
shown in Figur e 22. The LSB bit is sele ctable using the
optional I2C_LSB pin which is available as an ordering
option for applications that require more than one
Si5338 on a single I2C bus. Devices without the
I2C_LSB pin option have a fixed 7-bit address of 70h
(111 0000) as shown in Figure 22. Other custom I2C
addresses are also possible. Se e Table 17 for details on
device ordering information with the optional I2C_LSB
pin.
Figure 22. Si5338 I2C Slave Address
Data is transferred MSB firs t in 8-bit words as specified
by the I2C specification. A write command consists of a
7-bit device (slave) address + a write bit, an 8-bit
register address, and 8 bits of data as shown in
Figure 23. A write burst operation is also shown where
every additional data word is written using an auto-
incremente d ad dr e ss.
Figure 23. I2C Write Operation
A read operation is performed in two stages. A data
write is used to set the register address, then a data
read is performed to retrieve the data from the set
address. A read burst operation is also supported. This
is shown in Figure 24.
Figure 24. I2C Read Operation
AC and dc electrical specifications for the SCL and SDA
pins are shown in Table 15. The timing specifications
and timing diagram for the I2C bus are compatible with
the I2C-Bus Standard. SDA timeout is supported for
compatibility with SMBus interfaces.
The I2C bus can be operated at a bus voltage of 1.71 to
3.63 V and is 3.3 V tolerant. If a bus volt age of less than
2.5 V is used, register 27[7] = 1 must be written to
maintain compatibility with the I2C bus standard.
Control
I2C_LSB I2C_LSB/PDEC/FDEC
OEB/PINC/FINC
0/1
SCL
SDA
I2C Bus
VDD
Slave Address
(with I2C_ LSB Op tion) 1 1 1 0 0 0 0/1
I2C_LSB pin
0123456
Slave Ad dress
(without I2C_LSB O ption) 1 1 1 0 0 0 0
0123456
1 – R ead
0 – W rite
A – A cknowledge (SD A LOW)
N – Not Acknowledge (SDA HIGH)
S – START condition
P – STOP condition
From slave to master
F rom mas te r to s la ve
W rite Operation – Single Byte
S 0 A Reg Addr [7:0]S lv A ddr [6 :0 ] AD a ta [7:0 ] PA
W rite Ope ration - Burst (Auto A ddress Increm ent)
Reg Addr +1
S 0 A Reg Addr [7:0]S lv A d dr [6 :0 ] AD a ta [7 :0] AData [7 :0 ] PA
1 – R ead
0 – W rite
A – A cknowledge (SD A LOW)
N – Not Acknowledge (SDA HIGH)
S – START condition
P – STOP condition
From slave to master
F rom mas te r to s la ve
Read O peration – Single Byte
S 0 A Reg Addr [7:0]S lv A ddr [6 :0 ] A P
Read O peration - Burst (Auto Address Increm ent)
Reg Addr +1
S 1 ASlv Addr [6:0] Da ta [7:0 ] PN
S 0 A Reg Addr [7:0]Slv Addr [6:0] A P
S 1 ASlv Addr [6:0] Da ta [7:0 ] A PNData [7:0]
Si5338
32 Rev. 1.6
6. Si5338 Registers
For many applications, the Si5338's register values are easily configured using ClockBuilder Desktop (see "3.1.1.
ClockBuilder™ Desktop Software" on p age 18 ). However, for customers in terested in using the Si5338 in o perating
modes beyond the capabilities available with ClockBuilder™, refer to the Si5338 Reference Manual: Configuring
the Si5338 without ClockBuilder Desktop for a detailed description of the Si5338 registers and their usage. Also
refer to “AN428: Jump Start: In-System, Flash-Based Programming for Silicon Labs’ Timing Product s” for a working
application example using Silicon Labs' F301 MCU to program the Si5338 register set.
Si5338
Rev. 1.6 33
7. Pin Descriptions
Note: Center pad must be tied to GND for normal operation.
Table 16. Si5338 Pin Descriptions
Pin # Pin Name I/O Signal Type Description
1,2 IN1/IN2 I Multi
CLKIN/CLKINB.
These pins are used as the main differential clock input or as the
XTAL input. See "3.2. Input Stage" on page 19, Figure 3 and
Figure 4, for connection details. Clock inputs to these pins must be
ac-coupled. Keep the traces from pins 1,2 to the crystal as sh ort as
possible and keep other signals and radiating sources away from
the crystal.
When not in use, leave IN1 unconnected and IN2 connected to
GND.
IN1
CLK2B
CLK2A
VDDO2
VDDO1
CLK1B
CLK1A
VDD VDD
SCL
CLK3A
CLK3B
INTR
SDA
VDDO0
CLK0B
CLK0A
RSVD_GND
VDDO3
GND
GND
Pad
5
4
3
2
1
613
10
987
IN2
IN3
IN4
IN5
IN6
Top View
11 12
15
14
16
17
18
192021
222324
Si5338
34 Rev. 1.6
3IN3 IMulti
This pin can have one of the following functions depending on the
part number:
CLKIN (for Si5338A/B/C and Si5338N/P/Q devices only)
Provides a high-impedance clock input for single ended clock
signals. This input should be dc-coupled as shown in “3.2. Input
Stage”, Figure 3.
If this pin is not used, it should be connected to ground.
PINC (for Si5338D/E/F devices only)
Used as the phase increment pin. See "3.10.2. Output Phase
Increment/Decrement" on page 27 for more details. Minimum
pulse width of 100 ns is required for proper ope ration. If this pin is
not used, it should be connected to grou nd.
FINC (for Si5338G/H/J devices only)
Used as the frequency increment pin. See "3.10.1. Frequency
Increment/Decrement" on page 27 for more details. Minimum
pulse width of 100 ns is required for proper ope ration. If this pin is
not used, it should be connected to grou nd.
OEB (for Si5338K/L/M de vice s on ly)
Used as an output enable pin. 0 = All outputs enabled; 1 = All
outputs disabled. By default, outputs are tri-stated when disabled.
4IN4 IMulti
This pin can have one of the following functions depending on the
part number
I2C_LSB (for Si5338A/B/C and Si5338K/L/M devices only)
This is the LSB of the Si53 3 8 I2C address. 0 = I2C address
70h (111 0000), 1 = I2C address 71h (111 0001).
FDBK (for Si5338N/P/Q devices only)
Provides a high-impedance feedback input for single-ended clock
signals. This input should be dc-coupled as shown in “3.2. Input
Stage”, Figure 3. If this pin is not used, it should be connected to
ground.
PDEC (for Si5338D/E/F) devices only)
Used as the phase decrement pin. See “3.10.2. Output Phase
Increment/Decrement” for more details. Minimum pulse width of
100 ns is required for proper operation. If this pin is not used, it
should be connected to ground.
FDEC (for Si5338G/H/J devices only)
Used as the frequency decrement pin. See “3.10.1. Frequency
Increment/Decrement” for more details. Minimum pulse width of
100 ns is required for proper operation. If this pin is not used, it
should be connected to ground.
Table 16. Si5338 Pin Descriptions (Continued)
Pin # Pin Name I/O Signal Type Description
Si5338
Rev. 1.6 35
5,6 IN5/IN6 I Multi
FDBK/FDBKB.
These pins can be used as a differential feedback input in zero
delay mode or as a secondary clock input. See section 3.2,
Figure 3, for termination details. See "3.10.6. Zero-Delay Mode" on
page 28 for zero delay mode set-up. Inputs to these pins must be
ac-coupled.
When not in use, leave IN5 unconnected and IN6 connected to
GND.
7 VDD VDD Supply
Core Supply Voltage.
This is the core supply voltage, which can operate from a 1.8, 2.5,
or 3.3 V supply. A 0.1 µF bypass capacitor should be located very
close to this pin.
8 INTR O Open Drain
Interrupt.
A typical pullup resistor of 1–4 k is used on this pin. This pin can
be pulled up to a supply vo ltage as high as 3.6 V regardless of the
other supply voltages on pins 7, 11, 15, 16, 20, and 24. The inter-
rupt condition allows the pull up resi stor to pull the output up to the
supply voltage.
9 CLK3B O Multi
Output Clock B for Channel 3.
May be a single-ended output or half of a differential output with
CLK3A being the othe r differential ha lf. If un us ed , lea ve this pin
floating.
10 CLK3A O Multi
Output Clock A for Channel 3.
May be a single-ended output or half of a differential output with
CLK3B being the othe r differential ha lf. If un us ed , lea ve this pin
floating.
11 VDDO3 VDD Supply
Output Clock Supply Voltage.
Supply voltage (3.3, 2.5, 1.8, or 1.5 V) for CLK 3A, B. A 0.1 µF
capac itor must be located very close to this pin. If CLK3 is not
used, this pin must be tied to VDD (pin 7, 24).
12 SCL I LVCMOS
I2C Serial Clock Input.
This is the serial clock input for th e I2C bus. A pullup resistor at this
pin is required. Typical values would be 1–4 k. See the I2C bus
spec for more information. This pin is 3.3 V tolerant regardless of
the other supply voltages on pi ns 7, 11, 15, 16, 20, 24. See Regis-
ter 27.
13 CLK2B O Multi
Output Clock B for Channel 2.
May be a single-ended output or half of a differential output with
CLK2A being the othe r differential ha lf. If un us ed , lea ve this pin
floating.
14 CLK2A O Multi
Output Clock A for Channel 2.
May be a single-ended output or half of a differential output with
CLK2B being the othe r differential ha lf. If un us ed , lea ve this pin
floating.
Table 16. Si5338 Pin Descriptions (Continued)
Pin # Pin Name I/O Signal Type Description
Si5338
36 Rev. 1.6
15 VDDO2 VDD Supply
Output Clock Supply Voltage.
Supply voltage (3.3, 2.5, 1.8, or 1.5 V) for CLK 2A, B.
A 0.1 µF capacitor must be located very close to this pin. If CLK2 is
not used, this pin must be tied to VDD (pin 7, 24).
16 VDDO1 VDD Supply
Output Clock Supply Voltage.
Supply voltage (3.3, 2.5, 1.8, or 1.5 V) for CLK 1A, B.
A 0.1 µF capacitor must be located very close to this pin. If CLK1 is
not used, this pin must be tied to VDD (pin 7, 24).
17 CLK1B O Multi
Output Clock B for Channel 1.
May be a single-ended output or half of a differential output with
CLK1A being the othe r differential ha lf. If un us ed , lea ve this pin
floating.
18 CLK1A O Multi
Output Clock A for Channel 1.
May be a single-ended output or half of a differential output with
CLK1B being the othe r differential ha lf. If un us ed , lea ve this pin
floating.
19 SDA I/O LVCMOS
I2C Serial Data.
This is the serial dat a for the I2C bus. A pullup resistor at this pin is
required. Typical values would be 1–4 k. See the I2C bus spec
for more information. This pin is 3.3 V tolerant regardless of the
other supply voltages on pins 7, 11, 15, 16, 20, 24. See Register
27.
20 VDDO0 VDD Supply
Output Clock Supply Voltage.
Supply voltage (3.3, 2.5, 1.8, or 1.5 V) for CLK 0A, B.
A 0.1 µF capacitor must be located very close to this pin. If CLK0 is
not used, this pin must be tied to VDD (pin 7, 24).
21 CLK0B O Multi Output Clock B for Channel 0.
May be a single-ended output or half of a differential output with
CLK0A being the othe r differential ha lf. If un us ed , lea ve this pin
floating.
22 CLK0A O Multi Output Clock A for Channel 0.
May be a single-ended output or half of a differential output with
CLK0B being the othe r differential ha lf. If un us ed , lea ve this pin
floating.
23 RSVD_GND GND GND Ground.
Must be connected to system ground. Minimize the ground path
impedance for optimal performance of this device.
24 VDD VDD Supply Core Supply Voltage.
The device operates from a 1.8, 2.5, or 3.3 V supply. A 0.1 µF
bypass capacitor should be located very close to this pin.
GND
PAD GND GND GND Ground Pad.
This is the large pad in the center of the package. Device
specifications cannot be guaranteed unless the ground pad is
properly connected to a ground pl ane on the PCB. See Table 19,
“PCB Land Pattern,” on page 40 for ground via requirements.
Table 16. Si5338 Pin Descriptions (Continued)
Pin # Pin Name I/O Signal Type Description
Si5338
Rev. 1.6 37
8. Device Pinout by Part Number
The Si5338 is orderable in three different speed grades: Si5338A/D/G/K/N have a maximum output clock
frequency limit of 710 MHz. Si5338B/E/H/L/P have a maximum output clock frequency of 350 MHz. Si5338C/F/J/
M/Q have a maximum output clock frequency of 200 MHz.
Devices are also orderable according to the pin control functions available on Pins 3 and 4:
CLKIN—single-ended clock input
I2C_LSB—determines the LSB bit of the 7-bit I2C address
FINC—frequency increment pin
FDEC—frequency decrement pin
PINC—phase increment pin
PDEC—phase decrement pin
FDBK—single-ended feedback input
OEB—output enable
Table 17. Pin Function by Part Number
Pin # Si5338A: 710 MHz
Si5338B: 350 MHz
Si5338C: 200 MHz
Si5338D: 710 MHz
Si5338E: 350 MHz
Si5338F: 200 MHz
Si5338G: 710 MHz
Si5338H: 350 MHz
Si5338J: 200 MHz
Si5338K: 710 MHz
Si5338L: 35 0 MHz
Si5338M: 200 MHz
Si5338N: 710 MHz
Si5338P: 350 MHz
Si5338Q: 200 MHz
1CLKIN
1CLKIN1CLKIN1CLKIN1CLKIN1
2CLKINB
1CLKINB1CLKINB1CLKINB1CLKINB1
3CLKIN
2PINC FINC OEB CLKIN2
4 I2C_LSB PDEC FDEC I2C_LSB FDBK3
5FDBK
4FDBK4FDBK4FDBK4FDBK4
6FDBKB
4FDBKB4FDBKB4FDBKB4FDBKB4
7 VDD VDD VDD VDD VDD
8INTRINTRINTRINTRINTR
9 CLK3B CLK3B CLK3B CLK3B CLK3B
10 CLK3A CLK3A CLK3A CLK3A CLK3A
11 VDDO3 VDDO3 VDDO3 VDDO3 VDDO3
12 SCL SCL SCL SCL SCL
13 CLK2B CLK2B CLK2B CLK2B CLK2B
14 CLK2A CLK2A CLK2A CLK2A CLK2A
15 VDDO2 VDDO2 VDDO2 VDDO2 VDDO2
16 VDDO1 VDDO1 VDDO1 VDDO1 VDDO1
Notes:
1. CLKIN/CLKINB on pins 1 and 2 are differential clock inputs or XTAL inputs.
2. CLKIN on pin 3 is a single-ended clock input.
3. FDBK on pin 4 is a single-ended feedback input.
4. FDBK/FDBKB on pins 5 and 6 are differential feedback inputs.
Si5338
38 Rev. 1.6
17 CLK1B CLK1B CLK1B CLK1B CLK1B
18 CLK1A CLK1A CLK1A CLK1A CLK1A
19SDASDASDASDASDA
20 VDDO0 VDDO0 VDDO0 VDDO0 VDDO0
21 CLK0B CLK0B CLK0B CLK0B CLK0B
22 CLK0A CLK0A CLK0A CLK0A CLK0A
23 GND GND GND GND GND
24 VDD VDD VDD VDD VDD
Table 17. Pin Function by Part Number (Continued)
Pin # Si5338A: 710 MHz
Si5338B: 350 MHz
Si5338C: 200 MHz
Si5338D: 710 MHz
Si5338E: 350 MHz
Si5338F: 200 MHz
Si5338G: 710 MHz
Si5338H: 350 MHz
Si5338J: 200 MHz
Si5338K: 710 MHz
Si5338L: 35 0 MHz
Si5338M: 200 MHz
Si5338N: 710 MHz
Si5338P: 350 MHz
Si5338Q: 200 MHz
Notes:
1. CLKIN/CLKINB on pins 1 and 2 are differential clock inputs or XTAL inputs.
2. CLKIN on pin 3 is a single-ended clock input.
3. FDBK on pin 4 is a single-ended feedback input.
4. FDBK/FDBKB on pins 5 and 6 are differential feedback inputs.
Si5338
Rev. 1.6 39
9. Package Outline: 24-Lead QFN
Figure 25. 24-Lead Quad Flat No-lead (QFN)
Table 18. Package Dimensions
Dimension Min Nom Max
A 0.80 0.85 0.90
A1 0.00 0.02 0.05
b 0.18 0.25 0.30
D 4.00 BSC.
D2 2.35 2.50 2.65
e 0.50 BSC.
E 4.00 BSC.
E2 2.35 2.50 2.65
L 0.30 0.40 0.50
aaa 0.10
bbb 0.10
ccc 0.08
ddd 0.10
eee 0.05
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Outline MO-220, variation VGGD-8.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
Si5338
40 Rev. 1.6
10. Recommended PCB Land Pattern
Table 19. PCB Land Pattern
Dimension Min Nom Max
P1 2.50 2.55 2.60
P2 2.50 2.55 2.60
X1 0.20 0.25 0.30
Y1 0.75 0.80 0.85
C1 3.90
C2 3.90
E0.50
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on the IPC-7351 guidelines.
4. Connect the center ground pad to a ground plane with no less than five vias. These 5 vias should have a length of no
more than 20 mils to the ground plane. Via drill size should be no smaller than 10 mils. A longer distance to the ground
plane is allowed if more vias are used to keep the inductance from increasing.
Solder Mask Design
5. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is
to be 60 µm mi nimum, all the way around the pad.
Stencil Design
6. A stainless steel, laser-cut and electro-polished stencil with tra pezoidal walls should be used to assure good solder
paste release.
7. The stencil thickness should be 0.125 mm (5 mils).
8. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins.
9. A 2x2 array of 1.0 mm square openings on 1.25 mm pitch should be used for the center ground pad.
Card Assembly
10. A No-Clean, Type-3 solder paste is recommended.
11. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
Si5338
Rev. 1.6 41
11. Top Marking
11.1. Si5338 Top Marking
11.2. Top Marking Explanation
Table 20. Top Marking Explanation
Line Characters Description
Line 1 Si5338 Base part number.
Line 2 Xxxxxx
X = Frequency and configuration code.
xxxxx = Optional NVM code for custom factory-programmed devices
(characters are not included for blank devices) .
See "12. Order ing Info rm at ion" on page 42.
Line 3 RTTTTT R = Product revision.
TTTTT = Manufacturing trace code.
Line 4
Circle with 0.5 mm diameter;
left-justified Pin 1 indicator.
YYWW
YY = Year.
WW = Work week.
Characters correspond to the year and work week of package assem-
bly.
YYWW
RTTTTT
Xxxxxx
Si5338
Si5338
42 Rev. 1.6
12. Ordering Information
Si5338X BXXXXX GMR
B = Product Revision B
XXXXX = NV M code (optional).
For blank devices, order Si5338X-B-GM(R).
For custom NVM configurations, a unique 5-digit ordering code
will be ass igned by the fa ctory. Consult y our sales representative
for custom NVM configurat ions.
Operat ing Temp Range: -40 to +85 °C
Package: 4 x 4 mm QFN, ROHS6, Pb-free
R = Tape & Reel (ordering option)
When ordering non Tape & Reel shipment
media, contact your sales representative
for more information.
Si5338A
Si5338B
Si5338C
Si5338D
Si5338E
Si5338F
Si5338G
Si5338H
Si5338J
Si5338K
Si5338L
Si5338M
Si5338N
Si5338P
Si5338Q
0.16 MHz to 710 MHz I2C_LSB
0.16 MHz to 350 MHz I2C_LSB
0.16 MHz to 200 MHz I2C_LSB
0.16 MHz to 710 MHz Phase Inc/Dec Pin Control
0.16 MHz to 350 MHz Phase Inc/Dec Pin Control
0.16 MHz to 200 MHz Phase Inc/Dec Pin Control
0.16 MHz to 710 MHz Freq I nc/Dec Pin Control
0.16 MHz to 350 MHz Freq I nc/Dec Pin Control
0.16 MHz to 200 MHz Freq I nc/Dec Pin Control
0.16 MHz to 710 MHz OEB Pin Control + I2C_LSB
0.16 MHz to 350 MHz OEB Pin Control + I2C_LSB
0.16 MHz to 200 MHz OEB Pin Control + I2C_LSB
0.16 MHz to 710 MHz Four Inputs (2 Differential, 2 Single-ended)
0.16 MHz to 350 MHz Four Inputs (2 Differential, 2 Single-ended)
0.16 MHz to 200 MHz Four Inputs (2 Differential, 2 Single-ended)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Si5338 EVB
PROG - EVB
Evaluation B oards
Si5338 Evaluati on Board
Si5338 Field Programmer
Si5338/56
Si5338
44 Rev. 1.6
DOCUMENT CHANGE LIST
Revision 0.2 to Revision 0.3
Changed minimum output clock frequency from
5MHz to 1MHz.
Updated slew rates .
Updated " Features" on page 1.
Updated Table 6, “Input and Output Clock
Characteristics,” on page 8.
Deleted Table 12, “Output Driver Slew Rate Control”.
Revision 0.3 to Revision 0.5
Major editorial changes to all sections to improve
clarity
Completed electrical specification tables with final
characterization results
Revised the maximum input and output frequencies
from 700 MHz to 710 MHz
Improved jitter specifications to reflect updated
characterization results
Added new Si5338N/ P/Q ord er ing codes
Added typical application diagrams
Added an application section to highlight the
flexibility of the Si5338 in various timing functions
Added a configuration section to clarify configuration
options
Revision 0.5 to Revision 0.55
Editorial changes to section 3.5 “Configuring the
Si5338” to improve clarity on orde ring custom
Si5338 and on configuring “blank” Si5338.
Added pin number s to de vic e package drawin gs.
Updated orde r ing info rm a tion to inclu de evaluation
boards.
Updated first page description and applications
Added JC to specification tables.
Added GbE RM jitter specification with 1.875–
20 MHz integration band.
Revision 0.55 to Revision 0.6
Changed output duty cycle to 45–55%.
All I2C address now in binary.
Changed ordering information to reflect 710 MHz
limit.
Info on POR and soft reset ad ded.
Updated Figu re 15 on page 28.
Added registe r sec tio n.
Update programming procedure in “3.5. Configuring
the Si5338” to improve robustness.
Updated Figure 9 to include the entire programm ing
procedure.
Added "3.2.1. Loss-of-Signal (LOS) Alarm
Detectors" on page 19 to show the location of the
LOS detector circuits.
Updated input circuit diagrams in "3.2. Input Stage"
on page 19.
Update block diagrams with new input circuit
diagrams.
Revision 0.6 to Revision 0.65
Updated Figure 9, “I2C Programming Procedure,” on
page 23 for consistency with register description.
Revision 0.65 to Revision 1.0
Expanded PCI jitter specifications in Table 12.
Moved “Si5338 Registers” section to AN411.
Added I2C data rate specifications to Table 15.
Revised CMOS output currents down for each
CMOS driver that is active in Table 3.
Clarified CMOS output loads in Table 3
Added peak reflow temperature and footnote in
Table 2.
Added sticky and mask register info in "3.6. Status
Indicators" on page 24.
Added more information to Table note about CMOS
outputs and jitter in Table 12.
Changed all reference of MultiSynth Mn to MSn
Added "11. Top Marking" on page 41.
Reworded 3.5.2 and 3.5.3 for clarity.
Revision 1.0 to Revision 1.1
Replaced all references to AN411 with "Si5338
Reference Manual" (AN411 has been replaced by
the Si5338 Reference Manual).
Clarified crystal specifications in Tables 8, 9, 10, 11
and added references to AN360.
Revision 1.1 to Revision 1.2
Updated Table 2 on page 4.
Added CML current consumption specification.
Updated Table 6 on page 8.
Corrected tR/tF for output clocks (single-ended) from
1.7 ns (max ) to 2.0 ns (max).
Added CML Output Voltage parameter.
Updated Table 12 on page 13.
Updated typical specifications for total jitter for PCI
Express 1.1 Common clocked topology.
Updated typical specifications for RMS jitter for PCI
Express 2.1 Common clocked topology.
Removed RMS jitter specification for PCI Express 2.1
Si5338
Rev. 1.6 45
and 3.0 Data clocked t o po l og y.
Added Table 13, “Jitter Specifications, Clock Buffer
Mode (PLL Bypass)*,” on page 15.
Updated typical additive jitter (12 kHz–20 MHz) from
0.150 to 0.165 ps RMS.
Updated Figure 9 on page 23 to provide work-
around for spread spectrum errata.
Removed "3.5.4. Modifying a MultiSynth Output
Divider Ratio/Frequency Configuration". A soft reset
is now recommended after any changes to the
feedback or output divider s.
Added " " on page 42.
Revision 1.2 to Revision 1.3
Removed down spread spectrum errata that has
been corrected in revision B.
Updated order i ng inform a tion to re fe r to re vision B
silicon.
Updated top marking explanation in Table 20.
Added further explanation to describe revision-
specific behavior of center spread spectrum in
section 3.10.7.
Revision 1.3 to Revision 1.4
Added link to errata document.
Revision 1.4 to Revision 1.5
Added setup and ho ld tim e specifications for I2C in
Table 15.
Revision 1.5 to Revision 1.6
Updated Features on page 1.
Updated Description on page 1.
Updated specs in Table 12.
Disclaimer
Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers
using or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific
device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Laboratories
reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy
or completeness of the included information. Silicon Laboratories shall have no liability for the consequences of use of the information supplied herein. This document does not imply
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