DC954A-C - Linear Technology

640220fa

LT6402-20

300MHz Low Distortion, Low

Noise Differential Ampliﬁ er/

ADC Driver (AV = 20dB)

The LT®6402-20 is a low distortion, low noise differential

ampliﬁ er/ADC driver for use in applications from DC to

300MHz. The LT6402-20 has been designed for ease of

use, with minimal support circuitry required. Exceptionally

low input-referred noise and low distortion (with either

single-ended or differential inputs) make the LT6402-20

an excellent solution for driving high speed 12-bit and

14-bit ADCs. In addition to the normal unﬁ ltered outputs

(+OUT and –OUT), the LT6402-20 has a built-in 75MHz

differential low pass ﬁ lter and an additional pair of ﬁ ltered

outputs (+OUTFILTERED, –OUTFILTERED) to reduce

external ﬁ ltering components when driving high speed

ADCs. The output common mode voltage is easily set via

the VOCM pin, eliminating an output transformer or AC-

coupling capacitors in many applications.

The LT6402-20 is designed to meet the demanding require-

ments of communications transceiver applications. It can

be used as a differential ADC driver, a general-purpose

differential gain block, or in other applications requiring

differential drive. The LT6402-20 can be used in data

acquisition systems required to function at frequencies

down to DC.

The LT6402-20 operates on a 5V supply and consumes

30mA. It comes in a compact 16-lead 3mm × 3mm QFN pack-

age and operates over a –40°C to 85°C temperature range.

■ Differential ADC Driver for:

Imaging

Communications

■ Differential Driver/Receiver

■ Single Ended to Differential Conversion

■ Differential to Single Ended Conversion

■ Level Shifting

■ IF Sampling Receivers

■ SAW Filter Interfacing/Buffering

■ 300 MHz –3dB Bandwidth

■ Fixed Gain of 20dB

■ Low Distortion:

51dBm OIP3, –81dBc HD3 (20MHz, 2VP-P)

■ Low Noise:

12.4dB NF, en = 1.9nV/√Hz (20MHz)

■ Differential Inputs and Outputs

■ Additional Filtered Outputs

■ Adjustable Output Common Mode Voltage

■ DC- or AC-Coupled Operation

■ Minimal Support Circuitry Required

■ Small 0.75mm Proﬁ le 16-Lead 3mm × 3mm QFN

Package

APPLICATIO S

FEATURES DESCRIPTIO

TYPICAL APPLICATIO

, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.

All other trademarks are the property of their respective owners.

6402 TA01a

IF IN

LT6402-20

–INA

–INB

VOCM

VCC

VEE

+INB

+INA

10Ω

10ΩLTC®2249

0.1µF

+OUT

–OUT

AIN+

AIN–

VCM

Distortion vs Frequency, Differential

Input, No RLOAD

FREQUENCY (MHz)

–100

DISTORTION (dBc)

–90

–80

–70

–60

–40

10 100

64022 G08

–50

HD2

HD3

FILTERED OUTPUTS

VOUT = 2VP-P

LT6402-20

640220fa

Total Supply Voltage (VCCA/VCCB/VCCC to

VEEA/VEEB/VEEC) ...................................................5.5V

Input Current (+INA, –INA, +INB, –INB,

VOCM, ENABLE) ................................................±10mA

Output Current (Continuous)

+OUT, –OUT ...................................................±100mA

+OUTFILTERED, –OUTFILTERED ......................±30mA

Output Short Circuit Duration (Note 2) ............ Indeﬁ nite

Operating Temperature Range (Note 3) ... –40°C to 85°C

Speciﬁ ed Temperature Range (Note 4) .... –40°C to 85°C

Storage Temperature Range ................... –65°C to 125°C

Junction Temperature ........................................... 125°C

Lead Temperature Range (Soldering 10 sec) ........ 300°C

(Note 1)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Input/Output Characteristics (+INA, +INB, –INA, –INB, +OUT, –OUT, +OUTFILTERED, –OUTFILTERED)

GDIFF Gain Differential (+OUT, –OUT), VIN = ±160mV

Differential

●18.9 20 20.9 dB

VSWINGMIN Single-Ended +OUT, –OUT, +OUTFILTERED,

–OUTFILTERED, VIN = ±600mV Differential ●

0.25 0.35

0.5

VSWINGMAX Single-Ended +OUT, –OUT, +OUTFILTERED,

–OUTFILTERED, VIN = ±600mV Differential ●

3.4

3.3

3.6 V

VSWINGDIFF Output Voltage Swing Differential (+OUT, –OUT), VIN = ±600mV

Differential ●

6.1

5.6

P-P

VP-P

IOUT Output Current Drive ●±30 ±35 mA

VOS Input Offset Voltage

●

–6.5

–10

1 6.5

TCVOS Input Offset Voltage Drift TMIN to TMAX ●2.5 µV/°C

ABSOLUTE AXI U RATI GS

PACKAGE/ORDER I FOR ATIO

UUW

16 15 14 13

5 6 7 8

TOP VIEW

UD PACKAGE

16-LEAD (3mm × 3mm) PLASTIC QFN

17 11

1VCCC

VOCM

VCCA

VEEA

VEEC

ENABLE

VCCB

VEEB

+INA

+INB

–INA

–INB

+OUT

+OUTFILTERED

–OUTFILTERED

–OUT

TJMAX = 125°C, θJA = 68°C/W, θJC = 4.2°C/W

EXPOSED PAD IS VEE (PIN 17)

MUST BE SOLDERED TO THE PCB

ORDER PART NUMBER UD PART MARKING*

LT6402CUD-20

LT6402IUD-20

LCBC

Order Options Tape and Reel: Add #TR

Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF

Lead Free Part Marking: http://www.linear.com/leadfree/

Consult LTC Marketing for parts speciﬁ ed with wider operating temperature ranges.

*The temperature grade is identiﬁ ed by a label on the shipping container.

The ● denotes the speciﬁ cations which apply over the full operating

temperature range, otherwise speciﬁ cations are at TA = 25°C. VCCA = VCCB = VCCC = 5V, VEEA = VEEB = VEEC = 0V,

⎯

E = 0.8V, +INA

shorted to +INB (+IN), –INA shorted to –INB (–IN), VOCM = 2.2V, Input common mode voltage = 2.2V, no RLOAD unless otherwise noted.

DC ELECTRICAL CHARACTERISTICS

640220fa

LT6402-20

The ● denotes the speciﬁ cations which apply over the full operating

temperature range, otherwise speciﬁ cations are at TA = 25°C. VCCA = VCCB = VCCC = 5V, VEEA = VEEB = VEEC = 0V,

⎯

E = 0.8V, +INA

shorted to +INB (+IN), –INA shorted to –INB (–IN), VOCM = 2.2V, Input common mode voltage = 2.2V, no RLOAD unless otherwise noted.

DC ELECTRICAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

IVRMIN Input Voltage Range, MIN Single-Ended ●0.9 V

IVRMAX Input Voltage Range, MAX Single-Ended ●3.9 V

RINDIFF Input Resistance ●77 100 122 Ω

CINDIFF Input Capacitance 1pF

CMRR Common Mode Rejection Ratio Input Common Mode 0.9V to 3.9V ●45 70 dB

ROUTDIFF Output Resistance 0.3 Ω

COUTDIFF Output Capacitance 0.8 pF

Common Mode Voltage Control (VOCM Pin)

GCM Common Mode Gain Differential (+OUT, –OUT), VOCM = 1.2V to 3.6V

Differential (+OUT, –OUT), VOCM = 1.4V to 3.4V ●

0.9

1 1.1

1.1

V/V

VOCMMIN Output Common Mode Voltage

Adjustment Range, MIN ●

1.2

1.4

VOCMMAX Output Common Mode Voltage

Adjustment Range, MAX

Single-Ended

●

3.6

3.4

VOSCM Output Common Mode Offset

Voltage

Measured from VOCM to Average of +OUT and –OUT –30 4 30 mV

IBIASCM VOCM Input Bias Current ●515 µA

RINCM VOCM Input Resistance ●0.8 3 MΩ

CINCM VOCM Input Capacitance 1pF

⎯

E Pin

VIL

⎯

E Input Low Voltage ●0.8 V

VIH

⎯

E Input High Voltage ●2V

IIL

⎯

E Input Low Current

⎯

E = 0.8V ●0.5 µA

IIH

⎯

E Input High Current

⎯

E = 2V ●13 µA

Power Supply

VSOperating Range ●4 5 5.5 V

ISSupply Current

⎯

E = 0.8V ●24 30 37 mA

ISDISABLED Supply Current (Disabled)

⎯

E = 2V ●250 500 µA

PSRR Power Supply Rejection Ratio 4V to 5.5V ●55 90 dB

LT6402-20

640220fa

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Input/Output Characteristics

–3dBBW –3dB Bandwidth 20mVP-P Differential (+OUT, –OUT) 200 300 MHz

0.1dBBW Bandwidth for 0.1dB Flatness 20mVP-P Differential (+OUT, –OUT) 30 MHz

0.5dBBW Bandwidth for 0.5dB Flatness 20mVP-P Differential (+OUT, –OUT) 80 MHz

SR Slew Rate 3.2VP-P Differential (+OUT, –OUT) 400 V/µs

ts1% 1% Settling 1% Settling for a 1VP-P Differential Step

(+OUT, –OUT)

8ns

tON Turn-On Time 100 ns

tOFF Turn-Off Time 1µs

Common Mode Voltage Control (VOCM Pin)

–3dBBWCM Common Mode Small-Signal –3dB

Bandwidth

0.1VP-P at VOCM, Measured Single-Ended at +OUT

and –OUT

200 MHz

SRCM Common Mode Slew Rate 1.3V to 3.4V Step at VOCM 250 V/µs

Noise/Harmonic Performance Input/Output Characteristics

10MHz Signal

Second/Third Harmonic Distortion 2VP-P Differential (+OUTFILTERED, –OUTFILTERED) –85 dBc

2VP-P Differential (+OUT, –OUT) –85 dBc

Third-Order IMD 2VP-P Differential Composite (+OUTFILTERED,

–OUTFILTERED), f1 = 9.5MHz, f2 = 10.5MHz

–93 dBc

OIP310M Output Third-Order Intercept Differential (+OUTFILTERED, –OUTFILTERED),

f1 = 9.5MHz, f2 = 10.5MHz (Note 5)

49.5 dBm

NF Noise Figure Measured Using DC954A Demo Board 12.3 dB

en10M Input Referred Noise Voltage Density 1.85 nV/√Hz

1dB Compression Point RL = 100Ω (Note 5) 19.5 dBm

20MHz Signal

Second/Third Harmonic Distortion 2VP-P Differential (+OUTFILTERED, –OUTFILTERED) –81 dBc

2VP-P Differential (+OUT, –OUT) –81 dBc

Third-Order IMD 2VP-P Differential Composite (+OUTFILTERED,

–OUTFILTERED), f1 = 19.5MHz, f2 = 20.5MHz

–96 dBc

2VP-P Differential Composite (+OUT, –OUT),

RL = 400Ω, f1 = 19.5MHz, f2 = 20.5MHz

–91 dBc

OIP320M Output Third-Order Intercept Differential (+OUTFILTERED, –OUTFILTERED),

f1 = 19.5MHz, f2 = 20.5MHz (Note 5)

51 dBm

NF Noise Figure Measured Using DC954A Demo Board 12.4 dB

en20M Input Referred Noise Voltage Density 1.9 nV/√Hz

1dB Compression Point RL = 100Ω (Note 5) 18 dBm

A = 25°C, VCCA = VCCB = VCCC = 5V, VEEA = VEEB = VEEC = 0V,

⎯

E = 0.8V, +INA shorted to +INB (+IN), –INA shorted to –INB (–IN), VOCM = 2.2V, Input common mode voltage = 2.2V, no RLOAD

unless otherwise noted.

AC ELECTRICAL CHARACTERISTICS

640220fa

LT6402-20

FREQUENCY (MHz)

GAIN (dB)

10 100 1000

64022 G01

–5

–10

UNFILTERED

FILTERED

VIN = 20mVP-P

UNFILTERED: RLOAD = 400Ω

FILTERED: RLOAD = 300Ω (EXTERNAL)

+ 100Ω (INTERNAL, FILTERED OUTPUTS)

FREQUENCY (MHz)

GAIN (dB)

10 100 1000

34022 G02

VIN = 20mVP-P

UNFILTERED OUTPUTS

0pF

1.6pF

5pF

10pF

FREQUENCY (MHz)

GAIN (dB)

10 100 1000

64022 G03

–5

–10

UNFILTERED

FILTERED

VIN = 20mVP-P

UNFILTERED: RLOAD = 100Ω

FILTERED: RLOAD = 100Ω

(INTERNAL, FILTERED OUTPUTS)

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: As long as output current and junction temperature are kept below

the Absolute Maximum Ratings, no damage to the part will occur.

Note 3: The LT6402 is guaranteed functional over the operating

temperature range of –40°C to 85°C.

Note 4: The LT6402C is guaranteed to meet speciﬁ ed performance from

0°C to 70°C. It is designed, characterized and expected to meet speciﬁ ed

performance from –40°C and 85°C but is not tested or QA sampled

at these temperatures. The LT6402I is guaranteed to meet speciﬁ ed

performance from –40°C to 85°C.

Note 5: Since the LT6402-20 is a feedback ampliﬁ er with low output

impedance, a resistive load is not required when driving an ADC.

Therefore, typical output power is very small. In order to compare the

LT6402-20 with typical gm ampliﬁ ers that require 50Ω output loading, the

LT6402-20 output voltage swing driving an ADC is converted to OIP3 and

P1dB as if it were driving a 50Ω load.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

25MHz Signal

Second/Third Harmonic Distortion 2VP-P Differential (+OUTFILTERED, –OUTFILTERED) –80 dBc

2VP-P Differential (+OUT, –OUT) –80 dBc

Third-Order IMD 2VP-P Differential Composite (+OUTFILTERED,

–OUTFILTERED), f1 = 24.5MHz, f2 = 25.5MHz

–86 dBc

2VP-P Differential Composite (+OUT, –OUT),

RL = 400Ω, f1 = 24.5MHz, f2 = 25.5MHz

–84 dBc

OIP325M Output Third-Order Intercept Differential (+OUTFILTERED, –OUTFILTERED),

f1 = 24.5MHz, f2 = 25.5MHz (Note 5)

46 dBm

NF Noise Figure Measured Using DC954A Demo Board 12.5 dB

en25M Input Referred Noise Voltage Density 1.9 nV/√Hz

1dB Compression Point RL = 100Ω (Note 5) 16.6 dBm

AC ELECTRICAL CHARACTERISTICS

A = 25°C, VCCA = VCCB = VCCC = 5V,VEEA = VEEB = VEEC = 0V,

⎯

E = 0.8V, +INA shorted to +INB (+IN), –INA shorted to –INB (–IN), VOCM = 2.2V, Input common mode voltage = 2.2V, no RLOAD

unless otherwise noted.

TYPICAL PERFORMANCE CHARACTERISTICS

Frequency Response

RLOAD = 400Ω

Frequency Response

RLOAD = 100Ω

Frequency Response vs

CLOAD, RLOAD = 400Ω

LT6402-20

640220fa

FREQUENCY (MHz)

OUTPUT IP3 (dBm)

10 15 20 25

64022 G06

30 35

UNFILTERED OUTPUTS

FILTERED OUTPUTS

2 TONES, 2VP-P COMPOSITE

1MHz TONE SPACING

FREQUENCY (MHz)

–110

THIRD ORDER IMD (dBc)

–100

–90

–80

10 15 20 25

64022 G04

–70

–60

–105

–95

–85

–75

–65

UNFILTERED OUTPUTS

FILTERED OUTPUTS

2 TONES, 2VP-P COMPOSITE

1MHz TONE SPACING

FREQUENCY (MHz)

–110

THIRD ORDER IMD (dBc)

–100

–90

–80

10 15 20 25

64022 G05

–70

–60

–105

–95

–85

–75

–65

UNFILTERED OUTPUTS

FILTERED OUTPUTS

2 TONES, 2VP-P COMPOSITE

1MHz TONE SPACING

FREQUENCY (MHz)

OUTPUT IP3 (dBm)

10 15 20 25

64022 G07

30 35

UNFILTERED OUTPUTS

FILTERED OUTPUTS

2 TONES, 2VP-P COMPOSITE

1MHz TONE SPACING

FREQUENCY (MHz)

–100

DISTORTION (dBc)

–90

–80

–70

–60

–40

10 100

64022 G08

–50

HD2

HD3

FILTERED OUTPUTS

VOUT = 2VP-P

FREQUENCY (MHz)

–100

DISTORTION (dBc)

–90

–80

–70

–60

–40

10 100

64022 G10

–50

HD2

HD3

UNFILTERED OUTPUTS

VOUT = 2VP-P

OUTPUT AMPLITUDE (dBm)

DISTORTION (dBc)

–80

–75

–70

64022 G12

–85

–90

–95 1234567 9

HD2

HD3

FILTERED OUTPUTS

20MHz DIFFERENTIAL INPUT

NO RLOAD

OUTPUT AMPLITUDE (dBm)

DISTORTION (dBc)

–70

–72

–74

–76

–78

–80

–82

–84

– 86

64022 G13

246 107135 9

HD2

HD3

UNFILTERED OUTPUTS

20MHz DIFFERENTIAL INPUT

NO RLOAD

FREQUENCY (Hz)

OUTPUT 1dB COMPRESSION (dBm)

10 100 1000

64022 G14

–5

–10

400Ω LOAD

UNFILTERED OUTPUTS

100Ω LOAD

Third Order Intermodulation

Distortion vs Frequency

Differential Input, No RLOAD

Third Order Intermodulation

Distortion vs Frequency

Differential Input, RLOAD = 400Ω

Output Third Order Intercept vs

Frequency, Differential Input,

No RLOAD

TYPICAL PERFOR A CE CHARACTERISTICS

Distortion vs Output Amplitude

20MHz Differential Input,

No RLOAD (Filtered)

Output 1dB Compression

vs Frequency

Output Third Order Intercept vs

Frequency, Differential Input,

RLOAD = 400Ω

Distortion vs Frequency,

Differential Input, No RLOAD

(Filtered)

Distortion vs Frequency,

Differential Input, No RLOAD

(Unﬁ ltered)

Distortion vs Output Amplitude

20MHz Differential Input,

No RLOAD (Unﬁ ltered)

640220fa

LT6402-20

FREQUENCY (MHz)

NOISE FIGURE (dB)

100 1000

64022 G15

MEASURED USING DC954A DEMO BOARD

FREQUENCY (MHz)

INPUT REFERRED NOISE VOLTAGE (nV/√Hz)

100 1000

64022 G16

FREQUENCY (MHz)

–70

ISOLATION (dB)

–50

–30

10 100 1000

64022 G17

–90

–80

–60

–40

–100

–110

UNFILTERED OUTPUTS

FREQUENCY (MHz)

INPUT IMPEDANCE (MAGNITUDE Ω, PHASE°)

400

350

300

250

200

150

100

–50

–100

10 100 1000

64022 G18

IMPEDANCE MAGNITUDE

IMPEDANCE PHASE

FREQUENCY (MHz)

OUTPUT IMPEDANCE (Ω)

1000

100

100 1000

64022 G19

UNFILTERED OUTPUTS

FREQUENCY (MHz)

–15

INPUT REFLECTION COEFFICIENT (S11)

–10

–5

10 100 1000

34022 G20

–20

–25

–30

–35

MEASURED USING

DC954A DEMO BOARD

FREQUENCY (MHz)

–20

OUTPUT REFLECTION COEFFICIENT (S22)

–10

10 100 1000

64022 G21

–30

–25

–15

–5

–35

–40

MEASURED USING

DC954A DEMO BOARD

FREQUENCY (MHz)

PSRR, CMRR (dB)

10 100 1000

64022 G22

120

100

110

UNFILTERED OUTPUTS

PSRR

CMRR 2.15

2.20

2.25

OUTPUT VOLTAGE (V)

TIME (5ns/DIV) 64022 G23

RLOAD = 100Ω PER OUTPUT

Noise Figure vs Frequency

Input Referred Noise Voltage

vs Frequency Isolation vs Frequency

TYPICAL PERFOR A CE CHARACTERISTICS

Differential Input Impedance

vs Frequency

Differential Output Impedance

vs Frequency

Input Reﬂ ection Coefﬁ cient

vs Frequency

Output Reﬂ ection Coefﬁ cient

vs Frequency PSRR, CMRR vs Frequency Small-Signal Transient Response

LT6402-20

640220fa

OUTPUT VOLTAGE (V)

1.8

3.0

3.2

3.4

TIME (10ns/DIV)

64022 G24

1.4

2.6

2.2

1.6

2.8

1.2

2.4

2.0

RLOAD = 100Ω PER OUTPUT

OUTPUT VOLTAGE (V)

2.5

3.0

3.5

TIME (25ns/DIV)

64022 G25

1.5

4.0

2.0

1.0

0.5

RLOAD = 100Ω PER OUTPUT

+OUT

–OUT

OUTPUT COMMON MODE VOLTAGE (V)

1 1.2

–90

DISTORTION (dBc)

–86

–80

1.4 1.8 2.0

64022 G26

–88

–82

–84

1.6 2.2 2.4

FILTERED OUTPUTS, NO RLOAD

VOUT = 20MHz 2VP-P

HD3

HD2

OUTPUT VOLTAGE (V)

1.5

2.0

2.5

TIME (125ns/DIV)

64022 G27

1.0

0.5

3.0

3.5

4.0 RLOAD = 100

PER OUTPUT

+OUT

–OUT

ENABLE

+OUT

–OUT

OUTPUT VOLTAGE (V)

1.5

2.0

2.5

TIME (250ns/DIV)

64022 G28

1.0

0.5

3.0

3.5

4.0 RLOAD = 100

PER OUTPUT

ENABLE

FREQUENCY (MHz)

AMPLITUDE (dBFS)

10 20 30 40

64022 G29

–120

–110

–100

–80

–60

–40

–20

–90

–70

–50

–30

–10

515

25 35

8192 POINT FFT

fIN = 10MHz, –1dBFS

FILTERED OUTPUTS

FREQUENCY (MHz)

AMPLITUDE (dBFS)

10 20 30 40

64022 G30

–120

–110

–100

–80

–60

–40

–20

–90

–70

–50

–30

–10

515

25 35

8192 POINT FFT

fIN = 20MHz, –1dBFS

FILTERED OUTPUTS

FREQUENCY (MHz)

AMPLITUDE (dBFS)

10 20 30 40

64022 G31

–120

–110

–100

–80

–60

–40

–20

–90

–70

–50

–30

–10

515

25 35

8192 POINT FFT

fIN = 25MHz, –1dBFS

FILTERED OUTPUTS

FREQUENCY (MHz)

–140

AMPLITUDE (dBFS)

–120

–100

–80

–40

510 12.5

–20

–60

–130

–110

–90

–10

–50

–30

–70

2.5 7.5 15 17.5 20 22.5

64022 G32

32768 POINT FFT

TONE 1 AT 19.5MHz, –7dBFS

TONE 2 AT 20.5MHz, –7dBFS

FILTERED OUTPUTS

TYPICAL PERFORMANCE CHARACTERISTICS

Large-Signal Transient Response Overdrive Recovery Time

Distortion vs Output Common

Mode Voltage LT6402-20 Driving

LTC2249 14-Bit ADC

Turn-On Time Turn-Off Time

10MHz 8192 Point FFT,

LT6402-20 Driving

LTC2249 14-Bit ADC

20MHz 8192 Point FFT,

LT6402-20 Driving

LTC2249 14-Bit ADC

25MHz 8192 Point FFT,

LT6402-20 Driving

LTC2249 14-Bit ADC

20MHz 2-Tone 32768 Point FFT,

LT6402-20 Driving

LTC2249 14-Bit ADC

640220fa

LT6402-20

VOCM (Pin 2): This pin sets the output common mode

voltage. Without additional biasing, both inputs bias to

this voltage as well. This input is high impedance.

VCCA, VCCB, VCCC (Pins 3, 10, 1): Positive Power Supply

(Normally Tied to 5V). All three pins must be tied to the

same voltage. Bypass each pin with 1000pF and 0.1µF

capacitors as close to the package as possible. Split

supplies are possible as long as the voltage between VCC

and VEE is 5V.

VEEA, VEEB, VEEC (Pins 4, 9, 12): Negative Power Supply

(Normally Tied to Ground). All three pins must be tied to

the same voltage. Split supplies are possible as long as

the voltage between VCC and VEE is 5V. If these pins are

not tied to ground, bypass each pin with 1000pF and 0.1µF

capacitors as close to the package as possible.

+OUT, –OUT (Pins 5, 8): Outputs (Unﬁ ltered). These

pins are high bandwidth, low-impedance outputs. The DC

output voltage at these pins is set to the voltage applied

at VOCM.

+OUTFILTERED, –OUTFILTERED (Pins 6, 7): Filtered

Outputs. These pins add a series 50Ω resistor from the

unﬁ ltered outputs and three 14pF capacitors. Each output

has 14pF to VEE, plus an additional 14pF between each pin

(See the Block Diagram). This ﬁ lter has a –3dB bandwidth

of 75MHz.

⎯

E (Pin 11): This pin is a TTL logic input referenced

to the VEEC pin. If low, the LT6402 is enabled and draws

typically 30mA of supply current. If high, the LT6402 is

disabled and draws typically 250µA.

+INA, +INB (Pins 15, 16): Positive Inputs. These pins are

normally tied together. These inputs may be DC- or AC-

coupled. If the inputs are AC-coupled, they will self-bias

to the voltage applied to the VOCM pin.

–INA, –INB (Pins 14, 13): Negative Inputs. These pins are

normally tied together. These inputs may be DC- or AC-

coupled. If the inputs are AC-coupled, they will self-bias

to the voltage applied to the VOCM pin.

Exposed Pad (Pin 17): Tie the pad to VEEC (Pin 12). If split

supplies are used, DO NOT tie the pad to ground.

PI FU CTIO S

UUU

–

INA

+OUT

6402 BD

VCCA

VCCB

VCCC

ENABLE

–

INB

14pF

VCCA

VEEA

VEEA 50Ω6

+OUTFILTERED

–

+INA

–OUT

+INB

VCCB

VEEB

100Ω

500Ω

50Ω

14pF

–OUTFILTERED

VEEC

VEEB

VEEA

–

VEEC

VCCC

VOCM

BIAS

BLOCK DIAGRA

LT6402-20

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APPLICATIO S I FOR ATIO

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Circuit Description

The LT6402-20 is a low noise, low distortion differential

ampliﬁ er/ADC driver with:

• –3dB bandwidth

DC to 300MHz

• Fixed gain independent of RLOAD

10V/V (20dB)

• Differential input impedance

100Ω

• Low output impedance

• Built-in, user adjustable output ﬁ ltering

• Requires minimal support circuitry

Referring to the block diagram, the LT6402-20 uses a

closed-loop topology which incorporates 3 internal am-

pliﬁ ers. Two of the ampliﬁ ers (A and B) are identical and

drive the differential outputs. The third ampliﬁ er is used

to set the output common mode voltage. Gain and input

impedance are set by the 500Ω and 100Ω resistors in

the internal feedback network. Output impedance is low,

determined by the inherent output impedance of ampliﬁ ers

A and B, and further reduced by internal feedback.

The LT6402-20 also includes built-in single-pole output

ﬁ ltering. The user has the choice of using the unﬁ ltered

outputs, the ﬁ ltered outputs (75MHz –3dB lowpass), or

modifying the ﬁ ltered outputs to alter frequency response

by adding additional components. Many lowpass and

bandpass ﬁ lters are easily implemented with just one or

two additional components.

The LT6402-20 has been designed to minimize the need

for external support components such as transformers or

AC-coupling capacitors. As an ADC driver, the LT6402-20

requires no external components except for power-supply

bypass capacitors. This allows DC-coupled operation for

applications that have frequency ranges including DC. At

the outputs, the common mode voltage is set via the VOCM

pin, allowing the LT6402-20 to drive ADCs directly. No

output AC-coupling capacitors or transformers are needed.

At the inputs, signals can be differential or single-ended

with virtually no difference in performance. Furthermore,

DC levels at the inputs can be set independently of the

output common mode voltage. These input characteristics

often eliminate the need for an input transformer and/or

AC-coupling capacitors.

Input Impedance and Matching Networks

Calculation of the input impedance of the LT6402-20 is

not straightforward from examination of the block diagram

because of the internal feedback network. In addition, the

input impedance when driven differentially is different than

when driven single-ended.

Differential Single-Ended

LT6402-20 100Ω85.9Ω

For single-ended 50Ω applications, a 121Ω shunt matching

resistor to ground will result in the proper input termina-

tion (Figure 1). For differential inputs there are several

termination options. If the input source is 50Ω differential,

then the input matching can be accomplished by either

a 100Ω shunt resistor across the inputs (Figure 3), or

equivalent 49.9Ω shunt resistors on each of the inputs

to ground (Figure 2). If additional AC gain is desired, an

impedance ratio transformer can also be used to better

match impedances.

6402 F01

IF IN

0.1µFLT6402-20

–INA

–INB –OUT

+OUT

+INB

+INA

121Ω

ZIN = 50Ω

SINGLE-ENDED

Figure 1. Input Termination for Single-Ended 50Ω

Input Impedance

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LT6402-20

APPLICATIO S I FOR ATIO

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Single-Ended to Differential Operation

The LT6402-20’s performance with single-ended inputs

is comparable to its performance with differential inputs.

This excellent single-ended performance is largely due

to the internal topology of the LT6402-20. Referring to

the block diagram, if the +INA and +INB pins are driven

with a single-ended signal (while –INA and –INB are tied

to AC ground), then the +OUT and –OUT pins are driven

differentially without any voltage swing needed from

ampliﬁ er C. Single-ended to differential conversion using

more conventional topologies suffers from performance

limitations due to the common mode ampliﬁ er.

Driving ADCs

The LT6402-20 has been speciﬁ cally designed to interface

directly with high speed Analog to Digital Converters

(ADCs). In general, these ADCs have differential inputs, with

an input impedance of 1kΩ or higher. In addition, there is

generally some form of lowpass or bandpass ﬁ ltering just

prior to the ADC to limit input noise at the ADC, thereby

improving system signal to noise ratio. Both the unﬁ ltered

and ﬁ ltered outputs of the LT6402-20 can easily drive the

high impedance inputs of these differential ADCs. If the

ﬁ ltered outputs are used, then cutoff frequency and the

type of ﬁ lter can be tailored for the speciﬁ c application if

needed.

Wideband Applications

(Using the +OUT and –OUT Pins)

In applications where the full bandwidth of the LT6402-20

is desired, the unﬁ ltered output pins (+OUT and –OUT)

should be used. They have a low output impedance;

therefore, gain is unaffected by output load. Capacitance

in excess of 5pF placed directly on the unﬁ ltered outputs

results in additional peaking and reduced performance.

When driving an ADC directly, a small series resistance

is recommended between the LT6402-20’s outputs and

the ADC inputs (Figure 4). This resistance helps eliminate

any resonances associated with bond wire inductances of

either the ADC inputs or the LT6402-20’s outputs. A value

between 10Ω and 25Ω gives excellent results.

Figure 3. Alternate Input Termination for Differential 50Ω

Input Impedance

6402 F03

IF IN–

IF IN+

LT6402-20

–INA

–INB

–OUT

+OUT

+INB

+INA

ZIN = 50Ω

DIFFERENTIAL

100Ω

6402 F04

LT6402-20

–OUT

+OUT

10Ω TO 25Ω

ADC

Figure 4. Adding Small Series R at LT6402 Output

Figure 2. Input Termination for Differential 50Ω Input Impedance

6402 F02

IF IN–

IF IN+

LT6402-20

–INA

–INB

–OUT

+OUT

+INB

+INA

49.9Ω

ZIN = 50Ω

DIFFERENTIAL

49.9Ω

LT6402-20

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APPLICATIO S I FOR ATIO

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Filtered Applications

(Using the +OUTFILTERED and –OUTFILTERED Pins)

Filtering at the output of the LT6402-20 is often desired

to provide either anti-aliasing or improved signal to noise

ratio. To simplify this ﬁ ltering, the LT6402-20 includes an

additional pair of differential outputs (+OUTFILTERED and

–OUTFILTERED) which incorporate an internal lowpass

ﬁ lter network with a –3dB bandwidth of 75MHz (Figure 5).

These pins each have an output impedance of 50Ω. Inter-

nal capacitances are 14pF to VEE on each ﬁ ltered output,

plus an additional 14pF capacitor connected differentially

between the two ﬁ ltered outputs. This resistor/capaci-

tor combination creates ﬁ ltered outputs that look like a

series 50Ω resistor with a 42pF capacitor shunting each

ﬁ ltered output to AC ground, giving a –3dB bandwidth of

75MHz.

The ﬁ lter cutoff frequency is easily modiﬁ ed with just a

few external components. To increase the cutoff frequency,

simply add 2 equal value resistors, one between +OUT and

+OUTFILTERED and the other between –OUT and –OUTFIL-

TERED (Figure 6). These resistors are in parallel with the

internal 50Ω resistor, lowering the overall resistance and

increasing ﬁ lter bandwidth. To double the ﬁ lter bandwidth,

for example, add two external 50Ω resistors to lower the

series resistance to 25Ω. The 42pF of capacitance remains

unchanged, so ﬁ lter bandwidth doubles.

To decrease ﬁ lter bandwidth, add two external capacitors,

one from +OUTFILTERED to ground, and the other from

–OUTFILTERED to ground. A single differential capacitor

connected between +OUTFILTERED and –OUTFILTERED

can also be used, but since it is being driven differentially

it will appear at each ﬁ ltered output as a single-ended

capacitance of twice the value. To halve the ﬁ lter band-

width, for example, two 42pF capacitors could be added

(one from each ﬁ ltered output to ground). Alternatively

one 21pF capacitor could be added between the ﬁ ltered

outputs, again halving the ﬁ lter bandwidth. Combinations

of capacitors could be used as well; a three capacitor

Figure 5. LT6402-20 Internal Filter Topology –3dB BW ≈75MHz

Figure 6. LT6402-20 Internal Filter Topology Modiﬁ ed

for 2x Filter Bandwidth (2 External Resistors)

Figure 7. LT6402-20 Internal Filter Topology Modiﬁ ed

for 1/2x Filter Bandwidth (3 External Capacitors)

6402 F05

50Ω

VEE

14pF

LT6402-20 –OUT

+OUT

50Ω

14pF

–OUTFILTERED

+OUTFILTERED

FILTERED OUTPUT

(75MHz)

VEE

6402 F06

50Ω

14pF

LT6402-20 –OUT

+OUT

50Ω

14pF

–OUTFILTERED

FILTERED OUTPUT

(150MHz)

+OUTFILTERED

VEE

6402 F07

50Ω

14pF

LT6402-20 –OUT

+OUT

50Ω

14pF

–OUTFILTERED

+OUTFILTERED

FILTERED OUTPUT

(37.5MHz)

Figure 8. LT6402-20 Output Filter Modiﬁ ed for Bandpass

Filtering (1 External Inductor, 1 External Capacitor)

VEE

6402 F08

50Ω

14pF

LT6402-20 –OUT

+OUT

50Ω

14pF

–OUTFILTERED

+OUTFILTERED

FILTERED OUTPUT

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LT6402-20

APPLICATIO S I FOR ATIO

WUUU

solution of 14pF from each ﬁ ltered output to ground plus

a 14pF capacitor between the ﬁ ltered outputs would also

halve the ﬁ lter bandwidth (Figure 7).

Bandpass ﬁ ltering is also easily implemented with just a

few external components. An additional 560pF and 62nH,

each added differentially between +OUTFILTERED and

–OUTFILTERED creates a bandpass ﬁ lter with a 26MHz

center frequency, –3dB points of 23MHz and 30MHz, and

1.6dB of insertion loss (Figure 8).

Output Common Mode Adjustment

The LT6402-20’s output common mode voltage is set by

the VOCM pin. It is a high-impedance input, capable of

setting the output common mode voltage anywhere in

a range from 1.1V to 3.6V. Bandwidth of the VOCM pin is

typically 200MHz, so for applications where the VOCM pin

is tied to a DC bias voltage, a 0.1µF capacitor at this pin is

recommended. For best distortion performance, the voltage

at the VOCM pin should be between 1.8V and 2.6V.

When interfacing with most ADCs, there is generally a

VOCM output pin that is at about half of the supply voltage

of the ADC. For 5V ADCs such as the LTC17XX family, this

VOCM output pin should be connected directly (with the

addition of a 0.1µF capacitor) to the input VOCM pin of the

LT6402-20. For 3V ADCs such as the LTC22XX families,

the LT6402-20 will function properly using the 1.65V from

the ADC’s VCM reference pin, but improved Spurious Free

Dynamic Range (SFDR) and distortion performance can

be achieved by level-shifting the LTC22XX’s VCM reference

voltage up to at least 1.8V. This can be accomplished as

shown in Figure 9 by using a resistor divider between the

LTC22XX’s VCM output pin and VCC and then bypassing

the LT6402-20’s VOCM pin with a 0.1µF capacitor. For a

common mode voltage above 1.9V, AC coupling capacitors

are recommended between the LT6402-20 and LTC22XX

ADCs because of the input voltage range constraints of

the ADC.

Large Output Voltage Swings

The LT6402-20 has been designed to provide the

3.2VP-P output swing needed by the LTC1748 family

of 14-bit low-noise ADCs. This additional output swing

improves system SNR by up to 4dB.

Input Bias Voltage and Bias Current

The input pins of the LT6402-20 are internally biased to

the voltage applied to the VOCM pin. No external biasing

resistors are needed, even for AC-coupled operation. The

input bias current is determined by the voltage difference

between the input common mode voltage and the VOCM

pin (which sets the output common mode voltage). For

example, if the inputs are tied to 2.5V with the VOCM pin

at 2.2V, then a total input bias current of 1mA will ﬂ ow

into the LT6402-20’s +INA and +INB pins. Furthermore,

an additional input bias current totaling 1mA will ﬂ ow into

the –INA and –INB inputs.

Application (Demo) Boards

The DC954A Demo Board has been created for stand-alone

evaluation of the LT6402-20 with either single-ended or

differential input and output signals. As shown, it accepts

a single-ended input and produces a single-ended output

so that the LT6402-20 can be evaluated using standard

laboratory test equipment. For more information on this

Demo Board, please refer to the layout and schematic

diagrams found later in this data sheet.

There are also additional demo boards available that

combine the LT6402-20 with a variety of different Linear

Technology ADCs. Please contact the factory for more

information on these demo boards.

6402 F9

IF IN

LT6402-20

–INA

–INB

VOCM

231

+INB

+INA

121Ω

10Ω

10ΩLTC22xx

0.1µF

+OUTFILTERED

–OUTFILTERED

AIN+

AIN–

4.02k

11k

1.9V

1.5V

VCM

Figure 9. Level Shifting 3V ADC VCM Voltage for

Improved SFDR

LT6402-20

640220fa

TYPICAL APPLICATIO

Top Silkscreen

640220fa

LT6402-20

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However,

no responsibility is assumed for its use. Linear Technology Corporation makes no representation that

the interconnection of its circuits as described herein will not infringe on existing patent rights.

3.00 ± 0.10

(4 SIDES)

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

1.45 ± 0.05

(4 SIDES)

NOTE:

1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WEED-2)

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

PIN 1

TOP MARK

(NOTE 6)

0.40 ± 0.10

BOTTOM VIEW—EXPOSED PAD

1.45 ± 0.10

(4-SIDES)

0.75 ± 0.05 R = 0.115

TYP

0.25 ± 0.05

PIN 1 NOTCH R = 0.20 TYP

OR 0.25 × 45° CHAMFER

15 16

0.50 BSC

0.200 REF

2.10 ± 0.05

3.50 ± 0.05

0.70 ±0.05

0.00 – 0.05

(UD16) QFN 0904

0.25 ±0.05

0.50 BSC

PACKAGE OUTLINE

UD Package

16-Lead Plastic QFN (3mm × 3mm)

(Reference LTC DWG # 05-08-1691)

PACKAGE DESCRIPTIO

LT6402-20

640220fa

LT 0706 • PRINTED IN USA

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com

PART NUMBER DESCRIPTION COMMENTS

LT1993-2 800MHz Differential Amplifier/ADC Driver AV = 2V/V, NF = 12.3dB, OIP3 = 38dBm at 70MHz

LT1993-4 900MHz Differential Ampliﬁ er/ADC Driver AV = 4V/V, NF = 14.5dB, OIP3 = 40dBm at 70MHz

LT1993-10 700MHz Differential Ampliﬁ er/ADC Driver AV = 10V/V, NF = 12.7dB, OIP3 = 40dBm at 70MHz

LT5514 Ultralow Distortion IF Ampliﬁ er/ADC Driver Digitally Controlled Gain Output IP3 47dBm at 100MHz

LT6600-5 Very Low Noise Differential Ampliﬁ er and 5MHz Lowpass Filter 82dB S/N with 3V Supply, SO-8 Package

LT6600-10 Very Low Noise Differential Ampliﬁ er and 10MHz Lowpass

Filter

82dB S/N with 3V Supply, SO-8 Package

LT6600-20 Very Low Noise Differential Ampliﬁ er and 20MHz Lowpass

Filter

76dB S/N with 3V Supply, SO-8 Package

LT6402-6 300MHz Differential Ampliﬁ er/ADC Driver AV = 6dB, en = 3.8nV/√Hz at 20MHz, 150mV

LT6402-12 300MHz Differential Ampliﬁ er/ADC Driver AV = 12dB, en = 2.6nV/√Hz at 20MHz, 150mV

LT6411 650MHz Differential ADC Driver/Dual Selectable Gain Ampliﬁ er 3300V/µs Slew Rate, 16mA Current Consumption, Selectable Gain:

AV = –1, +1, +2

TYPICAL APPLICATIO

RELATED PARTS

•

C20, 0.1µF

•

VCC

C14

4.7µF

C15

1µF

•

TEST IN

TEST OUT

VOCM

•

VCC

VCC C10

0.01µF

1000pF

6402 TA02

11 10 912

VCC

GND

SW1

23 41

[1]

R10

24.9Ω

0Ω

R18

0Ω

[1]

24.9Ω

R12

75Ω

R16

0Ω

R15

[1] +14dB

R11

75Ω

0dB

C18

0.01µF

NOTES: UNLESS OTHERWISE SPECIFIED,

[1] DO NOT STUFF.

0.1µF

1:1 Z-RATIO

M/A-COM

ETC1-1T

MINI-

CIRCUITS

TCM 4-19

MINI-

CIRCUITS

TCM 4-19

4:1 Z-RATIO

C17

1000pF

C13

0.01µF

C12

1000pF

R22

[1]

R21

[1]

0.01µF

–INA

–INB

+INB

+INA

VEEC VCCB VEEB

VOCM VCCA

VCCC VEEA

–OUTFILTERED

–OUT

+OUTFILTERED

+OUT

ENABLE

TP1

ENABLE

R14

0Ω

–OUT

+OUT

R13

[1]

49.9Ω

0Ω

–IN

+IN

[1]

0dB

R20

11k

R19

14k

R17

0Ω

VCC VCC

TP2

VCC

0.1µF

4:1

TP3

GND

LT6402-20

C21

0.1µF

1:4

C19, 0.1µF

21 21

[1]

C11

[1]

C22

0.1µF

C16

[1]

+18.8dB

+8dB

MINI-

CIRCUITS

TCM 4-19

Demo Circuit DC954A Schematic (AC Test Circuit)