A1262LLHLT-X-T - ALLEGRO MICROSYSTEMS

The A1262 is a two channel, latching Hall-effect sensor IC

that features both vertical and planar Hall elements. The

vertical and planar Hall elements feature sensing axes that are

orthogonal to one another and provide 90° of phase separation

for ring magnets that is inherently independent of magnet pole

spacing and air gap.

The 2D architecture of the A1262 simplifies the design of

motors and magnetic encoders by providing quadrature output

signals in a very small footprint. The A1262 outputs allow the

speed and direction of a rotating ring magnet to be determined.

The A1262 is available in two sensing options that allow

flexibility in end-system magnetic design. Both options

feature a planar Hall plate that is sensitive to magnetic fields

perpendicular to the face of the package (Z). Two options of

vertical Hall plate orientation (X or Y) in both packages offer

flexibility in system design and magnet to sensor placement.

A1262-DS, Rev. 5

MCO-0000158

• 2D magnetic sensing via planar and vertical Hall elements

□Quadrature outputs

□90° phase separation between channels

• Dual-channel output allows independent use of

Z-axis planar Hall in conjunction with vertical Hall:

□Y-axis (default option)

□X-axis (with -X option)

• High sensitivity, BOP typically 17 G

• Automotive grade

□AEC-Q100 qualified for use in automotive

applications (L temperature range option)

□Output short-circuit protection

□Resistant to physical stress

□Reverse-battery protection

□Superior temperature stability

□Supply voltage Zener clamp

• Small size

2D, Dual-Channel, Ultrasensitive Hall-Effect Latch

PACKAGES:

Functional Block Diagram

Not to scale

A1262

X/Y Hall

Z Hall

Amp

Dynamic Offset

Cancellation &

Multiplexer

Demultiplexer

Low-Pass

Filter

To All

Subcircuits

Sample, Hold

&Averaging

Regulator

Current

Limit

Current

Limit

OUTPUTA

VDD

GND

OUTPUTB

FEATURES AND BENEFITS DESCRIPTION

5-Pin SOT23W

(Sux LH)

Continued on the next page…

4-Pin SIP

(Sux K)

August 8, 2018

• Automotive

□Blower fans

□Electric pumps

□Electronic power

steering

□Seat motors

□Trunk/liftgate motors

□Window/sunroof

motors

• Industrial, Commercial,

and Consumer

□Garage doors

□Industrial motors

□Motorized window

blinds

□Motorized gates

□Pumps

□White goods

TYPICAL APPLICATIONS

2D, Dual-Channel, Ultrasensitive Hall-Effect Latch

A1262

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

DESCRIPTION (continued)

On a single silicon chip, the A1262 includes: voltage regulator, reverse

battery protection, two Hall plates (one planar and one vertical), a

multiplexer, a small-signal amplifier, chopper stabilization, a Schmitt

trigger, and two short-circuit protected open-drain outputs that can

sink up to 20 mA continuously.

The A1262 is available in two temperature ranges: –40°C to 85°C

(E temperature range option) or –40°C to 150°C (L temperature

range option).

The A1262 is available in a 5-pin SOT23W surface-mount package

(LH) and a 4 pin SIP package (K). Each is offered in two options for

a variety of magnet to sensor orientations. The packages are RoHS

compliant and lead (Pb) free, with 100% matte-tin leadframe plating.

Terminal List Table

Number Symbol Description

K LH

1 1 VDD Connects power supply to chip

2 2 OUTPUTA Output of Z magnetic field direction [1]

3 3 OUTPUTB Default option: Output of Y magnetic field direction

With -X option: Output of X magnetic field direction

4 4 GND Ground

– 5 GND Ground

[1] Z-axis recommended for use as the speed channel in a speed and direction application, due to better

repeatability.

1VDD

OUTPUTA OUTPUTB

GND

Package LH, 5-Pin SOT23W Pinout

RoHS

COMPLIANT

2 3 41

VCC

OUTPUTA

OUTPUTB

GND

Package K, 4-Pin SIP Pinout

ΔZ

ΔY

XΔ

ΔY

SELECTION GUIDE

Part Number Packing Package Temperature Range, TA (°C) Description

A1262ELHLT-T 7-in. reel, 3000 pieces/reel 5-pin SOT-23W surface mount –40 to 85

2 Outputs of Y and Z

A1262ELHLX-T 13-in. reel, 10000 pieces/reel 5-pin SOT-23W surface mount

A1262LK-Y-T Bulk bag, 500 pieces/bag 4-pin SIP through-hole

–40 to 150A1262LLHLT-T 7-in. reel, 3000 pieces/reel 5-pin SOT-23W surface mount

A1262LLHLX-T 13-in. reel, 10000 pieces/reel 5-pin SOT-23W surface mount

A1262ELHLT-X-T 7-in. reel, 3000 pieces/reel 5-pin SOT-23W surface mount –40 to 85

2 Outputs of X and Z

A1262ELHLX-X-T 13-in. reel, 10000 pieces/reel 5-pin SOT-23W surface mount

A1262LK-X-T Bulk bag, 500 pieces/bag 4-pin SIP through-hole

–40 to 150A1262LLHLT-X-T 7-in. reel, 3000 pieces/reel 5-pin SOT-23W surface mount

A1262LLHLX-X-T 13-in. reel, 10000 pieces/reel 5-pin SOT-23W surface mount

2D, Dual-Channel, Ultrasensitive Hall-Effect Latch

A1262

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

ABSOLUTE MAXIMUM RATINGS

Characteristic Symbol Notes Rating Unit

Forward Supply Voltage VDD 26.5 V

Reverse Supply Voltage VRDD –16 V

Magnetic Flux Density B Unlimited G

Output Off Voltage VOUT 26.5 V

Output Sink Current IOUT(SINK) Internally Limited mA

Maximum Junction Temperature TJ(MAX)

165 °C

For 500 hours 175 °C

Storage Temperature Tstg –65 to 170 °C

THERMAL CHARACTERISTICS: May require derating at maximum conditions; see application information

Characteristic Symbol Notes Rating Unit

Package Thermal Resistance RθJA

Package K, single-sided PCB with copper limited to solder pads 177 °C/W

Package LH-5 4-layer board based on the JEDEC standard 124 °C/W

* Additional thermal information available on the Allegro website.

Maximum Power Dissipation versus Ambient Temperature

20 40 60 80 100 120 140 160

180

Temperature (°C)

Power Dissipation, P

(mW)

100

200

300

400

500

600

700

800

900

1000

1100

1200

1300

1400

1500

1600

1700

1800

1900

4-Layer PCB, Package LH-5

θJA

=124ºC/W)

Single-Sided PCB, Package K

θJA

=177ºC/W)

2D, Dual-Channel, Ultrasensitive Hall-Effect Latch

A1262

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

ELECTRICAL CHARACTERISTICS: Valid over full operating voltage and TA = –40°C to 85°C (Range E) or TA = –40°C to 150°C (Range L),

unless otherwise specied.

Characteristics Symbol Test Conditions Min. Typ. [1] Max. Unit

Forward Supply Voltage VDD Operating, TJ < 165°C 4 – 24 V

Output Leakage Current IOUTOFF B < BRP – – 10 µA

Output On Voltage VOUT(SAT) IOUT = 20 mA, B > BOP – 180 500 mV

Supply Current IDD 2 3 4.5 mA

Reverse-Battery Current IRDD VRDD = –16 V – – –5 mA

Supply Zener Clamp Voltage VZICC = 5 mA; TA = 25°C 28 34 – V

Output Current IOUT – – 20 mA

Output Short-Circuit Current Limit IOUT(SINK)LIM TJ < TJ(max), VOUT = 12 V 30 – 60 mA

Output Sink Current, Peak IOUT(SINK)PK t < 3 seconds – – 110 mA

Chopping Frequency fC– 800 – kHz

Output Rise Time [2][3] trRL = 820 Ω, CS = 20 pF – 0.2 – µs

Output Fall Time [2][3] tfRL = 820 Ω, CS = 20 pF – 0.1 – µs

Power-On Time [2] tON Both channels, VDD > VDD(MIN) – 32 48 µs

Power-On State POS VDD > VDD(MIN), t< tON Low –

[1] Typical data are at TA = 25°C and VDD = 4 V.

[2] Power-on time, rise time, and fall time are guaranteed through device characterization.

[3] CS = oscilloscope probe capacitance.

2D, Dual-Channel, Ultrasensitive Hall-Effect Latch

A1262

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

MAGNETIC CHARACTERISTICS: Valid over full operating voltage and TA = –40°C to 85°C (Range E) or TA = –40°C to 150°C (Range L),

unless otherwise specied.

Characteristics Symbol Test Conditions Min. Typ. Max. Unit [4]

Operate Point [5] BOP 1 17 40 G

Release Point [5] BRP –40 –17 –1 G

Hysteresis BHYS BOP – BRP 15 34 68 G

Symmetry: Channel A, Channel B,

BOP(A) + BRP(A), BOP(B) + BRP(B)

BSYM(A),

BSYM(B)

–35 – 35 G

Operate Symmetry: BOP(A) – BOP(B) BSYM(AB,OP) –25 – 25 G

Release Symmetry: BRP(A) – BRP(B) BSYM(AB,RP) –25 – 25 G

[4] 1 G (gauss) = 0.1 mT (millitesla)

[5] Applicable to all directions (X/Y and Z).

The A1262 output is turned on when presented with a south polarity magnetic eld beyond BOP in the orientations illustrated above.

The X-axis eld response is only applicable to the -X option; the Y-axis eld response is only applicable to the default option. Note that

magnetic polarity between the LH and K X-axis options are opposite.

2D, Dual-Channel, Ultrasensitive Hall-Effect Latch

A1262

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

CHARACTERISTIC DATA

-60 -40 -20 0 20 40 60 80 100 120 140 160

Supply Current, IDD (mA)

Ambient Temperature, TA(°C)

Average Supply Current vs. Ambient Temperature

4 V

24 V

2 6 10 14 18 22 26

Supply Current, IDD (mA)

Supply Voltage, VDD (V)

Average Supply Current vs. Supply Voltage

-40°C

25°C

150°C

100

150

200

250

300

350

400

450

500

-60 -40 -20 0 20 40 60 80 100 120 140 160

Output On Voltage, VOUT(SAT) (mV)

Ambient Temperature, TA(°C)

Avg. Output On Voltage vs. Ambient Temperature

VOUT(SAT)-A

VOUT(SAT)-B

-60 -40 -20 0 20 40 60 80 100 120 140 160

Output Leakage Current, IOUTOFF (µA)

Ambient Temperature, TA(°C)

Avg. Output Leakage Current vs. Ambient

Temperature

IOUT(OFF)-A

IOUT(OFF)-B

-60 -40 -20 0 20 40 60 80 100 120 140 160

Operate Point, BOP (G)

Ambient Temperature, TA(°C)

Avg. OUTPUTA Operate Point vs. Ambient

Temperature

4 V

24 V

2 6 10 14 18 22 2

Operate Point, BOP (G)

Supply Voltage, VDD (V)

Avg. OUTPUTA Operate Point vs. Supply Voltage

-40°C

25°C

150°C

2D, Dual-Channel, Ultrasensitive Hall-Effect Latch

A1262

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

CHARACTERISTIC DATA (continued)

-60 -40 -20 0 20 40 60 80 100 120 140 160

Operate Point, BOP (G)

Ambient Temperature, TA(°C)

Avg. OUTPUTB Operate Point vs. Ambient

Temperature

4 V

24 V

2 6 10 14 18 22 26

Operate Point, BOP (G)

Supply Voltage, VDD (V)

Avg. OUTPUTB Operate Point vs. Supply Voltage

-40°C

25°C

150°C

-40

-35

-30

-25

-20

-15

-10

-5

-60 -40 -20 0 20 40 60 80 100 120 140 160

Release Point, BRP (G)

Ambient Temperature, TA(°C)

Avg. OUTPUTA Release Point vs. Ambient

Temperature

4 V

24 V

-40

-35

-30

-25

-20

-15

-10

-5

2 6 10 14 18 22 26

Release Point, BRP (G)

Supply Voltage, VDD (V)

Avg. OUTPUTA Release Point vs. Supply Voltage

-40°C

25°C

150°C

-40

-35

-30

-25

-20

-15

-10

-5

-60 -40 -20 0 20 40 60 80 100 120 140 160

Release Point, BRP (G)

Ambient Temperature, TA(°C)

Avg. OUTPUTB Release Point vs. Ambient

Temperature

4 V

24 V

-40

-35

-30

-25

-20

-15

-10

-5

2 6 10 14 18 22 26

Release Point, BRP (G)

Supply Voltage, VDD (V)

Avg. OUTPUTB Release Point vs. Supply Voltage

-40°C

25°C

150°C

2D, Dual-Channel, Ultrasensitive Hall-Effect Latch

A1262

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

CHARACTERISTIC DATA (continued)

-60 -40 -20 0 20 40 60 80 100 120 140 160

Hysteresis, BHYS (G)

Ambient Temperature, TA(°C)

Avg. OUTPUTA Hysteresis vs. Ambient

Temperature

4 V

24 V

2 6 10 14 18 22 26

Hysteresis, BHYS (G)

Supply Voltage, VDD (V)

Avg. OUTPUTA Hysteresis vs. Supply Voltage

-40°C

25°C

150°C

-60 -40 -20 0 20 40 60 80 100 120 140 160

Hysteresis, BHYS (G)

Ambient Temperature, TA(°C)

Avg. OUTPUTB Hysteresis vs. Ambient

Temperature

4 V

24 V

2 6 10 14 18 22 26

Hysteresis, BHYS (G)

Supply Voltage, VDD (V)

Avg. OUTPUTB Hysteresis vs. Supply Voltage

-40°C

25°C

150°C

-15

-10

-5

-60 -40 -20 0 20 40 60 80 100 120 140 160

Symmetry, BSYM(A) (G)

Ambient Temperature, TA(°C)

Avg. BOP(A)+BRP(A) Symmetry vs. Ambient

Temperature

4 V

24 V

-15

-10

-5

-60 -40 -20 0 20 40 60 80 100 120 140 160

Symmetry, BSYM(B) (G)

Ambient Temperature, TA(°C)

Avg. BOP(B)+BRP(B) Symmetry vs. Ambient

Temperature

4 V

24 V

2D, Dual-Channel, Ultrasensitive Hall-Effect Latch

A1262

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

CHARACTERISTIC DATA (continued)

-15

-10

-5

-60 -40 -20 0 20 40 60 80 100 120 140 160

Symmetry, BSYM(AB,OP) (G)

Ambient Temperature, TA(°C)

Avg. BOP(A)–BOP(B) Symmetry vs. Ambient

Temperature

4 V

24 V

-15

-10

-5

-60 -40 -20 0 20 40 60 80 100 120 140 160

Symmetry, BSYM(AB,RP) (G)

Ambient Temperature, TA(°C)

Avg. BRP(A)–BRP(B) Symmetry vs. Ambient

Temperature

4 V

24 V

2D, Dual-Channel, Ultrasensitive Hall-Effect Latch

A1262

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

FUNCTIONAL DESCRIPTION

Operation

The outputs of the A1262 switch low (turn on) when the cor-

responding Hall element is presented with a perpendicular south

magnetic field of sufficient strength. OUTPUTA switches low if

the Z-axis direction exceeds the operate point (BOP), and OUT-

PUTB switches low if the Y-axis direction (A1262 with default

option) or X-axis direction (A1262 with -X option) exceeds BOP.

After turn-on, the output voltage is VOUT(SAT). The device outputs

switch high (turn off) when the strength of a perpendicular north

magnetic field exceeds the release point (BRP). The difference in

the magnetic operate and release points is the hysteresis (BHYS)

of the device. See Figure 1.

Removal of the magnetic field will leave the device output

latched on if the last crossed switchpoint is BOP, or latched off if

the last crossed switchpoint is BRP.

This built-in hysteresis allows clean switching of the output even

in the presence of external mechanical vibration and electrical

noise. The device will power-on in the low output state, even

when powering-on in the hysteresis region, between BOP and BRP.

Unlike dual-planar Hall-effect sensors, which have two planar

Hall-effect sensing elements spaced apart across the width of the

package, both the vertical and planar sensing elements on the

A1262 are located in essentially the same location on the IC.

V+ VOUT(OFF)

Switch to Low

Switch to High

VOUT(ON)

OUTPUT

B- 0B+

BOP

BHYS

Figure 1: Switching Behavior of Latches

On the horizontal axis, the B+ direction indicates increasing

south polarity magnetic field strength, and the B– direction

indicates decreasing south polarity field strength (including

the case of increasing north polarity

With dual-planar Hall sensors, the ring magnet must be properly

designed and optimized for the physical Hall spacing (distance)

in order to have the outputs of the two latches to be in quadra-

ture, or 90 degrees out of phase. With the A1262, which uses one

planar and one vertical Hall-effect sensing element, no target

optimization is required. When the face of the IC is facing the

ring magnet, the planar Hall senses the magnet poles and the

vertical Hall senses the transition between poles, therefore the

Figure 2: Ring magnet optimized for a dual-planar Hall-e󰀨ect sensor resulting in output

quadrature also results in quadrature for the A1262.

Dual-Planar

Sensor

A1262

dual

planar

2D, Dual-Channel, Ultrasensitive Hall-Effect Latch

A1262

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

two channels will inherently be in quadrature, irrespective of the

ring-magnet pole spacing.

Figure 2 above shows a ring magnet optimized for the E1-to-E2

spacing of a dual-planar sensor, resulting in quadrature, or 90

degrees phase separation between channels. This same target

also results in quadrature for the 2D sensing A1262. However

when a different ring magnet is used which is not optimized for

Figure 3: Ring magnet not optimized for a dual-planar Hall-e󰀨ect sensor resulting in signi-

cantly reduced output phase separation, however still results in quadrature for the A1262.

the E1-to-E2 spacing, the dual-planar sensor exhibits diminished

phase separation, making signal processing the outputs into speed

and direction less robust. Using a different ring-magnet geom-

etry has no effect on the A1262, and the two channels remain in

quadrature (see Figure 3 below).

The relationship of the various signals and the typical system tim-

ing is shown in Figure 4.

Figure 4: Typical System Timing

The Planar (P) and Vertical (V) signals represent the magnetic input signal, which is converted to the device outputs,

OUTPUTA and OUTPUTB, respectively. While the A1262 does not process the signals into Speed and Direction, these

could be determined by the user based on the individual output signals.

Dual-Planar

Sensor

A1262

A1262dual

planar

2D, Dual-Channel, Ultrasensitive Hall-Effect Latch

A1262

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Figure 5: Typical System Timing

Clockwise Rotation Counterclockwise Rotation

VerticalPlanar

Bx Time

(s)

Time

(s)

Time

(s)

Output Response to a

Speed and Direction Part

A1262

The two active Hall signals represent the magnetic input signal,

which is converted to the device outputs, OUTPUTA and

OUTPUTB.

2D, Dual-Channel, Ultrasensitive Hall-Effect Latch

A1262

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Figure 6: Output signal updating with respect to the channel sampling

The two active channels are multiplexed with a typical 16 µs

sampling period per channel. If the magnetic signal crosses the

respective BOP or BRP of a particular channel, that channel’s

output will not be updated until the end of its sampling period.

If the signal crosses the thresholds while the alternate channel is

sampling, the update will occur at the end of the next sampling

period (as long as the signal does not cross back over the

thresholds). This is illustrated in Figure 6. The sampling error

introduced by the multiplexing increases with magnetic input

frequency, which can affect the output duty cycle and phase

separation between outputs. Contact your Allegro representative

for more information regarding suitability to high frequency

applications.

Sampling

Cycle

BOP(A)

BRP(A)

BOP(B)

BRP(B)

Signal OUTPUTA

Signal OUTPUTB

Channel A Channel A Channel B Channel A Channel B Channel AChannel B Channel B Channel A Channel B

Signal

OUTPUTA

BOP(A)

BRP(A)

Sampling

Cycle

Signal

OUTPUTA

Sampling

Cycle

BOP(A)

BRP(A)

Channel A Channel B Channel AChannel B Channel B Channel A Channel B Channel A

2D, Dual-Channel, Ultrasensitive Hall-Effect Latch

A1262

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

A1262 Sensor and Relationship to Target

The A1262 is available in two sensing options: with Z-axis planar

Hall and the Y-axis vertical Hall active (default option), or with

the Z-axis planar Hall and the X-axis vertical Hall active (-X

option). This offers incredible flexibility for positioning the IC

within various applications.

The Z-Y option supports the traditional configuration with the

face of the package facing the ring magnet (Figure 7a or 7c), with

the axis of rotation going cross the leads, or opposide the leaded

side(s) of the package facing the ring magnet (Figure 7b or 7d).

Figure 7a: LH (-Y option) Figure 7b: LH (-Y option)

Figure 7c: K (-Y option)

Figure 7d: K (-Y option)

2D, Dual-Channel, Ultrasensitive Hall-Effect Latch

A1262

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

The Z-X option supports having the IC positioned with the face

of the package facing the ring magnet, and the axis of rotation

(Figure 8a or 8c) lengthwise along the package body, or with

either of the non-leaded sides of the package facing the ring mag-

net (Figure 8b or 8d). This latter configuration has the advantage

of being able to be mounted extremely close to the ring magnet,

since there are no leads or solder pads to accommodate for in that

dimension.

Figure 8a: LH (-X option) Figure 8b: LH (-X option)

Figure 8c: K (-X option) Figure 8d: K (-X option)

2D, Dual-Channel, Ultrasensitive Hall-Effect Latch

A1262

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Applications

It is strongly recommended that an external capacitor be con-

nected (in close proximity to the Hall sensor) between the supply

and ground of the device to reduce both external noise and noise

generated by the chopper stabilization technique. As shown in

Figure 10, a 0.1 µF capacitor is typical.

Extensive applications information on magnets and Hall-effect

sensors is available in:

• Hall-Effect IC Applications Guide, AN27701,

• Hall-Effect Devices: Guidelines for Designing Subassemblies

Using Hall-Effect Devices, AN27703.1

• Soldering Methods for Allegro’s Products – SMD and

Through-Hole, AN26009

• Air-Gap-Independent Speed and Direction Sensing Using the

Allegro A1262, AN296124

• Improved Speed and Direction Sensing Using Vertical Hall

Technology, AN296130

All are provided on the Allegro website:

www.allegromicro.com

CBYP

0.1 µF

VDD

GND

RLOAD RLOAD

Sensor

Output

A1262

OUTPUTA

OUTPUTB

Power-On Sequence and Timing

The states of OUTPUTA and OUTPUT B are only valid when the

supply voltage is within the specified operating range (VDD(MIN)

≤ VDD ≤ VDD(MAX)) and the power-on time has elapsed (t > tON).

Refer to Figure 9: Power-On Sequence and Timing for an illustra-

tion of the power-on sequence.

time

OUT(OFF)

DD(MIN)

Output Undefined for

< V

DD(MIN)

OUT(ON)

POS

time

OUT(OFF)

Output Undefined for

< V

DD(MIN)

OUT(ON)

POS

Planar

(Z)

Vertical

(X/Y)

Output Responds According

to Magnetic Field Input

B > B

or B < B

t > t

ON(MAX)

Output Responds According

to Magnetic Field Input

B > B

or B < B

t > t

ON(MAX)

Figure 9: Power-On Sequence and Timing

Once the supply voltage is within the operational range, the

outputs will be in the low state (power-on state), irrespective of

the magnetic field. The outputs will remain low until the sensor

is fully powered on (t > tON), at which point, both outputs will

respond to the corresponding magnetic field presented to the sen-

sor (the vertical Hall channel typically responds before the planar

Hall channel).

Figure 10: Typical Application Circuit

2D, Dual-Channel, Ultrasensitive Hall-Effect Latch

A1262

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

When using Hall-effect technology, a limiting factor for switch-

point accuracy is the small signal voltage developed across the

Hall element. This voltage is disproportionally small relative to

the offset that can be produced at the output of the Hall sensor.

This makes it difficult to process the signal while maintaining an

accurate, reliable output over the specified operating temperature

and voltage ranges.

Chopper stabilization is a proven approach used to minimize

Hall offset on the chip. The Allegro technique, namely Dynamic

Quadrature Offset Cancellation, removes key sources of output

drift induced by thermal and mechanical stresses. This technique

is based on a signal modulation-demodulation process. The

undesired offset signal is separated from the magnetic field-

induced signal in the frequency domain, through modulation.

The subsequent demodulation acts as a modulation process for

the offset, causing the magnetic field induced signal to recover

its original spectrum at baseband, while the DC offset becomes a

Chopper Stabilization Technique

Amp.

Multiplexer

Low-Pass

Filter

Sample, Hold &

Averaging

VDD

Figure 11: Model of Chopper Stabilization Technique

high-frequency signal. The magnetic sourced signal then can pass

through a low-pass filter, while the modulated DC offset is sup-

pressed. This configuration is illustrated in Figure 11.

The chopper stabilization technique uses a 400 kHz high-

frequency clock. For demodulation process, a sample, hold, and

averaging technique is used, where the sampling is performed

at twice the chopper frequency (800 kHz). This high-frequency

operation allows a greater sampling rate, which results in higher

accuracy and faster signal-processing capability. This approach

desensitizes the chip to the effects of thermal and mechani-

cal stresses, and produces devices that have extremely stable

quiescent Hall output voltages and precise recoverability after

temperature cycling. This technique is made possible through the

use of a BiCMOS process, which allows the use of low-offset,

low-noise amplifiers in combination with high-density logic and

sample-and-hold circuits.

2D, Dual-Channel, Ultrasensitive Hall-Effect Latch

A1262

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

POWER DERATING

The device must be operated below the maximum junction

temperature of the device, TJ(max). Under certain combinations of

peak conditions, reliable operation may require derating supplied

power or improving the heat dissipation properties of the appli-

cation. This section presents a procedure for correlating factors

affecting operating TJ. (Thermal data is also available on the

Allegro MicroSystems website.)

The Package Thermal Resistance (RθJA) is a figure of merit sum-

marizing the ability of the application and the device to dissipate

heat from the junction (die), through all paths to the ambient air.

Its primary component is the Effective Thermal Conductivity (K)

of the printed circuit board, including adjacent devices and traces.

Radiation from the die through the device case (RθJC) is relatively

small component of RθJA. Ambient air temperature (TA) and air

motion are significant external factors, damped by overmolding.

The effect of varying power levels (Power Dissipation, PD), can

be estimated. The following formulas represent the fundamental

relationships used to estimate TJ at PD.

PD = VIN × IIN (1)

  ∆T=PD × RθJA (2)

TJ = TA+∆T (3)

For example, given common conditions such as: TA = 25°C,

VDD = 12 V, IDD = 3 mA, and RθJA = 124°C/W for the LH5 pack-

age, then:

PD = VDD × IDD = 12 V × 3.0 mA = 36.0 mW

∆T=PD × RθJA = 36.0 mW × 124°C/W = 4.5°C

TJ = TA+∆T=25°C+4.5°C=29.5°C

A worst-case estimate (PD(max)) represents the maximum allow-

able power level (VDD(max), IDD(max)), without exceeding TJ(max),

at a selected RθJA and TA.

Example: Reliability for VDD at TA = 150°C, package LH5, using

low-K PCB.

Observe the worst-case ratings for the device, specifically:

RθJA = 124°C/W, TJ(max) = 165°C, VDD(max) = 24 V, and

IDD(max) = 7.5 mA.

Calculate the maximum allowable power level (PD(max)). First,

invert equation 3:

∆Tmax = TJ(max) – TA = 165°C – 150°C = 15°C

This provides the allowable increase to TJ resulting from internal

power dissipation. Then, invert equation 2:

PD(max)=∆Tmax ÷ RθJA = 15°C ÷ 124°C/W = 121 mW

Finally, invert equation 1 with respect to voltage:

VDD(est) = PD(max) ÷ IDD(max)

VDD(est) = 121 mW ÷ 7.5 mA

VDD(est) = 16.1 V

The result indicates that, at TA, the application and device can

dissipate adequate amounts of heat at voltages ≤ VDD(est).

Compare VDD(est) to VDD(max). If VDD(est) ≤ VDD(max), then reli-

able operation between VDD(est) and VDD(max) requires enhanced

RθJA. If VDD(est) ≥ VDD(max), then operation between VDD(est) and

VDD(max) is reliable under these conditions.

2D, Dual-Channel, Ultrasensitive Hall-Effect Latch

A1262

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

PACKAGE OUTLINE DRAWINGS

Figure 12: Package K, 4-Pin SIP

2 431

E3 E2

0.84 REF

1.27 NOM

2.16

MAX

45°

DActive Area Depth, 0.42 mm

Hall Elements (E1, E2, and E3), not to scale;

E2 and E3 are active in the A1262LK-T;

E1 and E3 are active in the A1262LK-X-T

EE2 E

E2 E

Gate and tie bar burr area

Dambar removal protrusion (8×)

For Reference Only; not for tooling use (reference DWG-9010)

Dimensions in millimeters

Dimensions exclusive of mold flash, gate burrs, and dambar protrusions

Exact case and lead configuration at supplier discretion within limits shown

Standard Branding Reference View

N = Device part number

Y = Last two digits of year of manufacture

W = Week of manufacture

Mold Ejector

Pin Indent

Branded

Face

YYWW

NNNN

5.21 +0.08

–0.05

0.38 +0.06

–0.03

3.43 +0.08

–0.05

0.41 +0.07

–0.05

14.73 ±0.51

1.55 ±0.05

1.32

2.60

0.17

0.11

Branding scale and appearance at supplier discretion

2D, Dual-Channel, Ultrasensitive Hall-Effect Latch

A1262

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

For Reference Only – Not for Tooling Use

(Reference DWG-9069)

Dimensions in millimeters – NOT TO SCALE

Dimensions exclusive of mold ﬂash, gate burrs, and dambar protrusions

Exact case and lead conﬁguration at supplier discretion within limits shown

0.20 MIN

2.40

0.70 0.95

1.00

PCB Reference Layout View

Standard Branding Reference View

NNN

Reference land pattern layout; all pads a minimum of 0.20 mm from all adjacent pads;

adjust as necessary to meet application process requirements and PCB layout tolerances

Branding Scale and appearance at supplier discretion

Hall Elements (D1, D2, and D3), not to scale; D2 and D3 are active in the A1262LLH-T;

D1 and D3 are active in the A1262LLH-X-T

D3 D2

SEATING PLANE

GAUGE PLANE

0.55

REF 0.25 BSC

0.95

BSC

Branded Face

2.90

0.17

REF

0.11

REF

+0.10

–0.20

4° ±4°

8X 12°

REF

0.180+0.020

–0.053

0.05+0.10

–0.05

0.25 MIN

1.91+0.19

–0.06

2.98+0.12

–0.08

1.00 ±0.13

0.40 ±0.10

AXActive Area Depth, X Axis, 1.49 ±0.2

AYActive Area Depth, Y Axis, 1.45 ±0.15

AZActive Area Depth, Z Axis, 0.28 ±0.04

Figure 13: Package LH, 5-Pin SOT23-W

2D, Dual-Channel, Ultrasensitive Hall-Effect Latch

A1262

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

For the latest version of this document, visit our website:

www.allegromicro.com

Revision History

Number Date Description

– September 21, 2015 Initial release

1 February 10, 2016 Added E temperature range option and magnetic switchpoint symmetry specifications

2 February 10, 2017

Updated Features and Benefits (page 1), Description (pages 1-2), Absolute Maximum Ratings table

(page 3), Electrical Characteristics table (page 4), Figure 5 (page 12), Figure 6 (page 13), Figure

7 and 8 labels (pages 14-15), Chopper Stabilization section (page 17); added Typical Applications;

added K package option; expanded Functional Description section.

3 May 19, 2017 Corrected Pinout Diagrams (page 2).

4 July 31, 2017 Updated Selection Guide table (page 2).

5 August 8, 2018 Minor editorial updates.

Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to

permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that

the information being relied upon is current.

Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of

Allegro’s product can reasonably be expected to cause bodily harm.

The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its

use; nor for any infringement of patents or other rights of third parties which may result from its use.

Copies of this document are considered uncontrolled documents.