ADC121S655CIMMX/NOPB - National Semiconductor

May 2007

ADC121S655

12-Bit, 200 kSPS to 500 kSPS, Differential Input, Micro

Power A/D Converter

General Description

The ADC121S655 is a 12-bit, 200 kSPS to 500 kSPS sam-

pling Analog-to-Digital (A/D) converter that features a fully

differential, high impedance analog input and an external ref-

erence. The reference voltage can be varied from 1.0V to

VA, with a corresponding resolution between 244µV and VA

divided by 4096.

The output serial data is binary 2's complement and is com-

patible with several standards, such as SPI™, QSPI™, MI-

CROWIRE™, and many common DSP serial interfaces. The

differential input, low power consumption, and small size

make the ADC121S655 ideal for direct connection to trans-

ducers in battery operated systems or remote data acquisition

applications.

Operating from a single 5V supply, the supply current when

operating at 500 kSPS is typically 1.8 mA. The supply current

drops down to 0.3 µA typically when the ADC121S655 enters

power-down mode. The ADC121S655 is available in the

MSOP-8 package. Operation is guaranteed over the indus-

trial temperature range of −40°C to +105°C and clock rates

of 3.2 MHz to 8 MHz.

Features

■True Differential Inputs

■Guaranteed performance from 200 kSPS to 500 kSPS

■External Reference

■Wide Input Common-Mode Voltage Range

■SPI™/QSPI™/MICROWIRE™/DSP compatible Serial

Interface

Key Specifications

■Conversion Rate 200 kSPS to 500 kSPS

■INL ± 0.95 LSB (max)

■DNL ± 0.85 LSB (max)

■Offset Error ± 3.0 LSB (max)

■Gain Error ± 5.5 LSB (max)

■SINAD 70 dB (min)

■Power Consumption at VA = 5V

■— Active, 500 kSPS 9 mW (typ)

— Active, 200 kSPS 7 mW (typ)

— Power-Down 1.5 µW (typ)

Applications

■Automotive Navigation

■Portable Systems

■Medical Instruments

■Instrumentation and Control Systems

■Motor Control

■Direct Sensor Interface

Pin-Compatible Alternatives by Speed

All devices are pin compatible.

Resolution Specified for Sample Rate Range of:

50 to 200 ksps 200 to 500 ksps 500 ksps to 1 Msps

12-bit ADC121S625 ADC121S655 ADC121S705

Connection Diagram

30010505

TRI-STATE® is a trademark of National Semiconductor Corporation.

MICROWIRE™ is a trademark of National Semiconductor Corporation.

QSPI™ and SPI™ are trademarks of Motorola, Inc.

ADC121S655 12-Bit, 200 kSPS to 500 kSPS, Differential Input, Micro Power A/D Converter

Ordering Information

Order Code Temperature Range Description Top Mark

ADC121S655CIMM −40°C to +105°C 8-Lead MSOP Package, 1000 Units Tape & Reel X2AC

ADC121S655CIMMX −40°C to +105°C 8-Lead MSOP Package, 3500 Units Tape & Reel X2AC

ADC121S705EB Evaluation Board

Block Diagram

30010502

Pin Descriptions and Equivalent Circuits

Pin No. Symbol Description

1VREF

Voltage Reference Input. A voltage reference between 1V and VA must be applied to this

input. VREF must be decoupled to GND with a minimum ceramic capacitor value of 1 µF.

A bulk capacitor value of 10 µF in parallel with the 1 µF is recommended for enhanced

performance.

2 +IN Non-Inverting Input. +IN is the positive analog input for the differential signal applied to

the ADC121S655.

3 −IN Inverting Input. −IN is the negative analog input for the differential signal applied to the

ADC121S655.

4 GND Ground. GND is the ground reference point for all signals applied to the ADC121S655.

5 CS Chip Select Bar. CS is active low. The ADC121S655 is in Normal Mode when CS is LOW

and Power-Down Mode when CS is HIGH. A conversion begins on the fall of CS.

6DOUT

Serial Data Output. The conversion result is provided on DOUT. The serial data output

word is comprised of 4 null bits and 12 data bits (MSB first). During a conversion, the data

is output on the falling edges of SCLK and is valid on the rising edges.

7 SCLK Serial Clock. SCLK is used to control data transfer and serves as the conversion clock.

8VA

Power Supply input. A voltage source between 4.5V and 5.5V must be applied to this

input. VA must be decoupled to GND with a ceramic capacitor value of 1 µF in parallel

with a bulk capacitor value of 10 µF.

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ADC121S655

Absolute Maximum Ratings (Notes 1, 2)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Analog Supply Voltage VA−0.3V to 6.5V

Voltage on Any Pin to GND −0.3V to (VA +0.3V)

Input Current at Any Pin (Note 3) ±10 mA

Package Input Current (Note 3) ±50 mA

Power Consumption at TA = 25°C See (Note 4)

ESD Susceptibility (Note 5)

Human Body Model

Machine Model

Charge Device Model

2500V

250V

750V

Junction Temperature +150°C

Storage Temperature −65°C to +150°C

Operating Ratings (Notes 1, 2)

Operating Temperature Range −40°C ≤ TA ≤ +105°C

Supply Voltage, VA+4.5V to +5.5V

Reference Voltage, VREF 1.0V to VA

Input Common-Mode Voltage, VCM See Figure 8 (Sect 2.3)

Digital Input Pins Voltage Range 0 to VA

Clock Frequency 3.2 MHz to 8 MHz

Differential Analog Input Voltage −VREF to +VREF

Package Thermal Resistance

Package θJA

8-lead MSOP 200°C / W

Soldering process must comply with National

Semiconductor's Reflow Temperature Profile specifications.

Refer to www.national.com/packaging. (Note 6)

ADC121S655 Converter Electrical Characteristics (Note 8)

The following specifications apply for VA = +4.5V to 5.5V, VREF = 2.5V, fSCLK = 3.2 to 8 MHz, fIN = 100 kHz, CL = 25 pF, unless

otherwise noted. Boldface limits apply for TA = TMIN to TMAX; all other limits are at TA = 25°C.

Symbol Parameter Conditions Typical Limits Units

(Note 7)

STATIC CONVERTER CHARACTERISTICS

Resolution with No Missing Codes 12 Bits

INL Integral Non-Linearity ±0.6 ±0.95 LSB (max)

DNL Differential Non-Linearity ±0.4 ±0.85 LSB (max)

OE Offset Error −0.5 ±3.0 LSB (max)

FSE Positive Full-Scale Error −0.5 ±2.3 LSB (max)

Negative Full-Scale Error -1.0 ±5 LSB (max)

GE Gain Error +1.0 ±5.5 LSB (max)

DYNAMIC CONVERTER CHARACTERISTICS

SINAD Signal-to-Noise Plus Distortion Ratio fIN = 100 kHz, −0.1 dBFS 72.3 70 dBc (min)

SNR Signal-to-Noise Ratio fIN = 100 kHz, −0.1 dBFS 72.9 71 dBc (min)

THD Total Harmonic Distortion fIN = 100 kHz, −0.1 dBFS −81.4 −74 dBc (max)

SFDR Spurious-Free Dynamic Range fIN = 100 kHz, −0.1 dBFS 84.4 74 dBc (min)

ENOB Effective Number of Bits fIN = 100 kHz, −0.1 dBFS 11.7 11.3 bits (min)

FPBW −3 dB Full Power Bandwidth Output at 70.7%FS with

FS Input

Differential

Input 26 MHz

Single-Ended

Input 22 MHz

ANALOG INPUT CHARACTERISTICS

VIN Differential Input Range −VREF V (min)

+VREF V (max)

IDCL DC Leakage Current VIN = VREF or VIN = -VREF ±1 µA (max)

CINA Input Capacitance In Track Mode 17 pF

In Hold Mode 3 pF

CMRR Common Mode Rejection Ratio See the Specification Definitions for the

test condition 76 dB

VREF Reference Voltage Range 1.0 V (min)

VAV (max)

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ADC121S655

Symbol Parameter Conditions Typical Limits Units

(Note 7)

IREF Reference Current

CS low, fSCLK = 8 MHz,

fS = 500 kSPS, output = FF8h 28 µA

CS low, fSCLK = 3.2 MHz,

fS = 200 kSPS, output = FF8h 12 µA

CS high, fSCLK = 0 0.12 µA

DIGITAL INPUT CHARACTERISTICS

VIH Input High Voltage 2.6 3.6 V (min)

VIL Input Low Voltage 2.5 1.5 V (max)

IIN Input Current VIN = 0V or VA ±1 µA (max)

CIND Input Capacitance 2 4pF (max)

DIGITAL OUTPUT CHARACTERISTICS

VOH Output High Voltage ISOURCE = 200 µA VA − 0.12 VA − 0.2 V (min)

ISOURCE = 1 mA VA − 0.16 V

VOL Output Low Voltage ISINK = 200 µA 0.01 0.4 V (max)

ISINK = 1 mA 0.05 V

IOZH, IOZL TRI-STATE Leakage Current Force 0V or VA ±1 µA (max)

COUT TRI-STATE Output Capacitance Force 0V or VA24pF (max)

Output Coding Binary 2'S Complement

POWER SUPPLY CHARACTERISTICS

VAAnalog Supply Voltage 4.5 V (min)

5.5 V (max)

IVA

(Normal))

Supply Current, Normal Mode

(Operational)

fSCLK = 8 MHz, fS = 500 kSPS, fIN = 100

kHz 1.8 2.2 mA (max)

fSCLK = 3.2 MHz, fS = 200 kSPS, fIN =

100 kHz 1.4 mA

IVA (PD) Supply Current, Power Down Mode (CS

high)

fSCLK = 8 MHz 32 µA (max)

fSCLK = 0 (Note 8) 0.3 2µA (max)

PWR

(Normal))

Power Consumption, Normal Mode

(Operational)

fSCLK = 8 MHz, fS = 500 kSPS, fIN = 100

kHz, VA = 5.0V 9 mW

fSCLK = 3.2 MHz, fS = 200 kSPS, fIN =

100 kHz, VA = 5.0V 7 mW

PWR

(PD)

Power Consumption, Power Down Mode

(CS high)

fSCLK = 8 MHz, VA = 5.0V 200 µW

fSCLK = 0, VA = 5.0V 1.5 µW

PSRR Power Supply Rejection Ratio See the Specification Definitions for the

test condition −85 dB

AC ELECTRICAL CHARACTERISTICS

fSCLK Maximum Clock Frequency 16 8MHz (min)

fSCLK Minimum Clock Frequency 0.8 3.2 MHz (max)

fSMaximum Sample Rate 1000 500 kSPS (min)

tACQ Track/Hold Acquisition Time

2.5 SCLK cycles

(min)

3.0 SCLK cycles

(max)

tCONV Conversion Time 13 SCLK cycles

tAD Aperture Delay See the Specification Definitions 6 ns

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ADC121S655

ADC121S655 Timing Specifications (Note 8)

The following specifications apply for VA = +4.5V to 5.5V, VREF = 2.5V, fSCLK = 3.2 MHz to 8 MHz, CL = 25 pF, Boldface limits

apply for TA = TMIN to TMAX: all other limits TA = 25°C.

Symbol Parameter Conditions Typical Limits Units

tCSH CS Hold Time after an SCLK rising edge 5ns (min)

tCSSU CS Setup Time prior to an SCLK rising edge 5ns (min)

tDH DOUT Hold time after an SCLK Falling edge 7 2.5 ns (min)

tDA DOUT Access time after an SCLK Falling edge 18 22 ns (max)

tDIS

DOUT Disable Time after the rising edge of CS

(Note 10) 20 ns (max)

tEN DOUT Enable Time after the falling edge of CS 8 20 ns (max)

tCH SCLK High Time 25 ns (min)

tCL SCLK Low Time 25 ns (min)

trDOUT Rise Time 7 ns

tfDOUT Fall Time 7 ns

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is

functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed

specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test

conditions. Operation of the device beyond the maximum Operating Ratings is not recommended.

Note 2: All voltages are measured with respect to GND = 0V, unless otherwise specified.

Note 3: When the input voltage at any pin exceeds the power supplies (that is, VIN < GND or VIN > VA), the current at that pin should be limited to 10 mA. The 50

mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to five.

Note 4: The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by TJmax, the

junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula PDMAX = (TJmax − TA)/θJA. The values

for maximum power dissipation listed above will be reached only when the ADC121S655 is operated in a severe fault condition (e.g. when input or output pins

are driven beyond the power supply voltages, or the power supply polarity is reversed). Such conditions should always be avoided.

Note 5: Human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is a 220 pF capacitor discharged through 0 Ω. Charge

device model simulates a pin slowly acquiring charge (such as from a device sliding down the feeder in an automated assembler) then rapidly being discharged.

Note 6: Reflow temperature profiles are different for lead-free packages.

Note 7: Tested limits are guaranteed to National's AOQL (Average Outgoing Quality Level).

Note 8: Data sheet min/max specification limits are guaranteed by design, test, or statistical analysis.

Note 9: While the maximum sample rate is fSCLK/16, the actual sample rate may be lower than this by having the CS rate slower than fSCLK/16.

Note 10: tDIS is the time for DOUT to change 10% while being loaded by the Timing Test Circuit.

Timing Diagrams

30010501

FIGURE 1. ADC121S655 Single Conversion Timing Diagram

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ADC121S655

30010504

FIGURE 2. ADC121S655 Continuous Conversion Timing Diagram

30010508

FIGURE 3. Timing Test Circuit

30010506

FIGURE 4. DOUT Rise and Fall Times

30010511

FIGURE 5. DOUT Hold and Access Times

30010510

FIGURE 6. Valid CS Assertion Times

30010512

FIGURE 7. Voltage Waveform for tDIS

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ADC121S655

Specification Definitions

APERTURE DELAY is the time between the fourth falling

edge of SCLK and the time when the input signal is acquired

or held for conversion.

COMMON MODE REJECTION RATIO (CMRR) is a measure

of how well in-phase signals common to both input pins are

rejected.

To calculate CMRR, the change in output offset is measured

while the common mode input voltage is changed from 2V to

3V.

CMRR = 20 LOG ( Δ Common Input / Δ Output Offset)

CONVERSION TIME is the time required, after the input volt-

age is acquired, for the ADC to convert the input voltage to a

digital word.

DIFFERENTIAL NON-LINEARITY (DNL) is the measure of

the maximum deviation from the ideal step size of 1 LSB.

DUTY CYCLE is the ratio of the time that a repetitive digital

waveform is high to the total time of one period. The specifi-

cation here refers to the SCLK.

EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE

BITS) is another method of specifying Signal-to-Noise and

Distortion or SINAD. ENOB is defined as (SINAD − 1.76) /

6.02 and says that the converter is equivalent to a perfect

ADC of this (ENOB) number of bits.

FULL POWER BANDWIDTH is a measure of the frequency

at which the reconstructed output fundamental drops 3 dB

below its low frequency value for a full scale input.

GAIN ERROR is the deviation from the ideal slope of the

transfer function. It is the difference between Positive Full-

Scale Error and Negative Full-Scale Error and can be calcu-

lated as:

Gain Error = Positive Full-Scale Error − Negative Full-Scale

Error

INTEGRAL NON-LINEARITY (INL) is a measure of the de-

viation of each individual code from a line drawn from negative

full scale (½ LSB below the first code transition) through pos-

itive full scale (½ LSB above the last code transition). The

deviation of any given code from this straight line is measured

from the center of that code value.

MISSING CODES are those output codes that will never ap-

pear at the ADC outputs. The ADC121S655 is guaranteed not

to have any missing codes.

NEGATIVE FULL-SCALE ERROR is the difference between

the differential input voltage at which the output code transi-

tions from negative full scale to the next code and −VREF + 0.5

LSB

OFFSET ERROR is the difference between the differential

input voltage at which the output code transitions from code

000h to 001h and 1/2 LSB.

POSITIVE FULL-SCALE ERROR is the difference between

the differential input voltage at which the output code transi-

tions to positive full scale and VREF minus 1.5 LSB.

POWER SUPPLY REJECTION RATIO (PSRR) is a measure

of how well a change in supply voltage is rejected. PSRR is

calculated from the ratio of the change in offset error for a

given change in supply voltage, expressed in dB. For the AD-

C121S655, VA is changed from 4.5V to 5.5V.

PSRR = 20 LOG (ΔOffset / ΔVA)

SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in

dB, of the rms value of the input signal to the rms value of the

sum of all other spectral components below one-half the sam-

pling frequency, not including harmonics or d.c.

SIGNAL TO NOISE PLUS DISTORTION (S/N+D or

SINAD) Is the ratio, expressed in dB, of the rms value of the

input signal to the rms value of all of the other spectral com-

ponents below half the clock frequency, including harmonics

but excluding d.c.

SPURIOUS FREE DYNAMIC RANGE (SFDR) is the differ-

ence, expressed in dB, between the desired signal amplitude

to the amplitude of the peak spurious spectral component,

where a spurious spectral component is any signal present in

the output spectrum that is not present at the input and may

or may not be a harmonic.

TOTAL HARMONIC DISTORTION (THD) is the ratio of the

rms total of the first five harmonic components at the output

to the rms level of the input signal frequency as seen at the

output, expressed in dB. THD is calculated as

where Af1 is the RMS power of the input frequency at the out-

put and Af2 through Af6 are the RMS power in the first 5

harmonic frequencies.

THROUGHPUT TIME is the minimum time required between

the start of two successive conversion.

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ADC121S655

Typical Performance Characteristics VA = 5.0V, VREF = 2.5V, TA = +25°C, fSAMPLE = 500 kSPS, fSCLK =

8 MHz, fIN = 100 kHz unless otherwise stated.

DNL - 500 kSPS

30010521

INL - 500 kSPS

30010522

DNL vs. VA

30010523

INL vs. VA

30010524

OFFSET ERROR vs. VA

30010574

GAIN ERROR vs. VA

30010577

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ADC121S655

Typical Performance Characteristics VA = 5.0V, VREF = 2.5V, TA = +25°C, fSAMPLE = 500 kSPS, fSCLK =

8 MHz, fIN = 100 kHz unless otherwise stated.

DNL vs. VREF

30010518

INL vs. VREF

30010519

OFFSET ERROR vs. VREF

30010556

GAIN ERROR vs. VREF

30010558

DNL vs. SCLK FREQUENCY

30010525

INL vs. SCLK FREQUENCY

30010526

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ADC121S655

Typical Performance Characteristics VA = 5.0V, VREF = 2.5V, TA = +25°C, fSAMPLE = 500 kSPS, fSCLK =

8 MHz, fIN = 100 kHz unless otherwise stated.

OFFSET ERROR vs. SCLK FREQUENCY

30010575

GAIN ERROR vs. SCLK FREQUENCY

30010578

DNL vs. SCLK DUTY CYCLE

30010527

INL vs. SCLK DUTY CYCLE

30010528

OFFSET ERROR vs. SCLK DUTY CYCLE

30010576

GAIN ERROR vs. SCLK DUTY CYCLE

30010579

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ADC121S655

Typical Performance Characteristics VA = 5.0V, VREF = 2.5V, TA = +25°C, fSAMPLE = 500 kSPS, fSCLK =

8 MHz, fIN = 100 kHz unless otherwise stated.

DNL vs. TEMPERATURE

30010529

INL vs. TEMPERATURE

30010530

OFFSET ERROR vs. TEMPERATURE

30010557

GAIN ERROR vs. TEMPERATURE

30010559

SNR vs. VA

30010531

THD vs. VA

30010532

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ADC121S655

Typical Performance Characteristics VA = 5.0V, VREF = 2.5V, TA = +25°C, fSAMPLE = 500 kSPS, fSCLK =

8 MHz, fIN = 100 kHz unless otherwise stated.

SINAD vs. VA

30010533

SFDR vs. VA

30010534

SNR vs. VREF

30010535

THD vs. VREF

30010536

SINAD vs. VREF

30010537

SFDR vs. VREF

30010538

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ADC121S655

Typical Performance Characteristics VA = 5.0V, VREF = 2.5V, TA = +25°C, fSAMPLE = 500 kSPS, fSCLK =

8 MHz, fIN = 100 kHz unless otherwise stated.

SNR vs. SCLK FREQUENCY

30010539

THD vs. SCLK FREQUENCY

30010540

SINAD vs. SCLK FREQUENCY

30010541

SFDR vs. SCLK FREQUENCY

30010542

SNR vs. SCLK DUTY CYCLE

30010543

THD vs. SCLK DUTY CYCLE

30010544

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ADC121S655

Typical Performance Characteristics VA = 5.0V, VREF = 2.5V, TA = +25°C, fSAMPLE = 500 kSPS, fSCLK =

8 MHz, fIN = 100 kHz unless otherwise stated.

SINAD vs. SCLK DUTY CYCLE

30010545

SFDR vs. SCLK DUTY CYCLE

30010546

SNR vs. INPUT FREQUENCY

30010547

THD vs. INPUT FREQUENCY

30010548

SINAD vs. INPUT FREQUENCY

30010549

SFDR vs. INPUT FREQUENCY

30010550

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ADC121S655

Typical Performance Characteristics VA = 5.0V, VREF = 2.5V, TA = +25°C, fSAMPLE = 500 kSPS, fSCLK =

8 MHz, fIN = 100 kHz unless otherwise stated.

SNR vs. TEMPERATURE

30010570

THD vs. TEMPERATURE

30010571

SINAD vs. TEMPERATURE

30010572

SFDR vs. TEMPERATURE

30010573

SUPPLY CURRENT vs. SCLK FREQUENCY

30010555

SUPPLY CURRENT vs. TEMPERATURE

30010554

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ADC121S655

Typical Performance Characteristics VA = 5.0V, VREF = 2.5V, TA = +25°C, fSAMPLE = 500 kSPS, fSCLK =

8 MHz, fIN = 100 kHz unless otherwise stated.

REF. CURRENT vs. SCLK FREQUENCY

30010552

REF. CURRENT vs. TEMPERATURE

30010551

SPECTRAL RESPONSE - 500 kSPS

30010514

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ADC121S655

Functional Description

The ADC121S655 analog-to-digital converter uses a succes-

sive approximation register (SAR) architecture based upon

capacitive redistribution containing an inherent sample/hold

function. The architecture and process allow the

ADC121S655 to acquire and convert an analog signal at

sample rates up to 500 kSPS while consuming very little pow-

er.

The ADC121S655 requires an external reference, external

clock, and a single +5V power source that can be as low as

+4.5V. The external reference can be any voltage between

1V and VA. The value of the reference voltage determines the

range of the analog input, while the reference input current

depends upon the conversion rate.

The external clock can take on values as indicated in the

Electrical Characteristics Table of this data sheet. The duty

cycle of the clock is essentially unimportant, provided the

minimum clock high and low times are met. The minimum

clock frequency is set by internal capacitor leakage. Each

conversion requires 16 SCLK cycles to complete. If less than

12 bits of conversion data are required, CS can be brought

high at any point during the conversion. This procedure of

terminating a conversion prior to completion is often referred

to as short cycling.

The analog input is presented to the two input pins: +IN and

–IN. Upon initiation of a conversion, the differential input at

these pins is sampled on the internal capacitor array. The in-

puts are disconnected from the internal circuitry while a con-

version is in progress.

The digital conversion result is clocked out by the SCLK input

and is provided serially, most significant bit first, at the DOUT

pin. The digital data that is provided at the DOUT pin is that of

the conversion currently in progress. With CS held low after

the conversion is complete, the ADC121S655 continuously

converts the analog input. The digital data on DOUT can be

clocked into the receiving device on the SCLK rising edges.

See the Digital Interface section and timing diagram for more

information.

1.0 REFERENCE INPUT

The externally supplied reference voltage sets the analog in-

put range. The ADC121S655 will operate with a reference

voltage in the range of 1V to VA.

As the reference voltage is reduced, the range of input volt-

ages corresponding to each digital output code is reduced.

That is, a smaller analog input range corresponds to one LSB

(Least Significant Bit). The size of one LSB is equal to twice

the reference voltage divided by 4096. When the LSB size

goes below the noise floor of the ADC121S655, the noise will

span an increasing number of codes and overall performance

will suffer. For example, dynamic signals will have their SNR

degrade, while D.C. measurements will have their code un-

certainty increase. Since the noise is Gaussian in nature, the

effects of this noise can be reduced by averaging the results

of a number of consecutive conversions.

Additionally, since offset and gain errors are specified in LSB,

any offset and/or gain errors inherent in the A/D converter will

increase in terms of LSB size as the reference voltage is re-

duced.

The reference input and the analog inputs are connected to

the capacitor array through a switch matrix when the input is

sampled. Hence, the only current required at the reference

and at the analog inputs is a series of transient spikes.

Lower reference voltages will decrease the current pulses at

the reference input and will slightly decrease the average in-

put current. The reference current changes only slightly with

temperature. See the curves, “Reference Current vs. SCLK

Frequency” and “Reference Current vs. Temperature” in the

Typical Performance Curves section for additional details.

2.0 ANALOG SIGNAL INPUTS

The ADC121S655 has a differential input, and the effective

input voltage that is digitized is (+IN) − (−IN). As is the case

with all differential input A/D converters, operation with a fully

differential input signal or voltage will provide better perfor-

mance than with a single-ended input. Yet, the

ADC121S655 can be presented with a single-ended input.

The current required to recharge the input sampling capacitor

will cause voltage spikes at +IN and −IN. Do not try to filter

out these noise spikes. Rather, ensure that the transient set-

tles out during the acquisition period (three SCLK cycles after

the fall of CS).

2.1 Differential Input Operation

With a fully differential input voltage or signal, a positive full

scale output code (0111 1111 1111b or 7FFh) will be obtained

when (+IN) − (−IN) ≥ VREF − 1.5 LSB. A negative full scale

code (1000 0000 0000b or 800h) will be obtained when (+IN)

− (−IN) ≤ −VREF + 0.5 LSB. This ignores gain, offset and lin-

earity errors, which will affect the exact differential input volt-

age that will determine any given output code.

2.2 Single-Ended Input Operation

For single-ended operation, the non-inverting input (+IN) of

the ADC121S655 should be driven with a signal or voltages

that have a maximum to minimum value range that is equal

to or less than twice the reference voltage. The inverting input

(−IN) should be biased at a stable voltage that is halfway be-

tween these maximum and minimum values.

Since the design of the ADC121S655 is optimized for a dif-

ferential input, the performance degrades slightly when driven

with a single-ended input. Linearity characteristics such as

INL and DNL typically degrade by 0.1 LSB and dynamic char-

acteristics such as SINAD typically degrades by 2 dB. Note

that single-ended operation should only be used if the perfor-

mance degradation (compared with differential operation) is

acceptable.

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ADC121S655

2.3 Input Common Mode Voltage

The allowable input common mode voltage (VCM) range de-

pends upon the supply and reference voltages used for the

ADC121S655. The ranges of VCM are depicted in Figure 8

and Figure 9. The minimum and maximum common mode

voltages for differential and single-ended operation are

shown in Table 1.

30010561

FIGURE 8. VCM range for Differential Input operation

30010562

FIGURE 9. VCM range for single-ended operation

TABLE 1. Allowable VCM Range

Input Signal Minimum VCM Maximum VCM

Differential VREF / 2 VA − VREF / 2

Single-Ended VREF VA − VREF

3.0 SERIAL DIGITAL INTERFACE

The ADC121S655 communicates via a synchronous 3-wire

serial interface as shown in the Timing Diagram section. CS,

chip select, initiates conversions and frames the serial data

transfers. SCLK (serial clock) controls both the conversion

process and the timing of serial data. DOUT is the serial data

output pin, where a conversion result is sent as a serial data

stream, MSB first.

A serial frame is initiated on the falling edge of CS and ends

on the rising edge of CS. The ADC121S655's DOUT pin is in

a high impedance state when CS is high and is active when

CS is low; thus CS acts as an output enable.

During the first three cycles of SCLK, the ADC121S655 is in

acquisition mode (tACQ), acquiring the input voltage. For the

next thirteen SCLK cycles (tCONV), the conversion is accom-

plished and the data is clocked out. SCLK falling edges one

through four clock out leading zeros while falling edges five

through sixteen clock out the conversion result, MSB first. If

there is more than one conversion in a frame (continuous

conversion mode), the ADC121S655 will re-enter acquisition

mode on the falling edge of SCLK after the N*16th rising edge

of SCLK and re-enter the conversion mode on the N*16+4th

falling edge of SCLK as shown in Figure 2. "N" is an integer

value.

The ADC121S655 can enter acquisition mode under three

different conditions. The first condition involves CS going low

(asserted) with SCLK high. In this case, the ADC121S655

enters acquisition mode on the first falling edge of SCLK after

CS is asserted. In the second condition, CS goes low with

SCLK low. Under this condition, the ADC121S655 automati-

cally enters acquisition mode and the falling edge of CS is

seen as the first falling edge of SCLK. In the third condition,

CS and SCLK go low simultaneously and the ADC121S655

enters acquisition mode. While there is no timing restriction

with respect to the falling edges of CS and SCLK, see Figure

6 for setup and hold time requirements for the falling edge of

CS with respect to the rising edge of SCLK.

3.1 CS Input

The CS (chip select bar) input is CMOS compatible and is

active low. The ADC121S655 is in normal mode when CS is

low and power-down mode when CS is high. CS frames the

conversion window. The falling edge of CS marks the begin-

ning of a conversion and the rising of CS marks the end of a

conversion window. Multiple conversions can occur within a

given conversion frame with each conversion requiring six-

teen SCLK cycles.

3.2 SCLK Input

The SCLK (serial clock) is used as the conversion clock and

to clock out the conversion results. This input is CMOS com-

patible. Internal settling time requirements limit the maximum

clock frequency while internal capacitor leakage limits the

minimum clock frequency. The ADC121S655 offers guaran-

teed performance with the clock rates indicated in the elec-

trical table.

3.3 Data Output

The output data format of the ADC121S655 is two’s comple-

ment, as shown in Table 2. This table indicates the ideal

output code for the given input voltage and does not include

the effects of offset, gain error, linearity errors, or noise. Each

data output bit is sent on the falling edge of SCLK.

While most receiving systems will capture the digital output

bits on the rising edge of SCLK, the falling edge of SCLK may

be used to capture each bit if the minimum hold time (tDH) for

DOUT is acceptable. See Figure 5 for DOUT hold and access

times.

DOUT is enabled on the falling edge of CS and disabled on the

rising edge of CS. If CS is raised prior to the 16th falling edge

of SCLK, the current conversion is aborted and DOUT will go

into its high impedance state. A new conversion will begin

when CS is taken LOW.

www.national.com 18

ADC121S655

TABLE 2. Ideal Output Code vs. Input Voltage

Analog Input

(+IN) − (−IN)

2's

Complement

Binary Output

2's

Comp.

Hex Code

2's

Comp.

Dec Code

VREF − 1.5 LSB 0111 1111 1111 7FF 2047

+ 0.5 LSB 0000 0000 0001 001 1

− 0.5 LSB 0000 0000 0000 000 0

0V − 1.5 LSB 1111 1111 1111 FFF −1

−VREF + 0.5 LSB 1000 0000 0000 800 −2048

Applications Information

OPERATING CONDITIONS

We recommend that the following conditions be observed for

operation of the ADC121S655:

−40°C ≤ TA ≤ +105°C

+4.5V ≤ VA ≤ +5.5V

1V ≤ VREF ≤ VA

3.2 MHz ≤ fCLK ≤ 8 MHz

VCM: See Section 2.3

4.0 POWER CONSUMPTION

The architecture, design, and fabrication process allow the

ADC121S655 to operate at conversion rates up to 500 kSPS

while consuming very little power. The ADC121S655 con-

sumes the least amount of power while operating in power

down mode. For applications where power consumption is

critical, the ADC121S655 should be operated in power down

mode as often as the application will tolerate. To further re-

duce power consumption, stop the SCLK while CS is high.

4.1 Short Cycling

Another way of saving power is to short cycle the conversion

process. This is done by pulling CS high after the last required

bit is received from the ADC121S655 output. This is possible

because the ADC121S655 places the latest converted data

bit on DOUT as it is generated. If only 8-bits of the conversion

result are needed, for example, the conversion can be termi-

nated by pulling CS high after the 8th bit has been clocked

out. Halting the conversion after the last needed bit is out-

putted is called short cycling.

Short cycling can be used to lower the power consumption in

those applications that do not need a full 12-bit resolution, or

where an analog signal is being monitored until some condi-

tion occurs. For example, it may not be necessary to use the

full 12-bit resolution of the ADC121S655 as long as the signal

being monitored is within certain limits. In some circum-

stances, the conversion could be terminated after the first few

bits. This will lower power consumption in the converter since

the ADC121S655 spends more time in power down mode and

less time in the conversion mode.

4.2 Burst Mode Operation

Normal operation of the ADC121S655 requires the SCLK fre-

quency to be sixteen times the sample rate and the CS rate

to be the same as the sample rate. However, in order to min-

imize power consumption in applications requiring sample

rates below 200 kSPS, the ADC121S655 should be run with

an SCLK frequency of 8 MHz and a CS rate as slow as the

system requires. When this is accomplished, the

ADC121S655 is operating in burst mode. The ADC121S655

enters into power down mode at the end of each conversion,

minimizing power consumption. This causes the converter to

spend the longest possible time in power down mode. Since

power consumption scales directly with conversion rate, min-

imizing power consumption requires determining the lowest

conversion rate that will satisfy the requirements of the sys-

tem.

5.0 TIMING CONSIDERATIONS

Proper operation requires that the fall of CS not occur simul-

taneously with a rising edge of SCLK. If the fall of CS occurs

during the rising edge of SCLK, the data might be clocked out

one bit early. Whether or not the data is clocked out early

depends upon how close the CS transition is to the SCLK

transition, the device temperature, and characteristics of the

individual device. To ensure that the data is always clocked

out at a given time (the 5th falling edge of SCLK), it is essential

that the fall of CS always meet the timing requirement speci-

fied in the Timing Specification table.

6.0 PCB LAYOUT AND CIRCUIT CONSIDERATIONS

For best performance, care should be taken with the physical

layout of the printed circuit board. This is especially true with

a low reference voltage or when the conversion rate is high.

At high clock rates there is less time for settling, so it is im-

portant that any noise settles out before the conversion be-

gins.

6.1 Power Supply

Any ADC architecture is sensitive to spikes on the power sup-

ply, reference, and ground pins. These spikes may originate

from switching power supplies, digital logic, high power de-

vices, and other sources. Power to the ADC121S655 should

be clean and well bypassed. A 0.1 µF ceramic bypass ca-

pacitor and a 1 µF to 10 µF capacitor should be used to

bypass the ADC121S655 supply, with the 0.1 µF capacitor

placed as close to the ADC121S655 package as possible.

6.2 Voltage Reference

The reference source must have a low output impedance and

needs to be bypassed with a minimum capacitor value of 0.1

µF. A larger capacitor value of 1 µF to 10 µF placed in parallel

with the 0.1 µF is preferred. While the ADC121S655 draws

very little current from the reference on average, there are

higher instantaneous current spikes at the reference input

that must settle out while SCLK is high. Since these transient

spikes can be as high as 20 mA, it is important that the ref-

erence circuit be capable of providing this much current and

settle out during the first three clock periods (acquisition time).

The reference input of the ADC121S655, like all A/D convert-

ers, does not reject noise or voltage variations. Keep this in

mind if the reference voltage is derived from the power supply.

Any noise and/or ripple from the supply that is not rejected by

the external reference circuitry will appear in the digital re-

sults. The use of an active reference source is recommended.

The LM4040 and LM4050 shunt reference families and the

LM4132 and LM4140 series reference families are excellent

choices for a reference source.

6.3 Power and Ground Planes

A single ground plane and the use of two or more power

planes is recommended. The power planes should all be in

the same board layer and will define the analog, digital, and

high power board areas. Lines associated with these areas

should always be routed within their respective areas.

The GND pin on the ADC121S655 should be connected to

the ground plane at a quiet point. Avoid connecting the GND

pin too close to the ground point of a microprocessor, micro-

controller, digital signal processor, or other high power digital

device.

19 www.national.com

ADC121S655

7.0 APPLICATION CIRCUITS

The following figures are examples of the ADC121S655 in

typical application circuits. These circuits are basic and will

generally require modification for specific circumstances.

7.1 Data Acquisition

Figure 10 shows a typical connection diagram for the

ADC121S655 operating at a supply voltage of +5V. A 5 to 10

ohm resistor is shown between the supply pin of the

ADC121S655 and the microcontroller to low pass filter any

high frequency noise present on the supply line. The refer-

ence pin, VREF, is connected to a 2.5V shunt reference, the

LM4040-2.5, to define the analog input range of the

ADC121S655 independent of supply variation on the +5V

supply line. The VREF pin should be de-coupled to the ground

plane by a 0.1 uF ceramic capacitor and a tantalum capacitor

of at least 4.7 uF. It is important that the 0.1 uF capacitor be

placed as close as possible to the VREF pin while the place-

ment of the tantalum capacitor is less critical. It is also rec-

ommended that the supply pin of the ADC121S655 be de-

coupled to ground by a 1 uF capacitor.

30010563

FIGURE 10. Low cost, low power Data Acquisition

System

7.2 Pressure Sensor

Figure 11 shows an example of interfacing a pressure sensor

to the ADC121S655. A digital-to-analog converter (DAC) is

used to bias the pressure sensor. The DAC081S101 provides

a means for dynamically adjusting the sensitivity of the sen-

sor. A shunt reference voltage of 2.5V is used as the reference

for the ADC121S655. The ADC121S655, DAC081S101, and

the LM4040 are all powered from the same voltage source.

30010566

FIGURE 11. Interfacing the ADC121S655 for a Pressure Sensor

www.national.com 20

ADC121S655

Physical Dimensions inches (millimeters) unless otherwise noted

8-Lead MSOP

Order Number ADC121S655CIMM

NS Package Number MUA08A

21 www.national.com

ADC121S655

Notes

ADC121S655 12-Bit, 200 kSPS to 500 kSPS, Differential Input, Micro Power A/D Converter

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