88EM8081XX-SAG2C000 - Marvell Semiconductor, Inc.

Marvell. Moving Forward Faster

Doc. No. MV-S106340-01, Rev. C

August 27, 2010

Document Classification: Proprietary

Customer Use Only

Cover

88EM8080/88EM8081

LED Power Supply Controller for

Flyback Converters with Power Factor

Correction

Datasheet

Document Conventions

Note: Provides related information or information of special importance.

Caution: Indicates potential damage to h ardware or software, or loss of data.

Warning: Indicates a risk of personal injury.

Document Status

Doc Status: 2.00 Technical Publication: 0.xx

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88EM8080/88EM8081

Datasheet

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88EM8080/88EM8081

LED Power Supply Controller for Flyback Converters

with Power Factor Correction

August 27, 2010, 2.00 Document Classification: Proprietary Page 3

PRODUCT OVERVIEW

The Marvell® 88EM8080/88EM8081 device is a high

performance LED power supply controller for flyback converters

with output regulation and power factor correction. The

88EM8080/8081 control algorithm uses Average Current Mode

Control (ACMC) for powe r factor correction (PFC) in LED

lighting applications with low harmonic distortion and good

noise immunity. The Marvell proprietary adaptive loop control

achieves high power factor under high input voltage and low

load conditions. Through Marvell's innovative digital signal

processing (DSP) solution, the LED controller with the PFC

function provides the customer with the smallest package, the

lowest system cost, the lowest total harmonic distortion (THD)

and the best power factor for LED lighting applications.

Both devices work at fixed frequencies, 88EM8080 at 60kHz

while 88EM8081 at 120kHz. The IC operates under Continuous

Conduction Mode (CCM) or Discontinuous Conduction Mode

(DCM) or both combined together operating in Mixed Mode.

The internal voltage loop compensation and current loop control

guarantee system stability and thus reduce the exernal

component count and costs.

The 8-pin SOIC package further facilitates the application

design process by saving board space. The resultant simple

system design and minimum cost makes 88EM8080/88EM8081

the ideal choice for LED applications with PFC. Figure 1 shows

a reference schematic for a universal isolated LED d river with

PFC using the 88EM8080/88EM8081 device.

General Features

Mixed Mode – CCM and DCM operation

Average current mode control

Adaptive control loop achieves high power factor and

low THD for a wide range of voltage and load

conditions

Adaptive over current protection for universal voltage

Fixed switching frequency

1.2A (typical) driver capability

Minimal external components required

Under voltage lockout (UVLO)

Over voltage protection (OVP)

Thermal shutdown

Input line frequency range from 45Hz to 65Hz

Applications

LED home and facility lighting

LED street lamps

Figure 1: Universal Isolated LED Driver with PFC

VIN

C14

FB ISNS

SGND

PGND

VDD

88EM8081

R19

R11

C5R6

VDD

T1B

R15

R16

R13

L1 HVDC

C7 C10

R18 R17

R12

VAR1

C12

D10

RS1J

C3 D9

C11 C13

NTC1

R23

R10

LED +

LED -

R8R3R1

TS321LT

PC1A

R22

R21

VREF

TL431

P/O PC1A

C15

88EM8080/88EM8081

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Table of Contents

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Table of Contents

Table of Contents .......................................................................................................................................5

List of Figures.............................................................................................................................................7

List of Tables ..............................................................................................................................................9

1 Signal Description.......................................................................................................................11

1.1 Pin Configurations...........................................................................................................................................11

1.2 Pin Descriptions..............................................................................................................................................11

2 Electrical Specifications .............................................................................................................15

2.1 Absolute Maximum Ratings ........ ...................................................................................................................15

2.2 Electrical Characteristics ................................................................................................................................16

3 Functional Description................................................................................................................19

3.1 Overview .........................................................................................................................................................19

3.2 VDD – Bias Power Input .................................................................................................................................20

3.3 PGND and SGND .... ... .............................................................................. ... ... ................... .............................20

3.4 SW – Switched PWM Output for Gate Drive...................................................................................................20

3.5 VIN – Input Voltage Sensing...........................................................................................................................21

3.5.1 Brown-out Protection........................................................................................................................21

3.6 FB – Output Voltage / Current Feedback........................................................................................................21

3.6.1 FB – Over Voltage Protection (OVP)................................................................................................21

3.6.2 FB – Regulation................................................................................................................................22

3.6.2.1 Output Current Regulation - Isolated Outp ut................ ....................... .. ... ....................... ...22

3.6.2.2 Output Current Regulation - Non-isolated Output......................... .....................................22

3.6.2.3 Output Voltage Regulation - Isolated Output......................................................................22

3.6.2.4 Output Voltage Re gu l a ti on - No n-i s o l ated Output..............................................................23

3.7 ISNS – Current Sensing / Over Current Protection.........................................................................................23

3.7.1 ISNS – Peak Current Sensing ..........................................................................................................23

3.7.2 ISNS – Average Current Mode Control ............................................................................................23

3.7.3 ISNS – Adaptive Over Current Protection ........................................................................................23

3.7.4 OCP – Cycle by Cycle Over Current Protection...............................................................................23

3.8 Mixed Modes of Operation..............................................................................................................................24

3.9 Compensation and Adaptive Control Loop .....................................................................................................24

3.10 Over Temperature Protection..........................................................................................................................24

4 Functional Characteristics .........................................................................................................25

4.1 VDD Characteristics ........................................................................................................................................25

4.2 VFB Characteristics for Over Voltage Protection.............................................................................................27

4.3 Switching Frequency Characteristics.............. ... ... ...................... ... ...................... ... ........................................28

4.4 Over Current Threshold Characteristics..........................................................................................................29

88EM8080/88EM8081

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5 Design and Applications Information........................................................................................31

5.1 Overview .........................................................................................................................................................31

5.2 Input Voltage Resistor Divider on VIN Pin.......................................................................................................32

5.2.1 Brown-out Protection........................................................................................................................33

5.2.2 Layout Guidelines............... ... .......................................... .......................................... .......................34

5.3 Output LED Current Contr ol................. ....................................... ... ... ................... ... ... .....................................34

5.3.1 Non-isolated Output LED Current Control ........................................................................................35

5.3.1.1 R1 and R2 Resistor Divider Design......................... .. ... ... ...................... ... ... .......................36

5.3.1.2 RC Filter Design.................................................................................................................36

5.3.1.3 Design of Operational Amplifier Circuit ....... ... ....................... .. ... ....................... ... .. ............36

5.3.2 Low-Cost LED Current Control with Non-isolated Output.................................................................37

5.3.3 LED Current Control with Isolated Output ........................................................................................38

5.3.4 Isolated LED Current Control - Circuit Design..................................................................................40

5.3.4.1 Design of Operational Amplifier Circuit ....... ... ....................... .. ... ....................... ... ..............41

5.3.5 NTC Compensation Circuit Design...................................................................................................43

5.3.5.1 Design Equations ...............................................................................................................44

5.3.5.2 Simplified Engineering Desig n Pro cedure..........................................................................46

5.4 Current Sensing and Over Current Protection ................................................................................................47

5.4.1 Current Sensing Through ISNS Pin..................................................................................................47

5.4.2 Average Current Signal and Over Power Limitation.........................................................................48

5.4.3 Peak Current and Average Current Relationship .............................................................................49

5.4.4 Cycle by Cycle Current Protection through OCP Pin........................................................................50

5.5 SW Pin to MOSFET Gate ...............................................................................................................................52

5.6 VDD, Signal (SGND) and Power (PGND) Grounds....................... ... ... ...................... ... ...................... ... .........52

5.7 Non-isolated LED Driv er ...................... ... ................... ... ....................................... ... ........................................54

5.7.1 Non-isolated LED Driver Schematic.................................................................................................54

5.7.2 Non-isolated LED Driver Description................................................................................................55

5.8 Isolated LED Driver.........................................................................................................................................56

5.8.1 Isolated LED Driver Schematic.........................................................................................................56

5.8.2 Isolated LED Driver Description........................................................................................................57

5.8.3 12.5W Universal Isolated LED Driver Test Results .................... .......................................... ............58

5.8.3.1 Efficiency and Power Factor......................................... ... ...................... ... ....................... ...58

5.8.3.2 Start-up Waveforms ......................... ... .......................................... .....................................59

5.8.3.3 Steady State Waveforms....................................................................................................59

6 Mechanical Drawings..................................................................................................................61

6.1 Mechanical Drawings......................................................................................................................................61

7 Part Order Numbering/Package Marking ..................................................................................63

7.1 Part Order Numbering ..................................................................................................................................63

7.2 Package Markings..................... ...................... .......................................... ......................................................64

A Revision History ..........................................................................................................................65

List of Figures

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List of Figures

Figure 1: Universal Isolated LED Driver with PFC.............................................................................................3

1 Signal Description ........................................................................................................................... 11

Figure 2: SOIC-8 Pin Diagram (Top View).......................................................................................................11

2 Electrical Specifications ................................................................................................................. 15

3 Functional Description.................................................................................................................... 19

Figure 3: Top Level Block Diagram..................................................................................................................19

4 Functional Characteristics.............................................................................................................. 25

Figure 4: IDD Quiescent (IDD_QST) vs. VDD ...................................................................................................25

Figure 5a: IDD vs. VDD (VDD_ON)........................................................................................................................25

Figure 5b: IDD vs. VDD (VDD_ON)........................................................................................................................25

Figure 6a: IDD Operation (IDD_OP) vs. Temperature........................................................................................ 26

Figure 6b: IDD Operation (IDD_OP) vs. Temperature........................................................................................ 26

Figure 7: VDD On/Off vs. Temperature ...........................................................................................................26

Figure 8: IDD vs. VFB........................................................................................................................................27

Figure 9: VFB_OVP vs. Temperature..............................................................................................................27

Figure 10: VFB_OVP Hysteresis vs. Temperature ............................................................................................27

Figure 11: VFB_OVP_LATCH vs. Temperature ................................................................................................27

Figure 12: Normal Regulation Reference (VFB_REG) vs. Temperature...........................................................28

Figure 13: Switching Frequency vs. Temperature .............................................................................................28

Figure 14: Over Current (VIOVER) vs. Input Voltage VIN Peak Value).............................................................29

Figure 15: Over Current (VIOVER) vs. Temperature.........................................................................................29

5 Design and Applications Information............................................................................................ 31

Figure 16: Internal Block for Zero-cross Detection, Brown-out Protection.........................................................32

Figure 17: Peak Detecting Signal for Predictive Sinusoidal AC Voltage............................................................33

Figure 18: Input Voltage Resistor Divider Layout Guide lines ............................................................................34

Figure 19: Non-Isolated Feedback Lo op Schematic..........................................................................................35

Figure 20: Low-cost, Non-isolated LED Current Contro l....................................................................................37

Figure 21: Isolated LED Current Control............................................................................................................38

Figure 22: Isolated LED Current Control with NTC Compensation....................................................................43

Figure 23: The Error Amplifier Output Voltage (VC) vs. Temperature...............................................................45

Figure 24: Current Sensing Circuit.....................................................................................................................47

Figure 25: Current Sensing and Over Current Protection Waveforms...............................................................49

Figure 26: Current Sensing and Cycle by Cycle Over Current Protection Circuit..............................................50

Figure 27: SW Pin Layout Guidelines................................................................................................................52

Figure 28: VDD Decoupling Capacitor and Ground Layout Guid elines.............................................................53

Figure 29: 1W Non-isolated LED Driver Schematic...........................................................................................54

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Figure 30: 12.5W Universal Isolated LED Driver Schematic..............................................................................56

Figure 31: Efficiency, Power Factor...................................................................................................................58

Figure 32: Start-up at 115VAC at Full Load.......................................................................................................59

Figure 33: Start-up at 230VAC at Full Load.......................................................................................................59

Figure 34: Steady State at 115VAC at Full Load...............................................................................................59

Figure 35: Steady State at 230VAC at Full Load...............................................................................................59

6 Mechanical Drawings ...................................................................................................................... 61

Figure 36: 8-Lead SOIC Mechanical Drawing ...................................................................................................61

7 Part Order Numbering/Package Marking....................................................................................... 63

Figure 37: Sample Ordering Part Number .........................................................................................................63

Figure 38: Package Marking..............................................................................................................................64

List of Tables

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List of Tables

1 Signal Description ............................................................................................................................11

Table 1: Pin Definitions...................................................................................................................................11

Table 2: Pin Descriptions................................................................................................................................12

2 Electrical Specifications ..................................................................................................................15

Table 3: Absolute Maximum Ratings..............................................................................................................15

Table 4: Electrical Characteristics ..................................................................................................................16

3 Functional Description.....................................................................................................................19

Table 5: Functional Summary.........................................................................................................................19

4 Functional Characteristics...............................................................................................................25

5 Design and Applications Information.............................................................................................31

Table 6: Comparison between Critical Transition Mode and Mixed Mode Controls.......................................32

Table 7: Current Sensing Circuit.....................................................................................................................48

Table 8: Current Sensing Resistor Selection Reference ................................................................................48

Table 9: Efficiency and Power Factor Test Results.................... ... ... ................... ... ............................... .........58

6 Mechanical Drawings .......................................................................................................................61

7 Part Order Numbering/Package Marking........................................................................................63

Table 10: 88EM8080/88EM8081 Part Order Options.......................................................................................63

Table 11: Revision History................................................................................................................................65

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Signal Description

Pin Configurations

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1Signal Description

1.1 Pin Configurations

1.2 Pin Descriptions

Table 1: Pin Definitions

Figure 2: SOIC-8 Pin Diagram (Top View)

PGND

SGND

ISNS

OCP

VDD

FBVIN

Pin # Pin Name Pin Type Pin Description

1 PGND GND Power Ground

2 SGND GND Signal Ground

3 ISNS Input Current Sen s e

4 VIN Input Voltage Input

5 FB Input Feedback

6 OCP Input Over Current Protection

7 VDD Supply IC Supply Voltage

8 SW Output Switch

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Table 2: Pin Descriptions

Pin # Pin Name Pin Function

1PGNDPower Ground

• Connected to the source of the primary MOSFET.

• The PCB trace from the power ground to the source of the primary MOSFET must be kept

as short as possible.

• To avoid any switching noise interruption on signal processing, PGND and SGND remain

seperate inside the I C.

2SGNDSignal Ground

• Must be connected to the power ground with the Kelvin sensing connection (typically

connected to th e source of the external MOSFET) so that SGND has dedicated trace and

connections and provides clean signal integrity.

• To avoid any switching noise interruption on signal processing, SGND and PGND remain

seperate inside the I C.

3ISNSCurrent Sense

• Used for current shaping and for over current protection.

• Sense resistor varies for different loads.

Examples - 0.15Ω at 120W rated load and 0.6Ω for 30W rated load.

4VINVoltage Input

• Connect s to resistance divider at input AC line “phase” to GND. Voltage applied is a half

rectified sine wave scaled down by the input resistance divider.

• Voltage input pin is a high impedance input pin. An impedance of 2M (typical) is

recommended to be designe d from the in put AC “phase” to GND f or the VIN resistor divid or

network to reduce the standby power. Higher impedance is preferred with the right PCB

design on this pin signal.

• This voltag e in put after comparing with an intern al t hreshold referen ce is used to det ect t he

zero-cross location of the input sine wave and is also used to synthesize (regenerate) the

input sine wave. This regenerated sine wave is used for the current reference.

• Brown-out protection function is also provided by this pin. A resistor devider with a 100:1

ratio from the highsid e resistor to the lowside resistor is corresponding to a “brown-out

protection” input voltage of 50V (RMS). Increasing that ratio will increase the “brown-out

voltage”. Brown-out voltage is determined by R6, R13 and R16 as shown in Figure 1. Refer to

Section 5.2 for further understanding.

5FBFeedback

• The output voltage of 100% rated value is scaled to 2.5V at the FB Pin.

• Transition from soft-start to normal regulation is at 87.5% rated VFB. When FB pin voltage

exceeds VFB_OVP, the IC shuts down the SW pin driver pul se. SW pi n dri ver pulse recove rs

when FB pin falls below the reference voltage, VFB_REG.

• There is another OVP latch threshold (VFB_OVP_LATCH) of 3.77V on the FB pin. When FB

exceeds VFB_OVP_LATCH, latched over voltage shutdown occurs until another VDD power

on resets the latch.

• The effective resistance bet ween FB and GND is 200k (typical).

6OCPOver Current Protection

• Used to turn off the MOSFET when it is pulled as logic low

Signal Description

Pin Descriptions

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7VDDIC Supply Voltage

• Nominal voltage is 12V and the Under Voltage Lock Out (UVLO) occurs when

VDD < VDD_UVLO and the IC is turned off.

• The IC is turned on whenever VDD > VDD_ON (typ. 11.9V).

• The maximum volt age on VDD is 16V.

• VDD should be clamped by a zener for protection i n the system de sign. Refer to Table 4 for

more details.

8SWSwitch

• PWM gate signal for the switch.

• It should be connected to the gate of external MOSFET through a gate resistor.

Table 2: Pin Descriptions

Pin # Pin Name Pin Function

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Electri ca l Specific at io ns

Absolute Maximum Ratings

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2Electrical Specifications

2.1 Absolute Maximum Ratings

Table 3: Absolute Maximum Ratings1

NOTE: Stresses above those listed in Absolute Maximum Ratings may cause permanent device failure. Functionality at or

above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device

reliability.

1. Exceeding the absolute maximum rating may damage the device.

Symbol Parameter Min Max Units

VDD Power Supply (Voltage to PGND=SGND) -0.3 18 V

VIsns Voltage at ISNS pin -0.5 0.5 V

VOCP Voltage at OCP pin -0.3 5.5 V

VVIN Voltage at VIN pin -0.3 5.5 V

VFB Voltage at FB pin -0.3 5.5 V

ISW Driver Current (In stantaneous Peak) 2 A

θJA Thermal Resistance 156.5 °C/W

TAOperating Ambient Temperature Range2

2. Specifications over the -40°C to 85°C ope rating temperature ranges are assured by design, characterization and

correlation with statistical process controls.

-40 85 °C

TJMaximum Junction Temperature 125 °C

TSTOR Storage Temperature Range -65 150 °C

VESD ESD Rating3

3. Devices are ESD sensitive. Handling precautions recommended. Human Body model, 1.5kΩ in series with 100pF.

2kV

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2.2 Electrical Characteristics

Table 4: Electrical Characteristics

NOTE: A 12V supply voltage is applied and the ambient temperature (TA) = 25°C.

Symbol Parameter Conditions Min Typ Max Units

VDD Supply

VDD Supply Voltage 7.0 12 16 V

VDD_ON VDD Power On Threshold 11.9 V

VDD_UVLO VDD Power Off Threshold

(UVLO) After VDD is powered up

and running 7.0 V

VDD_UVLO_HYS VDD_UVLO Hysteresis 4.8 5 V

IDD_QST VDD Quiescent Current1VDD = 12V 95 µA

IDD_OP VDD Operating Current VDD = 12V;

CGate = 1nF

FSW = 118kHz

VIN=0

5.2 mA

Thermal Shutdown

TSD Thermal Shutdown 150 °C

TSD_HYS Hysteresis for Thermal

Shutdown 25 °C

Output Gate Driver

VG_HI Minimum Gate High Voltage2VDD = 12V

CGate = 1nF

Sourcing 500mA

10.0 V

VG_LO Maximum Gate Low

Voltage3VDD = 12V

CGate = 1nF

Sinking 500mA

2.0 V

RDSON Gate Drive Resistance S ourcing 120mA

T=25C2.4 Ω

Gate Drive Resistance Sinking 120mA

T=25C2.0 Ω

ISW_PK Driver Peak Current CGate = 10nF

VDD = 12V 1.2 A

tRRise Time CGate = 1 nF 35 ns

CGate = 10 nF 125 ns

tFFall Time CGate = 1 nF 35 ns

CGate = 10 nF 145 ns

DMAX Maximum Duty Cycle 88 %

Electri ca l Specific at io ns

Electrical Characteristics

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DMIN Minimum Duty Cycle43%

Feedback/Overvoltage

VFB_REG Normal Regulation

Reference IC powered on 2.55 V

VFB_OVP Over Voltage Protection

Threshold At 120% of VFB_REG.3.04V

VFB_OVP_HYS Over Voltage Protection

Hysteresis 0.49 V

VFB_OVP_LATCH Over Voltage Protection

Latch 3.77 V

Current Sensing and Current Pr otection5

VIOVER_TH1 Over Current Threshold

Zone 16Peak value of half-sine

voltage at VIN:

1.26<VIN<1.89Vpk7

397 mV

VIOVER_TH2 Over Current Threshold

Zone 25Peak value of half-sine

voltage at VIN:

1.89<VIN<2.59Vpk8

329 mV

VIOVER_TH3 Over Current Threshold

Zone 35Peak value of half-sine

voltage at VIN:

2.59< VIN<3.43Vpk9

269 mV

VIOVER_TH4 Over Current Threshold

Zone 45Peak value of half-sine

voltage at VIN:

3.43<VIN<3.85Vpk10

202 mV

VIOVER_CYC Cycle by cycle current

protection logic input (OCP

pin) threshold for SW on11

1.68 V

88EM8080 Switching Frequency Oscil lator

FSW Frequency

(Average Mode) 59 kHz

88EM8081 Switching Frequency Oscil lator

FSW Frequency

(Average Mode) 118 kHz

1. VDD Quiescent Current: VDD power supply current before VDD first time reaches VDD_ON.

2. Considering the voltage drop on the internal driver MOSFET during current sourcing.

3. Considering the voltage drop on the internal driver MOSFET during current sinking.

Table 4: Electrical Characteristics (Continued)

NOTE: A 12V supply voltage is applied and the ambient temperature (TA) = 25°C.

Symbol Parameter Conditions Min Typ Max Units

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4. If the duty cycle is less than 3% from the DSP calculations, one PWM cycle is skipped and this duty-cycle value is added

to the next PWM duty cycle calculation.

5. To achieve almost constant power limit for the universal input range, current protection self-adjusts thresholds in four

zones of input voltage levels. A margin of 50% compared to the rated current is considered for the threshold current

values.

6. Threshold of negative voltage drop across Rsns due to instantaneous current

7. With input divider ratio of 1/100, these values are equivalent to 90 Vrms<Vline<135 Vrms. (Section 5.2, equation (1))

8. With input divider ratio of 1/100, these values are equivalent to 135 Vrms<Vline<185 Vrms. (Section 5.2, equation (1))

9. With input divider ratio of 1/100, these values are equivalent to 185 Vrms<Vline<245 Vrms. (Section 5.2, equation (1))

10.With input divider ratio of 1/100, these values are equivalent to 245 Vrms<Vline<275 Vrms. (Section 5.2, equation (1))

11.OCP falling threshold for VIOVER_CYC is 1V with a hysteresis of 0.68V.

Functional Description

Overview

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3Functional Description

3.1 Overview

The 88EM8080/88EM8081 is a high-performance power factor correction controller for single stage flyback LED

lighting applications with a minimum number of components at a low cost. The following section outlines the

functions of various input and output signals of the 88EM8080/88EM8081 device as listed below in Table 5 .

Table 5: Functional Summary

Section Pin Name Function

Section 3.2 VDD Bias power for IC

Section 3.3 PGND/SGND Power and signal ground is the return for power and signals

Section 3.4 SW Gate drive output

Section 3.5 VIN Input voltage sensing and brown-out protection

Section 3.6 FB Inverting input of an internal error amplifier used for regulation of output voltage / current

Section 3.7 ISNS Input current sensing used for providing PFC and for adaptive over current protection

Section 3.7.3 OCP Over current protection used for cycle by cycle protection

Figure 3: Top Level Block Diagram

DSP

Core

88EM8080/8081

Current

Amplifier MUX

Switcher

ADC

Current

Protection

Threshold

Selection

Zero Cross

Detect

Power

Distribution

and

Bandgaps

Start up S et t i ng

Frequency Sett i ng

Over

Temperature

Gate

Driver

C urrent Protecti on

Protection

Management

Clock

ISNS

VIN

_over

o_over

_over

o_over

OCPVDD

Oscillator

Fault

Driver

Disable

PGND SGND

Output

Voltage

Level Det ect

Serial Data

Interface

State

Machine

Note

I_over, Vo_over, and T_over are the over current, over voltage, and over temperature signals

respectively.

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3.2 VDD – Bias Power Input

The controller needs bias power which is recieved through the VDD and PGND pins. The nominal

voltage for the VDD pin is around 12 V olt s and the IC will start switching as long as the VDD voltage

exceeds the VDD_ON Power-on threshold described in Table 4, Electrical Characteristics, on

page 16. The PWM switched output at the SW pin is available after the IC is switched on. Once

powered up and switching has started, the VDD voltage can reach as low as 7 Volts (typical), at

which point the IC is switched off. This 7 volt threshold is the under voltage lockout (UVLO) value.

Once VDD goes below the UVLO thresho ld voltage, VDD must climb back to the VDD_ON threshold

to start switching once again. The maximum voltage needs to be less than 16 volts which provides

some margin from an absolute maximum VDD voltage rating of 18 Volts. When the IC is not

switching (less than 12 volts before turn-on and less than 7 volts after turn-on), the

88EM8080/88EM8081 draws very little quiescent current which has a typical rating of 95μA. During

switching, the operating current from the VDD source is around 5.2mA.

From a circuit design point of view, bias can be provided initially from the rectified low frequency AC

input. Once the IC starts switching, bias power can be derived from the high frequen cy part of the

circuit. As an example, an auxiliary winding on the flyback transformer can be used to provide this

high frequency power . It is necessary to rectify the high frequency AC from the auxiliary winding and

to have necessary filtering to reduce the high frequency ripple at the VDD pin. This approach of

providing high frequency bias power after turn-on will impr ove the efficiency of the bias power

circuitry in the steady state. It should be noted that during startup, at the instant of switching, the

current drawn by the chip increases from 95μA to 5.2mA (typical). This sudden step load of bias

power will tend to decrease the VDD voltage. If the VDD voltage falls below 7 volts due to this

reason, the IC will go through another starting cycle. To prevent this hiccup, adequate energy

storage (capacitor) needs to be provided. The capacitors across VDD and PGND will help to keep

the VDD voltage above 7 volts.

Care is also needed in the design of bias power circuit from the rectified low frequency AC side. If a

simple resistance is used to charge the capacitor across VDD and PGND, the turn-on time could be

longer. Variations in the bia s circuit design may be accommodated to meet the specified turn-on

time.

The under voltage lockout (UVLO) feature can be used to shut off the IC during a fault condition by

forcing the VDD voltage to go below 7 volts. If the fault is removed, VDD voltage can be allowed to

increase to VDD_ON and the IC will go through a new starting cycle.

3.3 PGND and SGND

The 88EM8080/88EM8081 has separated the power ground pin (PGND) and signal ground pin

(SGND) inside the IC to avoid any noise interruption during signal processing. The PGND pin should

be connected to the primary MOSFET source pin and the connection trace should be as short as

possible. The SGND must be connected to the PGND through a Kelvin sensing connection trace to

achieve a clean signal ground.

3.4 SW – Switched PWM Output for Gate Drive

The SW pin is the PWM output pin for the IC. The IC has an internal totem pole drive circuit to drive

the gate of an external power MOSFET through this SW pin. A gate resistor is recommended to

provide damping in the external drive circuit and to minimize the parasitic ringing. The PWM outp ut

gate drive capibility is 1.2A (typical). If necessary, additional drive circuitry along with speed up

circuitry can be added to the SW pin output for very high power levels.

Functional Description

VIN – Input V o ltag e Sen s ing

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3.5 VIN – Input Voltage Sensing

The PFC function is implemented by sensing the input current waveform and forcing the average of

the input current to follow the input voltage sinusoidal waveform. A resistor divider is used betw een

AC input and a primary reference ground to sens e the input voltage. The primary reference ground

is connected to the 88EM8080/88EM8081 IC reference ground and to the source pin of the external

switching MOSFET Q1 as in Figure 1, Universal Isolated LED Driver with PFC, on page 3. The

output of the resistor divider which is a half sinusoidal waveform is the input to the VIN pin. By

sensing the input voltage waveform at the VIN pin, the control ler can generate its own internal

sinusoidal reference at the same frequency as the input. This is done by having an internal DC

threshold (0.72 Volts), a comparator and a zero-cross detection circuit. The details of the

calculations are described in Section 5.2.

It is recommended to use a high impe dance divider network between the AC line to reference AC

ground to sense the input voltage at the VIN pin. This will help to reduce the no load input power and

will improve the efficiency in general. Due to the VIN pin being a high impedance input pi n, a 10nF

(typical) decoupling noise capacitor between it and ground is required.

3.5.1 Brown-out Protection

VIN pin is also used for the brown-out protection function. A resistor divider of 100:1 ratio from the

high voltage side corresponds to a brown-out protection input voltage of around 50V RMS for the

defined internal threshold of 0.72 Volts. Increasing the high voltage divider turns ratio will increase

brown-out protection voltage.

3.6 FB – Output Voltage / Current Feedback

The 88EM8080/88EM8081 has an internal current loop and output voltage/current loop to

implement the PFC and the output voltage/current regulating function. FB pin is the inverting input of

a voltage error amplifier with 2.5 volts as the internal refe rence vo ltage. For steady state operation

100% of required output voltage/current is scaled to 2.5V at the feedba ck pin by exte rnal circuitry.

For output current regulation, the much smaller voltage across the load current sensing resistor

could be amplified to be 2.5 V and then applied to the FB pin.

During startup, when FB pin is below 87.5% of the reference voltage, the PFC controller operates in

soft-start mode. The internal voltage error amplifier switches over to normal regulation phase once

the FB pin voltage reaches 87.5% of the reference value.

3.6.1 FB – Over Voltage Protection (OVP)

Over voltage protection is implemented through the FB pin. When th e FB pi n vol tage exceeds

VFB_OVP threshold voltage (refer to Table 4, Electrical Characteristics, on page 16), the IC is

switched off and no PWM output is available at SW pin of the IC.

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3.6.2 FB – Regulation

3.6.2.1 Output Current Regulation - Isolated Output

The general application for 88EM80 80/88EM8081 is for LED current control. Th e LED current is

passed through a series sense resistor and the voltage across that resistor is proportional to the

LED current. This sense resistor needs to be very small to limit the power dissipation in the resistor.

The sensed voltage is then amplified to have 2.5V at the full load current. It is applied to the TL431

type of device where the error voltage between the amplified voltage and TL431 device reference

(2.5V) is amplified. An optocoupler can be used to pass the error information to the feedback pin FB

on the primary side. In addition the primary current is sensed and the average current is adjusted to

be sinusoidal (in phase with AC input Voltage). The amplitude of the primary current is adjusted to

make the secondary LED current constant at the desired level. Because this is a single stage PFC

there will be second harmonic ripple at the output. Output capacitors are added to reduce the output

second harmonic ripple and also the high frequency switching ripple. The proportional and integral

compensation within the IC make the system stable. The over voltage protection at the output can

be achieved by clamping the output of TL431.

It is well known that CTR of an optocoupler varies with temperature and there is a CTR variation

among different units of the same optocoupler. An NTC circuit can be designed to help reduce the

effect of variation of CTR. The entire circuit design of the NTC circuit is provided in Section 5.3.5.

It is important to note that the IC has internal compensation for the loop stability.

3.6.2.2 Output Current Regulation - Non-isolated Output

The application is similar to the isolated example (Section 3.6.2.1) except there is no opto coupler.

The LED current is passed through a series sense resistor and the voltage across that resistor is

proportional to the LED current. This sense resistor needs to be very small to limit the power

dissipation in the resistor. The sensed voltage is then amplified to be 2.5V at the full load current. To

reduce the number of components the amplifier can be eliminated. In this case, a higher valued

sense resister should be used to get the sense voltage equal to 2.5V at full load. It is to be noted that

this will reduce the over all efficiency of the LED driver.

To have over voltage protection, the output voltage also can be sensed and diode or'ed to the output

of the current sensing circuit. Initially voltage loop takes over because the LED load needs a

minimum voltage to turn on. The voltage from the current sensing side is designed to be higher than

the voltage from voltage sensing diode during normal operation. Also the voltage sensing helps to

limit the output voltage, if one of the LEDs becomes open for any reason. The proportional and

integral compensation within the IC make the system stable.

3.6.2.3 Output Voltage Regulation - Isolated Output

The output voltage is sensed through a divider resistor and a TL431 type of device can be used to

amplify the error voltage from a reference voltage. An optocoupler can be used to pass the error

information to the feedback pin FB on the primary side for isolating the output. In addition, the

primary current is sensed and the average current is adjusted to be sinusoidal (in phase with AC

input Voltage). The amplitude of the primary current is adjusted to make the secondary voltage

constant at the desired level. Because this is a single stage PFC there will be second harmonic

ripple at the output. Output capacitors are added to reduce the output second harmonic ripple and

also the high frequency switching ripple. The proportional and integral compensation within the IC

make the system stable. The over voltage protection at the output can be achieved by clamping the

output of TL431.

It is well known that Current Transfer Ra tio (CTR) of an optocoupler varies with te mperature and

there is also a CTR variation among different units of the same optocoupler. An NTC circuit can be

designed to help reduce the effect of variation of CTR.

Functional Description

ISNS – Current Sensing / Over Current Protection

August 27, 2010, 2.00 Document Classification: Proprietary Page 23

It is important to note that the IC has internal compensation for the loop stability. There is no need for

external compensation.

3.6.2.4 Output Voltage Regulation - Non-isolated Output

When non-isolated, an opto-isolator is not necessary. The output voltage is sensed through the

output divider and the output of the divider is connected directly to the feedback pin FB. The IC then

controls the output voltage in the same way as for the isolated case. It is important to note that the IC

has internal compensation for the loop stability.

3.7 ISNS – Current Sensing / Over Current Protection

3.7.1 ISNS – Peak Current Sensing

The 88EM8080/88EM8081 LED driver provides power factor correction (PFC) in addition to

providing regulation. Regarding the PFC function, the average input current is varied to be

proportional to the input voltage. This way the average input current will be sinusoidal. This input

current is the same as the primary MOSFET current in a flyback circuit. Therefore, the IC can sense

the MOSFET current and then use average current mode control to implement the PFC function.

The voltage across the resistor in series with MOSFET (connected between MOSFET source pin

and bridge diode negative DC terminal) is used as primary current sensing signal. The primary

MOSFET source pin is grounded to apply a PWM si gnal between the gate and the source. The

current sense signal in series MOSFET source therefore becomes negative with respect to ground.

The IC uses this negative signal for input current control to provide the PFC function.

3.7.2 ISNS – Average Current Mode Control

The voltage across the primary current sense resistor is proportional to the peak value of switching

current. An RC filter can be used to provide the average current. The output of the RC filter is then

applied to ISNS pin. The internal current loop adjusts the duty cycle so that average current is

sinusoidal. The amplitude of the sinusoidal current is adjusted by the e xternal vol tage /current loop to

achieve constant output load voltage/current.

3.7.3 ISNS – Adaptive Over Current Protection

The average current signal at the output of the RC filter is also used for over current protection. The

IC has an internal current comparator with four different internal thre sholds for current protection on

ISNS pin as the input voltage signal varies. The input current varies in versely with the AC input

voltage. There are four different OCP thresholds at four different input voltage ranges. The different

thresholds; VIOVER_TH1, VIOVER_TH2, VIOVER_TH3 and VIOVER_TH4 are detailed in Table 4 , Ele c t r ical

Characteristics, on page 16. With these four adaptive over current protection steps the IC provides

almost constant power protection over the entire AC input voltage range.

3.7.4 OCP – Cycle by Cycle Over Current Protection

The voltage across the primary current sense resistor is proportional to the peak value of switching

current. This voltage can be used for cycle by cycle over current protection by the OCP pin. When

the OCP pin is pulled low the IC will shut down and there is no switched output signal at SW pin.

88EM8080/88EM8081

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3.8 Mixed Modes of Operation

The 88EM8080/88EM8081 controller operates in Continuous Conduction Mode (CCM) or

Discontinuous Mode (DCM) modes of operation. The transformer primary inductance and the load

determine the modes of operation. The CCM mode will have lower pe ak current than the

discontinuous mode of operation. At high power levels CCM is recomme nded because of reduction

of copper losses in the transformer and also the conduction losses in the primary MOSFET. In

addition CCM could reduce the input filter size. DCM mode may be recommended at lower power

levels to reduce the turn-on switching losses and the Primary FET losses due to reverse recovery

time and charge of the output diode.

3.9 Compensation and Adaptive Control Loop

The LED current control is a feedback control system. The bandwidth of the voltage loop for the

single stage LED feedback control system has to be much less than twice the line frequency to

provide a high power factor and low THD. The entire feedback system needs to be designed for high

power factor and low THD at low line (90-132VAC) and high line (180-264VAC). Marvell has an

internal proportional and integra l gain control feature for the voltage loop due to Marvell's DSP

Control Technology. This means by sensing the input voltage, the IC sets PI control automatically to

change the bandwidth for different AC input line ranges. This innovative adaptive feature will help

achieve low THD and high power factor at all lines and loads. Because of this proporti onal and

integral control within the IC, no external compensation is required for non-isolated outputs. Minimal

external compensation is required for isolated outputs mainly for the compensation on the error

amplifier (TL431) at the secondary side. This compensation network provides enough attenuation at

120Hz so that the second harmonic ripple voltage from the sensed current signal is attenuated and

not amplified.

3.10 Over Temperature Protection

The 88EM8080/88EM8081 IC has an internal over temperature sensin g ci rcui t. On over

temperature, the fault detection signal shuts off the PWM switching output at the SW pin.

Functional Characteristics

VDD Characteristics

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4Functional Characteristics

The following applies unless otherwise noted: VIN = 60Hz half-w ave sinusoidal from 0V to the peak

voltage (VPK) given in the test conditions of each grap h . TA = 25°C.

All measurement readings are typical.

4.1 VDD Characteristics

Figure 4: IDD Quiescent (IDD_QST) vs. VDD

Test Conditions:

VIN = 0V

FSW = 118kHz

VFB = 0V

CGate = 1nF

V_Isns = 0V

Figure 5a: IDD vs. VDD (VDD_ON)Figure 5b: IDD vs. VDD (VDD_ON)

Test Conditions:

VIN = 0V

FSW = 118kHz

VFB = 0V

CGate = 1nF

V_Isns = 0V

Test Conditions:

VIN = 0V

FSW = 118kHz

VFB = 2.4V

CGate = 1nF

V_Isns = 0V

100

024681012

VDD (V)

IDD (μA)

0246810121416

VDD ( V)

IDD (mA)

VDD Fal ling

VDD Ris ing

0246810121416

VDD (V)

IDD (mA)

VDD Fal ling

VDD Ris ing

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Figure 6a: IDD Operation (IDD_OP) vs.

Temperature Figure 6b: IDD Operation (IDD_OP) vs.

Temperature

Test Conditions:

VDD = 12V

VIN = 0V

FSW = 118kHz

VFB = 0V

CGate = 1nF

V_Isns = 0V

Test Conditions:

VDD = 12V

VIN = 0V

FSW = 118kHz

VFB = 2.4V

CGate = 1nF

V_Isns = 0V

Figure 7: VDD On/Off vs. Temperature

Test Conditions:

VIN = 0V

FSW = 118kHz

FFB = 2.4V

CGate = 1nF

V_Isns = 0V

-40-20020406080

Temperature (°C)

I DD ( mA)

-40-20 0 20406080

Temperature (°C)

I DD (m A)

-40-200 20406080

Temperature (C)

VDD (V)

Off

Hysteresis

Functional Characteristics

VFB Characteristics for Over Voltage Protection

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4.2 VFB Characteristics for Over Voltage Protection

Figure 8: IDD vs. VFB Figure 9: VFB_OVP vs. Temp era tur e

Test Conditions:

VDD = 12V

VIN = 0V

FSW = 118kHz

CGate = 1nF

V_Isns = 0V

Test Conditions:

VDD = 12V

VIN = 0V

FSW = 118kHz

CGate = 1nF

V_Isns = 0V

Figure 10: VFB_OVP Hysteresis vs. Temp era ture Figure 11: VFB_OVP_LATCH vs. Temperatu re

Test Conditions:

VDD = 12V

VIN = 0V

FSW = 118kHz

CGate = 1nF

V_Isns = 0V

Test Conditions: FSW = 118kHz

VDD = 12V CGate = 1nF

VIN = 0V V_Isns = 0V

3.0

3.5

4.0

4.5

5.0

5.5

2.0 2.2 2.4 2.6 2.8 3.0 3.2

VFB (V)

IDD (mA)

VFB Down

VFB Up

-40-200 20406080

Temperature (C)

VFB (V)

OVP_Threshold

Recover Threshold

OVP Threshold

Recovery Threshold

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

-40-20020406080

Temperature (C)

VFB (V)

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

-40 -20 0 20 40 60 80

Temperature (°C)

VFB (V)

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4.3 Switching Frequency Characteristics

Figure 12: Normal Regulation Reference

(VFB_REG) vs. Temperature

Test Conditions:

VDD = 12V

VIN = 2V

FSW = 118kHz

CGate = 1nF

V_Isns = 0V

Figure 13: Switching Frequency vs. Temperature

Test Conditions:

VDD = 12V

VIN = 0V

VFB = 2.4V

CGate = 1nF

V_Isns = 0V

2.0

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

2.9

3.0

-40-200 20406080

Te m perature (°C)

VFB (V)

100

120

140

-40 -20 0 20 40 60 80

T emperature ( ° C)

Frequency (kHz)

FSW (8 081)

FSW (8 080)

Functional Characteristics

Over Current Threshold Characteristics

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4.4 Over Current Threshold Characteristics

Figure 14: Over Current (VIOVER) vs. Input Volt age

VIN Peak Value)

Test Conditions:

VDD = 12V

FSW = 118kHz

VFB = 2.4V

CGate = 1nF

V_Isns = 0V

0.00

0.05

0.10

0.15

0.20

0.25

0.30

0.35

0.40

0.45

012345

VIN (V)

VCS (V)

Figure 15: Over Current (VIOVER) vs. Temperature

Test Conditions:

VDD = 12V

FSW = 118kHz

VFB = 2.4V

CGate = 1nF

V_Isns = 0V

100

150

200

250

300

350

400

450

-40-20020406080

Temperature ( C)

VCS (V)

= 1.5V

= 3V

= 2.25V

= 3.7V

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Design and Applications Information

Overview

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5Design and Applications Information

5.1 Overview

The 88EM8080/88EM8081 is a PWM controller for LED applications with PFC. Flyback topology is

used to simplify the two stage (front-end PFC and output stage) design to a single stage that

includes Power Factor Correction (PFC) and regulati on of the output. Compared to the two stage

structure, a single stage with PFC is a more cost effective solution for LED lighting applications. The

following section provides guidelines for the application design, component selection, and board

layout in order to improve LED application performance with PFC based on the flyback topology.

The 88EM8080/88EM8081 IC control algorithm uses Average Current Mode Control for power factor

correction applications with low harmonic distortion and good noise immunity. The IC senses the

output current and forces it to follow the reference LED current matching the design requirements.

The chip also senses the primary current and forces the average sign al of the primar y current to

follow the sinusoidal current reference, therefore achieving power factor correction. This is possible

because the bandwidth of the outer current/voltage loop is much smaller than twice the line

frequency. This IC implements the adaptive loop control so that the LED power supply achieves high

power factor even under high input voltage and low load conditions. The device also provides strong

gate drive capability of 1.2A (typical).

There are four analog input signals and one lo gic output signal for the 88EM8080/88EM8081

controller. Each signal is briefly described below.

Input voltage signal at VIN pin is a half sinusoidal waveform. It is fed into the VIN pin through the

input voltage resistor divider. This is for the line frequency zero-cross detection for PFC. Using

the zero-crossing detector, the IC can predict the input sinusoidal waveform. The design of the

input voltage divider and the design equations for the prediction of input sinusoidal voltage are

described in the following Section 5.2.T he signal at the VIN pin also provides brown-out

protection because of the minimum VIN voltage requireme nt. This brown-out protection is

described in Section 5.2.1.

Input signal at FB pin is the output feedback signal through the output voltage resistor divider

plus the compensation. For LED current control, LED current is sensed and fed back to FB pin.

An optocoupler can be used for isolation, if necessary . This signal helps to obtain output voltage

regulation.

Input current sensing signal is derived from the sensing resistor to the ISN S pin. This is fo r the

average current mode control to achieve a good sinusoidal current waveform and hig h power

factor. This average current signal is also used for over current protection.

Input over current protection (OCP) signal is a logic signal instead of an analog signal. It is used

to shut down the output at the SW pin when pulled low for cycle by cycle current limiting.

The output signal from the 88EM8080/88EM80 81 is the PWM gate drive signal from the SW

pin. The switching frequency on the 88EM8080 device is fixed to 60kHz while the 88EM8081 is

fixed to 120kHz. Refer to the 88EM8080/88EM8081 Application Note located on Marvell.com

for more application details.

88EM8080/88EM8081

Datasheet

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The advantages of this device operating under Mixed Mode Control when compared to Critical

Transition Mode are shown in Table 6.

5.2 Input Voltage Resistor Divider on VIN Pin

Accurate peak detection signal and zero-cross det ection for regenerating the input sinusoidal

voltage is the most important issue for a proper curre nt shaping and total harmonic distortion (THD)

improvement. A peak detecting pulse is generated after comparing the VIN sinusoidal signal to an

internal threshold reference of 0.72V (typical) as shown in Figure 17. If the threshold reference is too

high, near the peak area, the calculation may loose accuracy because of the low slope. On the other

hand, if the threshold reference is too low , there could be an error on zero-cross detection due to the

possible distortions near the zero-crossing. For a universal input voltage range (85Vac~270Vac) the

optimum accuracy would be achieved if the threshold level is around 30 of the line cycle.

Figure 16: Internal Block for Zero-cross Detection, Brown-out Protection

Table 6: Comparison between Critical Transition Mode and Mixed Mode Controls

Critical Transition Mode Control Mixed Mode – CCM/DCM Control

High peak current on switch Low peak current on switch

High diode peak current at secondary side Low diode peak current at secondary side

Variable switching frequency with lowest

switching frequency at peak input voltage Fixed switching frequency

Big transformer Small transformer

Diffi c ult to achieve high power Easy to achieve high power

High cost Low cost

VIN

88EM8080/8081

Peak

detecting

pulse

Phase ( )

Zero

Crossing

Power Limit

Threshold

Selection

Brown-Out

Protection

Predictive

Sinusoidal

AC Voltage

DCin

line_pk

Design and Applications Information

Input Voltage Resistor Divider o n VIN Pin

August 27, 2010, 2.00 Document Classification: Proprietary Page 33

The values for the sensing resistors Ra, Rb, and Rc in Figure 16 are selected to get proper sinusoidal

AC voltage, under voltage lockout, and peak voltage detection. If the values are too small there will

be higher power loss and if they are too big there might be picku p noise on the VIN signal. The

recommended values are shown in the following equation:

Equation (1)

Where Ra + Rb is recommended to be 1.8MΩ and Rc is selected as 18kΩ. Knowing (Ra + Rb), Ra

and Rb can be designed.

For this input voltage resistor divider, the appropriate combination based on the voltage / power

rating of the resistors should also be considered.

Figure 17: Peak Detecting Signal for Predictive Sinusoidal AC Voltage

As can be seen in Figure 16, the internal peak detecting circuit generates peak detecting pulse

through the inside comparator which has a threshold voltage of 0.72V and external AC sensing

resistors of Ra, Rb and Rc. This pulse is processed in the DSP core to calculate the mid-point (peak

point) and the zero-crossing point of the sinusoidal waveform. The phase angle of

is calculated

using the widths (M and N) of the high and low signals.

Equation (2)

Equation (3)

Equation (4)

Peak value of the sinusoidal waveform is calculated by the following equation:

Equation (5)

5.2.1 Brown-out Protection

The signal that appears on the VIN pin is a half sinusoidal voltage waveform and its peak value has

to be higher than 0.72V for normal operation. Whenever the VIN voltage is less than 0.72V at the

peak value, it is considered as a Brown-out condition. During the brown-out condition, the IC

generates a low duty cycle of 6% to protect the system. For the design shown in equation (1) the

brown-out protection occurs at the AC input of 50V RMS (72V peak, VIN=0.72V). To adjust the

brown-out protection point, the resistance value of Ra, Rb and Rc can be changed.

RaRb

------------------ 100

---------1.8MΩ

18kΩ

-----------------

V (

) = Vline_pk x sin

Half line cycle

NMN

Vline_pk

Half line cycle

Peak detecting Pulse

line_pk

VVIN_BR = 0.72V (T yp.)

φφφ

Nπ2

–()=

Mπ2

+()=

MN–()4⁄=

Vline_pk V

()

sin()⁄=

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5.2.2 Layout Guidelines

It is recommended that a 0.1nF–10nF capacitor (Cc) is connected between VIN and ground for noise

immunity. The layout of Rb, Rc and Cc should be kept as close as possible to the VIN pin, as shown

in Figure 18 to reduce noise pickup. Ra should be kept as close as possible to the high voltage input.

Figure 18: Input Voltag e Resistor Divider Layout Guidelines

5.3 Output LED Current Control

The brightness and color of a LED are functions of LED current. A constant current source driver for

LED current therefore helps in control of brightness and color. The LED current is passed through a

current sense resistor and the voltage across the sense resistor is used as a feedback signal for

LED current control. Reference designs are presented in the following sections for isolated and

non-isolated outputs for the control of LED current using Marvell 88EM8080/88EM8081 IC.

OCP

VDD

VIN

ISNS

PGND

SGND

RcCc

Keep layout of Rb, Rc and Cc as

clo se as possibl e to VIN pin to

keep high nois e immu nization

88EM8080/81

Design and Applications Information

Output LED Current Control

August 27, 2010, 2.00 Document Classification: Proprietary Page 35

5.3.1 Non-isolated Output LED Current Control

Figure 19 shows a typical configuration for non-isolated output LED current control. LED current is

sensed by the resistor Rsen2. The voltage across Rsen2 is amplified by an amplifier U2. The output of

the operational amplifier is connected to FB pin through a diode D2. A voltage loop is also added for

voltage regulation at no load. The two feedback loops (output voltage and output current) are

implemented in an OR structure through D1 and D2.

During startup, the output voltage increases and must reach a certain level before th e LED current

can flow. The output voltage is fed back through the resistor divider (R1 and R2) and the diode D1.

R1 and R2 are designed to limit the output voltage during startup (with no LED current) and when the

LED string is open.

Figure 19: Non-Isolated Feedback Loop Schematic

88EM8080/81

OUT

sen2

LEDs

= 200k

88EM8080/88EM8081

Datasheet

Page 36 Document Classification: Proprietary August 27, 2010, 2.00

5.3.1.1 R1 and R2 Resistor Divider Design

The following equation can be used for the design of R1 and R2.

Equation (6)

Where VOUT_MAX is the output over voltage regulation point during starting or under a no load

condition, R1 and R2 are in kΩ, VD1 is the voltage drop of the diode D1 and VREF is the reference

voltage inside the 88EM8080/88EM8081 IC. The nominal value of VREF is 2.5V.

This equation takes into account of the internal leak age at FB pin. The leakage at the FB pin is

equivalent to a 200k Resistor. Because the forward current of diode D1 is less than 25mA, the

voltage drop VD1 is about 0.1V to 0.3V depending on the diode and the temperature of the diode. It

should be noted that under steady state conditions the current loop should be active and not the

voltage loop. Therefore care must be taken in selection of R2 to make sure that the voltage at the

cathode of D1 is less than the voltage at the cathode of D2 under steady state conditions.

5.3.1.2 RC Filter Design

In single stage PFC LED applications, the output voltage / current has twice the line frequency ripple

which may trigger the OVP function through the voltage at the FB pin. An RC filter (resistor R5 and

capacitor Ccp) can be embedded into the operational amplifier circuit for filtering this twic e the line

frequency ripple. The design of the ope rational amplifier circuit is described in the follo wing section.

5.3.1.3 Design of Operational Amplifier Circuit

The DC gain of the non-inverting amplifier ci rcuit is based on the following equation:

Equation (7)

However, the average current through the LED is controlled by the following equation:

Equation (8)

Where, IAVG is the average LED current, VD2 is the voltage drop on the diode D2 and KU2 is the DC

gain of the operational amplifier circuit. From Equation (8) the required KU2 can be determined.

R5 and R4 are then designed from Equation (7).

The cross over frequency of R5 and Ccp is selected well below 120Hz in order to attenuate twice the

line frequency ripple. The recommended value for this cross over frequency is around 10Hz.

Equation (9)

Knowing R5, Ccp can be calculated.

VOUT_MAX

--------------------------VD11

------1

------

⎝⎠

⎛⎞

–

------1

200

---------

-------------------------------------------------------------------VREF

KU21R5

------

⎝⎠

⎛⎞

IAVG Rsen2

×KU2

()VD2

–×VREF

2πR5Ccp

----------------------10=

Design and Applications Information

Output LED Current Control

August 27, 2010, 2.00 Document Classification: Proprietary Page 37

5.3.2 Low-Cost LED Current Control with Non-isolated Output

One can have a cost effective design by not having the operational amplifier in the output current

feedback loop. The circuit is shown in Figure 20.

Figure 20: Low-cost, Non-isolated LED Current Control

In this case, the voltage across Rsen2 is directly connected to VFB pin through the filter R3 and CCP

and the diode D2 but without the operational amplifier U2. Also it should be noted that Rsen2 has to

be selected so that the voltage across it is higher than 2.5V (by a diode drop) under steady state

conditions. Because of this condition, Rsen2 will be of a higher valu e than when the operational

amplifier is present and there will be a significant power loss in the Rsen2 resistor. The ef ficiency of

this LED driver circuit will be lower than that of application circuit in Fig ure 19, Non-Isolated

Feedback Loop Schematic, on page 35.

The following equation can be used for the design of R3 in addition to equation 7.

Equation (10)

Where, IAVG is the average LED current, VD2 is the voltage drop on the diode D2, VREF is the

internal reference of the 88EM8080/88EM8081 IC, and resistors R3 and R4 are in kΩ.

88EM8080/81

OUT

sen2

LEDs

= 200k

IAVG Rsen2

×()VD2

–VREF 1R3

------R3

200

---------

⎝⎠

⎛⎞

88EM8080/88EM8081

Datasheet

Page 38 Document Classification: Proprietary August 27, 2010, 2.00

The following equation can be used for the design of R1 and R2.

Equation (11)

Where, VOUT_MAX is the maximum outp ut voltage, VD1 is the voltage drop on the diode D1, and

resistors R1, R2 and R4 are in kΩ.

A reference design for a cost effective non-isolated LED driver is presen ted in Section 5.7.

5.3.3 LED Current Control with Isolated Output

The typical isolated output current control is shown in Figure 21.

Figure 21: Isolated LED Current Control

Figure 21 shows a typical configuration for LED current control when the output is isolated from the

AC input. The current through the LED also passes through the resistor R8 and the voltage across

R8 is used for output current sensing and for LED current control. In order to reduce the power

dissipation in the current sensing resistor, R8 could be selected as a low value such as 0.1Ω. The

voltage across R8 at 500mA steady state current is 50mV.

This current sense voltage across R8 is amplified by the non-inverting amplifier U2 and is applied to

the inverting input of the U1 circuit. T ypically, the TL431 IC is used for U1. U2 is necessary to amplify

the sense voltage to 2.5V at the steady state LED regulated current. This is because the

non-inverting input of U1 has a reference voltage of 2.5V nominal. Capici tor C15 and resistor R2

VOUT_MAX VREF 1R1

200

---------R1

------R1

------

+++

⎝⎠

⎛⎞

VD11R1

------

⎝⎠

⎛⎞

VIN

C14

FB ISNS

OCP

SGND

PGND

VDD

88EM8081

R19

R11

VDD

HVDC

C6 Q1

D9C11 C13

R23

LE D +

LED -

R8R3R1

TS321LT

PC1A

FOD817A

R22

R21

VREF

TL431

OUT

Input Voltage from

Rectifier Bridge

EOPTO

R12

R7 C8

OUT_U2

C15

Design and Applications Information

Output LED Current Control

August 27, 2010, 2.00 Document Classification: Proprietary Page 39

provide attinuation for 120Hz ripple. The U1 device is used to generate an error voltage of VC at the

output after comparing the output voltage of U2 to the internal reference voltage of U1.

An optocoupler is connected between the output (LED+) and the U1 error voltage output through a

resistor R23. The current through the optocoupler is a function of error voltage at the output of U1

(TL431) and is varied until the output voltage of U2 is equal to the reference voltage of U1.

The current through the opto-transistor and resistor R11 is proportional to the opto-diode current by

a factor of current transfer ratio of the optocoupler. The voltage across R11 is applied as input to FB

pin. Therefore, the voltage at the FB pin is a function of the error voltage output of U1.The voltage at

the FB pin controls the duty cycle of the drive signal to the external MOSFET Q1. The switching

current of Q1 is sensed by the voltage across resistor R5. At steady state conditions the FB pin

voltage will be 2.5V which is equal to the nominal value of internal reference for

88EM8080/88EM8081 IC.

The voltage across resistor R5 is filtered and the filtered voltage is proportional to the average

current. The duty cycle is varied so that the average of the input current through the ISNS pin

follows the AC Input voltage. The amplitude of the AC sinusoidal input current is varied to adjust the

output voltage, therefore adjusting the LED current until the output voltage of U2 equals the

reference voltage of U1 (2.5V, typical).

During startup, the FB pin voltage is zero and the duty cycle at the SW pin is 6% (typical). Soft start

is provided until feedback voltage reaches 2.1V which is 87.5% of the reference voltage of U3 (2.5V,

typical). During the time the voltage at FB pin rises to 2.1V, the internal current reference increases

linearly. The internal current reference determines how fast the power is delivered to the secondary

side in addition to other circuit parameters. Therefore, the soft start time is th e du ra ti on for internal

current reference to raise linearly. When the FB pin reaches 2.1V, the internal feedback loop starts

closed loop operation to eventually reach steady state. It is to be noted that LEDs will not conduct

until the voltage across them reaches a minimal value. This means the LED load is open circuited

during startup. The voltage across the output capacitors C11 and C13 is zero initially at starting. The

output capacitors C11 and C13 will get charged rather quickly and the output voltage could

overshoot the steady state value. During starting condition when LEDs are not conducting or if the

LED string is open circuited, the output voltage across the LED string may go higher than the normal

steady state value and the zener D6 will be conducting. The output voltage of U1 is equal to the

zener voltage. Once the LEDs starts conducting the output voltage of U1 starts decreasing and will

come to a steady state value at which point the voltage across D6 will be much lower than the zener

conduction voltage.

If the ambient temperature is increased, the CTR of the optocoupler will become less, then more

current through the optodiod e becomes necessary for LED current regulation. This means the

output voltage of U1 (TL431) will be lower than the steady state voltage at the lower ambient. If the

ambient is decreased, U1 voltage will be higher than the steady state voltage at the higher ambient.

The design of the U1 circuit should be such that the zener diod e D6 should not conduct during

normal operation at any temperature. In addition, the output voltage of U1 cannot go below the

reference voltage (2.5V for TL431) for any reason during steady state operation.

88EM8080/88EM8081

Datasheet

Page 40 Document Classification: Proprietary August 27, 2010, 2.00

5.3.4 Isolated LED Current Control - Circuit Design

The relation between output current signal and the reference voltage of U1 is provided by the

following equation:

Equation (12)

Where VREFU1 is the U1 (TL431) reference voltage and is equal to 2.5V nominal, ILEDavg is the

average current through the LED.

R8 is selected to be a low value so that the power dissipation is minimum. For the reference design it

is 0.1Ω.

One can select R2 and R3 from the above equation after selecting R8 since VREFU1 is equal to 2.5V.

C11 and C13 are selected so that the second harmonic ripp le at the output is at a desired level.

The Zener diode D1 is selected to be 4.7V so that the voltage at the FB pin cannot exceed the rated

maximum voltage for the FB pin.

The output voltage of U1 error amplifier (VC), and the secondary side optocoupler diode current are

related by the following equation:

Equation (13)

Where VFD is the forward vo ltage drop of op tocoupler diode and is abo ut 1V.

VC is also related to the FB pin voltage or the reference voltage of U3 by the following equation:

Equation (14)

Where VFB_REG is the reference voltage of U3 and CTR is the current transfer rati o of optocoupler.

At steady state no load condition, the secondary side error amplifier enters into positive saturation

status because of no current feedback signal. Therefore, the output voltage VC increases to the

maximum clamp voltage VZD6 as pointed out in the previous section. VZD6 should be higher than

normal operation voltage of VC to keep enough margin. Then the no load output voltage will increase

until the FB pin voltage reaches 2.5V. The following equation can be used to calculate the no load

output voltage.

Equation (15)

VO_NOLOAD is also equal to the maximum voltage when the LED string is broken or when the sense

line is open.

The following equation is provided to calculate the output over voltage protection point.

Equation (16)

VREFU1R2R3

------------------ ILEDavg

×R8

×=

Isf VOVFD

–VC

–

R23

------------------------------------

VOVFD

–VC

–

R23

------------------------------------CTR R11 VFB_REG

=××

VO_NOLOAD VFD

–VZD6

–

R23

---------------------------------------------------------------CTR R11 VFB_REG

=××

VO_OVP VFD

–VZD6

–

R23

-----------------------------------------------------CTR R11 VFB_OVP

=××

Design and Applications Information

Output LED Current Control

August 27, 2010, 2.00 Document Classification: Proprietary Page 41

At OVP condition the error amplifier output voltage increases to VZD6. It is pointed out that the

primary FB pin voltage reaches the OVP threshold VFB_OVP (which is about 3V) when the output

voltage increases to OVP level. This OVP condition can occur with a low output capacitance and

high output ripple.

The steady state output at no load can also be calculated using the following equation which

depends on the normal operation voltage VC of the U1 (TL431) error amplifier at nominal full load

condition and VZD6.

Equation (17)

It is important to note that VC varies with temperature and will also vary from unit to unit of the

optocoupler.

The transfer function of u1 (TL431) amplifier circuit is:

Equation (18)

Where VOUT_U2 is the output voltage of the amplifier U2 as shown in Figure 21. The values of C1,

R21 and R22 are selected in such a manner that there is enough DC gain for the average current

feedback signal. At the same time there should be enough attenuation at 120Hz so that the second

harmonic ripple voltage from the sensed current signal is attenuated and not amplified. Therefore,

the low frequency zero should be placed far below twice the line frequency (<20Hz).

5.3.4.1 Design of Operational Amplifier Circuit

The DC gain of the non-inverting amplifier ci rcuit is based on the following equation:

Equation (19)

However, the average current through the LED is controlled by the following equation:

Equation (20)

Where, IAVG is the average LED current and KU2 is the DC gain of the operational amplifier circuit.

From Equation (20) the required KU2 can be determined.

R2 and R3 are then designed from Equation (19).

The cross over frequency of R2 and C15 is selected well below 120Hz. The recommended value for

this cross over frequency is around 10Hz.

Equation (21)

Knowing R2, C15 can be calculated.

VO_NOLOAD VOVZD6VC

–+()=

Hs() VCs()

VOUT_U2 s()

---------------------------- 1sC

1R21

××+

×C1

---------------------------------------

KU21R2

------

⎝⎠

⎛⎞

IAVG R8

×KU2

()×VREF

2πR2C15

----------------------10=

88EM8080/88EM8081

Datasheet

Page 42 Document Classification: Proprietary August 27, 2010, 2.00

Gain of the operational amplifier circuit at any frequency ‘f’ is given by the following equation:

Equation (22)

Where:

Equation (23)

Equation (24)

Equation (25)

Equation (22) can be used to dete rmine the attenuation at 120Hz from the DC gain.

KU2f() 1R2

------

⎝⎠

⎛⎞

1A2B2

×+

1C2B2

×+

--------------------------------

×=

AR2R3

R2R3

------------------ C15

×=

B2π× f×=

2C15

×=

Design and Applications Information

Output LED Current Control

August 27, 2010, 2.00 Document Classification: Proprietary Page 43

5.3.5 NTC Compensation Circuit Design

The secondary side error amplifier output voltage VC varies between the maximum value VZD6 and

the minimum value 2.5V (U1 (TL431) minimum supply voltage). From Equation (14) it can been

seen that the variation of VC depends on the tolerance of R11 and R23 value, VFB_REG reference

voltage and CTR value of optocoupler.

But the CTR value of optocoupler has a wide vari at ion from unit to unit and also with temperature.

For example, the relative CTR of FOD817 form Fairchild changes from 105% to 55% with ambient

temperature from 0ºC to 110ºC. If am bient temperature increases, the CTR of optocoupler

decreases, which results in a lower value for VC. When ambient temperature is over 110ºC, the VC

voltage could reach the minimum limit value of 2.5V. Then the power system will be out of regulation.

It is pointed out that 0ºC and 110ºC are selected for illustration only.

At 0ºC VC would increase from the value at room temperature. If it is high enough zener D6 would

conduct and the power system is out of regulation.

In order to keep VC at a reasonable range (below zener D6 V oltage and above 2.5V with a margin) a

NTC compensation circuit, shown in Figure 22, is introduced. An actual reference design is shown

for illustration of NTC compensation. This compensation circuit is composed of an NTC resistor

NTC1 and resistors R10 and R23 (instead of resistor R23 only).

Figure 22: Isolated LED Current Control with NTC Compensation

VIN

C14

0.1μF

FB ISNS

OCP

SGND

PGND

VDD

88EM8081

0.1μF

R19

20.5Ω

1/8W

R11

1.24k

4.7V

500mW

VDD

22μF

25V

HVDC

1.0Ω

1/4W

100pF Q1

650V

4.5A

STPS3150RL

C11

330μF

35V

C13

330μF

35V

NTC1

33k

R23

3.01k

R10

4.02k

LE D +

LED -

1.0μF

35V

4.99k

0.1Ω

4.99k

243k

TS321LT

PC1A

FOD817A

15V

500mW

R22

10k

R21

4.99k

1.0μF

50V

VREF

TL431

+25.0 VDC, 500mA (nominal)

Input Voltage from

Rectifier Bridge

EOPTO

0.047μF

50V

187Ω

R12

200Ω

P/O PC1A

C15

0.047μF

88EM8080/88EM8081

Datasheet

Page 44 Document Classification: Proprietary August 27, 2010, 2.00

5.3.5.1 Design Equations

With NTC compensation circuit, the total equivalent resistance decreases when ambien t

temperature increases and will compensate for the variation of the CTR with temperature and

maintain VC at a narrow range. Similar effect takes place when the ambient temperature is

decreased.

The following two equations at 25ºC and 110 ºC ambient temperature cond ition are used for

selection of resistors R10 and R23 values.

Equation (26)

Equation (27)

Where, RNTC1_25 and RNTC1_110 are the resistance value of NTC1 at 25ºC and 110ºC ambient

temperature. CTR_25 and CTR_110 are the CTR values of optocoupler at 25ºC and 110ºC ambient

temperature and VC_25 and VC_110 are the actual output voltages of U1 amplifier at 25ºC and 110ºC

ambient te mp eratures.

In the following, VC is assumed to be constant at 25ºC and 100ºC for the selection of resistors R10

and R23. Once the resistors are selected the variation of VC at 25ºC and 100ºC can be calculated.

Equation (28)

Equation (29)

Equation (30)

Equation (31)

Equation (32)

Equation (33)

Equation (34)

VOVFD

–VC_25

–

R23

RNTC1_25 R10

-------------------------------------

----------------------------------------------------CTR_25 R11 VFB_REF

=××

VOVFD

–VC_110

–

R23

RNTC1_110 R10

---------------------------------------

------------------------------------------------------ CTR_110 R11 VFB_REF

=××

VC_25 VC_110 VC

AVFB_REF

R11 VOVFD

–VC

–()×

-------------------------------------------------------

BCTR_110 CTR_25–=

NTC1_25 RNTC1_110

–=

EBAD×+=

F4E×BR

NTC1_25

×RNTC1_110

××=

Design and Applications Information

Output LED Current Control

August 27, 2010, 2.00 Document Classification: Proprietary Page 45

R10 can then be calculated from the following equation:

Equation (35)

R23 can then be calculated from the following equation:

Equation (36)

Marvell provides an Excel spread sheet tool for the required NT C compensation circuit selection to

meet design requirements. The selection of a different value for NTC part, will provide diffent values

for R10 and R23. The Excel spread sheet tool will help calculate variation of VC with temperature.

The designer can then select a suitable NTC value to minimize the variation of VC. Figure 23 shows

the variation of VC with temperature for a 25V, 500mA output design with 33K NTC part. It is evident

that the variation of VC voltage is small when ambient temperature changes from 0ºC to 120ºC. This

clearly shows that the NTC compensation circuit can be used effectively to compensate for the

tolerance of the components and also for the wider variation of CTR of the optocoupler . A reference

design for an isolated LED driver is presented in Section 5.8.

Figure 23: The Error Amplifier Output Voltage (VC) vs. Temperature

R10 BC–BC()

2F–+ 2E

------------------------------------------------------------------------

23 CTR_25

---------------------R10 RNTC1_25

R10 RNTC1_25

-------------------------------------

–=

0 102030405060708090100110120

T emperatur e ( ° C)

Volt age ( V )

88EM8080/88EM8081

Datasheet

Page 46 Document Classification: Proprietary August 27, 2010, 2.00

5.3.5.2 Simplified Engineering Design Procedure

In the previous section, by assuming VC_25 = VC_110, values for resistors R23 and R10 are

estimated by solving the two simulataneous equations(Equation (26) and Equation (27)).

The simplified procedure can be used to get the estimates of R23 and R10. The steps are as

follows.

1. Knowing the zener value of D6, one can estimate VC_25. For example, if D6 is a 15V zener, one

can choose 11 Volts for VC_25. This provides 4V nominal margin for the zener not to conduct.

2. Once VC_25 is known, Equation (26) is solved to get estimate for (RC) =

3. Assuming and to get the value of R23 and R10.

4. An NTC can be selected such that, RNTC1_25 is about 5 to 10 times the value of R10 and

RNTC1_110 is about 1/5 to 1/10 the value of R10.

5. VC_110 can then be calculated from Equation (27).

6. VC_110 should be in the allowable range for the U1 (TL431) and no conduction for zener D6.

For this example, the voltage range for VC_110 should be around 5V to 10V. This will satisfy the

minimum requirement for VC (not less than 2.5V) with a margin.

7. This process can be repeated un ti l V C_110 is in the allowable range.

R23

RNTC1_25 R10

--------------------------------------

R23 RC

-------

R10 RC

-------

Design and Applications Information

Current Sensing an d Over Current Protecti on

August 27, 2010, 2.00 Document Classification: Proprietary Page 47

5.4 Current Sensing and Over Current Protection

5.4.1 Current Sensing Through ISNS Pin

The current sensing circuit is illustrated in Figure 24. The voltage drop on the current sense resistor

should be kept very small in order to reduce the power consumption on the sense resistor. In flyback

topology, the drain to source current flows through the tra nsformer primary, MOSFET and current

sense resistor (Rsen). The average current mode control single stage solution uses two signals: the

peak current signal to avoid the transformer saturation including a short circuit condition, and the

average current sense signal to achieve PFC operation. The voltage drop (Vsen) across resistor

(Rsen) represents the flyback peak current signal. The voltage of (VCS), after RCS and CCS low pass

filter, represents the average current signal of the primary side of the flyback converter.

Figure 24: Current Sensing Circuit

Drain

VDD

sen

VIN

sen

ISNS

SW SGND

CS1

sen

PGND

OUT

DCin

88EM8080/81

CS2

88EM8080/88EM8081

Datasheet

Page 48 Document Classification: Proprietary August 27, 2010, 2.00

The resistor (Rsen) should be designed as the example in Table 7 where Rsen is designed for a 60W

power supply.

Table 8 shows the reference value of the current sensing resistor for different input power levels. In

the practical design, the current sensing resistor value could be fine tuned arou nd the value shown

in the table based on the specification and the primary inductance of the flyback transformer.

5.4.2 Average Current Signal and Over Power Limitation

The peak current is sensed as the voltage across the sense resistor . To convert flyback peak current

into an average current signal, an RC filter is required as described in the previous secti on.

Figure 25 shows how the addition of the filter will result in an average current signal. This average

current signal, Vcs is fed back onto the ISNS pin and used to achieve a sinusoidal current waveform

by an internal current control loop. It is also used to achieve power limitation. The corner frequen cy

of the RC filter is recommended approximately 1/10~1/6 of the switching frequency. The

recommended value for Rcs1 is 187Ω, Rcs2 is 200Ω. Rcs1 and Rcs2 are used for the purpose of

blocking excessive negative and surge voltages. A single stage PFC operates at 120kHz (typical)

using the 88EM8081 device. Ccs is designed as 47nF which results in a corner frequency of 18kHz.

The corner frequency of the low pass filter is defined by the following equation;

Equation (37)

U3 is designed to perform over power limitation according to different over current thresholds as

shown in Table 4, Electrical Characteristi cs, on page 16. The adaptive over current and hence

adaptive over power protection feature is described in Section 3.7.3

Table 7: Current Sensing Circuit

Input Power Pin 60W

Minimum input voltage Vin_min 85V

Maximum average input current 1A

Over current threshold Zone 1 VIOVER_TH1 0.39V

Over current margin IMargin 30%

Current sensing resistor calculation 0.30Ω

Current sensing resistor selection Rsns 0.30Ω

Iin_max 2Pin

Vin_min

-----------------

×=

Rsns VIOVER_TH1

iin_max 1Iminarg

+()×

-----------------------------------------------------

Table 8: Current Sensing Resistor Selection Reference

Input Power (W) 10 30 60 120

Current Sensing Resistor (Ω) 1.0 - 2.0 0.50 - 0.70 0.25 - 0.35 0.12 - 0.15

fcorner 1

2πRcs1Ccs

--------------------------

Design and Applications Information

Current Sensing an d Over Current Protecti on

August 27, 2010, 2.00 Document Classification: Proprietary Page 49

Figure 25: Current Sensing and Over Cu rrent Protection Waveforms

5.4.3 Peak Current and Average Current Relationship

The relationship between the flyback peak and the average current signals is derived in this section.

Figure 25 explains this in detail.

The peak to peak ripple current through the Rsen resi stor is given by the following equation.

Equation (38)

The average current sensing signal across Rsen during the MOSF ET switching on time is...

Equation (39)

The average current sensing signal during the whole switching cycle can be calculated as

Equation (40)

Leading Edge Current

GND

P ower Li m i t OC P

VCS

VSEN VCS

avg

VSEN

avg

Switching Period

SEN

VCS

avg

VSEN

avg

ΔIins Vline D×

Lmfs

----------------------

Vsenavg Vsenpk

ΔIins

------------Rsen

×–=

Vcsavg Vsenavg D×=

88EM8080/88EM8081

Datasheet

Page 50 Document Classification: Proprietary August 27, 2010, 2.00

5.4.4 Cycle by Cycle Current Protection through OCP Pin

The voltage across Rsen and the OCP pin are used for cycle by cycle over current protection. This

protection helps to avoid the transformer saturation. A circuit consisting of an NPN transistor Q2 with

a low base to emitter parasitic capacitance is recommended for the desig n as shown in Figure 26.

The sensing voltage through Rsen should trigger and turn on the transistor Q2 during the over

current condition. Q2 then pulls the OCP pin to low and turns off the gate signal to the external

MOSFET.

For the design of the protection circuit a -2mV/°C (typical) temperature coefficient of the base to

emitter voltage of Q2 (Vbe) should be considered. The lowest base to emitter voltage will be set at

the junction temperature of 80°C.

Figure 26: Current Sensing and Cycle by Cycle Over Current Protection Circuit

At 80°C, the base to emitter voltage can be calcuated from the following equation

Equation (41)

The highest base to emitter voltage occurs when the junction temperature is -25°C.

Equation (42)

Drain

VDD

sen

VIN

sen

ISNS

SW SGND

CS1

sen

PGND

OUT

DCin

88EM8080/81

CS2

OCP

Vbe 0.65V2mV 80 25–()0.54V=×–≅

Vbe 0.65V2mV 25–25–()0.75V=×–≅

Design and Applications Information

Current Sensing an d Over Current Protecti on

August 27, 2010, 2.00 Document Classification: Proprietary Page 51

The voltage Vbe should have tolerance margin to select the resistor , Rsen. Rsen can be selected from

the following equation.

Equation (43)

The minimum saturation current poi nt of Ilim for the transformer should satisfy:

Equation (44)

Ilim should have enough margins considering transformer saturation condition at lower ambie nt

temperature.

R1 and R2 act as voltage dividers to setup the right current limitation threshold. R2 controls base

current of the transistor Q2. R1 helps to discharge the parasitic capacitance of the transistor. The

value of R1 is recommended as 500~2kΩ, R2 as 500~2kΩ and R3 as 10kΩ. R3 is connected

between the collector of Q2 and OCP as shown in Figure 26.

A capacitor in parallel with the Rsns resistor is used to filter the noise fo r this OCP circuit to function

properly. When the MOSFET turns on, external COSS of the MOSFET starts discharging. This

causes the leading edge spikes of current and increases switching loss. Figure 25 shows that this

spike of current causes unwanted over current protection. This phenomenon can be avoided by

adding one capacitor, Csen. The leading edge current timing is less than 300ns (typical). Csen is

recommended to have a value of 0.22μF/25V. The capacitive reactance of Csen should be far less

than Rsen for proper filtering of this leading edge current spike.

Rsen 0.50V

Idspeak

----------------

≤

Ilim 0.75V

Rsen

-------------- R1R2

+()

-----------------------

×=

88EM8080/88EM8081

Datasheet

Page 52 Document Classification: Proprietary August 27, 2010, 2.00

5.5 SW Pin to MOSFET Gate

The 88EM8080/88EM8081 provides a 1.2A (typical) drive current, which is the strongest driver

capability in comparison with other similar parts. A gate resistor of about 20Ω is used between the

SW pin and the gate of the external MOSFET. The gate driver loop is subject to fast rise times so the

layout trace should be kept as short as possible in order to minimize the parasitic inductance, as

shown in Figure 27.

Figure 27: SW Pin Layout Guidelines

5.6 VDD, Signal (SGND) and Power (PGND) Grounds

VDD is the IC power supply pin. It has a typical value of 12V and a maximum operating voltage of

16V. A Zener diode circuit below 16V is recommended to guarantee that the voltage on VDD will not

go any higher than 16V. The IC starts switching when VDD reaches 12V. The IC continues to switch

as long as the VDD is higher than VDD_UVLO, which is 7V (typical). An electrolytic capacitor 22μF

(typical) is recommended betwee n VDD and ground to keep VDD above 7V during startup. After

startup, the bias transformer winding takes over and provides enough energy to power the IC. The

description of these functions can be found in Section 3.2.

A 0.01-0.1μF ceramic capacitor is strongly recommended to be placed between the VDD and IC

ground with the layout trace as close to the IC as possible. This capacitor is used for decoupling the

noise to VDD and to maintain the VDD voltage during the switching of the internal driver circuit.

SGND is directly connected to the system ground by a Kelvin connection trace. The system ground

is the source of the MOSFET, as shown in Figure 28. PGND connects to the system ground

separately and can not share the same trace with SGND. This is due to pulse current on PGND

while driving the external MOSF ET on and off. This pulse current produces pulse voltage drops on

the PGND trace and may cause the current sensing signal to be distorted if the SGND shares the

same trace. Figure 28 provides layout guidelines.

Drain

OCP

VDD

Rgate

VIN

ISNS

SW SGND

PGND

K ee p t hi s trace as short

as poss i bl e i n l ayout

88EM8080/81

DCin

OUT

Design and Applications Information

VDD, Signal (SGND) and Power (PGND) Grounds

August 27, 2010, 2.00 Document Classification: Proprietary Page 53

Figure 28: VDD Decoupling Capacitor and Ground Layout Guidelines

Drain

OCP

VDD

Rgate

VIN

ISNS

SW SGND

PGND

K eep thi s trac e ri ght besi de

I C an d as short as possi bl e

U s ing Kelvin sens ing c onnect ion for

S GND wi t h separat e trace f rom P GND

88EM8080/81

DCin

OUT

88EM8080/88EM8081

Datasheet

Page 54 Document Classification: Proprietary August 27, 2010, 2.00

5.7 Non-isolated LED Driver

5.7.1 Non-isolated LED Driver Schematic

Figure 29: 1W Non-isolated LED Driver Schematic

VIN

C11

1μF

25V

90VAC to 264VAC – Universal

47Hz to 63Hz

Non-isolated, low-co st application

FB ISNS

SGND

PGND

VDD

88EM8081

R15

20Ω

1/8W

4.7V

500mW

R14

18k

VDD

15V

500mW

150k

1/2W

1.8M

1/2W

1.0mH HVDC

0.1μF 450VDC

R10

150k

0.047μF

25V

R12

187Ω

R22

200Ω

1.0Ω

1/4W

100pF

50V Q1

650V

4.5A

1000pF

1kV

RS1J

STPS3150RL

330μF

35V

LE D +

LE D -

R20

5.6Ω

R17

1.91k

+27.5 VDC, 450mA (nominal)

33μF

25V

R16

18.7k

D12

BAT54C

D7, S 1M

D6, S 1M

D5, S 1M

D2, S 1M

R21

25k

TRAN-EF16

C14

0.01μF

25V

T1B

R22

10Ω

1/8W

US1D-13-F

C14

330μF

35V

C13

0.1μF

Design and Applications Information

Non-isolated LED Driver

August 27, 2010, 2.00 Document Classification: Proprietary Page 55

5.7.2 Non-isolated LED Driver Description

Figure 29 is a single stage non-isolated flyback LED driver with output regulation and PFC. The AC

input is rectified by the diodes D2,D5,D6 and D7. Fuse F1 is used for AC input over current

protection. Inductor L1 used for EMI filtering and also helps for input surge voltage protection.

Resistors R5 and R14 provide the necessary voltage at VIN pin for AC input voltage sensing.

Transformer T1 is the flyback transformer and MOSFET Q1 is the primary switch which is driven by

the 88EM8080/88EM8081 PFC control ler through a gate resisto r R15 . Dio de D4, Resistor R10 and

capacitor C2 form the primary RCD clamp. Resistor R7 senses the primary current and provides the

input to ISNS pin. Diode D3 is the flyback diode and capacitors C1 and C14 are the output

capacitors. Resistor R4 provides the initial bias for the PFC controller from the rectified AC input.

Auxiliary winding T1B provides the bias power after startup. Maximum output voltage protection is

provided by resistors R16 and R17. The LED current is sensed as the voltage across the resistor

R20. The sensed output voltage from the resistor divider network R16 and R17 and the voltage

across resistor R20 are both or’ed through the D12 dual diode. The output of D12 is connected to FB

pin. C13 is a decoupling capacitor and is selected as 0.1μF. R21 is a 25.5k resistor. This value is

chosen based on the RC time constant of R21 and C13. R21 changes the peak detector circuit

formed by D12 and C1 into an average detector. In addition, the value of resistor R21 (25.5k)

provides the right time constant for the best overall dynamic response. R21 could be selected in the

range of 20k to 30k. The selection of R21 also affects the design of the output voltage divider R16

and R17 as defined by the design equations in Section 5.3.2. Zeners D9 and D1 are used for

protection.

The key points for this design are:

Output -- 27.5VDC at 450mA

Universal Input – 90V to 264 VAC

Dual diode for maximum output voltage protection and for sensing the LED current

Small size, low cost

Maximum over voltage protection at 31VDC (typical)

No optocoupler and no external operatio nal amplifier

High power factor and low THD throughout the AC line, load and temperature ranges

No external compensation

88EM8080/88EM8081

Datasheet

Page 56 Document Classification: Proprietary August 27, 2010, 2.00

5.8 Isolated LED Driver

5.8.1 Isolated LED Driver Schematic

Figure 30: 12.5W Universal Isolated LED Driver Schematic

VIN

C14

0.1μF

25V

90VAC to 264VAC – Universal

47Hz to 63Hz

Isolated applications

FB ISNS

SGND

PGND

VDD

88EM8081

0.1μF

25V

R19

20Ω

1/8W

R11

1.24k

4.7V

500mW

0.01μF

25V

18k

VDD

15V

500mW

T1B

TRAN-EF16

22μF

25V

R15

10Ω

1/8W

US1D-13-F

150k

1/2W

R16

866k

1/4W

R13

1.0M

1/4W

1.0mH HVDC

C7 C10

0.82μF , 400VDC

0.1μF, 400VDC

R18

300k

1/8W

R17

300k

1/8W

0.047μF

50V

187Ω

R12

200Ω

VAR1

1.0Ω

1/4W

100pF

50V Q1

650V

4.5A

C12

1000pF

1kV

D10

RS1J

1.0nF-YCAP D9

STPS3150RL

C11

330μF

35V

C13

330μF

35V

NTC1

33k

R23

3.01k

R10

4.02k

LED +

LED -

1.0μF

35V

4.99k

0.1Ω

4.99k

243k

TS321LT

PC1A

FOD817A

15V

500mW

R22

10k

R21

4.99k

1.0μF

50V

VREF

TL431

+25.0 VDC, 500mA (nom inal)

P/O PC1A

D7 S1M

D8 S1M

D2 S1M

D3 S1M

C15

0.047μF

Design and Applications Information

Isolated LED Driver

August 27, 2010, 2.00 Document Classification: Proprietary Page 57

5.8.2 Isolated LED Driver Description

Figure 30 is a single stage isolated flyback LED driver with output regulation and PFC. The AC input

is rectified by the diodes D2,D 3,D7 and D8. Fuse F1 is used for AC input over current protection.

Inductor L1 used for EMI filtering and also helps for input surge voltage protection. Resisto r s R6,

R13 and R16 provide the necessary voltage at VIN pin for AC Input voltage sensing. Transformer T1

is the flyback transformer and MOSFET Q1 is the primary switch which is driven by

88EM8080/88EM8081 PFC controller through a gate resistor R19. Diode D10, Resistors R17,R18

and capacitor C12 form the primary RCD clamp. Resistor R5 senses the primary current and

provides the input to ISNS pin. Diode D9 is th e flyback diode and capacitors C11 and C13 are the

output capacitors. Resistor R9 provides the initial bias for the PFC controller from the rectified AC

input. A secondary winding T1B of transformer T1, resistor R15, diode D4 and capacitor C4 provides

the bias power to VDD pin after startup. Output OVP protection is provided by Zener D6. The LED

current is sensed as the voltage across the resistor R8. This sensed voltage is amplified by U2 and

then used as the input to the error amplifier U1. The optodiode of PC1A opto coupler is connected to

the output of the error amplifier through R23, R10 and the NTC1. The opto transistor of PC1A

optocoupler is connected to VDD and R11. The voltage across the resistor R11 is connected to FB

pin of the controller. Zeners D1, D5 and D6 are used for protection.

The key points for this design are:

Output -- 25VDC at 500 mA

Universal Input – 90V to 264 VAC

High operating temperature range 0 C to 110 C

Innovative NTC compensation circuit for stable operating point of the error amplifier throughout

the temperature range

Small size, low cost

Over voltage protection around 27VDC

High power factor and low THD throughout the AC line, load and temperature ranges

High efficiency

88EM8080/88EM8081

Datasheet

Page 58 Document Classification: Proprietary August 27, 2010, 2.00

5.8.3 12.5W Universal Isolated LED Driver Test Results

A reference board has been built and tested. The following are the test results.

5.8.3.1 Efficiency and Power Factor

The following Table 9 and Figure 31 provides the efficiency, power factor and total harmonic

distortion data at various AC input line voltages at full load LED current of 500mA (typical).

Figure 31: Efficiency, Power Factor

Table 9: Efficiency and Power Factor Test Results

Input Voltage

(VAC) Input

Current (A) Input Power

(W) Power

Factor THD Output Voltage

(V) Output Current

(A) Output Power

(W) Efficiency

(%)

90 0.17 15.272 0.999 3.00% 25.41 0.5064 12.87 84.26

115 0.133 15.04 0.999 2.92% 25.4 0.5068 12.87 85.59

135 0.113 14.95 0.998 2.97% 25.39 0.5072 12.88 86.14

180 0.0858 14.987 0.993 3.45% 25.39 0.5076 12.89 85.99

230 0.0684 15.074 0.979 7.00% 25.39 0.5082 12.90 85.60

265 0.0613 15.292 0.965 9.60% 25.39 0.5094 12.93 84.58

0.75

0.80

0.85

0.90

0.95

1.00

1.05

90 115 135 180 230 265

AC Input Voltage RMS

Pow er Factor

Efficiency

Design and Applications Information

Isolated LED Driver

August 27, 2010, 2.00 Document Classification: Proprietary Page 59

5.8.3.2 Start-up Waveforms

Output Voltage and Input Current waveforms were captured at 115AC and 230VAC at full load

during start-up and are shown in Figure 32 and Figure 33

5.8.3.3 Steady State Waveforms

The steady state output voltage and input current waveforms were captured at 115V AC and 230VAC

at full load and are shown in Figure 34 and Figure 35

Figure 32: Start-up at 115VAC at Full Load Figure 33: Start-up at 230VAC at Full Load

Figure 34: Steady State at 115VAC at Ful l Load Figure 35: Steady State at 230VAC at Full Load

88EM8080/88EM8081

Datasheet

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Mechanical Drawings

August 27, 2010, 2.00 Document Classification: Proprietary Page 61

6Mechanical Drawings

6.1 Mechanical Drawings

Figure 36: 8-Lead SOIC Mechanical Drawing

Notes:

All dimensions in mm.

See Section 7, Part Order Numbering/Package Marking, on page 63 for package marking and pin 1

location.

88EM8080/88EM8081

Datasheet

Page 62 Document Classification: Proprietary August 27, 2010, 2.00

THIS PAGE INTENTIONALLY LEFT BLANK

Part Order Numbering/Package Mark ing

Part Order Numbering

August 27, 2010, 2.00 Document Classification: Proprietary Page 63

7Part Order Numbering/Package Marking

7.1 Part Order Numbering

Figure 37 shows the part order numbering scheme. For complete ordering information, contact your

Marvell FAE or sales representative.

The standard ordering part number for the respective solution is shown in Table 10.

Figure 37: Sample Ordering Pa rt Number

xx–SAG2C000–xxxx

Part number

Package code

Environmental code

2 = Green Halogen Free

Temperature code

C = Commercial

Custom code (optional)

88EM808X

Custom code

Table 10: 88EM8080/88EM8081 Part Order Options1

1. Please note that the 88EM8080 device is 60kHz and the 88EM8081 device is 120kHz.

Package Type Part Order Number

8-Pin SOIC 88EM8080xx-SAG2C000

8-Pin SOIC 88EM8080xx-SAG2C000-T (Tape and Reel)

8-Pin SOIC 88EM8081xx-SAG2C000

8-Pin SOIC 88EM8081xx-SAG2C000-T (Tape and Reel)

88EM8080/88EM8081

Datasheet

Page 64 Document Classification: Proprietary August 27, 2010, 2.00

7.2 Package Markings

Figure 38 shows a typical package marking and pin 1 location.

Figure 38: Package Marking

MRVL

808X

YWWG

Marvell company abbreviation

Date code and assembly house code

Y = last digit of year

WW = work week

G = assembly house code

Abbreviated part nu mber

XXXX = 4 character abbreviated part number

Note: The above example is not drawn to scale. Location of markings are approximate.

Pin 1 location

August 27, 2010, 2.00 Document Classification: Proprietary Page 65

ARevision History

Table 11: Revision History

Document Type Document Revision

Release 88EM8080/88EM8081 Rev. C

Reworked Sections: Functional Description and Application Information

Revised Sections:

• Application Information: edited section

Release 88EM8080/88EM8081 Rev. B

Reworked Sections: Functional Description and Application Information

Revised Sections:

• Product overview: added Universal schematic and removed other two

• Signal Descripti on:updated pin descriptions

• Electrical Characteristics: updated EC table values

• Functional Description: completely rewrote section (removed old content)

• Application Information: completely rewrote section (reworked old content)

Release 88EM8080/88EM8081 Rev. A

Changed 30W Isolated Schematic

Release 88EM8080/88EM8081 Rev. –

First Release

Marvell. Moving Forward Faster

Marvell Semiconductor, Inc.

5488 Marvell Lane

Santa Clara, CA 95054, USA

Tel: 1.408.222.2500

Fax: 1.408.752.9028

www.marvell.com

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