135 MHz Quad IF Receiver AD6684 Data Sheet FEATURES 4 integrated wideband digital downconverters (DDCs) 48-bit numerically controlled oscillator (NCO), up to 4 cascaded half-band filters 1.4 GHz analog input full power bandwidth Amplitude detect bits for efficient automatic gain control (AGC) implementation Differential clock input Integer clock divide by 1, 2, 4, or 8 On-chip temperature diode Flexible JESD204B lane configurations JESD204B (Subclass 1) coded serial digital outputs Lane rates up to 15 Gbps 1.68 W total power at 500 MSPS 420 mW per analog-to-digital converter (ADC) channel SFDR = 82 dBFS at 305 MHz (1.8 V p-p input range) SNR = 66.8 dBFS at 305 MHz (1.8 V p-p input range) Noise density = -151.5 dBFS/Hz (1.8 V p-p input range) Analog input buffer On-chip dithering to improve small signal linearity Flexible differential input range 1.44 V p-p to 2.16 V p-p (1.80 V p-p nominal) 82 dB channel isolation/crosstalk 0.975 V, 1.8 V, and 2.5 V dc supply operation Noise shaping requantizer (NSR) option for main receiver Variable dynamic range (VDR) option for digital predistortion (DPD) APPLICATIONS Communications Diversity multiband, multimode digital receivers 3G/4G, W-CDMA, GSM, LTE, LTE-A HFC digital reverse path receivers Digital predistortion observation paths General-purpose software radios FUNCTIONAL BLOCK DIAGRAM AVDD1 AVDD1_SR (0.975V) (0.975V) VIN+A BUFFER ADC CORE VIN-A AVDD2 (1.8V) AVDD3 (2.5V) DVDD (0.975V) DRVDD1 (0.975V) FD_B FAST DETECT DIGITAL DOWNCONVERTER (x2) ADC CORE VIN-B NOISE SHAPED REQUANTIZER (x2) SIGNAL MONITOR BUFFER VIN+B SPIVDD (1.8V) SIGNAL PROCESSING 14 VCM_AB FD_A DRVDD2 (1.8V) 2 JESD204B HIGH SPEED SERIALIZER Tx OUTPUTS SERDOUTAB0 SERDOUTAB1 VARIABLE DYNAMIC RANGE (x2) 14 SIGNAL MONITOR AND FAST DETECT CLK- SYSREF JESD204B SUBCLASS 1 CONTROL CLOCK GENERATION CLK+ SYNCINBAB SYNCINBCD /2 /4 /8 VIN+C ADC CORE VIN-C VCM_CD FD_C SIGNAL PROCESSING BUFFER FAST DETECT 14 DIGITAL DOWNCONVERTER (x2) SIGNAL MONITOR NOISE SHAPED REQUANTIZER (x2) JESD204B HIGH SPEED SERIALIZER 2 Tx OUTPUTS SERDOUTCD0 SERDOUTCD1 FD_D VIN+D BUFFER ADC CORE VIN-D 14 VARIABLE DYNAMIC RANGE (x2) SPI CONTROL AGND DRGND 14994-001 PDWN/STBY AD6684 SDIO SCLK CSB Figure 1. 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Technical Support www.analog.com AD6684 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 DDC Gain Stage ......................................................................... 44 Applications ....................................................................................... 1 DDC Complex to Real Conversion ......................................... 44 Functional Block Diagram .............................................................. 1 DDC Example Configurations ................................................. 45 Revision History ............................................................................... 3 Noise Shaping Requantizer (NSR) ............................................... 49 General Description ......................................................................... 4 Decimating Half-Band Filter .................................................... 49 Product Highlights ........................................................................... 4 NSR Overview ............................................................................ 50 Specifications..................................................................................... 5 Variable Dynamic Range (VDR) .................................................. 51 DC Specifications ......................................................................... 5 VDR Real Mode.......................................................................... 52 AC Specifications.......................................................................... 6 VDR Complex Mode ................................................................. 52 Digital Specifications ................................................................... 8 Digital Outputs ............................................................................... 54 Switching Specifications .............................................................. 9 Introduction to the JESD204B Interface ................................. 54 Timing Specifications .................................................................. 9 JESD204B Overview .................................................................. 54 Absolute Maximum Ratings .......................................................... 11 Functional Overview ................................................................. 56 Thermal Characteristics ............................................................ 11 JESD204B Link Establishment ................................................. 56 ESD Caution ................................................................................ 11 Physical Layer (Driver) Outputs .............................................. 57 Pin Configuration and Function Descriptions ........................... 12 JESD204B Tx Converter Mapping ........................................... 59 Typical Performance Characteristics ........................................... 14 Setting Up the AD6684 Digital Interface ................................ 60 Equivalent Circuits ......................................................................... 21 Latency ............................................................................................. 64 Theory of Operation ...................................................................... 23 End-To-End Total Latency ........................................................ 64 ADC Architecture ...................................................................... 23 Multichip Synchronization............................................................ 65 Analog Input Considerations.................................................... 23 SYSREF Setup/Hold Window Monitor ................................. 67 Voltage Reference ....................................................................... 25 Test Modes ....................................................................................... 69 Clock Input Considerations ...................................................... 26 ADC Test Modes ........................................................................ 69 Temperature Diode .................................................................... 27 JESD204B Block Test Modes .................................................... 70 ADC Overrange and Fast Detect .................................................. 28 Serial Port Interface ........................................................................ 72 ADC Overrange .......................................................................... 28 Configuration Using the SPI ..................................................... 72 Fast Threshold Detection (FD_A, FD_B, FD_C and FD_D).... 28 Hardware Interface ..................................................................... 72 Signal Monitor ................................................................................ 29 SPI Accessible Features .............................................................. 72 SPORT Over JESD204B ............................................................. 29 Memory Map .................................................................................. 73 Digital Downconverter (DDC) ..................................................... 32 Reading the Memory Map Register Table............................... 73 DDC I/Q Input Selection .......................................................... 32 Memory Map .................................................................................. 74 DDC I/Q Output Selection ....................................................... 32 Memory Map Details ................................................................. 74 DDC General Description ........................................................ 32 Applications Information .............................................................. 98 Frequency Translation ................................................................... 38 Power Supply Recommendations............................................. 98 General Description ................................................................... 38 Exposed Pad Thermal Heat Slug Recommendations ............ 98 DDC NCO + Mixer Loss and SFDR ........................................ 39 AVDD1_SR (Pin 64) and AGND_SR (Pin 63 and Pin 67) ... 98 Numerically Controlled Oscillator........................................... 39 Outline Dimensions ....................................................................... 99 FIR Filters ........................................................................................ 41 Ordering Guide .......................................................................... 99 General Description ................................................................... 41 Half-Band Filters ........................................................................ 42 Rev. A | Page 2 of 99 Data Sheet AD6684 REVISION HISTORY 4/2020--Rev. 0 to Rev. A Change to Unit Interval (UI) Parameter, Table 4 and Data Rate per Channel (NRZ) Parameter, Table 4 .......................................... 9 Changes to De-Emphasis Section .................................................58 Added Table 33; Renumbered Sequentially and Figure 94; Renumbered Sequentially ..............................................................58 Changes to Setting Up the AD6684 Digital Interface Section ..60 Changes to Example 1: ADC with DDC Option (Two ADCs Plus Two DDCs in Each Pair) Section .........................................62 Changes to Figure 104 ....................................................................67 Changes to Reading the Memory Map Register Table Section .......73 Deleted Memory Map Summary Section and Table 45; Renumbered Sequentially .............................................................. 74 Changes to Register 0x05B0 Row, Table 46 ................................. 94 Added Register 0x05C1 Rows, Table 46 ....................................... 95 Changes to Register 0x05C4 Row and Register 0x05C6 Row, Table 46 ............................................................................................. 95 10/2016--Revision 0: Initial Version Rev. A | Page 3 of 99 AD6684 Data Sheet GENERAL DESCRIPTION The AD6684 is a 135 MHz bandwidth, quad intermediate frequency (IF) receiver. It consists of four 14-bit, 500 MSPS ADCs and various digital processing blocks consisting of four wideband DDCs, an NSR, and VDR monitoring. The device has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. This device is designed to support communications applications. The analog full power bandwidth of the device is 1.4 GHz. The quad ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. The AD6684 is optimized for wide input bandwidth, excellent linearity, and low power in a small package. The analog inputs and clock signal input are differential. Each pair of ADC data outputs are internally connected to two DDCs through a crossbar mux. Each DDC consists of up to five cascaded signal processing stages: a 48-bit frequency translator, NCO, and up to four half-band decimation filters. Each ADC output is connected internally to an NSR block. The integrated NSR circuitry allows improved SNR performance in a smaller frequency band within the Nyquist bandwidth. The device supports two different output modes selectable via the serial port interface (SPI). With the NSR feature enabled, the outputs of the ADCs are processed such that the AD6684 supports enhanced SNR performance within a limited portion of the Nyquist bandwidth while maintaining a 9-bit output resolution. Each ADC output is also connected internally to a VDR block. This optional mode allows full dynamic range for defined input signals. Inputs that are within a defined mask (based on DPD applications) are passed unaltered. Inputs that violate this defined mask result in the reduction of the output resolution. With VDR, the dynamic range of the observation receiver is determined by a defined input frequency mask. For signals falling within the mask, the outputs are presented at the maximum resolution allowed. For signals exceeding defined power levels within this frequency mask, the output resolution is truncated. This mask is based on DPD applications and supports tunable real IF sampling, and zero IF or complex IF receive architectures. Operation of the AD6684 in the DDC, NSR, and VDR modes is selectable via SPI-programmable profiles (the default mode is NSR at startup). In addition to the DDC blocks, the AD6684 has several functions that simplify the AGC function in the communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect output bits of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input. Users can configure each pair of IF receiver outputs onto either one or two lanes of Subclass 1 JESD204B-based high speed serialized outputs, depending on the decimation ratio and the acceptable lane rate of the receiving logic device. Multiple device synchronization is supported through the SYSREF, SYNCINBAB, and SYNCINBCD input pins. The AD6684 has flexible power-down options that allow significant power savings when desired. All of these features can be programmed using the 1.8 V capable, 3-wire SPI. The AD6684 is available in a Pb-free, 72-lead LFCSP and is specified over the -40C to +105C junction temperature range. This product may be protected by one or more U.S. or international patents PRODUCT HIGHLIGHTS 1. 2. 3. 4. 5. 6. 7. Rev. A | Page 4 of 99 Low power consumption per channel. JESD204B lane rate support up to 15 Gbps. Wide full power bandwidth supports IF sampling of signals up to 1.4 GHz. Buffered inputs ease filter design and implementation. Four integrated wideband decimation filters and NCO blocks supporting multiband receivers. Programmable fast overrange detection. On-chip temperature diode for system thermal management. Data Sheet AD6684 SPECIFICATIONS DC SPECIFICATIONS AVDD1 = 0.975 V, AVDD1_SR = 0.975 V, AVDD2 = 1.8 V, AVDD3 = 2.5 V, DVDD = 0.975 V, DRVDD1 = 0.975 V, DRVDD2 = 1.8 V, SPIVDD = 1.8 V, specified maximum sampling rate, clock divider = 4, 1.8 V p-p full-scale differential input, 0.5 V internal reference, AIN = -1.0 dBFS, default SPI settings, unless otherwise noted. Minimum and maximum specifications are guaranteed for the full operating TJ range of -40C to +105C. Typical specifications represent performance at TJ = 50C (TA = 25C). Table 1. Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Offset Matching Gain Error Gain Matching Differential Nonlinearity (DNL) Integral Nonlinearity (INL) TEMPERATURE DRIFT Offset Error Gain Error INTERNAL VOLTAGE REFERENCE Voltage INPUT REFERRED NOISE ANALOG INPUTS Differential Input Voltage Range (Programmable) Common-Mode Voltage (VCM) Differential Input Capacitance Differential Input Resistance Analog Input Full Power Bandwidth POWER SUPPLY 1 AVDD1 AVDD1_SR AVDD2 AVDD3 DVDD DRVDD1 DRVDD2 SPIVDD IAVDD1 IAVDD1_SR IAVDD2 IAVDD3 IDVDD 2 IDRVDD1 IDRVDD2 ISPIVDD POWER CONSUMPTION Total Power Dissipation (Including Output Drivers)2 Power-Down Dissipation Standby 3 Min 14 Typ Max Guaranteed 0 0 -5.0 +5.0 1.0 -0.7 -5.1 Power is measured at NSR, 28% bandwidth, L, M, and F = 222. Default mode, no decimation enabled. For each link, L = 2, M = 2, and F = 2. 3 Standby mode is controlled by the SPI. 1 2 Rev. A | Page 5 of 99 0.4 1.0 +0.7 +5.1 Unit Bits % FSR % FSR % FSR % FSR LSB LSB 8 214 ppm/C ppm/C 0.5 2.6 V LSB rms 1.44 1.80 1.34 1.75 200 1.4 2.16 V p-p V pF GHz 0.95 0.95 1.71 2.44 0.95 0.95 1.71 1.71 0.975 0.975 1.8 2.5 0.975 0.975 1.8 1.8 319 21 438 87 145 162 23 1 1.00 1.00 1.89 2.56 1.00 1.00 1.89 1.89 482 53 473 103 198 207 29 1.6 V V V V V V V V mA mA mA mA mA mA mA mA 1.68 325 1.20 1.94 W mW W AD6684 Data Sheet AC SPECIFICATIONS AVDD1 = 0.975 V, AVDD1_SR = 0.975 V, AVDD2 = 1.8 V, AVDD3 = 2.5 V, DVDD = 0.975 V, DRVDD1 = 0.975 V, DRVDD2 = 1.8 V, SPIVDD = 1.8 V, specified maximum sampling rate, clock divider = 4, 1.8 V p-p full-scale differential input, 0.5 V internal reference, AIN = -1.0 dBFS, default SPI settings, VDR mode (input mask not triggered), unless otherwise noted. Minimum and maximum specifications are guaranteed for the full operating junction temperature (TJ) range of -40C to +105C. Typical specifications represent performance at TJ = 50C (TA = 25C). Table 2. Parameter 1 ANALOG INPUT FULL SCALE NOISE DENSITY 2 SIGNAL-TO-NOISE RATIO (SNR) 3 VDR Mode fIN = 10 MHz fIN = 155 MHz fIN = 305 MHz fIN = 450 MHz fIN = 765 MHz fIN = 985 MHz 21% Bandwidth (BW) Mode (>105 MHz at 500 MSPS) fIN = 10 MHz fIN = 155 MHz fIN = 305 MHz fIN = 450 MHz fIN = 765 MHz fIN = 985 MHz 28% BW Mode (>135 MHz at 500 MSPS) fIN = 10 MHz fIN = 155 MHz fIN = 305 MHz fIN = 450 MHz fIN = 765 MHz fIN = 985 MHz SIGNAL-TO-NOISE-AND-DISTORTION RATIO (SINAD)3 fIN = 10 MHz fIN = 155 MHz fIN = 305 MHz fIN = 450 MHz fIN = 765 MHz fIN = 985 MHz EFFECTIVE NUMBER OF BITS (ENOB)3 fIN = 10 MHz fIN = 155 MHz fIN = 305 MHz fIN = 450 MHz fIN = 765 MHz fIN = 985 MHz Analog Input Full Scale = 1.44 V p-p Min Typ Max 1.44 -149.7 65.4 65.3 65.2 65.0 64.8 64.5 Analog Input Full Scale = 1.80 V p-p Min Typ Max 1.80 -151.5 Analog Input Full Scale = 2.16 V p-p Min Typ Max 2.16 -153.0 Unit V p-p dBFS/Hz 67.1 67.0 66.8 66.6 66.5 66.0 68.4 68.3 68.0 67.8 67.5 66.9 dBFS dBFS dBFS dBFS dBFS dBFS 72.1 71.8 71.9 71.6 71.0 70.6 73.8 73.5 73.5 73.2 72.7 72.1 75.1 74.8 74.7 74.4 73.7 73.0 dBFS dBFS dBFS dBFS dBFS dBFS 69.6 69.1 69.1 69.4 68.5 68.5 71.3 70.8 70.7 71.0 70.2 70.0 72.6 72.1 71.9 72.2 71.2 70.9 dBFS dBFS dBFS dBFS dBFS dBFS 67.0 66.8 66.6 66.4 66.1 65.5 68.2 67.9 67.6 67.3 66.9 66.2 dBFS dBFS dBFS dBFS dBFS dBFS 10.8 10.8 10.7 10.7 10.6 10.6 11.0 10.9 10.9 10.8 10.8 10.7 Bits Bits Bits Bits Bits Bits 65.3 65.2 65.1 65.0 64.7 64.2 10.5 10.5 10.5 10.5 10.4 10.3 64.8 64.5 10.4 Rev. A | Page 6 of 99 Data Sheet Parameter 1 SPURIOUS-FREE DYNAMIC RANGE (SFDR)3 fIN = 10 MHz fIN = 155 MHz fIN = 305 MHz fIN = 450 MHz fIN = 765 MHz fIN = 985 MHz SPURIOUS-FREE DYNAMIC RANGE (SFDR) AT -3 dBFS3 fIN = 10 MHz fIN = 155 MHz fIN = 305 MHz fIN = 450 MHz fIN = 765 MHz fIN = 985 MHz WORST HARMONIC, SECOND OR THIRD3 fIN = 10 MHz fIN = 155 MHz fIN = 305 MHz fIN = 450 MHz fIN = 765 MHz fIN = 985 MHz WORST HARMONIC, SECOND OR THIRD AT -3 dBFS3 fIN = 10 MHz fIN = 155 MHz fIN = 305 MHz fIN = 450 MHz fIN = 765 MHz fIN = 985 MHz WORST OTHER, EXCLUDING SECOND OR THIRD HARMONIC3 fIN = 10 MHz fIN = 155 MHz fIN = 305 MHz fIN = 450 MHz fIN = 765 MHz fIN = 985 MHz TWO TONE INTERMODULATION DISTORTION (IMD), AIN1 AND AIN2 = -7 dBFS fIN1 = 154 MHz, fIN2 = 157 MHz fIN1 = 302 MHz, fIN2 = 305 MHz CROSSTALK 4 FULL POWER BANDWIDTH 5 AD6684 Analog Input Full Scale = 1.44 V p-p Min Typ Max 89 89 82 82 77 82 Analog Input Full Scale = 1.80 V p-p Min Typ Max Analog Input Full Scale = 2.16 V p-p Min Typ Max Unit 90 85 82 83 75 79 80 77 78 77 72 76 dBFS dBFS dBFS dBFS dBFS dBFS 94 94 89 87 82 85 94 90 90 86 80 82 86 82 83 84 77 79 dBFS dBFS dBFS dBFS dBFS dBFS -89 -89 -82 -82 -77 -82 -90 -85 -82 -83 -75 -79 -80 -77 -78 -77 -72 -76 dBFS dBFS dBFS dBFS dBFS dBFS -94 -94 -89 -87 -82 -85 -94 -90 -90 -86 -80 -82 -86 -82 -83 -84 -77 -79 dBFS dBFS dBFS dBFS dBFS dBFS -96 -97 -97 -95 -92 -90 -98 -97 -98 -96 -91 -89 -99 -97 -97 -96 -88 -86 dBFS dBFS dBFS dBFS dBFS dBFS -93 -90 82 1.4 -90 -90 82 1.4 -84 -84 82 1.4 dBFS dBFS dB GHz 75 -75 -86 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. Noise density is measured with no analog input signal. See Table 9 for recommended settings for full-scale voltage and buffer current setting. 4 Crosstalk is measured at 155 MHz with a -1.0 dBFS analog input on one channel and no input on the adjacent channel. 5 Measured with circuit shown in Figure 58. 1 2 3 Rev. A | Page 7 of 99 AD6684 Data Sheet DIGITAL SPECIFICATIONS AVDD1 = 0.975 V, AVDD1_SR = 0.975 V, AVDD2 = 1.8 V, AVDD3 = 2.5 V, DVDD = 0.975 V, DRVDD1 = 0.975 V, DRVDD2 = 1.8 V, SPIVDD = 1.8 V, specified maximum sampling rate, clock divider = 4, 1.8 V p-p full-scale differential input, 0.5 V internal reference, AIN = -1.0 dBFS, default SPI settings, unless otherwise noted. Minimum and maximum specifications are guaranteed for the full operating junction temperature (TJ) range of -40C to +105C. Typical specifications represent performance at TJ = 50C (TA = 25C). Table 3. Parameter CLOCK INPUTS (CLK+, CLK-) Logic Compliance Differential Input Voltage Input Common-Mode Voltage Input Resistance (Differential) Input Capacitance SYSREF INPUTS (SYSREF+, SYSREF-) 1 Logic Compliance Differential Input Voltage Input Common-Mode Voltage Input Resistance (Differential) Input Capacitance (Single-Ended per Pin) LOGIC INPUTS (PDWN/STBY) Logic Compliance Logic 1 Voltage Logic 0 Voltage Input Resistance LOGIC INPUTS (SDIO, SCLK, CSB) Logic Compliance Logic 1 Voltage Logic 0 Voltage Input Resistance LOGIC OUTPUT (SDIO) Logic Compliance Logic 1 Voltage (IOH = 800 A) Logic 0 Voltage (IOL = 50 A) SYNCIN INPUT (SYNCINB+AB, SYNCINB-AB, SYNCINB+CD, SYNCINB-CD) Logic Compliance Differential Input Voltage Input Common-Mode Voltage Input Resistance (Differential) Input Capacitance (Single-Ended per Pin) LOGIC OUTPUTS (FD_A, FD_B) Logic Compliance Logic 1 Voltage Logic 0 Voltage Input Resistance DIGITAL OUTPUTS (SERDOUTx, x = AB0, AB1, CD0, and CD1) Logic Compliance Differential Output Voltage Short-Circuit Current (ID SHORT) Differential Termination Impedance 1 Min Typ 400 400 0.6 18 Max Unit LVDS/LVPECL 800 1600 0.69 32 0.9 mV p-p V k pF LVDS/LVPECL 800 1800 0.69 2.2 22 0.7 mV p-p V k pF CMOS 0.65 x SPIVDD 0 0.35 x SPIVDD V V M 0.35 x SPIVDD V V k 10 CMOS 0.65 x SPIVDD 0 56 CMOS SPIVDD - 0.45 V 0 400 0.6 18 0.45 LVDS/LVPECL/CMOS 800 1800 0.69 2.2 22 0.7 V V mV p-p V k pF CMOS 0.8 x SPIVDD 0 DC-coupled input only. Rev. A | Page 8 of 99 56 V V k CML 455.8 15 100 mV p-p mA 0.5 Data Sheet AD6684 SWITCHING SPECIFICATIONS AVDD1 = 0.975 V, AVDD1_SR = 0.975 V, AVDD2 = 1.8 V, AVDD3 = 2.5 V, DVDD = 0.975 V, DRVDD1 = 0.975 V, DRVDD2 = 1.8 V, SPIVDD = 1.8 V, specified maximum sampling rate, clock divider = 4, 1.8 V p-p full-scale differential input, 0.5 V internal reference, AIN = -1.0 dBFS, default SPI settings, unless otherwise noted. Minimum and maximum specifications are guaranteed for the full operating junction temperature (TJ) range of -40C to +105C. Typical specifications represent performance at TJ = 50C (TA = 25C). Table 4. Parameter CLOCK Clock Rate at CLK+/CLK- Pins Maximum Sample Rate 1 Minimum Sample Rate 2 Clock Pulse Width High Clock Pulse Width Low OUTPUT PARAMETERS Unit Interval (UI) 3 Rise Time (tR) (20% to 80% into 100 Load) Fall Time (tF) (20% to 80% into 100 Load) Phase-Locked Loop (PLL) Lock Time Data Rate per Channel (NRZ) 4 LATENCY 5 Pipeline Latency Fast Detect Latency APERTURE Aperture Delay (tA) Aperture Uncertainty (Jitter, tj) Out-of-Range Recovery Time Min Typ 0.3 500 240 125 125 66.67 1.6875 100 31.25 31.37 5 10 Max Unit 2.4 GHz MSPS MSPS ps ps 15 ps ps ps ms Gbps 30 Sample clock cycles Sample clock cycles 54 160 44 1 ps fs rms Sample clock cycles The maximum sample rate is the clock rate after the divider. The minimum sample rate operates at 240 MSPS with L = 2 or L = 1. Refer to SPI Register 0x011A to reduce the threshold of the clock detect circuit. 3 Baud rate = 1/UI. A subset of this range can be supported. 4 Default L = 2. This number can be changed based on the sample rate and decimation ratio. 5 No DDCs used. L = 2, M = 2, F = 2 for each link. 1 2 TIMING SPECIFICATIONS Table 5. Parameter CLK+ to SYSREF+ TIMING REQUIREMENTS tSU_SR tH_SR SPI TIMING REQUIREMENTS tDS tDH tCLK tS tH tHIGH tLOW tACCESS tDIS_SDIO Test Conditions/Comments See Figure 3 Device clock to SYSREF+ setup time Device clock to SYSREF+ hold time See Figure 4 Setup time between the data and the rising edge of SCLK Hold time between the data and the rising edge of SCLK Period of the SCLK Setup time between CSB and SCLK Hold time between CSB and SCLK Minimum period that SCLK must be in a logic high state Minimum period that SCLK must be in a logic low state Maximum time delay between falling edge of SCLK and output data valid for a read operation Time required for the SDIO pin to switch from an output to an input relative to the CSB rising edge (not shown in Figure 4) Rev. A | Page 9 of 99 Min Typ Max -44.8 64.4 ps ps 6 ns ns ns ns ns ns ns ns 4 2 40 2 2 10 10 10 Unit 10 ns AD6684 Data Sheet Timing Diagrams APERTURE DELAY SAMPLE N N - 53 N+1 N - 54 N - 52 N - 51 N-1 N - 50 14994-002 ANALOG INPUT SIGNAL CLK- CLK+ Figure 2. Data Output Timing (NSR Mode, 21%, L, M, F = 222) CLK- CLK+ tSU_SR tH_SR 14994-003 SYSREF- SYSREF+ Figure 3. SYSREF Setup and Hold Timing tHIGH tDS tS tCLK tDH tACCESS tH tLOW CSB SDIO DON'T CARE DON'T CARE R/W A14 A13 A12 A11 A10 A9 A8 A7 D7 Figure 4. Serial Port Interface Timing Diagram Rev. A | Page 10 of 99 D6 D3 D2 D1 D0 DON'T CARE 14994-004 SCLK DON'T CARE Data Sheet AD6684 ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS Table 6. Parameter Electrical AVDD1 to AGND AVDD1_SR to AGND AVDD2 to AGND AVDD3 to AGND DVDD to DGND DRVDD1 to DRGND DRVDD2 to DRGND SPIVDD to AGND VINx to AGND CLK to AGND SCLK, SDIO, CSB to DGND PDWN/STBY to DGND SYSREF to AGND_SR SYNCINAB/SYNCINCD to DRGND Environmental Operating Junction Temperature Range Maximum Junction Temperature Storage Temperature Range (Ambient) Rating 1.05 V 1.05 V 2.00 V 2.70 V 1.05 V 1.05 V 2.00 V 2.00 V -0.3 V to AVDD3 + 0.3 V -0.3 V to AVDD1 + 0.3 V -0.3 V to SPIVDD + 0.3 V -0.3 V to SPIVDD + 0.3 V 0 V to 2.5 V 0 V to 2.5 V Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Careful attention to PCB thermal design is required. Table 7. Thermal Resistance PCB Type JEDEC 2s2p Board 10-Layer Board Airflow Velocity (m/sec) 0.0 1.0 2.5 0.0 JA 21.58 17.94 1, 2 16.58 1, 2 1, 2 9.74 JCB 1.951, 3 N/A4 N/A4 1.00 Per JEDEC 51-7, plus JEDEC 51-5 2s2p test board. Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air). 3 Per MIL-STD 883, Method 1012.1. 4 N/A means not applicable. 1 2 ESD CAUTION -40C to +105C 125C -65C to +150C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. A | Page 11 of 99 Unit C/W C/W C/W C/W AD6684 Data Sheet 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 AVDD2 AVDD1 AVDD1 AVDD1 AVDD1 AGND_SR SYSREF- SYSREF+ AVDD1_SR AGND_SR AVDD1 CLK- CLK+ AVDD1 AVDD1 AVDD1 AVDD1 AVDD2 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 AD6684 TOP VIEW (Not to Scale) AVDD3 VIN-C VIN+C AVDD2 AVDD2 AVDD3 VIN+D VIN-D AVDD2 AVDD1 AVDD1 VCM_CD/VREF DVDD DGND SPIVDD CSB SCLK SDIO NOTES 1. EXPOSED PAD. ANALOG GROUND. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES THE GROUND REFERENCE FOR AVDDx, SPIVDD, DVDD, DRVDD1, AND DRVDD2. THIS EXPOSED PAD MUST BE CONNECTED TO GROUND FOR PROPER OPERATION. 14994-005 SYNCINB-AB SYNCINB+AB DRGND DRVDD1 SERDOUTAB0- SERDOUTAB0+ SERDOUTAB1- SERDOUTAB1+ SERDOUTCD1+ SERDOUTCD1- SERDOUTCD0+ SERDOUTCD0- DRVDD1 DRGND SYNCINB+CD SYNCINB-CD FD_D FD_C 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 AVDD3 VIN-A VIN+A AVDD2 AVDD2 AVDD3 VIN+B VIN-B AVDD2 AVDD1 AVDD1 VCM_AB DVDD DGND DRVDD2 PDWN/STBY FD_A FD_B Figure 5. Pin Configuration (Top View) Table 8. Pin Function Descriptions Pin No. 0 Mnemonic AGND/EPAD Type Ground 1, 6, 49, 54 2, 3 4, 5, 9, 46, 50, 51, 55, 72 7, 8 10, 11, 44, 45, 56, 57, 58, 59, 62, 68, 69, 70, 71 12 AVDD3 VIN-A, VIN+A AVDD2 VIN+B, VIN-B AVDD1 Supply Input Supply Input Supply VCM_AB Output 13, 42 14, 41 15 16 DVDD DGND DRVDD2 PDWN/STBY Supply Ground Supply Input 17, 18, 36, 35 FD_A, FD_B, FD_C, FD_D Output 19 SYNCINB-AB Input 20 SYNCINB+AB Input 21, 32 22, 31 DRGND DRVDD1 Ground Supply Description Exposed Pad. Analog Ground. The exposed thermal pad on the bottom of the package provides the ground reference for AVDDx, SPIVDD, DVDD, DRVDD1, and DRVDD2. This exposed pad must be connected to ground for proper operation. Analog Power Supply (2.5 V Nominal). ADC A Analog Input Complement/True. Analog Power Supply (1.8 V Nominal). ADC B Analog Input True/Complement. Analog Power Supply (0.975 V Nominal). Common-Mode Level Bias Output for Analog Input Channel A and Channel B Digital Power Supply (0.975 V Nominal). Ground Reference for DVDD and SPIVDD. Digital Power Supply for JESD204B PLL (1.8 V Nominal). Power-Down Input (Active High). The operation of this pin depends on the SPI mode and can be configured as powerdown or standby. Requires external 10 k pull-down resistor. Fast Detect Outputs for Channel A, Channel B, Channel C, and Channel D. Active Low JESD204B LVDS Sync Input Complement for Channel A and Channel B. Active Low JESD204B LVDS/CMOS Sync Input True for Channel A and Channel B. Ground Reference for DRVDD1 and DRVDD2. Digital Power Supply for SERDOUT Pins (0.975 V Nominal). Rev. A | Page 12 of 99 Data Sheet Pin No. 23, 24 AD6684 Type Output 33 Mnemonic SERDOUTAB0-, SERDOUTAB0+ SERDOUTAB1-, SERDOUTAB1+ SERDOUTCD1+, SERDOUTCD1- SERDOUTCD0+, SERDOUTCD0- SYNCINB+CD 34 SYNCINB-CD Input 37 38 39 40 43 SDIO SCLK CSB SPIVDD VCM_CD/VREF Input/output Input Input Supply Output/input 47, 48 52, 53 60, 61 63, 67 64 65, 66 VIN-D, VIN+D VIN+C, VIN-C CLK+, CLK- AGND_SR AVDD1_SR SYSREF+, SYSREF- Input Input Input Ground Supply Input 25, 26 27, 28 29, 30 Output Output Output Input Description Lane 0 Output Data Complement/True for Channel A and Channel B. Lane 1 Output Data Complement/True for Channel A and Channel B. Lane 1 Output Data True/Complement for Channel C and Channel D. Lane 0 Output Data True/Complement for Channel C and Channel D. Active Low JESD204B LVDS/CMOS Sync Input True for Channel C and Channel D. Active Low JESD204B LVDS Sync Input Complement for Channel C and Channel D. SPI Serial Data Input/Output. SPI Serial Clock. SPI Chip Select (Active Low). Digital Power Supply for SPI (1.8 V Nominal). Common-Mode Level Bias Output for Analog Input Channel C and Channel D/0.5 V Reference Voltage Input. This pin is configurable through the SPI as an output or an input. Use this pin as the common-mode level bias output if using the internal reference. This pin requires a 0.5 V reference voltage input if using an external voltage reference source. ADC D Analog Input Complement/True. ADC C Analog Input True/Complement. Clock Input True/Complement. Ground Reference for SYSREF. Analog Power Supply for SYSREF (0.975 V Nominal). Active Low JESD204B LVDS System Reference (SYSREF) Input True/Complement. DC-coupled input only. Rev. A | Page 13 of 99 AD6684 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS AVDD1 = 0.975 V, AVDD1_SR = 0.975 V, AVDD2 = 1.8 V, AVDD3 = 2.5 V, DVDD = 0.975 V, DRVDD1 = 0.975 V, DRVDD2 = 1.8 V, SPIVDD = 1.8 V, specified maximum sampling rate, clock divider = 4, 1.5 V p-p full-scale differential input, AIN = -1.0 dBFS, default SPI settings, VDR mode (input mask not triggered), unless otherwise noted. Minimum and maximum specifications are guaranteed for the full operating junction temperature (TJ) range of -40C to +105C. Typical specifications represent performance at TJ = 50C (TA = 25C). -20 AMPLITUDE (dBFS) -40 -60 -80 -40 -60 -80 -100 -100 -120 -120 50 100 150 200 250 FREQUENCY (MHz) -140 14994-100 -140 0 AIN = -1dBFS SNR = 66.8dB SFDR = 82dBFS ENOB = 10.7 BITS 0 100 150 AIN = -1dBFS SNR = 67.0dB SFDR = 85dBFS ENOB = 10.8 BITS -20 AMPLITUDE (dBFS) -60 -80 -40 -60 -80 -100 -100 -120 -120 100 150 200 FREQUENCY (MHz) 250 -140 14994-101 -140 50 AIN = -1dBFS SNR = 66.6dB SFDR = 83dBFS ENOB = 10.7 BITS -20 -40 0 250 Figure 8. Single-Tone FFT with fIN = 305 MHz 0 0 200 FREQUENCY (MHz) Figure 6. Single-Tone FFT with fIN = 10.3 MHz AMPLITUDE (dBFS) 50 14994-102 -20 AMPLITUDE (dBFS) 0 AIN = -1dBFS SNR = 67.10dB SFDR = 90dBFS ENOB = 10.8 BITS 0 50 100 150 200 FREQUENCY (MHz) Figure 9. Single-Tone FFT with fIN = 453 MHz Figure 7. Single-Tone FFT with fIN = 155 MHz Rev. A | Page 14 of 99 250 14994-103 0 Data Sheet 95 0 AIN = -1dBFS SNR = 66.5dB SFDR = 75dBFS ENOB = 10.6 BITS -20 90 -40 85 SNR/SFDR (dBFS) -100 70 -120 65 565 ANALOG INPUT FREQUENCY (MHz) Figure 10. Single-Tone FFT with fIN = 765 MHz 0 67.5 67.4 67.3 67.2 67.1 -40 67.0 -60 SNR (dBFS) AMPLITUDE (dBFS) Figure 13. SNR/SFDR vs. Analog Input Frequency (fIN) AIN = -1dBFS SNR = 66.0dB SFDR = 79dBFS ENOB = 10.6 BITS -20 14994-107 465 365 265 245 225 60 205 FREQUENCY (MHz) SNRFS, -40C SNRFS, +50C SNRFS, +105C 185 250 200 165 150 145 100 125 50 85 0 14994-104 -140 SFDR (dBFS), -40C SFDR (dBFS), +50C SFDR (dBFS), +105C 75 105 -80 80 65 -60 10 AMPLITUDE (dBFS) AD6684 -80 66.9 66.8 66.7 66.6 66.5 -100 66.4 66.3 -120 66.2 66.1 465 ANALOG INPUT FREQUENCY (MHz) 14994-108 365 265 245 225 205 185 165 66.0 145 FREQUENCY (MHz) 125 250 200 105 150 85 100 65 50 10 0 14994-105 -140 Figure 14. SNR vs. Analog Input Frequency (fIN), First and Second Nyquist Zones; AIN at -3 dBFS Figure 11. Single-Tone FFT with fIN = 985 MHz 94 90 93 92 85 SFDR 91 SFDR (dBFS) 89 75 70 88 87 86 85 84 SNR 83 65 82 81 Figure 12. SNR/SFDR vs. Sample Rate (fS), fIN = 155 MHz 465 365 14994-109 ANALOG INPUT FREQUENCY (MHz) 265 245 225 205 185 165 145 125 105 85 10 650 14994-106 625 600 575 525 550 500 475 450 425 400 375 325 350 300 275 250 225 200 SAMPLE RATE (MHz) 65 80 60 175 SNR/SFDR (dBFS) 90 80 Figure 15. SFDR vs. Analog Input Frequency (fIN), First and Second Nyquist Zones; AIN at -3 dBFS Rev. A | Page 15 of 99 AD6684 Data Sheet 0 67.5 AIN1 AND AIN2 = -7dBFS SFDR = 85.9dBFS -20 AMPLITUDE (dBFS) -40 SNR (dBFS) 67.0 66.5 -60 -80 -100 -120 -140 795 14994-110 765 735 705 675 645 615 585 555 525 495 465 ANALOG INPUT FREQUENCY (MHz) 0 50 100 150 14994-113 -160 66.0 250 200 FREQUENCY (MHz) Figure 16. SNR vs. Analog Input Frequency (fIN), Third Nyquist Zone AIN at -3 dBFS Figure 19. Two Tone FFT; fIN1 = 303.5 MHz, fIN2 = 306.5 MHz 94 0 93 92 -20 SFDR/IMD3 (dBc AND dBFS) 91 90 SFDR (dBFS) 89 88 87 86 85 84 83 82 SFDR (dBc) -40 IMD3 (dBc) -60 -80 SFDR (dBFS) -100 -120 IMD3 (dBFS) ANALOG INPUT AMPLITUDE (dBFS) Figure 17. SFDR vs. Analog Input Frequency (fIN), Third Nyquist Zone; AIN at -3 dBFS Figure 20. Two Tone SFDR/IMD3 vs. Analog Input Amplitude (AIN) with fIN1 = 303.5 MHz and fIN2 = 306.5 MHz 0 AIN1 AND AIN2 = -7dBFS SFDR = 86.4dBFS -20 SNR/SFDR (dB) -60 -80 -100 -120 -140 0 50 100 150 200 FREQUENCY (MHz) 250 14994-112 AMPLITUDE (dBFS) -40 -160 0 120 110 100 90 80 70 60 50 40 30 20 10 0 -10 -20 -30 -40 -100 SFDR (dBFS) SNRFS SFDR (dBc) SNR -90 -80 -70 -60 -50 -40 -30 -20 ANALOG INPUT FREQUENCY (MHz) -10 0 Figure 21. SNR/SFDR vs. Analog Input Frequency, fIN = 155 MHz Figure 18. Two Tone FFT; fIN1 = 153.5 MHz, fIN2 = 156.5 MHz Rev. A | Page 16 of 99 14994-115 735 ANALOG INPUT FREQUENCY (MHz) -140 -90 -84 -78 -72 -66 -60 -54 -48 -42 -36 -30 -24 -18 -12 14994-111 705 675 645 615 585 555 525 495 465 80 14994-114 81 Data Sheet 1.0 SFDR (dBFS) 0.8 0.6 SNRFS 0.4 0.2 DNL (LSB) SFDR (dBc) SNR 0 -0.2 -0.4 -0.6 16384 14994-119 15360 14336 13312 12288 11264 9216 10240 8192 7168 6144 5120 -1.0 4096 0 3072 -10 2048 -80 -70 -60 -50 -40 -30 -20 ANALOG INPUT FREQUENCY (MHz) 0 -90 1024 -0.8 14994-116 SNR/SFDR (dB) 120 110 100 90 80 70 60 50 40 30 20 10 0 -10 -20 -30 -40 -100 AD6684 OUTPUT CODE Figure 22. SNR/SFDR vs. Analog Input Frequency, fIN = 305 MHz Figure 25. DNL, fIN = 10.3 MHz 90 6000 5000 80 4000 NUMBER OF HITS 85 SNR 2000 129 JUNCTION TEMPERATURE (C) 14994-117 122 111 91 71 -10 51 0 31 60 11 1000 -31 65 CODE Figure 23. SNR/SFDR vs. Junction Temperature, fIN = 155 MHz Figure 26. Input-Referred Noise Histogram 2.1 2.0 1.5 POWER DISSIPATION (W) 2.0 0.5 0 -0.5 -1.0 1.9 1.8 1.7 1.6 Figure 24. INL, fIN = 10.3 MHz 16384 15360 14336 13312 -38 -21 8 20 43 49 59 TEMPERATURE (C) 14994-118 OUTPUT CODE 12288 11264 10240 9216 8192 7168 6144 5120 4096 3072 2048 1.5 0 -2.0 81 100 115 14994-121 -1.5 1024 INL (LSB) 1.0 Figure 27. NSR Mode Power Dissipation vs. Junction Temperature Rev. A | Page 17 of 99 14994-120 70 3000 N - 10 N-9 N-8 N-7 N-6 N-5 N-4 N-3 N-2 N-1 0 N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 N+9 N + 10 75 -54 SNR/SFRDR (dBFS) SFDR Data Sheet 1.85 0 1.80 -20 1.75 1.70 NSR 1.65 1.60 1.55 -60 -80 -100 -120 1.50 250 300 350 500 400 450 SAMPLE RATE (MSPS) 550 600 650 -1.25 8.75 0 18.75 28.75 AIN = -1dBFS SNRFS = 74.50dB SFDR = 100.68dBFS -20 -40 -60 -80 -100 -60 -80 -100 -120 -120 -140 -140 -75 -25 25 FREQUENCY (MHz) 75 125 -160 -15.625 14994-123 -160 -125 Figure 29. DDC Mode (4 DDCs, DCM2, L, M, and F = 244) with fIN = 305 MHz -10.625 4.375 9.375 14.375 Figure 32. DDC Mode (4 DDCs, Decimate by 16, L, M, and F = 148) with fIN = 305 MHz AIN = -1dBFS SNRFS = 71.80dB SFDR = 98.27dBFS -20 -0.625 FREQUENCY (MHz) 0 0 -5.625 14994-126 AMPLITUDE (dBFS) -40 AIN = -1dBFS SNRFS = 74.50dB SFDR = 100.68dBFS -20 -40 AMPLITUDE (dBFS) -40 -60 -80 -100 -60 -80 -100 -120 -120 -140 -140 -160 57.5 62.5 5 14994-124 FREQUENCY (MHz) 37.5 17.5 0 -22.5 -42.5 -62.5 -160 Figure 30. DDC Mode (4 DDCs, Decimate by 4, L, M, and F = 148) with fIN = 305 MHz 25 45 65 85 FREQUENCY (MHz) 105 125 14994-127 AMPLITUDE (dBFS) -11.25 FREQUENCY (MHz) AIN = -1dBFS SNRFS = 65.94dB SFDR = 89.01dBFS -20 -21.25 Figure 31. DDC Mode (4 DDCs, Decimate by 8, L, M, and F = 148) with fIN = 305 MHz Figure 28. Power Dissipation vs. Sample Rate (fS) 0 -160 -31.25 14994-122 1.40 14994-125 -140 1.45 AMPLITUDE (dBFS) AIN = -1dBFS SNRFS = 71.80dB SFDR = 98.27dBFS -40 AMPLITUDE (dBFS) POWER DISSIPATION (W) AD6684 Figure 33. NSR Mode (Decimate by 2, L, M, and F = 124) with fIN = 305 MHz Rev. A | Page 18 of 99 Data Sheet AD6684 Figure 37. SFDR vs. Analog Input Frequency with Different Buffer Current Settings (Third Nyquist Zone) 67.0 66.9 66.8 66.7 66.6 SFDR (dBFS) 66.4 66.3 66.2 66.1 66.0 65.9 65.8 65.7 65.6 DIFFERENTIAL VOLTAGE (V) ANALOG INPUT FREQUENCY (MHz) Figure 35. SNR vs. Clock Amplitude (Differential Voltage), fIN = 155.3 MHz Figure 38. SFDR vs. Analog Input Frequency with Different Buffer Current Settings (Fourth Nyquist Zone) 69 = 160A = 200A = 240A = 280A INPUT FULL SCALE = 2.16V 68 SNR (dBFS) BUFFER CURRENT BUFFER CURRENT BUFFER CURRENT BUFFER CURRENT 67 66 INPUT FULL SCALE = 1.44V 65 465 365 14994-133 ANALOG INPUT FREQUENCY (MHz) Figure 36. SFDR vs. Analog Input Frequency with Different Buffer Current Settings (First and Second Nyquist Zones) 265 245 225 205 185 165 145 125 105 85 10 465 365 14994-130 ANALOG INPUT FREQUENCY (MHz) 265 245 225 205 185 165 145 125 105 85 65 64 10 SFDR (dBFS) = 320A = 360A = 400A = 440A 730 760 790 820 850 880 910 940 970 1030 1060 1090 1120 1150 1180 1210 1240 1270 1300 1330 1360 1390 1420 1450 1480 1510 1540 1570 1600 1630 1660 1690 1720 1750 1780 1810 14994-129 0.118 0.132 0.148 0.166 0.185 0.207 0.234 0.262 0.293 0.328 0.370 0.416 0.468 0.526 0.587 0.693 0.778 0.873 0.979 1.091 1.209 1.322 1.482 1.653 1.833 65.5 BUFFER CURRENT BUFFER CURRENT BUFFER CURRENT BUFFER CURRENT 65 SNR (dBFS) 66.5 -80 -78 -76 -74 -72 -70 -68 -66 -64 -62 -60 -58 -56 -54 -52 -50 -48 -46 -44 -42 -40 14994-132 Figure 34. NSR Mode (LMF = 222) with fIN = 305 MHz -95 -94 -93 -92 -91 -90 -89 -88 -87 -86 -85 -84 -83 -82 -81 -80 -79 -78 -77 -76 -75 735 ANALOG INPUT FREQUENCY (MHz) 14994-131 465 250 FREQUENCY (MHz) 14994-128 225 200 175 150 125 100 75 50 25 0 -140 705 -120 = 200A = 240A = 280A = 320A 675 -100 BUFFER CURRENT BUFFER CURRENT BUFFER CURRENT BUFFER CURRENT 645 -80 615 -60 585 SFDR (dBFS) AMPLITUDE (dBFS) -40 555 -20 -85 -84 -83 -82 -81 -80 -79 -78 -77 -76 -75 -74 -73 -72 -71 -70 -69 -68 -67 -66 -65 525 AIN = -1dBFS SNRFS = 70.7dB SFDR = 82dBFS 495 0 Figure 39. SNR vs. Analog Input Frequency with Different Analog Input Full Scales (First and Second Nyquist Zones) Rev. A | Page 19 of 99 Data Sheet 565 14994-136 465 365 265 245 225 205 185 165 145 795 14994-137 765 735 705 675 645 ANALOG INPUT FREQUENCY (MHz) Figure 43. SFDR vs. Analog Input Frequency with Different Analog Input Full Scales (Third Nyquist Zone) -81 INPUT FULL SCALE = 1.44V -79 -77 -75 -73 SFDR (dBFS) -71 -69 INPUT FULL SCALE = 2.16V -67 -65 -63 -61 -59 1780 1720 1660 14994-138 ANALOG INPUT FREQUENCY (MHz) 1600 1540 1480 1420 1360 1300 1240 1180 1120 970 1060 -55 910 -57 850 Figure 41. SNR vs. Analog Input Frequency with Different Analog Input Full Scales (Fourth Nyquist Zone) 615 465 14994-135 730 760 790 820 850 880 910 940 970 1000 1030 1060 1090 1120 1150 1180 1210 1240 1270 1300 1330 1360 1390 1420 1450 1480 1510 1540 1570 1600 1630 1660 1690 1720 1750 1780 1810 62 585 63 INPUT FULL SCALE = 2.16V 555 64 INPUT FULL SCALE = 1.44V 525 SFDR (dBFS) SNR (dBFS) 66 -90 -89 -88 -87 -86 -85 -84 -83 -82 -81 -80 -79 -78 -77 -76 -75 -74 -73 -72 -71 -70 495 INPUT FULL SCALE = 2.16V INPUT FULL SCALE = 1.44V 125 Figure 42. SFDR vs. Analog Input Frequency with Different Analog Input Full Scales (First and Second Nyquist Zones) 68 ANALOG INPUT FREQUENCY (MHz) 85 ANALOG INPUT FREQUENCY (MHz) 790 Figure 40. SNR vs. Analog Input Frequency with Different Analog Input Full Scales (Third Nyquist Zone) 65 105 10 735.3 ANALOG INPUT FREQUENCY (MHz) 67 INPUT FULL SCALE = 2.16V 14994-134 705.3 675.3 645.3 615.3 585.3 555.3 525.3 495.3 INPUT FULL SCALE = 1.44V INPUT FULL SCALE = 1.44V 65 SFDR (dBFS) INPUT FULL SCALE = 2.16V -90 -89 -88 -87 -86 -85 -84 -83 -82 -81 -80 -79 -78 -77 -76 -75 -74 -73 -72 -71 -70 730 69.0 68.8 68.6 68.4 68.2 68.0 67.8 67.6 67.4 67.2 67.0 66.8 66.6 66.4 66.2 66.0 65.8 65.6 65.4 65.2 65.0 64.8 64.6 64.4 64.2 64.0 465.3 SNR (dBFS) AD6684 Figure 44. SFDR vs. Analog Input Frequency with Different Analog Input Full Scales (Fourth Nyquist Zone) Rev. A | Page 20 of 99 Data Sheet AD6684 EQUIVALENT CIRCUITS AVDD3 AVDD3 VIN+x 3.5pF AVDD3 100 400 EMPHASIS/SWING CONTROL (SPI) VCM BUFFER 10pF DRVDD AVDD3 SERDOUTABx+/ SERDOUTCDx+ x = 0, 1 DATA+ AVDD3 VIN-x DRGND OUTPUT DRIVER AIN CONTROL (SPI) DATA- SERDOUTABx-/ SERDOUTCDx- x = 0, 1 DRGND 14994-024 3.5pF DRVDD Figure 45. Analog Inputs 14994-027 100 Figure 48. Digital Outputs DRVDD DRGND 2.5k AVDD1 CLK+ SYNCINB+AB/ SYNCINB+CD 25 DRVDD 100 10k 1.9pF 130k DRGND LEVEL TRANSLATOR DRGND 16k CMOS PATH SYNCINB PIN CONTROL (SPI) 130k DRVDD AVDD1 16k 1.9pF VCM = 0.69V 100 DRGND DRGND Figure 49. SYNCINBAB, SYNCINBCD Inputs Figure 46. Clock Inputs SYSREF+ 10k 14994-028 SYNCINB-AB/ SYNCINB-CD 25 14994-025 CLK- 100 10k 1.9pF 130k SPIVDD LEVEL TRANSLATOR ESD PROTECTED 130k SCLK 10k 1.9pF 56k Figure 47. SYSREF Inputs ESD PROTECTED DGND Figure 50. SCLK Input Rev. A | Page 21 of 99 DGND 14994-029 100 14994-026 SYSREF- SPIVDD AD6684 Data Sheet SPIVDD ESD PROTECTED SPIVDD ESD PROTECTED 56k PDWN/ STBY ESD PROTECTED ESD PROTECTED DGND 14994-030 DGND DGND DGND Figure 54. PDWN/STBY Input Figure 51. CSB Input SPIVDD SPIVDD SDI ESD PROTECTED DGND ESD PROTECTED AVDD2 SPIVDD DGND DGND DGND AGND Figure 52. SDIO Input SPIVDD FD JESD204B LMFC 56k JESD204B SYNC DGND DGND FD_x PIN CONTROL (SPI) DGND 14994-032 ESD PROTECTED VREF PIN CONTROL (SPI) Figure 55. VREF Input/Output SPIVDD ESD PROTECTED EXTERNAL REFERENCE VOLTAGE INPUT VREF SDO TEMPERATURE DIODE VOLTAGE Figure 53. FD_A/FD_B/FD_C/FD_D Outputs Rev. A | Page 22 of 99 14994-034 56k 14994-031 SDIO FD_A/FD_B/ FD_C/FD_D PDWN CONTROL (SPI) 14994-033 CSB Data Sheet AD6684 THEORY OF OPERATION ADC ARCHITECTURE Differential Input Configurations The architecture of the AD6684 consists of an input buffered pipelined ADC. The input buffer is designed to provide a 200 termination impedance to the analog input signal. The equivalent circuit diagram of the analog input termination is shown in Figure 45. There are several ways to drive the AD6684, either actively or passively. However, optimum performance is achieved by driving the analog input differentially. For applications where SNR and SFDR are key parameters, differential transformer coupling is the recommended input configuration (see Figure 57 and Figure 58) because the noise performance of most amplifiers is not adequate to achieve the true performance of the AD6684. The input buffer provides a linear high input impedance (for ease of drive) and reduces kickback from the ADC. The buffer is optimized for high linearity, low noise, and low power. The quantized outputs from each stage are combined into a final 14-bit result in the digital correction logic. The pipelined architecture permits the first stage to operate with a new input sample while, at the same time, the remaining stages operate with the preceding samples. Sampling occurs on the rising edge of the clock. For low to midrange frequencies, a double balun or double transformer network (see Figure 57) is recommended for optimum performance of the AD6684. For higher frequencies in the second or third Nyquist zones, it is recommended to remove some of the front-end passive components to ensure wideband operation (see Figure 58). ANALOG INPUT CONSIDERATIONS Input Common Mode The analog input to the AD6684 is a differential buffer with an internal common-mode voltage of 1.34 V. The clock signal alternately switches the input circuit between sample mode and hold mode. Either a differential capacitor or two single-ended capacitors can be placed on the inputs to provide a matching passive network. This configuration ultimately creates a low-pass filter at the input, which limits unwanted broadband noise. See Figure 57 and Figure 58 for details on input network recommendations. For more information, see the Analog Dialogue article "Transformer-Coupled Front-End for Wideband A/D Converters" (Volume 39, April 2005). In general, the precise values depend on the application. The analog inputs of the AD6684 are internally biased to the common mode as shown in Figure 56. For best dynamic performance, the source impedances driving VIN+x and VIN-x must be matched such that common-mode settling errors are symmetrical. These errors are reduced by the common-mode rejection of the ADC. An internal reference buffer creates a differential reference that defines the span of the ADC core. Maximum SNR performance is achieved by setting the ADC to the largest span in a differential configuration. In the case of the AD6684, the available span is programmable through the SPI port from 1.44 V p-p to 2.16 V p-p differential with 1.80 V p-p differential being the default. Dither For dc-coupled applications, the recommended operation procedure is to export the common-mode voltage to the VCM_CD/VREF pin using the SPI writes listed in this section. The common-mode voltage must be set by the exported value to ensure proper ADC operation. Disconnect the internal common-mode buffer from the analog input using Register 0x1908. When performing SPI writes for dc coupling operation, use the following register settings in order: 1. 2. 3. 4. 5. 6. 7. 8. The AD6684 has internal on-chip dither circuitry that improves the ADC linearity and SFDR, particularly at smaller signal levels. A known but random amount of white noise is injected into the input of the AD6684. This dither improves the small signal linearity within the ADC transfer function and is precisely subtracted out digitally. The dither is turned on by default and does not reduce the ADC input dynamic range. The data sheet specifications and limits are obtained with the dither turned on. The dither can be disabled using SPI writes to Register 0x0922. Disabling the dither can slightly improve the SNR (by about 0.2 dB) at the expense of the small signal SFDR. Rev. A | Page 23 of 99 Set Register 0x1908, Bit 2 to 1; this setting disconnects the internal common-mode buffer from the analog input. Set Register 0x18A6 to 0x00; this setting turns off the voltage reference. Set Register 0x18E6 to 0x00; this setting turns off the temperature diode export. Set Register 0x18E0 to 0x04. Set Register 0x18E1 to 0x1C. Set Register 0x18E2 to 0x14. Set Register 0x18E3, Bit 6 to 0x01; this setting turns on the VCM export. Set Register 0x18E3, Bits[5:0] to the buffer current setting (copy the buffer current setting from Register 0x1A4C and Register 0x1A4D to improve the accuracy of the commonmode export). AD6684 Data Sheet Analog Input Controls and SFDR Optimization Using Register 0x1A4C and Register 0x1A4D, the buffer currents on each channel can be scaled to optimize the SFDR over various input frequencies and bandwidths of interest. As the input buffer currents are set, the amount of current required by the AVDD3 supply changes. This relationship is shown in Figure 59. For a complete list of buffer current settings, see Table 46. The AD6684 offers flexible controls for the analog inputs, such as buffer current and input full-scale adjustment. All of the available controls are shown in Figure 56. AVDD3 AVDD3 VIN+x 3.5pF AVDD3 100 400 VCM BUFFER 10pF 100 AVDD3 AVDD3 VIN-x 3.5pF 14994-037 AIN CONTROL (SPI) Figure 56. Analog Input Controls AGND 0.1F 10 2pF 0 10 50 VIN+x 10 0.1F BALUN 2pF AGND 0.1F 50 10 10 0 10 VIN-x 14994-038 2pF AGND Figure 57. Differential Transformer Coupled Configuration for First and Second Nyquist Frequencies AGND 0.1F 10 DNI 0 10 50 VIN+x DNI 0.1F BALUN DNI 0.1F 50 10 DNI 0 10 DNI AGND VIN-x 14994-039 AGND Figure 58. Differential Transformer Coupled Configuration for Third and Fourth Nyquist Zones Rev. A | Page 24 of 99 Data Sheet AD6684 0.20 VIN+A/ VIN+B 0.18 VIN-A/ VIN-B INTERNAL VREF GENERATOR 0.12 0.10 INPUT FULL-SCALE RANGE ADJUST SPI REGISTER (0x1910) 0.08 VREF 0.06 VREF PIN CONTROL SPI REGISTER (0x18A6) 0.04 150 200 250 300 350 400 450 500 550 600 BUFFER CURRENT SETTING (A) 14994-139 0.02 0 100 ADC CORE FULL-SCALE VOLTAGE ADJUST Figure 60. Internal Reference Configuration and Controls The SPI Register 0x18A6 enables the user to either use this internal 0.5 V reference, or to provide an external 0.5 V reference. When using an external voltage reference, provide a 0.5 V reference. The full-scale adjustment is made using the SPI, irrespective of the reference voltage. For more information on adjusting the full-scale level of the AD6684, refer to the Memory Map section. Figure 59. AVDD3 Power vs. Buffer Current Setting In certain high frequency applications, the SFDR can be improved by reducing the full-scale setting. Table 9 shows the recommended buffer current settings for the different analog input frequency ranges. Table 9. SFDR Optimization for Input Frequencies Nyquist Zone First, Second, and Third Nyquist Fourth Nyquist The SPI writes required to use the external voltage reference, in order, are as follows: Input Buffer Current Control Setting, Register 0x1A4C and Register 0x1A4D 240 (Register 0x1A4C, Bits[5:0] = Register 0x1A4D, Bits[5:0] = 01100) 400 (Register 0x1A4C, Bits[5:0] = Register 0x1A4D, Bits[5:0] = 10100) 1. 2. 3. Absolute Maximum Input Swing The absolute maximum input swing allowed at the inputs of the AD6684 is 4.3 V p-p differential. Signals operating near or at this level can cause permanent damage to the ADC. VOLTAGE REFERENCE A stable and accurate 0.5 V voltage reference is built into the AD6684. This internal 0.5 V reference is used to set the fullscale input range of the ADC. The full-scale input range can be adjusted via the ADC function register (Register 0x1910). For more information on adjusting the input swing, see Table 46. Figure 60 shows the block diagram of the internal 0.5 V reference controls. Set Register 0x18E3 to 0x00 to turn off VCM export. Set Register 0x18E6 to 0x00 to turn off temperature diode export. Set Register 0x18A6 to 0x01 to turn on the external voltage reference. The use of an external reference may be necessary, in some applications, to enhance the gain accuracy of the ADC or to improve thermal drift characteristics. The external reference has to be a stable 0.5 V reference. The ADR130 is a good option for providing the 0.5 V reference. Figure 61 shows how the ADR130 can be used to provide the external 0.5 V reference to the AD6684. The grayed out areas show unused blocks within the AD6684 while using the ADR130 to provide the external reference. INTERNAL VREF GENERATOR FULL-SCALE VOLTAGE ADJUST ADR130 INPUT NC 6 1 NC 2 GND SET 5 3 VIN 0.1F VOUT 4 VREF 0.1F 14994-040 0.14 VREF PIN AND FULL-SCALE VOLTAGE CONTROL Figure 61. External Reference Using ADR130 Rev. A | Page 25 of 99 14994-042 AVDD3 POWER (W) 0.16 AD6684 Data Sheet CLOCK INPUT CONSIDERATIONS Input Clock Divider For optimum performance, drive the AD6684 sample clock inputs (CLK+ and CLK-) with a differential signal. This signal is typically ac-coupled to the CLK+ and CLK- pins via a transformer or clock drivers. These pins are biased internally and require no additional biasing. The AD6684 contains an input clock divider with the ability to divide the input clock by 1, 2, 4, and 8. The divider ratios can be selected using Register 0x0108 (see Figure 65). Figure 62 shows a preferred method for clocking the AD6684. The low jitter clock source is converted from a single-ended signal to a differential signal using an RF transformer. In applications where the clock input is a multiple of the sample clock, care must be taken to program the appropriate divider ratio into the clock divider before applying the clock signal. This ratio ensures that the current transients during device startup are controlled. CLK+ 0.1F CLK+ 100 50 CLK- /2 ADC /4 CLK- 0.1F /8 Figure 62. Transformer-Coupled Differential Clock REG 0x0108 Another option is to ac couple a differential CML or LVDS signal to the sample clock input pins, as shown in Figure 63 and Figure 64. 3.3V 71 10pF 33 33 Z0 = 50 0.1F Figure 65. Clock Divider Circuit The AD6684 clock divider can be synchronized using the external SYSREF input. A valid SYSREF causes the clock divider to reset to a programmable state. This synchronization feature allows multiple devices to have their clock dividers aligned to guarantee simultaneous input sampling. Clock Jitter Considerations CLK+ CLK- 0.1F High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given input frequency (fA) due only to aperture jitter (tJ) can be calculated by 14994-044 ADC Z0 = 50 14994-046 1:1Z 14994-043 CLOCK INPUT Figure 63. Differential CML Sample Clock SNR = -20 x log (2 x x fA x tJ) CLK+ 0.1F LVDS DRIVER CLK+ 100 CLK- CLOCK INPUT 501 501 ADC CLK- 0.1F 150 RESISTORS ARE OPTIONAL. 14994-045 CLOCK INPUT In this equation, the rms aperture jitter represents the root mean square of all jitter sources, including the clock input, analog input signal, and ADC aperture jitter specifications. IF undersampling applications are particularly sensitive to jitter (see Figure 66). 130 12.5fS 25fS 50fS 100fS 200fS 400fS 800fS 120 Figure 64. Differential LVDS Sample Clock 110 Clock Duty Cycle Considerations SNR (dB) 100 Typical high speed ADCs use both clock edges to generate a variety of internal timing signals. The AD6684 contains an internal clock divider and a duty cycle stabilizer (DCS). In applications where the clock duty cycle cannot be guaranteed to be 50%, a higher multiple frequency clock along with the usage of the clock divider is recommended. When it is not possible to provide a higher frequency clock, it is recommended to turn on the DCS using Register 0x011C. The output of the divider offers a 50% duty cycle, high slew rate (fast edge) clock signal to the internal ADC. See the Memory Map section for more details on using this feature. Rev. A | Page 26 of 99 90 80 70 60 50 40 30 10 100 1000 10000 ANALOG INPUT FREQUENCY (MHz) Figure 66. Ideal SNR vs. Analog Input Frequency and Jitter 14994-047 0.1F 0.1F Data Sheet AD6684 Figure 66 shows the estimated SNR of the AD6684 across input frequency for different clock induced jitter values. The SNR can be estimated by using the following equation: - SNR JITTER - SNRADC SNR(dBFS) = -10log 10 10 + 10 10 that other voltages may be exported to the same pin at the same time, which may result in undefined behavior. Thus, to ensure a proper readout, switch off all other voltage exporting circuits as detailed in this section. The SPI writes required to export the temperature diode are as follows (see Table 46 for more information): 1. 2. 3. Set Register 0x0009 to 0x03 to select both cores. Set Register 0x18E3 to 0x00 to turn off VCM export. Set Register 0x18A6 to 0x00 to turn off the voltage reference. Set Register 0x18E6 to 0x01 to turn on temperature diode export. The typical voltage response of the temperature diode is shown in Figure 67. However, it is recommended to take measurements from a pair of diodes into account when introducing another step. Set Register 0x18E6 to 0x02 to turn on the second temperature diode (that is, 20x the size) of the pair. 4. 5. The AD6684 has a PDWN/STBY pin that can be used to configure the device in power-down or standby mode. The default operation is power-down. The PDWN/STBY pin is a logic high pin. When in power-down mode, the JESD204B link is disrupted. The power-down option can also be set via Register 0x003F and Register 0x0040. In standby mode, the JESD204B link is not disrupted and transmits zeros for all converter samples. This setting can be changed using Register 0x0571, Bit 7 to select /K/ characters. TEMPERATURE DIODE The AD6684 contains a diode-based temperature sensor for measuring the temperature of the die. The diode can output a voltage and serve as a coarse temperature sensor to monitor the internal die temperature. For the method utilizing two diodes simultaneously giving a more accurate result, see the AN-1432 Application Note, Practical Thermal Modeling and Measurements in High Power ICs. 0.80 TEMPERATURE DIODE VOLTAGE (V) Power-Down/Standby Mode The temperature diode voltage can be output to the VCM_CD/ VREF pin using the SPI. Use Register 0x18E6 to enable or disable the diode. Register 0x18E6 is a local register. Both cores must be selected in the core index register (Register 0x0009 = 0x03) to enable the temperature diode readout. It is important to note Rev. A | Page 27 of 99 0.75 0.70 0.65 0.60 0.55 0.50 -40 -20 0 20 40 60 80 100 JUNCTION TEMPERATURE (C) Figure 67. Temperature Diode Voltage vs. Junction Temperature 14994-048 Treat the clock input as an analog signal in cases where aperture jitter may affect the dynamic range of the AD6684. Separate the power supplies for clock drivers from the ADC output driver supplies to avoid modulating the clock signal with digital noise. If the clock is generated from another type of source (by gating, dividing, or other methods), retime the clock by the original clock at the last step. Refer to the AN-501 Application Note and the AN-756 Application Note for more in-depth information about jitter performance as it relates to ADCs. AD6684 Data Sheet ADC OVERRANGE AND FAST DETECT The FD indicator is asserted if the input magnitude exceeds the value programmed in the fast detect upper threshold registers, located at Register 0x0247 and Register 0x0248. The selected threshold register is compared with the signal magnitude at the output of the ADC. The fast upper threshold detection has a latency of 30 clock cycles (maximum). The approximate upper threshold magnitude is defined by In receiver applications, it is desirable to have a mechanism to reliably determine when the converter is about to be clipped. The standard overrange bit in the JESD204B outputs provides information on the state of the analog input that is of limited usefulness. Therefore, it is helpful to have a programmable threshold below full scale that allows time to reduce the gain before the clip actually occurs. In addition, because input signals can have significant slew rates, the latency of this function is of major concern. Highly pipelined converters can have significant latency. The AD6684 contains fast detect circuitry for individual channels to monitor the threshold and to assert the FD_A, FD_B, FD_C, and FD_D pins. Upper Threshold Magnitude (dBFS) = 20log (Threshold Magnitude/213) The FD indicators are not cleared until the signal drops below the lower threshold for the programmed dwell time. The lower threshold is programmed in the fast detect lower threshold registers, located at Register 0x0249 and Register 0x024A. The fast detect lower threshold register is a 13-bit register that is compared with the signal magnitude at the output of the ADC. This comparison is subject to the ADC pipeline latency, but is accurate in terms of converter resolution. The lower threshold magnitude is defined by ADC OVERRANGE The ADC overrange indicator is asserted when an overrange is detected on the input of the ADC. The overrange indicator can be embedded within the JESD204B link as a control bit. The latency of this overrange indicator matches the sample latency. FAST THRESHOLD DETECTION (FD_A, FD_B, FD_C AND FD_D) Lower Threshold Magnitude (dBFS) = 20log (Threshold Magnitude/213) The FD bits (Register 0x0040, Bits[5:0]) are immediately set whenever the absolute value of the input signal exceeds the programmable upper threshold level. The FD bits are only cleared when the absolute value of the input signal drops below the lower threshold level for greater than the programmable dwell time. This feature provides hysteresis and prevents the FD bits from excessively toggling. For example, to set an upper threshold of -6 dBFS, write 0xFFF to Register 0x0247 and Register 0x0248. To set a lower threshold of -10 dBFS, write 0xA1D to Register 0x0249 and Register 0x024A. The dwell time can be programmed from 1 to 65,535 sample clock cycles by placing the desired value in the fast detect dwell time registers, located at Register 0x024B and Register 0x024C. See the Memory Map section (Register 0x040, and Register 0x245 to Register 0x24C in Table 46) for more details. The operation of the upper threshold and lower threshold registers, along with the dwell time registers, is shown in Figure 68. UPPER THRESHOLD DWELL TIME TIMER RESET BY RISE ABOVE LOWER THRESHOLD DWELL TIME FD_A OR FD_B Figure 68. Threshold Settings for the FD_A and FD_B Signals Rev. A | Page 28 of 99 TIMER COMPLETES BEFORE SIGNAL RISES ABOVE LOWER THRESHOLD 14994-050 MIDSCALE LOWER THRESHOLD Data Sheet AD6684 SIGNAL MONITOR The signal monitor block provides additional information about the signal being digitized by the ADC. The signal monitor computes the peak magnitude of the digitized signal. This information can be used to drive an AGC loop to optimize the range of the ADC in the presence of real-world signals. The results of the signal monitor block can be obtained either by reading back the internal values from the SPI port or by embedding the signal monitoring information into the JESD204B interface as special control bits. A global, 24-bit programmable period controls the duration of the measurement. Figure 69 shows the simplified block diagram of the signal monitor block. FROM MEMORY MAP SIGNAL MONITOR PERIOD REGISTER (SMPR) 0x0271, 0x0272, 0x0273 DOWN COUNTER When the monitor period timer reaches a count of 1, the 13-bit peak level value is transferred to the signal monitor holding register, which can be read through the memory map or output through the SPORT over the JESD204B interface. The monitor period timer is reloaded with the value in the SMPR, and the countdown restarts. In addition, the magnitude of the first input sample is updated in the magnitude storage register, and the comparison and update procedure, as explained previously, continues. IS COUNT = 1? LOAD FROM INPUT LOAD LOAD SIGNAL MONITOR HOLDING REGISTER SPORT OVER JESD204B TO SPORT OVER JESD204B AND MEMORY MAP 14994-051 CLEAR MAGNITUDE STORAGE REGISTER decimated clock rate. The magnitude of the input signal is compared with the value in the internal magnitude storage register (not accessible to the user), and the greater of the two is updated as the current peak level. The initial value of the magnitude storage register is set to the current ADC input signal magnitude. This comparison continues until the monitor period timer reaches a count of 1. COMPARE A>B Figure 69. Signal Monitor Block The peak detector captures the largest signal within the observation period. The detector only observes the magnitude of the signal. The resolution of the peak detector is a 13-bit value, and the observation period is 24 bits and represents converter output samples. The peak magnitude can be derived by using the following equation: Peak Magnitude (dBFS) = 20log(Peak Detector Value/213) The magnitude of the input port signal is monitored over a programmable time period, which is determined by the signal monitor period register (SMPR). The peak detector function is enabled by setting Bit 1 of Register 0x0270 in the signal monitor control register. The 24-bit SMPR must be programmed before activating this mode. After enabling peak detection mode, the value in the SMPR is loaded into a monitor period timer, which decrements at the The signal monitor data can also be serialized and sent over the JESD204B interface as control bits. These control bits must be deserialized from the samples to reconstruct the statistical data. The signal control monitor function is enabled by setting Bits[1:0] of Register 0x0279 and Bit 1 of Register 0x027A. Figure 70 shows two different example configurations for the signal monitor control bit locations inside the JESD204B samples. A maximum of three control bits can be inserted into the JESD204B samples; however, only one control bit is required for the signal monitor. Control bits are inserted from MSB to LSB. If only one control bit is to be inserted (CS = 1), only the most significant control bit is used (see Example Configuration 1 and Example Configuration 2 in Figure 70). To select the SPORT over JESD204B option, program Register 0x0559, Register 0x055A, and Register 0x058F. See Table 46 for more information on setting these bits. Figure 71 shows the 25-bit frame data that encapsulates the peak detector value. The frame data is transmitted MSB first with five 5-bit subframes. Each subframe contains a start bit that can be used by a receiver to validate the deserialized data. Figure 72 shows the SPORT over JESD204B signal monitor data with a monitor period timer set to 80 samples. Rev. A | Page 29 of 99 AD6684 Data Sheet 16-BIT JESD204B SAMPLE SIZE (N' = 16) EXAMPLE CONFIGURATION 1 (N' = 16, N = 15, CS = 1) 1-BIT CONTROL BIT (CS = 1) 15-BIT CONVERTER RESOLUTION (N = 15) 15 S[14] X 14 S[13] X 13 S[12] X 12 11 S[11] X 10 S[10] X 9 S[9] X 8 S[8] X 7 S[7] X 6 S[6] X 5 S[5] X S[4] X 4 S[3] X 3 S[2] X 2 S[1] X 1 0 S[0] X CTRL [BIT 2] X SERIALIZED SIGNAL MONITOR FRAME DATA 16-BIT JESD204B SAMPLE SIZE (N' = 16) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 S[13] X S[12] X S[11] X S[10] X S[9] X S[8] X S[7] X S[6] X S[5] X S[4] X S[3] X S[2] X S[1] X S[0] X CTRL [BIT 2] X TAIL X SERIALIZED SIGNAL MONITOR FRAME DATA Figure 70. Signal Monitor Control Bit Locations 5-BIT SUBFRAMES 5-BIT IDLE SUBFRAME (OPTIONAL) 25-BIT FRAME IDLE 1 IDLE 1 IDLE 1 IDLE 1 IDLE 1 5-BIT IDENTIFIER START 0 SUBFRAME ID[3] 0 ID[2] 0 ID[1] 0 ID[0] 1 5-BIT DATA MSB SUBFRAME START 0 P[12] P[11] P[10] P[9] 5-BIT DATA SUBFRAME START 0 P[8] P[7] P[6] P5] 5-BIT DATA SUBFRAME START 0 P[4] P[3] P[2] P[1] 5-BIT DATA LSB SUBFRAME START 0 P[0] 0 0 0 P[ ] = PEAK MAGNITUDE VALUE 14994-053 EXAMPLE CONFIGURATION 2 (N' = 16, N = 14, CS = 1) Figure 71. SPORT over JESD204B Signal Monitor Frame Data Rev. A | Page 30 of 99 14994-052 1 CONTROL BIT 1 TAIL (CS = 1) BIT 14-BIT CONVERTER RESOLUTION (N = 14) Data Sheet AD6684 SMPR = 80 SAMPLES (0x0271 = 0x50; 0x0272 = 0x00; 0x0273 = 0x00) 80 SAMPLE PERIOD PAYLOAD 3 25-BIT FRAME (N) IDENTIFIER DATA MSB DATA DATA DATA LSB IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE 80 SAMPLE PERIOD PAYLOAD 3 25-BIT FRAME (N + 1) IDENTIFIER DATA MSB DATA DATA DATA LSB IDLE IDLE IDLE IDLE IDLE 80 SAMPLE PERIOD IDENTIFIER DATA MSB DATA DATA DATA LSB IDLE IDLE IDLE IDLE IDLE Figure 72. SPORT over JESD204B Signal Monitor Example with Period = 80 Samples Rev. A | Page 31 of 99 14994-054 PAYLOAD 3 25-BIT FRAME (N + 2) AD6684 Data Sheet DIGITAL DOWNCONVERTER (DDC) The AD6684 includes four DDCs that provide filtering and reduce the output data rate. This digital processing section includes an NCO, a half-band decimating filter, a finite impulse response (FIR) filter, a gain stage, and a complex to real conversion stage. Each of these processing blocks has control lines that allow it to be independently enabled and disabled to provide the desired processing function. Each pair of ADC channels has two DDCs (DDC0 and DDC1) for a total of four DDCs. The digital downconverter can be configured to output either real data or complex output data. The DDCs output a 16-bit stream. To enable this operation, the converter number of bits, N, is set to a default value of 16, even though the analog core only outputs 14 bits. In full bandwidth operation, the ADC outputs are 9-bit words followed by seven zeros, unless the tail bits are enabled. DDC I/Q INPUT SELECTION The AD6684 has four ADC channels and four DDC channels. Each DDC channel has two input ports that can be paired to support both real and complex inputs through the I/Q crossbar mux. For real signals, both DDC input ports must select the same ADC channel (that is, DDC Input Port I = ADC Channel A and DDC Input Port Q = ADC Channel A). For complex signals, each DDC input port must select different ADC channels (that is, DDC Input Port I = ADC Channel A and DDC Input Port Q = ADC Channel B, or DDC Input Port I = ADC Channel C and DDC Input Port Q = ADC Channel D). The inputs to each DDC are controlled by the DDC input selection registers (Register 0x0311 and Register 0x0331) in conjunction with the pair index register (Register 0x0009). See Table 46 for information on how to configure the DDCs. DDC I/Q OUTPUT SELECTION Each DDC channel has two output ports that can be paired to support both real and complex outputs. For real output signals, only the DDC Output Port I is used (the DDC Output Port Q is invalid). For complex I/Q output signals, both DDC Output Port I and DDC Output Port Q are used. The I/Q outputs to each DDC channel are controlled by the DDC complex to real enable bit, Bit 3 in the DDC control registers (Register 0x0310 and Register 0x0330) in conjunction with the pair index register (Register 0x0009). The Chip Q ignore bit in the chip mode register (Register 0x0200, Bit 5) controls the chip output muxing of all the DDC channels. When all DDC channels use real outputs, set this bit high to ignore all DDC Q output ports. When any of the DDC channels are set to use complex I/Q outputs, the user must clear this bit to use both DDC Output Port I and DDC Output Port Q. For more information, see Figure 81. DDC GENERAL DESCRIPTION The four DDC blocks are used to extract a portion of the full digital spectrum captured by the ADC(s). The DDC blocks are intended for IF sampling or oversampled baseband radios requiring wide bandwidth input signals. Each DDC block contains the following signal processing stages: * * * * Frequency translation stage (optional) Filtering stage Gain stage (optional) Complex to real conversion stage (optional) Frequency Translation Stage (Optional) This stage consists of a 48-bit complex NCO and quadrature mixers that can be used for frequency translation of both real and complex input signals. This stage shifts a portion of the available digital spectrum down to baseband. Filtering Stage After shifting down to baseband, this stage decimates the frequency spectrum using a chain of up to four half-band, lowpass filters for rate conversion. The decimation process lowers the output data rate, which in turn reduces the output interface rate. Gain Stage (Optional) To compensate for losses associated with mixing a real input signal down to baseband, this stage adds an additional 0 dB or 6 dB of gain. Complex to Real Conversion Stage (Optional) When real outputs are necessary, this stage converts the complex outputs back to real by performing an fS/4 mixing operation plus a filter to remove the complex component of the signal. Figure 73 shows the detailed block diagram of the DDCs implemented in the AD6684. Rev. A | Page 32 of 99 Data Sheet AD6684 REAL/I CONVERTER 0 Q CONVERTER 1 SYSREF GAIN = 0dB OR 6dB COMPLEX TO REAL CONVERSION (OPTIONAL) COMPLEX TO REAL CONVERSION (OPTIONAL) REAL/Q Q GAIN = 0dB OR 6dB NCO + MIXER (OPTIONAL) ADC SAMPLING AT fS HB1 FIR DCM = 2 I HB2 FIR DCM = BYPASS OR 2 REAL/I HB3 FIR DCM = BYPASS OR 2 DDC 1 REAL/I CONVERTER 2 JESD204B TRANSMIT INTERFACE COMPLEX TO REAL CONVERSION (OPTIONAL) GAIN = 0dB OR 6dB HB1 FIR DCM = 2 HB2 FIR DCM = BYPASS OR 2 HB3 FIR DCM = BYPASS OR 2 REAL/Q Q HB4 FIR DCM = BYPASS OR 2 REAL/Q NCO + MIXER (OPTIONAL) ADC SAMPLING AT fS I/Q CROSSBAR MUX REAL/I I HB4 FIR DCM = BYPASS OR 2 DDC 0 REAL/I L JESD204B LANES AT UP TO 15Gbps Q CONVERTER 3 SYSREF HB1 FIR DCM = 2 REAL/I CONVERTER 2 L JESD204B LANES AT UP TO 15Gbps Q CONVERTER 3 14994-055 COMPLEX TO REAL CONVERSION (OPTIONAL) GAIN = 0dB OR 6dB HB1 FIR DCM = 2 NCO + MIXER (OPTIONAL) HB2 FIR DCM = BYPASS OR 2 I HB3 FIR DCM = BYPASS OR 2 REAL/I JESD204B TRANSMIT INTERFACE Q CONVERTER 1 DDC 1 ADC SAMPLING AT fS SYNCHRONIZATION CONTROL CIRCUITS REAL/I CONVERTER 0 SYSREF REAL/Q Q SYSREF HB2 FIR DCM = BYPASS OR 2 REAL/Q Q HB3 FIR DCM = BYPASS OR 2 NCO + MIXER (OPTIONAL) HB4 FIR DCM = BYPASS OR 2 REAL/Q ADC SAMPLING AT fS I/Q CROSSBAR MUX REAL/I I HB4 FIR DCM = BYPASS OR 2 DDC 0 REAL/I SYSREF Figure 73. DDC Detailed Block Diagram Figure 74 shows an example usage of one of the four DDC blocks with a real input signal and four half-band filters (HB4 + HB3 + HB2 + HB1). It shows both complex (decimate by 16) and real (decimate by 8) output options. When DDCs have different decimation ratios, the chip decimation ratio (Register 0x0201) must be set to the lowest decimation ratio of all the DDC blocks on a per pair basis in conjunction with the pair index (Register 0x0009). In this scenario, samples of higher decimation ratio DDCs are repeated to match the chip decimation ratio sample rate. Whenever the NCO frequency is set or changed, the DDC soft reset must be issued. If the DDC soft reset is not issued, the output may potentially show amplitude variations. Table 10, Table 11, Table 12, Table 13, and Table 14 show the DDC samples when the chip decimation ratio is set to 1, 2, 4, 8, or 16, respectively. When DDCs have different decimation ratios, the chip decimation ratio must be set to the lowest decimation ratio of all the DDC channels in the respective channel pair (Channel A/Channel B or Channel C/Channel D). In this scenario, samples of higher decimation ratio DDCs are repeated to match the chip decimation ratio sample rate. Rev. A | Page 33 of 99 AD6684 Data Sheet ADC ADC SAMPLING AT fS REAL REAL INPUT--SAMPLED AT fS BANDWIDTH OF INTEREST IMAGE -fS/2 -fS/3 -fS/4 REAL BANDWIDTH OF INTEREST fS/32 -fS/32 -fS/16 fS/16 DC -fS/8 FREQUENCY TRANSLATION STAGE (OPTIONAL) DIGITAL MIXER + NCO FOR fS/3 TUNING, THE FREQUENCY TUNING WORD = ROUND ((fS/3)/fS x 248) = +9.382513 (0x555555555555) fS/8 fS/4 fS/3 fS/2 I NCO TUNES CENTER OF BANDWIDTH OF INTEREST TO BASEBAND cos(t) REAL 48-BIT NCO 90 0 -sin(t) Q DIGITAL FILTER RESPONSE -fS/2 -fS/3 -fS/4 fS/32 -fS/32 DC -fS/16 fS/16 -fS/8 BANDWIDTH OF INTEREST IMAGE (-6dB LOSS DUE TO NCO + MIXER) BANDWIDTH OF INTEREST (-6dB LOSS DUE TO NCO + MIXER) fS/8 fS/4 fS/3 fS/2 FILTERING STAGE HB4 FIR 4 DIGITAL HALF-BAND FILTERS (HB4 + HB3 + HB2 + HB1) I HALFBAND FILTER Q HALFBAND FILTER HB2 FIR HB3 FIR 2 HALFBAND FILTER 2 HALFBAND FILTER HB4 FIR 2 HALFBAND FILTER 2 HALFBAND FILTER HB3 FIR HB1 FIR 2 HALFBAND FILTER 2 HALFBAND FILTER HB2 FIR 2 I HB1 FIR 2 Q 6dB GAIN TO COMPENSATE FOR NCO + MIXER LOSS COMPLEX (I/Q) OUTPUTS GAIN STAGE (OPTIONAL) DIGITAL FILTER RESPONSE I GAIN STAGE (OPTIONAL) Q 0dB OR 6dB GAIN COMPLEX TO REAL CONVERSION STAGE (OPTIONAL) fS/4 MIXING + COMPLEX FILTER TO REMOVE Q -fS/32 fS/32 DC -fS/16 fS/16 -fS/8 DECIMATE BY 16 0dB OR 6dB GAIN 2 +6dB 2 +6dB I Q fS/32 -fS/32 DC -fS/16 fS/16 fS/8 DOWNSAMPLE BY 2 I REAL (I) OUTPUTS +6dB I DECIMATE BY 8 Q +6dB Q COMPLEX REAL/I TO REAL -fS/8 fS/32 -fS/32 DC -fS/16 fS/16 fS/8 Figure 74. DDC Theory of Operation Example (Real Input, Decimate by 16) Rev. A | Page 34 of 99 14994-056 6dB GAIN TO COMPENSATE FOR NCO + MIXER LOSS Data Sheet AD6684 Table 10. DDC Samples in Each JESD204B Link When Chip Decimation Ratio = 1 HB1 FIR (DCM 1 = 1) N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 N+9 N + 10 N + 11 N + 12 N + 13 N + 14 N + 15 N + 16 N + 17 N + 18 N + 19 N + 20 N + 21 N + 22 N + 23 N + 24 N + 25 N + 26 N + 27 N + 28 N + 29 N + 30 N + 31 1 Real (I) Output (Complex to Real Enabled) HB3 FIR + HB2 HB4 FIR + HB3 FIR + HB2 FIR + FIR + HB1 FIR HB2 FIR + HB1 FIR HB1 FIR (DCM1 = 4) (DCM1 = 8) (DCM1 = 2) N N N N N N N+1 N N N+1 N N N+2 N+1 N N+2 N+1 N N+3 N+1 N N+3 N+1 N N+4 N+2 N+1 N+4 N+2 N+1 N+5 N+2 N+1 N+5 N+2 N+1 N+6 N+3 N+1 N+6 N+3 N+1 N+7 N+3 N+1 N+7 N+3 N+1 N+8 N+4 N+2 N+8 N+4 N+2 N+9 N+4 N+2 N+9 N+4 N+2 N + 10 N+5 N+2 N + 10 N+5 N+2 N + 11 N+5 N+2 N + 11 N+5 N+2 N + 12 N+6 N+3 N + 12 N+6 N+3 N + 13 N+6 N+3 N + 13 N+6 N+3 N + 14 N+7 N+3 N + 14 N+7 N+3 N + 15 N+7 N+3 N + 15 N+7 N+3 Complex (I/Q) Outputs (Complex to Real Disabled) HB2 FIR + HB3 FIR + HB2 HB4 FIR + HB3 FIR + HB1 FIR HB1 FIR FIR + HB1 FIR HB2 FIR + HB1 FIR (DCM1 = 2) (DCM1 = 4) (DCM1 = 8) (DCM1 = 16) N N N N N N N N N+1 N N N N+1 N N N N+2 N+1 N N N+2 N+1 N N N+3 N+1 N N N+3 N+1 N N N+4 N+2 N+1 N N+4 N+2 N+1 N N+5 N+2 N+1 N N+5 N+2 N+1 N N+6 N+3 N+1 N N+6 N+3 N+1 N N+7 N+3 N+1 N N+7 N+3 N+1 N N+8 N+4 N+2 N+1 N+8 N+4 N+2 N+1 N+9 N+4 N+2 N+1 N+9 N+4 N+2 N+1 N + 10 N+5 N+2 N+1 N + 10 N+5 N+2 N+1 N + 11 N+5 N+2 N+1 N + 11 N+5 N+2 N+1 N + 12 N+6 N+3 N+1 N + 12 N+6 N+3 N+1 N + 13 N+6 N+3 N+1 N + 13 N+6 N+3 N+1 N + 14 N+7 N+3 N+1 N + 14 N+7 N+3 N+1 N + 15 N+7 N+3 N+1 N + 15 N+7 N+3 N+1 DCM means decimation. Table 11. DDC Samples in Each JESD204B Link When Chip Decimation Ratio = 2 Real (I) Output (Complex to Real Enabled) HB4 FIR + HB3 FIR + HB3 FIR + HB2 FIR + HB2 FIR + HB2 FIR + HB1 FIR HB1 FIR HB1 FIR (DCM 1 = 2) (DCM1 = 4) (DCM1 = 8) N N N N+1 N N N+2 N+1 N N+3 N+1 N N+4 N+2 N+1 N+5 N+2 N+1 N+6 N+3 N+1 N+7 N+3 N+1 N+8 N+4 N+2 N+9 N+4 N+2 Complex (I/Q) Outputs (Complex to Real Disabled) HB4 FIR + HB3 FIR + HB3 FIR + HB2 FIR + HB2 FIR + HB2 FIR + HB1 FIR HB1 FIR HB1 FIR HB1 FIR (DCM1 = 2) (DCM1 = 4) (DCM1 = 8) (DCM1 = 16) N N N N N+1 N N N N+2 N+1 N N N+3 N+1 N N N+4 N+2 N+1 N N+5 N+2 N+1 N N+6 N+3 N+1 N N+7 N+3 N+1 N N+8 N+4 N+2 N+1 N+9 N+4 N+2 N+1 Rev. A | Page 35 of 99 AD6684 Real (I) Output (Complex to Real Enabled) HB4 FIR + HB3 FIR + HB3 FIR + HB2 FIR + HB2 FIR + HB2 FIR + HB1 FIR HB1 FIR HB1 FIR (DCM 1 = 2) (DCM1 = 4) (DCM1 = 8) N + 10 N+5 N+2 N + 11 N+5 N+2 N + 12 N+6 N+3 N + 13 N+6 N+3 N + 14 N+7 N+3 N + 15 N+7 N+3 1 Data Sheet Complex (I/Q) Outputs (Complex to Real Disabled) HB4 FIR + HB3 FIR + HB3 FIR + HB2 FIR + HB2 FIR + HB2 FIR + HB1 FIR HB1 FIR HB1 FIR HB1 FIR (DCM1 = 2) (DCM1 = 4) (DCM1 = 8) (DCM1 = 16) N + 10 N+5 N+2 N+1 N + 11 N+5 N+2 N+1 N + 12 N+6 N+3 N+1 N + 13 N+6 N+3 N+1 N + 14 N+7 N+3 N+1 N + 15 N+7 N+3 N+1 DCM means decimation. Table 12. DDC Samples in Each JESD204B Link When Chip Decimation Ratio = 4 Real (I) Output (Complex to Real Enabled) HB4 FIR + HB3 FIR + HB3 FIR + HB2 FIR + HB2 FIR + HB1 FIR (DCM1 = 8) HB1 FIR (DCM 1 = 4) N N N+1 N N+2 N+1 N+3 N+1 N+4 N+2 N+5 N+2 N+6 N+3 N+7 N+3 1 Complex (I/Q) Outputs (Complex to Real Disabled) HB4 FIR + HB3 FIR + HB2 FIR + HB1 FIR HB3 FIR + HB2 FIR + HB2 FIR + HB1 FIR (DCM1 = 4) HB1 FIR (DCM1 = 8) (DCM1 = 16) N N N N+1 N N N+2 N+1 N N+3 N+1 N N+4 N+2 N+1 N+5 N+2 N+1 N+6 N+3 N+1 N+7 N+3 N+1 DCM means decimation. Table 13. DDC Samples in Each JESD204B Link When Chip Decimation Ratio = 8 Real (I) Output (Complex to Real Enabled) HB4 FIR + HB3 FIR + HB2 FIR + HB1 FIR (DCM 1 = 8) N N+1 N+2 N+3 N+4 N+5 N+6 N+7 1 Complex (I/Q) Outputs (Complex to Real Disabled) HB3 FIR + HB2 FIR + HB1 FIR HB4 FIR + HB3 FIR + HB2 FIR + (DCM1 = 8) HB1 FIR (DCM1 = 16) N N N+1 N N+2 N+1 N+3 N+1 N+4 N+2 N+5 N+2 N+6 N+3 N+7 N+3 DCM means decimation. Table 14. DDC Samples in Each JESD204B Link When Chip Decimation Ratio = 16 Real (I) Output (Complex to Real Enabled) HB4 FIR + HB3 FIR + HB2 FIR + HB1 FIR (DCM 1 = 16) Not applicable Not applicable Not applicable Not applicable 1 Complex (I/Q) Outputs (Complex to Real Disabled) HB4 FIR + HB3 FIR + HB2 FIR + HB1 FIR (DCM1 = 16) N N+1 N+2 N+3 DCM means decimation. Rev. A | Page 36 of 99 Data Sheet AD6684 For example, if the chip decimation ratio is set to decimate by 4, DDC 0 is set to use HB2 + HB1 filters (complex outputs, decimate by 4) and DDC 1 is set to use HB4 + HB3 + HB2 + HB1 filters (real outputs, decimate by 8). DDC 1 repeats its output data two times for every one DDC 0 output. The resulting output samples are shown in Table 15. Table 15. DDC Output Samples in Each JESD204B Link When Chip DCM 1 = 4, DDC 0 DCM1 = 4 (Complex), and DDC 1 DCM1 = 8 (Real) DDC Input Samples N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 N+9 N + 10 N + 11 N + 12 N + 13 N + 14 N + 15 1 Output Port I I0 (N) DDC 0 Output Port Q Q0 (N) I0 (N + 1) Q0 (N + 1) I0 (N + 2) Q0 (N + 2) I0 (N + 3) Q0 (N + 3) DCM means decimation. Rev. A | Page 37 of 99 Output Port I I1 (N) I1 (N + 1) DDC 1 Output Port Q Not applicable Not applicable AD6684 Data Sheet FREQUENCY TRANSLATION GENERAL DESCRIPTION Variable IF Mode Frequency translation is accomplished by using a 48-bit complex NCO with a digital quadrature mixer. This stage translates either a real or complex input signal from an IF to a baseband complex digital output (carrier frequency = 0 Hz). NCO and mixers are enabled. NCO output frequency can be used to digitally tune the IF frequency. 0 Hz IF (ZIF) Mode The mixers are bypassed, and the NCO is disabled. The frequency translation stage of each DDC can be controlled individually and supports four different IF modes using Bits[5:4] of the DDC control registers (Register 0x0310 and Register 0x0330) in conjunction with the pair index register (Register 0x0009). These IF modes are The mixers and the NCO are enabled in special downmixing by fS/4 mode to save power. Test Mode Input samples are forced to 0.9599 to positive full scale. The NCO is enabled. This test mode allows the NCOs to directly drive the decimation filters. Variable IF mode 0 Hz IF or zero IF (ZIF) mode fS/4 Hz IF mode Test mode Figure 75 and Figure 76 show examples of the frequency translation stage for both real and complex inputs. NCO FREQUENCY TUNING WORD (FTW) SELECTION 48-BIT NCO FTW = MIXING FREQUENCY/ADC SAMPLE RATE x 248 I ADC + DIGITAL MIXER + NCO REAL INPUT--SAMPLED AT fS REAL cos(t) ADC SAMPLING AT fS REAL 48-BIT NCO 90 0 COMPLEX -sin(t) Q BANDWIDTH OF INTEREST BANDWIDTH OF INTEREST IMAGE -fS/2 -fS/3 -fS/4 -fS/8 -fS/32 fS/32 DC fS/16 -fS/16 fS/8 fS/4 fS/3 fS/2 -6dB LOSS DUE TO NCO + MIXER 48-BIT NCO FTW = ROUND ((fS/3)/fS x 248) = +9.3825 13 (0x555555555555) POSITIVE FTW VALUES -fS/32 DC fS/32 48-BIT NCO FTW = ROUND ((-fS/3)/fS x 248) = -9.3825 13 (0xFFFF000000000000) NEGATIVE FTW VALUES -fS/32 DC fS/32 Figure 75. DDC NCO Frequency Tuning Word Selection--Real Inputs Rev. A | Page 38 of 99 14994-057 * * * * fS/4 Hz IF Mode Data Sheet AD6684 NCO FREQUENCY TUNING WORD (FTW) SELECTION 48-BIT NCO FTW = MIXING FREQUENCY/ADC SAMPLE RATE x 248 QUADRATURE ANALOG MIXER + 2 ADCs + QUADRATURE DIGITAL REAL MIXER + NCO COMPLEX INPUT--SAMPLED AT fS QUADRATURE MIXER ADC SAMPLING AT fS I + I I Q Q 90 PHASE 48-BIT NCO 90 0 Q Q ADC SAMPLING AT fS Q Q I I - -sin(t) I I + COMPLEX Q + BANDWIDTH OF INTEREST IMAGE DUE TO ANALOG I/Q MISMATCH -fS/3 -fS/4 -fS/32 fS/32 fS/16 -fS/16 DC -fS/8 fS/8 fS/4 fS/3 fS/2 48-BIT NCO FTW = ROUND ((fS/3)/fS x 248) = +9.3825 13 (0x555555555555) POSITIVE FTW VALUES -fS/32 fS/32 14994-058 -fS/2 DC Figure 76. DDC NCO Frequency Tuning Word Selection--Complex Inputs DDC NCO + MIXER LOSS AND SFDR Setting Up the NCO FTW and POW When mixing a real input signal down to baseband, 6 dB of loss is introduced in the signal due to filtering of the negative image. An additional 0.05 dB of loss is introduced by the NCO. The total loss of a real input signal mixed down to baseband is 6.05 dB. For this reason, it is recommended that the user compensate for this loss by enabling the 6 dB of gain in the gain stage of the DDC to recenter the dynamic range of the signal within the full scale of the output bits. The NCO frequency value is given by the 48-bit twos complement number entered in the NCO FTW. Frequencies between -fS/2 and +fS/2 (fS/2 excluded) are represented using the following frequency words: When mixing a complex input signal down to baseband, the maximum value that each I/Q sample can reach is 1.414 x full scale after it passes through the complex mixer. To avoid overrange of the I/Q samples and to keep the data bit widths aligned with real mixing, 3.06 dB of loss is introduced in the mixer for complex signals. An additional 0.05 dB of loss is introduced by the NCO. The total loss of a complex input signal mixed down to baseband is -3.11 dB. The worst case spurious signal from the NCO is greater than 102 dBc SFDR for all output frequencies. NUMERICALLY CONTROLLED OSCILLATOR The AD6684 has a 48-bit NCO for each DDC that enables the frequency translation process. The NCO allows the input spectrum to be tuned to dc, where it can be effectively filtered by the subsequent filter blocks to prevent aliasing. The NCO can be set up by providing a frequency tuning word (FTW) and a phase offset word (POW). * * * 0x8000 0000 0000 represents a frequency of -fS/2. 0x0000 0000 0000 represents dc (frequency is 0 Hz). 0x7FFF FFFF FFFF represents a frequency of +fS/2 - fS/248. The NCO frequency tuning word can be calculated using the following equation: mod ( fC , f S ) NCO_FTW = round 248 fS where: NCO_FTW is a 48-bit twos complement number representing the NCO FTW. fC is the desired carrier frequency in Hz. fS is the AD6684 sampling frequency (clock rate) in Hz. mod( ) is a remainder function. For example, mod(110,100) = 10 and for negative numbers, mod(-32, 10) = -2. round( ) is a rounding function. For example, round(3.6) = 4 and for negative numbers, round(-3.4) = -3. Note that this equation applies to the aliasing of signals in the digital domain (that is, aliasing introduced when digitizing analog signals). Rev. A | Page 39 of 99 AD6684 Data Sheet For example, if the ADC sampling frequency (fS) is 500 MSPS and the carrier frequency (fC) is 140.312 MHz, then mod (140.312,500 ) NCO_FTW = round 248 = 500 13 7.89886 x 10 Hz of the NCO. See the Setting Up the NCO FTW and POW section for more information. Use the following two methods to synchronize multiple PAWs within the chip. * This, in turn, converts to 0x47D in the 48-bit twos complement representation for NCO_FTW. The actual carrier frequency, fC_ACTUAL, is calculated based on the following equation: fC_ACTUAL = NCO _ FTW x f S 2 48 = 140.312 MHz A 48-bit POW is available for each NCO to create a known phase relationship between multiple AD6684 chips or individual DDC channels inside one AD6684 chip. The POW registers can be updated in the NCO at any time without disrupting the phase accumulators, allowing phase adjustments to occur during normal operation. However, the following procedure must be followed to update the FTW registers to ensure proper operation of the NCO: 1. 2. Write to the FTW registers for all the DDCs. Synchronize the NCOs either through the DDC NCO soft reset bit (Register 0x0300, Bit 4), which is accessible through the SPI, or through the assertion of the SYSREF pin. It is important to note that the NCOs must be synchronized either through the SPI or through the SYSREF pin after all writes to the FTW or POW registers are complete. This step is necessary to ensure the proper operation of the NCO. NCO Synchronization Each NCO contains a separate phase accumulator word (PAW). The initial reset value of each PAW is set to zero, and the phase increment value of each PAW is determined by the FTW. The POW is added to the PAW to produce the instantaneous phase * Using the SPI. Use the DDC NCO soft reset bit in the DDC synchronization control register (Register 0x0300, Bit 4) to reset all the PAWs in the chip. This is accomplished by setting the DDC NCO soft reset bit high and then setting this bit low. Note that this method can only be used to synchronize DDC channels within the same pair (A/B or C/D) of a AD6684 chip. Using the SYSREF pin. When the SYSREF pin is enabled in the SYSREF control registers (Register 0x0120 and Register 0x0121) and the DDC synchronization is enabled in the DDC synchronization control register (Register 0x0300, Bits[1:0]), any subsequent SYSREF event resets all the PAWs in the chip. Note that this method can be used to synchronize DDC channels within the same AD6684 chip or DDC channels within separate AD6684 chips. Mixer The NCO is accompanied by a mixer. Its operation is similar to an analog quadrature mixer. It performs the downconversion of input signals (real or complex) by using the NCO frequency as a local oscillator. For real input signals, this mixer performs a real mixer operation (with two multipliers). For complex input signals, the mixer performs a complex mixer operation (with four multipliers and two adders). The mixer adjusts its operation based on the input signal (real or complex) provided to each individual channel. The selection of real or complex inputs can be controlled individually for each DDC block using Bit 7 of the DDC control registers (Register 0x0310 and Register 0x0330) in conjunction with the pair index register (Register 0x0009). Rev. A | Page 40 of 99 Data Sheet AD6684 FIR FILTERS GENERAL DESCRIPTION There are four sets of decimate by 2, low-pass, half-band, FIR filters (labeled HB1 FIR, HB2 FIR, HB3 FIR, and HB4 FIR in Figure 73) following the frequency translation stage. After the carrier of interest is tuned down to dc (carrier frequency = 0 Hz), these filters efficiently lower the sample rate, while providing sufficient alias rejection from unwanted adjacent carriers around the bandwidth of interest. HB1 FIR is always enabled and cannot be bypassed. The HB2, HB3, and HB4 FIR filters are optional and can be bypassed for higher output sample rates. Table 16 shows the different bandwidths selectable by including different half-band filters. In all cases, the DDC filtering stage on the AD6684 provides <-0.001 dB of pass-band ripple and >100 dB of stop-band alias rejection. Table 17 shows the amount of stop-band alias rejection for multiple pass-band ripple/cutoff points. The decimation ratio of the filtering stage of each DDC can be controlled individually through Bits[1:0] of the DDC control registers (Register 0x0310 and Register 0x0330) in conjunction with the pair index register (Register 0x0009). Table 16. DDC Filter Characteristics Half Band Filter Selection HB1 Real Output Output Sample Decimation Rate Ratio (MSPS) 1 500 HB1 + HB2 2 250 HB1 + HB2 + HB3 HB1 + HB2 + HB3 + HB4 4 125 8 62.5 1 Complex (I/Q) Output Output Sample Decimation Rate Ratio (MSPS) 2 250 (I) + 250 (Q) 4 125 (I) + 125 (Q) 8 62.5 (I) + 62.5 (Q) 16 31.25 (I) + 31.25 (Q) Alias Protected Bandwidth (MHz) 200 Ideal SNR Improvement 1 (dB) 1 100 4 50 7 25 10 Pass-Band Ripple (dB) <-0.0001 Alias Rejection (dB) >100 Ideal SNR improvement due to oversampling and filtering = 10log(bandwidth/(fS/2)). Table 17. DDC Filter Alias Rejection Alias Rejection (dB) >100 95 90 85 80 25.07 19.3 10.7 1 Pass-Band Ripple/Cutoff Point (dB) <-0.0001 <-0.0002 <-0.0003 <-0.0005 <-0.0009 -0.5 -1.0 -3.0 Alias Protected Bandwidth for Real (I) Outputs 1 <40% x fOUT <40.12% x fOUT <40.23% x fOUT <40.36% x fOUT <40.53% x fOUT 45.17% x fOUT 46.2% x fOUT 48.29% x fOUT fOUT = ADC input sample rate / DDC decimation. Rev. A | Page 41 of 99 Alias Protected Bandwidth for Complex (I/Q) Outputs <80% x fOUT <80.12% x fOUT <80.46% x fOUT <80.72% x fOUT <81.06% x fOUT 90.34% x fOUT 92.4% x fOUT 96.58% x fOUT AD6684 Data Sheet HALF-BAND FILTERS Table 19. HB3 Filter Coefficients The AD6684 offers four half-band filters to enable digital signal processing of the ADC converted data. These half-band filters are bypassable and can be individually selected. HB3 Coefficient Number C1, C11 C2, C10 C3, C9 C4, C8 C5, C7 C6 Table 18. HB4 Filter Coefficients HB4 Coefficient Number C1, C11 C2, C10 C3, C9 C4, C8 C5, C7 C6 Decimal Coefficient 0.006042 0 -0.049377 0 0.293334 0.500000 Quantized Coefficient (15-Bit) 99 0 -809 0 4806 8192 Quantized Coefficient (17-Bit) 435 0 -3,346 0 19,295 32,768 0 -20 -40 -60 -80 -100 -120 -140 -160 -180 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 NORMALIZED FREQUENCY (x RAD/SAMPLE) 1.0 14994-060 The first decimate by 2, half-band, low-pass, FIR filter (HB4) uses an 11-tap, symmetrical, fixed coefficient filter implementation that is optimized for low power consumption. The HB4 filter is only used when complex outputs (decimate by 16) or real outputs (decimate by 8) are enabled; otherwise, it is bypassed. Table 18 and Figure 77 show the coefficients and response of the HB4 filter. MAGNITUDE (dB) HB4 Filter Decimal Coefficient 0.006638 0 -0.051055 0 0.294418 0.500000 Figure 78. HB3 Filter Response 0 HB2 Filter -100 The third decimate by 2, half-band, low-pass, FIR filter (HB2) uses a 19-tap, symmetrical, fixed coefficient filter implementation that is optimized for low power consumption. -150 The HB2 filter is only used when complex or real outputs (decimate by 4, 8, or 16) is enabled; otherwise, it is bypassed. -200 Table 20 and Figure 79 show the coefficients and response of the HB2 filter. MAGNITUDE (dB) -50 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 NORMALIZED FREQUENCY (x RAD/SAMPLE) 1.0 14994-059 Table 20. HB2 Filter Coefficients -250 Figure 77. HB4 Filter Response HB3 Filter The second decimate by 2, half-band, low-pass, FIR filter (HB3) uses an 11-tap, symmetrical, fixed coefficient filter implementation that is optimized for low power consumption. The HB3 filter is only used when complex outputs (decimate by 8 or 16) or real outputs (decimate by 4 or 8) are enabled; otherwise, it is bypassed. Table 19 and Figure 78 show the coefficients and response of the HB3 filter. HB2 Coefficient Number C1, C19 C2, C18 C3, C17 C4, C16 C5, C15 C6, C14 C7, C13 C8, C12 C9, C11 C10 Rev. A | Page 42 of 99 Decimal Coefficient 0.000671 0 -0.005325 0 0.022743 0 -0.074181 0 0.306091 0.500000 Quantized Coefficient (18-Bit) 88 0 -698 0 2,981 0 -9,723 0 40,120 65,536 Data Sheet AD6684 Table 21. HB1 Filter Coefficients 0 -20 MAGNITUDE (dB) -40 -60 -80 -100 -120 -140 -180 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 NORMALIZED FREQUENCY (x RAD/SAMPLE) 1.0 14994-061 -160 Figure 79. HB2 Filter Response HB1 Filter The fourth and final decimate by 2, half-band, low-pass, FIR filter (HB1) uses a 63-tap, symmetrical, fixed coefficient filter implementation that is optimized for low power consumption. The HB1 filter is always enabled and cannot be bypassed. Table 21 and Figure 80 show the coefficients and response of the HB1 filter. 0 -20 -60 -80 -100 -120 -140 -160 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 NORMALIZED FREQUENCY (x RAD/SAMPLE) 1.0 14994-062 MAGNITUDE (dB) -40 HB1 Coefficient Number C1, C63 C2, C62 C3, C61 C4, C60 C5, C59 C6, C58 C7, C57 C8, C56 C9, C55 C10, C54 C11, C53 C12, C52 C13, C51 C14, C50 C15, C49 C16, C48 C17, C47 C18, C46 C19, C45 C20, C44 C21, C43 C22, C42 C23, C41 C24, C40 C25, C39 C26, C38 C27, C37 C28, C36 C29, C35 C30, C34 C31, C33 C32 Figure 80. HB1 Filter Response Rev. A | Page 43 of 99 Decimal Coefficient -0.000019 0 0.000072 0 -0.000194 0 0.000442 0 -0.000891 0 0.001644 0 -0.002840 0 0.004653 0 -0.007311 0 0.011121 0 -0.016553 0 0.024420 0 -0.036404 0 0.056866 0 -0.101892 0 0.316883 0.500000 Quantized Coefficient (20-Bit) -10 0 38 0 -102 0 232 0 -467 0 862 0 -1,489 0 2,440 0 -3,833 0 5,831 0 -8,679 0 12,803 0 -19,086 0 29,814 0 -53,421 0 166,138 262,144 AD6684 Data Sheet DDC GAIN STAGE DDC COMPLEX TO REAL CONVERSION Each DDC contains an independently controlled gain stage. The gain is selectable as either 0 dB or 6 dB. When mixing a real input signal down to baseband, it is recommended that the user enable the 6 dB of gain to recenter the dynamic range of the signal within the full scale of the output bits. Each DDC contains an independently controlled complex to real conversion block. The complex to real conversion block reuses the last filter (HB1 FIR) in the filtering stage along with an fS/4 complex mixer to upconvert the signal. After upconverting the signal, the Q portion of the complex mixer is no longer needed and is dropped. When mixing a complex input signal down to baseband, the mixer has already recentered the dynamic range of the signal within the full scale of the output bits, and no additional gain is necessary. However, the optional 6 dB gain compensates for low signal strengths. The downsample by 2 portion of the HB1 FIR filter is bypassed when using the complex to real conversion stage. HB1 FIR Figure 81 shows a simplified block diagram of the complex to real conversion. GAIN STAGE COMPLEX TO REAL ENABLE LOW-PASS FILTER I 2 0dB OR 6dB I 0 I/REAL 1 COMPLEX TO REAL CONVERSION 0dB OR 6dB I cos(t) + REAL 90 fS/4 0 - sin(t) LOW-PASS FILTER 2 Q 0dB OR 6dB Q Q 14994-063 Q 0dB OR 6dB HB1 FIR Figure 81. Complex to Real Conversion Block Rev. A | Page 44 of 99 Data Sheet AD6684 DDC EXAMPLE CONFIGURATIONS Table 22 describes the register settings for multiple DDC example configurations. Table 22. DDC Example Configurations (Per ADC Channel Pair) DDC Input Type Complex DDC Output Type Complex Bandwidth Per DDC 1 40% x fS No. of Virtual Converters Required 2 4 Complex Complex 20% x fS 2 2 Real Real 20%x fS 2 Chip Application Layer One DDC Chip Decimation Ratio 2 One DDC Two DDCs Rev. A | Page 45 of 99 Register Settings 2 0x0009 = 0x01, 0x02, or 0x03 (pair selection) 0x0200 = 0x01 (one DDC; I/Q selected) 0x0201 = 0x01 (chip decimate by 2) 0x0310 = 0x83 (complex mixer; 0 dB gain; variable IF; complex outputs; HB1 filter) 0x0311 = 0x04 (DDC I input = ADC Channel A/ Channel C; DDC Q input = ADC Channel B/ Channel D) 0x0314, 0x0315, 0x0316, 0x0317, 0x0318, 0x031A, 0x031D, 0x031E, 0x031F, 0x0320, 0x0321, 0x0322 = FTW and POW set as required by application for DDC 0 0x0009 = 0x01, 0x02, or 0x03 (pair selection) 0x0200 = 0x01 (one DDC; I/Q selected) 0x0201 = 0x02 (chip decimate by 4) 0x0310= 0x80 (complex mixer; 0 dB gain; variable IF; complex outputs; HB2 + HB1 filters) 0x0311= 0x04 (DDC I input = ADC Channel A/ Channel C; DDC Q input = ADC Channel B/ Channel D) 0x0314, 0x0315, 0x0316, 0x0317, 0x0318, 0x031A, 0x031D, 0x031E, 0x031F, 0x0320, 0x0321, 0x0322 = FTW and POW set as required by application for DDC 0 0x0009 = 0x01, 0x02, or 0x03 (pair selection) 0x0200 = 0x22 (two DDCs; I only selected) 0x0201 = 0x01 (chip decimate by 2) 0x0310, 0x0330 = 0x48 (real mixer; 6 dB gain; variable IF; real output; HB2 + HB1 filters) 0x0311 = 0x00 (DDC 0 I input = ADC Channel A/ Channel C; DDC 0 Q input = ADC Channel A/ Channel C) 0x0331 = 0x05 (DDC 1 I input = ADC Channel B/ Channel D; DDC 1 Q input = ADC Channel B/ Channel D) 0x0314, 0x0315, 0x0316, 0x0317, 0x0318, 0x031A, 0x031D, 0x031E, 0x031F, 0x0320, 0x0321, 0x0322 = FTW and POW set as required by application for DDC 0 0x0334, 0x0335, 0x0336, 0x0337, 0x0338, 0x033A, 0x033D, 0x033E, 0x033F, 0x0340, 0x0341, 0x0342 = FTW and POW set as required by application for DDC 1 AD6684 Data Sheet DDC Input Type Complex DDC Output Type Complex Bandwidth Per DDC 1 40%x fS No. of Virtual Converters Required 4 4 Complex Complex 20% x fS 4 4 Complex Real 10% x fS 2 Chip Application Layer Two DDCs Chip Decimation Ratio 2 Two DDCs Two DDCs Rev. A | Page 46 of 99 Register Settings 2 0x0009 = 0x01, 0x02, or 0x03 (pair selection) 0x0200 = 0x22 (two DDCs; I only selected) 0x0201 = 0x01 (chip decimate by 2) 0x0310, 0x0330 = 0x4B (complex mixer; 6 dB gain; variable IF; complex output; HB1 filter) 0x0311, 0x0331 = 0x04 (DDC 0 I input = ADC Channel A/Channel C; DDC 0 Q input = ADC Channel B/Channel D) 0x0314, 0x0315, 0x0316, 0x0317, 0x0318, 0x031A, 0x031D, 0x031E, 0x031F, 0x0320, 0x0321, 0x0322 = FTW and POW set as required by application for DDC 0 0x0334, 0x0335, 0x0336, 0x0337, 0x0338, 0x033A, 0x033D, 0x033E, 0x033F, 0x0340, 0x0341, 0x0342= FTW and POW set as required by application for DDC 1 0x0009 = 0x01, 0x02, or 0x03 (pair selection) 0x0200 = 0x02 (two DDCs; I/Q selected) 0x0201 = 0x02 (chip decimate by 4) 0x0310, 0x0330 = 0x80 (complex mixer; 0 dB gain; variable IF; complex outputs; HB2 + HB1 filters) 0x0311, 0x0331 = 0x04 (DDC I input = ADC Channel A/Channel C; DDC Q input = ADC Channel B/Channel D) 0x0314, 0x0315, 0x0316, 0x0317, 0x0318, 0x031A, 0x031D, 0x031E, 0x031F, 0x0320, 0x0321, 0x0322 = FTW and POW set as required by application for DDC 0 0x0334, 0x0335, 0x0336, 0x0337, 0x0338, 0x033A, 0x033D, 0x033E, 0x033F, 0x0340, 0x0341, 0x0342= FTW and POW set as required by application for DDC 1 0x0009 = 0x01, 0x02, or 0x03 (pair selection) 0x0200 = 0x22 (two DDCs; I only selected) 0x0201 = 0x02 (chip decimate by 4) 0x0310, 0x0330 = 0x89 (complex mixer; 0 dB gain; variable IF; real output; HB3 + HB2 + HB1 filters) 0x0311, 0x0331 = 0x04 (DDC I input = ADC Channel A/Channel C; DDC Q input = ADC Channel B/Channel D) 0x0314, 0x0315, 0x0316, 0x0317, 0x0318, 0x031A, 0x031D, 0x031E, 0x031F, 0x0320, 0x0321, 0x0322 = FTW and POW set as required by application for DDC 0 0x0334, 0x0335, 0x0336, 0x0337, 0x0338, 0x033A, 0x033D, 0x033E, 0x033F, 0x0340, 0x0341, 0x0342= FTW and POW set as required by application for DDC 1 Data Sheet Chip Application Layer Two DDCs Chip Decimation Ratio 4 Two DDCs 4 AD6684 DDC Input Type Real DDC Output Type Real Bandwidth Per DDC 1 10% x fS No. of Virtual Converters Required 2 Real Complex 20% x fS 4 Rev. A | Page 47 of 99 Register Settings 2 0x0009 = 0x01, 0x02, or 0x03 (pair selection) 0x0200 = 0x22 (two DDCs; I only selected) 0x0201 = 0x02 (chip decimate by 4) 0x0310, 0x0330 = 0x49 (real mixer; 6 dB gain; variable IF; real output; HB3 + HB2 + HB1 filters) 0x0311 = 0x00 (DDC 0 I input = ADC Channel A/ Channel C; DDC 0 Q input = ADC Channel A/ Channel C) 0x0331 = 0x05 (DDC 1 I input = ADC Channel B/ Channel D; DDC 1 Q input = ADC Channel B/ Channel D) 0x0314, 0x0315, 0x0316, 0x0317, 0x0318, 0x031A, 0x031D, 0x031E, 0x031F, 0x0320, 0x0321, 0x0322 = FTW and POW set as required by application for DDC 0 0x0334, 0x0335, 0x0336, 0x0337, 0x0338, 0x033A, 0x033D, 0x033E, 0x033F, 0x0340, 0x0341, 0x0342= FTW and POW set as required by application for DDC 1 0x0009 = 0x01, 0x02, or 0x03 (pair selection) 0x0200 = 0x02 (two DDCs; I/Q selected) 0x0201 = 0x02 (chip decimate by 4) 0x0310, 0x0330 = 0x40 (real mixer; 6 dB gain; variable IF; complex output; HB2 + HB1 filters) 0x0311 = 0x00 (DDC 0 I input = ADC Channel A/ Channel C; DDC 0 Q input = ADC Channel A/ Channel C) 0x0331 = 0x05 (DDC 1 I input = ADC Channel B/ Channel D; DDC 1 Q input = ADC Channel B/ Channel D) 0x0314, 0x0315, 0x0316, 0x0317, 0x0318, 0x031A, 0x031D, 0x031E, 0x031F, 0x0320, 0x0321, 0x0322 = FTW and POW set as required by application for DDC 0 0x0334, 0x0335, 0x0336, 0x0337, 0x0338, 0x033A, 0x033D, 0x033E, 0x033F, 0x0340, 0x0341, 0x0342= FTW and POW set as required by application for DDC 1 AD6684 Chip Application Layer Two DDCs 1 2 Data Sheet Chip Decimation Ratio 8 DDC Input Type Real DDC Output Type Real Bandwidth Per DDC 1 5% x fS No. of Virtual Converters Required 2 Register Settings 2 0x0009 = 0x01, 0x02, or 0x03 (pair selection) 0x0200 = 0x22 (two DDCs; I only selected) 0x0201 = 0x03 (chip decimate by 8) 0x0310, 0x0330 = 0x4A (real mixer; 6 dB gain; variable IF; real output; HB4 + HB3 + HB2 + HB1 filters) 0x0311 = 0x00 (DDC 0 I input = ADC Channel A/ Channel C; DDC 0 Q input = ADC Channel A/ Channel C) 0x0331 = 0x05 (DDC 1 I input = ADC Channel B/ Channel D; DDC 1 Q input = ADC Channel B/ Channel D) 0x0314, 0x0315, 0x0316, 0x0317, 0x0318, 0x031A, 0x031D, 0x031E, 0x031F, 0x0320, 0x0321, 0x0322 = FTW and POW set as required by application for DDC 0 0x0334, 0x0335, 0x0336, 0x0337, 0x0338, 0x033A, 0x033D, 0x033E, 0x033F, 0x0340, 0x0341, 0x0342= FTW and POW set as required by application for DDC 1 fS is the ADC sample rate. Bandwidths listed are <-0.001 dB of pass-band ripple and >100 dB of stop-band alias rejection. The NCOs must be synchronized either through the SPI or through the SYSREF pin after all writes to the FTW or POW registers have completed. This is necessary to ensure the proper operation of the NCO. See the NCO Synchronization section for more information. Rev. A | Page 48 of 99 Data Sheet AD6684 NOISE SHAPING REQUANTIZER (NSR) Half-Band Filter Features The half-band decimating filter provides approximately 39.5% of the output sample rate in usable bandwidth (19.75% of the input sample clock). The filter provides >40 dB of rejection. The normalized response of the half-band filter in low-pass mode is shown in Figure 82. In low-pass mode, operation is allowed in the first Nyquist zone, which includes frequencies of up to fS/2, where fS is the decimated sample rate. For example, with an input clock of 500 MHz, the output sample rate is 250 MSPS and fS/2 = 125 MHz. 10 0 -10 The AD6684 optional decimating half-band filter reduces the input sample rate by a factor of 2 while rejecting aliases that fall into the band of interest. For an input sample clock of 500 MHz, this filter reduces the output sample rate to 250 MSPS. This filter is designed to provide >40 dB of alias protection for 39.5% of the output sample rate (79% of the Nyquist band). For an ADC sample rate of 500 MSPS, the filter provides a maximum usable bandwidth of 98.75 MHz. -20 MAGNITUDE (dB) DECIMATING HALF-BAND FILTER -30 -40 -50 -60 -70 -80 0 Half-Band Filter Coefficients Table 23. Fixed Coefficients for Half-Band Filter Decimal Coefficient 0.012207 -0.022949 0.045410 -0.094726 0.314453 0.500000 Quantized Coefficient (12-Bit) 25 -47 93 -194 644 1024 The half-band filter can also be used in high-pass mode. The usable bandwidth remains at 39.5% of the output sample rate (19.75% of the input sample clock), which is the same as in lowpass mode). Figure 83 shows the normalized response of the half-band filter in high-pass mode. In high-pass mode, operation is allowed in the second and third Nyquist zones, which includes frequencies from fS/2 to 3fS/2, where fS is the decimated sample rate. For example, with an input clock of 500 MHz, the output sample rate is 250 MSPS, fS/2 = 125 MHz, and 3fS/2 = 375 MHz. 10 0 -10 -20 -30 -40 -50 -60 -70 -80 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 NORMALIZED FREQUENCY (x RAD/SAMPLE) Figure 83. High-Pass, Half-Band Filter Response Rev. A | Page 49 of 99 1.0 14994-065 Coefficient Number 0 C2, C16 C4, C14 C6, C12 C8, C10 C9 0.50 Figure 82. Low-Pass, Half-Band Filter Response MAGNITUDE (dB) The 19-tap, symmetrical, fixed coefficient half-band filter has low power consumption due to its polyphase implementation. Table 23 lists the coefficients of the half-band filter in low-pass mode. In high-pass mode, Coefficient C9 is multiplied by -1. The decimal coefficients used in the implementation and the decimal equivalent values of the coefficients are listed. Coefficients not listed in Table 23 are 0s. 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 NORMALIZED FREQUENCY (x RAD/SAMPLE) 14994-064 When operating the AD6684 with the NSR enabled, a decimating half-band filter that is optimized at certain input frequency bands can also be enabled. This filter offers the user the flexibility in signal bandwidth processing and image rejection. Careful frequency planning can offer advantages in analog filtering preceding the ADC. The filter can function either in high-pass or low-pass mode. The filter can be optionally enabled on the AD6684 when the NSR is enabled. When operating with the NSR enabled, the decimating half-band filter mode (low pass or high pass) is selected by setting Bit 7 in Register 0x041E. When the decimating half-band filter is enabled, the chip decimation ratio register (Register 0x0201) must be set to a decimation rate of 2 (register value = 0x01). AD6684 Data Sheet NSR OVERVIEW The AD6684 features an NSR to allow higher than 9-bit SNR to be maintained in a subset of the Nyquist band. The harmonic performance of the receiver is unaffected by the NSR feature. When enabled, the NSR contributes an additional 3.0 dB of loss to the input signal, such that a 0 dBFS input is reduced to -3.0 dBFS at the output pins. This loss does not degrade the SNR performance of the AD6684. The NSR feature can be independently controlled per channel via the SPI. Two different bandwidth modes are provided; select the mode from the SPI port. In each of the two modes, the center frequency of the band can be tuned such that IFs can be placed anywhere in the Nyquist band. The NSR feature is enabled by default on the AD6684. The bandwidth and mode of the NSR operation are selected by setting the appropriate bits in Register 0x0420 and Register 0x0422. By selecting the appropriate profile and mode bits in these two registers, the NSR feature can be enabled for the desired mode of operation. 21% BW Mode (>100 MHz at 491.52 MSPS) mode, the useful frequency range can be set using the 6-bit tuning word in the NSR tuning register (Address 0x0422). There are 59 possible tuning words (TW), from 0 to 58; each step is 0.5% of the ADC sample rate. The following three equations describe the left band edge (f0), the channel center (fCENTER), and the right band edge (f1), respectively: f0 = fADC x 0.005 x TW fCENTER = f0 + 0.105 x fADC f1 = f0 + 0.21 x fADC 28% BW Mode (>130 MHz at 491.52 MSPS) The second NSR mode offers excellent noise performance across a bandwidth that is 28% of the ADC output sample rate (56% of the Nyquist band) and can be centered by setting the NSR mode bits in the NSR mode register (Address 0x0420) to 001. In this mode, the useful frequency range can be set using the 6-bit tuning word in the NSR tuning register (Address 0x0422). There are 44 possible tuning words (TW, from 0 to 43); each step is 0.5% of the ADC sample rate. The following three equations describe the left band edge (f0), the channel center (fCENTER), and the right band edge (f1), respectively: The first NSR mode offers excellent noise performance across a bandwidth that is 21% of the ADC output sample rate (42% of the Nyquist band) and can be centered by setting the NSR mode bits in the NSR mode register (Address 0x0420) to 000. In this Rev. A | Page 50 of 99 f0 = fADC x 0.005 x TW fCENTER = f0 + 0.14 x fADC f1 = f0 + 0.28 x fADC Data Sheet AD6684 VARIABLE DYNAMIC RANGE (VDR) The AD6684 features a VDR digital processing block to allow up to a 14-bit dynamic range to be maintained in a subset of the Nyquist band. Across the full Nyquist band, a minimum 9-bit dynamic range is available at all times. This operation is suitable for applications such as DPD processing. The harmonic performance of the receiver is unaffected by this feature. When enabled, VDR does not contribute loss to the input signal but operates by effectively changing the output resolution at the output pins. This feature can be independently controlled per channel via the SPI. The VDR block operates in either complex or real mode. In complex mode, VDR has selectable bandwidths of 25% and 43% of the output sample rate. In real mode, the bandwidth of operation is limited to 25% of the output sample rate. The bandwidth and mode of the VDR operation are selected by setting the appropriate bits in Register 0x0430. When the VDR block is enabled, input signals that violate a defined mask (signified by the gray shaded areas in Figure 84) result in the reduction of the output resolution of the AD6684. The VDR block analyzes the peak value of the aggregate signal level in the disallowed zones to determine the reduction of the output resolution. To indicate that the AD6684 is reducing output, the resolution VDR punish bits and/or a VDR high/low resolution bit can optionally be inserted into the output data stream as control bits by programming the appropriate value into Register 0x0559 and Register 0x055A. Up to two control bits can be used without the need to change the converter resolution parameter, N. Up to three control bits can be used, but if using three, the converter resolution parameter, N, must be changed to 13. The VDR high/low resolution bit can be programmed into either of the three available control bits and indicates if VDR is reducing output resolution (bit value is a 1), or if full resolution is available (bit value is a 0). Enable the two punish bits to provide a clearer indication of the available resolution of the sample. To decode these two bits, see Table 24. Table 24. VDR Reduced Output Resolution Values VDR Punish Bits[1:0] 00 01 10 11 Output Resolution (Bits) 14 13 12 or 11 10 or 9 The frequency zones of the mask are defined by the bandwidth mode selected in Register 0x0430. The upper amplitude limit for input signals located in these frequency zones is -30 dBFS. If the input signal level in the disallowed frequency zones exceeds an amplitude level of -30 dBFS (into the gray shaded areas), the VDR block triggers a reduction in the output resolution, as shown in Figure 84. The VDR block engages and begins limiting output resolution gradually as the signal amplitudes increase in the mask regions. As the signal amplitude level increases into the mask regions, the output resolution is gradually lowered. For every 6 dB increase in signal level above -30 dBFS, one bit of output resolution is discarded from the output data by the VDR block, as shown in Table 25. These zones can be tuned within the Nyquist band by setting Bits[3:0] in Register 0x0434 to determine the VDR center frequency (fVDR). The VDR center frequency in complex mode can be adjusted from 1/16 fS to 15/16 fS in 1/16 fS steps. In real mode, fVDR can be adjusted from 1/8 fS to 3/8 fS in 1/16 fS steps. Table 25. VDR Reduced Output Resolution Values Signal Amplitude Violating Defined VDR Mask Amplitude -30 dBFS -30 dBFS < amplitude -24 dBFS -24 dBFS < amplitude -18 dBFS -18 dBFS < amplitude -12 dBFS -12 dBFS < amplitude -6 dBFS -6 dBFS < amplitude 0 dBFS Output Resolution (Bits) 14 13 12 11 10 9 dBFS 0 fS 0 INTERMODULATION PRODUCTS < -30dBFS fS INTERMODULATION PRODUCTS > -30dBFS Figure 84. VDR Operation--Reduction in Output Resolution Rev. A | Page 51 of 99 14994-072 -30 AD6684 Data Sheet VDR REAL MODE VDR COMPLEX MODE The real mode of VDR works over a bandwidth of 25% of the sample rate (50% of the Nyquist band). The output bandwidth of the AD6684 can be 25% only when operating in real mode. Figure 85 shows the frequency zones for the 25% bandwidth real output VDR mode tuned to a center frequency (fVDR) of fS/4 (tuning word = 0x04). The frequency zones where the amplitude cannot exceed -30 dBFS are the upper and lower portions of the Nyquist band signified by the gray shaded areas. The complex mode of VDR works with selectable bandwidths of 25% of the sample rate (50% of the Nyquist band) and 43% of the sample rate (86% of the Nyquist band). Figure 86 and Figure 87 show the frequency zones for VDR in the complex mode. When operating VDR in complex mode, place in-phase (I) input signal data in Channel A and place quadrature (Q) signal data in Channel B. dBFS Figure 86 shows the frequency zones for the 25% bandwidth VDR mode with a center frequency of fS/4 (tuning word = 0x04). The frequency zones where the amplitude may not exceed -30 dBFS are the upper and lower portions of the Nyquist band extending into the complex domain. dBFS -30 0 -1/2 fS 1/8 fS 3/8 fS 1/2 fS Figure 85. 25% VDR Bandwidth, Real Mode The center frequency (fVDR) of the VDR function can be tuned within the Nyquist band from 1/8 fS to 3/8 fS in 1/16 fS steps. In real mode, Tuning Word 2 (0x02) through Tuning Word 6 (0x06) are valid. Table 26 shows the relative frequency values, and Table 27 shows the absolute frequency values based on a sample rate of 491.52 MSPS. Table 26. VDR Tuning Words and Relative Frequency Values, 25% BW, Real Mode Tuning Word 2 (0x02) 3 (0x03) 4 (0x04) 5 (0x05) 6 (0x06) Lower Band Edge 0 1/16 fS 1/8 fS 3/16 fS 1/4 fS Center Frequency 1/8 fS 3/16 fS 1/4 fS 5/16 fS 3/8 fS Upper Band Edge 1/4 fS 5/16 fS 3/8 fS 7/16 fS 1/2 fS Table 27. VDR Tuning Words and Absolute Frequency Values, 25% BW, Real Mode (fS = 491.52 MSPS) Tuning Word 2 (0x02) 3 (0x03) 4 (0x04) 5 (0x05) 6 (0x06) Lower Band Edge (MHz) 0 30.72 61.44 92.16 122.88 Center Frequency (MHz) 61.44 92.16 122.88 153.6 184.32 3/8 fS 1/2 fS Figure 86. 25% VDR Bandwidth, Complex Mode 14994-073 0 1/8 fS 14994-074 -30 Upper Band Edge (MHz) 122.88 153.6 184.32 215.04 245.76 The center frequency (fVDR) of the VDR function can be tuned within the Nyquist band from 0 to 15/16 fS in 1/16 fS steps. In complex mode, Tuning Word 0 (0x00) through Tuning Word 15 (0x0F) are valid. Table 28 and Table 29 show the tuning words and frequency values for the 25% complex mode. Table 28 shows the relative frequency values, and Table 29 shows the absolute frequency values based on a sample rate of 491.52 MSPS. Table 28. VDR Tuning Words and Relative Frequency Values, 25% BW, Complex Mode Tuning Word 0 (0x00) 1 (0x01) 2 (0x02) 3 (0x03) 4 (0x04) 5 (0x05) 6 (0x06) 7 (0x07) 8 (0x08) 9 (0x09) 10 (0x0A) 11 (0x0B) 12 (0x0C) 13 (0x0D) 14 (0x0E) 15 (0x0F) Rev. A | Page 52 of 99 Lower Band Edge -1/8 fS -1/16 fS 0 1/16 fS 1/8 fS 3/16 fS 1/4 fS 5/16 fS 3/8 fS 7/16 fS 1/2 fS 9/16 fS 5/8 fS 11/16 fS 3/4 fS 13/16 fS Center Frequency 0 1/16 fS 1/8 fS 3/16 fS 1/4 fS 5/16 fS 3/8 fS 7/16 fS 1/2 fS 9/16 fS 5/8 fS 11/16 fS 3/4 fS 13/16 fS 7/8 fS 15/16 fS Upper Band Edge 1/8 fS 3/16 fS 1/4 fS 5/16 fS 3/8 fS 7/16 fS 1/2 fS 9/16 fS 5/8 fS 11/16 fS 3/4 fS 13/16 fS 7/8 fS 15/16 fS fS 17/16 fS Data Sheet AD6684 Table 30. VDR Tuning Words and Relative Frequency Values, 43% BW, Complex Mode Table 29. VDR Tuning Words and Absolute Frequency Values, 25% BW, Complex Mode (fS = 491.52 MSPS) Lower Band Edge (MHz) -61.44 -30.72 0.00 30.72 61.44 92.16 122.88 153.6 184.32 215.04 245.76 276.48 307.2 337.92 368.64 399.36 Tuning Word 0 (0x00) 1 (0x01) 2 (0x02) 3 (0x03) 4 (0x04) 5 (0x05) 6 (0x06) 7 (0x07) 8 (0x08) 9 (0x09) 10 (0x0A) 11 (0x0B) 12 (0x0C) 13 (0x0D) 14 (0x0E) 15 (0x0F) Center Frequency (MHz) 0.00 30.72 61.44 92.16 122.88 153.6 184.32 215.04 245.76 276.48 307.2 337.92 368.64 399.36 430.08 460.8 Upper Band Edge (MHz) 61.44 92.16 122.88 153.6 184.32 215.04 245.76 276.48 307.2 337.92 368.64 399.36 430.08 460.8 491.52 522.24 Tuning Word 0 (0x00) 1 (0x01) 2 (0x02) 3 (0x03) 4 (0x04) 5 (0x05) 6 (0x06) 7 (0x07) 8 (0x08) 9 (0x09) 10 (0x0A) 11 (0x0B) 12 (0x0C) 13 (0x0D) 14 (0x0E) 15 (0x0F) Table 30 and Table 31 show the tuning words and frequency values for the 43% complex mode. Table 30 shows the relative frequency values, and Table 31 shows the absolute frequency values based on a sample rate of 491.52 MSPS. Figure 87 shows the frequency zones for the 43% BW VDR mode with a center frequency (fVDR) of fS/4 (tuning word = 0x04). The frequency zones where the amplitude may not exceed -30 dBFS are the upper and lower portions of the Nyquist band extending into the complex domain. dBFS -1/2 fS 0 1/29 fS 1/4 fS 1/2 fS 20/43 fS Figure 87. 43% VDR Bandwidth, Complex Mode 14994-075 -30 Lower Band Edge (MHz) -14/65 fS -11/72 fS -1/11 fS -1/36 fS 1/29 fS 7/72 fS 4/25 fS 2/9 fS 2/7 fS 25/72 fS 34/83 fS 17/36 fS 23/43 fS 43/72 fS 31/47 fS 13/18 fS Center Frequency (MHz) 0 1/16 fS 1/8 fS 3/16 fS 1/4 fS 5/16 fS 3/8 fS 7/16 fS 1/2 fS 9/16 fS 5/8 fS 11/16 fS 3/4 fS 13/16 fS 7/8 fS 15/16 fS Upper Band Edge (MHz) 14/65 fS 5/18 fS 16/47 fS 29/72 fS 20/43 fS 19/36 fS 49/83 fS 47/72 fS 5/7 fS 7/9 fS 21/25 fS 65/72 fS 28/29 fS 37/36 fS 12/11 fS 83/72 fS Table 31. VDR Tuning Words and Absolute Frequency Values, 43% BW, Complex Mode (fS = 491.52 MSPS) Tuning Word 0 (0x00) 1 (0x01) 2 (0x02) 3 (0x03) 4 (0x04) 5 (0x05) 6 (0x06) 7 (0x07) 8 (0x08) 9 (0x09) 10 (0x0A) 11 (0x0B) 12 (0x0C) 13 (0x0D) 14 (0x0E) 15 (0x0F) Rev. A | Page 53 of 99 Lower Band Edge (MHz) -105.37 -75.09 -44.68 -13.65 16.95 47.79 78.64 109.23 140.43 170.67 201.35 232.11 262.91 293.55 324.19 354.99 Center Frequency (MHz) 0.00 30.72 61.44 92.16 122.88 153.6 184.32 215.04 245.76 276.48 307.2 337.92 368.64 399.36 430.08 460.8 Upper Band Edge (MHz) 105.87 136.53 167.33 197.97 228.61 259.41 290.17 320.85 351.09 382.29 412.88 443.73 474.57 505.17 536.2 566.61 AD6684 Data Sheet DIGITAL OUTPUTS INTRODUCTION TO THE JESD204B INTERFACE * The AD6684 digital outputs are designed to the JEDEC standard JESD204B, serial interface for data converters. JESD204B is a protocol to link the AD6684 to a digital processing device over a serial interface with lane rates of up to 15 Gbps. The benefits of the JESD204B interface over LVDS include a reduction in required board area for data interface routing, and an ability to enable smaller packages for converter and logic devices. JESD204B OVERVIEW The JESD204B data transmit blocks assemble the parallel data from the ADC into frames and uses 8-bit/10-bit encoding as well as optional scrambling to form serial output data. Lane synchronization is supported through the use of special control characters during the initial establishment of the link. Additional control characters are embedded in the data stream to maintain synchronization thereafter. A JESD204B receiver is required to complete the serial link. For additional details on the JESD204B interface, refer to the JESD204B standard. The JESD204B data transmit blocks in the AD6684 map up to two physical ADCs or up to four virtual converters (when the DDCs are enabled) over each of the two JESD204B links. Each link can be configured to use one or two JESD204B lanes for up to a total of four lanes for the AD6684 chip. The JESD204B specification refers to a number of parameters to define the link, and these parameters must match between the JESD204B transmitter (the AD6684 output) and the JESD204B receiver (the logic device input). The JESD204B outputs of the AD6684 function effectively as two individual JESD204B links. The two JESD204B links can be synchronized, if desired, using the SYSREF input. Each JESD204B link is described according to the following parameters: * * * * * * L = number of lanes per converter device (lanes per link) (AD6684 value = 1 or 2) M = number of converters per converter device (virtual converters per link) (AD6684 value = 1, 2, or 4) F = octets per frame (AD6684 value = 1, 2, 4, or 8) N = number of bits per sample (JESD204B word size) (AD6684 value = 8 or 16) N = converter resolution (AD6684 value = 7 to 16) CS = number of control bits per sample (AD6684 value = 0, 1, 2, or 3) * * * K = number of frames per multiframe (AD6684 value = 4, 8, 12, 16, 20, 24, 28, or 32 ) S = samples transmitted per single converter per frame cycle (AD6684 value = set automatically based on L, M, F, and N) HD = high density mode (AD6684 = set automatically based on L, M, F, and N) CF = number of control words per frame clock cycle per converter device (AD6684 value = 0) Figure 88 shows a simplified block diagram of the AD6684 JESD204B link. By default, the AD6684 is configured to use four converters and four lanes. The Converter A and Converter B data is output to SERDOUTAB0 and SERDOUTAB1, and the Converter C and Converter D data is output to SERDOUTCD0 and SERDOUTCD1. The AD6684 allows other configurations, such as combining the outputs of each pair of converters into a single lane, or changing the mapping of the digital output paths. These modes are set up via a quick configuration register in the SPI register map, along with additional customizable options. By default in the AD6684, the 14-bit converter word from each converter is broken into two octets (eight bits of data). Bit 13 (MSB) through Bit 6 are in the first octet. The second octet contains Bit 5 through Bit 0 (LSB) and two tail bits. The tail bits can be configured as zeros or a pseudorandom number sequence. The tail bits can also be replaced with control bits indicating overrange, SYSREF, VDR punish bits, or fast detect output. Control bits are filled and inserted MSB first such that enabling CS = 1 activates Control Bit 2, enabling CS = 2 activates Control Bit 2 and Control Bit 1, and enabling CS = 3 activates Control Bit 2, Control Bit 1, and Control Bit 0. The two resulting octets can be scrambled. Scrambling is optional; however, it is recommended to avoid spectral peaks when transmitting similar digital data patterns. The scrambler uses a self synchronizing, polynomial-based algorithm defined by the equation 1 + x14 + x15. The descrambler in the receiver is a self synchronizing version of the scrambler polynomial. The two octets are then encoded with an 8-bit/10-bit encoder. The 8-bit/10-bit encoder works by taking eight bits of data (an octet) and encoding them into a 10-bit symbol. Figure 89 shows how the 14-bit data is taken from the ADC, the tail bits are added, the two octets are scrambled, and how the octets are encoded into two 10-bit symbols. Figure 89 shows the default data format. Rev. A | Page 54 of 99 Data Sheet AD6684 CONVERTER A INPUT ADC A CONVERTER B INPUT MUX/ FORMAT (SPI REGISTERS: 0x0561, 0x0564) JESD204B PAIR A/B LINK CONTROL (L, M, F) (SPI REGISTER 0x0570) LANE MUX AND MAPPING (SPI REGISTERS: 0x05B0, 0x05B2, 0x05B3) MUX/ FORMAT (SPI REGISTERS: 0x0561, 0x0564) JESD204B PAIR A/B LINK CONTROL (L, M, F) (SPI REGISTER 0x0570) LANE MUX AND MAPPING (SPI REGISTERS: 0x05B0, 0x05B2, 0x05B3) SERDOUTAB0+ SERDOUTAB0- SERDOUTAB1+ SERDOUTAB1- ADC B SYSREF SYNCINAB SYNCINCD CONVERTER C INPUT CONVERTER D INPUT SERDOUTCD0+ SERDOUTCD0- SERDOUTCD1+ SERDOUTCD1- 14994-076 ADC C ADC D Figure 88. Transmit Link Simplified Block Diagram Showing Full Bandwidth Mode (Register 0x0200 = 0x00) LSB CONTROL BITS MSB A13 A5 TAIL BITS REG 0x0571[6] LSB A12 A11 A10 A9 A8 A7 A6 MSB A4 A3 A2 A1 A0 C2 T LSB 8-BIT/10-BIT ENCODER S7 S6 S5 S4 S3 S2 S1 S0 a b .... OCTET1 OCTET0 JESD204B SAMPLE CONSTRUCTION A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 SCRAMBLER 1 + x14 + x15 (OPTIONAL) SERDOUTAB0/ SERDOUTCD0/ SERDOUTAB0/ SERDOUTCD0/ SERIALIZER i j a b .... SYMBOL0 a b c d e f g h i j a b c d e f g h i j i j SYMBOL1 S7 S6 S5 S4 S3 S2 S1 S0 14994-077 ADC OCTET0 FRAME CONSTRUCTION OCTET1 ADC TEST PATTERNS (REG 0x0550, REG 0x0551 TO REG 0x0558) MSB A13 JESD204B DATA LINK LAYER TEST PATTERNS REG 0x0574[2:0] JESD204B INTERFACE TEST PATTERNS (REG 0x0573, REG 0x0551 TO REG 0x0558) JESD204B LONG TRANSPORT TEST PATTERN REG 0x0571[5] C2 C1 C0 Figure 89. ADC Output Datapath Showing Data Framing DATA LINK LAYER PROCESSED SAMPLES FROM ADC SAMPLE CONSTRUCTION FRAME CONSTRUCTION SCRAMBLER ALIGNMENT CHARACTER GENERATION 8-BIT/10-BIT ENCODER PHYSICAL LAYER CROSSBAR MUX SERIALIZER Tx OUTPUT 14994-078 TRANSPORT LAYER SYSREF SYNCINB Figure 90. Data Flow Rev. A | Page 55 of 99 AD6684 Data Sheet FUNCTIONAL OVERVIEW The block diagram in Figure 90 shows the flow of data through each of the two JESD204B links from the sample input to the physical output. The processing can be divided into layers that are derived from the open source initiative (OSI) model widely used to describe the abstraction layers of communications systems. These layers are the transport layer, data link layer, and physical layer (serializer and output driver). Transport Layer The transport layer handles packing the data (consisting of samples and optional control bits) into JESD204B frames that are mapped to 8-bit octets. These octets are sent to the data link layer. The transport layer mapping is controlled by rules derived from the link parameters. Tail bits are added to fill gaps where required. The following equation can be used to determine the number of tail bits within a sample (JESD204B word): T = N - N - CS Data Link Layer Physical Layer The physical layer consists of the high speed circuitry clocked at the serial clock rate. In this layer, parallel data is converted into one, two, or four lanes of high speed differential serial data. JESD204B LINK ESTABLISHMENT The AD6684 JESD204B transmitter (Tx) interface operates in Subclass 1 as defined in the JEDEC Standard 204B (July 2011 specification). The link establishment process is divided into the following steps: code group synchronization and SYNCINBAB/ SYNCINBCD, initial lane alignment sequence, and user data and error correction. The CGS is the process by which the JESD204B receiver finds the boundaries between the 10-bit symbols in the stream of data. During the CGS phase, the JESD204B transmit block transmits /K28.5/ characters. The receiver must locate /K28.5/ C D For more information on the code group synchronization phase, refer to the JEDEC Standard JESD204B, July 2011, Section 5.3.3.1. The SYNCINBAB and SYNCINBCD pin operation can also be controlled by the SPI. The SYNCINBAB and SYNCINBCD signals are differential LVDS mode signals by default, but can also be driven single-ended. For more information on configuring the SYNCINBAB and SYNCINBCD pin operation, refer to Register 0x0572. The ILAS phase follows the CGS phase and begins on the next LMFC boundary. The ILAS consists of four mulitframes, with an /R/ character marking the beginning and an /A/ character marking the end. The ILAS begins by sending an /R/ character followed by 0 to 255 ramp data for one multiframe. On the second multiframe, the link configuration data is sent, starting with the third character. The second character is a /Q/ character to confirm that the link configuration data follows. All undefined data slots are filled with ramp data. The ILAS sequence is never scrambled. The ILAS sequence construction is shown in Figure 91. The four multiframes include the following: * * * Code Group Synchronization (CGS) and SYNCINB D A R Q C The receiver issues a synchronization request by asserting the SYNCINBAB and SYNCINBCD pins of the AD6684 low. The JESD204B Tx then begins sending /K/ characters. After the receiver synchronizes, it waits for the correct reception of at least four consecutive /K/ symbols. It then deasserts SYNCINBAB and SYNCINBCD. The AD6684 then transmits an ILAS on the following local multiframe clock (LMFC) boundary. Initial Lane Alignment Sequence (ILAS) The data link layer is responsible for the low level functions of passing data across the link. These functions include optionally scrambling the data, inserting control characters for multichip synchronization, lane alignment, or monitoring, and encoding 8-bit octets into 10-bit symbols. The data link layer is also responsible for sending the initial lane alignment sequence (ILAS), which contains the link configuration data used by the receiver to verify the settings in the transport layer. K K R D characters in its input data stream using clock and data recovery (CDR) techniques. * D A R D Multiframe 1. Begins with an /R/ character (/K28.0/) and ends with an /A/ character (/K28.3/). Multiframe 2. Begins with an /R/ character followed by a /Q/ (/K28.4/) character, followed by link configuration parameters over 14 configuration octets (see Table 32) and ends with an /A/ character. Many of the parameter values are of the value - 1 notation. Multiframe 3. Begins with an /R/ character (/K28.0/) and ends with an /A/ character (/K28.3/). Multiframe 4. Begins with an /R/ character (/K28.0/) and ends with an /A/ character (/K28.3/). D A R D D A D START OF ILAS START OF USER DATA START OF LINK CONFIGURATION DATA Figure 91. Initial Lane Alignment Sequence Rev. A | Page 56 of 99 14994-079 END OF MULTIFRAME Data Sheet AD6684 After the initial lane alignment sequence is complete, the user data is sent. Normally, within a frame, all characters are considered user data. However, to monitor the frame clock and multiframe clock synchronization, there is a mechanism for replacing characters with /F/ or /A/ alignment characters when the data meets certain conditions. These conditions are different for unscrambled and scrambled data. The scrambling operation is enabled by default, but it can be disabled using the SPI. For scrambled data, any 0xFC character at the end of a frame is replaced with an /F/, and any 0xFD character at the end of a multiframe is replaced with an /A/. The JESD204B receiver (Rx) checks for /F/ and /A/ characters in the received data stream and verifies that they only occur in the expected locations. If an unexpected /F/ or /A/ character is found, the receiver handles the situation by using dynamic realignment or asserting the SYNCINB signal for more than four frames to initiate a resynchronization. For unscrambled data, if the final character of two subsequent frames are equal, the second character is replaced with an /F/ if it is at the end of a frame, and an /A/ if it is at the end of a multiframe. The 8-bit/10-bit interface has options that can be controlled via the SPI. These operations include bypass and invert. These options are intended to be troubleshooting tools for the verification of the digital front end (DFE). Refer to the Memory Map section, Register 0x0572, Bits[2:1] for information on configuring the 8-bit/ 10-bit encoder. PHYSICAL LAYER (DRIVER) OUTPUTS Digital Outputs, Timing, and Controls The AD6684 physical layer consists of drivers that are defined in the JEDEC Standard JESD204B, July 2011. The differential digital outputs are powered up by default. The drivers use a dynamic 100 internal termination to reduce unwanted reflections. Place a 100 differential termination resistor at each receiver input to result in a nominal 300 mV p-p swing at the receiver (see Figure 92). Alternatively, single-ended 50 termination can be used. When single-ended termination is used, the termination voltage is DRVDD1/2. Otherwise, 0.1 F ac coupling capacitors can be used to terminate to any singleended voltage. Insertion of alignment characters can be modified using the SPI. The frame alignment character insertion (FACI) is enabled by default. More information on the link controls is available in the Memory Map section, Register 0x0571. VRXCM DRVDD 50 100 DIFFERENTIAL 0.1F TRACE PAIR SERDOUTx+ 8-Bit/10-Bit Encoder 100 The 8-bit/10-bit encoder converts 8-bit octets into 10-bit symbols and inserts control characters into the stream when needed. The control characters used in JESD204B are shown in Table 32. The 8-bit/10-bit encoding ensures that the signal is dc balanced by using the same number of ones and zeros across multiple symbols. 50 OR RECEIVER SERDOUTx- 0.1F OUTPUT SWING = 300mV p-p VCM = VRXCM 14994-080 User Data and Error Detection Figure 92. AC-Coupled Digital Output Termination Example Table 32. AD6684 Control Characters used in JESD204B Abbreviation /R/ /A/ /Q/ /K/ /F/ 1 Control Symbol /K28.0/ /K28.3/ /K28.4/ /K28.5/ /K28.7/ 8-Bit Value 000 11100 011 11100 100 11100 101 11100 111 11100 10-Bit Value, RD 1 = -1 001111 0100 001111 0011 001111 0100 001111 1010 001111 1000 RD means running disparity. Rev. A | Page 57 of 99 10-Bit Value, RD1 = +1 110000 1011 110000 1100 110000 1101 110000 0101 110000 0111 Description Start of multiframe Lane alignment Start of link configuration data Group synchronization Frame alignment AD6684 Data Sheet Figure 94 shows deterministic jitter vs. insertion loss. 30 25 100 DIFFERENTIAL TRACE PAIR SERDOUTx+ 15 10 POST POST POST POST 5 100 RECEIVER 0 SERDOUTx- 2.500 4.970 7.120 9.170 11.410 13.770 EMPHASIS = 0 EMPHASIS = 1 EMPHASIS = 2 EMPHASIS = 3 15.340 17.420 19.460 VCM = DRVDD/2 Figure 93. DC-Coupled Digital Output Termination Example If there is no far end receiver termination, or if there is poor differential trace routing, timing errors may result. To avoid such timing errors, it is recommended that the trace length be less than six inches, and that the differential output traces be close together and at equal lengths. Figure 95, Figure 96, and Figure 97 show examples of the digital output data eye, time interval error (TIE) jitter histogram, and bathtub curve, respectively, for one AD6684 lane running at 15 Gbps. The format of the output data is twos complement by default. To change the output data format, see the Memory Map section (Register 0x0561 in Table 46). De-Emphasis De-emphasis enables the receiver eye diagram mask to be met in conditions where the interconnect insertion loss does not meet the JESD204B specification. Use the pre-emphasis feature only when the receiver is unable to recover the clock due to excessive insertion loss. Under normal conditions, pre-emphasis is disabled to conserve power. Additionally, enabling and setting too high a pre-emphasis value on a short link can cause the receiver eye diagram to fail. Use the pre-emphasis setting with caution because it can increase electromagnetic interference (EMI). See the Memory Map section (Registers 0x05C4 and Register 0x05C6 in Table 46) for more details. Figure 94. Deterministic Jitter vs. Insertion Loss Phase-Locked Loop The phase-locked loop (PLL) is used to generate the serializer clock, which operates at the JESD204B lane rate. The status of the PLL lock can be checked in the PLL lock status bit (Register 0x056F, Bit 7). This read only bit lets the user know if the PLL has achieved a lock for the specific setup. The JESD204B lane rate control bit, Bit 4 of Register 0x056E, must be set to correspond with the lane rate. 500 400 300 200 VOLTAGE (mV) OUTPUT SWING = 300mV p-p 14994-081 INSERTION LOSS (dB) De-Emphasis Setting 0 1 2 3 -100 Tx EYE MASK -300 -400 -500 -60 -40 -20 0 TIME (ps) 20 40 60 Figure 95. AD6684 Digital Outputs Data Eye Diagram; External 100 Terminations at 15 Gbps Table 33. Insertion Loss Table Voltage Swing Setting 0 0 0 0 0 -200 Table 33 shows the insertion loss with respect to the emphasis settings. Insertion Loss (dB) 0 to 4 4 to 9 9 to 14 >14 100 14994-140 DRVDD 20 14994-144 DETERMINISTIC JITTER (ps) The AD6684 digital outputs can interface with custom application specific integrated circuits (ASICs) and field programmable gate array (FPGA) receivers, providing superior switching performance in noisy environments. Single point to point network topologies are recommended with a single differential 100 termination resistor placed as close to the receiver inputs as possible. The common mode of the digital output automatically biases itself to half the DRVDD1 supply of 1.25 V (VCM = 0.6 V). See Figure 93 for an example of dc coupling the outputs to the receiver logic. Post Tap Level (dB) 0 3 6 9 Rev. A | Page 58 of 99 Data Sheet AD6684 16000 JESD204B Tx CONVERTER MAPPING 14000 To support the different chip operating modes, the AD6684 design treats each sample stream (real or I/Q) as originating from separate virtual converters. The I/Q samples are always mapped in pairs with the I samples mapped to the first virtual converter and the Q samples mapped to the second virtual converter. With this transport layer mapping, the number of virtual converters are the same whether 12000 8000 6000 * 4000 2000 * -4 -2 0 2 4 14994-141 0 6 TIME (ps) Figure 96. AD6684 Digital Outputs Histogram; External 100 Terminations at 15 Gbps Figure 98 shows a block diagram of the two scenarios described for I/Q transport layer mapping. The JESD204B Tx block for AD6684 supports up to four DDC blocks. Each DDC block outputs either two sample streams (I/Q) for the complex data components (real + imaginary), or one sample stream for real (I) data. The JESD204B interface can be configured to use up to eight virtual converters depending on the DDC configuration. Figure 99 shows the virtual converters and their relationship to the DDC outputs when complex outputs are used. Table 34 shows the virtual converter mapping for each chip operating mode when channel swapping is disabled. 1 1-2 1-4 1-6 1-8 1-10 1-12 1-14 1-16 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 UI 14994-142 BER A single real converter is used along with a digital downconverter block producing I/Q outputs, or An analog downconversion is used with two real converters producing I/Q outputs. Figure 97. AD6684 Digital Outputs Bathtub Curve; External 100 Terminations at 15 Gbps DIGITAL DOWNCONVERSION M=2 I CONVERTER 0 REAL ADC REAL DIGITAL DOWNCONVERSION JESD204B Tx L LANES JESD204B Tx L LANES Q CONVERTER 1 I REAL I/Q ANALOG MIXING M=2 I CONVERTER 0 ADC 90 PHASE Q ADC Q CONVERTER 1 Figure 98. I/Q Transport Layer Mapping Rev. A | Page 59 of 99 14994-084 HITS 10000 AD6684 Data Sheet ADC SAMPLING AT fS REAL/I REAL/Q I/Q CROSSBAR MUX REAL/Q REAL/I ADC SAMPLING AT fS REAL/I REAL/Q ADC A SAMPLING AT fS REAL/I I/Q CROSSBAR MUX REAL/Q ADC SAMPLING AT fS REAL/Q REAL/I REAL/Q DDC 0 I I Q Q DDC 1 I I Q Q DDC 0 I I Q Q REAL/I CONVERTER 0 Q CONVERTER 1 OUTPUT INTERFACE REAL/I CONVERTER 2 Q CONVERTER 3 REAL/I CONVERTER 4 Q CONVERTER 5 OUTPUT INTERFACE DDC 1 I I Q Q REAL/I CONVERTER 6 Q CONVERTER 7 14994-085 REAL/I Figure 99. DDCs and Virtual Converter Mapping SETTING UP THE AD6684 DIGITAL INTERFACE The following SPI writes are required for the AD6684 at startup and each time the ADC is reset (datapath reset, soft reset, link power-down/power-up, or hard reset): 1. 2. 3. 4. 5. 6. Write 0x4F to Register 0x1228. Write 0x0F to Register 0x1228. Write 0x04 to Register 0x1222. Write 0x00 to Register 0x1222. Write 0x08 to Register 0x1262. Write 0x00 to Register 0x1262. 10 M x N 'x x fOUT 8 Lane Line Rate = L where: fOUT = The AD6684 has two JESD204B links. The device offers an easy way to set up the JESD204B link through the JESD204B quick configuration register (Register 0x0570). The serial outputs (SERDOUTABx and SERDOUTCDx) are considered to be part of one JESD204B link. The basic parameters that determine the link setup are * * * The maximum lane rate allowed by the JESD204B specification is 15 Gbps. The lane line rate is related to the JESD204B parameters using the following equation: Number of lanes per link (L) Number of converters per link (M) Number of octets per frame (F) If the internal DDCs are used for on-chip digital processing, M represents the number of virtual converters. The virtual converter mapping setup is shown in Figure 99. f ADC _ CLOCK Decimation Ratio The decimation ratio (DCM) is the parameter programmed in Register 0x0201. Use the following steps to configure the output: 1. 2. 3. 4. 5. 6. Power down the link. Select quick configuration options. Configure detailed options Set output lane mapping (optional). Set additional driver configuration options (optional). Power up the link. If the lane line rate calculated is less than 6.75 Gbps, select the low line rate option by programming a value of 0x10 to Register 0x056E. Table 35 and Table 36 show the JESD204B output configurations for both N = 16 and N = 8 for a given number of virtual converters. Take care to ensure that the serial line rate for given configuration is within the supported range of 1.6875 Gbps to 15 Gbps. Rev. A | Page 60 of 99 Data Sheet AD6684 Table 34. Virtual Converter Mapping (Per Link) Number of Virtual Converters Supported 1 to 2 Chip Application Mode (Register 0x0200, Bits[3:0]) Full bandwidth mode (0x0) Chip Q Ignore (Register 0x0200, Bit 5) Real or complex (0x0) 1 One DDC mode (0x1) Real (I only) (0x1) 2 One DDC mode (0x1) Complex (I/Q) (0x0) 2 Two DDC mode (0x2) Real (I only) (0x1) 4 Two DDC mode (0x2) Complex (I/Q) (0x0) Virtual Converter Mapping 0 ADC A/C samples DDC 0 I samples DDC 0 I samples DDC 0 I samples DDC 0 I samples 1 ADC B/D samples Unused 2 Unused 3 Unused Unused Unused DDC 0 Q samples DDC 1 I samples DDC 0 Q samples Unused Unused Unused Unused DDC 1 I samples DDC 1 Q samples Table 35. JESD204B Output Configurations for N= 16 Number of Virtual Converters Supported (Same Value as M) 1 2 4 JESD204B Quick Configuration (0x0570) 0x01 0x40 0x41 0x0A 0x49 0x13 0x52 JESD204B Transport Layer Settings 2 JESD204B Serial Line Rate 1 20 x fOUT 10 x fOUT 10 x fOUT 40 x fOUT 20 x fOUT 80 x fOUT 40 x fOUT L 1 2 2 1 2 1 2 M 1 1 1 2 2 4 4 F 2 1 2 4 2 8 4 S 1 1 2 1 1 1 1 HD 0 1 0 0 0 0 0 N 8 to 16 8 to 16 8 to 16 8 to 16 8 to 16 8 to 16 8 to 16 N 16 16 16 16 16 16 16 CS 0 to 3 0 to 3 0 to 3 0 to 3 0 to 3 0 to 3 0 to 3 K3 Only valid K values that are divisible by 4 are supported fOUT = output sample rate = ADC sample rate/chip decimation ratio. The JESD204B serial line rate must be 1687.5 Mbps and 15,000 Mbps. When the serial line rate is 15 Gbps and >13.5 Gbps, set Bits[7:4] to 0x3 in Register 0x056E. When the serial line rate is 13.5 Gbps and > 6.75 Gbps, set Bits[7:4] to 0x0 in Register 0x056E. When the serial line rate is 6.75 Gbps and > 3.375 Gbps, set Bits[7:4] to 0x1 in Register 0x056E. When the serial line rate is 3.375 Gbps and 1687.5 Mbps, set Bits[7:4] to 0x5 in Register 0x056E. 2 JESD204B transport layer descriptions are as described in the JESD204B Overview section. 3 For F = 1, K = 20, 24, 28, and 32. For F = 2, K = 12, 16, 20, 24, 28, and 32. For F = 4, K = 8, 12, 16, 20, 24, 28, and 32. For F = 8 and F = 16, K = 4, 8, 12, 16, 20, 24, 28, and 32. 1 Table 36. JESD204B Output Configurations for N= 8 Number of Virtual Converters Supported (Same Value as M) 1 2 JESD204B Quick Configuration (Register 0x0570) 0x00 0x01 0x40 0x41 0x42 0x09 0x48 0x49 JESD204B Transport Layer Settings 2 Serial Line Rate 1 10 x fOUT 10 x fOUT 5 x fOUT 5 x fOUT 5 x fOUT 20 x fOUT 10 x fOUT 10 x fOUT L 1 1 2 2 2 1 2 2 M 1 1 1 1 1 2 2 2 F 1 2 1 2 4 2 1 2 S 1 2 2 4 8 1 1 2 HD 0 0 0 0 0 0 0 0 N 7 to 8 7 to 8 7 to 8 7 to 8 7 to 8 7 to 8 7 to 8 7 to 8 N 8 8 8 8 8 8 8 8 CS 0 to 1 0 to 1 0 to 1 0 to 1 0 to 1 0 to 1 0 to 1 0 to 1 K3 Only valid K values which are divisible by 4 are supported fOUT = output sample rate = ADC sample rate/chip decimation ratio. The JESD204B serial line rate must be 1687.5 Mbps and 15,000 Mbps. When the serial line rate is 15 Gbps and >13.5 Gbps, set Bits[7:4] to 0x3 in Register 0x056E. When the serial line rate is 13.5 Gbps and >6.75 Gbps, set Bits[7:4] to 0x0 in Register 0x056E. When the serial line rate is 6.75 Gbps and >3.375 Gbps, set Bits[7:4] to 0x1 in Register 0x056E. When the serial line rate is 3.375 Gbps and 1687.5 Mbps, set Bits[7:4] to 0x5 in Register 0x056E. 2 JESD204B transport layer descriptions are as described in the JESD204B Overview section. 3 For F = 1, K = 20, 24, 28, and 32. For F = 2, K = 12, 16, 20, 24, 28, and 32. For F = 4, K = 8, 12, 16, 20, 24, 28, and 32. For F = 8 and F = 16, K = 4, 8, 12, 16, 20, 24, 28, and 32. 1 Rev. A | Page 61 of 99 AD6684 Data Sheet Example 1: ADC with DDC Option (Two ADCs Plus Two DDCs in Each Pair) * * * * * The chip application mode is DDC mode (see Figure 100) with the following characteristics: Chip application mode = two DDC mode (see Figure 100) Two 14-bit converters at 500 MSPS Two DDC application layer mode with complex outputs (I/Q) Chip decimation ratio = 4 DDC decimation ratio = 4 (see Table 34) For L = 1, set Bits[7:4] to 0x1 in Register 0x056E. For L = 2, set Bits[7:4] to 0x5 in Register 0x056E. Example 1 shows the flexibility in the digital and lane configurations for the AD6684. The sample rate is 500 MSPS, but the outputs are all combined in either one or two lanes, depending on the I/O speed capability of the receiving device. The JESD204B output configuration is as follows: Virtual converters required = 4 (see Table 34) Output sample rate (fOUT) = 500/4 = 125 MSPS N = 16 bits REAL/I CONVERTER 0 Q CONVERTER 1 SYSREF GAIN = 0dB OR 6dB COMPLEX TO REAL CONVERSION (OPTIONAL) COMPLEX TO REAL CONVERSION (OPTIONAL) REAL/Q Q GAIN = 0dB OR 6dB NCO + MIXER (OPTIONAL) ADC SAMPLING AT fS HB1 FIR DCM = 2 I HB2 FIR DCM = BYPASS OR 2 REAL/I HB3 FIR DCM = BYPASS OR 2 DDC 1 REAL/I CONVERTER 2 JESD204B TRANSMIT INTERFACE COMPLEX TO REAL CONVERSION (OPTIONAL) GAIN = 0dB OR 6dB HB1 FIR DCM = 2 HB2 FIR DCM = BYPASS OR 2 HB3 FIR DCM = BYPASS OR 2 REAL/Q Q HB4 FIR DCM = BYPASS OR 2 REAL/Q NCO + MIXER (OPTIONAL) ADC SAMPLING AT fS I/Q CROSSBAR MUX REAL/I I HB4 FIR DCM = BYPASS OR 2 DDC 0 REAL/I L JESD204B LANES AT UP TO 15Gbps Q CONVERTER 3 SYSREF REAL/I CONVERTER 2 L JESD204B LANES AT UP TO 15Gbps Q CONVERTER 3 HB1 FIR DCM = 2 14994-086 COMPLEX TO REAL CONVERSION (OPTIONAL) NCO + MIXER (OPTIONAL) GAIN = 0dB OR 6dB I HB1 FIR DCM = 2 REAL/I JESD204B TRANSMIT INTERFACE Q CONVERTER 1 DDC 1 ADC SAMPLING AT fS SYNCHRONIZATION CONTROL CIRCUITS REAL/I CONVERTER 0 SYSREF REAL/Q Q SYSREF HB2 FIR DCM = BYPASS OR 2 REAL/Q Q HB3 FIR DCM = BYPASS OR 2 NCO + MIXER (OPTIONAL) HB3 FIR DCM = BYPASS OR 2 REAL/Q ADC SAMPLING AT fS HB4 FIR DCM = BYPASS OR 2 REAL/I I HB4 FIR DCM = BYPASS OR 2 DDC 0 REAL/I I/Q CROSSBAR MUX * * * HB2 FIR DCM = BYPASS OR 2 * * * * * N = 16 bits L = 1, M = 4, and F = 8 (quick configuration = 0x13) CS = 0 to 1 K = 32 Output serial line rate = 10 Gbps per lane (L = 1) or 5 Gbps per lane (L = 2) SYSREF Figure 100. Two ADC + Four DDC Mode in Each Pair Rev. A | Page 62 of 99 Data Sheet AD6684 Example 2: ADC with NSR Option (Two ADCs + NSR in Each Pair) The JESD204B output configuration is as follows: The chip application mode is NSR mode (see Figure 101) with the following characteristics: Two 14-bit converters at 500 MSPS NSR blocks enabled for each channel Chip decimation ratio = 1 REAL 14-BIT ADC CORE AT 500MSPS Virtual converters required = 2 (see Table 34). Output sample rate (fOUT) = 500 MSPS N = 16 bits N = 9 bits L = 2, M = 2, and F = 2 (quick configuration = 0x49) CS = 0 to 2 K = 32 Output serial lane rate = 10 Gbps per lane (L = 2) * Set Bits[7:4] to 0x0 in Register 0x056E NSR CONVERTER 0 (21% OR 28% BANDWIDTH) AT 500MSPS JESD204B TRANSMIT INTERFACE (JTX) REAL 14-BIT ADC CORE AT 500MSPS NSR CONVERTER 1 (21% OR 28% AT 500MSPS BANDWIDTH) REAL 14-BIT ADC CORE AT 500MSPS NSR CONVERTER 0 (21% OR 28% BANDWIDTH) AT 500MSPS JESD204B TRANSMIT INTERFACE (JTX) REAL 14-BIT ADC CORE AT 500MSPS NSR CONVERTER 1 (21% OR 28% BANDWIDTH) AT 500MSPS Figure 101. Two ADC + NSR Mode Rev. A | Page 63 of 99 1 OR 2 LANES AT UP TO 15Gbps 1 OR 2 LANES AT UP TO 15Gbps 14994-087 * * * * * * * * * * * AD6684 Data Sheet LATENCY END-TO-END TOTAL LATENCY Total latency in the AD6684 is dependent on the various digital signal processing (DSP) and JESD204B configuration modes. Latency is fixed at 28 encode clocks through the ADC itself, but the latency through the DSP and JESD204B blocks can vary greatly, depending on the configuration. Therefore, the total latency must be calculated based on the DSP options selected and the JESD204B configuration. Table 37 shows the combined latency through the ADC, DSP, and JESD204B blocks for some of the different application modes supported by the AD6684. Latency is in units of the encode clock. Table 37. Latency Through the AD6684 ADC Application Mode Full Bandwidth (9-Bit) DDC (HB1) 1 DDC (HB2 + HB1)1 DDC (HB3 +HB2 + HB1)1 DDC (HB4 + HB3 + HB2 + HB1)1 Decimate by 2 + NSR NSR 1 L 2 2 1 1 1 1 2 JESD204B Transport Layer Settings M F 2 2 4 4 4 8 4 8 4 8 2 4 2 2 No mixer, complex outputs. Rev. A | Page 64 of 99 Latency (Number of Encode Clocks) ADC + DSP JESD204B Total 30 14 44 92 17 109 162 13 175 292 28 320 548 39 587 64 6 70 38 16 54 Data Sheet AD6684 MULTICHIP SYNCHRONIZATION The AD6684 has a SYSREF input that provides flexible options for synchronizing the internal blocks. The SYSREF input is a source synchronous system reference signal that enables multichip synchronization. The input clock divider, DDCs, signal monitor block, and JESD204B link can be synchronized using the SYSREF input. For the highest level of timing accuracy, SYSREF must meet setup and hold requirements relative to the CLK input. The flowchart in Figure 102 describes the internal mechanism for multichip synchronization in the AD6684. The AD6684 supports several features that aid users in meeting the requirements set out for capturing a SYSREF signal. The SYSREF sample event can be defined as either a synchronous low to high transition, or a synchronous high to low transition. Additionally, the AD6684 allows the SYSREF signal to be sampled using either the rising edge or falling edge of the CLK input. The AD6684 also has the ability to ignore a programmable number (up to 16) of SYSREF events. The SYSREF control options can be selected using Register 0x0120 and Register 0x0121. Rev. A | Page 65 of 99 AD6684 Data Sheet START INCREMENT SYSREF IGNORE COUNTER NO NO RESET SYSREF IGNORE COUNTER SYSREF ENABLED? (0x0120) NO NO SYSREF ASSERTED? YES UPDATE SETUP/HOLD DETECTOR STATUS (0x0128) YES SYSREF IGNORE COUNTER EXPIRED? (0x0121) YES ALIGN CLOCK DIVIDER PHASE TO SYSREF INPUT CLOCK DIVIDER ALIGNMENT REQUIRED? YES YES NO SYNCHRONIZATION MODE? (0x01FF) CLOCK DIVIDER AUTO ADJUST ENABLED? (0x0108) NO TIMESTAMP MODE SYSREF TIMESTAMP DELAY (0x0123) INCREMENT SYSREF COUNTER (0x012A) CLOCK DIVIDER > 1? (0x010B) YES NO SYSREF CONTROL BITS? (0x0559, 0x055A, 0x058F) YES SYSREF INSERTED IN JESD204B CONTROL BITS NO RAMP TEST MODE ENABLED? (0x0550) NORMAL MODE YES SYSREF RESETS RAMP TEST MODE GENERATOR BACK TO START NO YES ALIGN PHASE OF ALL INTERNAL CLOCKS (INCLUDING LMFC) TO SYSREF SEND INVALID 8-BIT/10-BIT CHARACTERS (ALL ZEROS) SYNC~ ASSERTED NO SEND K28.5 CHARACTERS NORMAL JESD204B INITIALIZATION NO NO SIGNAL MONITOR ALIGNMENT ENABLED? (0x026F) YES YES ALIGN SIGNAL MONITOR COUNTERS DDC NCO ALIGNMENT ENABLED? (0x0300) YES NO Figure 102. Multichip Synchronization Rev. A | Page 66 of 99 ALIGN DDC NCO PHASE ACCUMULATOR BACK TO START 14994-088 JESD204B LMFC ALIGNMENT REQUIRED? Data Sheet AD6684 SYSREF SETUP/HOLD WINDOW MONITOR To ensure a valid SYSREF signal capture, the AD6684 has a SYSREF setup/hold window monitor. This feature allows the system designer to determine the location of the SYSREF signals relative to the CLK signals by reading back the amount of setup/hold margin on the interface through the memory map. Figure 103 and Figure 104 show the setup and hold status values for different phases of SYSREF. The setup detector returns the status of the SYSREF signal before the CLK edge, and the hold detector returns the status of the SYSREF signal after the CLK edge. Register 0x0128 stores the status of SYSREF and lets the user know if the SYSREF signal is captured by the ADC. 0xF 0xE 0xD 0xC 0xB 0xA 0x9 REG 0x0128[3:0] 0x8 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 CLK INPUT SYSREF INPUT VALID FLIP FLOP SETUP (MIN) FLIP FLOP HOLD (MIN) 14994-089 FLIP FLOP HOLD (MIN) Figure 103. SYSREF Setup Detector 0xF 0xE 0xD 0xC 0xB 0xA 0x9 0x8 0x7 0x6 0x5 0x4 0x3 0x2 0x1 REG 0x0128[7:4] 0x0 CLK INPUT SYSREF INPUT FLIP-FLOP SETUP (MIN) FLIP-FLOP HOLD (MIN) FLIP-FLOP HOLD (MIN) Figure 104. SYSREF Hold Detector Rev. A | Page 67 of 99 14994-090 VALID AD6684 Data Sheet Table 38 shows the description of the contents of Register 0x0128 and how to interpret them. Table 38. SYSREF Setup/Hold Monitor, Register 0x0128 Register 0x0128, Bits[7:4], Hold Status 0x0 0x0 to 0x8 0x8 0x8 0x9 to 0xF 0x0 Register 0x0128, Bits[3:0], Setup Status 0x0 to 0x7 0x8 0x9 to 0xF 0x0 0x0 0x0 Description Possible setup error. The smaller this number, the smaller the setup margin. No setup or hold error (best hold margin). No setup or hold error (best setup and hold margin). No setup or hold error (best setup margin). Possible hold error. The larger this number, the smaller the hold margin. Possible setup or hold error. Rev. A | Page 68 of 99 Data Sheet AD6684 TEST MODES ADC TEST MODES The AD6684 has various test options that aid in the system level implementation. The AD6684 has ADC test modes that are available in Register 0x0550. These test modes are described in Table 39. When an output test mode is enabled, the analog section of the ADC is disconnected from the digital back-end blocks, and the test pattern is run through the output formatting block. Some of the test patterns are subject to output formatting, and some are not. The PN generators from the PN sequence tests can be reset by setting Bit 4 or Bit 5 of Register 0x0550. These tests can be performed with or without an analog signal (if present, the analog signal is ignored); however, they do require an encode clock. If the application mode is set to select a DDC mode of operation, the test modes must be enabled for each DDC enabled. The test patterns can be enabled via Bit 2 and Bit 0 of Register 0x0327, Register 0x0347, depending on which DDC(s) are selected. The (I) data uses the test patterns selected for Channel A, and the (Q) data uses the test patterns selected for Channel B. For more information, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. Table 39. ADC Test Modes Output Test Mode Bit Sequence 0000 0001 0010 0011 0100 0101 0110 0111 Default/ Seed Value Not applicable Not applicable Not applicable Not applicable Not applicable 0x3AFF 0x0092 Not applicable Expression Not applicable 00 0000 0000 0000 01 1111 1111 1111 10 0000 0000 0000 10 1010 1010 1010 x23 + x18 + 1 x9 + x5 + 1 11 1111 1111 1111 1000 Pattern Name Off (default) Midscale short +Full-scale short -Full-scale short Checkerboard PN sequence long PN sequence short One word/zero word toggle User input Register 0x0551 to Register 0x0558 Not applicable 1111 Ramp output (x) % 214 Not applicable Rev. A | Page 69 of 99 Sample (N, N + 1, N + 2, ...) Not applicable Not applicable Not applicable Not applicable 0x1555, 0x2AAA, 0x1555, 0x2AAA, 0x1555 0x3FD7, 0x0002, 0x26E0, 0x0A3D, 0x1CA6 0x125B, 0x3C9A, 0x2660, 0x0c65, 0x0697 0x0000, 0x3FFF, 0x0000, 0x3FFF, 0x0000 User Pattern 1[15:2], User Pattern 2[15:2], User Pattern 3[15:2], User Pattern 4[15:2], User Pattern 1[15:2] ... for repeat mode User Pattern 1[15:2], User Pattern 2[15:2], User Pattern 3[15:2], User Pattern 4[15:2], 0x0000 ... for single mode (x) % 214, (x +1) % 214, (x +2) % 214, (x +3) % 214 AD6684 Data Sheet JESD204B BLOCK TEST MODES In addition to the ADC pipeline test modes, the AD6684 also has flexible test modes in the JESD204B block. These test modes are listed in Register 0x0573 and Register 0x0574. These test patterns can be injected at various points along the output datapath. These test injection points are shown in Figure 89. Table 40 describes the various test modes available in the JESD204B block. For the AD6684, a transition from test modes (Register 0x0573 0x00) to normal mode (Register 0x0573 = 0x00) requires an SPI soft reset. This is done by writing 0x81 to Register 0x0000 (self cleared). Transport Layer Sample Test Mode The transport layer samples are implemented in the AD6684 as defined by Section 5.1.6.3 in the JEDEC JESD204B specification. These tests indicated by the value of Register 0x0571, Bit 5. The test pattern is equivalent to the raw samples from the ADC. Interface Test Modes The interface test modes are described in Register 0x0573, Bits[3:0]. These test modes are also explained in Table 40. The interface tests can be injected at various points along the data. See Figure 89 for more information on the test injection points. Register 0x0573, Bits[5:4] show where these tests are injected. Table 41, Table 42, and Table 43 show examples of some of the test modes when injected at the JESD204B sample input, PHY 10-bit input, and scrambler 8-bit input. In Table 41, Table 42, and Table 43, UPx represent the user pattern control bits from the customer register map. Table 40. JESD204B Interface Test Modes Output Test Mode Bit Sequence 0000 0001 0010 0011 0100 0101 0110 0111 1000 1110 1111 Pattern Name Off (default) Alternating checkerboard 1/0 word toggle 31-bit PN sequence 23-bit PN sequence 15-bit PN sequence 9-bit PN sequence 7-bit PN sequence Ramp output Continuous/repeat user test Single user test Expression Not applicable 0x5555, 0xAAAA, 0x5555, ... 0x0000, 0xFFFF, 0x0000, ... x31 + x28 + 1 x23 + x18 + 1 x15 + x14 + 1 x9 + x 5 + 1 x7 + x6 + 1 (x) % 216 Register 0x0551 to Register 0x0558 Register 0x0551 to Register 0x0558 Default Not applicable Not applicable Not applicable 0x0003AFFF 0x003AFF 0x03AF 0x092 0x07 Ramp size depends on test injection point User Pattern 1 to User Pattern 4, then repeat User Pattern 1 to User Pattern 4, then zeros Table 41. JESD204B Sample Input for M = 2, S = 2, N' = 16 (Register 0x0573, Bits[5:4] = 'b00) Frame Number 0 0 0 0 1 1 1 1 2 2 2 2 3 3 3 3 4 4 4 4 Converter Number 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Sample Number 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Alternating Checkerboard 0x5555 0x5555 0x5555 0x5555 0xAAAA 0xAAAA 0xAAAA 0xAAAA 0x5555 0x5555 0x5555 0x5555 0xAAAA 0xAAAA 0xAAAA 0xAAAA 0x5555 0x5555 0x5555 0x5555 1/0 Word Toggle 0x0000 0x0000 0x0000 0x0000 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0x0000 0x0000 0x0000 0x0000 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0x0000 0x0000 0x0000 0x0000 Ramp (x) % 216 (x) % 216 (x) % 216 (x) % 216 (x +1) % 216 (x +1) % 216 (x +1) % 216 (x +1) % 216 (x +2) % 216 (x +2) % 216 (x +2) % 216 (x +2) % 216 (x +3) % 216 (x +3) % 216 (x +3) % 216 (x +3) % 216 (x +4) % 216 (x +4) % 216 (x +4) % 216 (x +4) % 216 Rev. A | Page 70 of 99 9-Bit PN 0x496F 0x496F 0x496F 0x496F 0xC9A9 0xC9A9 0xC9A9 0xC9A9 0x980C 0x980C 0x980C 0x980C 0x651A 0x651A 0x651A 0x651A 0x5FD1 0x5FD1 0x5FD1 0x5FD1 23-Bit PN 0xFF5C 0xFF5C 0xFF5C 0xFF5C 0x0029 0x0029 0x0029 0x0029 0xB80A 0xB80A 0xB80A 0xB80A 0x3D72 0x3D72 0x3D72 0x3D72 0x9B26 0x9B26 0x9B26 0x9B26 User Repeat UP1[15:0] UP1[15:0] UP1[15:0] UP1[15:0] UP2[15:0] UP2[15:0] UP2[15:0] UP2[15:0] UP3[15:0] UP3[15:0] UP3[15:0] UP3[15:0] UP4[15:0] UP4[15:0] UP4[15:0] UP4[15:0] UP1[15:0] UP1[15:0] UP1[15:0] UP1[15:0] User Single UP1[15:0] UP1[15:0] UP1[15:0] UP1[15:0] UP2[15:0] UP2[15:0] UP2[15:0] UP2[15:0] UP3[15:0] UP3[15:0] UP3[15:0] UP3[15:0] UP4[15:0] UP4[15:0] UP4[15:0] UP4[15:0] 0x0000 0x0000 0x0000 0x0000 Data Sheet AD6684 Table 42. Physical Layer 10-Bit Input (Register 0x0573, Bits[5:4] = 'b01) 10-Bit Symbol Number 0 1 2 3 4 5 6 7 8 9 10 11 Alternating Checkerboard 0x155 0x2AA 0x155 0x2AA 0x155 0x2AA 0x155 0x2AA 0x155 0x2AA 0x155 0x2AA 1/0 Word Toggle 0x000 0x3FF 0x000 0x3FF 0x000 0x3FF 0x000 0x3FF 0x000 0x3FF 0x000 0x3FF Ramp (x) % 210 (x + 1) % 210 (x + 2) % 210 (x + 3) % 210 (x + 4) % 210 (x + 5) % 210 (x + 6) % 210 (x + 7) % 210 (x + 8) % 210 (x + 9) % 210 (x + 10) % 210 (x + 11) % 210 9-Bit PN 0x125 0x2FC 0x26A 0x198 0x031 0x251 0x297 0x3D1 0x18E 0x2CB 0x0F1 0x3DD 23-Bit PN 0x3FD 0x1C0 0x00A 0x1B8 0x028 0x3D7 0x0A6 0x326 0x10F 0x3FD 0x31E 0x008 User Repeat UP1[15:6] UP2[15:6] UP3[15:6] UP4[15:6] UP1[15:6] UP2[15:6] UP3[15:6] UP4[15:6] UP1[15:6] UP2[15:6] UP3[15:6] UP4[15:6] User Single UP1[15:6] UP2[15:6] UP3[15:6] UP4[15:6] 0x000 0x000 0x000 0x000 0x000 0x000 0x000 0x000 Table 43. Scrambler 8-Bit Input (Register 0x0573, Bits[5:4] = 'b10) 8-Bit Octet Number 0 1 2 3 4 5 6 7 8 9 10 11 Alternating Checkerboard 0x55 0xAA 0x55 0xAA 0x55 0xAA 0x55 0xAA 0x55 0xAA 0x55 0xAA 1/0 Word Toggle 0x00 0xFF 0x00 0xFF 0x00 0xFF 0x00 0xFF 0x00 0xFF 0x00 0xFF 9-Bit PN 0x49 0x6F 0xC9 0xA9 0x98 0x0C 0x65 0x1A 0x5F 0xD1 0x63 0xAC Ramp (x) % 28 (x + 1) % 28 (x + 2) % 28 (x + 3) % 28 (x + 4) % 28 (x + 5) % 28 (x + 6) % 28 (x + 7) % 28 (x + 8) % 28 (x + 9) % 28 (x + 10) % 28 (x + 11) % 28 Data Link Layer Test Modes The data link layer test modes are implemented in the AD6684 as defined by Section 5.3.3.8.2 in the JEDEC JESD204B specification. These tests are shown in Register 0x0574, Bits[2:0]. Test 23-Bit PN 0xFF 0x5C 0x00 0x29 0xB8 0x0A 0x3D 0x72 0x9B 0x26 0x43 0xFF User Repeat UP1[15:9] UP2[15:9] UP3[15:9] UP4[15:9] UP1[15:9] UP2[15:9] UP3[15:9] UP4[15:9] UP1[15:9] UP2[15:9] UP3[15:9] UP4[15:9] User Single UP1[15:9] UP2[15:9] UP3[15:9] UP4[15:9] 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 patterns inserted at this point are useful for verifying the functionality of the data link layer. When the data link layer test modes are enabled, disable SYNCINBAB/SYNCINBCD by writing 0xC0 to Register 0x0572. Rev. A | Page 71 of 99 AD6684 Data Sheet SERIAL PORT INTERFACE The AD6684 SPI allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. The SPI gives the user added flexibility and customization, depending on the application. Addresses are accessed via the serial port and can be written to or read from the port. Memory is organized into bytes that can be further divided into fields. These fields are documented in the Memory Map section. For detailed operational information, see the Serial Control Interface Standard (Rev. 1.0). command is issued. This bit allows the SDIO pin to change direction from an input to an output. CONFIGURATION USING THE SPI Data can be sent in MSB first mode or in LSB first mode. MSB first mode is the default on power-up and can be changed via the SPI port configuration register. For more information about this and other features, see the Serial Control Interface Standard (Rev. 1.0). Three pins define the SPI of this ADC: the SCLK pin, the SDIO pin, and the CSB pin (see Table 44). The SCLK (serial clock) pin is used to synchronize the read and write data presented from and to the ADC. The SDIO (serial data input/output) pin is a dual-purpose pin that allows data to be sent and read from the internal ADC memory map registers. The CSB (chip select bar) pin is an active low control that enables or disables the read and write cycles. Table 44. Serial Port Interface Pins Pin SCLK SDIO CSB Function Serial clock. The serial shift clock input, which is used to synchronize serial interface reads and writes. Serial data input/output. A dual-purpose pin that typically serves as an input or an output, depending on the instruction being sent and the relative position in the timing frame. Chip select bar. An active low control that gates the read and write cycles. The falling edge of CSB, in conjunction with the rising edge of SCLK, determines the start of the framing. An example of the serial timing and its definitions can be found in Figure 4 and Table 5. Other modes involving the CSB pin are available. The CSB pin can be held low indefinitely, which permanently enables the device; this is called streaming. The CSB can stall high between bytes to allow for additional external timing. When CSB is tied high, SPI functions are placed in a high impedance mode. This mode turns on the secondary functions of the SPI pin. All data is composed of 8-bit words. The first bit of each individual byte of serial data indicates whether a read or write In addition to word length, the instruction phase determines whether the serial frame is a read or write operation, allowing the serial port to be used both to program the chip and to read the contents of the on-chip memory. If the instruction is a readback operation, performing a readback causes the SDIO pin to change direction from an input to an output at the appropriate point in the serial frame. HARDWARE INTERFACE The pins described in Table 44 comprise the physical interface between the user programming device and the serial port of the AD6684. The SCLK pin and the CSB pin function as inputs when using the SPI interface. The SDIO pin is bidirectional, functioning as an input during write phases and as an output during readback. The SPI interface is flexible enough to be controlled by either FPGAs or microcontrollers. One method for SPI configuration is described in detail in the AN-812 Application Note, Microcontroller-Based Serial Port Interface (SPI) Boot Circuit. Do not activate the SPI port during periods when the full dynamic performance of the converter is required. Because the SCLK signal, the CSB signal, and the SDIO signal are typically asynchronous to the ADC clock, noise from these signals can degrade converter performance. If the on-board SPI bus is used for other devices, it may be necessary to provide buffers between this bus and the AD6684 to prevent these signals from transitioning at the converter inputs during critical sampling periods. SPI ACCESSIBLE FEATURES Table 45 provides a brief description of the general features that are accessible via the SPI. These features are described in detail in the Serial Control Interface Standard (Rev. 1.0). The AD6684 device specific features are described in the Memory Map section. Table 45. Features Accessible Using the SPI Feature Name Mode Clock DDC Test Input/Output Output Mode SERDES Output Setup Description Allows the user to set either power-down mode or standby mode. Allows the user to access the clock divider via the SPI. Allows the user to set up decimation filters for different applications. Allows the user to set test modes to have known data on output bits. Allows the user to set up outputs. Allows the user to vary SERDES settings such as swing and emphasis. Rev. A | Page 72 of 99 Data Sheet AD6684 MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Each row in the memory map register table has eight bit locations. The memory map is divided into four sections: the Analog Devices SPI registers (Register 0x0000 to Register 0x000D and Register 0x18A6 to Register 0x1A4D), the ADC function registers (Register 0x003F to Register 0x027A), the DDC, NSR, and VDR function registers (Register 0x0300 to Register 0x0434), and the digital outputs and test modes registers (Register 0x0550 to Register 0x05C6). Open and Reserved Locations All address and bit locations that are not included in Table 46 are not currently supported for this device. Write unused bits of a valid address location with 0s unless the default value is set otherwise. Writing to these locations is required only when part of an address location is unassigned (for example, Address 0x0561). If the entire address location is open (for example, Address 0x0013), do not write to this address location. Default Values After the AD6684 is reset, critical registers are loaded with default values. The default values for the registers are given in the memory map register table, Table 46. Logic Levels An explanation of logic level terminology follows: * * * "Bit is set" is synonymous with "bit is set to Logic 1" or "writing Logic 1 for the bit." "Clear a bit" is synonymous with "bit is set to Logic 0" or "writing Logic 0 for the bit." X denotes a don't care bit. ADC Pair Addressing The AD6684 functionally operates as two pairs of dual IF receiver channels. There are two ADCs, two NSR processing blocks, two VDR processing blocks, and two DDCs in each pair, resulting in a total of four of each for the AD6684. To access the SPI registers for each pair, the pair index must be written in Register 0x0009. The pair index register must be written prior to any other SPI write to the AD6684. Channel-Specific Registers Some channel setup functions, such as the fast detect control (Register 0x0247), can be programmed to a different value for each channel. In these cases, channel address locations are internally duplicated for each channel. These registers and bits are designated in Table 46 as local. These local registers and bits can be accessed by setting the appropriate Channel A/Channel C or Channel B/Channel D bits in Register 0x0008. The particular channel that is addressed is dependent upon the pair selection written to Register 0x0009. If both bits are set, the subsequent write affects the registers of both channels. In a read cycle, set only Channel A/Channel C or Channel B/Channel D to read one of the two registers. If both bits are set during an SPI read cycle, the device returns the value for Channel A. If both pairs and both channels have been selected via Register 0x0009 and Register 0x0008, then the device returns the value for Channel A. The names of the registers listed in Table 46 are prefixed with either global map, channel map, JESD204B map, or pair map. Registers in the pair map and JESD204B map apply to a pair of channels, either Pair A/B or Pair C/D. To write registers in the pair map and the JESD204B map, the pair index register (Register 0x0009) must be written to address the appropriate pair. The SPI Configuration A (Register 0x0000), SPI Configuration B (Register 0x0001), and pair index (Register 0x0009) registers are the only registers that reside in the global map. Registers in the channel map are local to each channel, either Channel A, Channel B, Channel C, or Channel D. To write registers in the channel map, the pair index register (Register 0x0009) must be written first to address the desired pair (Pair A/B or Pair C/D), followed by writing the channel index register (Register 0x0008) to select the desired channel (Channel A/Channel C or Channel B/ Channel D). For example, to write Channel A to a test mode (set by Register 0x0550), first write a value of 0x01 to Register 0x0009 to select Pair A/B, followed by writing 0x01 to Register 0x0008 to select Channel A. Then, write Register 0x0550 to the value for the desired test mode. To write all channels to a test mode (set by Register 0x0550), first write Register 0x0009 to a value of 0x03 to select both Pair A/B and Pair C/D, followed by writing Register 0x0008 to a value of 0x03 to select Channel A, Channel B, Channel C, and Channel D. Next, write Register 0x0550 to the value for the desired test mode. SPI Soft Reset After issuing a soft reset by programming 0x81 to Register 0x0000, the AD6684 requires 5 ms to recover. When programming the AD6684 for application setup, ensure that an adequate delay is programmed into the firmware after asserting the soft reset and before starting the device setup. Rev. A | Page 73 of 99 AD6684 Data Sheet MEMORY MAP MEMORY MAP DETAILS All address locations that are not included in Table 46 are not currently supported for this device and must not be written. Table 46. Memory Map Details Address 0x0000 Name Global Map SPI Configuration A Bits 7 6 5 Bit Name Soft reset (self clearing) Settings 0 1 Description When a soft reset is issued, the user must wait 5 ms before writing to any other register. This wait provides sufficient time for the boot loader to complete. Do nothing. Reset the SPI and registers (self clearing). 1 0 LSB shifted first for all SPI operations. MSB shifted first for all SPI operations. 0 Multibyte SPI operations cause addresses to auto-increment. Multibyte SPI operations cause addresses to auto-increment. Reserved. LSB first mirror Address ascension mirror 1 [4:3] 2 Reserved Address ascension 0 1 1 0 Soft reset (self clearing) 0 1 0x0001 Global Map SPI Configuration B 7 [6:2] 1 Reserved Datapath soft reset (self clearing) 0 1 0 LSB shifted first for all SPI operations. MSB shifted first for all SPI operations. When a soft reset is issued, the user must wait 5 ms before writing to any other register. This wait provides sufficient time for the boot loader to complete. Do nothing. Reset the SPI and registers (self clearing). Single instruction 0 1 Reserved Access R/W 0x0 R/W 0x0 R/W 0x0 0x0 R R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 0x0 R R/W 0x0 R Multibyte SPI operations cause addresses to autoincrement. Multibyte SPI operations cause addresses to auto increment. LSB first 1 0 Reset 0x0 SPI streaming enabled. Streaming (multibyte read/write) is disabled. Only one read or write operation is performed, regardless of the state of the CSB line. Reserved. Normal operation. Datapath soft reset (self-clearing). Reserved. Rev. A | Page 74 of 99 Data Sheet Address 0x0002 Name Channel map chip configuration AD6684 Bits [7:2] [1:0] Bit Name Reserved Channel power modes Settings 00 10 11 0x0003 0x0004 0x0006 0x0008 Pair map chip type [7:0] Pair map chip ID LSB Pair map chip grade [7:0] CHIP_ID [7:4] CHIP_SPEED_GRADE [3:0] [7:2] 1 Reserved Reserved Channel B/Channel D Pair map device index CHIP_TYPE 0x3 0101 0 1 0 1 Global map pair index [7:2] 1 Reserved Pair C/D 0 1 0 Reset 0x0 0x0 Access R R/W 0x3 R 0xDC R Chip speed grade. 500 MHz. Reserved. Reserved. 0x0 R 0x0 0x0 0x1 R R R/W 0x1 R/W 0x0 0x1 R R/W 0x1 R/W 0x07 R/W 0x1 R 0x56 R 0x4 R ADC Core B/ADC Core D does not receive the next SPI command. ADC Core B/ADC Core D receives the next SPI command. Channel A/Channel C 0 0x0009 Description Reserved. Channel power modes. Normal mode (power up). Standby mode. The digital datapath clocks are disabled, the JESD204B interface is enabled, and the outputs are enabled. Power-down mode. The digital datapath clocks are disabled, the digital datapath is held in reset, the JESD204B interface is disabled, and the outputs are disabled. Chip type. High speed ADC. Chip ID. ADC Core A/ADC Core C does not receive the next SPI command. ADC Core A/ADC Core C receives the next SPI command. Reserved. ADC Pair C/D does not receive the next read/ write command from the SPI interface. ADC Pair C/D does not receive the next read/ write command from the SPI interface. Pair A/B 0 0x000A Pair map scratch pad [7:0] Scratch pad 0x000B Pair map SPI revision [7:0] SPI_REVISION Pair map vendor ID LSB Pair map vendor ID MSB [7:0] CHIP_VENDOR_ID[7:0] ADC Pair A/B does not receive the next read/ write command from the SPI interface. ADC Pair A/B receives the next read/write command from the SPI interface. Chip scratch pad register. This register provides a consistent memory location for software debug. SPI revision register (0x01 = Revision 1.0). Revision 1.0. Vendor ID. [7:0] CHIP_VENDOR_ID[15:8] Vendor ID. 1 0x000C 0x000D 00000001 Rev. A | Page 75 of 99 AD6684 Address 0x003F Name Channel map chip powerdown pin Data Sheet Bits 7 Bit Name PDWN/STBY disable Settings 0 1 0x0040 Pair Map Chip Pin Control 1 [6:0] [7:6] Reserved PDWN/STBY function 00 01 10 [5:3] 111 111 0x0108 Pair map clock divider control [7:3] [2:0] Reserved Clock divider 000 001 011 111 0x0109 Channel map clock divider phase [7:4] [3:0] Reserved Clock divider phase offset 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 Access R/W 0x0 0x0 R R/W 0x7 R/W 0x7 R/W 0x0 0x1 R R/W 0x0 0x0 R R/W Fast Detect B/Fast Detect D output. JESD204B LMFC output. JESD204B internal SYNC signal in the ADC output. Disabled (configured as an input with a weak pull down). Fast Detect A/Fast Detect C (FD_A/FD_C) 000 001 010 Reset 0x0 Power-down pin--assertion of the external power-down pin (PDWN/STBY) causes the chip to enter full power-down mode. Standby pin--assertion of the external power-down pin (PDWN/STBY) causes the chip to enter standby mode. Pin disabled--assertion of the external power-down pin (PDWN/STBY) is ignored. Fast Detect B/Fast Detect D (FD_B/FD_D) 000 001 010 [2:0] Description This bit is used in conjunction with Register 0x0040. Power-down pin (PDWN/STBY) enabled; global pin control selection enabled (default). Power-down pin (PDWN/STBY) disabled/ ignored; global pin control selection ignored. Reserved. Fast Detect A/Fast Detect C output. JESD204B LMFC output. JESD204B internal SYNC signal in the ADC output. Disabled (configured as an input with a weak pull down). Reserved. Divide by 1. Divide by 2. Divide by 4. Divide by 8. Reserved. 0 input clock cycles delayed. 1/2 input clock cycles delayed (invert clock). 1 input clock cycles delayed. 1 1/2 input clock cycles delayed. 2 input clock cycles delayed. 2 1/2 input clock cycles delayed. 3 input clock cycles delayed. 3 1/2 input clock cycles delayed. 4 input clock cycles delayed. 4 1/2 input clock cycles delayed. 5 input clock cycles delayed. 5 1/2 input clock cycles delayed. Rev. A | Page 76 of 99 Data Sheet AD6684 Address Name Bits Bit Name 0x010A Pair map clock divider SYSREF control 7 Clock divider auto phase adjust Settings 1100 1101 1110 1111 0 1 [6:4] [3:2] Reserved Clock divider negative skew window 00 01 10 11 [1:0] 01 10 11 Pair map clock delay control [7:3] [2:0] Reserved Clock delay mode select 000 001 010 011 100 101 110 0x0111 Channel map clock super fine delay [7:0] Clock divider phase is not changed by SYSREF (disabled). Clock divider phase is automatically adjusted by SYSREF (enabled). Reserved. Clock super fine delay adjust 0x00 0x08 0x80 Reset Access 0x0 R/W 0x0 0x0 R R/W 0x0 R/W 0x0 0x0 R R/W 0x0 R/W No negative skew; SYSREF must be captured accurately. 1/2 device clock of negative skew. 1 device clocks of negative skew. 1 1/2 device clocks of negative skew. Clock divider positive skew window 00 0x0110 Description 6 input clock cycles delayed. 6 1/2 input clock cycles delayed. 7 input clock cycles delayed. 7 1/2 input clock cycles delayed. No positive skew; SYSREF must be captured accurately. 1/2 device clock of positive skew. 1 device clocks of positive skew. 1 1/2 device clocks of positive skew. Reserved. Clock delay mode select; used in conjunction with Register 0x0111 and Register 0x0112. No clock delay. Reserved. Fine delay; only Delay Step 0 to Delay Step 16 are valid. Fine delay (lowest jitter); only Delay Step 0 to Delay Step 16 are valid. Fine delay; all 192 delay steps are valid. Reserved (same as 001). Fine delay enabled; all 192 delay steps are valid. Super fine delay enabled (all 128 delay steps are valid). This is an unsigned control to adjust the super fine sample clock delay in 0.25 ps steps. 0 delay steps. ... 8 delay steps. ... 128 delay steps. These bits are only used when Register 0x0110, Bits[2:0] = 0x2 or 0x6. Rev. A | Page 77 of 99 AD6684 Address 0x0112 Name Channel map clock fine delay Data Sheet Bits [7:0] Bit Name Clock fine delay adjust Settings 0x00 0x08 0xC0 0x011A Clock detection control [7:5] [4:3] Reserved Clock detection threshold 01 11 2 Clock detection enable 1 0 0x011B Pair map clock status [1:0] [7:1] 0 Reserved. Reserved Input clock detect 0 1 0x011C Clock DCS control [7:3] 1 Reserved Clock DCS enable 0 1 0 Clock DCS power-up 0 1 0x0120 Pair map SYSREF Control 1 7 6 Reserved SYSREF flag reset 5 4 Reserved SYSREF transition select 0 1 0 1 3 CLK edge select [2:1] SYSREF mode select 0 Reserved 0 1 00 01 10 Description Clock fine delay adjust. This is an unsigned control to adjust the fine sample clock skew in 1.725 ps steps. 0 delay steps. ... 8 delay steps. ... 192 delay steps. These bits are only used when Register 0x0110, Bits[2:0] = 0x2, 0x3, 0x4, or 0x6. Reserved. Clock detection threshold. 200 MHz. 150 MHz. Clock detection enable Enable. Disable. Reserved. Reserved. Clock detection status. Input clock not detected. Input clock detected/locked. Reserved. Clock DCS enable. DCS bypassed. DCS enabled. Clock DCS power-up. DCS powered down. DCS powered up. The DCS must be powered up before being enabled. Reserved. Normal flag operation. SYSREF flags held in reset (setup/hold error flags cleared). Reserved. SYSREF is valid on low to high transitions using the selected CLK input edge. When changing this setting, the SYSREF mode select must be set to disabled. SYSREF is valid on high to low transitions using the selected CLK input edge. When changing this setting, the SYSREF mode select must be set to disabled. Captured on rising edge of CLK input. Captured on falling edge of CLK input. Disabled. Continuous. N shot. Reserved. Rev. A | Page 78 of 99 Reset 0xC0 Access R/W 0x0 0x1 R/W R/W 0x1 R/W 0x2 0x0 0x0 R/W R R 0x1 0x0 R/W R/W 0x0 R/W 0x0 0x0 R R/W 0x0 0x0 R R/W 0x0 R/W 0x0 R/W 0x0 R Data Sheet Address 0x0121 Name Pair map SYSREF Control 2 AD6684 Bits [7:4] [3:0] Bit Name Reserved SYSREF N shot ignore counter select Settings 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0x0123 Pair map SYSREF Control 4 7 [6:0] Reserved SYSREF time stamp delay[6:0] 0 1 127 0x0128 0x0129 Pair map SYSREF Status 1 Pair map SYSREF Status 2 [7:4] SYSREF hold status[7:4] [3:0] SYSREF setup status[3:0] [7:4] [3:0] Reserved Clock divider phase when SYSREF is captured 0000 0001 0010 0011 0100 0101 1111 0x012A Pair map SYSREF Status 3 [7:0] SYSREF counter [7:0] (increments when a SYSREF is captured) Description Reserved. Next SYSREF only (do not ignore). Ignore the first SYSREF transition. Ignore the first two SYSREF transitions. Ignore the first three SYSREF transitions. Ignore the first four SYSREF transitions. Ignore the first five SYSREF transitions. Ignore the first six SYSREF transitions. Ignore the first seven SYSREF transitions. Ignore the first eight SYSREF transitions. Ignore the first nine SYSREF transitions. Ignore the first 10 SYSREF transitions. Ignore the first 11 SYSREF transitions. Ignore the first 12 SYSREF transitions. Ignore the first 13 SYSREF transitions. Ignore the first 14 SYSREF transitions. Ignore the first 15 SYSREF transitions. Reserved. SYSREF timestamp delay (in converter sample clock cycles) 0 sample clock cycle delay 1 sample clock cycle delay ... 127 sample clock cycle delay SYSREF hold status. See Table 38 for more information. SYSREF setup status. See Table 38 for more information. Reserved. SYSREF divider phase. These bits represent the phase of the divider when SYSREF is captured. In phase. SYSREF is 1/2 cycle delayed from clock. SYSREF is 1 cycle delayed from clock. 11/2 input clock cycles delayed. 2 input clock cycles delayed. 21/2 input clock cycles delayed. ... 71/2 input clock cycles delayed. SYSREF count. These bits are a running counter that increments whenever a SYSREF event is captured. These bits are reset by Register 0x0120, Bit 6, and wrap around at 255. Read these bits only while Register 0x120, Bits[2:1] are disabled. Rev. A | Page 79 of 99 Reset 0x0 0x0 Access R R/W 0x0 0x40 R R/W 0x0 R 0x0 R 0x0 0x0 R R 0x0 R AD6684 Address 0x01FF Name Pair map chip sync Data Sheet Bits [7:1] 0 Bit Name Reserved Synchronization mode Settings Description Reserved. 0x0 Sample synchronization mode. The SYSREF signal resets all internal sample dividers. Use this mode when synchronizing multiple chips as specified in the JESD204B standard. If the phase of any of the dividers must change, the JESD204B link is interrupted. Partial synchronization/timestamp mode. The SYSREF signal does not reset sample internal dividers. In this mode, the JESD204B link, the signal monitor, and the parallel interface clocks are not affected by the SYSREF signal. The SYSREF signal simply time stamps a sample as it passes through the ADC. Reserved. Chip real (I) only selection. Both real (I) and complex (Q) selected. Only real (I) selected. Complex (Q) is ignored. Reserved. 0x1 0x0200 Pair map chip mode [7:6] 5 Reserved Chip Q ignore 0 1 4 [3:0] Reserved Chip application mode 0000 0001 0010 0111 1000 0x0201 Pair map chip decimation ratio [7:3] [2:0] Reserved Chip decimation ratio select 0x0228 Channel map custom offset [7:0] Offset adjust in LSBs from +127 to -128 0x0245 Channel map fast detect control [7:4] 3 Reserved Force FD_A/FD_B/FD_C/ FD_D pins 000 001 010 011 100 0 1 2 1 0 Force value of FD_A/FD_B/ FD_C/FD_D pins; if force pins is true, this value is output on the fast detect pins Reserved Enable fast detect output Full bandwidth mode. One DDC mode (DDC 0 only). Two DDC mode (DDC 0 and DDC 1 only). Noise shaped requantizer (NSR) mode. Variable dynamic range (VDR) mode. Reserved. Chip decimation ratio. Decimate by 1 (full sample rate). Decimate by 2. Decimate by 4. Decimate by 8. Decimate by 16. Digital datapath offset. Twos complement offset adjustment aligned with least significant converter resolution bit. Reserved. Normal operation of the fast detect pin. Force a value on the fast detect pin (see Bit 2 of this register). The fast detect output pin for this channel is set to this value when the output is forced. Reserved. 0 1 Fine fast detect disabled. Fine fast detect enabled. Rev. A | Page 80 of 99 Reset 0x0 0x0 Access R R/W 0x0 0x0 R/W R/W 0x0 0x7 R R/W 0x0 0x0 R R/W 0x0 R/W 0x0 0x0 R R/W 0x0 R/W 0x0 0x0 R R/W Data Sheet Address 0x0247 0x0248 0x0249 0x024A AD6684 Name Channel map fast detect upper threshold LSB Channel map fast detect upper threshold MSB Bits [7:0] Bit Name Fast detect upper threshold [7:0] [7:5] [4:0] Reserved Fast detect upper threshold[12:8] Channel map fast detect lower threshold LSB Channel map fast detect lower threshold MSB [7:0] Fast detect lower threshold[7:0] [7:5] [4:0] Reserved Fast detect lower threshold[12:8] Settings 0x024B Channel map fast detect dwell time LSB [7:0] Fast detect dwell time[7:0] 0x024C Channel map fast detect dwell time MSB [7:0] Fast detect dwell time[15:8] 0x026F Pair map signal monitor sync control [7:2] 1 0 Reserved Reserved Signal monitor synchronization mode 0 1 0x0270 0x0271 0x0272 0x0273 Channel map signal monitor control Channel map Signal Monitor Period 0 Channel map Signal Monitor Period 1 Channel map Signal Monitor Period 2 [7:2] 1 Reserved Peak detector 0 1 0 [7:0] Reserved Signal monitor period[7:0] [7:0] Signal monitor period[15:8] [7:0] Signal monitor period[23:16] Description LSBs of fast detect upper threshold. Eight LSBS of the programmable 13-bit upper threshold that is compared to the fine ADC magnitude. Reserved. LSBs of fast detect upper threshold. Eight LSBS of the programmable 13-bit upper threshold that is compared to the fine ADC magnitude. LSBs of fast detect lower threshold. Eight LSBS of the programmable 13-bit lower threshold that is compared to the fine ADC magnitude Reserved. LSBs of fast detect lower threshold. Eight LSBS of the programmable 13-bit lower threshold that is compared to the fine ADC magnitude LSBs of fast detect dwell time counter target. This target is a load value for a 16-bit counter that determines how long the ADC data must remain below the lower threshold before the FD_x pins are reset to 0 LSBs of fast detect dwell time counter target. This target is a load value for a 16-bit counter that determines how long the ADC data must remain below the lower threshold before the FDD_x pins are reset to 0. Reserved. Reserved. Synchronization disabled. Only the next valid edge of the SYSREF pin is used to synchronize the signal monitor block. Subsequent edges of the SYSREF pin are ignored. After the next SYSREF is received, this bit is cleared. Note that the SYSREF input pin must be enabled to synchronize the signal monitor blocks. Reserved. Peak detector disabled. Peak detector enabled. Reserved. This 24-bit value sets the number of output clock cycles over which the signal monitor performs its operation. Bit 0 is ignored. This 24-bit value sets the number of output clock cycles over which the signal monitor performs its operation. Bit 0 is ignored. This 24-bit value sets the number of output clock cycles over which the signal monitor performs its operation. Bit 0 is ignored. Rev. A | Page 81 of 99 Reset 0x0 Access R/W 0x0 0x0 R R/W 0x0 R/W 0x0 0x0 R R/W 0x0 R/W 0x0 R/W 0x0 0x0 0x0 R R/W R/W 0x0 0x0 R R/W 0x0 0x80 R R/W 0x0 R/W 0x0 R/W AD6684 Address 0x0274 Name Channel map signal monitor status control Data Sheet Bits [7:5] 4 3 [2:0] Bit Name Reserved Result update Settings Description Reserved. 1 Status update based on Bits[2:0] (self clearing). Reserved. Reserved Result selection 001 0x0275 Channel map Signal Monitor Status 0 [7:0] Signal monitor result[7:0] 0x0276 Channel map Signal Monitor Status 1 [7:0] Signal monitor result[15:8] 0x0277 Channel map Signal Monitor Status 2 [7:4] [3:0] Reserved Signal monitor result[19:16] 0x0278 Channel map signal monitor status frame counter Channel map signal monitor serial framer control [7:0] Period count result[7:0] [7:2] 1 0 Reserved Reserved Signal monitor SPORT over JESD204B enable 0x0279 Reserved. Reserved. 0 1 0x027A Channel map signal monitor serial framer input selection [7:6] [5:0] Peak detector placed on status readback signals. Signal monitor status result. This 20-bit value contains the status result calculated by the signal monitor block. The content is dependent on the Register 0x0274, Bits[2:0] bit settings. Signal monitor status result. This 20-bit value contains the status result calculated by the signal monitor block. The content is dependent on the Register 0x0274, Bits[2:0] bit settings. Reserved. Signal monitor status result. This 20-bit value contains the status result calculated by the signal monitor block. The content is dependent on the Register 0x0274, Bits[2:0] bit settings. Signal monitor frame counter status bits. The frame counter increments whenever the period counter expires. Reserved Signal monitor SPORT over JESD204B peak detector enable 1 Disabled. Enabled. Reserved. Peak detector enabled. Rev. A | Page 82 of 99 Reset 0x0 0x0 Access R R/W 0x0 0x1 R R/W 0x0 R 0x0 R 0x0 0x0 R R 0x0 R 0x0 0x0 0x0 R R/W R/W 0x0 0x2 R R/W Data Sheet Address 0x0300 Name Pair map DDC sync control AD6684 Bits [7:6] 5 4 Bit Name Reserved Reserved DDC NCO soft reset Settings 0 1 [3:2] 1 Reserved DDC next sync 0 1 0 DDC synchronization mode 0 1 0x0310 Pair map DDC 0 control 7 DDC 0 mixer select 0 0 1 Real mixer (I and Q inputs must be from the same real channel). Complex mixer (I and Q must be from separate real and imaginary quadrature ADC receive channels--analog demodulator). Gain can be used to compensate for the 6 dB loss associated with mixing an input signal down to baseband and filtering out its negative component. 0 dB gain. 6 dB gain (multiply by 2). 00 01 10 11 Variable IF mode. 0 Hz IF mode. fS/4 Hz IF mode. Test mode. 1 6 [5:4] 3 DDC 0 gain select DDC 0 IF mode DDC 0 complex to real enable 0 1 2 Description Reserved. Reserved. This bit can be used to synchronize all the NCOs inside the DDC blocks. Normal operation. DDC held in reset. Reserved. The SYSREF pin must be an integer multiple of the NCO frequency for this function to operate correctly in continuous mode. Continuous mode. Only the next valid edge of the SYSREF pin is used to synchronize the NCO in the DDC block. Subsequent edges of the SYSREF pin are ignored. After the next SYSREF is found, the DDC synchronization enable bit is cleared. The SYSREF input pin must be enabled to synchronize the DDCs. Synchronization disabled. If the DDC next sync bit = 1, only the next valid edge of the SYSREF pin is used to synchronize the NCO in the DDC block. Subsequent edges of the SYSREF pin are ignored. After the next SYSREF is received, this bit is cleared. Reserved Complex (I and Q) outputs contain valid data. Real (I) output only. Complex to real enabled. Uses extra fS/4 mixing to convert to real. Reserved. Rev. A | Page 83 of 99 Reset 0x0 0x0 0x0 Access R/W R R/W 0x0 0x0 R R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R AD6684 Address Name Data Sheet Bits [1:0] Bit Name DDC 0 decimation rate select Settings 11 00 01 10 11 00 01 10 11 00 01 10 0x0311 Pair map DDC 0 input select [7:3] 2 Reserved DDC 0 Q input select 0 1 1 0 Reserved DDC 0 I input select 0 1 0x0314 Pair map DDC 0 Phase Increment 0 [7:0] DDC 0 NCO frequency value, twos complement[7:0] 0x0315 Pair map DDC 0 Phase Increment 1 [7:0] DDC 0 NCO frequency value, twos complement[15:8] 0x0316 Pair map DDC 0 Phase Increment 2 [7:0] DDC 0 NCO frequency value, twos complement[23:16] 0x0317 Pair map DDC 0 Phase Increment 3 [7:0] DDC 0 NCO frequency value, twos complement[31:24] 0x0318 Pair map DDC 0 Phase Increment 4 [7:0] DDC 0 NCO frequency value, twos complement[39:32] 0x031A Pair map DDC 0 Phase Increment 5 [7:0] DDC 0 NCO frequency value, twos complement[47:40] 0x031D Pair map DDC 0 Phase Offset 0 [7:0] DDC 0 NCO phase value, twos complement[7:0] Description Decimation filter selection. Complex outputs (complex to real disabled): HB1 filter selection (decimate by 2). HB2 + HB1 filter selection (decimate by 4). HB3 + HB2 + HB1 filter selection (decimate by 8). HB4 + HB3 + HB2 + HB1 filter selection (decimate by 16). Real outputs (complex to real enabled): HB1 filter selection (decimate by 1). HB2 + HB1 filter selection (decimate by 2). HB3 + HB2 + HB1 filter selection (decimate by 4). HB4 + HB3 + HB2 + HB1 filter selection (decimate by 8). HB1 filter selection: decimate by 1 or 2. HB2 + HB1 filter selection (decimate by 2 or 4). HB3 + HB2 + HB1 filter selection (decimate by 4 or 8) HB4 + HB3 + HB2 + HB1 filter selection (decimate by 8 or 16) Reserved. Channel A. Channel B. Reserved. Channel A. Channel B. NCO phase increment value; twos complement phase increment value for the NCO. Complex mixing frequency = (DDC phase increment x fS)/248. NCO phase increment value; twos complement phase increment value for the NCO. Complex mixing frequency = (DDC_PHASE_INC x fS)/248. NCO phase increment value; twos complement phase increment value for the NCO. Complex mixing frequency = (DDC_PHASE_INC x fS)/248. NCO phase increment value; twos complement phase increment value for the NCO. Complex mixing frequency = (DDC_PHASE_INC x fS)/248. NCO phase increment value; twos complement phase increment value for the NCO. Complex mixing frequency = (DDC_PHASE_INC x fS)/248. NCO phase increment value; twos complement phase increment value for the NCO. Complex mixing frequency = (DDC_PHASE_INC x fS)/248. Twos complement phase offset value for the NCO. Rev. A | Page 84 of 99 Reset 0x0 Access R/W 0x0 0x0 R R/W 0x0 0x0 R R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W Data Sheet Address 0x031E 0x031F 0x0320 0x0321 0x0322 0x0327 Name Pair map DDC 0 Phase Offset 1 Pair map DDC 0 Phase Offset 2 Pair map DDC 0 Phase Offset 3 Pair Map DDC 0 Phase Offset 4 Pair map DDC 0 Phase Offset 5 Pair map DDC 0 test enable AD6684 Bits [7:0] Bit Name DDC 0 NCO phase value, twos complement[15:8] [7:0] Settings Description Twos complement phase offset value for the NCO. Reset 0x0 Access R/W DDC 0 NCO phase value, twos complement[23:16] Twos complement phase offset value for the NCO. 0x0 R/W [7:0] DDC 0 NCO phase value, twos complement[31:24] Twos complement phase offset value for the NCO. 0x0 R/W [7:0] DDC 0 NCO phase value, twos complement[39:32] Twos complement phase offset value for the NCO. 0x0 R/W [7:0] DDC 0 NCO phase value, twos complement[47:40] Twos complement phase offset value for the NCO. 0x0 R/W [7:3] 2 Reserved DDC 0 Q output test mode enable Reserved. Q samples always use the Test Mode B/ Test Mode D block. Test mode disabled. Test mode enabled. Reserved. I Samples always use Test Mode A/ Test Mode C block. Test mode disabled. Test mode enabled. 0x0 0x0 R R/W 0x0 0x0 R R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R 0 1 1 0 Reserved DDC 0 I output test mode enable 0 1 0x0330 Pair map DDC 1 control 7 DDC 1 mixer select 0 0 1 Real mixer (I and Q inputs must be from the same real channel). Complex mixer (I and Q must be from separate, real and imaginary quadrature ADC receive channels--analog demodulator). Gain can be used to compensate for the 6 dB loss associated with mixing an input signal down to baseband and filtering out its negative component. 0 dB gain. 6 dB gain (multiply by 2). 00 01 10 11 Variable IF mode. 0 Hz IF mode. fS/4 Hz IF mode. Test mode. 1 6 [5:4] 3 DDC 1 gain select DDC 1 IF mode DDC 1 complex to real enable 0 1 2 Reserved Complex (I and Q) outputs contain valid data. Real (I) output only. Complex to real enabled. Uses extra fS/4 mixing to convert to real. Reserved. Rev. A | Page 85 of 99 AD6684 Address Name Data Sheet Bits [1:0] Bit Name DDC 1 decimation rate select Settings 11 00 01 10 11 00 01 10 11 00 01 10 0x0331 Pair map DDC 1 input select [7:3] 2 Reserved DDC 1 Q input select 0 1 1 0 Reserved DDC 1 I input select 0 1 0x0334 Pair map DDC 1 Phase Increment 0 [7:0] DDC 1 NCO frequency value, twos complement[7:0] 0x0335 Pair map DDC 1 Phase Increment 1 [7:0] DDC 1 NCO frequency value, twos complement[15:8] 0x0336 Pair map DDC 1 Phase Increment 2 [7:0] DDC 1 NCO frequency value, twos complement[23:16] 0x0337 Pair map DDC 1 Phase Increment 3 [7:0] DDC 1 NCO frequency value, twos complement[31:24] 0x0338 Pair map DDC 1 Phase Increment 4 [7:0] DDC 1 NCO frequency value, twos complement[39:32] 0x033A Pair map DDC 1 Phase Increment 5 [7:0] DDC 1 NCO frequency value, twos complement[47:40] 0x033D Pair map DDC 1 Phase Offset 0 [7:0] DDC 1 NCO phase value, twos complement[7:0] Description Decimation filter selection. Complex outputs (complex to real disabled): HB1 filter selection (decimate by 2). HB2 + HB1 filter selection (decimate by 4). HB3 + HB2 + HB1 filter selection (decimate by 8). HB4 + HB3 + HB2 + HB1 filter selection (decimate by 16). Real outputs (complex to real enabled): HB1 filter selection (decimate by 1). HB2 + HB1 filter selection (decimate by 2). HB3 + HB2 + HB1 filter selection (decimate by 4). HB4 + HB3 + HB2 + HB1 filter selection (decimate by 8). HB1 filter selection: decimate by 1 or 2. HB2 + HB1 filter selection (decimate by 2 or 4). HB3 + HB2 + HB1 filter selection (decimate by 4 or 8) HB4 + HB3 + HB2 + HB1 filter selection (decimate by 8 or 16) Reserved. Channel A. Channel B. Reserved. Channel A. Channel B. NCO phase increment value. Twos complement phase increment value for the NCO. Complex mixing frequency = (DDC phase increment x fS)/248. NCO phase increment value. Twos complement phase increment value for the NCO. Complex mixing frequency = (DDC phase increment x fS)/248. NCO phase increment value. Twos complement phase increment value for the NCO. Complex mixing frequency = (DDC phase increment x fS)/248. NCO phase increment value. Twos complement phase increment value for the NCO. Complex mixing frequency = (DDC phase increment x fS)/248. NCO phase increment value. Twos complement phase increment value for the NCO. Complex mixing frequency = (DDC phase increment x fS)/248. NCO phase increment value. Twos complement phase increment value for the NCO. Complex mixing frequency = (DDC phase increment x fS)/248. Twos complement phase offset value for the NCO. Rev. A | Page 86 of 99 Reset 0x0 Access R/W 0x0 0x1 R R/W 0x0 0x1 R R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W Data Sheet Address 0x033E 0x033F 0x0340 0x0341 0x0342 0x0347 Name Pair map DDC 1 Phase Offset 1 Pair map DDC 1 Phase Offset 2 Pair map DDC 1 Phase Offset 3 Pair map DDC 1 Phase Offset 4 Pair map DDC 1 Phase Offset 5 Pair map DDC 1 test enable AD6684 Bits [7:0] Bit Name DDC 1 NCO phase value, twos complement[15:8] [7:0] Settings Description Twos complement phase offset value for the NCO. Reset 0x0 Access R/W DDC 1 NCO phase value, twos complement[23:16] Twos complement phase offset value for the NCO. 0x0 R/W [7:0] DDC 1 NCO phase value, twos complement[31:24] Twos complement phase offset value for the NCO. 0x0 R/W [7:0] DDC 1 NCO phase value, twos complement[39:32] Twos complement phase offset value for the NCO. 0x0 R/W [7:0] DDC 1 NCO phase value, twos complement[47:40] Twos complement phase offset value for the NCO. 0x0 R/W [7:3] 2 Reserved DDC 1 Q output test mode enable Reserved. Q samples always use the Test Mode B/ Test Mode D block. Test mode disabled. Test mode enabled. Reserved. I samples always use the Test Mode A/ Test Mode C block. Test mode disabled. Test mode enabled. Decimate by 2 high-pass/low-pass mode. Enable LPF. Enable HPF. Reserved. Reserved. Reserved. 0x0 0x0 R R/W 0x0 0x0 R R/W 0x0 R/W 0x0 0x0 0x0 0x0 R R/W R R/W 0x0 0x0 0x0 R/W R R/W 0x0 0x0 0x0 R R R/W 0 1 1 0 Reserved DDC 1 I output test mode enable 0 1 0x041E Channel map NSR decimate by 2 control 7 High-pass/low-pass mode 0 1 6 [5:4] [3:1] 0 Reserved Reserved Reserved NSR decimate by 2 enable 0 1 0x0420 NSR mode 7 [6:4] [3:1] Reserved Reserved NSR mode 000 001 0x0422 Channel map NSR tuning 0 [7:6] [5:0] Reserved Reserved NSR tuning word Decimate by 2 disabled. Decimate by 2 enabled. Reserved. Reserved. 21% BW mode. 28% BW mode. Reserved. Reserved. Noise shaped requantizer tuning frequency (see the Noise Shaping Requantizer (NSR) section for details). Rev. A | Page 87 of 99 AD6684 Address 0x0430 Name Pair map VDR control Data Sheet Bits 7 [6:5] 4 [3:2] 1 0 Bit Name Reserved Reserved Reserved Reserved VDR bandwidth Settings Description Reserved. Reserved. Reserved. Reserved. 0 1 25% BW mode. 43% BW mode. Only available in complex mode. 0 1 Dual real mode. Ignore Bit 1. Dual complex mode. Complex input, Channel A and Channel C are I and Channel B and Channel D are Q. Reserved. See the Variable Dynamic Range (VDR) section for details. VDR complex mode enable 0x0434 Channel map VDR tuning frequency [7:4] [3:0] Reserved VDR center frequency 0x0550 Channel map test mode control 7 User pattern selection 0 1 6 5 4 [3:0] Reserved Reset PN long generation 0 1 Long PN enabled. Long PN held in reset. 0 1 Short PN enabled. Short PN held in reset. Reset PN short generation Test mode selection 0000 0001 0010 0011 0100 0101 0110 0111 1000 0x0552 0x0553 0x0554 0x0555 0x0556 0x0557 0x0558 Pair map User Pattern 1 LSB Pair map User Pattern 1 MSB Pair map User Pattern 2 LSB Pair map User Pattern 2 MSB Pair map User Pattern 3 LSB Pair map User Pattern 3 MSB Pair map User Pattern 4 LSB Pair map User Pattern 4 MSB Access R/W R R/W R R/W 0x1 R/W 0x0 0x0 R R/W 0x0 R/W 0x0 0x0 R R/W 0x0 R/W 0x0 R/W 0x0 R/W [7:0] User Pattern 1[7:0] Off--normal operation. Midscale short. Positive full scale. Negative full scale. Alternating checker board. PN sequence--long. PN sequence--short. 1/0 word toggle. User pattern test mode (used with the test mode pattern selection and the User Pattern 1 through User Pattern 4 registers) Ramp output. User Test Pattern 1 least significant byte [7:0] User Pattern 1[15:8] User Test Pattern 1 most significant byte 0x0 R/W [7:0] User Pattern 2[7:0] User Test Pattern 2 least significant byte 0x0 R/W [7:0] User Pattern 2[15:8] User Test Pattern 2 most significant byte 0x0 R/W [7:0] User Pattern 3[7:0] User Test Pattern 3 least significant byte 0x0 R/W [7:0] User Pattern 3[15:8] User Test Pattern 3 most significant byte 0x0 R/W [7:0] User Pattern 4[7:0] User Test Pattern 4 least significant byte 0x0 R/W [7:0] User Pattern 4[15:8] User Test Pattern 4 most significant byte 0x0 R/W 1111 0x0551 Continuous repeat. Single pattern. Reserved. Reset 0x0 0x0 0x0 0x0 0x0 Rev. A | Page 88 of 99 Data Sheet Address 0x0559 Name Pair map Output Control Mode 0 AD6684 Bits 7 [6:4] 3 [2:0] 0x055A 0x0561 Pair Map Output Control Mode 1 [7:3] [2:0] Pair map output sample mode [7:3] 2 [1:0] 0x0564 0x056E 0x056F Pair map output channel select JESD204B map PLL control JESD204B map PLL status [7:2] 1 0 [7:4] [3:0] 7 Bit Name Reserved Converter Control Bit 1 selection Reserved Converter Control Bit 0 selection Settings Description Reserved. 000 001 010 011 100 101 110 111 Tie low (1'b0). Overrange bit. Signal monitor bit or VDR punish Bit 0. Fast detect (FD) bit or VDR punish Bit 1. VDR high/low resolution bit. SYSREF. Reserved. Reserved. Reserved. 000 001 010 011 100 101 Reserved Converter control Bit 2 selection 000 001 010 011 100 101 110 111 Reserved Sample invert Tie low (1'b0). Overrange bit. Signal monitor bit or VDR punish Bit 0. Fast detect (FD) bit or VDR punish Bit 1. VDR high/low resolution bit. SYSREF. Reserved. Reserved. Reserved. 0 1 ADC sample data is not inverted. ADC sample data is inverted. 00 01 Offset binary. Twos complement (default). Reserved. Reserved. Data format select Reserved Reserved Converter channel swap control 0 1 Normal channel ordering. Channel swap enabled. 0000 0001 0011 0101 Lane rate = 6.75 to 13.5 Gbps. Lane rate = 3.375 Gbps to 6.75 Gbps. Lane rate = 13.5 to 15 Gbps. Lane rate = 1.6875 Gbps to 3.375 Gbps. Reserved. JESD204B lane rate control Reserved PLL lock status 0 1 [6:4] 3 [2:0] Tie low (1'b0) Overrange bit. Signal monitor or VDR punish Bit 0. Fast detect (FD) bit or VDR punish Bit 1. VDR high/low resolution bit. SYSREF. Reserved. Reserved Reserved Reserved Not locked. Locked. Reserved. Reserved. Reserved. Rev. A | Page 89 of 99 Reset 0x0 0x0 Access R R/W 0x0 0x0 R R/W 0x0 0x1 R R/W 0x0 0x0 R R/W 0x1 R/W 0x0 0x0 0x0 R R/W R/W 0x0 R/W 0x0 0x0 R R 0x0 0x0 0x0 R R R AD6684 Address 0x0570 Name JESD204B map JTX quick configuration Data Sheet Bits [7:6] Bit Name Quick Configuration L Settings 0 1 [5:3] Quick Configuration M 0 1 10 [2:0] Quick Configuration F 0 1 10 11 0x0571 JESD204B map JTX Link Control 1 7 Standby mode 0 1 6 5 4 [3:2] 0 1 Disable. Enable. 0 1 JESD204B test samples disabled. JESD204B test samples enabled. The long transport layer test sample sequence (as specified in JESD204B Section 5.1.6.3) sent on all link lanes. 0 1 Disable FACI uses /K28.7/. Enable FACI uses /K28.3/ and /K28.7/. 00 Initial lane alignment sequence disabled (see JESD204B Section 5.3.3.5). Initial lane alignment sequence enabled (see JESD204B Section 5.3.3.5). Initial lane alignment sequence always on test mode. JESD204B data link layer test mode where repeated lane alignment sequence (as specified in JESD204B, Section 5.3.3.8.2) sent on all lanes. Long transport layer test Lane synchronization ILAS sequence mode 11 FACI 0 1 0 1 Access R/W 0x1 R/W 0x1 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x1 R/W 0x1 R/W 0x0 R/W 0x0 R/W Frame alignment character insertion enabled (JESD204B, Section 5.3.3.4). Frame alignment character insertion disabled; for debug only (JESD204B, Section 5.3.3.4) Link control 0 Reset 0x1 Standby mode forces zeros for all converter samples. Standby mode forces code group synchronization (K28.5 characters). Tail bit (t) PN 01 1 Description Number of lanes (L) = 2Register0x0570, Bits[7:6] L = 1. L = 2. Number of converters (M) = 2Register 0x0570, Bits[5:3] M = 1. M = 2. M = 4. Number of octets/frame (F) = 2Register 0x0570, Bits[2:0] F = 1. F = 2. F = 4. F = 8. JESD204B serial transmit link enabled. Transmission of the /K28.5/ characters for code group synchronization is controlled by the SYNCINBx signal pin. JESD204B serial transmit link powered down (held in reset and clock gated). Rev. A | Page 90 of 99 Data Sheet Address 0x0572 Name JESD204B map JTX Link Control 2 AD6684 Bits [7:6] Bit Name SYNCINBAB/ SYNCINBCD pin control Settings Description 00 10 Normal mode. Ignore SYNCINBAB/SYNCINBCD (force CGS). Ignore SYNCINBAB/SYNCINBCD (force ILAS/user data). 11 5 SYNCINBAB/ SYNCINBCD pin invert 0 1 4 3 2 1 0x0573 JESD204B map JTX Link Control 3 0 [7:6] Reserved 8-bit/10-bit bypass 8-bit/10-bit enabled. 8-bit/10-bit bypassed (the most significant two bits are 0). 0 1 Normal. Invert a b c d e f g h i j symbols. Reserved. 8-bit/10-bit bit invert 00 01 10 11 [5:4] JESD204B test mode patterns 0x0 R/W 0x0 R/W 0x0 0x0 R R/W 0x0 R/W 0x0 0x0 R/W R/W 0x0 R/W 0x0 R/W Checksum is the sum of all the 8-bit registers in the link configuration table. Checksum is the sum of all individual link configuration fields (LSB aligned). Checksum is disabled (set to 0). For test purposes only. Unused. Test injection point 0 1 [3:0] LVDS differential pair SYNC signal input. CMOS single-ended SYNC signal input. Reserved. 0 1 Reserved Checksum mode Access R/W SYNCINBAB/SYNCINBCD pin not inverted. SYNCINBAB/SYNCINBCD pin inverted. SYNCINBAB/ SYNCINBCD pin type 0 1 Reset 0x0 10 N' sample input. 10-bit data at 8-bit/10-bit output (for PHY testing). 8-bit data at scrambler input. 0 1 10 11 100 101 110 111 1000 1110 1111 Normal operation (test mode disabled). Alternating checkerboard. 1/0 word toggle. 31-bit PN sequence: x31 + x28 + 1. 23-bit PN sequence: x23 + x18 + 1. 15-bit PN sequence: x15 + x14 + 1. 9-bit PN sequence: x9 + x5 + 1. 7-bit PN sequence: x7 + x6 + 1. Ramp output. Continuous/repeat user test. Single user test. Rev. A | Page 91 of 99 AD6684 Address 0x0574 Name JESD204B map JTX Link Control 4 Data Sheet Bits [7:4] Bit Name ILAS delay Settings Description 0 Transmit ILAS on first LMFC after SYNCINBx is deasserted. Transmit ILAS on second LMFC after SYNCINB is deasserted. Transmit ILAS on third LMFC after SYNCINBx is deasserted. Transmit ILAS on fourth LMFC after SYNCINB is deasserted. Transmit ILAS on fifth LMFC after SYNCINBx is deasserted. Transmit ILAS on sixth LMFC after SYNCINBx is deasserted. Transmit ILAS on seventh LMFC after SYNCINBx is deasserted. Transmit ILAS on eighth LMFC after SYNCINBx is deasserted. Transmit ILAS on ninth LMFC after SYNCINBx is deasserted. Transmit ILAS on 10th LMFC after SYNCINBx is deasserted. Transmit ILAS on 11th LMFC after SYNCINBx is deasserted. Transmit ILAS on 12th LMFC after SYNCINBx is deasserted. Transmit ILAS on 13th LMFC after SYNCINBx is deasserted. Transmit ILAS on 14th LMFC after SYNCINBx is deasserted. Transmit ILAS on 15th LMFC after SYNCINBx is deasserted. Transmit ILAS on 16th LMFC after SYNCINBx is deasserted. Reserved. 1 10 11 100 101 110 111 1000 1001 1010 1011 1100 1101 1110 1111 3 [2:0] Reserved Link layer test mode 000 001 010 011 100 101 110 111 0x0578 JESD204B map JTX LMFC offset [7:5] [4:0] Reserved LMFC phase offset value Normal operation (link layer test mode disabled). Continuous sequence of /D21.5/ characters. Reserved. Reserved. Modified RPAT test sequence. JSPAT test sequence. JTSPAT test sequence. Reserved. Reserved. LMFC phase offset value; reset value for LMFC phase counter when SYSREF is asserted. Used for deterministic delay applications. Rev. A | Page 92 of 99 Reset 0x0 Access R/W 0x0 0x0 R R/W 0x0 0x0 R R/W Data Sheet Address 0x0580 AD6684 Name JESD204B map JTX DID configuration JESD204B map JTX BID configuration Bits [7:0] Bit Name JESD204B Tx DID value [7:4] [3:0] Reserved JESD204B Tx BID value 0x0583 JESD204B map JTX LID0 configuration [7:5] [4:0] Reserved Lane 0 LID value 0x0585 JESD204B map JTX LID1 configuration [7:5] [4:0] Reserved Lane 1 LID Value 0x058B JESD204B map JTX SCR L configuration 7 JESD204B scrambling (SCR) 0x0581 Settings 0 1 [6:5] [4:0] Reserved JESD204B lanes (L) 0x0 0x1 0x058C 0x058D JESD204B map JTX F configuration JESD204B map JTX K configuration [7:0] Number of octets per frame (F) [7:5] [4:0] Reserved Number of frames per multiframe (K) 00011 00111 01100 01111 10011 10111 11011 11111 0x058E JESD204B Map JTX M configuration [7:0] Number of converters per link 00000000 00000001 00000011 0x058F JESD204B map JTX CS N configuration [7:6] Reset 0x0 Access R/W Reserved. JESD204B serial bank identification (BID) number (extension to DID). Reserved. JESD204B serial lane identification (LID) number for Lane 0. Reserved. JESD204B serial lane identification (LID) number for Lane 1. 0x0 0x0 R R/W 0x0 0x0 R R/W 0x0 0x2 R R/W 0x1 R/W 0x0 0x1 R R 0x1 R 0x0 0x1F R R/W 0x1 R 0x0 R/W 0x0 R JESD204B scrambler disabled. SCR = 0. JESD204B scrambler enabled. SCR = 1. Reserved. One lane per link (L = 1). Two lanes per link (L = 2). Number of octets per frame. F = Register 0x058C, Bits[7:0] + 1. Reserved. JESD204B number of frames per multiframe (K = Register 0x058D, Bits[4:0] + 1). Only values where F x K are divisible by 4 can be used. K = 4. K = 8. K = 12. K = 16. K = 20. K = 24. K = 28. K = 32. Link connected to one virtual converter (M = 1). Link connected to two virtual converters (M = 2). Link connected to four virtual converters (M = 4). Number of control bits (CS) per sample 0 1 10 11 5 Description JESD204B serial device identification (DID) number. Reserved No control bits (CS = 0). One control bit (CS = 1), Control Bit 2 only. Two control bits (CS = 2), Control Bit 2 and Control Bit 1 only. Three control bits (CS = 3), all control bits (Bits[2:0]). Reserved. Rev. A | Page 93 of 99 AD6684 Address 0x0590 Name JESD204B map JTX SCV NP configuration Data Sheet Bits [4:0] [7:5] [4:0] 0x0591 JESD204B map JTX JV S configuration [7:5] [4:0] 0x0592 JESD204B map JTX HD CF configuration 7 0x05A0 0x05A1 0x05B0 0x05B2 0x05B3 JESD204B map JTX Checksum 0 configuration JESD204B map JTX Checksum 1 configuration SERDOUTx0/ SERDOUTx1 power-down JESD204B map JTX Lane Assignment 1 JESD204B map JTX Lane Assignment 2 Bit Name ADC converter resolution (N) Settings Description 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 N = 7-bit resolution. N = 8-bit resolution. N = 9-bit resolution. N = 10-bit resolution. N = 11-bit resolution. N = 12-bit resolution. N = 13-bit resolution. N = 14-bit resolution. N = 15-bit resolution. N = 16-bit resolution. 000 001 Subclass 0. Subclass 1. 00111 01111 N' = 8. N' = 16. Reserved. Samples per converter frame cycle (S = Register 0x0591, Bits[4:0] + 1). Subclass support ADC number of bits per sample (N') Reserved Samples per converter frame cycle (S) HD value 0 1 [6:5] [4:0] Reserved Control words per frame clock cycle per link (CF) [7:0] Checksum 0 checksum value for SERDOUTAB0/ SERDOUTCD0 [7:0] Checksum 1 checksum value for SERDOUTAB1/ SERDOUTCD1 [7:3] 2 1 0 7 [6:4] 3 [2:0] Reserved SERDOUTx1 power-down Reserved SERDOUTx0 power-down Reserved Reserved Reserved SERDOUTAB0/ SERDOUTCD0 lane assignment 7 [6:4] 3 [2:0] Reserved Reserved Reserved SERDOUTAB1/ SERDOUTCD1 lane assignment 0 1 0 1 High density format disabled. High density format enabled. Reserved. Number of control words per frame clock cycle per link (CF = Register 0x0592, Bits[4:0]). Serial checksum value for Lane 0, automatically calculated for each lane. Sum (all link configuration parameters for Lane 0) mod 256. Serial checksum value for Lane 1, automatically calculated for each lane. Sum (all link configuration parameters for Lane 1) mod 256. Reserved. Physical Lane 1 force power-down. Reserved. Physical Lane 0 force power-down. Reserved. Reserved. Reserved. Logical Lane 0 (default). Logical Lane 1. Reserved. Reserved. Reserved. Logical Lane 0. Logical Lane 1 (default). Rev. A | Page 94 of 99 Reset 0xF Access R/W 0x1 R/W 0xF R/W 0x1 0x0 R R 0x0 R 0x0 0x0 R R 0xC3 R 0xC4 R 0x1F 0x0 0x1 0x0 0x0 0x0 0x0 0x0 R/W R/W R/W R/W R R/W R R/W 0x0 0x1 0x0 0x1 R R/W R R/W Data Sheet Address 0x05C0 0x05C1 0x05C4 Name JESD204B map JESD204B serializer drive adjust JESD204B map JESD204B serializer drive adjust SERDOUTx0 pre-emphasis select AD6684 Bits [7:3] [2:0] Bit Name Reserved Swing voltage SERDOUTx0 Settings [7:3] Reserved [2:0] 7 Swing voltage SERDOUTx1 Post tab polarity 0 1 0 0 1 [6:4] Sets post tap level for SERDOUTx0 0 1 10 11 100 101 110 111 3 Pretab polarity 0 1 [2:0] Sets pretab level 0 1 10 11 100 101 110 111 0x05C6 SERDOUTx1 pre-emphasis select 7 Post tap enable 0 1 [6:4] Sets post tap level for SERDOUTx1 0 1 10 11 100 101 110 111 3 Pretab polarity 0 1 Description Reserved. 1.0 x DRVDD1 (differential). 0.850 x DRVDD1 (differential). Reset 0x0 0x1 Access R R/W Reserved. 0x0 R 1.0 x DRVDD1 (differential). Post tab polarity. Normal. Inverted. These bits set the post tab level. 0x1 0x0 R/W R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0 dB. 3 dB. 6 dB. 9 dB. 12 dB. Not valid. Not valid. Not valid. Pretab polarity. Normal. Inverted. These bits set the pretab level. 0 dB. 3 dB. 6 dB. 9 dB. 12 dB. Not valid. Not valid. Not valid. Post tab polarity. Normal. Inverted. These bits set the post tab level. 0 dB. 3 dB. 6 dB. 9 dB. 12 dB. Not valid. Not valid. Not valid. This bit sets the pretab polarity. Normal. Inverted. Rev. A | Page 95 of 99 AD6684 Address Name Data Sheet Bits [2:0] Bit Name Sets pretab level Settings 0 1 10 11 100 101 110 111 0x0922 0x1222 0x1228 0x1262 0x18A6 Large dither control [7:0] PLL calibration [7:0] JESD204B start-up circuit reset [7:0] 1110000 1110001 PLL calibration 0x00 0x04 JESD204B start-up circuit reset 0x0F 0x4F PLL loss of lock control Pair map VREF control Large dither control PLL loss of lock control 0x00 0x08 [7:5] 4 [3:1] 0 Reserved Reserved Reserved VREF control 0 1 0x1908 Channel map analog input control [7:6] [5:4] 3 2 Reserved Reserved Reserved Analog input dc coupling control 0 1 0x1910 Channel map input fullscale range 1 0 [7:4] [3:0] Reserved Reserved Reserved Input full-scale control 0000 1010 1011 1100 1101 1110 1111 Description These bits set the pretab level. 0 dB. 3 dB. 6 dB. 9 dB. 12 dB. Not valid. Not valid. Not valid. Enables/disables the large dither control. Enable. Disable. PLL calibration. Normal operation. PLL calibration JESD204B start-up circuit reset. Normal operation. Start-up circuit reset. PLL loss of lock control. Normal operation. Clear loss of lock. Reserved. Reserved. Reserved. Internal reference. External reference. Reserved. Reserved. Reserved. Analog input dc coupling control. AC coupling. DC coupling. Reserved. Reserved. Reserved. Input full-scale control 2.16 V p-p. 1.44 V p-p. 1.56 V p-p. 1.68 V p-p. 1.80 V p-p. 1.92 V p-p. 2.04 V p-p. Rev. A | Page 96 of 99 Reset 0x0 Access R/W 0x70 R/W 0x0 R/W 0xF R/W 0x0 R/W 0x0 0x0 0x0 0x0 R R/W R R/W 0x0 0x0 0x0 0x0 R R/W R R/W 0x0 0x0 0x0 0xD R R/W R R/W Data Sheet Address 0x1A4C 0x1A4D 0x18E0 0x18E1 0x18E2 0x18E3 AD6684 Name Channel map Buffer Control 1 Bits [7:6] [5:0] Channel map Buffer Control 2 [7:6] [5:0] External VCM Buffer Control 1 External VCM Buffer Control 2 External VCM Buffer Control 3 External VCM buffer control [7:0] Bit Name Reserved Buffer Control 1 Settings Reset 0x0 0xC Access R R/W 0x0 0xC R R/W External VCM Buffer Control 1 Description Reserved. Buffer Control 1. 120 A. 160 A. 200 A. 240 A. 280 A. 320 A. 360 A. 400 A. 440 A. Reserved. Buffer Control 2. 120 A. 160 A. 200 A. 240 A. 280 A. 320 A. 360 A. 400 A. 440 A. See the Input Common Mode section for details. 0x0 R/W [7:0] External VCM Buffer Control 2 See the Input Common Mode section for details. 0x0 R/W [7:0] External VCM Buffer Control 3 See the Input Common Mode section for details. 0x0 R/W 7 6 Reserved External VCM buffer Reserved. External VCM buffer. Enable. Disable. See the Input Common Mode section for details. Reserved. Temperature diode export. Enable. Disable. 0x0 0x0 R/W R/W 0x0 R/W 0x0 0x0 R/W R/W 00110 01000 01010 01100 01110 10000 10010 10100 10110 Reserved Buffer Control 2 00110 01000 01010 01100 01110 10000 10010 10100 10110 1 0 [5:0] 0x18E6 Temperature diode export [7:1] 0 External VCM buffer current setting Reserved Temperature diode export 1 0 Rev. A | Page 97 of 99 AD6684 Data Sheet APPLICATIONS INFORMATION POWER SUPPLY RECOMMENDATIONS The AD6684 must be powered by the following seven supplies: AVDD1 = AVDD1_SR = 0.975 V, AVDD2 = 1.8 V, AVDD3 = 2.5 V, DVDD = 0.975 V, DRVDD1 = 0.975 V, and SPIVDD = 1.8 V. For applications requiring an optimal high power efficiency and low noise performance, it is recommended that the ADP5054 quad switching regulator be used to convert the 6.0 V or 12 V input rails to intermediate rails (1.3 V, 2.4 V, and 3.0 V). These intermediate rails are then post regulated by very low noise, low dropout (LDO) regulators (ADP1762, ADP7159, ADP151, and ADP7118). Figure 105 shows the recommended power supply scheme for the AD6684. 1.3V ADP1762 (LDO) ADP5054 1.3V (SWITCHING REGULATOR) 2.4V AVDD1: 0.95V FILTER AVDD1_SR: 0.95V ADP1762 FILTER (LDO) DVDD: 0.95V It is required that the exposed pad on the underside of the ADC be connected to AGND to achieve the best electrical and thermal performance of the AD6684. Connect an exposed continuous copper plane on the PCB to the AD6684 exposed pad, Pin 0. The copper plane must have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the PCB. These vias must be solder filled or plugged. The number of vias and the fill determine the resultant JA measured on the board (see Table 7). See Figure 106 for a PCB layout example. For detailed information on packaging and the PCB layout of chip scale packages, see the AN-772 Application Note, A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP). FILTER 3.0V DRVDD1: 0.95V ADP7159 (LDO) ADP7159 (LDO) ADP151 (LDO) ADP7118 (LDO) FILTER FILTER FILTER FILTER AVDD2: 1.8V AVDD3: 2.5V DRVDD2: 1.8V SPIVDD: 1.8V 14994-091 6V/12V INPUT EXPOSED PAD THERMAL HEAT SLUG RECOMMENDATIONS It is not necessary to split all of these power domains in all cases. The recommended solution shown in Figure 105 provides the lowest noise, highest efficiency power delivery system for the AD6684. If only one 0.975 V supply is available, route to AVDD1 first and then tap it off and isolate it with a ferrite bead or a filter choke, preceded by decoupling capacitors for AVDD1_SR, DVDD, and DRVDD, in that order. The user can employ several different decoupling capacitors to cover both high and low frequencies. These capacitors must be located close to the point of entry at the PCB level and close to the devices, with minimal trace lengths. 14994-092 Figure 105. High Efficiency, Low Noise Power Solution for the AD6684 Figure 106. Recommended PCB Layout of Exposed Pad for the AD6684 AVDD1_SR (PIN 64) AND AGND_SR (PIN 63 AND PIN 67) AVDD1_SR (Pin 64) and AGND_SR (Pin 63 and Pin 67) can be used to provide a separate power supply node to the SYSREF circuits of the AD6684. If running in Subclass 1, the AD6684 can support periodic one-shot or gapped signals. To minimize the coupling of this supply into the AVDD1 supply node, adequate supply bypassing is needed. Rev. A | Page 98 of 99 Data Sheet AD6684 OUTLINE DIMENSIONS 10.10 10.00 SQ 9.90 0.60 0.42 0.24 0.60 0.42 0.24 0.30 0.23 0.18 55 72 54 PIN 1 INDICATOR 1 PIN 1 INDICATOR 9.85 9.75 SQ 9.65 0.50 BSC 0.50 0.40 0.30 19 BOTTOM VIEW 0.05 MAX 0.02 NOM SEATING PLANE 0.20 MIN 8.50 REF 0.80 MAX 0.65 NOM COPLANARITY 0.08 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.20 NOM COMPLIANT TO JEDEC STANDARDS MO-220-VNND-4 06-30-2015-A PKG-004890 12 MAX 18 37 36 TOP VIEW 1.00 0.85 0.80 7.45 7.30 SQ 7.15 EXPOSED PAD Figure 107. 72-Lead Lead Frame Chip Scale Package [LFCSP] 10 mm x 10 mm Body and 0.85 mm Package Height (CP-72-10) Dimensions shown in millimeters ORDERING GUIDE Model 1 AD6684BCPZ-500 AD6684BCPZRL7-500 AD6684-500EBZ 1 Junction Temperature Range -40C to +105C -40C to +105C Package Description 72-Lead Lead Frame Chip Scale Package [LFCSP] 72-Lead Lead Frame Chip Scale Package [LFCSP] Evaluation Board for AD6684 Z = RoHS Compliant Part. (c)2016-2020 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D14994-4/20(A) Rev. A | Page 99 of 99 Package Option CP-72-10 CP-72-10