S7017 series is a family of FFT-CCD area image sensors specifically designed for low-light-level detection in scientific applications. By using the
binning operation, S7017 series can be used as a linear image sensor having a long aperture in the direction of the device length. This makes
S7017 series ideally suited for use in spectrophotometry. The binning operation offers significant improvement in S/N and signal processing
speed compared with conventional methods by which signals are digitally added by an external circuit. S7017 series also features low noise and
low dark signal (MPP mode operation). These enable low-light-level detection and long integration time, thus achieving a wide dynamic range.
S7017 series has a pixel size of 24 × 24 µm and is available in active area of 24.576 (H) × 2.976 (V) and 24.576 (H) × 6.048 (V) mm.
A four-stage Peltier element is built into the same package for thermoelectric cooling. At room temperature operation, the device can be cooled
down to -70 ˚C with using forced air cooling. In addition, since both the CCD chip and Peltier element are hermetically sealed, no dry air is
required, thus allowing easy handling.
Features Applications
IMAGE SENSOR
CCD area image sensor
Four-stage TE-cooled, front-illuminated FFT-CCDs
S7017 series
■ Selection and order guide
Type No. Cooling Number of
total pixels
Number of
active pixels
Active area
[mm (H) × mm (V)]
S7017-1007 1044 × 128 1024 ×124 24.576 × 2.976
S7017-1008
Four-stage
TE-cooled 1044 × 256 1024 × 252 24.576 × 6.048
S7017 series has a hermetically-sealed package with AR-coated sapphire window.
■ General ratings
Parameter Specification
CCD structure Full frame transfer
Fill factor 100 %
Number of active pixels S7017-1007: 1024 (H) × 124 (V)
S7017-1008: 1024 (H) × 252 (V)
Pixel size 24 (H) × 24 (V) µm
Active area S7017-1007: 24.576 (H) × 2.976 (V) mm
S7017-1008: 24.576 (H) × 6.048 (V) mm
Vertical clock phase 2 phase
Horizontal clock phase 2 phase
Output circuit One-stage MOSFET source follower
Package 28 pin metal package
Window AR coated Sapphire
● 1024 (H) × 124 (V) and 1024 (H) × 252 (V) pixel for mat
● Pixel size: 24 × 24 µm
● 100 % fill factor
● Wide dynamic range
● Low dark current
● Low readout noise
● MPP operation
● Four-stage TE-cooled
● Astronomy
● Scientific measuring instr ument
● Fluorescence spectrometer
● Raman spectrophotometer
● Optical and spectrophotometric analyzer
● For low-light-level detection requiring
1
CCD area image sensor
S7017 series
■ Absolute maximum ratings (Ta=25 °C)
Parameter Symbol Min. Typ. Max. Unit
Operating temperature Topr -50 - +30 °C
Storage temperature Tstg -100 -+70 °C
OD voltage VOD -0.5 - +25 V
RD voltage VRD -0.5 -+18 V
ISV voltage VISV -0.5 - +18 V
ISH voltage VISH -0.5 -+18 V
IGV voltage VIG1V, VIG2V -10 - +15 V
IGH voltage VIG1H, VIG2H -10 -+15 V
SG voltage VSG -10 - +15 V
OG voltage VOG -10 -+15 V
RG voltage VRG -10 - +15 V
TG voltage VTG -10 -+15 V
Vertical clock voltage VP1V, VP2V -10 - +15 V
Horizontal clock voltage VP1H, VP2H -10 -+15 V
■ Operating conditions (MPP mode, Ta=25 °C)
Parameter Symbol Min. Typ. Max. Unit
Output transistor drain voltage VOD 18 20 22 V
Reset drain voltage VRD 11.5 12 12.5 V
Output gate voltage VOG 135V
Substrate voltage VSS - 0 - V
Test point (vertical input source) VISV -V
RD -V
Test point (horizontal input source) VISH - VRD - V
Test point (vertical input gate) VIG1V, VIG2V -8 0 - V
Test point (horizontal input gate) VIG1H, VIG2H -8 0 - V
High VP1VH, VP2VH 468
Vertical shift register
clock voltage Low VP1VL, VP2VL -9 -8 -7 V
High VP1HH, VP2HH 4 6 8
Horizontal shift register
clock voltage Low VP1HL, VP2HL -9 -8 -7 V
High VSGH 468
Summing gate voltage Low VSGL -9 -8 -7 V
High VRGH 4 6 8
Reset gate voltage Low VRGL -9 -8 -7 V
High VTGH 468
Transfer gate voltage Low VTGL -9 -8 -7 V
■ Electrical characteristics (Ta=25 °C)
Parameter Symbol Remark Min. Typ. Max. Unit
Signal output frequency fc - - 80 2,000 kHz
Reset clock frequency frg - - 80 2,000 kHz
S7017-1007 - - 3,200 -Vertical shift register
capacitance S7017-1008 CP1V, CP2V - - 6,400 - pF
Horizontal shift register capacitance CP1H, CP2H - - 300 -pF
Summing gate capacitance CSG -- 7 -pF
Reset gate capacitance CRG - - 7 - pF
Transfer gate capacitance CTG - - 150 - pF
Transfer efficiency CTE *10.99995 0.99999 - -
DC output level Vout *212 15 18 V
Output impedance Zo *2- 3 - kΩ
Power dissipation P *2, *3-15-mW
*1: Charge transfer efficiency per pixel, measured at half of the full well capacity.
*2: VOD=20 V , Load resistance=22 kΩ
*3: Power dissipation of the on-chip amplifier.
2
CCD area image sensor
S7017 series
■Electrical and optical characteristics (Ta=25 °C, unless otherwise noted)
Parameter Symbol Remark Min. Typ. Max. Unit
Saturation output voltage Vsat - - Fw × Sv - V
Vertical 150 300 -
Full well
capacity Horizontal Fw *4
300 600 -ke-
CCD conversion efficiency Sv *51.8 2.2 - µV/e-
+25 °C -400 3,000
0 °C -20 150
Dark current
(MPP mode) -70 °C
DS *6
-0.0015 0.01
e-/pixel/s
Readout noise Nr *7-612
e-rms
Line binning 25,000 75,000 -
Dynamic range Area scanning DR *8
12,500 37,500 --
Spectral response range λ- - 400 to 1,100 - nm
Photo response non-uniformity PRNU *9- - ±10 %
Point defects *10 --0
Cluster defects *11 --0Blemish
Column defects
-
*12 --0
-
*4: Large horizontal full well for line binning operation.
*5: VOD=20 V , Load resistance=22 kΩ
*6: Dark current nearly doubles for every 5 to7 °C increase in temperature.
*7: -40 °C, operating frequency is 80 kHz.
*8: DR = Fw / Nr
*9: Measured at half of the full well capacity. PRNU (%) = noise / signal × 100, noise: fixed pattern noise (peak to peak)
*10: White spots > 3 % of full well at 0 °C after Ts=1 s, Black spots > 50 % reduction in response relative to adjacent
pixels
*11: continuous 2 to 9 point defects
*12: continuous >10 point defects
■ PIN connections
Pin No. Symbol Description Remark
1P- TE-cooler-
2NC
3SS
Substrate (GND)
4NC
5ISV
Test point (vertical input source) Shorted to RD
6IG2V Test point (vertical input gate-2) Shorted to 0 V
7 IG1V Test point (vertical input gate-1) Shorted to 0 V
8RG Reset gate
9RD Reset drain
10 OS Output transistor source
11 OD Output transistor drain
12 OG Output gate
13 SG Summing gate Same timin
g
as P2H
14 P+ TE-cooler+
15 TSH1 Temperature sensor (hot side)
16 TSC1 Temperature sensor (cool side)
17 TSC2 Temperature sensor (cool side)
18 P2H CCD horizontal register clock-2
19 P1H CCD horizontal register clock-1
20 IG2H Test point (horizontal input gate-2) Shorted to 0 V
21 IG1H Test point (horizontal input gate-1) Shorted to 0 V
22 ISH Test point (horizontal input source) Shorted to RD
23 P2V CCD vertical register clock-2
24 P1V CCD vertical register clock-1
25 TG Transfer gate Same timing as P2V *13
26 NC
27 NC
28 TSH2 Temperature sensor (hot side)
*13: TG is an isolation gate between vertical register and horizontal resister.
In standard o
p
eration, the same
p
ulse of P2V should be a
pp
lied to the TG.
3
CCD area image sensor
S7017 series
50
40
30
20
10
0
400 500 600 700
WAVELENGTH (nm)
800 900 1000 1100 1200
QUANTUM EFFICIENCY (%)
(Typ. Ta=25 ˚C)
KMPDB0051EA
■ Spectral response without window
100 (Typ. Ta=25 ˚C)
95
90
85
80
400 500 600 700 800
WAVELENGTH (nm)
TRANSMITTANCE (%)
900 1000 1100 1200
AR COATED SAPPHIRE
KMPDB0106EA
KMPDA0098EA
■ Dimensional outline (unit: mm)
4.0 7.0
5.0PINCHED OFF TUBE
S7017-1007
TYPE No.
24.576 (H)
a
S7017-1008 24.576 (H)
2.976 (V)
b
ACTIVE AREA
6.048 (V)
2.54
27.94
0.46
20.0
b
36.0
44.0
50.0
35.0
6.4 ± 0.5
18.5 ± 0.5
47.0
50.8
0.25
14
13
12
3
2
16
17
26
27
a
1.0
PIN No. 1
1st PIN INDEX MARK
AR-COATED SAPPHIRE WINDOW
15
28
■ Spectral transmittance characteristic
of window material
4
CCD area image sensor
S7017 series
KMPDC0085EA
■ Device structure, line output format
......
......
......
V
1H
IG1V IG2V ISV SS
RG
RD
OS
OD OG SG
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
S1
S2
S1023
S1024
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
8
9
10
11 12 13
3
657 25 24
V=124, 252
H=1024
ISH
IG1H
IG2H
P1HP2H
22
21
201918
4 BLANK4 BLANK 4 OPTICAL
BLACK 4 OPTICAL
BLACK
1024
SIGNAL OUT
2 ISOLATOIN 2 ISOLATOIN
TG P1V 23
P2V
KMPDC0086EA
■ Timing chart
● Area scanning 1 (low dark current mode)
INTEGRATION PERIOD
(Shutter must be open)
P1V
RG
OS
P2V, TG
P1H
P2H, SG
READOUT PERIOD (Shutter must be closed)
ENLARGED VIEW
4..127
4..255 128←124+4 (ISOLATION)
256←252+4 (ISOLATION) : S7017-1007
: S7017-1008
Tpwv
Tovr
Tpwr
D1 D2 D3 D4 D18 D19 D20
D5..D10, S1..S1024, D11..D17
P2V, TG
P1H
P2H, SG
RG
OS
Tpwh, Tpws
123
Pixel format
Left ← Horizontal Direction → Right
Blank Optical Black Isolation Effective Isolation Optical Black Blank
4421024244
Top ← Vertical Direction → Bottom
Isolation Effective Isolation
2124 or 2522
5
CCD area image sensor
S7017 series
Parameter Symbol Remark Min. Typ. Max. Unit
Pulse width Tpwv 6 *15 --µs
P1V, P2V, TG Rise and fall time Tprv, Tpfv *14
200 - - ns
Pulse width Tpwh 250 - - ns
Rise and fall time Tprh, pfh 10 - - nsP1H, P2H
Duty ratio -
*14
-50 - %
Pulse width Tpws 250 - - ns
Rise and fall time Tprs, Tpfs 10 - - nsSG
Duty ratio -
-
-50- %
Pulse width Tpwr 100 - - ns
RG Rise and fall time Tprr, Tpfr -5 - - ns
TG – P1H Overlap time Tovr - 3 - - µs
*14: Symmetrical pulses should be overlapped at 50 % of maximum amplitude.
*15: In case of S7017-1007.
KMPDC0100EA
● Area scanning 2 (large full well mode)
INTEGRATION PERIOD
(Shutter must be open)
P1V
RG
OS
P2V, TG
P1H
P2H, SG
READOUT PERIOD (Shutter must be closed)
ENLARGED VIEW
4..127
4..255 128←124+4 (ISOLATION)
256←252+4 (ISOLATION) : S7017-1007
: S7017-1008
Tpwv
Tovr
Tpwr
D1 D2 D3 D4 D18 D19 D20
D5..D10, S1..S1024, D11..D17
P2V, TG
P1H
P2H, SG
RG
OS
Tpwh, Tpws
123
Parameter Symbol Remark Min. Typ. Max. Unit
Pulse width Tpwv 6 *17 --µs
P1V, P2V, TG Rise and fall time Tprv, Tpfv *16
200 - - ns
Pulse width Tpwh 250 - - ns
Rise and fall time Tprh, Tpfh 10 - - nsP1H, P2H
Duty ratio -
*16
-50 - %
Pulse width Tpws 250 - - ns
Rise and fall time Tprs, Tpfs 10 - - nsSG
Duty ratio -
-
-50- %
Pulse width Tpwr 100 - - ns
RG Rise and fall time Tprr, Tpfr -5 - - ns
TG - P1H Overlap time Tovr - 3 - - µs
*16: Symmetrical pulses should be overlapped at 50 % of maximum amplitude.
*17: In case of S7017-1007.
6
CCD area image sensor
S7017 series
KMPDC0087EA
● Line binning
Parameter Symbol Remark Min. Typ. Max. Unit
Pulse width Tpwv 6 *19 --µs
P1V, P2V, TG Rise and fall time Tprv, Tpfv *18
200 - - ns
Pulse width Tpwh 250 - - ns
Rise and fall time Tprh, Tpfh 10 - - nsP1H, P2H
Duty ratio -
*18
-50 - %
Pulse width Tpws 250 - - ns
Rise and fall time Tprs, Tpfs 10 - - nsSG
Duty ratio -
-
-50- %
Pulse width Tpwr 100 - - ns
RG Rise and fall time Tprr, Tpfr -5 - - ns
TG – P1H Overlap time Tovr - 3 - - µs
*18: Symmetrical pulses should be overlapped at 50 % of maximum amplitude.
*19: In case of S7017-1007.
■ Specifications of built-in TE-cooler
Parameter Symbol Condition Min. Typ. Max. Unit
Internal resistance Rint Ta=27 °C - 1.6 - Ω
Maximum current *20 Imax Th *21=27 °C
∆T *22=∆Tmax - - 4.4 A
Maximum voltage Vmax
Th*21=27 °C
∆T=∆Tmax
I=Imax
--7.4V
Maximum heat absorption *23 Qmax Tc *24=Th *21=27 °C
I=Imax - - 3.0 W
Maximum temperature at hot side - - - 50 °C
CCD temperature -Ta=25 °C --70 -50 °C
*20: If the current is greater than Imax, the heat absorption begins to decrease due to the Joule heat. It should be noted that
this value is not a damage threshold. To protect the thermoelectric cooler (Peltier element) and maintain stable operation,
the supply current should be less than 60 % of this maximum current.
*21: Temperature at hot side of thermoelectric cooler.
*22: ∆T=Th - Tc
*23: This is a theoretical heat absorption level that offsets the temperature difference in the Peltier element when the maximum
current is supplied to the unit.
*24: Temperature at cool side of thermoelectric cooler.
INTEGRATION PERIOD
(Shutter must be open) VERTICAL BINNING PERIOD
(Shutter must be closed)
3..126
3..254 127
255 128←
256←
P1V
P2V, TG
P1H
P2H, SG
READOUT PERIOD (Shutter must be closed)
124+4 (ISOLATION): S7017-1007
252+4 (ISOLATION): S7017-1008
Tpwv
Tovr
Tpwh, Tpws
Tpwr
123
1043 1044
4..1042
12
D19D2D1 D20
D3..D10, S1..S1024, D11..D18
RG
OS
7
CCD area image sensor
S7017 series
KMPDB0107EA
V - I
CCD TEMPERATURE - I
0
1
2
3
VOLTAGE (V)
CCD TEMPERATURE (˚C)
4
5
6
-80
3.02.52.01.5
CURRENT (A)
1.00.50
-60
-40
-20
0
20
40
(Typ. Ta=25 ˚C)
■ Specifications of built-in temperature sensors
Parameter Symbol Condition Min. Typ. Max. Unit
Resistance at cool side Rc T=0 °C - 1,000 - Ω
Temperature coefficient of resistance at cool side - - - 0.00375 -Ω/Ω
Resistance at hot side Rh T=0 °C - 1,000 - Ω
Temperature coefficient of resistance at hot side - - - 0.00385 -Ω/Ω
KMPDB0108EA
0
-100 -80 -60 -40 -20 0 20 40
RESISTANCE (Ω)
1400
1200
1000
800
600
400
200
TEMPERATURE (˚C)
(Typ. Ta=25 ˚C)
■ Precaution for use (electrostatic countermeasures)
● Handle these sensors with bare hands or wearing cotton gloves. In addition, wear anti-static clothing or use a wrist band with
an earth ring, in order to prevent electrostatic damage due to electrical charges from friction.
● Avoid directly placing these sensors on a work-desk or work-bench that may carry an electrostatic charge.
● Provide ground lines or ground connection with the work-floor, wor k-desk and wor k-bench to allow static electricity to
discharge.
● Ground the tools used to handle these sensors, such as tweezers and soldering irons.
It is not always necessary to provide all the electrostatic measures stated above. Implement these measures according to the
amount of damage that occurs.
■ Element cooling/heating temperature incline rate
Element cooling/heating temperature incline rate should be set at less than 5 K/min.
HAMAMATSU PHOTONICS K.K., Solid State Division
1126-1 Ichino-cho, Hamamatsu City, 435-8558 Japan, Telephone: (81) 053-434-3311, Fax: (81) 053-434-5184, http://www.hamamatsu.com
U.S.A.: Hamamatsu Corporation: 360 Foothill Road, P.O.Box 6910, Bridgewater, N.J. 08807-0910, U.S.A., Telephone: (1) 908-231-0960, Fax: (1) 908-231-1218
Germany: Hamamatsu Photonics Deutschland GmbH: Arzbergerstr. 10, D-82211 Herrsching am Ammersee, Germany, Telephone: (49) 08152-3750, Fax: (49) 08152-2658
France: Hamamatsu Photonics France S.A.R.L.: 8, Rue du Saule Trapu, Parc du Moulin de Massy, 91882 Massy Cedex, France, Telephone: 33-(1) 69 53 71 00, Fax: 33-(1) 69 53 71 10
United Kingdom: Hamamatsu Photonics UK Limited: 2 Howard Court, 10 Tewin Road, Welwyn Garden City, Hertfordshire AL7 1BW, United Kingdom, Telephone: (44) 1707-294888, Fax: (44) 1707-325777
North Europe: Hamamatsu Photonics Norden AB: Smidesvägen 12, SE-171 41 Solna, Sweden, Telephone: (46) 8-509-031-00, Fax: (46) 8-509-031-01
Italy: Hamamatsu Photonics Italia S.R.L.: Strada della Moia, 1/E, 20020 Arese, (Milano), Italy, Telephone: (39) 02-935-81-733, Fax: (39) 02-935-81-741
Information furnished by HAMAMATSU is believ ed to be reliable. However, no responsibility is assumed for possible inaccuracies or omissions.
Specifications are subject to change without notice. No patent rights are granted to any of the circuits described herein. ©2005 Hamamatsu Photonics K.K.
Cat. No. KMPD1030E07
Apr. 2005 DN
8
