73S8009C-DB - Maxim Integrated

73S8009C

Versatile Power Management

and Smar t C ard In t erface IC

Simplifying System Integration™ D ATA SH EET

DS_8009C_025 February 2010

DESCRIPTION

The Terid ian 73S8009C is a versati le power

management and single smart car d i nterface circuit

t hat is ideal ly suited for smart car d r eader pr oducts

t hat are battery an d/or U SB bus -power ed. In

addition to its EMV 4.1 and ISO-7816-3 compliant

smart card-to-h ost interface ci r cuitry; i t provides

control , conversion, and regul ation of pow er for a

companion host processor circuit and power for the

smart card. The 73S8009C can operate from a

si ngle 2. 7 V to 6.5 V so ur ce su ppl y, or a

combination of battery power (4.0 V to 6.5 V) and

USB power (4.4 V to 5.5 V).

The 73S 80 09C suppor ts 5 V, 3 V, and 1. 8 V smar t

cards. The smart card signals for RST, C LK, IO,

and au xil iary signals AU X1 and AUX2 are

level-shifted to the selected VCC value. A lth ough

t he host control l er is r equi r ed to handle the

det ai led si gnal timing for activation and de-

activation under normal co ndi ti ons, th e 73S8009C

blocks any spurious signals on CLK, RST and IO

dur ing power-up (as VCC rises) and pow er-down.

The 73S8009C contai ns two handshaking signals

for t he cont r oller: OFF i ndicates that a ca r d i s

prese nt, and RDY i ndicates that VCC is at an

accept able val ue. Th e 73S8009C will perform

emergency deactiva tion upon card removal,

voltage faults, or over-cu r r ent even ts

The power management circuitry of the 73S8009C

allows operation fr om a wide r ange of vo lt ages

from mul tiple sour ces. VPC is converted by using

an inducti ve, step-up power conver ter to the

intermedi ate voltage, VP. VP i s used by li near

vol tage regul ators and switc hes t o create th e

vol tages V DD and as requir ed, VCC. VDD is use d by

t he 73S8009C and is al so made availabl e for the

comp anion controll er cir cuit or other ext er nal

circuits. The VBAT and VBUS pins provide inputs

from alternate power source s as r equi r ed. An

internal switch in the 73S8009C acts as a

single-pole, double-throw switch that selects either

VBAT or VBUS to b e connected to VPC. When t he

vol tage on VBUS is zer o, VBAT i s connected t o VPC.

When volt age i s appli ed to VBUS, the sw i tch selects

VBUS as the so ur ce for power.

When power is supplied by VPC or V BAT, the

73S 8009C is cont r olled by the ON_OF F pin in the

manner of a “push-on/push-off” butt on action. The

O FF_R EQ and OFF_A C K signals provide

hand shaking and control of the power “of f”

f unct i o n by the co ntroller. A SPST momentary

switch to ground connected to O N _OFF is all that

is r equired for power control. Alternatively, the

“off” state can be in it i ated from the host controll er

t hr ough OFF_ACK. When the 73S8009C i s “off,”

the curren t is less than 1 µA.

When power is suppli ed via the VBUS pin, th e

73S8009C is unconditionally in the “power-on”

state regardl ess of the action of the ON/OFF

switch or OFF_ACK signal. Power supply current

operating from the VBUS p ower wh en VCC is off is

less than 500 µA to conform to USB “SUSPEND ”

requirements.

APPLICATIONS

• Handheld PINpad smart ca r d r eader s for

e-commerce, secur e log in, e-health, Gov’t ID

and loyalty

• P oint of Sales & Transacti on Termi nal s

• G ener al Pur pose Smart Card Readers

ADVANTAGES

• Ideally suited to USB bus-powered

applications

 Ideal for combo bus -powered and/or

self-powered sy stems

 Autom atic battery switchover in bus

powered systems

• Ve ry low-power mode (sub-µA) with

push-button ON/OFF switch input with

de-bounce

• P r ovides 3. 3 V / 40 mA pow er to external

circuitry (host processor or peripheral circuit s)

• The inductor-base d D C-DC co nverter provides

higher current and efficiency than usual

charge-pump capacitor-based converter s:

 Ideal for battery-powered applications

73S 8009C Dat a Sheet DS_8009C_025

2 Rev. 1.5

FEATURES

• Smart card Interface:

• Complies with ISO-7816-3 a n d EM V 4.1

and d er ivative standar ds

• A DC-DC Converter provides 1.8 V/3 V/5 V

t o the ca r d from a wide r ange of exter nal

power supply inputs

• P r ovides up t o 65 mA to the car d

• ISO-7816-3 Card emergency deacti vation

sequencer

• 2 volt age supervisor s detect voltage d r ops

on the VCC (card) and VDD ( dig i tal ) power

supplies

• Card over-cur r ent detection 150 mA max.

• 2 car d detecti on inputs, 1 for either use r

polarity

• Auxiliary I/O lines for synchronous and

ISO-7816-12 USB card su pport

• Card CLK clock frequency up to 20 MHz

• 6 kV ES D and short circuit protecti on on

t he card interface

• S ystem Controll er Interface:

• 5 S ign al images of the card signals

(RSTIN, CLKIN, I/OUC, AUX1UC and

AUX2UC)

• 2 In puts activate and select the card

vol tage (CMDVCC% and CMDVCC#)

• 2 Outputs, interrupt to the system controller

(OFF and RDY) , to inform the system

control ler of t he card presen ce / fau l ts and

status of the interface

• 1 Chip S elect input

• 2 Handshaking signals for proper shutdown

sequencing of all output supply voltages

(OFF_REQ, OFF_ACK)

• ON/OF F Mai n Sy st e m Sw itch:

• I nput for an SPS T momentary switch to

ground

• DC-DC Conve rter:

• Step-up co nverter

• G ener ates an in termediary volt age VP

• Requir es a single 10 µH Inductor

• S ystem P ower Sup ply req ui r emen ts:

• When using VB U S: Stand ar d US B +5

input (range +4.4 V to 5.5 V)

• When using V BAT: 4.0 V to 6.5 V

• When using V PC: 2.7 V to 6.5 V

• A utomated detecti on of vo lt age presence -

Priority on VBUS over VBAT

• Power Supply Output:

• VDD su pply output available to power up

external circuitry: 3.3 V ±0.3 V, 40 mA

• I ndustrial temper ature r ange

• S mall format QF N package

• RoHS compliant (6 /6) lead-free packag e

73S 8009C Dat a Sheet DS_8009C_025

Rev. 1.5 3

FUNCTIONAL DI AGRAM

Pin numbers reference the QFN32 package.

Figure 1: 73S8009C Block Di agram

SMART CARD I/O BUFFERS

AND SIGNAL LOGIC

SWITCH/LDO

REGULATOR

VOLTAGE

REFERENCE

CONTROL

LOGIC

RESET

BUFFER

CLOCK

BUFFER

R-C

OSC.

VCC FAULT

VPC FAULT

1.5MHz

VDD VBUS

VCC

RST

CLK

PRES

I/O

AUX1

AUX2

CLKIN

I/OUC

AUX1UC

AUX2UC

RSTIN

RDY

GND

OFF

TEST2

bias currents

vref

GND

VBAT

VPC

LIN

VCC OK

VCC = 3

VCC = 5

POWER DOWN

ON/OFF

ON_OFF S2 S1

OFF_REQ

OFF_ACK

CS TEST1

3010

12 29 25 23

CMDVCC5

CMDVCC3

73S 8009C Dat a Sheet DS_8009C_025

4 Rev. 1.5

Table of Contents

1 Pinout ............................................................................................................................................. 6

2 Electrical Specifications .............................................................................................................. 10

2.1 Abso lu te Maximum Ratings ................................................................................................... 10

2.2 Recommend ed Operating C ondit i ons .................................................................................... 11

2.3 Smar t Car d Interface Requiremen ts ...................................................................................... 11

2.4 Digital S ign als Characteristics ............................................................................................... 14

2.5 DC Characteristics ................................................................................................................ 15

2.6 Voltage / Tem per ature Fault Detecti on C ircuits ...................................................................... 15

2.7 Th er mal Char acteristics ........................................................................................................ 15

3 Applic ations Informa ti on ............................................................................................................. 16

3.1 Example 73S8009C Schematics ........................................................................................... 16

3.2 Power Suppl y and Convert er ................................................................................................. 18

3.3 Interface Fu nction - ON/OFF Modes ...................................................................................... 18

3.4 System C ontrol ler In terface ................................................................................................... 20

3.5 Card P ower Supply an d Vol tage Supervision......................................................................... 20

3.6 Activation and D e-activation Sequence ................................................................................. 21

3.7 OFF an d Fau lt D etection ....................................................................................................... 22

3.8 Chip Selection ....................................................................................................................... 23

3.9 I/O Circuit ry and Timing......................................................................................................... 24

4 Equivalent Circuits ...................................................................................................................... 26

5 Mechanical Draw in g .................................................................................................................... 30

6 Order i ng Informa tion ................................................................................................................... 31

7 Related Documentation ............................................................................................................... 31

8 Contact Information ..................................................................................................................... 31

DS_8009C_025 73S80 09C Data Sheet

Rev. 1.5 5

Figures

Figure 1: 73S8009C Block Diagram ......................................................................................................... 3

Figure 2: 73S8009C 32-Pin QFN Pinout .................................................................................................. 6

Figure 3: Typical 73S8009C Application Schematic ............................................................................... 17

Figure 4: 73S8009C Logical Block Diagram ........................................................................................... 19

Figure 5: Activation Sequence ............................................................................................................... 21

Fi gur e 6: Deactivation Sequence ........................................................................................................... 22

Figure 7: OFF Activity ............................................................................................................................ 22

Fig ure 8: CS Timing Definit ions .............................................................................................................. 23

Fi gur e 9: I/O and I/O UC Stat e D iagram .................................................................................................. 24

Fi gure 1 0: I/O – I/OUC Delays - Timing Diagram .................................................................................... 25

Figure 11: On_Off Pin ............................................................................................................................ 26

Fi gur e 12: Open Drai n type – OFF and RDY .......................................................................................... 26

Figure 13: Power Inpu t/Output Circuit, VDD, LIN, V PC, VCC, VP ........................................................... 26

Fig ure 14: Smart Card CLK Driver Circu it .............................................................................................. 27

Fig ure 15: Smart Card RST Driver Circuit .............................................................................................. 27

Fi gur e 16: Smart Car d IO, A UX 1, and AUX2 Interface C ircuit ................................................................. 28

Fig ure 17: Smart Card I/OUC, AUX1UC and AUX2UC Interface Circuit .................................................. 28

Figure 18: General Input Circuit ............................................................................................................. 29

Fi gur e 19: OFF _REQ Inte r face Ci r cui t ................................................................................................... 29

Fi gur e 20: 32-P i n QF N Package Dimensions ......................................................................................... 30

Tables

Table 1: 73S8009C Pin Definitions .......................................................................................................... 7

Tabl e 2: Absolut e M aximum Device R ati ngs .......................................................................................... 10

Tabl e 3: Recommended Operating C ondit i ons ....................................................................................... 11

Tabl e 4: DC S mart Card Interface R equirements ................................................................................... 11

Table 5 : Digital Sig nals Ch aracterist ics .................................................................................................. 14

Table 6 : DC Characterist ics ................................................................................................................... 15

Tabl e 7: Voltage / Temper ature Fault Detection Circuit s ......................................................................... 15

Tabl e 8: Ther mal Char acteristics ........................................................................................................... 15

Tabl e 9: Order N umb er s and Packaging Mar ks ...................................................................................... 31

73S 8009C Dat a Sheet DS_8009C_025

6 Rev. 1.5

1 Pinout

The 73S8009C is supplied as a 32-pin Q FN pa ckage .

Figure 2: 73S8009C 32-Pin QFN Pinout

LIN

VPC

RDY

PRES

I/O

ON_OFF

VBUS

GND

VDD

RSTIN

OFF_ACK

AUX2

AUX1

GND

CLK

RST

VCC

TERIDIAN

73S8009C

TEST1

CLKIN

VBAT

AUX2UC

AUX1UC

I/OUC

PRES

CMDVCC5

CMDVCC3

OFF_REQ TEST2

GND

OFF

DS_8009C_025 73S80 09C Data Sheet

Rev. 1.5 7

Tabl e 1 describes the pin functions for the device.

Table 1: 73S8009C Pin Defi ni ti ons

Name Pin

(QFN32) Type Equivalent

Circuit Description

Card Interface

I/O 22 IO Figure 16 C ar d I/O : Data signal to/from card. Includes a pul l-up

resistor to VCC.

AUX1 21 IO Figure 16 A UX 1: Auxili ary data signal to/ from car d. Incl udes a

pull-up resistor to V CC.

AUX2 20 IO Figure 16 A UX 2: Auxili ary data signal to/ from car d. Incl udes a

pull-up resistor to V CC.

RST 18 O Figure 15 C ar d reset: pr ovides reset ( RS T) signal to ca r d. RST is

the pass through signal on RSTIN. Internal control logic

will hold RST low when card is not act ivated or VCC is

t oo l ow.

CLK 16 O Figure 14 Card clock: provides cl ock signal (CLK) to ca r d. CL K i s

t he pass through of the sign al on pin CLKIN. Int er nal

control log ic will hold CLK low wh en card is not

activated or VCC i s too low.

PRES 14 I Figure 18 C ar d Presence swi tch: active h igh indicat es ca r d i s

present. Should be tied to GND when not used, but it

Includes a high-impe da nce pull -down current source.

PRES 13 I Figure 18 C ar d Presence swi tch: active low in dicates card i s

present. Sho uld be ti e d to VDD when not used, but it

Includes a high-impe da nce pull -up current so ur ce.

VCC 19 PSO Figure 13 Card power supply – logicall y co ntrol led by sequencer ,

out put of LDO regulator. R equi r es an external 0. 47 µF

low ES R filter capacit or to G ND.

GND 17 GND – Card ground.

Miscellaneous Inputs and Outputs

CLKIN 7 I Figure 18 Clock si gnal source for the ca r d clock.

TEST1 10

–

Factory test pin. This pin must be tied to GND in

typical application s .

TEST2 30

–

Factory test pin. This pin must be tied to GND in

typical application s .

Power Supply and Ground

VDD 29 PSO Figure 13 S ystem in terface suppl y volt age and supply voltage for

comp anion controll er cir cuitry. R equires a minimum of

two 0.1 µF capacit or s t o gr ound for proper decoupli ng.

VPC 26 PSI Figure 13 P ower sup pl y so ur ce for main voltage co nverter circuit.

A 10 µF a nd a 0.1 µF cer amic capacitor must be

connected to this pin.

VBAT 25 Alternate power source i nput, t ypicall y from two series

cells, V > 4 V.

73S 8009C Dat a Sheet DS_8009C_025

8 Rev. 1.5

Name Pin

(QFN32) Type Equivalent

Circuit Description

VBUS 23 A l ternate powe r source i nput from U SB connector or

hub.

LIN 27 PSI Figure 13 Connection t o 10 µH inductor for i nternal step up

converter. Note: inductor m ust be rated for 400 m A

maximum peak cur r ent.

VP 15 PSO Figure 13 Int er med iat e output of main co nverter circuit. Requir es

an external 4.7 µF low ESR filter capacitor to GND.

GND 28,31 – Ground.

M icrocontroller Interface

CS 12 I Figure 18

When CS = 1, the control and signal pins are configured

normal l y. When CS is se t low, CMDVCC%, RSTIN, and

CMDVCC# are l atched . I/OUC, AUX1 UC, and

A UX 2UC are set to high-im pedance pull -up mode and

do not pass data to or from the smart car d. Signal s

RDY an d OFF ar e disabl ed to prevent a l ow out put and

t he i nternal pull-up resistors are di sconnected.

OFF 32 O Figure 12 Interrupt signal to th e pr ocessor. Acti ve Low - Multi-

fu nction indi cating fault condit i ons and car d pr esence .

Open drain output configuration – It includes an internal

20 kΩ pull-up to VDD. Pull-

up is disabled in Power down

state and CS = 0 modes.

I/OUC 1 IO Figure 17 System con troller data I/ O to/from th e card. Incl udes a

pull-up resistor to V DD.

AUX1UC 2 IO Figure 17 System con troller auxiliary d ata I/O to/from the car d.

Includes a pul l-up r esistor to V DD.

AUX2UC 3 IO Figure 17 System con troller auxiliary d ata I/O to/from the car d.

I ncludes a pu ll-up resistor to VDD.

CMDVCC%

CMDVCC# 4

5 I

I Figure 18 L ogi c low on one or both of t hese pins will ca use the

LDO t o r am p the Vcc su pply to the sm ar t ca r d and

smart card i nterface to the value described i n the

following table.

CMDVCC% CMDVCC# Vcc Ou tput Voltage

0 0 1.8 V

0 1 5.0 V

1 0 3.0 V

1 1 LDO Of f

Note: See the descript ion of the Card Power Supply for

more detail on the operation of CMDVCC% and

CMDVCC#.

RSTIN 6 I Figure 18 Reset I nput: This sign al is the r eset command to the

card.

RDY 8 Figure 12 Signal to control ler indi cat ing th e 73S8009C is r eady

because V CC is above t he r equi r ed value after

CMDVCC% and/or CMDVCC# i s asserted low. A 20 kΩ

pull-up resistor to V DD is provid ed internally. Pu ll-up is

disabled in Power down state and CS=0 modes.

DS_8009C_025 73S80 09C Data Sheet

Rev. 1.5 9

Name Pin

(QFN32) Type Equivalent

Circuit Description

ON_OFF 24 I Figure 11 Power cont r ol pin. Connected to normally open SPS T

switch to ground. Closing switch for durati on greater

tha n de -

bounce period will turn 73S8009C circuit “on.”

If 73S8009C is “on,” closing switch will turn 73S8009C

t o “ off” state after the d e-bounce per i od and

OFF_REQ/OFF_ACK handshake.

OFF_REQ 11 O Figure 19 D igital output . Req uest to the host system co ntrol l er to

turn the 73S8009C off. If ON_OFF switch is closed (to

ground) for de-bounce duration and circuit is “on,”

OFF_REQ will go high (Request to turn OFF).

Connected to OFF_A CK via 100 kΩ int er nal r esistor.

OFF_ACK 9 I Figure 18 S etting OF F_A CK high will power “off” all analog

functions and disconnect the 73S8009C from VBAT or

VPC. The pin has an internal 100 kΩ resistor

connection to O FF_REQ so th at when not co nnected or

no host interaction is requir ed, the Acknowled ge will be

true and the circuit will turn “off” imm ediately with

OFF_REQ.

73S 8009C Dat a Sheet DS_8009C_025

10 Rev. 1.5

2 Electrical Specifications

This section provides the following:

 Absolute maximum ratings

 Reco mmended ope r a ti ng conditi o ns

 S mart car d in terface requirement s

 Digital signals charact erist ics

 V olt age / temperature fault detecti on circuits

 Thermal characteristics

2.1 Absolute Maximum Ratings

Table 2 lists th e m aximu m oper ati ng conditions for the 73S8009C. Permanent device damage may occur

if absolut e maximu m r ati ngs are exceeded. E xposure t o the extr emes of the absolut e m aximum r ati ng for

extended peri ods may affect d evice reli ability. The smart card i nterface pi ns are protected agai nst short

circuits to VCC, gr ound, and each ot her.

Table 2: Absolute Maximum Device Ratings

Parameter Rating

S upply Voltage VBUS -0.5 t o 6. 6 VD C

S upply Voltage VBAT -0.5 t o 6. 6 VD C

S upply Voltage VPC -0.5 t o 6. 6 VD C

VDD -0.5 t o 4. 0 VDC

I nput Voltage for Di git al Inputs -0.3 to (VDD +0.5) VDC

S torage Temperature -60 to 150° C

P in V olt age ( except ca r d int er face ) -0.3 to (VDD + 0.5) VDC

P in V olt age ( card interface) -0.3 to (VCC + 0.3) VDC

Pin Voltage, LIN pin 0. 3 to 6.5 VDC

ESD Tolerance – C ar d i nterface pins +/- 6 kV

E SD Tolerance – Other pins +/- 2 kV

Pin Current, except LIN ± 20 0 m A

Pi n Cur r ent, LIN + 500 mA in, -200 mA out

Note: ESD testing on sm ar t ca r d pi ns is HBM condition, 3 pulses, each p olarity refe r enced t o gr ound.

Note: Smart Card pins are protected agai nst shor ts between any co mb in ati ons of S mart Card pins.

DS_8009C_025 73S80 09C Data Sheet

Rev. 1.5 11

2.2 Recommended Operating Conditions

Funct i on oper ation should be r estricted to the recommended operating conditions specified i n Table 3.

Table 3: Recommended Opera ting Conditions

Parameter Rating

S upply voltage VPC 2. 7 to 6.5 VDC

S upply Voltage VBUS 4. 4 to 5.5 VDC

S upply Voltage VBAT 4.0 t o 6.5 VDC

Ambient operating temperature -40 °C to +85 °C

2.3 Smart Card Interface Requirements

Table 4 lists the 73S8009C Smar t Car d i nterface requir emen ts.

Table 4: DC Smart Card Interface Requirements

Symbol Parameter Condition Min Nom Max Unit

Card Power Supply (V CC) Regulator

Ge neral Conditions: -4 0C < 85C , 2.7 V < VPC < 6.6 V

VCC Card supply voltage

including ripple and noise

I nactive mode -0.1

–

0.1 V

I nactive mode I CC = 1 mA -0.1

–

0.4 V

A ctive mode; ICC <65 mA; 5 V 4.65

–

5.25 V

A ctive mode; ICC < 65 mA; 3 V 2.85

–

3.15 V

A ctive mode; ICC < 40 mA; 1.8 V 1.68

–

1.92 V

A ctive mode; si ngl e pulse of

100 mA for 2 µs; 5 V, fixed load

= 2 5 mA

4.6

–

5.25

A ctive mode; si ngl e pulse of

100 mA for 2 µs; 3 V, fixed load

= 2 5 mA

2.76

–

3.15 V

A ctive mode; curr ent pul ses of

40nAs with peak |ICC | <200

mA, t <400 ns; 5 V

4.6

–

5.25 V

A ctive mode; curr ent pul ses of

40nAs with peak |ICC | <200

mA, t <400 ns; 3 V

2.7

–

3.15 V

A ctive mode; curr ent pul ses of

20nAs with peak |ICC | <100

mA, t <400 ns; 1.8 V

1.62

–

1.92 V

CCrip

ripple f

RIPPLE

= 2 0 kHz – 200 MHz

–

350 mV

ICCmax Card supply output

current St ati c load current, V

>1.65

–

40 mA

S tatic load current, V CC> 4.6 or

2. 7 volts as selected

–

65 mA

ICCF ICC fault current Class A, B (5 V and 3 V) 75

–

150 mA

Class C (1.8 V) 55

–

130 mA

ISC Maximum current pri or to

shut-down Load cur r ent limit pri or to Vcc

shut-down 80 – 150 mA

Load current limit prior to Vcc

shut-down for Vcc=1.8 V 60 – 130 mA

VS V cc sl ew rat e, rise and

fall C = 0.5 µF 0.10 0.30 0.70 V/μs

73S 8009C Dat a Sheet DS_8009C_025

12 Rev. 1.5

Vrdy Vcc ready voltage (RDY

= 1 ) 5 V operation, Vcc rising 4.6

–

3 V oper ation, Vcc ri sing 2.75

–

1.8 V operation, Vcc ri sing 1.65

–

VCCF RDY = 0

(VCC voltage sup er visor

threshold)

VCC = 5 V

–

4.6 V

VPC

E xternal filt er cap fo r V

8.0

10.0

12.0

µF

Cvp External filter cap for VP 2.0 4.7 6.8 µF

CF External filt er capacit or

(VCC to GND) CF should b e ceramic with low

ESR (<100 mΩ). 0.2 0.47 1.0 µF

CVDD VDD filter capacit or 0.2 – 1.0 µF

Ivpcoff VPC supply current for

Vcc=0 Vpc= 5 V, Vcc=0 V (off) 400 µA

DS_8009C_025 73S80 09C Data Sheet

Rev. 1.5 13

Symbol Parameter Condition Min Nom Max Unit

I nter f ace Re quirements – Data Signals: I/O, AUX1, AUX2, and host interfaces: I/OUC, AUX1UC,

AUX2UC, DP, DM. ISHORTL, ISHORTH, and VINACT requi rements do not pe r tain to I/OUC, AUX1 UC, AUX2UC

VOH Output level, high (I/O,

AUX1, AUX2) IOH =0 0.9 * VCC

–

VCC+0.1 V

VOH Output level, high (I/OUC,

AUX1 UC, AUX2 UC) IOH = -40 µA 0.7 5 VCC

–

VCC+0.1 V

=0 0 .9 V

–

+0.1 V

VOL O utput level, low (I/O,

AUX1, AUX2) IOH = -40 µA 0.7 5 VDD

–

VDD+0.1 V

=1 mA

–

0.15 *V

VOL Output level, low (I/OUC,

AUX1 UC, AUX2 UC) IOL=1 mA

–

0.3 V

VIH Input leve l, high (I/O,

AUX1, AUX2) 0.6 * VCC

–

VCC+0.30 V

VIH Input leve l, high (I/OUC,

AUX1 UC, AUX2UC) 0.6 * VDD

–

VDD+0.30 V

VIL Input leve l, low (I/O,

AUX1, AUX2) -0.15

–

0.2 * VCC V

VIL Input leve l, low (I/OUC,

AUX1 UC, AUX2 UC) -0.15

–

0.2 * VDD V

VINACT Output voltage when

out side of se ssion IOL = 0

–

0.1 V

IOL = 1 mA

–

0.3 V

LEAK

Input leakage

= V

–

µA

IIL Input current, low (I/O,

AUX1, AUX2) VIL = 0

–

0.65 mA

IIL Input current, low (I/OUC,

AUX1 UC, AUX2 UC) VIL = 0

–

0.7 mA

ISHORTL Short circuit output

current For output low, shorted to

VCC th r ough 33 Ω

–

15 mA

ISHORTH Short circuit output

current For output high, shorted to

ground through 33 Ω

–

15 mA

tR, tF O utput rise time, fall

times Fo r I/O, AUX 1, AU X 2,

CL = 80p F, 10 % to 90% .

Fo r I/OUC , AUX1U C ,

AUX2UC, CL=50Pf, 10%

t o 90%.

–

100 ns

tIR, tIF I nput ri se, fall times

–

1 µs

RPU Internal pul l-up r esistor Output stable for >200ns 8 11 14 kΩ

FDMAX Maximum data rate – – 1 MHz

TFDIO Delay, I/O to I/OUC, AUX1

to AUX1UC, AUX2 to

AUX2UC,I/OUC to I/O,

AUX1UC to AUX1, AUX2UC

to AUX2 (respectively falling

edge to falling edge and

rising edge to rising edge)

E dge from master to

sl ave, measured at 50% 60 100 200 ns

TRDIO – 15 – ns

CIN Input cap acitance

–

10 pF

73S 8009C Dat a Sheet DS_8009C_025

14 Rev. 1.5

Symbol

Parameter

Condition

Min

Nom

Max

Unit

Reset and Clock for card interface, RST, CL K

VOH Output level, high IOH =-200 µA 0.9 * VCC

–

VCC V

VOL O utput level, low IOL=200 µA 0

–

0.15

VINACT Output voltage when

out side of se ssion IOL = 0

–

0.1 V

IRST_LIM Output current limit, RS T

–

30 mA

ICLK_LIM Output current limit, C L K

–

70 mA

tR, tF Output rise time, fall time CL = 35p F for CLK, 10% to

90%

–

12 ns

CL = 200pF for RST, 10% to

90%

–

100 ns

Duty cycle for CLK

CL =35pF, FCLK ≤ 20 MHz,

CLKIN duty cycle is 4 8% to

52%.

–

2.4 Digital Signals Characteristics

Table 5 lists the 73S8009C digital signals characteristics.

Table 5: Digital Signals Characteristics

Symbol

Parameter

Condition

Min

Nom

Max

Unit

Digital I /O

(exce pt for I/ OUC, AUX1UC, AUX 2UC; see

Smart Card Interface Requirements

for those specifications)

VIL I nput Low Vol tage -0.3

–

0.8 V

VILOFFACK Input low voltage for

OFF_AC K pin OFF_REQ pin = VDD -0.3

–

0.7 V

VIH I nput H i gh Vol tage 1.8

–

VDD + 0.3 V

VOL O utput Low Voltage IOL = 2 mA

–

0.45 V

VOH Output High Voltage IOH = -1 mA VDD - 0.45

–

OUT

Pull-up r esistor;

OFF,

RDY

kΩ

RACK Resistor betw een

OFF_RE Q and 0FF_ACK 70 100 130 kΩ

|IIL1| I nput Leaka ge C ur r ent G ND < VIN < VDD –

–

5 μA

tSL Time from CS goes h igh t o

interface active 50

–

tDZ Time from CS goes low to

interface inactive, Hi-Z 50

–

tIS Set-up t ime , co ntrol

sig nals to CS rising edge 50

–

Hold ti me, control signals

from CS risi ng edge

–

tID Set-up time, control

sig nals to CS fall 50

–

tDI Hold ti me, control signals

from C S fa ll

–

50 ns

DS_8009C_025 73S80 09C Data Sheet

Rev. 1.5 15

2.5 DC Characteristics

Table 6 lists the DC characteristics.

Table 6: DC Characteristics

Symbol

Parameter

Condition

Min

Nom

Max

Unit

VDD VDD Supply Voltage 2.7v < VPC < 6.5v, IVDDEXT <

40 mA. 3.0 3.3 3.6 V

IDDEXT VDD Curr ent to External

Load – – 40 mA

IVPC Supply Current

Vpc = 2.7V, V

off, I

= 0

–

1.7

–

Vpc = 3.3V, V

off, I

= 0

–

1.1

–

Vpc = 5.0V, VCC off, IDD = 0 – 0.7 – mA

OFF mode – 0.01 1 µA

VBUSON VBUS detecti on

threshold VDD =3.3 V 3.5 3.9 4.3 V

VBUSIDIS VBUS discharge

current 0.5 1.0 3 mA

VBUSSTBY VBUS standby current 370 500 µA

2.6 Voltage / Temperature Fault Detection Circuits

Table 7 lists th e voltage / t emp er ature faul t detection cir cuits.

Table 7: Voltage / Temperature Fault Detection Circuits

Symbol

Parameter

Condition

Min

Nom

Max

Unit

IVPmax VP over-current fault

–

150 mA

ICCF Card overcurrent fau lt 80

–

150 mA

ICCF1P8 Card overcurrent fau lt VCC = 1.8 V 60

–

130 mA

2.7 Thermal Characteristics

Table 8 lists the therm al characteristics.

Table 8: Ther mal Ch ar acterist ics

Symbol

Parameter

Condition

Min

Nom

Max

Unit

Tj Junction tem perature

–

– 125 °C

θ ja Th er mal Resistance,

Junction-to-Ambient

–

°C/W

θ jc Thermal Resistance,

Junction-to-case

–

°C/W

73S 8009C Dat a Sheet DS_8009C_025

16 Rev. 1.5

3 Applications Information

Thi s section provides gen er al usage i nformation f or the design and implementat i on of the 73S8009 C.

The documents listed in Relat ed D ocumentat ion provide more detai led information.

3.1 Example 73 S8009C Schematics

Figure 3 shows a typ i cal appl i cation schematic for the im pl ement ation of the 73S800 9C with a main

system switch. N ote that minor changes m ay occur to the reference mat er i al from t i me t o tim e and the

reader i s encour aged to co ntact Teridian f or the latest information.

DS_8009C_025 73S8009 C Data Sheet

Rev. 1.5 17

CLKIN_from_uC

0.47µF,

OFF_ACK_from_uC

OFF_interrupt_to_uC

CLK track should be routed

far from RST, I/O, C4 and C8

NOTES:

1) VBUS = 4.5V to 5.5V DC.

2) VPC = 2.7V to 6.5V DC (should only be used when V

BAT

and

BUS

are unused)

3) VBAT = 4.0V to 6.5V DC.

4) Internal pull-up allows it to be left open if unused.

I/OUC_to/from_uC

Card detection

switch is

normally closed

VDD

AUX1UC_to/from_uC

AUX2UC_to/from_uC

RSTIN_from_uC

Low ESR (<100 M? )

should be placed near the

SC connecter contact

CS_from_uC

CMDVCC%_from_uC

20K

Smart Card Connector

VCC

RST

CLK

GND

VPP

I/O

SW-1

SW-2

See

NOTE 4

CMDVCC#_from_uC

RDY_status_to_uC

See NOTE 2

OFF_REQ_to_uC 0

4.7µF

27pF

See

NOTE 5

5) Resistor footpring is included in case some filtering is needed on CLK

32 QFN73S80009C

TEST1

GND

VPC

CLKIN

AUX2

RDY

PRES

I/O

AUX1

VBUS

CLK

RST

VCC

TEST2

CMDVCC%

RSTIN

VDD

GND

OFF

AUX2UC

AUX1UC

I/OUC

CMDVCC#

OFF_ACK

OFF_REQ

ON/OFF

VBAT

LIN

GND

VBAT 10µF

10µH

VDD

VBUS

Pushbutton Switch

SW1

See NOTE 3

See NOTE 1

VDD_supply_to_uC

See

NOTE 6

See

NOTE 6

6) Capacitors C4 and C5 are provisional and their footprints should be added

for added noise rejection if necessary.

7) Inductor must be rated for 400 mA maximum peak current.

See NOTE 7

8) V

- 3.3V, +/- 0.3V, 40mA max. Requires min two 0.1µF caps to gnd)

See NOTE 8C6

0.1µF

Figure 3: Typical 73S8009C Application Sc hema tic

73S 8009C Dat a Sheet DS_8009C_025

18 Rev. 1.5

3.2 Power Supply and Converter

The power suppl y and converter circuit t akes power from any on e of three so ur ces; VPC, VBUS, and VBAT.

VPC is specified to range from 2.7 to 6.5 volts and would typically be supplied by a single cell battery with

a vol tage range of 2.7 t o appr oximatel y 3. 1 volts. VPC i s also ap pr opr iat e for system su ppl ies of 3.3 or 5

volts. VBUS i s t ypically sup pl ied by a connected USB cable and ranges in value from 4.5 t o 5.5 volts

(6.5 V ma xi mu m) . VBAT i s exp ected t o be supplied from a b attery of tw o series con nected cells with a

voltage value of 4.0 V to 6.5 V. VBAT and VBUS are co nnected to VPC by two FET switches configured as

an SP DT switch (break-before-m ake). They are not en abled at the same t i me. VBUS i s aut omatical ly

sel ected in l i eu of VBAT when VBUS i s pre sent. If VPC is provided and VBAT or VBUS are also used, the

sour ce of V PC mu st be diod e isol ated from the VPC pi n to prevent current flow from V BAT or VBUS i nto the

VPC source.

The power supplied to the VPC is up-co nverted to t he voltage V P uti l izi ng an i nductive, step -up co nverter.

A series power inductor (nominal value = 10 µH) i s connected from VPC t o LIN , and a 10 µF filt er capaci tor

plus a 0. 1 µF capacitor must be connected to V PC. VP requires a 4.7 µF filter capaci tor and will have a

nominal value of 5.5 V dur i ng nor mal operation. VP is used by t he smartca r d in terface ci r cuits (CLK, RST,

I O, AUX1, and AU X2) and i s the source of t he r egul ated smart car d supply V CC. VCC can be program med

for val ues of 5 V , 3 V, and 1.8 V. VDD i s also produce d from V P. VDD is used by the 73S8009C circuit for

logic, input/ output buffer ing, and anal og functi ons as well as being ca pable of supplying up to 40 mA of

cur r ent to external devices. Figure 4 shows t he bl ock diag r am of the 73S8009C.

3.3 Po wer ON /OFF

When no power i s appli ed to the VBUS pin, a power ON/OFF function is provided such that the circuit will

be inoperative during the “OF F” state, consumi ng minimum current from VPC and VBAT. If VBUS power is

supplied, the functions of the ON/OFF switch and circuitry are overridden and the 73S8009C is in the

“ON” state with VP and VDD avail abl e. Wit hout VBUS applied, and in the OFF state, the circuit responds

only to the ON_OFF pin. The ON_OFF pin shal l be connected to a SPS T switch to ground. If the cir cuit

is OF F and th e swi tch is closed for a de-bounce period of 50-100ms, the circuit shall go into the “ON”

state wherein all functions ar e oper ating i n nor mal fashi on. If t he circuit is in the “ON” stat e and the

ON_OF F pin is co nnected to ground for a per i od gr eater than the de-bounce period, OFF_REQ will be

asserted high and held. Typically, the OFF_REQ signal is presented to a host controller that will assert

OFF_ACK high when it has completed all shu tdown activities. Wh en OFF_ACK is set high, the circu it will

de-activat e the smart car d int er face if required and turn off all analog functions and the VDD sup pl y for the

logic and com panion ci r cuits. The O FF_AC K pin is connected in ternal l y to O FF_R EQ wit h a resistor such

t hat if OFF_ACK is unconnected, the acti on of OFF_REQ will asser t OFF_A CK high. In this

configur ation, the circu i t shall go int o the “OFF” state immediately upon O FF_R EQ = 1. The default state

upon application of power is the “OFF” stat e unl ess power is suppl ied t o the VBUS supply. Note that at any

t i me, the co ntroller may assert OFF_A CK and the 73S8009C will go i nto the “OFF” state (wh en VBUS is

not pr esent .)

I f power is appl i ed to both VBAT and VBUS, the circuit will automatical ly consume p ow er from only the VBUS

source. The circuit will be uncondition ally “ON” when VBUS is applied. If t he VBUS sou r ce is removed, the

ci r cuit will swi tchover to the VBA T input supply and remain in the “ON” stat e. Th e cont r oller circuit

firmware is req ui r ed to assert OFF_ACK base d on no activit y or VBUS removal to reduce bat tery power

consumption. When operating from VBUS, and not calling for VCC, the ste p-up converter becomes a simple

sw itch connectin g VBUS to VP in or der to sa ve power. This condition i s appropri ate for the USB

“SUSPEND ” stat e. Th e U SB “SU SPEND ” stat e r equi r es t he power supply current to be less than 500 µA.

I n or der to obtain and meet this low cu r r ent l i mitat ion , the co m pani on cont r oller must be confi gur ed i nto a

power-down condition using less than 20 µA from VDD.

Note: When using the V BUS input as the sole power source for an ‘alway s on’ configuration

(ON_OFF input not use d), the OFF_ACK and ON_OFF inputs must be connected to ground.

DS_8009C_025 73S80 09C Data Sheet

Rev. 1.5 19

VPC

VDD

VBAT

3.5V

REF

VCC

LIN

ON/OFF

OFF_REQ

OFF_ACK

RDY

CMDVCC#

CMDVCC%

Delay

Circuit

3.3V Regulator

VCC Regulator

Linear/

DC - DC

Converter

V1.8

ThREF

V3.0

ThREF

V5.0

ThREF

Analog

Mux

Debounce

and Latch

OFF

SHUTDOWN

VBUS

10µF

0.47µF

4.7µF

10uH

I/O

RST

CLK

AUX1

AUX2

I/OUC

RSTIN

CLKIN

AUX1UC

AUX2UC

Card

Supply/

Control

Logic

PRES

GND GND GND

OFF

Card

I/O

Buffer

and

Signal

Logic

100K

0.1µF0.1µF

0.1µF

Figure 4: 73S 8009C Logica l Blo ck Dia gram

73S 8009C Dat a Sheet DS_8009C_025

20 Rev. 1.5

3.4 System Controller Interface

Four separate digi tal input s and t wo ou tputs al low dir ect control of the ca r d i nterface from the h ost:

 P in CS: Chip select control .

 Pin CMDVCC# and/or CMDVCC%: When l ow, starts an activation sequence.

 Pin RSTIN: controls the card RST signal.

 Pin RDY: Indicates when sm art card power supply is stable and r eady.

 Pin OFF: Indicator of card pr esence and any ca r d fault co ndit i ons.

I nterr upt output to the host: When the car d i s not activat ed, the OFF pin informs the host about the card

presence only (Low = No card in the reader, high = card inserted). When CMDVCC (#/% signal s) is/are

set low (card acti vat ion sequence r equested from the host), low level on OFF means a fault has b een

det ected (e.g . card removal during car d session, or voltage f ault , or thermal / over-current fault) that

aut omatically initiates a deactivation se quence. The smart car d pass through signals are enabled when

t he R DY conditi ons are met.

3.5 Card P o wer Sup ply a nd Volt ag e Super v i sio n

The 73S8009C smart car d i nterface I C in corporates an L DO voltage regul ator for the ca r d power suppl y,

VCC (VP to VCC conversion uses an internal LDO). The voltage output is controlled by the digital input

sequence of CMDVCC# and CMDVCC%. This r egulat or i s able to provide 1.8V , 3V or 5V ca r d voltage

sour ced from the V P power supply. Internal digital circuit r y is also powered by the VP power supply

(except for the ON/OFF circuitry which is powered from VPC). A card deacti vat ion sequence is forced

upo n f aul t detect e d by an ove r curr ent co ndi ti on or card removal event . Th e voltage regulator can provide

a car d current of 65 mA i n compl i ance with EMV 4.1 for 3-V and 5-V ca r ds and 40 mA for 1.8 V cards .

The signals CMDVCC# and CMDVCC% co ntrol t he turn-on, output volt age value, and t urn -off o f VCC.

When either signal i s asserted low, VCC will r amp to the selected value or if both signals ar e asserted low

(within 400ns of each other), VCC will ram p t o 1 .8 V. Th ese signals ar e edge tri gger ed. If CMDVCC% is

asserted low (t o command VCC to be 5 V) and at a much later time ( gr eater than 2 µs, typically),

CMDVCC# is asser ted l ow, it will be ign or ed ( and vice ver sa. )

A t the assertion ( lo w) of either or both CMDVCC (#/% signals), VCC will rise to the requested value. When

VCC rises to an acceptable value, and stays above t hat value for approximately 20 µs, RDY will b e set

high. App r oximately 510 µs after the fa ll of CMDVCC (#/%) , the circuit will check t he see if VCC is at or

above the required minimum value (indicated by RDY=1) and if not, will begin an em ergency deactivation

sequence. During the 510 µs t ime, car d removal, or de-assertion of CMDVCC (#/%) shall al so ini tiate an

emergency deactiva tion sequence. Th e cir cuit provides over-cur ren t protection and li mits Icc to 150 mA,

maximum for self-p r otection. W hen an over-current condition is sensed, the circuit will invoke a

de-activat i on sequence.

DS_8009C_025 73S80 09C Data Sheet

Rev. 1.5 21

3.6 Activ ati on an d De -a ctiv ati on Se que nc e

The host controller is fu lly responsibl e for the activation sequencin g of the sm ar t card signals CLK, RST,

I/O, AUX1 and AUX2. All these signals are hel d l ow by the 73S8009C when the card is in the de-

activated state. Upon car d activati on ( the fall of CMDVCC (#/%)), all the signals are held low by the

73S8009C until RDY goes high. The host should set the signals RSTIN, I/OUC, CLKIN, AUX1UC and

A UX 2UC low p r ior to activating the car d and al low RDY to go high before transitioni ng any of t hese

si gnals. In order to ini ti ate activation, the car d mu st be prese nt and OFF must be high.

CMDVCC5 or CMDVCC3

VCC

I/OUC

I/O

RDY

RSTIN

RST

CLKIN

CLK

Ignored

I/O, AUX1, AUX2, CLK, RST are held LOW until RDY = 1 and CMDVCCx = 0

I/O = I/OUC if RDY=1

CLK=CLKIN if RDY=1

RST = RSTIN if RDY=1

At t1 (50 ξs), if RDY=0 or overcurrent, circuit will de-activate (safety feature)

VCC valid

Figure 5: Activation Sequ ence

Deactivati on i s ini tiated ei ther by t he system co ntrol ler by sett ing b oth CMDVCC (#/%) high, or

aut omatical ly in the even t of hardware f aul ts or assertion of the O FF_AC K signal. Hard ware faults ar e

over-current, und er -vo lt age, and ca r d ext r action duri ng the session. The host can manage the I/O

signals, CLKIN, RSTIN, and CMDVCC (#/%) to creat e other de-acti vation se quences for non-emergency

situations.

The following steps show the deactivation sequence and the timing of the card control signals when the

system controll er sets the CMDVCC(x)B high:

1. RST goes low at the end of time t1.

2. De-assert CLK at the end of ti me t2 .

3. I/O goes low at t he end of time t3. Exit r ecept ion mode.

4. De-assert internal V CC_ON at th e end of time t4. Aft er a del ay, V CC is de-asserted.

Note: Since the 73S8009C does not control the waveshape of C LK (it is determined by the i nput form the

host CLKIN) , there i s no guarantee t hat the dut y cycle of the l ast CLK high pul se wi ll co nform t o duty

cycle requir emen ts d ur ing an emergency deacti vation.

73S 8009C Dat a Sheet DS_8009C_025

22 Rev. 1.5

CMDVCC

RST

CLK

I/O

VCC_ON

VCC

t1 t2 t3 t4 t5

Figure 6: Deact iv at i on Seq uenc e

3.7 OFF and Fault Detection

There ar e two d if ferent ca ses that the system cont r oller can monitor the OFF signal: to query regarding

t he card presence outside car d sessions, or for fault det ection durin g card sessions.

O utside a ca r d session: In th i s co ndi tion, CMDVCC (#/%) are always high, OFF is low if the ca r d i s not

prese nt, and high if the ca r d i s prese nt. Because it is out side a card se ssion, no faul t detection can occur

and it will not act upon the OFF signal. No deactivati on i s requir ed dur ing this time.

Duri ng a card se ssion: CMDVCC# and/or CMDVCC% is always low, and OFF falls low if the card is

extracted or if any fault detection is detected. At t he same time that OFF i s set l ow, the se quencer start s

t he deactivation pr ocess and the host sh oul d stop all transitions on th e signal lines.

Figure 7 shows the timi ng di agr am for the signals CMDVCC (#/%), PRES, and OFF dur ing a card session

and outsid e the ca r d session.

PRES

OFF

CMDVCC

VCC

outside card session within card session

OFF is low by

card extracted OFF is low by

any fault

within card

session

Figure 7: OFF Activity

DS_8009C_025 73S80 09C Data Sheet

Rev. 1.5 23

3.8 Chip S elect ion

The C S pi n al l ows mu lt i ple ci r cuits to operate i n parallel, driven from the same host control bus. When

CS is high, the pins RSTIN, CMDVCC%, CMDVCC# and CLKIN control the chip as described. The pins

I/ OUC, AUX1UC, and AUX2UC h ave 1 1 kΩ pull-up resistors and operate to t r ansf er data to t he smart

car d via I/O , AUX1, and AUX2 when the smart car d i s acti vated . Th e signal s OFF and RDY have 20 kΩ

pull-up resistors.

When CS goes l ow, the states of the pi ns RSTIN , CMDVCC%, CMDVCC, and CLKIN are latched and hel d

internally. The pull-up for pins I/OUC, AUX1UC, and AUX2UC become a very weak pull-up of

approximately 3 µA. No transfer of d ata i s possibl e between I/OUC, AUX1U C, AUX2UC and the

smart-card signals I /O, AUX 1, and AUX2. The signal s OFF and RDY ar e set to hi gh impedance and the

internal pull-up resistors of 20 kΩ are d i scon nected. With regard to de-activation, CS does not affect t he

operation of t he fault sensi ng circuits and card sense input.

OFF, I/OUC,

AUX1UC, AUX2UC

CONTROL SIGNALS

FUNCTIONAL HI-Z STATE

HI-Z STATE

Figure 8: CS T iming Definitions

73S 8009C Dat a Sheet DS_8009C_025

24 Rev. 1.5

3.9 I/O Circuitry and Timing

The states of t he I/O, AUX1, and AUX2 pin s are low after power on reset and they are in hi gh wh en the

activation se quencer turns on the I/ O reception state. See t he Activati on and D e-acti vation Sequence

section for mor e detail s on when the I/ O recept ion is en abl ed. Th e stat es of I/OUC , AUX1U C, and

A UX 2UC are hi gh after power on r eset .

Within a card se ssion and when the I /O recept i on stat e is turned on, the first I/O line on which a falling

edge is detected becomes the input I/O li ne and the other becomes the output I/O line. When th e input

I /O li ne r i sing edge i s det ected, then both I /O li nes return to th eir neut r al state. Figure 9 sh ows the state

diagram of how t he I/O and I/O UC lines ar e man aged to beco me input or out put.

Neutral

State

I/OUC

I/O

reception

I/OICC

Yes

No No

Yes

I/O

not I/OUC

I/OUC

not I/O

I/OUC I/O

yesyes

Figure 9: I/O and I/OUC Stat e Diagram

DS_8009C_025 73S80 09C Data Sheet

Rev. 1.5 25

The del ay bet w een the I/O signal s is shown in Figure 10.

I/O

I/OUC

tI/O_HL tI/O_LH tI/OUC_HL tI/OUC_LH

Delay from I/O to I/OUC: tI/O_HL = 100ns tI/O_LH = 15ns

Delay from I/OUC to I/O: tI/OUC_HL = 100ns tI/OUC_LH = 15ns

Figure 10: I/O – I/OUC D elays - Timing Diagram

73S 8009C Dat a Sheet DS_8009C_025

26 Rev. 1.5

4 Equivalent Circuits

Thi s section provides illustrations of ci r cuits equi valent to t hose descri bed i n the Pinout section.

ESD

VPC

24K

Figure 11: On_ Off Pin

VDD

STRONG

NFET

Data

From

circuit

Output

Disable

20K

ESD

Figure 12: Open Drain type – OFF and RDY

ESD

Internal

circuits

Figure 13: Power Input/Output Circ uit, VDD, LIN, VPC, VCC, VP

DS_8009C_025 73S80 09C Data Sheet

Rev. 1.5 27

CLK

VCC

VERY

STRONG

PFET

VERY

STRONG

NFET

From

circuit

ESD

Figure 14: Smart Card CLK Driver Circuit

RST

VCC

STRONG

PFET

STRONG

NFET

From

circuit

ESD

Figure 15: Smart Card RST Driver Circuit

73S 8009C Dat a Sheet DS_8009C_025

28 Rev. 1.5

400ns

DELAY

VCC

STRONG

PFET

STRONG

NFET

RL=11K

From

circuit

CMOS

circuit

ESD

Figure 16: Smart Card IO, AUX1, and AUX2 Interface Circuit

400ns

DELAY UC

VDD

STRONG

PFET

STRONG

NFET

RL=11K

From

circuit

CMOS

circuit

ESD

Figure 17: Smart Card I/OUC, AUX1 UC and AUX2 UC Interface Circuit

DS_8009C_025 73S80 09C Data Sheet

Rev. 1.5 29

VDD

TTL

circuit

Pull-up

Disable VERY

WEAK

PFET

ESD

VERY

WEAK

NFET

Pull-down

Enable

ESD

Note: Pins CMDVCC%, CMDVCC#, CS have the pull-up enabled.

Pins RSTIN, CLKIN, PRES, EXT_RST have the pull-down enabled.

Pin OFF_ACK has a 100 kΩ resistor connected to pin OFF_REQ internally.

Figure 18: General Input Circuit

VDD

STRONG

PFET

STRONG

NFET

Data

From

circuit

OFF_ACK

pad

Output

Disable

ESD

100k ohm

Notes: Strong PFET or NFET is approximately 100 Ω.

Very strong PFET or NFET is approximately 50 Ω.

Medium strength PFET is approximately 1 kΩ.

Very weak PFET or NFET is approximately 1 MΩ.

The diodes represent ESD protection devices that will conduct current if forward biased.

Figure 19: OFF_REQ Interface Circuit

73S 8009C Dat a Sheet DS_8009C_025

30 Rev. 1.5

5 Mechanical Drawings

Figure 20: 32-Pin QFN Packa ge Dimensions

2.5

TOP VIEW

0.85 NOM.

0.9MAX. 0.00 / 0.005

0.20 REF.

SEATING

PLANE

SIDE VIEW

0.2 MIN.

0.35 / 0.45

1.5 / 1.875

3.0 / 3.75

0.18 / 0.3

BOTTOM VIEW

0.25

0.5

0.25

3.0 / 3.75

1.5 / 1.875

0.35 / 0.45

CHAMFERED

0.30

DS_8009C_025 73S80 09C Data Sheet

Rev. 1.5 31

6 Ordering Information

Table 9 lists th e or der num ber s and packaging mar ks u sed t o ident i fy 73S8009C products.

Table 9: Order Numbers and Packaging Marks

Part Description O rder Number Packaging Mar k

73S8009C-32QFN

32-pin Lead-Fr ee QF N 73S8009C-32IM/F 73S8009C

73S8009C-32QFN

32-pin Lead-Fr ee QF N Tape / Reel 73S8009C-32IMR/F 73S8009C

7 Related Documentation

The following 73S8009C document is available from Teri dian Semico nductor Corpor ati on:

73S8009C Data Sheet

73S8009C Demo Board User Manual

8 Contact Infor mation

For more information about Teridian Semico nduct or pr oduct s or to check the availabi l it y of the

73S8009C, co ntact us at:

6440 Oak Canyon Road

Suite 100

I r vine, CA 92618-5201

Telephone: (714) 508-8800

FAX : (71 4) 50 8-8878

E mail: scr.support@teridi an.com

For a compl ete list of worldwide sales of fi ces, go to http://www.teridian.com.

73S 8009C Dat a Sheet DS_8009C_025

32 Rev. 1.5

Rev isi on Histor y

Revision Date Description

1.0 2/15/2007 First publication.

1.1 12/5/2007 Replaced 32QFN punched with SAWN.

Updated 32QFN package mark.

1.2 1/21/2008 Changed the dimension of the bottom view 32-pin QFN package.

1.3 8/28/2009 Added Pin Current, LIN to Table 2.

Added Section 2.7, Ther mal Characteristics.

A dded a note to th e end of Section 3.6.

Added Section 4 , Equivalent Circuit s .

Added Section 7 R elat ed D ocumentat ion and Section 8 Contact Information

section.

Format ted to new docu ment ation style. M iscellaneous editori al changes.

1.4 1/5/2010 Chan ged the name of the “ON/OFF ” pin t o “ ON_OF F” throughout the

document.

In Figure 1, co r r ected t he name of the “IOUC ” pi n to “I/OUC” .

In Table 1, co r r ected the OFF_ACK name, pin number and typ e information.

In Table 7, changed “ IDDmax” to “IVPmax”.

A t the end of S ection 3.3, added a note about using VB US i nput.

In Section 3. 5, deleted “A voltage super visor checks the value of the voltage

VCC” and added “and 40 mA for 1. 8 V cards”.

1.5 2/4/2010 Removed all references to the 20Q FN package.

A dded C6 t o the schemati c in Figure 3.

Teridian Semiconductor C or por ation is a r egi stered trademark of Terid ian Semiconductor C or por ation .

A ll other trademar ks ar e the proper ty of their r espective own er s.

Simplifying System Integration is a t r ademark of Teridian Semiconduct or Corporation.

Thi s Data Sheet is propr iet ar y t o Teridi an Semico nductor Corpor ati on (TSC) and set s forth design goal s

for t he described product. Th e data sheet i s su bj ect t o change. TSC assumes no obli gation regarding

future manufacture, unless agreed to in writing. If and when manufactured and sold, this product is sold

subj ect t o the terms and condit i ons of sal e suppli ed at the t ime of order acknowledgment, including those

pertaining to war r anty, patent infringement and l i mitat ion of liabi l ity. Teridian Semi conductor C or por ation

(TSC ) r eserves the rig ht to make changes in speci fi cat ion s at any time without not ice. Accordi ngl y, t he

reader i s cauti oned to verify that a dat a sheet is cur r ent before placing ord ers. TSC assum es no liability

for app lica ti ons assistance.

Teridian Semiconductor C or p., 6440 O ak Canyon, Sui te 100, I r vine, CA 92618

TEL (714) 508-8800, FAX (714) 508-8877, http://www.teridian.com