ADC11DV200CISQ/NOPB - National Semiconductor

ADC11DV200

April 23, 2009

Dual 11-bit, 200 MSPS Low-Power A/D Converter with

Parallel LVDS/CMOS Outputs

General Description

The ADC11DV200 is a monolithic analog-to-digital converter

capable of converting two analog input signals into 11-bit dig-

ital words at rates up to 200 Mega Samples Per Second

(MSPS). The digital output mode is selectable and can be ei-

ther differential LVDS or CMOS signals. This converter uses

a differential, pipelined architecture with digital error correc-

tion and an on-chip sample-and-hold circuit to minimize die

size and power consumption while providing excellent dy-

namic performance. A unique sample-and-hold stage yields

a full-power bandwidth of 900MHz. Fabricated in core CMOS

process, the ADC11DV200 may be operated from a single

1.8V power supply. The ADC11DV200 achieves approxi-

mately 10.06 effective bits at Nyquist and consumes just

280mW at 170MSPS in CMOS mode 450mW at 200MSPS in

LVDS mode. The power consumption can be scaled down

further by reducing sampling rates.

Applications

■Digital Predistortion (DPD)

■Wireless Communications Infrastructure

■Medical Imaging

■Portable Instrumentation

■Digital Video

Features

■Single 1.8V power supply operation.

■Power scaling with clock frequency.

■Internal sample-and-hold.

■Internal or external reference.

■Power down mode.

■Offset binary or 2's complement output data format.

■LVDS or CMOS output signals.

■60-pin LLP package, (9x9x0.8mm, 0.5mm pin-pitch)

■Clock Duty Cycle Stabilizer.

■IF Sampling Bandwidth > 900MHz.

Key Specifications

■Resolution 11 Bits

■Conversion Rate 200 MSPS

■ENOB 10.06 bits (typ) @Fin=70MHz

■SNR 62.5 dBFS (typ) @Fin=70MHz

■SINAD 62.3 dBFS (typ) @Fin=70MHz

■SFDR 82 dBFS (typ) @Fin=70MHz

■LVDS Power 450 mW (typ) @Fs=200 MSPS

■CMOS Power 280 mW (typ) @Fs=170 MSPS

■Operating Temp. Range −40°C to +85°C.

Block Diagram

30087502

ADC11DV200 Dual 11-bit, 200 MSPS Low-Power A/D Converter with Parallel Outputs

Connection Diagram

30087501

Ordering Information

Industrial (−40°C ≤ TA ≤ +85°C) Package

ADC11DV200CISQ 60 Pin LLP

ADC11DV200CISQE 60 Pin LLP,

250 pc. Tape and Reel

ADC11DV200EB Evaluation Board

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ADC11DV200

Pin Descriptions and Equivalent Circuits

Pin No. Symbol Equivalent Circuit Description

ANALOG I/O

VINA+

VINB+

Differential analog input pins. The differential full-scale input

signal level is 1.5VP-P with each input pin signal centered on

a common mode voltage, VCM.

VINA-

VINB-

VRPA

VRPB

These pins should each be bypassed to AGND with a low ESL

(equivalent series inductance) 0.1 µF capacitor placed very

close to the pin to minimize stray inductance. An 0201 size 0.1

µF capacitor should be placed between VRP and VRN as close

to the pins as possible.

VRP and VRN should not be loaded. VRM may be loaded to 1mA

for use as a temperature stable 0.9V reference.

It is recommended to use VRM to provide the common mode

voltage, VCM for the differential analog inputs.

VRMA

VRMB

VRNA

VRNB

17 VREF

Reference Voltage select pin and external reference input.

The relationship between the voltage on the pin and the

reference voltage is as follows:

1.4V ≤ VREF ≤ VA The internal 0.75V reference is

used.

0.2V ≤ VREF ≤ 1.4V The external reference voltage is

used.

Note: When using an external

reference, be sure to bypass with

a 0.1µF capacitor to AGND as

close to the pin as possible.

AGND ≤ VREF ≤ 0.2V The internal 0.5V reference is

used.

19 REXT

Programming resistor for analog bias current. Nominally a

3.3kΩ to AGND for 200MSPS, or tie to VA to use the internal

frequency scaling current.

20 DF/DCS Data Format/Duty Cycle Correction selection pin.

(see Table 1)

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ADC11DV200

Pin No. Symbol Equivalent Circuit Description

DIGITAL I/O

CLK +

CLK -

Clock input pins signal. The analog inputs are sampled on the

rising edge of this signal. The clock can be configured for

single-ended mode by shorting the CLK- pin to AGND. When

in differential mode, the common mode voltage for the clock

is internally set to 1.2V.

PD_A

PD_B

Two-state input controlling Power Down.

PD = VA, Power Down is enabled and power dissipation is

reduced.

PD = AGND, Normal operation.

23 OUTSEL

Two-state input controlling Output Mode.

OUTSEL = VD, LVDS Output Mode.

OUTSEL = AGND, CMOS Output Mode.

LVDS Output Mode

24, 25

26, 27

28, 29

32, 33

34, 35

39, 40

41, 42

43, 44

47, 48

49, 50

51, 52

D0+,D0-

D1+, D1-

D2+, D2-

D3+, D3-

D4+, D4-

D5+, D5-

D6+, D6-

D7+, D7-

D8+, D8-

D9+, D9-

D10+, D10-

LVDS Output pairs for bits 0 through 10. A-channel and B-

channel digital LVDS outputs are interleaved. A channel is

ready at rising edge of DRDY and B channel is ready at the

falling edge of DRDY.

DRDY+

DRDY-

Data Ready Strobe. This signal is a LVDS DDR clock used to

capture the output data. A-channel data is valid on the rising

edge of this signal and B-channel data is valid on the falling

edge.

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ADC11DV200

Pin No. Symbol Equivalent Circuit Description

CMOS Output Mode

24-29,

32-35,51 DA0-DA10

Digital data output pins that make up the 11-bit conversion

result for Channel A. DA0 (pin 24) is the LSB, while DA10 (pin

51) is the MSB of the output word. Output levels are CMOS

compatible.

39-44,

47-50,52 DB0-DB10

Digital data output pins that make up the 11-bit conversion

result for Channel B. DB0 (pin 39) is the LSB, while DB10 (pin

52) is the MSB of the output word. Output levels are CMOS

compatible.

37 DRDYA

Data Ready Strobe for channel A. This signal is used to clock

the A-Channel output data. DRDYA is a SDR clock with same

frequency as CLK rate and data is valid on the rising edges.

38 DRDYB

Data Ready Strobe for channel B. This signal is used to clock

the B-Channel output data. DRDYB is a SDR clock with same

frequency as CLK rate and data is valid on the rising edges.

ANALOG POWER

8, 16, 18, 59,

60 VA

Positive analog supply pins. These pins should be connected

to a quiet source and be bypassed to AGND with 0.1 µF

capacitors located close to the power pins.

1, 4, 12, 15,

22, 55, 58, EP AGND

The ground return for the analog supply.

Exposed Pad (EP) must be soldered to AGND to ensure rated

performance.

DIGITAL POWER

21, 54 VD

Positive digital supply pins. These pins should be connected

to a quiet source and be bypassed to AGND with 0.1 µF

capacitors located close to the power pins.

31, 45 VDR

Positive driver supply pin for the output drivers. This pin should

be connected to a quiet voltage source and be bypassed to

DRGND with a 0.1 µF capacitor located close to the power

pin.

30, 46 DRGND The ground return for the digital output driver supply. This pin

should be connected to the system digital ground.

TABLE 1. Voltage on DF/DCS Pin and Corresponding Chip Response

Voltage on DF/DCS Results Suggestions

Min Max DF DCS

0 mV 200mV 1 1 2's complement data, duty cycle correction on Tie to AGND

250 mV 600 mV 0 0 Offset binary data, duty cycle correction off Leave floating

750 mV 1250 mV 1 0 2's complement data, duty cycle correction off

1400mV VA0 1 Offset binary data, duty cycle correction on Tie to VA

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ADC11DV200

Absolute Maximum Ratings (Notes 3, 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Supply Voltage (VA, VD VDR) −0.3V to 2.2V

Voltage on Any Pin

(Not to exceed 2.2V)

−0.3V to (VA +0.3V)

Input Current at Any Pin other

than Supply Pins (Note 4)

±25 mA

Package Input Current (Note 4) ±50 mA

Max Junction Temp (TJ) +150°C

Thermal Resistance (θJA)30°C/W

ESD Rating (Note 6)

Human Body Model 2500V

Machine Model 250V

Human Body Model 750V

Storage Temperature −65°C to +150°C

Soldering process must comply with National

Semiconductor's Reflow Temperature Profile

specifications. Refer to www.national.com/packaging.

(Note 7)

Operating Ratings (Notes 1, 3)

Operating Temperature −40°C ≤ TA ≤ +85°C

Supply Voltage (VA, VD, VDR) +1.7V to +1.9V

Clock Duty Cycle

(DCS Enabled) 30/70 %

(DCS disabled) 48/52 %

VCM 0.8V to 1.0V

Converter Electrical Characteristics

Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = VD = VDR = +1.8V, fCLK = 200 MHz,

CLK duty cycle = 50%, DCS = ON, Internal 0.75V Reference, LVDS Output. Typical values are for TA = 25°C. Boldface limits

apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = +25°C (Notes 8, 9)

Symbol Parameter Conditions Typical

(Note 10) Limits Units

(Limits)

STATIC CONVERTER CHARACTERISTICS

Resolution with No Missing Codes 11 Bits (min)

INL Integral Non Linearity 0.65 1.5

-1.5

LSB (max)

LSB (min)

DNL Differential Non Linearity 0.32 0.75

-0.65

LSB (max)

LSB (min)

PGE Positive Gain Error 0.57 ±3 %FS (max)

NGE Negative Gain Error 0.60 ±2.7 %FS (max)

TC PGE Positive Gain Error Tempco −40°C ≤ TA ≤ +85°C 13 ppm/°C

TC NGE Negative Gain Error Tempco −40°C ≤ TA ≤ +85°C 15 ppm/°C

VOFF Offset Error 0.1 ±0.55 %FS (max)

TC VOFF Offset Error Tempco −40°C ≤ TA ≤ +85°C 4 ppm/°C

Under Range Output Code 0 0

Over Range Output Code 2047 2047

REFERENCE AND ANALOG INPUT CHARACTERISTICS

VRM Common Mode Output Voltage 0.9 1

0.85

V (min)

V (max)

VCM Analog Input Common Mode Voltage 0.9 V

CIN

VIN Input Capacitance (each pin to

AGND) (Note 11)

VIN = 0.75 Vdc

± 0.5 V

(CLK LOW) 1 pF

(CLK HIGH) 2.5 pF

VRP Internal Reference Top 1.33 V

VRN Internal Reference Bottom 0.55 V

Internal Reference Accuracy (VRP-VRN)0.78 V

EXT

VREF

External Reference Voltage 0.5

1.0

V (Min)

V (max)

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ADC11DV200

Dynamic Converter Electrical Characteristics

Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = VD = VDR = +1.8V, fCLK = 200 MHz,

CLK duty cycle = 50%, DCS = ON, Internal 0.75V Reference, LVDS Output. Typical values are for TA = 25°C. Boldface limits

apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = +25°C (Notes 8, 9)

Symbol Parameter Conditions Typical

(Note 10) Limits

Units

(Limits)

(Note 2)

DYNAMIC CONVERTER CHARACTERISTICS, AIN = -1dBFS

FPBW Full Power Bandwidth (Note 16) -1 dBFS Input, −3 dB Corner 900 MHz

SNR Signal-to-Noise Ratio (Note 13)

fIN = 10 MHz, Vref = 0.75V 62.5 dBFS

fIN = 10 MHz, Vref = 1.0V 63.8 dBFS

fIN = 70 MHz, Vref = 0.75V 62.5 61.5 dBFS (min)

fIN = 70 MHz, Vref = 1.0V 63.7 dBFS

SFDR Spurious Free Dynamic Range (Note

14)

fIN = 10 MHz, Vref = 0.75V 82 dBFS

fIN = 10 MHz, Vref = 1.0V 82.4 dBFS

fIN = 70 MHz, Vref = 0.75V 82 71.5 dBFS (min)

fIN = 70 MHz, Vref = 1.0V 81.8 dBFS

ENOB Effective Number of Bits fIN = 10 MHz 10.06 Bits

fIN = 70 MHz 10.06 9.84 Bits (min)

H2 Second Harmonic Distortion fIN = 10 MHz -94 dBFS

fIN = 70 MHz -94 -71.5 dBFS (min)

H3 Third Harmonic Distortion fIN = 10 MHz -85 dBFS

fIN = 70 MHz -84 -71.5 dBFS (min)

SINAD Signal-to-Noise and Distortion Ratio

(Note 15)

fIN = 10 MHz 62.3 dBFS

fIN = 70 MHz 62.3 61 dBFS (min)

IMD Intermodulation Distortion (Note 16) fIN1 = 69 MHz AIN1 = -7 dBFS 93 dBFS

fIN2 = 70 MHz AIN2 = -7 dBFS

Cross Talk (Note 16) fIN1 = 69 MHz AIN1 = -1 dBFS 97 dBFS

fIN2 = 70MHz AIN2 = -1 dBFS

Power Supply Electrical Characteristics

Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = VD = VDR = +1.8V, fCLK = 200 MHz,

CLK duty cycle = 50%, DCS = ON, Internal 0.75V Reference, LVDS Output. Typical values are for TA = 25°C. Boldface limits

apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25°C (Notes 8, 9)

Symbol Parameter Conditions Typical

(Note 10) Limits Units

(Limits)

LVDS OUTPUT MODE

IAAnalog Supply Current Full Operation, Internal Bias 160 mA

Full Operation, External 3.3kΩ Bias 148 168 mA (max)

IDDigital Supply Current Full Operation 36 41 mA (max)

IDR Output Driver Supply Current 64 83 mA (max)

Power Consumption Internal Bias 473 mW

External 3.3kΩ Bias 450 525 mW (max)

Power Down Power Consumption PDA=PDB=VA57 mW

CMOS OUTPUT MODE (Note 12)

IAAnalog Supply Current Full Operation, Internal Bias 138 mA

Full Operation, External 3.3kΩ Bias 124

IDDigital Supply Current Full Operation 31 mA

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ADC11DV200

Symbol Parameter Conditions Typical

(Note 10) Limits Units

(Limits)

Power Consumption Internal Bias 310 mW

External 3.3kΩ Bias 280

Power Down Power Consumption PDA=PDB=VA60 mW

Input/Output Logic Electrical Characteristics

Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = VD = VDR = +1.8V, fCLK = 200 MHz,

CLK duty cycle = 50%, DCS = ON, Internal 0.75V Reference. Typical values are for TA = 25°C. Boldface limits apply for TMIN

≤ TA ≤ TMAX. All other limits apply for TA = 25°C (Notes 8, 9)

Symbol Parameter Conditions Typical

(Note 10) Limits Units

(Limits)

DIGITAL INPUT CHARACTERISTICS (PD_A,PD_B)

VIN(1) Logical “1” Input Voltage (Note 16) VA = 1.9V 0.89 V (min)

VIN(0) Logical “0” Input Voltage (Note 16) VA = 1.7V 0.67 V (max)

IIN(1) Logical “1” Input Current VIN = 1.8V 10.6 µA

IIN(0) Logical “0” Input Current VIN = 0V -7.6 µA

CIN Digital Input Capacitance 2 pF

LVDS OUTPUT CHARACTERISTICS (D0-D10,DRDY)

VOD LVDS differential output voltage (Note 16) 330 mVP-P

±VOD

Output Differential Voltage

Unbalance 0 50 mV

VOS LVDS common-mode output voltage (Note 16) 1.25 V

±VOS Offset Voltage Unbalance 50 mV

RLIntended Load Resistance 100 Ω

CMOS OUTPUT CHARACTERISTICS (DA0-DA10,DB0-DB10,DRDYA, DRDYB) (Note 12)

VOH Logical "1" Output Voltage VDR = 1.8V (Unloaded) 1.8 V

VOL Logical "0" Output Voltage VDR = 1.8V (Unloaded) 0 V

+IOSC Output Short Circuit Source Current VOUT = 0V -20 mA

-IOSC Output SHort Circuit Sink Current VOUT = VDR 20 mA

COUT Digital Output Capacitance 2 pF

Timing and AC Characteristics

Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = VD = VDR = +1.8V, fCLK = 200 MHz,

CLK duty cycle = 50%, DCS = ON, Internal 0.75V Reference. Typical values are for TA = 25°C. Timing measurements are taken

at 50% of the signal amplitude. Boldface limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25°C (Notes 8, 9)

Symbol Parameter Conditions Typical

(Note 10) Limits Units

(Limits)

LVDS OUTPUT MODE

Maximum Clock Frequency 200 MHz (max)

Minimum Clock Frequency DCS On

DCS Off 65

45 MHz (min)

tCH Clock High Time DCS On

DCS Off 1.5

2.4 ns (min)

tCL Clock Low Time DCS On

DCS Off 1.5

2.4 ns (min)

tCONV Conversion Latency 5/5.5

(A/B) Clock Cycles

tODA Output Delay of CLK to A-Channel Data Relative to rising edge of CLK 2.7 1.46 ns (min)

tODB Output Delay of CLK to B-Channel Data Relative to falling edge of CLK 2.7 1.46 ns (min)

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ADC11DV200

Symbol Parameter Conditions Typical

(Note 10) Limits Units

(Limits)

LVDS OUTPUT MODE

tSU Data Output Setup Time Relative to DRDY 1.2 0.7 ns (min)

tHData Output Hold Time Relative to DRDY 1.2 0.7 ns (min)

tAD Aperture Delay 0.7 ns

tAJ Aperture Jitter 0.3 ps rms

tSKEW Data-Data Skew 20 470 ps

CMOS OUTPUT MODE (Note 12)

Maximum Clock Frequency 170 MHz

Minimum Clock Frequency DCS On

DCS Off 65

25 MHz

tCH Clock High Time DCS On

DCS Off 1.76

2.82 ns

tCL DCS On

DCS Off 1.76

2.82 ns

tCONV Conversion Latency 5.5 Clock Cycles

tOD Output Delay of CLK to DATA Relative to falling edge of CLK 4.5 3.15

5.81

ns (min)

ns (max)

tSU Data Output Setup Time Relative to DRDY 2.5 1.79 ns (min)

tHData Output Hold Time Relative to DRDY 3.4 2.69 ns (min)

tAD Aperture Delay 0.7 ns

tAJ Aperture Jitter 0.3 ps rms

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is

guaranteed to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics.

The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under

the listed test conditions. Operation of the device beyond the maximum Operating Ratings is not recommended.

Note 2: Units of dBFS indicates the value that would be attained with a full-scale input signal.

Note 3: All voltages are measured with respect to GND = AGND = DRGND = 0V, unless otherwise specified.

Note 4: When the input voltage at any pin exceeds the power supplies (that is, VIN < AGND, or VIN > VA), the current at that pin should be limited to ±5 mA. The

±50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of ±5 mA to 10.

Note 5: The maximum allowable power dissipation is dictated by TJ,max, the junction-to-ambient thermal resistance, (θJA), and the ambient temperature, (TA), and

can be calculated using the formula PD,max = (TJ,max - TA )/θJA. The values for maximum power dissipation listed above will be reached only when the device is

operated in a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Such

conditions should always be avoided.

Note 6: Human Body Model is 100 pF discharged through a 1.5 kΩ resistor. Machine Model is 220 pF discharged through 0Ω resistor. Charged device model

simulates a pin slowly acquiring charge (such as from a device sliding down the feeder in an automated assembler) then rapidly being discharged.

Note 7: Reflow temperature profiles are different for lead-free and non-lead-free packages.

Note 8: The inputs are protected as shown below. Input voltage magnitudes above VA or below GND will not damage this device, provided current is limited per

(Note 4). However, errors in the A/D conversion can occur if the input goes above VA or below AGND.

30087511

Note 9: With a full scale differential input of 1.5VP-P , the 11-bit LSB is 732.8µV.

Note 10: Typical figures are at TA = 25°C and represent most likely parametric norms at the time of product characterization. The typical specifications are not

guaranteed.

Note 11: The input capacitance is the sum of the package/pin capacitance and the sample and hold circuit capacitance.

Note 12: CMOS Specifications are for FCLK = 170 MHz.

Note 13: SNR minimum and typical values are for LVDS mode. Typical values for CMOS mode are typically 0.2dBFS lower.

Note 14: SFDR minimum and typical values are for LVDS mode. Typical values for CMOS mode are typically 2dBFS lower.

Note 15: SINAD minimum and typical values are for LVDS mode. Typical values for CMOS mode are typically 0.1dBFS lower.

Note 16: This parameter is guaranteed by design and/or characterization and is not tested in production.

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ADC11DV200

Specification Definitions

APERTURE DELAY is the time after the falling edge of the

clock to when the input signal is acquired or held for conver-

sion.

APERTURE JITTER (APERTURE UNCERTAINTY) is the

variation in aperture delay from sample to sample. Aperture

jitter manifests itself as noise in the output. The amount of

SNR reduction can be calculated as

SNR Reduction = 20 x log10[½ x π x ƒA x tj]

CLOCK DUTY CYCLE is the ratio of the time during one cycle

that a repetitive digital waveform is high to the total time of

one period. The specification here refers to the ADC clock

input signal.

COMMON MODE VOLTAGE (VCM) is the common DC volt-

age applied to both input terminals of the ADC.

CONVERSION LATENCY is the number of clock cycles be-

tween initiation of conversion and when that data is presented

to the output driver stage. Data for any given sample is avail-

able at the output pins the Pipeline Delay plus the Output

Delay after the sample is taken. New data is available at every

clock cycle, but the data lags the conversion by the pipeline

delay.

CROSSTALK is coupling of energy from one channel into the

other channel.

DIFFERENTIAL NON-LINEARITY (DNL) is the measure of

the maximum deviation from the ideal step size of 1 LSB.

EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE

BITS) is another method of specifying Signal-to-Noise and

Distortion Ratio or SINAD. ENOB is defined as (SINAD -

1.76) / 6.02 and says that the converter is equivalent to a

perfect ADC of this (ENOB) number of bits.

FULL POWER BANDWIDTH is a measure of the frequency

at which the reconstructed output fundamental drops 3 dB

below its low frequency value for a full scale input.

GAIN ERROR is the deviation from the ideal slope of the

transfer function. It can be calculated as:

Gain Error = Positive Full Scale Error − Negative Full Scale

Error

It can also be expressed as Positive Gain Error and Negative

Gain Error, which are calculated as:

PGE = Positive Full Scale Error - Offset Error

NGE = Offset Error - Negative Full Scale Error

INTEGRAL NON LINEARITY (INL) is a measure of the de-

viation of each individual code from a best fit straight line. The

deviation of any given code from this straight line is measured

from the center of that code value.

INTERMODULATION DISTORTION (IMD) is the creation of

additional spectral components as a result of two sinusoidal

frequencies being applied to the ADC input at the same time.

It is defined as the ratio of the power in the intermodulation

products to the total power in the original frequencies. IMD is

usually expressed in dBFS.

LSB (LEAST SIGNIFICANT BIT) is the bit that has the small-

est value or weight of all bits. This value is VFS/2n, where

“VFS” is the full scale input voltage and “n” is the ADC reso-

lution in bits.

MISSING CODES are those output codes that will never ap-

pear at the ADC outputs. The ADC is guaranteed not to have

any missing codes.

MSB (MOST SIGNIFICANT BIT) is the bit that has the largest

value or weight. Its value is one half of full scale.

NEGATIVE FULL SCALE ERROR is the difference between

the actual first code transition and its ideal value of ½ LSB

above negative full scale.

OFFSET ERROR is the difference between the two input

voltages [(VIN+) – (VIN-)] required to cause a transition from

code 2047 to 2048.

OUTPUT DELAY is the time delay after the falling edge of the

clock before the data update is presented at the output pins.

PIPELINE DELAY (LATENCY) See CONVERSION LATEN-

CY.

POSITIVE FULL SCALE ERROR is the difference between

the actual last code transition and its ideal value of 1½ LSB

below positive full scale.

POWER SUPPLY REJECTION RATIO (PSRR) is a measure

of how well the ADC rejects a change in the power supply

voltage. PSRR is the ratio of the Full-Scale output of the ADC

with the supply at the minimum DC supply limit to the Full-

Scale output of the ADC with the supply at the maximum DC

supply limit, expressed in dB.

SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in

dB, of the rms value of the input signal to the rms value of the

sum of all other spectral components below one-half the sam-

pling frequency, not including harmonics or DC.

SIGNAL TO NOISE PLUS DISTORTION (S/N+D or

SINAD) Is the ratio, expressed in dB, of the rms value of the

input signal to the rms value of all of the other spectral com-

ponents below half the clock frequency, including harmonics

but excluding d.c.

SPURIOUS FREE DYNAMIC RANGE (SFDR) is the differ-

ence, expressed in dB, between the rms values of the input

signal and the peak spurious signal, where a spurious signal

is any signal present in the output spectrum that is not present

at the input.

TOTAL HARMONIC DISTORTION (THD) is the ratio, ex-

pressed in dB, of the rms total of the first six harmonic levels

at the output to the level of the fundamental at the output. THD

is calculated as

where f1 is the RMS power of the fundamental (output) fre-

quency and f2 through f7 are the RMS power of the first six

harmonic frequencies in the output spectrum.

SECOND HARMONIC DISTORTION (2ND HARM) is the dif-

ference expressed in dB, between the RMS power in the input

frequency at the output and the power in its 2nd harmonic

level at the output.

THIRD HARMONIC DISTORTION (3RD HARM) is the dif-

ference, expressed in dB, between the RMS power in the

input frequency at the output and the power in its 3rd harmonic

level at the output.

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ADC11DV200

Timing Diagrams

30087509

FIGURE 1. LVDS Output Timing

30087516

FIGURE 2. CMOS Output Timing

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ADC11DV200

Transfer Characteristic

30087510

FIGURE 3. Transfer Characteristic

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ADC11DV200

Typical Performance Characteristics DNL, INL Unless otherwise specified, the following

specifications apply: AGND = DRGND = 0V, VA = VD = VDR = +1.8V, fCLK = 200 MHz, 50% Duty Cycle, DCS Enabled, LVDS Output,

VCM = VRM, TA = 25°C.

DNL

30087541

INL

30087542

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ADC11DV200

Typical Performance Characteristics Unless otherwise specified, the following specifications apply:

AGND = DRGND = 0V, VA = VD = VDR = +1.8V, fCLK = 200 MHz, 50% Duty Cycle, DCS disabled, LVDS Output, VCM = VRM, fIN =

70 MHz, TA = 25°C.

SNR, SINAD, SFDR vs. VA

30087551

Distortion vs. VA

30087552

SNR, SINAD, SFDR vs. Temperature

30087553

Distortion vs. Temperature

30087554

SNR, SINAD, SFDR vs. Clock Duty Cycle, fIN = 10MHz

30087555

Distortion vs. Clock Duty Cycle, fIN = 10MHz

30087556

www.national.com 14

ADC11DV200

SNR, SINAD, SFDR vs. Ext. Reference Voltage

30087557

Distortion vs. Ext. Reference Voltage

30087558

SNR, SINAD, SFDR vs. Clock Frequency

30087559

Distortion vs. Clock Frequency

30087560

SNR, SINAD, SFDR vs. Ext. VCM

30087561

Distortion vs. Ext. VCM

30087562

15 www.national.com

ADC11DV200

Spectral Response @ 10 MHz Input

30087563

Spectral Response @ 70 MHz Input

30087564

Spectral Response @ 170 MHz Input

30087565

IMD, fIN1 = 69 MHz, fIN2 = 70 MHz

30087566

Total Power vs. Clock Frequency, fIN = 10 MHz

30087567

www.national.com 16

ADC11DV200

Functional Description

Operating on a single +1.8V supply, the ADC11DV200 digi-

tizes two differential analog input signals to 11 bits, using a

differential pipelined architecture with error correction circuitry

and an on-chip sample-and-hold circuit to ensure maximum

performance. The user has the choice of using an internal

0.75V stable reference, or using an external 0.75V reference.

Any external reference is buffered on-chip to ease the task of

driving that pin. Duty cycle stabilization and output data format

are selectable using the quad state function DF/DCS pin (pin

20). The output data can be set for offset binary or two's com-

plement.

Applications Information

1.0 OPERATING CONDITIONS

We recommend that the following conditions be observed for

operation of the ADC11DV200:

1.7V ≤ VA ≤ 1.9V

1.7V ≤ VDR ≤ VA

45 MHz ≤ fCLK ≤ 200 MHz, with DCS off

65 MHz ≤ fCLK ≤ 200 MHz, with DCS on

0.75V internal reference

VREF = 0.75V (for an external reference)

VCM = 0.9V (from VRM)

2.0 ANALOG INPUTS

2.1 Signal Inputs

2.1.1 Differential Analog Input Pins

The ADC11DV200 has a pair of analog signal input pins for

each of two channels. VIN+ and VIN− form a differential input

pair. The input signal, VIN, is defined as

VIN = (VIN+) – (VIN−)

Figure 4shows the expected input signal range. Note that the

common mode input voltage, VCM, should be 0.9V. Using

VRM (pins 5,11) for VCM will ensure the proper input common

mode level for the analog input signal. The positive peaks of

the individual input signals should each never exceed 2.2V.

Each analog input pin of the differential pair should have a

maximum peak-to-peak voltage of 1.5V, be 180° out of phase

with each other and be centered around VCM.The peak-to-

peak voltage swing at each analog input pin should not ex-

ceed the 1V or the output data will be clipped.

30087580

FIGURE 4. Expected Input Signal Range

For single frequency sine waves the full scale error in LSB

can be described as approximately

EFS = 2048 ( 1 - sin (90° + dev))

Where dev is the angular difference in degrees between the

two signals having a 180° relative phase relationship to each

other (see Figure 5). For single frequency inputs, angular er-

rors result in a reduction of the effective full scale input. For

complex waveforms, however, angular errors will result in

distortion.

30087581

FIGURE 5. Angular Errors Between the Two Input Signals

Will Reduce the Output Level or Cause Distortion

It is recommended to drive the analog inputs with a source

impedance less than 100Ω. Matching the source impedance

for the differential inputs will improve even ordered harmonic

performance (particularly second harmonic).

Table 2 indicates the input to output relationship of the AD-

C11DV200.

17 www.national.com

ADC11DV200

TABLE 2. Input to Output Relationship

VIN+VIN−Binary Output 2’s Complement Output

VCM − VREF/2 VCM + VREF/2 000 0000 0000 100 0000 0000 Negative Full-Scale

VCM − VREF/4 VCM + VREF/4 010 0000 0000 110 0000 0000

VCM VCM 100 0000 0000 000 0000 0000 Mid-Scale

VCM + VREF/4 VCM − VREF/4 110 0000 0000 010 0000 0000

VCM + VREF/2 VCM − VREF/2 111 1111 1111 011 1111 1111 Positive Full-Scale

2.1.2 Driving the Analog Inputs

The VIN+ and the VIN− inputs of the ADC11DV200 have an

internal sample-and-hold circuit which consists of an analog

switch followed by a switched-capacitor amplifier.

Figure 6 and Figure 7 show examples of single-ended to dif-

ferential conversion circuits. The circuit in Figure 6 works well

for input frequencies up to approximately 70MHz, while the

circuit in Figure 7 works well above 70MHz.

30087582

FIGURE 6. Low Input Frequency Transformer Drive Circuit

30087583

FIGURE 7. High Input Frequency Transformer Drive Circuit

One short-coming of using a transformer to achieve the sin-

gle-ended to differential conversion is that most RF trans-

formers have poor low frequency performance. A differential

amplifier can be used to drive the analog inputs for low fre-

quency applications. The amplifier must be fast enough to

settle from the charging glitches on the analog input resulting

from the sample-and-hold operation before the clock goes

high and the sample is passed to the ADC core.

2.1.3 Input Common Mode Voltage

The input common mode voltage, VCM, should be in the range

of 0.8V to 1.0V and be a value such that the peak excursions

of the analog signal do not go more negative than ground or

more positive than the VA supply. It is recommended to use

VRM (pins 5,11) as the input common mode voltage.

If the ADC11DV200 is operated with VA=1.8V, a resistor of

approximately 1KΩ should be used from the VRM pin to AG-

ND. This will help maintain stability over the entire tempera-

ture range when using a high supply voltage.

2.2 Reference Pins

The ADC11DV200 is designed to operate with an internal or

external voltage reference. The voltage on the VREF pin se-

lects the source and level of the reference voltage. An internal

0.75 Volt reference is used when a voltage between 1.4 V to

VA is applied to the VREF pin. An internal 0.5 Volt reference is

sued when a voltage between 0.2V and AGND is applied to

the VREF pin. If a voltage between 0.2V and 1.4V is applied to

the VREF pin, then that voltage is used for the reference. SNR

will improve without a significant degradation in SFDR for

VREF=1.0V. SNR will decrease if VREF=0.5V, yet linearity will

be maintained. If using an external reference the VREF pin

should be bypassed to ground with a 0.1 µF capacitor close

to the reference input pin.

It is important that all grounds associated with the reference

voltage and the analog input signal make connection to the

ground plane at a single, quiet point to minimize the effects of

noise currents in the ground path.

The Reference Bypass Pins (VRP, VRM, and VRN) for channels

A and B are made available for bypass purposes. These pins

should each be bypassed to AGND with a low ESL (equivalent

www.national.com 18

ADC11DV200

series inductance) 0.1 µF capacitor placed very close to the

pin to minimize stray inductance. A 0.1 µF capacitor should

be placed between VRP and VRN as close to the pins as pos-

sible. This configuration is shown in Figure 8. It is necessary

to avoid reference oscillation, which could result in reduced

SFDR and/or SNR. VRM may be loaded to 1mA for use as a

temperature stable 0.9V reference. The remaining pins

should not be loaded.

Smaller capacitor values than those specified will allow faster

recovery from the power down mode, but may result in de-

graded noise performance. Loading any of these pins, other

than VRM may result in performance degradation.

The nominal voltages for the reference bypass pins are as

follows:

VRM = 0.9 V

VRP = 1.33 V

VRN = 0.55 V

2.3 DF/DCS Pin

Duty cycle stabilization and output data format are selectable

using this quad state function pin. When enabled, duty cycle

stabilization can compensate for clock inputs with duty cycles

ranging from 30% to 70% and generate a stable internal clock,

improving the performance of the part. See Table 1 for DF/

DCS voltage vs output format description. DCS mode of op-

eration is limited to 65 MHz ≤ fCLK ≤ 200 MHz.

3.0 DIGITAL INPUTS

Digital CMOS compatible inputs consist of CLK, PD_A,

PD_B, and OUTSEL.

3.1 Clock Input

The CLK controls the timing of the sampling process. To

achieve the optimum noise performance, the clock input

should be driven with a stable, low jitter clock signal in the

range indicated in the Electrical Table. The clock input signal

should also have a short transition region. This can be

achieved by passing a low-jitter sinusoidal clock source

through a high speed buffer gate. The trace carrying the clock

signal should be as short as possible and should not cross

any other signal line, analog or digital, not even at 90°.

If the clock is interrupted, or its frequency is too low, the

charge on the internal capacitors can dissipate to the point

where the accuracy of the output data will degrade. This is

what limits the minimum sample rate.

The clock line should be terminated at its source in the char-

acteristic impedance of that line. Take care to maintain a

constant clock line impedance throughout the length of the

line. Refer to Application Note AN-905 for information on set-

ting characteristic impedance. It is highly desirable that the

the source driving the ADC clock pins only drive that pin.

The duty cycle of the clock signal can affect the performance

of the A/D Converter. Because achieving a precise duty cycle

is difficult, the ADC11DV200 has a Duty Cycle Stabilizer.

4.0 DIGITAL OUTPUTS

Digital outputs consist of the LVDS signals D0-D10 and

DRDY.

The ADC11DV200 has 12 LVDS compatible data output pins:

11 data output pins corresponding to the converted input val-

ue, and a data ready (DRDY) signal that should be used to

capture the output data. Valid data is present at these outputs

while the PD pin is low. A-Channel data should be captured

and latched with the rising edge of the DRDY signal and B-

Channel data should be captured and latched with the falling

edge of DRDY.

To minimize noise due to output switching, the load currents

at the digital outputs should be minimized. This can be

achieved by keeping the PCB traces less than 2 inches long;

longer traces are more susceptible to noise. The character-

istic impedance of the LVDS traces should be 100Ω, and the

effective capacitance < 10pF. Try to place the 100Ω termina-

tion resistor as close to the receiving circuit as possible. (See

Figure 8)

19 www.national.com

ADC11DV200

30087585

FIGURE 8. Application Circuit

www.national.com 20

ADC11DV200

5.0 POWER SUPPLY CONSIDERATIONS

The power supply pins should be bypassed with a 0.1 µF ca-

pacitor and with a 100 pF ceramic chip capacitor close to each

power pin. Leadless chip capacitors are preferred because

they have low series inductance.

As is the case with all high-speed converters, the AD-

C11DV200 is sensitive to power supply noise. Accordingly,

the noise on the analog supply pin should be kept below 100

mVP-P.

No pin should ever have a voltage on it that is in excess of the

supply voltages, not even on a transient basis. Be especially

careful of this during power turn on and turn off.

21 www.national.com

ADC11DV200

Physical Dimensions inches (millimeters) unless otherwise noted

TOP View...............................SIDE View...............................BOTTOM View

60-Lead LLP Package

Ordering Numbers:

ADC11DV200CISQ

NS Package Number SQA60A

www.national.com 22

ADC11DV200

Notes

23 www.national.com

ADC11DV200

Notes

ADC11DV200 Dual 11-bit, 200 MSPS Low-Power A/D Converter with Parallel Outputs

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