GaN Bias Controller/Sequencer Module
Dual Supply: -8 to -3 V, +12 to +55 V
Rev. V2
MABC-001000-DP000L
4
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Applications Section
Functional Description
The MABC-001000-DP000L GaN Bias Controller/
Sequencer Module circuitry provides proper
sequencing and generation of the gate voltage and
pulsed drain voltage for a device under test (DUT).
Reference the Product View and Pin Configuration
table on page 1. The basic functions of the circuits
within the module are described as follows:
Overhead Voltages for the Circuits within the
MABC-001000-DP000L Module
○ Pin 8 (VDS) is the Drain (+) Supply Voltage
that provides the input voltage to a low drop-
out linear regulator (VREG). This supplies
the positive voltage for the circuits within the
module. It also provides the Auxiliary
+4.3 V Output to Pin 11 (P4V).
○ Pin 5 (VGS) is the Gate (-) Supply Voltage
that is also used to supply the negative
voltage for the circuits within the module.
Negative Gate Voltage for the Device Under
Test (DUT)
○ A voltage follower op-amp circuit provides a
low impedance output to Pin 3 (GCO) Gate
Voltage (-) Control Output. Pin 3 (GCO)
output is applied to the gate terminal of a
DUT as shown in Figure 1 on page 5.
○ The reference voltage for the voltage
follower is provided by the Pin 4 (GCI) Gate
Voltage (-) Analog Input. This input
reference voltage is developed by an
external potentiometer/ resistive divider
circuit as shown in Figure 1 on page 6. It is
recommended to use the -8 V to -3 V
voltage that is also applied to Pin 5 (VGS).
○ Reference: The external potentiometer is
adjusted to set the gate voltage Pin 3 (GCO)
to the DUT. Alternative voltage inputs such
as a temperature compensation circuit or a
Digital-to-Analog (DAC) converter could also
be supplied to Pin 4 (GCI).
Pin 9 (SWG) MOS Switch Driver Output
○ An N-Channel MOSFET develops the
pulsed signal (SWG) to drive the
resistive divider network for the gate of an
external p-Channel HEXFET as shown in
Figure 1 on page 5. The input signal for the
internal MOSFET is provided by the output
from the sequencing circuits.
Sequencing Circuits
○ A voltage comparator circuit senses if the
negative gate voltage is present as an input
on Pin 1 (GFB) - Gate Voltage (-) Feedback.
○ A logic circuit provides the switched input
enable signal for the N-Channel MOSFET.
The following 3 signals must be at correct
levels to generate the enable logic
signal:
Pin 12 (ENS) MOS Switch Enable TTL
Negative gate voltage (GFB) is present
The internal positive voltage output is
present from V_REG