XR76121
13/18
REV1C
Applications Information (Continued)
Overcurrent Protection (OCP)
If the load current exceeds the programmed overcurrent
threshold IOCP for four consecutive switching cycles,
the regulator enters the hiccup mode of operation.
In hiccup mode the MOSFET gates are turned off for 110ms
(hiccup timeout). Following the hiccup timeout a soft-start
is attempted. If OCP persists, hiccup timeout will repeat.
The regulator will remain in hiccup mode until load current
is reduced below the programmed IOCP. In order to program
overcurrent protection use the following equation:
VIN × [tON
–
(2.5 × 10-8)]
RON = 3.45 × 10-10
VOUT
tON = VIN x 1.06 x f x Eff.
RON = (3.45 × 10-10)
–
[(2.5 × 10-8) x VIN]
VOUT
1.06 x f x Eff.
RLIM =
+
0.16kΩ
(IOCP + (0.5 × ∆IL))
ILIM
RDS
R1 = R2 x VOUT
0.6
–
1
CSS = tSS x 10µA
0.6V
CFF = 1
2 x
π
x R1 x 5 x fLC
fLC = 1
2 x
π
x
√
L x COUT
RFF = 1
2 x
π
x f x CFF
Where:
RLIM is resistor value in kΩ for programming IOCP
IOCP is the overcurrent value to be programmed
ΔIL is the peak-to-peak inductor current ripple
ILIM/RDS is the minimum value of the parameter
specified in the tabulated data
ILIM/RDS = 14.5uA/mΩ
0.16kΩ accounts for OCP comparator offset
The above equation is for worst-case analysis and
safeguards against premature OCP. Typical value of IOCP,
for a given RLIM, will be higher than that predicted by
the above equation. Graph of calculated IOCP vs. RLIM is
compared to typical IOCP in Figures 23.
Short-Circuit Protection (SCP)
If the output voltage drops below 60% of its programmed
value (i.e., FB drops below 0.36V), the regulator will enter
hiccup mode. Hiccup mode will persist until short-circuit
is removed. The SCP circuit becomes active at the end
of soft-start. Hiccup mode and short-circuit recovery
waveform is shown in Figure 16.
Over Temperature Protection (OTP)
OTP triggers at a nominal controller temperature of 138°C.
The gates of the switching FET and the synchronous FET
are turned off. When controller temperature cools down to
123°C, soft-start is initiated and regular operation resumes.
Overvoltage Protection (OVP)
The output OVP function detects an overvoltage condition
on VOUT of the regulator. OVP is achieved by comparing
the voltage at VSNS pin to an OVP threshold voltage
set at 1.2 x VREF. When VSNS voltage exceeds the
OVP threshold, an internal overvoltage signal asserts after
1us (typical). This OVP signal latches off the high-side FET,
turns on the low-side FET and also asserts PGOOD low.
The low-side FET remains on to discharge the output
capacitor until VSNS voltage drops below 1.15 x VREF.
Then low-side FET turns off to prevent complete discharge
of VOUT. The high-side and low-side FETs remain latched
off until VIN or EN is recycled. In order to use this feature,
connect VSNS to VOUT with a resistor divider as shown in
the application circuit. Use the same resistor divider value
that was used for programming VOUT.
Programming the Output Voltage
Use a voltage divider as shown in Figure 1 to program the
output voltage VOUT.
VIN × [tON
–
(2.5 × 10-8)]
RON = 3.45 × 10-10
VOUT
tON = VIN x 1.06 x f x Eff.
RON = (3.45 × 10-10)
–
[(2.5 × 10-8) x VIN]
VOUT
1.06 x f x Eff.
RLIM =
+
0.16kΩ
(IOCP + (0.5 × ∆IL))
ILIM
RDS
R1 = R2 x VOUT
0.6
–
1
CSS = tSS x 10µA
0.6V
CFF = 1
2 x
π
x R1 x 5 x fLC
fLC = 1
2 x
π
x
√
L x COUT
RFF = 1
2 x
π
x f x CFF
The recommended value for R2 is 2kΩ.
Programming the Soft-Start
Place a capacitor CSS between the SS and AGND pins to
program the soft-start. In order to program a soft-start time
of tSS, calculate the required capacitance CSS from the
following equation:
VIN × [tON
–
(2.5 × 10-8)]
RON = 3.45 × 10-10
VOUT
tON = VIN x 1.06 x f x Eff.
RON = (3.45 × 10-10)
–
[(2.5 × 10-8) x VIN]
VOUT
1.06 x f x Eff.
RLIM =
+
0.16kΩ
(IOCP + (0.5 × ∆IL))
ILIM
RDS
R1 = R2 x VOUT
0.6
–
1
CSS = tSS x 10µA
0.6V
CFF = 1
2 x
π
x R1 x 5 x fLC
fLC = 1
2 x
π
x
√
L x COUT
RFF = 1
2 x
π
x f x CFF
Pre-Bias Startup
XR76121 has the capability to startup into a pre-charged
output. Typical pre-bias startup waveforms are shown in
Figure 15.
Maximum Allowable Voltage Ripple at FB Pin
The steady-state voltage ripple at feedback pin FB
(VFB,RIPPLE) must not exceed 50mV in order for the regulator
to function correctly. If VFB,RIPPLE is larger than 50mV then
COUT and/or L should be increased as necessary in order to
keep the VFB,RIPPLE below 50mV.