PROFET® BTS 840 S2
Infineon technologies Page 1 of 17 1999-Nov-18
Smart High-Side Power Switch
Two Channels: 2 x 30mΩ
Current Sense
Product Summary Package
Operating Voltage Vbb(on) 5.0...34V
Active channels: one two parallel
On-state Resistance RON 30mΩ15mΩ
Load Current (ISO) IL(ISO) 12A 24A
Current Limitation IL(SCr) 24A 24A
General Description
• N channel vertical power MOSFET with charge pump, ground referenced CMOS compatible input,
diagnostic feedback and proportional load current sense monolithically integrated in Smart SIPMOS
technology.
• Fully protected by embedded protection functions
Applications
• µC compatible high-side power switch with diagnostic feedback for 12V and 24V grounded loads
• All types of resistive, inductive and capacitve loads
• Most suitable for loads with high inrush currents, so as lamps
• Replaces electromechanical relays, fuses and discrete circuits
Basic Functions
• CMOS compatible input
• Undervoltage and overvoltage shutdown with auto-restart and hysteresis
• Fast demagnetization of inductive loads
• Logic ground independent from load ground
Protection Functions
• Short circuit protection
• Overload protection
• Current limitation
• Thermal shutdown
• Overvoltage protection (including load dump) with external
resistor
• Reverse battery protection with external resistor
• Loss of ground and loss of Vbb protection
• Electrostatic discharge protection (ESD)
Diagnostic Functions
• Proportinal load current sense
• Diagnostic feedback with open drain output
• Open load detection in OFF-state with external resistor
• Feedback of thermal shutdown in ON-state
Vbb
Logic
Channel
1
Logic
Channel
2
IN1
ST1
IS1
IN2
ST2
IS2
GND
Load 1
Load 2
PROFET
OUT 1
OUT 2
P-DSO-20-12 (Power SO 20)
BTS 840 S2
Infineon technologies Page 2 1999-Nov-18
Functional diagram
Pin Definitions and Functions
Pin Symbol Function
1,10,
11,12, Vbb Positive power supply voltage. For high
current applications the heat slug should be
used as Vbb connection.
3IN1
7IN2
Input 1,2, activates channel 1,2 in case of
logic high signal
16,17,
18,19 OUT1
12,13,
14,15 OUT2
Output 1,2, protected high-side power output
of channel 1,2. All pins of each output have to
be connected in parallel for operation
according ths spec (e.g. kilis). Design the
wiring for the max. short circuit current
4ST1
8ST2
Diagnostic feedback 1,2 of channel 1,2
open drain, invers to input level
2 GND1
6 GND2 Ground 1,2 of chip channel 1,2
5IS1
9IS2
Sense current output 1,2; proportional to the
load current, zero in the case of current
limitation of the load current
Heatslug Vbb Positiv powersupply voltage. Good way to
design a very low thermal resistance.
Pin configuration
(top view)
Vbb 1 •20 Vbb
GND1 2 19 OUT1
IN1 3 18 OUT1
ST1 4 17 OUT1
IS1 5 16 OUT1
GND2 6 Vbb 15 OUT2
IN2 7 14 OUT2
ST2 8 13 OUT2
IS2 9 12 OUT2
Vbb 10 11 Vbb
Heat slug
OUT1
overvoltage
protection
logic
internal
volta
g
e suppl
y
ESD
temperature
sensor
clamp for
inductive load
gate
control
+
charge
pump
current limit
Open load
detection
ST1
VBB
LOAD
IN1
PROFET
GND1
Control and protection circuit
of
channel 2
IN2
ST2
OUT2
Channel 1
Current
sense
GND2
IS2
IS1
R
O
1
GND1
BTS 840 S2
Infineon technologies Page 3 1999-Nov-18
Maximum Ratings at
T
j = 25°C unless otherwise specified
Parameter Symbol Values Unit
Supply voltage (overvoltage protection see page 4)
V
bb 43 V
Supply voltage for full short circuit protection
T
j,start = -40 ...+150°C
V
bb 34 V
Load current (Short-circuit current, see page 6)
I
Lself-limited A
Load dump protection1)
V
LoadDump =
V
A +
V
s,
V
A = 13.5 V
R
I2) = 2 Ω,
t
d = 200 ms; IN = low or high,
each channel loaded with
R
L = 1.0 Ω,
V
Load dump3)60 V
Operating temperature range
Storage temperature range
T
j
T
stg -40 ...+150
-55 ...+150 °C
Power dissipation
(
DC
)
4)
T
a =
25°C:
(all channels active)
T
a =
85°C:
P
tot 3.8
2.0 W
Maximal switchable inductance, single pulse
Vbb = 12V,
T
j,start = 150°C4),
I
L
= 4 A,
E
AS = 1.13J, 0 Ωone channel:
L
= 12 A,
E
AS = 430mJ, 0 Ωone channel:
I
L
= 24 A,
E
AS = 800mJ, 0 Ω two parallel channels:
see diagrams on page 11
ZL100
4.4
2.0
mH
Electrostatic dischar
g
e capabilit
y
(
ESD
)
IN:
(
Human Bod
y
Model
)
ST, IS:
out to all other pins shorted:
acc. MIL-STD883D, method 3015.7 and ESD assn. std. S5.1-1993
R=1.5kΩ; C=100pF
V
ESD 1.0
4.0
8.0
kV
Input voltage (DC)
V
IN -10 ... +16 V
Current through input pin (DC)
Current through status pin (DC)
Current through current sense pin (DC)
see internal circuit diagram page 10
I
IN
I
ST
I
IS
±2.0
±5.0
±14
mA
1)Supply voltages higher than Vbb(AZ) require an external current limit for the GND and status pins a 150Ω
resistor for the GND connection is recommended.
2)
R
I = internal resistance of the load dump test pulse generator
3) VLoad dump is set up without the DUT connected to the generator per ISO 7637-1 and DIN 40839
4)Device on 50mm*50mm*1.5mm epoxy PCB FR4 with 6cm2 (one layer, 70µm thick) copper area for Vbb
connection. PCB is vertical without blown air.
BTS 840 S2
Infineon technologies Page 4 1999-Nov-18
Thermal Characteristics
Parameter and Conditions Symbol Values Unit
min typ max
Thermal resistance
junction -case each channel:
R
thjs -- -- 1 K/W
j
unction - ambient4) one channel active:
all channels active:
R
thja --
-- 37
30 --
--
Electrical Characteristics
Parameter and Conditions, each of the two channels Symbol Values Unit
at Tj = -40...+150°C,
V
bb = 12 V unless otherwise specified min typ max
Load Switching Capabilities and Characteristics
On-state resistance (Vbb to OUT); IL = 5 A
each channel,
T
j = 25°C:
T
j = 150°C:
two parallel channels,
T
j = 25°C:
R
ON -- 27
54
14
30
60
15
mΩ
Output voltage drop limitation at small load
currents, see page 16
I
L = 0.5 A
T
j =-40...+150°C:
V
ON(NL) -- 50 -- mV
Nominal load current, ISO Norm
one channel active:
two parallel channels active:
ISO 10483-1, 6.7:
Von
=0.5V
T
c = 85°C
I
L(NOM) 11
22 12
24 -- A
Output current while GND disconnected or pulled up;
Vbb = 30 V,
V
IN = 0,
see diagram page 11; (not tested specified by design)
I
L(GNDhigh) -- -- 8 mA
Turn-on time5) IN to 90%
V
OUT:
Turn-off time IN to 10%
V
OUT:
R
L = 12 Ω
t
on
t
off
25
25 70
80 150
200 µs
Slew rate on 5)
10 to 30%
V
OUT,
R
L = 12 Ω:d
V
/dton 0.1 -- 1 V/µs
Slew rate off 5)
70 to 40%
V
OUT,
R
L = 12 Ω:-d
V
/dtoff 0.1 -- 1 V/µs
5)See timing diagram on page 13.
BTS 840 S2
Parameter and Conditions, each of the two channels Symbol Values Unit
at Tj = -40...+150°C,
V
bb = 12 V unless otherwise specified min typ max
Infineon technologies Page 5 1999-Nov-18
Operating Parameters
Operating voltage6)
V
bb(on) 5.0 -- 34 V
Undervoltage shutdown
V
bb(under) 3.2 -- 5.0 V
Undervolta
g
e restart
T
j
=-40...+25°C:
T
j =+150°C:
V
bb(u rst) -- 4.5 5.5
6.0 V
Undervolta
g
e restart of char
g
e pump
see dia
g
ram pa
g
e 15
T
j
=-40...+25°C:
T
j =150°C:
V
bb(ucp) --
-- 4.7
-- 6.5
7.0 V
Undervoltage hysteresis
∆
V
bb(under) =
V
bb(u rst) -
V
bb(under) ∆
V
bb(under) -- 0.5 -- V
Overvoltage shutdown
V
bb(over) 34 -- 43 V
Overvoltage restart
V
bb(o rst) 33 -- -- V
Overvoltage hysteresis ∆
V
bb(over) -- 1 -- V
Overvolta
g
e protection7)
T
j
=-40:
I
bb=40 mA
T
j =+25...+150°C:
V
bb(AZ) 41
43 --
47 --
52 V
Standby current8)
T
j =-40°C...25°C:
VIN = 0; see diagram page 10
T
j =150°C:
I
bb(off) --
-- 8
24 30
50 µA
Leakage output current (included in
I
bb(off))
V
IN = 0
I
L(off) -- -- 20 µA
Operating current 9),
V
IN = 5V,
I
GND =
I
GND1 +
I
GND2, one channel on:
two channels on:
I
GND --
-- 1.2
2.4 3
6mA
Protection Functions
Current limit, (see timing diagrams, page 14)
T
j =-40°C:
T
j =25°C:
T
j =+150°C:
I
L(lim) 48
40
31
56
50
37
65
58
45
A
Repetitive short circuit current limit,
T
j =
T
jt each channel
two parallel channels
(see timing diagrams, page 14)
I
L(SCr) --
-- 24
24 --
-- A
Initial short circuit shutdown time
T
j,start =25°C:
(see timing diagrams on page 14)
t
off(SC) -- 4.0 -- ms
6) At supply voltage increase up to
V
bb= 4.7 V typ without charge pump,
V
OUT ≈
V
bb - 2 V
7) Supply voltages higher than Vbb(AZ) require an external current limit for the GND and status pins (a 150 Ω
resistor in the GND connection is recommended). See also
V
ON(CL) in table of protection functions and
circuit diagram page 10.
8)Measured with load; for the whole device; all channels off
9)Add
I
ST, if
I
ST > 0
BTS 840 S2
Parameter and Conditions, each of the two channels Symbol Values Unit
at Tj = -40...+150°C,
V
bb = 12 V unless otherwise specified min typ max
Infineon technologies Page 6 1999-Nov-18
Output clamp (inductive load switch off)10)
at VON(CL) = Vbb - VOUT,
I
L= 40 mA
T
j =-40°C:
T
j =25°C...150°C:
V
ON(CL) 41
43 --
47 --
52 V
Thermal overload trip temperature
T
jt 150 -- -- °C
Thermal hysteresis
∆
T
jt -- 10 -- K
Reverse Battery
Reverse battery voltage 11)-
V
bb -- -- 32 V
Drain-source diode voltage (Vout > Vbb)
I
L = - 4.0 A,
T
j = +150°C -
V
ON -- 600 -- mV
Diagnostic Characteristics
Current sense ratio12), static on-condition,
V
IS = 0...5 V,
V
bb(on) = 6.513)...27V,
k
ILIS =
I
L /
I
IS
T
j = -40°C,
I
L = 5 A:
k
ILIS 4350 4800 5800
T
j= -40°C,
I
L= 0.5 A: 3100 4800 7800
T
j
= 25...+150°C,
I
L= 5 A:
T
j= 25...+150°C,
I
L = 0.5 A: 4350
3800 4800
4800 5350
6300
Current sense output voltage limitation
T
j = -40 ...+150°C
I
IS = 0,
I
L = 5 A:
V
IS(lim) 5.4 6.1 6.9 V
Current sense leakage/offset current
T
j = -40 ...+150°C
V
IN=0,
V
IS = 0,
I
L = 0:
I
IS(LL) 0--1
µA
V
IN=5 V,
V
IS = 0,
I
L = 0:
I
IS(LH) 0--15
V
IN=5 V,
V
IS = 0,
V
OUT = 0 (short circuit)
(
I
IS(SH) not tested, specified by design)
I
IS(SH) 0--10
Current sense settling time to
I
IS static±10% after
positive input slope,
I
L = 0 5 A
(not tested, specified by design)
t
son(IS) -- -- 300 µs
10)If channels are connected in parallel, output clamp is usually accomplished by the channel with the lowest
VON(CL)
11)Requires a 150 Ω resistor in GND connection. The reverse load current through the intrinsic drain-source
diode has to be limited by the connected load. Power dissipation is higher compared to normal operating
conditions due to the voltage drop across the drain-source diode. The temperature protection is not active
during reverse current operation! Input and Status currents have to be limited (see max. ratings page 3 and
circuit page 10).
12) This range for the current sense ratio refers to all devices. The accuracy of the
k
ILIS can be raised at least by
a factor of two by matching the value of
k
ILIS for every single device.
In the case of current limitation the sense current
I
IS is zero and the diagnostic feedback potential
V
ST is
High. See figure 2c, page 13.
13) Valid if
V
bb(u rst) was exceeded before.
BTS 840 S2
Parameter and Conditions, each of the two channels Symbol Values Unit
at Tj = -40...+150°C,
V
bb = 12 V unless otherwise specified min typ max
Infineon technologies Page 7 1999-Nov-18
Current sense settling time to 10% of
I
IS static after
negative input slope,
I
L = 5 0 A
(not tested, specified by design)
t
soff(IS) -- 30 100 µs
Current sense rise time (60% to 90%) after change
of load current
I
L = 2.5 5 A
(not tested, specified by design)
t
slc(IS) -- 10 -- µs
Open load detection voltage14) (off-condition)
V
OUT(OL) 234V
Internal output pull down
(pin 16,17,18,19 to 2 resp. 12,13,14,15 to 6),
V
OUT=5 V
R
O51540kΩ
Input and Status Feedback15)
Input resistance
(see circuit page 10)
R
I3.0 4.5 7.0 kΩ
Input turn-on threshold voltage
V
IN(T+) -- -- 3.5 V
Input turn-off threshold voltage
V
IN(T-) 1.5 -- -- V
Input threshold hysteresis ∆
V
IN(T) -- 0.5 -- V
Off state input current
V
IN = 0.4 V:
I
IN(off) 1--50µA
On state input current
V
IN = 5 V:
I
IN(on) 20 50 90 µA
Delay time for status with open load
after Input neg. slope (see diagram page 15) td(ST OL3) -- 400 -- µs
Status delay after positive input slope
(not tested, specified by design)
t
don(ST) -- 13 -- µs
Status delay after negative input slope
(not tested, specified by design)
t
doff(ST) -- 1 -- µs
Status output (open drain)
Zener lim it voltage
T
j =-40...+150°C,
I
ST = +1.6 mA:
ST low volta
g
e
T
j
=-40...+25°C,
ST = +1.6 mA:
T
j = +150°C,
I
ST = +1.6 mA:
V
ST(high)
V
ST(low)
5.4
--
--
6.1
--
--
6.9
0.4
0.7
V
Status leakage current,
V
ST = 5 V,
T
j=25 ... +150°C:
I
ST(high) -- -- 2 µA
14) External pull up resistor required for open load detection in off state.
15) If ground resistors RGND are used, add the voltage drop across these resistors.
BTS 840 S2
Infineon technologies Page 8 1999-Nov-18
Truth Table
Input 1 Output 1 Status 1 Current
Sense 1
Input 2 Output 2 Status 2 Current
Sense 2
level level level IIS
Normal
operation L
HL
HH
L0
nominal
Current-
limitation L
HL
HH
H0
0
Short circuit to
GND L
HL
L16)H
H0
0
Over-
temperature L
HL
LH
H0
0
Short circuit to
Vbb L
HH
HL17)
L0
<nominal 18)
Open load L
HL19)
HH (L20))
L0
0
Undervoltage L
HL
LH
L0
0
Overvoltage L
HL
LH
L0
0
Negative output
voltage clamp LL H 0
L = "Low" Level X = don’ t care Z = high impedance, potential depends on external circuit
H = "High" Level Status signal after the time delay shown in the diagrams (see fig 5. page 15)
Parallel switching of channel 1 and 2 is possible by connecting the inputs and outputs in parallel. The status
outputs ST1 and ST2 have to be configured as a ’Wired OR’ function with a single pull-up resistor. The current
sense outputs IS1 and IS2 have to be connected with a single pull-down resistor.
16)The voltage drop over the power transistor is
V
bb-
V
OUT > 3V typ. Under this condition the sense current
I
IS is
zero
17) An external short of output to Vbb, in the off state, causes an internal current from output to ground. If RGND
is used, an offset voltage at the GND and ST pins will occur and the VST low signal may be errorious.
18)Low ohmic short to
V
bb may reduce the output current
I
L and therefore also the sense current
I
IS.
19)Power Transistor off, high impedance
20)with external resistor between VBB and OUT
BTS 840 S2
Infineon technologies Page 9 1999-Nov-18
Terms
PROFET
V
IS1
ST1
GND1
bb
VST1
VIN1
IST1
IIN1
Vbb
Ibb
IGND1
17,18
2
Leadframe
3
5
IN1
VIS1
IIS1
VOUT1
VON1
IL1
OUT1
4
RGND1
Chip 1 PROFET
V
IS2
ST2
GND2
bb
VST2
VIN2
IST2
IIN2
IGND2
13,14
6
Leadframe
7
9
IN2
VIS2
IIS2
VOUT2
VON2
OUT2
8
IL2
RGND2
Chip 2
Leadframe (Vbb) is connected to pin 1,10,11,20
External RGND optional; two resistors RGND1, RGND2 = 150 Ω or a single resistor RGND = 75 Ω for reverse
battery protection up to the max. operating voltage.
BTS 840 S2
Infineon technologies Page 10 1999-Nov-18
Input circuit (ESD protection), IN1 or IN2
IN
GND
I
R
ESD-ZD I
I
I
The use of ESD zener diodes as voltage clamp at DC
conditions is not recommended.
Status output, ST1 or ST2
ST
GND
ESD-
ZD
+5V
RST(ON)
ESD-Zener diode: 6.1 V typ., max 5.0 mA; RST(ON) < 375 Ω
at 1.6 mA. The use of ESD zener diodes as voltage clamp at
DC conditions is not recommended.
Current sense output, IS1 or IS2
IS
GND IS
R
IS
I
ESD-ZD
IS
V
ESD-Zener diode: 6.1 V typ., max 14 mA;
R
IS = 1 kΩ nominal
Inductive and overvoltage output clamp,
OUT1 or OUT2
+Vbb
OUT
VZ
VON
Power GND
V
ON clamped to
V
ON(CL) = 47 V typ.
Overvoltage and reverse batt. Protection
For each channel
+ Vbb
IN
IS
V
R
GND
GND
R
Signal GND
Logic
PROFET
VZ2
I
R
VZ1
Load GND
Load
R
OUT
ST
R
+ 5V
ST
IS
R
V
Z1 = 6.1 V typ.,
V
Z2 = 47 V typ.,
R
GND = 150 Ω,
R
ST=15kΩ,
R
I=4.5kΩ typ.,
R
IS=1kΩ,
R
V=15kΩ,
In case of reverse battery the current has to be limited
by the load. Temperature protection is not active
Open-load detection OUT1 or OUT2
OFF-state diagnostic condition:
V
OUT > 3 V typ.; IN low
Logic
ST
Out VOUT
Signal GND
REXT
RO
OFF
Vbb
BTS 840 S2
Infineon technologies Page 11 1999-Nov-18
GND disconnect, each channel
PROFET
V
IN
ST
OUT
GND
bb
Vbb VIN VST VGND
Any kind of load. In case of IN = high is
V
OUT ≈
V
IN -
V
IN(T+).
Due to VGND > 0, no VST = low signal available.
GND disconnect with GND pull up
each channel
PROFET
V
IN
ST
OUT
GND
bb
Vbb VGND
VINVST
Any kind of load. If VGND >
V
IN -
V
IN(T+) device stays off
Due to VGND > 0, no VST = low signal available.
Vbb disconnect with energized inductive
load, each channel
PROFET
V
IN
ST
OUT
GND
bb
Vbb
high
For inductive load currents up to the limits defined by ZL
(max. ratings and diagram on page 11) each switch is
protected against loss of Vbb.
Consider at your PCB layout that in the case of Vbb dis-
connection with energized inductive load all the load current
flows through the GND connection.
Inductive load switch-off energy
dissipation, each channel
PROFET
V
IN
ST
OUT
GND
bb
=
E
E
E
EAS
bb
L
R
ELoad
RL
L
{
L
Z
Energy stored in load inductance:
E
L = 1/2·L·I2
L
While demagnetizing load inductance, the energy
dissipated in PROFET is
E
AS= Ebb + EL - ER= ∫ VON(CL)·iL(t) dt,
with an approximate solution for RL > 0 Ω:
E
AS= IL· L
2·RL(Vbb + |VOUT(CL)|) ln (1+ IL·RL
|VOUT(CL)| )
Maximum allowable load inductance for
a single switch off (one channel)4)
L = f (IL ); Tj,start = 150°C, Vbb = 12 V, RL = 0 Ω
ZL [mH]
0.1
1
10
100
4681012141618202224
IL [A]
BTS 840 S2
Infineon technologies Page 12 1999-Nov-18
Figure 1a: Switching a resistive load,
change of load current in on-condition:
IN
ST
OUT
L
t
V
I
IIS tson(IS)
tt
slc(IS)slc(IS)
Load 1 Load 2
soff(IS)
t
tdon(ST) tdoff(ST)
tt
on off
The sense s i gnal i s not valid during s ettling time after turn or
change of load current.
Figure 1b: Vbb turn on:
IN2
V
OUT1
t
V
bb
ST1 open drain
IN1
VOUT2
ST2 open drain
proper turn on under all conditions
Timing diagrams
Both channels are symmetric and consequently the diagrams are valid for channel 1 and
channel 2
BTS 840 S2
Infineon technologies Page 13 1999-Nov-18
Figure 2a: Switching a resistive load,
turn-on/off time and slew rate definition:
IN
t
VOUT
IL
t
t
on
off
90%
dV/dton
dV/dtoff
10%
Figure 2b: Switching a lamp:
IN
ST
OUT
L
t
V
I
The initial peak current should be li m i ted by the lamp and not by
the current l i mit of the dev i c e.
Figure 2c: Switching a lamp with current limit:
IN
ST
OUT
L
t
V
I
IIS
Figure 2d: Switching an inductive load
IN
ST
L
t
V
I
OUT
IL(OL)
*) if the t i m e constant of l oad i s too large, open-load-status may
occur
BTS 840 S2
Infineon technologies Page 14 1999-Nov-18
Figure 3a: Turn on into short circuit:
shut down by overtemperature, restart by cooling
other channel: normal operation
I
t
ST 1
IN1
L1
L(SCr)
I
IL(lim)
toff(SC)
IS 1 = 0
Heating up of the c hip may require several milliseconds , depending
on external conditions
Figure 3b: Turn on into short circuit:
shut down by overtemperature, restart by cooling
(two parallel switched channels 1 and 2)
t
S 1= IS 2 = 0
IN1/2
L1 L2
L(SCr)
I
2xIL(lim)
I + I
toff(SC)
ST 1/2
ST1 and ST2 have to be configured as a ’Wired OR’ function
ST1/2 with a single pull-up res i s tor.
Figure 4a: Overtemperature:
Reset if
T
j <
T
jt
IN
ST
OUT
J
t
V
T
BTS 840 S2
Infineon technologies Page 15 1999-Nov-18
Figure 5a: Open load: detection (with REXT),
turn on/off to open load
IN
ST
OUT
t
V
I
open load
L
IIS
d(ST OL3)
t
Figure 6a: Undervoltage:
IN
V
t
bb
ST
VV
bb(under) bb(u cp)
V
IL
IIS
bb(u rst)
not defined
Figure 6b: Undervoltage restart of charge pump
bb(under)
V
Vbb(u rst)
Vbb(over)
Vbb(o rst)
Vbb(u cp)
off-
state on-state
VON(CL)
Vbb
Von
off-
state
charge pump starts at
V
bb(ucp) =4.7 V typ.
Figure 7a: Overvoltage:
IN
V
t
bb
ST
ON(CL)
VVbb(over) Vbb(o rst)
IL
IIS
BTS 840 S2
Infineon technologies Page 16 1999-Nov-18
Figure 8a: Current sense versus load current21::
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
0123456
IL
[A]
[mA] IIS
21 This range for the current sense ratio refers to all
devices. The accuracy of the
k
ILIS can be raised at
least by a factor of two by matching the value of
k
ILIS for every single device.
Figure 8b: Current sense ratio:
0
5000
10000
15000
012345678910111213
IL
[A]
kILIS
Figure 9a: Output voltage drop versus load current:
0.0
0.1
0.2
012345678
IL
[A]
[V] VON
ON(NL)
V
ON
R
BTS 840 S2
Infineon technologies Page 17 1999-Nov-18
Package and Ordering Code
Standard: P-DSO-20-12 (Power SO 20)
Sales Code BTS 840
Ordering Code tbd
All dimensions in millimetres
Published by Siemens AG, Bereich Bauelemente, Vertrieb,
Produkt-Information, Balanstraße 73, D-81541 München
Siemens AG 1999. All Rights Reserved
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