Rev. 1.4 June 2012
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Page 1 of 15
AOZ1025D
EZBuck™ 8A Synchronous Buck Regulator
General Description
The AOZ1025D is a high efficiency, simple to use, buck
regulator, capable of up to 8A with an external low side
MOSFET. The AOZ1025D works from a 4.75V to 16V
input voltage range,
The AOZ1025D comes in a 5 x 4 DFN-16 package and is
rated over a -40°C to +85°C ambient temperature range.
Features
4.75 to 16V operating input voltage range
Synchronous rectification: Integrated high side
MOSFET
High efficiency: up to 95%
Internal soft start
Output voltage adjustable to 0.8V
Up to 8A continuous output current
Fixed 500kHz PWM operation
Cycle-by-cycle current limit
Short-circuit protection
Thermal shutdown
Small size 5 x 4 DFN-16 package
Applications
Point of load DC/DC conversion
Desktops/graphics cards
PCIe graphics cards
Set top boxes
Blu-Ray and HD-DVD–recorders
LCD TVs
Typical Application
Figure 1. 1.2V/8A Synchronous Buck Regulator
LX
VIN GOOD
VOUT
5V DC
VIN = 12V
FB
NGATE
PGND
EN
COMP
AGND
C1, C2
22µF
Ceramic
C3, C4, C5
22µF
Ceramic
R1
R2
RC
CC
L1 2.2µH
AOZ1025D
AOZ1025D
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Page 2 of 15
Ordering Information
AOS Green Products use reduced levels of Halogens, and are also RoHS compliant.
Please visit www.aosmd.com/media/AOSGreenPolicy.pdf for additional information.
Pin Configuration
Pin Description
Part Number Ambient Temperature Range Package Environmental
AOZ1025DIL -40°C to +85°C 5 x 4 DFN-16 Green Product
LX
LX
LX
NGATE
PGOOD
PGND
EN
COMP
LX
VIN
VIN
VIN
VIN
AGND
FB
NC
5 x 4 DFN-16
(Top Thru View)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
AGND
LX
Pin Number Pin Name Pin Function
1 LX PWM output connection to inductor. Thermal connection for output stage.
2, 3, 4, 5 V
IN
Supply voltage input. When VIN rises above the UVLO threshold the device starts up.
6 AGND Reference connection for controller section. Also used as thermal connection for controller
section. Electrically needs to be connected to PGND
7 FB The FB pin is used to determine the output voltage via a resistor divider between the output and
GND.
8 NC Not connected
9 COMP External loop compensation pin.
10 EN The enable pin is active high. Do not leave it open.
11 PGND Power ground. Electrically needs to be connected to AGND.
12 PGOOD Power Good. Open drain. Use resistor to pull up to 5V supply.
13 NGATE Low side MOSFET driver; Connect it to the gate of external low side MOSFET.
14, 15, 16 LX PWM output connection to inductor. Thermal connection for output stage.
AOZ1025D
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Page 3 of 15
Block Diagram
Absolute Maximum Ratings
Exceeding the Absolute Maximum ratings may damage the
device.
Note:
1. Devices are inherently ESD sensitive, handling precautions are
required. Human body model rating: 1.5k
Ω
in series with 100pF.
Recommend Operating Ratings
The device is not guaranteed to operate beyond the Maximum
Operating Ratings.
Note:
2. The value of
JA
is measured with the device mounted on 1-in
2
FR-4
board with 2oz. Copper, in a still air environment with T
A
= 25°C. The
value in any given application depends on the user's specific board
design.
500kHz/68kHz
Oscillator
AGND PGND
VIN
EN
FB
PGOOD
COMP
LX
LDRV
OTP
Internal
+5V
ILimit
PWM
Control
Logic
5V LDO
Regulator
UVLO
& POR
Softstart
Reference
& Bias
0.8V
Q1
PWM
Comp
Level
Shifter
+
FET
Driver
ISen
EAmp
+
–
+
–
Frequency
Foldback
Comparator
0.2V
+
–
+
–
+
Over Voltage
Comparator
0.72V +
–
0.96V
0.86V
+
–
Parameter Rating
Supply Voltage (V
IN
) 18V
LX to AGND -0.7V to V
IN
+0.3V
EN to AGND -0.3V to V
IN
+0.3V
FB to AGND -0.3V to 6V
COMP to AGND -0.3V to 6V
PGND to AGND -0.3V to +0.3V
Junction Temperature (T
J
) +150°C
Storage Temperature (T
S
) -65°C to +150°C
ESD Rating
(1)
2kV
Parameter Rating
Supply Voltage (V
IN
) 4.75V to 16V
Output Voltage Range 0.8V to V
IN
Ambient Temperature (T
A
) -40°C to +85°C
Package Thermal Resistance
5 x 4 DFN-16 (
JA
)
(2
)
50°C/W
Package Thermal Resistance
5 x 4 DFN-16 (
JC
)
(2
)
5°C/W
AOZ1025D
Rev. 1.4 June 2012
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Page 4 of 15
Electrical Characteristics
T
A
= 25°C, V
IN
= V
EN
= 12V, V
OUT
= 1.2V unless otherwise specified
(3
)
Note:
3. Specification in BOLD indicate an ambient temperature range of -40°C to +85°C. These specifications are guaranteed by design.
Symbol Parameter Conditions Min. Typ. Max. Units
V
IN
Supply Voltage 4.75 16 V
V
UVLO
Input Under-Voltage Lockout Threshold V
IN
Rising
V
IN
Falling
4.1
3.7 V
I
IN
Supply Current (Quiescent) I
OUT
= 0, VFB = 1.2V, V
EN
> 1.2V 1.2 3 mA
I
OFF
Shutdown Supply Current V
EN
= 0V 30 µA
V
FB
Feedback Voltage 0.788 0.8 0.812 V
Load Regulation 0.5 %
Line Regulation 0.2 %
I
FB
Feedback Voltage Input Current 200 nA
V
EN
EN Input Threshold Off Threshold
On Threshold 2
0.6 V
V
HYS
EN Input Hysteresis 100 mV
MODULATOR
f
O
Frequency 350 500 600 kHz
D
MAX
Maximum Duty Cycle 100 %
D
MIN
Minimum Duty Cycle 6%
Error Amplifier Voltage Gain 500 V
/ V
Error Amplifier Transconductance 200 µA
/
V
PROTECTION
I
LIM
Current Limit 10 A
Over-Temperature Shutdown Limit T
J
Rising
T
J
Falling
150
100 °C
V
PR
Output Over-voltage Protection Threshold Off Threshold
On Threshold
960
860 mV
t
SS
Soft Start Interval 3 4 6.5 ms
POWER GOOD
V
OLPG
PG LOW Voltage I
OL
= 1mA 0.5 V
PG Leakage 1µA
V
PGL
PG Threshold Voltage -12 -10 -8 %
PG Threshold Voltage Hysteresis 3 %
PG Delay Time 128 µs
OUTPUT STAGE
High-Side Switch On-Resistance V
IN
= 12V 43 57 m
Ω
LOW SIDE DRIVER
Pull-up Resistance 20
Ω
Pull-up Resistance 7
Ω
AOZ1025D
Rev. 1.4 June 2012
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Page 5 of 15
Maximum Output Current
Maximum output current of buck converters such as AOZ1025D is related with driving capability and thermal condition.
AOZ1025D’s driving voltage varies with the input voltage. When input voltage is higher than 6.5V, the driver inside the
AOZ1025D can drive both high side and low side MOSFETs to deliver 8A output current; but when the input voltage is
5V, the recommended maximum output current is de-rated to 6A.
The output voltage within a fixed input voltage directed determines the turn-on ratio of integrated PMOS, and thus the
thermal condition of AOZ1025D during the operation. The following diagrams show the safe operation region of
AOZ1025 operating at VIN = 5V, and VIN = 12V respectively.
Input Voltage Vs. Maximum Output Current
AOZ1025D’s driving voltage varies with the input voltage.þWhen input voltage is higher than 6.5V, the driver inside the
AOZ1025D can drive both high side and low side MOSFETs to deliver 8A output current; but when the input voltage is
5V, the recommended maximum output current is de-rated to 6A.þThe following diagram shows relations of the input
voltage and the maximum output current of AOZ1025D.
0
1
2
3
4
5
6
7
8
9
0.8 1.3 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3
0
1
2
3
4
5
6
7
0.8 1.3 1.8 2.3 2.8 3.3 3.8
VIN = 12V Safe Operation Region
Output Voltage (V)
Output Current (A)
VIN = 5V Safe Operation Region
Output Voltage (V)
Output Current (A)
2
3
4
5
6
7
8
9
56 7 8 9 10 11 12 13 14 15 16
Input Voltage vs. Maximum Output Current
Voltage (V)
Current (A)
Rev. 1.4 June 2012
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Page 6 of 15
AOZ1025D
Efficiency
The efficiency was measured based on Figure 1 with the low-side external MOSFET (AO4722).
70
75
80
85
90
95
100
Efficiency
(VIN = 5V)
01234
VO = 1.1V
VO = 1.8V
VO = 3.3V
VO = 1.1V
VO = 1.8V
VO = 3.3V
VO = 5.0V
56
Current (A)
Efficiency (%)
70
75
80
85
90
95
100
Efficiency
(VIN = 12V)
012345678
Current (A)
Efficiency (%)
70
75
80
85
90
95
100
Efficiency
(VIN = 5V)
01234
VO = 1.1V
VO = 1.8V
VO = 3.3V
VO = 1.1V
VO = 1.8V
VO = 3.3V
VO = 5.0V
56
Current (A)
Efficiency (%)
70
75
80
85
90
95
100
Efficiency
(VIN = 12V)
012345678
Current (A)
Efficiency (%)
Rev. 1.4 June 2012
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Page 7 of 15
AOZ1025D
Detailed Description
The AOZ1025D is a current-mode step down regulator
with integrated high-side PMOS switch. It operates from
a 4.75V to 16V input voltage range and supplies up to 8A
of load current. The duty cycle can be adjusted from 6%
to 100% allowing a wide range of output voltage.
Features include enable control, Power-On Reset, input
under voltage lockout, output over voltage protection,
fixed internal soft-start and thermal shut down.
Enable and Soft Start
The AOZ1025D has internal soft start feature to limit
in-rush current and ensure the output voltage ramps up
smoothly to regulation voltage. A soft start process
begins when the input voltage rises to 4.0V and voltage
on EN pin is HIGH. In soft start process, the output
voltage is ramped to regulation voltage in typically 4ms.
The 4ms soft start time is set internally.
The voltage on EN pin must rise above 1.8V to enable
the AOZ1025D. When voltage on EN pin falls below
0.6V, the AOZ1025D is disabled.
Steady-State Operation
Under steady-state conditions, the converter operates
in fixed frequency and Continuous-Conduction Mode
(CCM).
The AOZ1025D integrates an internal P-MOSFET as the
high-side switch. Inductor current is sensed by amplifying
the voltage drop across the drain to source of the high
side power MOSFET. Output voltage is divided down by
the external voltage divider at the FB pin. The difference
of the FB pin voltage and reference is amplified by the
internal transconductance error amplifier. The error
voltage, which shows on the COMP pin, is compared
against the current signal, which is sum of inductor
current signal and ramp compensation signal, at PWM
comparator input. If the current signal is less than the
error voltage, the internal high-side switch is on. The
inductor current flows from the input through the inductor
to the output. When the current signal exceeds the error
voltage, the high-side switch is off. The inductor current is
freewheeling through the external low-side N-MOSFET
switch to output. The internal adaptive FET driver
guarantees no turn on overlap of both high-side and
low-side switch.
The AOZ1025D uses an external freewheeling
NMOSFET to realize synchronous rectification. It greatly
improves the converter efficiency and reduces power
loss in the low-side switch.
The AOZ1025D uses a P-Channel MOSFET as the
high-side switch. It saves the bootstrap capacitor
normally seen in a circuit which is using an NMOS
switch.
Switching Frequency
The AOZ1025D switching frequency is fixed and set by
an internal oscillator. The practical switching frequency
could range from 350 kHz to 600 kHz due to device
variation.
Output Voltage Programming
Output voltage can be set by feeding back the output to
the FB pin by using a resistor divider network. In the
application circuit shown in Figure 1. The resistor divider
network includes R1 and R2. Usually, a design is started
by picking a fixed R2 value and calculating the required
R1 with equation:
Some standard value of R1, R2 and most used output
voltage values are listed in Table 1.
Table 1.
The combination of R1 and R2 should be large enough to
avoid drawing excessive current from the output, which
will cause power loss.
VO (V) R1 (k
Ω
) R2 (k
Ω
)
0.8 1.0 Open
1.2 4.99 10
1.5 10 11.5
1.8 12.7 10.2
2.5 21.5 10
3.3 31.6 10
5.0 52.3 10
VO0.8 1 R1
R2
-------
+



=
AOZ1025D
Rev. 1.4 June 2012
www.aosmd.com
Page 8 of 15
Protection Features
The AOZ1025D has multiple protection features to
prevent system circuit damage under abnormal
conditions.
Over Current Protection (OCP)
The sensed inductor current signal is also used for over
current protection. Since the AOZ1025D employs peak
current mode control, the COMP pin voltage is propor-
tional to the peak inductor current. The COMP pin
voltage is limited to be between 0.4V and 2.5V internally.
The peak inductor current is automatically limited cycle
by cycle.
When the output is shorted to ground under fault
conditions, the inductor current decays very slow during
a switching cycle because of VO = 0V. To prevent
catastrophic failure, a secondary current limit is designed
inside the AOZ1025D. The measured inductor current is
compared against a preset voltage which represents the
current limit. When the output current is more than
current limit, the high side switch will be turned off and
EN pin will be pulled down. The converter will initiate a
soft start once the over-current condition disappears.
Output Over Voltage Protection (OVP)
The AOZ1025D monitors the feedback voltage: when
the feedback voltage is higher than 960mV, it immediate
turns-off the PMOS to protect the output voltage
overshoot at fault condition. When feedback voltage is
lower than 840mV, the PMOS is allowed to turn on in the
next cycle.
Under-voltage Lock-out (UVLO)
A power-on reset circuit monitors the input voltage.
When the input voltage exceeds 4V, the converter starts
operation. When input voltage falls below 3.7V, the
converter will be shut down.
Thermal Protection
An internal temperature sensor monitors the junction
temperature. It shuts down the internal control circuit and
high side PMOS if the junction temperature exceeds
150°C. The regulator will restart automatically under the
control of soft-start circuit when the junction temperature
decreases to 100°C.
Power Good
The output of Power-Good is an open drain N-channel
MOSFET, which supplies an active high power good
stage. A pull-up resistor should connect this pin to a
DC power trail with maximum voltage no higher than 6V.
The AOZ1025D monitors the FB voltage: when FB pin
voltage is lower than 90% of the normal voltage,
N-channel MOSFET turns on and the Power-Good pin
is pulled low, which indicates the power is abnormal.
Application Information
The basic AOZ1025D application circuit is show in
Figure 1. Component selection is explained below.
Input Capacitor
The input capacitor must be connected to the VIN pin and
PGND pin of AOZ1025D to maintain steady input voltage
and filter out the pulsing input current. The voltage rating
of input capacitor must be greater than maximum input
voltage plus ripple voltage.
The input ripple voltage can be approximated by
equation below:
Since the input current is discontinuous in a buck
converter, the current stress on the input capacitor is
another concern when selecting the capacitor. For a buck
circuit, the RMS value of input capacitor current can be
calculated by:
if we let m equal the conversion ratio:
The relationship between the input capacitor RMS
current and voltage conversion ratio is calculated and
shown in Figure 2. It can be seen that when VO is half of
VIN, CIN is under the worst current stress. The worst
current stress on CIN is 0.5 x IO.
Figure 2. I
CIN
vs. Voltage Conversion Ratio
VIN
IO
fC
IN
----------------- 1VO
VIN
---------
–



VO
VIN
---------
=
ICIN_RMS IO
VO
VIN
---------1VO
VIN
---------
–



=
VO
VIN
---------m=
0
0.1
0.2
0.3
0.4
0.5
0 0.5 1
m
I
CIN_RMS
(m)
I
O
AOZ1025D
Rev. 1.4 June 2012
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Page 9 of 15
For reliable operation and best performance, the input
capacitors must have current rating higher than ICIN_RMS
at worst operating conditions. Ceramic capacitors are
preferred for input capacitors because of their low ESR
and high current rating. Depending on the application
circuits, other low ESR tantalum capacitor may also be
used. When selecting ceramic capacitors, X5R or X7R
type dielectric ceramic capacitors should be used for
their better temperature and voltage characteristics.
Note that the ripple current rating from capacitor
manufactures are based on certain amount of life time.
Further de-rating may be necessary in practical design.
Inductor
The inductor is used to supply constant current to output
when it is driven by a switching voltage. For given input
and output voltage, inductance and switching frequency
together decide the inductor ripple current, which is:
The peak inductor current is:
High inductance gives low inductor ripple current but
requires larger size inductor to avoid saturation. Low
ripple current reduces inductor core losses. It also
reduces RMS current through inductor and switches,
which results in less conduction loss. Usually, peak to
peak ripple current on inductor is designed to be 20%
to 40% of output current.
When selecting the inductor, make sure it is able to
handle the peak current without saturation even at the
highest operating temperature.
The inductor takes the highest current in a buck circuit.
The conduction loss on inductor need to be checked for
thermal and efficiency requirements.
Surface mount inductors in different shape and styles are
available from Coilcraft, Elytone and Murata. Shielded
inductors are small and radiate less EMI noise. But they
cost more than unshielded inductors. The choice
depends on EMI requirement, price and size.
Output Capacitor
The output capacitor is selected based on the DC output
voltage rating, output ripple voltage specification and
ripple current rating.
The selected output capacitor must have a higher rated
voltage specification than the maximum desired output
voltage including ripple. De-rating needs to be
considered for long term reliability.
Output ripple voltage specification is another important
factor for selecting the output capacitor. In a buck con-
verter circuit, output ripple voltage is determined by
inductor value, switching frequency, output capacitor
value and ESR. It can be calculated by the equation
below:
where,
C
O
is output capacitor value, and
ESR
CO
is the equivalent series resistance of the output
capacitor.
When low ESR ceramic capacitor is used as output
capacitor, the impedance of the capacitor at the switching
frequency dominates. Output ripple is mainly caused by
capacitor value and inductor ripple current. The output
ripple voltage calculation can be simplified to:
If the impedance of ESR at switching frequency
dominates, the output ripple voltage is mainly decided by
capacitor ESR and inductor ripple current. The output
ripple voltage calculation can be further simplified to:
For lower output ripple voltage across the entire
operating temperature range, X5R or X7R dielectric type
of ceramic, or other low ESR tantalum are recommended
to be used as output capacitors.
In a buck converter, output capacitor current is
continuous. The RMS current of output capacitor is
decided by the peak to peak inductor ripple current. It
can be calculated by:
Usually, the ripple current rating of the output capacitor is
a smaller issue because of the low current stress. When
the buck inductor is selected to be very small and
inductor ripple current is high, output capacitor could be
overstressed.
IL
VO
fL
-----------1VO
VIN
---------
–



=
ILpeak IO
IL
2
--------
+=
VOILESRCO
1
8fC
O
-------------------------
+


=
VOIL
1
8fC
O
-------------------------
=
VOILESRCO
=
ICO_RMS
IL
12
----------
=
AOZ1025D
Rev. 1.4 June 2012
www.aosmd.com
Page 10 of 15
Loop Compensation
The AOZ1025D employs peak current mode control for
easy use and fast transient response. Peak current mode
control eliminates the double pole effect of the output
L&C filter. It greatly simplifies the compensation loop
design.
With peak current mode control, the buck power stage
can be simplified to be a one-pole and one-zero system
in frequency domain. The pole is dominant pole can be
calculated by:
The zero is a ESR zero due to output capacitor and its
ESR. It is can be calculated by:
where;
C
O
is the output filter capacitor,
R
L
is load resistor value, and
ESR
CO
is the equivalent series resistance of output capacitor.
The compensation design is actually to shape the
converter control loop transfer function to get desired
gain and phase. Several different types of compensation
network can be used for the AOZ1025D. For most cases,
a series capacitor and resistor network connected to the
COMP pin sets the pole-zero and is adequate for a stable
high-bandwidth control loop.
In the AOZ1025D, FB pin and COMP pin are the
inverting input and the output of internal error amplifier.
A series R and C compensation network connected to
COMP provides one pole and one zero. The pole is:
where;
G
EA
is the error amplifier transconductance, which is 200 x 10
-6
A/V,
G
VEA
is the error amplifier voltage gain, which is 500 V/V, and
C
C
is the compensation capacitor.
The zero given by the external compensation network,
capacitor CC and resistor RC, is located at:
To design the compensation circuit, a target crossover
frequency fC for close loop must be selected. The system
crossover frequency is where control loop has unity gain.
The crossover is the also called the converter bandwidth.
Generally a higher bandwidth means faster response to
load transient. However, the bandwidth should not be too
high because of system stability concern. When
designing the compensation loop, converter stability
under all line and load condition must be considered.
Usually, it is recommended to set the bandwidth to be
equal or less than 1/10 of switching frequency. The
AOZ1025D operates at a fixed 500kHz switching
frequency. It is recommended to choose a crossover
frequency equal or less than 40kHz.
The strategy for choosing RC and CC is to set the cross
over frequency with RC and set the compensator zero
with CC. Using selected crossover frequency, fC, to calcu-
late RC:
where;
f
C
is the desired crossover frequency. For best performance,
f
C
is set to be about 1/10 of the switching frequency;
V
FB
is 0.8V,
G
EA
is the error amplifier transconductance, which is 200 x 10
-6
A/V, and
G
CS
is the current sense circuit transconductance, which is 10.8
A/V
The compensation capacitor CC and resistor RC together
make a zero. This zero is put somewhere close to the
dominate pole fp1 but lower than 1/5 of selected
crossover frequency. CC can is selected by:
The previous equation can also be simplified to:
fP1
1
2CORL
-----------------------------------
=
fZ1
1
2COESRCO
------------------------------------------------
=
fP2
GEA
2CCGVEA
-------------------------------------------
=
fZ2
1
2CCRC
-----------------------------------
=
fC40kHz=
RCfC
VO
VFB
---------- 2CO
GEA GCS
------------------------------
=
CC
1.5
2RCfP1
-----------------------------------
=
CC
CORL
RC
---------------------
=
AOZ1025D
Rev. 1.4 June 2012
www.aosmd.com
Page 11 of 15
Thermal Management and Layout
Consideration
In the AOZ1025 buck regulator circuit, the major power
dissipating components are the AOZ1025 output
inductor, and low-side NMOSFET. The total power
dissipation of converter circuit can be measured by
input power minus output power:
The power dissipation of inductor can be approximately
calculated by output current and DCR of inductor:
The power dissipation of low-side NMOSFET can be
approximately calculated by output current, Rdson, and
duty cycle (VO
/
VIN).
The actual junction temperature can be calculated with
power dissipation in the AOZ1025 and thermal
impedance from junction to ambient.
The thermal performance of the AOZ1025D is strongly
affected by the PCB layout. Extra care should be taken
by users during design to ensure that the IC will operate
under the recommended environmental conditions.
Several layout tips are listed below for the best electric
and thermal performance:
1. Do not use thermal relief connection to the VIN and
the PGND pin. Pour a maximized copper area to
the PGND pin and the VIN pin to help thermal
dissipation.
2. Input capacitor should be connected to the VIN pin
and the PGND pin as close as possible.
3. A ground plane is preferred. If a ground plane is not
used, separate PGND from AGND and connect them
only at one point to avoid the PGND pin noise
coupling to the AGND pin.
4. Make the current trace from LX pins to L to Co to the
PGND as short as possible.
5. Pour copper plane on all unused board area and
connect it to stable DC nodes, like VIN, PGND or
SGND.
6. Keep sensitive signal trace away from switching
node, LX. The copper pour area connected to the
LX pin should be as wide as possible to avoid the
switching noise on the LX pin coupling to other part
of circuit.
Ptotal_loss VIN IIN VOIO
–=
Pinductor_loss IO2Rinductor 1.1=
Pinductor_loss IO2Rinductor 1VO
VIN
---------
–



=
Tjunction Ptotal_loss Pinductor_loss
–Pnmos_loss
–
JA Tamb
+=
Figure 3. AOZ1025D (DFN 5x4) PCB Layout
AOZ1025D
Rev. 1.4 June 2012
www.aosmd.com
Page 12 of 15
Package Dimensions, DFN-16 5x4
AOZ1025D
Rev. 1.4 June 2012
www.aosmd.com
Page 13 of 15
Tape Dimensions, DFN-16 5x4
R0.40
P0
K0 A0
E
E2 D0
E1
D1
B0
Package
DFN 5x4
(12 mm)
A0 B0 K0 E E1 E2D0 D1 P0 P1 P2 T
5.30
±0.10 ±0.10
4.30
±0.10
1.20 Min.
1.50 1.50 12.00
±0.10
1.75
±0.10
5.50
±0.10
8.00
±0.20
4.00
±0.10
2.00
±0.05
0.30
Unit: mm
T
Typ.
0.20
Feeding
Direction
Tape
Leader/Trailer and Orientation
±0.30
+0.10 / –0
Trailer Tape
(300mm Min.)
Components Tape
Orientation in Pocket
Leader Tape
(500mm Min.)
AOZ1025D
Rev. 1.4 June 2012
www.aosmd.com
Page 14 of 15
Reel Dimensions, DFN-16 5x4
VIEW: C
C
0.05
3-1.8
ø96±0.2
6.45±0.05
3-ø2.9±0.05
3-ø1/8"
3-ø1/4"
8.9±0.1
11.90
14 REF
1.8
5.0
12 REF
41.5 REF
43.00
44.5±0.1
2.00
6.50
10.0
10.71
10°
3-ø3/16"
R48 REF
ø86.0±0.1
2.20
6.2
ø13.00
ø21.20
ø17.0
R1.10
R3.10
2.00
3.3
4.0
6.10
0.80
3.00
8.00
+0.05
0.00
R0.5
1.80
2.5
38°
44.5±0.1
46.0±0.1
8.0±0.1
40°
6°
3-ø3/16"
R3.95
6.50
ø90.00
6.0
1.8
1.8
R1
8.00
0.00
-0.05
N=ø100±2 A
A
A
R121
R127
R159
R6
R55
P
B
W1
M
II I
I
6.0±1
R1
Zoom In
III
Zoom In
II
Zoom In
A
AOZ1025D
Rev. 1.4 June 2012
www.aosmd.com
Page 15 of 15
Package Marking
Z1025DI
FAYWLT
Part Number Code
Underline Denotes Green Product
Assembly Lot Code
Fab & Assembly Location
Year & Week Code
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body or (b) support or sustain life, and (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of
the user.
2. A critical component in any component of a life
support, device, or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
This data sheet contains preliminary data; supplementary data may be published at a later date.
Alpha & Omega Semiconductor reserves the right to make changes at any time without notice.
LIFE SUPPORT POLICY
ALPHA & OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL
COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS.