LTC2302/LTC2306
1
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For more information www.linear.com/LTC2302
Typical applicaTion
FeaTures
applicaTions
DescripTion
Low Noise, 500ksps,
1-/2-Channel, 12-Bit ADCs
The LT C
®
2302/LTC2306 are low noise, 500ksps, 1‑/2‑chan‑
nel, 12‑bit ADCs with an SPI/MICROWIRE compatible
serial interface. These ADCs include a fully differential
sample‑and‑hold circuit to reduce common mode noise.
The internal conversion clock allows the external serial
output data clock (SCK) to operate at any frequency up
to 40MHz.
The LTC2302/LTC2306 operate from a single 5V supply
and draw just 2.8mA at a sample rate of 500ksps. The
auto‑shutdown feature reduces the supply current to 14µA
at a sample rate of 1ksps.
The LTC2302/LTC2306 are packaged in a tiny 10‑pin 3mm
× 3mm DFN. The low power consumption and small size
make the LTC2302/LTC2306 ideal for battery‑operated
and portable applications, while the 4‑wire SPI compat‑
ible serial interface makes these ADCs a good match for
isolated or remote data acquisition systems.
8192 Point FFT, fIN = 1kHz (LTC2306)
n 12-Bit Resolution
n 500ksps Sampling Rate
n Low Noise: SINAD = 72.8dB
n Guaranteed No Missing Codes
n Single 5V Supply
n Auto‑Shutdown Scales Supply Current with Sample
Rate
n Low Power: 14mW at 500ksps
70µW at 1ksps
35µW Sleep Mode
n 1‑Channel (LTC2302) and 2‑Channel (LTC2306)
Versions
n Unipolar or Bipolar Input Ranges (Software
Selectable)
n Internal Conversion Clock
n SPI/MICROWIRE Compatible Serial Interface
n Separate Output Supply OVDD (2.7V to 5.25V)
n Software Compatible with the LTC2308
n 10‑Pin (3mm × 3mm) DFN Package
n High Speed Data Acquisition
n Industrial Process Control
n Motor Control
n Accelerometer Measurements
n Battery‑Operated Instruments
n Isolated and/or Remote Data Acquisition
TYPE
NUMBER OF INPUT CHANNELS
128
Int Reference LTC2308
Ext Reference LTC2302 LTC2306
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
SDI
SDO
SCK
CONVST
23026 TA01
SERIAL
PORT
ANALOG
INPUT
MUX
CH0 (IN+)
CH1 (IN–)
ANALOG INPUTS
0V TO 4.096V UNIPOLAR
±2.048V BIPOLAR
VREF
2.7V TO 5.25V
SERIAL DATA LINK TO
ASIC, PLD, MPU, DSP
OR SHIFT REGISTER
LTC2302
LTC2306
VDD OVDD
GND
0.1µF
5V
12-BIT
500ksps
ADC
+
–
0.1µF
PIN NAMES IN PARENTHESIS
REFER TO LTC2302 10µF0.1µF
10µF
FREQUENCY (kHz)
0
–40
–20
0
200
23026 TA01b
–60
–80
50 100 150 250
–100
–120
–50
–30
–10
–70
–90
–110
–130
–140
MAGNITUDE (dB)
fSMPL = 500kHz
SINAD = 72.8dB
THD = –88.7dB
LTC2302/LTC2306
2
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For more information www.linear.com/LTC2302
absoluTe MaxiMuM raTings
Supply Voltage (VDD, OVDD) ........................–0.3V to 6V
Analog Input Voltage (Note 3)
CH0(IN+)‑CH1(IN–),
REF ..............................(GND – 0.3V) to (VDD + 0.3V)
Digital Input Voltage
(Note 3) .............................(GND – 0.3V) to (VDD + 0.3V)
(Notes 1, 2)
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC2302CDD#PBF LTC2302CDD#TRPBF LDGV 10‑Lead (3mm × 3mm) Plastic DFN 0°C to 70°C
LTC2302IDD#PBF LTC2302IDD#TRPBF LDGV 10‑Lead (3mm × 3mm) Plastic DFN –40°C to 85°C
LTC2306CDD#PBF LTC2306CDD#TRPBF LDGW 10‑Lead (3mm × 3mm) Plastic DFN 0°C to 70°C
LTC2306IDD#PBF LTC2306IDD#TRPBF LDGW 10‑Lead (3mm × 3mm) Plastic DFN –40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
orDer inForMaTion
TOP VIEW
11
LTC2302
DD PACKAGE
10-LEAD (3mm × 3mm) PLASTIC DFN
10
9
6
7
8
4
5
3
2
1OVDD
SCK
SDI
GND
VREF
SDO
CONVST
VDD
IN+
IN–
TJMAX = 150°C, θJA = 43°C/W
EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB
TOP VIEW
11
LTC2306
DD PACKAGE
10-LEAD (3mm × 3mm) PLASTIC DFN
10
9
6
7
8
4
5
3
2
1OVDD
SCK
SDI
GND
VREF
SDO
CONVST
VDD
CH0
CH1
TJMAX = 150°C, θJA = 43°C/W
EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB
pin conFiguraTion
Digital Output Voltage ... (GND – 0.3V) to (OVDD + 0.3V)
Power Dissipation .............................................. 500mW
Operating Temperature Range
LTC2302C/LTC2306C .............................. 0°C to 70°C
LTC2302I/LTC2306I .............................–40°C to 85°C
Storage Temperature Range ..................–65°C to 150°C
LTC2302/LTC2306
3
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For more information www.linear.com/LTC2302
conVerTer anD MulTiplexer cHaracTerisTics
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN+Absolute Input Range (CH0, CH1, IN+) (Note 9) l–0.05 VREF V
VIN–Absolute Input Range (CH0, CH1, IN–) Unipolar (Note 9)
Bipolar (Note 9)
l
l
–0.05
–0.05
0.25 • VREF
0.75 • VREF
V
V
VIN+ – VIN–Input Differential Voltage Range VIN = VIN+ – VIN– (Unipolar)
VIN = VIN+ – VIN– (Bipolar)
l
l
0 to VREF
±VREF/2
V
V
IIN Analog Input Leakage Current l±1 µA
CIN Analog Input Capacitance Sample Mode
Hold Mode
55
5
pF
pF
CMRR Input Common Mode Rejection Ratio 70 dB
The l denotes the specifications
which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 4, 5)
PARAMETER CONDITIONS MIN TYP MAX UNITS
Resolution (No Missing Codes) l12 Bits
Integral Linearity Error (Note 6) l±0.3 ±1 LSB
Differential Linearity Error l±0.25 ±1 LSB
Bipolar Zero Error (Note 7) l±1 ±6 LSB
Bipolar Zero Error Drift 0.002 LSB/°C
Unipolar Zero Error (Note 7) l±1 ±6 LSB
Unipolar Zero Error Drift 0.002 LSB/°C
Unipolar Zero Error Match (LTC2306) ±0.3 ±3 LSB
Bipolar Full‑Scale Error (Note 8) l±1.5 ±8 LSB
Bipolar Full‑Scale Error Drift 0.05 LSB/°C
Unipolar Full‑Scale Error (Note 8) l±1.2 ±6 LSB
Unipolar Full‑Scale Error Drift 0.05 LSB/°C
Unipolar Full‑Scale Error Match (LTC2306) ±0.3 ±3 LSB
analog inpuT
The l denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VREF Input Range l0.1 VDD V
IREF Reference Input Current fSMPL = 0ksps, VREF = 4.096V
fSMPL = 500ksps, VREF = 4.096V
l
l
50
230
80
260
µA
µA
CREF Reference Input Capacitance 55 pF
reFerence inpuT
The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. (Note 4)
LTC2302/LTC2306
4
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For more information www.linear.com/LTC2302
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIH High Level Input Voltage VDD = 5.25V l2.4 V
VIL Low Level Input Voltage VDD = 4.75V l0.8 V
IIN High Level Input Current VIN = VDD l±10 µA
CIN Digital Input Capacitance 5 pF
VOH High Level Output Voltage OVDD = 4.75V, IOUT = –10µA
OVDD = 4.75V, IOUT = –200µA
l
4
4.74 V
V
VOL Low Level Output Voltage OVDD = 4.75V, IOUT = 160µA
OVDD = 4.75V, IOUT = 1.6mA
l
0.05
0.4
V
V
IOZ Hi‑Z Output Leakage VOUT = 0V to OVDD, CONVST High l±10 µA
COZ Hi‑Z Output Capacitance CONVST High 15 pF
ISOURCE Output Source Current VOUT = 0V –10 mA
ISINK Output Sink Current VOUT = OVDD 10 mA
DigiTal inpuTs anD DigiTal ouTpuTs
The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VDD Supply Voltage l4.75 5 5.25 V
OVDD Output Driver Supply Voltage l2.7 5.25 V
IDD Supply Current
Sleep Mode
CL = 25pF
CONVST = 5V, Conversion Done
l
l
2.8
7
3.5
15
mA
µA
PDPower Dissipation
Sleep Mode
14
35
mW
µW
poWer reQuireMenTs
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
SINAD Signal‑to‑(Noise + Distortion) Ratio fIN = 1kHz l71 72.8 dB
SNR Signal‑to‑Noise Ratio fIN = 1kHz l71 73.2 dB
THD Total Harmonic Distortion fIN = 1kHz, First 5 Harmonics l–88 –78 dB
SFDR Spurious Free Dynamic Range fIN = 1kHz l79 89 dB
Channel‑to‑Channel Isolation fIN = 1kHz –109 dB
Full Linear Bandwidth (Note 11) 700 kHz
–3dB Input Linear Bandwidth 25 MHz
Aperture Delay 13 ns
Transient Response Full‑Scale Step 240 ns
DynaMic accuracy
The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Notes 4, 10)
LTC2302/LTC2306
5
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For more information www.linear.com/LTC2302
TiMing cHaracTerisTics
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSMPL(MAX) Maximum Sampling Frequency l500 kHz
fSCK Shift Clock Frequency l40 MHz
tWHCONV CONVST High Time (Note 9) l20 ns
tHD Hold Time SDI After SCK↑l2.5 ns
tSUDI Setup Time SDI Stable Before SCK↑l0 ns
tWHCLK SCK High Time fSCK = fSCK(MAX) l10 ns
tWLCLK SCK Low Time fSCK = fSCK(MAX) l10 ns
tWLCONVST CONVST Low Time During Data Transfer (Note 9) l410 ns
tHCONVST Hold Time CONVST Low After Last SCK↓(Note 9) l20 ns
tCONV Conversion Time l1.3 1.6 µs
tACQ Acquisition Time 7th SCK↑ to CONVST↑ (Note 9) l240 ns
tdDO SDO Data Valid After SCK↓CL = 25pF (Note 9) l10.8 12.5 ns
thDO SDO Hold Time SCK↓CL = 25pF l4 ns
ten SDO Valid After CONVST↓CL = 25pF l11 15 ns
tdis Bus Relinquish Time CL = 25pF l11 15 ns
trSDO Rise Time CL = 25pF 4 ns
tfSDO Fall Time CL = 25pF 4 ns
tCYC Total Cycle Time 2 µs
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground with VDD
and OVDD
wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below ground or above VDD,
they will be clamped by internal diodes. These products can handle input
currents greater than 100mA below ground or above VDD without latchup.
Note 4: VDD = 5V, OVDD = 5V, VREF = 4.096V, fSMPL = 500ksps, unless
otherwise specified.
Note 5: Linearity, offset and full‑scale specifications apply for a single‑
ended analog input with respect to GND for the LTC2306 and IN+ with
respect to IN– tied to GND for the LTC2302.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7: Bipolar zero error is the offset voltage measured from –0.5LSB
when the output code flickers between 0000 0000 0000 and 1111 1111
1111. Unipolar zero error is the offset voltage measured from +0.5LSB
when the output code flickers between 0000 0000 0000 and 0000 0000
0001.
Note 8: Full‑scale bipolar error is the worst‑case of –FS or +FS untrimmed
deviation from ideal first and last code transitions and includes the effect
of offset error. Unipolar full‑scale error is the deviation of the last code
transition from ideal and includes the effect of offset error.
Note 9: Guaranteed by design, not subject to test.
Note 10: All specifications in dB are referred to a full‑scale ±2.048V input
with a 4.096V reference voltage.
Note 11: Full linear bandwidth is defined as the full‑scale input frequency
at which the SINAD degrades to 60dB or 10 bits of accuracy.
LTC2302/LTC2306
6
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For more information www.linear.com/LTC2302
Typical perForMance cHaracTerisTics
Integral Nonlinearity
vs Output Code
Differential Nonlinearity
vs Output Code
1kHz Sine Wave
8192 Point FFT Plot
SNR vs Input Frequency SINAD vs Input Frequency THD vs Input Frequency
Supply Current
vs Sampling Frequency Supply Current vs Temperature
(LTC2302) TA = 25°C, VDD = OVDD = 5V, VREF = 4.096V, fSMPL = 500ksps, unless otherwise noted.
OUTPUT CODE
0
INL (LSB)
0
0.25
0.50
4096
23026 G01
–0.25
–0.50
–1.00 1024 2048 3072
–0.75
1.00
0.75
OUTPUT CODE
0
DNL (LSB)
0
0.25
0.50
4096
23026 G02
–0.25
–0.50
–1.00 1024 2048 3072
–0.75
1.00
0.75
FREQUENCY (kHz)
0
–40
–20
0
200
23026 G03
–60
–80
50 100 150 250
–100
–120
–50
–30
–10
–70
–90
–110
–130
–140
MAGNITUDE (dB)
SNR = 73.2dB
SINAD = 72.8dB
THD = –89.5dB
FREQUENCY (kHz)
1
50
SNR (dB)
70
75
80
10 100 1000
23026 G04
65
60
55
FREQUENCY (kHz)
1
50
SINAD (dB)
70
75
80
10 100 1000
23026 G05
65
60
55
FREQUENCY (kHz)
1
–80
THD (dB)
–70
–60
10 100 1000
23026 G06
–90
–85
–75
–65
–95
–100
SAMPLING FREQUENCY (ksps)
1
2.0
SUPPLY CURRENT (mA)
2.5
3.0
3.5
10 100 1000
23026 G07
1.5
1.0
0.5
0
TEMPERATURE (°C)
–50
2.0
SUPPLY CURRENT (mA)
2.2
2.6
2.8
3.0
4.0
3.4
050 75
23026 G08
2.4
3.6
3.8
3.2
–25 25 100 125
LTC2302/LTC2306
7
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For more information www.linear.com/LTC2302
Sleep Current vs Temperature
Typical perForMance cHaracTerisTics
Analog Input Leakage Current
vs Temperature
Offset Error vs Temperature Full-Scale Error vs Temperature
(LTC2302) TA = 25°C, VDD = OVDD = 5V, VREF = 4.096V, fSMPL = 500ksps, unless otherwise noted.
TEMPERATURE (°C)
–50
0
SLEEP CURRENT (µA)
1
3
4
5
10
7
050 75
23026 G09
2
8
9
6
–25 25 100 125
TEMPERATURE (°C)
–50
0
INPUT LEAKAGE CURRENT (nA)
100
300
400
500
1000
700
050 75
23026 G10
200
800
900
600
–25 25 100 125
TEMPERATURE (°C)
–50
–1.0
–1.5
–2.0
–2.5
OFFSET ERROR (LSB)
–0.5
0.5
1.0
1.5
2.5
050 75
23026 G11
0
2.0
–25 25 100 125
BIPOLAR
UNIPOLAR
TEMPERATURE (°C)
–50
FULL-SCALE ERROR (LSB)
1.5
25
23026 G12
0
–1.0
–25 0 50
–1.5
–2.0
2.0
1.0
0.5
–0.5
75 100 125
BIPOLAR
UNIPOLAR
LTC2302/LTC2306
8
23026fb
For more information www.linear.com/LTC2302
Typical perForMance cHaracTerisTics
Integral Nonlinearity
vs Output Code
Differential Nonlinearity
vs Output Code
1kHz Sine Wave
8192 Point FFT Plot
SNR vs Input Frequency SINAD vs Input Frequency THD vs Input Frequency
Supply Current
vs Sampling Frequency Supply Current vs Temperature
(LTC2306) TA = 25°C, VDD = OVDD = 5V, VREF = 4.096V, fSMPL = 500ksps, unless otherwise noted.
OUTPUT CODE
0
INL (LSB)
0
0.25
0.50
4096
23026 G13
–0.25
–0.50
–1.00 1024 2048 3072
–0.75
1.00
0.75
OUTPUT CODE
0
DNL (LSB)
0
0.25
0.50
4096
23026 G14
–0.25
–0.50
–1.00 1024 2048 3072
–0.75
1.00
0.75
FREQUENCY (kHz)
0
–40
–20
0
200
23026 G15
–60
–80
50 100 150 250
–100
–120
–50
–30
–10
–70
–90
–110
–130
–140
MAGNITUDE (dB)
SNR = 73.2dB
SINAD = 72.8dB
THD = –88.7dB
FREQUENCY (kHz)
1
50
SNR (dB)
70
75
80
10 100 1000
23026 G16
65
60
55
FREQUENCY (kHz)
1
50
SINAD (dB)
70
75
80
10 100 1000
23026 G17
65
60
55
FREQUENCY (kHz)
1
–80
THD (dB)
–70
–60
10 100 1000
23026 G18
–90
–85
–75
–65
–95
–100
SAMPLING FREQUENCY (ksps)
1
2.0
SUPPLY CURRENT (mA)
2.5
3.0
3.5
10 100 1000
23026 G19
1.5
1.0
0.5
0
TEMPERATURE (°C)
–50
2.0
SUPPLY CURRENT (mA)
2.2
2.6
2.8
3.0
4.0
3.4
050 75
23026 G20
2.4
3.6
3.8
3.2
–25 25 100 125
LTC2302/LTC2306
9
23026fb
For more information www.linear.com/LTC2302
Sleep Current vs Temperature
Typical perForMance cHaracTerisTics
Analog Input Leakage Current
vs Temperature
Offset Error vs Temperature Full-Scale Error vs Temperature
(LTC2306) TA = 25°C, VDD = OVDD = 5V, VREF = 4.096V, fSMPL = 500ksps, unless otherwise noted.
TEMPERATURE (°C)
–50
0
SLEEP CURRENT (µA)
1
3
4
5
10
7
050 75
23026 G21
2
8
9
6
–25 25 100 125
TEMPERATURE (°C)
–50
0
INPUT LEAKAGE CURRENT (nA)
100
300
400
500
1000
700
050 75
23026 G22
200
800
900
600
–25 25 100 125
TEMPERATURE (°C)
–50
OFFSET ERROR (LSB)
1.5
25
23026 G23
0
–1.0
–25 0 50
–1.5
–2.0
2.0
1.0
0.5
–0.5
75 100 125
BIPOLAR
UNIPOLAR
TEMPERATURE (°C)
–50
FULL-SCALE ERROR (LSB)
1.5
25
23026 G24
0
–1.0
–25 0 50
–1.5
–2.0
2.0
1.0
0.5
–0.5
75 100 125
BIPOLAR
UNIPOLAR
LTC2302/LTC2306
10
23026fb
For more information www.linear.com/LTC2302
pin FuncTions
LTC2302
SDO (Pin 1): Three‑State Serial Data Out. SDO outputs
the data from the previous conversion. SDO is shifted
out serially on the falling edge of each SCK pulse. SDO is
enabled by a low level on CONVST.
CONVST (Pin 2): Conversion Start. A rising edge at
CONVST begins a conversion. For best performance,
ensure that CONVST returns low within 40ns after the
conversion starts or after the conversion ends.
VDD (Pin 3): 5V Supply. The range of VDD is 4.75V to 5.25V.
Bypass VDD to GND with a 0.1µF ceramic capacitor and a
10µF tantalum capacitor in parallel.
IN+, IN– (Pin 4, Pin 5): Positive (IN+) and Negative (IN–)
Differential Analog Inputs.
VREF (Pin 6): Reference Input. Connect an external refer‑
ence at VREF
. The range of the external reference is 0.1V
to VDD. Bypass to GND with a minimum 10µF tantalum
capacitor in parallel with a 0.1µF ceramic capacitor.
GND (Pin 7): Ground. All GND pins must be connected to
a solid ground plane.
SDI (Pin 8): Serial Data Input. The SDI serial bit stream
configures the ADC and is latched on the rising edge of
the first 6 SCK pulses.
SCK (Pin 9): Serial Data Clock. SCK synchronizes the
serial data transfer. The serial data input at SDI is latched
on the rising edge of SCK. The serial data output at SDO
transitions on the falling edge of SCK.
OVDD (Pin 10): Output Driver Supply. Bypass OVDD to
GND with a 0.1µF ceramic capacitor close to the pin. The
range of OVDD is 2.7V to 5.25V.
Exposed Pad (Pin 11): Exposed Pad Ground. Must be
soldered directly to ground plane.
LTC2306
SDO (Pin 1): Three‑State Serial Data Out. SDO outputs
the data from the previous conversion. SDO is shifted
out serially on the falling edge of each SCK pulse. SDO is
enabled by a low level on CONVST.
CONVST (Pin 2): Conversion Start. A rising edge at
CONVST begins a conversion. For best performance,
ensure that CONVST returns low within 40ns after the
conversion starts or after the conversion ends
.
VDD (Pin 3): 5V Supply. The range of VDD is 4.75V to 5.25V.
Bypass VDD to GND with a 0.1µF ceramic capacitor and a
10µF tantalum capacitor in parallel.
CH0, CH1 (Pin 4, Pin 5): Channel 0 and Channel 1 Analog
Inputs. CH0, CH1 can be configured as single‑ended or
differential input channels. See the Analog Input Multi‑
plexer section.
VREF (Pin 6): Reference Input. Connect an external refer‑
ence at VREF
.The range of the external reference is 0.1V
to VDD. Bypass to GND with a minimum 10µF tantalum
capacitor in parallel with a 0.1µF ceramic capacitor.
GND (Pin 7): Ground. All GND pins must be connected to
a solid ground plane.
SDI (Pin 8): Serial Data Input. The SDI serial bit stream
configures the ADC and is latched on the rising edge of
the first 6 SCK pulses.
SCK (Pin 9): Serial Data Clock. SCK synchronizes the
serial data transfer. The serial data input at SDI is latched
on the rising edge of SCK. The serial data output at SDO
transitions on the falling edge of SCK.
OVDD (Pin 10): Output Driver Supply. Bypass OVDD to
OGND with a 0.1µF ceramic capacitor close to the pin.
The range of OVDD is 2.7V to 5.5V.
Exposed Pad (Pin 11): Exposed Pad Ground. Must be
soldered directly to ground plane.
LTC2302/LTC2306
11
23026fb
For more information www.linear.com/LTC2302
block DiagraM
TesT circuiTs
Load Circuit for tdis Waveform 1 Load Circuit for tdis Waveform 2, ten
SDI
SDO
SCK
CONVST
23026 BD
SERIAL
PORT
ANALOG
INPUT
MUX
CH0 (IN+)
CH1 (IN–)
VREF
LTC2302
LTC2306
PIN NAMES IN PARENTHESIS
REFER TO LTC2302
VDD OVDD
GND
12-BIT
500ksps
ADC
+
–
SDO TEST POINT
VDD
3k
CL
23026 TC01
SDO TEST POINT
3k CL
23026 TC02
LTC2302/LTC2306
12
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For more information www.linear.com/LTC2302
tWLCLK (SCK Low Time)
tWHCLK (SCK High Time)
tHD (Hold Time SDI After SCK↑)
tSUDI (Setup Time SDI Stable Before SCK↑)
Voltage Waveforms for ten
Voltage Waveforms for SDO Rise and Fall Times tr, tf
23026 TD03
SCK
SDI
tWLCLK tWHCLK
tHD
tSUDI
23026 TD04
CONVST
SDO
ten
SDO
trtf23004 TD05
VOH
VOL
TiMing DiagraMs
Voltage Waveforms for SDO Delay Times, tdDO and thDO Voltage Waveforms for tdis
SCK
SDO
VIL
tdDO
thDO
VOH
VOL
23026 TD01
SDO
WAVEFORM 1
(SEE NOTE 1)
VIH
tdis
90%
10%
SDO
WAVEFORM 2
(SEE NOTE 2)
CONVST
NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL
NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL
23026 TD02
LTC2302/LTC2306
13
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For more information www.linear.com/LTC2302
applicaTions inForMaTion
Overview
The LTC2302/LTC2306 are low noise, 500ksps, 1‑/2‑chan‑
nel, 12‑bit successive approximation register (SAR) A/D
converters. The LTC2306 includes a 2‑channel analog
input multiplexer (MUX) while the LTC2302 includes an
input MUX that allows the polarity of the differential input
to be selected. Both ADCs include an SPI‑compatible se‑
rial port for easy data transfers and can operate in either
unipolar or bipolar mode. Unipolar mode should be used
for single‑ended operation with the LTC2306, since single‑
ended input signals are always referenced to GND. The
LTC2302/LTC2306 can be put into a power‑down sleep
mode during idle periods to save power.
Conversions are initiated by a rising edge on the CONVST
input. Once a conversion cycle has begun, it cannot be
restarted. Between conversions, a 6‑bit input word (DIN)
at the SDI input configures the MUX and programs vari‑
ous modes of operation. As the DIN bits are shifted in,
data from the previous conversion is shifted out on SDO.
After the 6 bits of the DIN word have been shifted in, the
ADC begins acquiring the analog input in preparation for
the next conversion as the rest of the data is shifted out.
The acquire phase requires a minimum time of 240ns
for the sample‑and‑hold capacitors to acquire the analog
input signal.
During the conversion, the internal 12‑bit capacitive
charge‑redistribution DAC output is sequenced through a
successive approximation algorithm by the SAR starting
from the most significant bit (MSB) to the least significant
bit (LSB). The sampled input is successively compared with
binary weighted charges supplied by the capacitive DAC
using a differential comparator. At the end of a conver‑
sion, the DAC output balances the analog input. The SAR
contents (a 12‑bit data word) that represent the sampled
analog input are loaded into 12 output latches that allow
the data to be shifted out.
Programming the LTC2306 and LTC2302
The software compatible LTC2302/LTC2306/LTC2308
family features a 6‑bit DIN word to program various modes
of operation. Don’t care bits (X) are ignored. The SDI data
bits are loaded on the rising edge of SCK, with the S/D bit
loaded on the first rising edge (see Figure 6 in the Timing
and Control section). The input data word for the LTC2306
is defined as follows:
S/D O/S X X UNI X
S/D = SINGLE‑ENDED/DIFFERENTIAL BIT
O/S = ODD/SIGN BIT
UNI = UNIPOLAR/BIPOLAR BIT
X = DON’ T CARE
For the LTC2302, the input data word is defined as:
X O/S X X UNI X
LTC2302/LTC2306
14
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For more information www.linear.com/LTC2302
applicaTions inForMaTion
Figure 1a. Example MUX Configurations
Figure 1b. Changing the MUX Assignment “On the Fly”
Analog Input Multiplexer
The analog input MUX is programmed by the S/D and O/S
bits of the DIN word for the LTC2306 and the O/S bit of the
DIN word for the LTC2302. Table 1 and Table 2 list MUX
configurations for all combinations of the configuration
bits. Figure 1a shows several possible MUX configurations
and Figure 1b shows how the MUX can be reconfigured
from one conversion to the next.
Driving the Analog Inputs
The analog inputs of the LTC2302/LTC2306 are easy to
drive. Each of the analog inputs of the LTC2306 (CH0
and CH1) can be used as a single‑ended input relative
to GND or as a differential pair. The analog inputs of the
LTC2302 (IN+, IN–) are always configured as a differential
pair. Regardless of the MUX configuration, the “+” and “–”
inputs are sampled at the same instant. Any unwanted
signal that is common to both inputs will be reduced by
the common mode rejection of the sample‑and‑hold cir‑
cuit. The inputs draw only one small current spike while
charging the sample‑and‑hold capacitors during the acquire
mode. In conversion mode, the analog inputs draw only
a small leakage current. If the source impedance of the
driving circuit is low, the ADC inputs can be driven directly.
Otherwise, more acquisition time should be allowed for a
source with higher impedance.
CH0
CH1
(–) GND
2 Single-Ended
+
1 Differential
+ (–)+
LTC2306 LTC2306
23026 F01a
– (+){CH0
CH1
1 Differential
+ (–)
LTC2302
– (+){IN+
IN–
CH0
CH1
(–) GND
LTC2306
2nd Conversion
+
1st Conversion
++
23026 F01b
–{CH0
CH1
LTC2306
S/D
0
0
1
1
O/S
0
1
0
1
CH0
+
–
+
CH1
–
+
+
WITH RESPECT
TO GND
NOTE: UNIPOLAR MODE SHOULD BE USED
FOR SINGLE-ENDED OPERATION, SINCE INPUT
SIGNALS ARE ALWAYS REFERENCED TO GND
Table 1. Channel Configuration
for the LTC2306
O/S
0
1
IN+
+
–
IN–
–
+
Table 2. Channel Configuration
for the LTC2302
LTC2302/LTC2306
15
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For more information www.linear.com/LTC2302
applicaTions inForMaTion
Figure 2b. Analog Input Equivalent Circuit for
Large Filter Capacitances
Figure 2a. Analog Input Equivalent Circuit
Reference
A low noise, stable reference is required to ensure full
performance. The LT
®
1790 and LT6660 are adequate
for most applications. The LT6660 is available in 2.5V,
3V, 3.3V and 5V versions, and the LT1790 is available in
1.25V, 2.048V, 2.5V, 3V, 3.3V, 4.096V and 5V versions.
The exceptionally low input noise allows the input range to
be optimized for the application by changing the reference
voltage. The VREF input must be decoupled with a 10µF
capacitor in parallel with a 0.1µF capacitor, so verify that
the device providing the reference voltage is stable with
capacitive loads.
If the voltage reference is 5V and can supply 5mA, it can
be used for both VREF and VDD. VDD must be connected
to a clean analog supply, and a quiet 5V reference voltage
makes a convenient supply for this purpose.
Input Filtering
The noise and distortion of the input amplifier and other
circuitry must be considered since they will add to the ADC
noise and distortion. Therefore, noisy input circuitry should
be filtered prior to the analog inputs to minimize noise. A
simple 1‑pole RC filter is sufficient for many applications.
The analog inputs of the LTC2302/LTC2306 can be modeled
as a 55pF capacitor (CIN) in series with a 100Ω resistor
(RON) as shown in Figure 2a. CIN gets switched to the
selected input once during each conversion. Large filter
RC time constants will slow the settling of the inputs. It
is important that the overall RC time constants be short
enough to allow the analog inputs to completely settle to
12‑bit resolution within the acquisition time (tACQ) if DC
accuracy is important.
When using a filter with a large CFILTER value (e.g., 1µF),
the inputs do not completely settle and the capacitive in‑
put switching currents are averaged into a net DC current
(IDC). In this case, the analog input can be modeled by an
equivalent resistance (REQ = 1/(fSMPL • CIN)) in series with
an ideal voltage source (VREF/2) as shown in Figure 2b.
The magnitude of the DC current is then approximately
IDC = (VIN – VREF/2)/REQ, which is roughly proportional
to VIN. To prevent large DC drops across the resistor
RFILTER, a filter with a small resistor and large capacitor
should be chosen. When running at the minimum cycle
time of 2µs, the input current equals 106µA at VIN = 5V,
which amounts to a full‑scale error of 0.5LSB when using
a filter resistor (RFILTER) of 4.7Ω. Applications requiring
lower sample rates can tolerate a larger filter resistor for
the same amount of full‑scale error.
CIN
55pF
RON
100Ω
RSOURCE
VIN
LTC2302
LTC2306
INPUT
(CH0, CH1
IN+, IN–)
C1
23026 F02a
REQ
1/(fSMPL • CIN)
VREF/2
RFILTER IDC
VIN
LTC2302
LTC2306
INPUT
(CH0, CH1
IN+, IN–)
CFILTER
23026 F02b
+
–
LTC2302/LTC2306
16
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For more information www.linear.com/LTC2302
applicaTions inForMaTion
Figure 3a. Optional RC Input Filtering for Single-Ended Input
Figure 3b. Optional RC Input Filtering for Differential Inputs
Figure 4. 1kHz Sine Wave 8192 Point FFT Plot (LTC2306)
Figures 3a and 3b show respective examples of input
filtering for single‑ended and differential inputs. For the
single‑ended case in Figure 3a, a 50Ω source resistor
and a 2000pF capacitor to ground on the input will limit
the input bandwidth to 1.6MHz. High quality capacitors
and resistors should be used in the RC filter since these
components can add distortion. NPO and silver mica type
dielectric capacitors have excellent linearity. Carbon surface
mount resistors can generate distortion from self heating
and from damage that may occur during soldering. Metal
film surface mount resistors are much less susceptible
to both problems.
Dynamic Performance
FFT (fast Fourier transform) test techniques are used to
test the ADC’s frequency response, distortion and noise
at the rated throughput. By applying a low distortion
sine wave and analyzing the digital output using an FFT
algorithm, the ADC’s spectral content can be examined
for frequencies outside the fundamental.
Signal-to-Noise and Distortion Ratio (SINAD)
The signal‑to‑noise and distortion ratio (SINAD) is the
ratio between the RMS amplitude of the fundamental input
frequency to the RMS amplitude of all other frequency
components at the A/D output. The output is band‑limited
to frequencies from above DC and below half the sampling
frequency. Figure 4 shows a typical SINAD of 72.8dB with
a 500kHz sampling rate and a 1kHz input. A SNR of 73.2dB
can be achieved with the LTC2302/LTC2306.
23026 F03a
CH0, CH1
LTC2306
VREF
2000pF
10µF
0.1µF
0.1µF
50Ω
ANALOG
INPUT
LT1790A-4.096
VOUT
VIN
5V
1000pF
23026 F03b
CH0, IN+
CH1, IN–
LTC2302
LTC2306
VREF
1000pF
1000pF
10µF 0.1µF
50Ω
50Ω
DIFFERENTIAL
ANALOG
INPUTS
0.1µF
LT1790A-4.096
VOUT
VIN
5V
Total Harmonic Distortion (THD)
Total Harmonic Distortion (THD) is the ratio of the RMS
sum of all harmonics of the input signal to the fundamental
itself. The out‑of‑band harmonics alias into the frequency
band between DC and half the sampling frequency(fSMPL/2).
THD is expressed as:
THD VVV V
V
N
=++ +
20 22324
log ...
where V1 is the RMS amplitude of the fundamental fre‑
quency and V2 through VN are the amplitudes of the second
through Nth harmonics.
FREQUENCY (kHz)
0
–40
–20
0
200
23026 F04
–60
–80
50 100 150 250
–100
–120
–50
–30
–10
–70
–90
–110
–130
–140
MAGNITUDE (dB)
SNR = 73.2dB
SINAD = 72.8dB
THD = –88.7dB
LTC2302/LTC2306
17
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For more information www.linear.com/LTC2302
applicaTions inForMaTion
Internal Conversion Clock
The internal conversion clock is factory trimmed to
achieve a typical conversion time (tCONV) of 1.3μs and a
maximum conversion time of 1.6μs over the full operating
temperature range. With a minimum acquisition time of
240ns, a throughput sampling rate of 500ksps is tested
and guaranteed.
Digital Interface
The LTC2302/LTC2306 communicate via a standard 4 ‑wire
SPI compatible digital interface. The rising edge of CONVST
initiates a conversion. After the conversion is finished, pull
CONVST low to enable the serial output (SDO). The ADC
then shifts out the digital data in 2’s complement format
when operating in bipolar mode or in straight binary format
when in unipolar mode, based on the setting of the UNI bit.
For best performance, ensure that CONVST returns low
within 40ns after the conversion starts (i.e., before the first
bit decision) or after the conversion ends. If CONVST is
low when the conversion ends, the MSB bit will appear at
SDO at the end of the conversion and the ADC will remain
powered up.
Timing and Control
The start of a conversion is triggered by the rising edge
of CONVST. Once initiated, a new conversion cannot be
restarted until the current conversion is complete. Figures 6
and 7 show the timing diagrams for two different examples
of CONVST pulses. Example 1 (Figure 6) shows CONVST
staying HIGH after the conversion ends. If CONVST is high
after the tCONV period, the LTC2302/LTC2306 enter sleep
mode (see Sleep Mode for more details).
When CONVST returns low, the ADC wakes up and the
most significant bit (MSB) of the output data sequence
at SDO becomes valid after the serial data bus is enabled.
All other data bits from SDO transition on the falling edge
of each SCK pulse. Configuration data (DIN) is loaded into
the LTC2302/LTC2306 at SDI, starting with the first SCK
rising edge after CONVST returns low. The S/D bit is loaded
on the first SCK rising edge.
Example 2 (Figure 7) shows CONVST returning low be‑
fore the conversion ends. In this mode, the ADC and all
internal circuitry remain powered up. When the conver‑
sion is complete, the MSB of the output data sequence at
SDO becomes valid after the data bus is enabled. At this
point(tCONV 1.3µs after the rising edge of CONVST), puls‑
ing SCK will shift data out at SDO and load configuration
data (DIN) into the LTC2302/LTC2306 at SDI. The first
SCK rising edge loads the S/D bit. SDO transitions on the
falling edge of each SCK pulse.
Figures 8 and 9 are the transfer characteristics for the
bipolar and unipolar modes. Data is output at SDO in 2’s
complement format for bipolar readings or in straight
binary for unipolar readings.
Sleep Mode
The ADC enters sleep mode when CONVST is held high
after the conversion is complete (tCONV). The supply
current decreases to 7μA in sleep mode between conver‑
sions, thereby reducing the average power dissipation as
the sample rate decreases. For example, the LTC2302/
LTC2306 draw an average of 14µA with a 1ksps sampling
rate. The LTC2302/LTC2306 power down all circuitry when
in sleep mode.
Board Layout and Bypassing
To obtain the best performance, a printed circuit board with
a solid ground plane is required. Layout for the printed
circuit board should ensure digital and analog signal lines
are separated as much as possible. Care should be taken
not to run any digital signal alongside an analog signal. All
analog inputs should be shielded by GND. VREF and VDD
should be bypassed to the ground plane as close to the
pin as possible. Maintaining a low impedance path for the
common return of these bypass capacitors is essential to
the low noise operation of the ADC. These traces should be
as wide as possible. See Figure 5 for a suggested layout.
LTC2302/LTC2306
18
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For more information www.linear.com/LTC2302
applicaTions inForMaTion
Figure 5. Suggested Layout
Figure 6. LTC2302/LTC2306 Timing with a Long CONVST Pulse
UNIO/SS/D
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
tCONV
CONVST
SCK
SDI
SDO Hi-ZHi-Z
23026 F06
MSB LSB
tACQ
tWLCONVST
tCYC
123456789101112
S/D BIT IS A DON’T CARE (X) FOR THE LTC2302
SLEEP
VDD, BYPASS
0.1µF||10µF, 0603
INPUT FILTER
CAPACITORS
OVDD, BYPASS
0.1µF, 0603
23026 F05
VREF, BYPASS
0.1µF||10µF 0603
SOLID GROUND
PLANE
LTC2302/LTC2306
19
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For more information www.linear.com/LTC2302
applicaTions inForMaTion
Figure 7. LTC2302/LTC2306 Timing with a Short CONVST Pulse
S/D BIT IS A DON’T CARE (X) FOR THE LTC2302
UNIO/SS/D
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
tCONV
CONVST
SCK
SDI
SDO Hi-ZHi-Z
23026 F07
MSB LSB
tACQ
tHCONVST
tCYC
123456789101112
tWHCONV
Figure 8. LTC2302/LTC2306 Bipolar Transfer Characteristics
(2’s Complement)
Figure 9. LTC2302/LTC2306 Unipolar Transfer Characteristics
(Straight Binary)
INPUT VOLTAGE (V)
0V
OUTPUT CODE (TWO’S COMPLEMENT)
–1
LSB
23026 F08
011...111
011...110
000...001
000...000
100...000
100...001
111...110
1
LSB
BIPOLAR
ZERO
111...111
FS/2 – 1LSB–FS/2
FS = 4.096V
1LSB = FS/2N
1LSB = 1mV
INPUT VOLTAGE (V)
OUTPUT CODE
20026 F09
111...111
111...110
100...001
100...000
000...000
000...001
011...110
011...111
FS – 1LSB0V
UNIPOLAR
ZERO
FS = 4.096V
1LSB = FS/2N
1LSB = 1mV
LTC2302/LTC2306
20
23026fb
For more information www.linear.com/LTC2302
Please refer to http://www.linear.com/product/LTC2302#packaging for the most recent package drawings.
package DescripTion
3.00 ±0.10
(4 SIDES)
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
0.40 ±0.10
BOTTOM VIEW—EXPOSED PAD
1.65 ±0.10
(2 SIDES)
0.75 ±0.05
R = 0.125
TYP
2.38 ±0.10
(2 SIDES)
15
106
PIN 1
TOP MARK
(SEE NOTE 6)
0.200 REF
0.00 – 0.05
(DD) DFN REV C 0310
0.25 ±0.05
2.38 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
1.65 ±0.05
(2 SIDES)2.15 ±0.05
0.50
BSC
0.70 ±0.05
3.55 ±0.05
PACKAGE
OUTLINE
0.25 ±0.05
0.50 BSC
DD Package
10-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1699 Rev C)
PIN 1 NOTCH
R = 0.20 OR
0.35 × 45°
CHAMFER
LTC2302/LTC2306
21
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For more information www.linear.com/LTC2302
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa‑
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
reVision HisTory
REV DATE DESCRIPTION PAGE NUMBER
B 10/15 Changed REFCOMP to VREF 3
(Revision history begins at Rev B)
LTC2302/LTC2306
22
23026fb
For more information www.linear.com/LTC2302
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035‑7417
LINEAR TECHNOLOGY CORPORATION 2008
LT 1015 REV B • PRINTED IN USA
(408) 432‑1900 ● FAX: (408) 434‑0507 ● www.linear.com/LTC2302
Typical applicaTion
Clock Squaring/Level Shifting Circuit Allows Testing with RF Sine Generator,
Convert Re-Timing Flip-Flop Preserves Low Jitter Clock Timing
SDI
SDO
SCK
CONVST
SERIAL
PORT
ANALOG
INPUT
MUX
CH0 (IN+)
CH1 (IN–)
VREF
CONVERT ENABLE
MASTER
CLOCK
RF SIGNAL
GENERATOR
OR OTHER LOW
JITTER SOURCE
VCC
0.1µF
NC7SVU04P5X
LTC2302
LTC2306
VDD OVDD
GND
MASTER
CLOCK
CONVERT
ENABLE JITTER
0.1µF
12-BIT
500ksps
ADC
+
–
10µF0.1µF
1k
10µF 0.1µF
Q D
PRE
VCC
NL17SZ74
CONTROL
LOGIC
(FPGA, CPLD,
DSP, ETC.)
QCLR
1k
23026 TA02
50Ω
• • • • • •
• • • • • •
• • • • • •
• • • • • •
• • • • • •
• • • • • •
CONVST
DATA TRANSFER
relaTeD parTs
PART NUMBER DESCRIPTION COMMENTS
LTC1417 14‑Bit, 400ksps Serial ADC 20mW, Unipolar or Bipolar, Internal Reference, SSOP‑16 Package
LT1468/LT1469 Single/Dual 90MHz, 22V/µs, 16‑Bit Accurate Op Amps Low Input Offset: 75µV/125µV
LTC1609 16‑Bit, 200ksps Serial ADC 65mW, Configurable Bipolar and Unipolar Input Ranges, 5V Supply
LT1790 Micropower Low Dropout Reference 60µA Supply Current, 10ppm/°C, SOT‑23 Package
LTC1850/LTC1851 10‑Bit/12‑Bit, 8‑channel, 1.25Msps ADCs Parallel Output, Programmable MUX and Sequencer, 5V Supply
LTC1852/LTC1853 10‑Bit/12‑Bit, 8‑channel, 400ksps ADCs Parallel Output, Programmable MUX and Sequencer, 3V or 5V Supply
LTC1860/LTC1861 12‑Bit, 1‑/2‑Channel 250ksps ADCs in MSOP 850µA at 250ksps, 2µA at 1ksps, SO‑8 and MSOP Packages
LTC1860L/LTC1861L 3V, 12‑bit, 1‑/2‑Channel 150ksps ADCs 450µA at 150ksps, 10µA at 1ksps, SO‑8 and MSOP Packages
LTC1863/LTC1867 12‑/16‑Bit, 8‑Channel 200ksps ADCs 6.5mW, Unipolar or Bipolar, Internal Reference, SSOP‑16 Package
LTC1863L/LTC1867L 3V, 12‑/16‑bit, 8‑Channel 175ksps ADCs 2mW, Unipolar or Bipolar, Internal Reference, SSOP‑16 Package
LTC1864/LTC1865 16‑Bit, 1‑/2‑Channel 250ksps ADCs in MSOP 850µA at 250ksps, 2µA at 1ksps, SO‑8 and MSOP Packages
LTC1864L/LTC1865L 3V, 16‑Bit, 1‑/2‑Channel 150ksps ADCs in MSOP 450µA at 150ksps, 10µA at 1ksps, SO‑8 and MSOP Packages
LTC2308 12‑Bit, 8‑Channel 500ksps ADC 5V, Internal Reference, 4mm × 4mm QFN Packages