Visit our website: www.e2v.com
for the latest version of the datasheet
e2v semiconductors SAS 2011
P4080
QorIQ Integrated Processor
Hardware Specifications
Datasheet
The P4080 QorIQ integrated communication processor combines eight Power Architecture® processor cores with high
performance data path acceleration logic and network and peripheral bus interfaces required for power intensive
applications in aerospace, defence and demanding outdoor environments.
This device can be used for combined control, data path, and application layer processing. Its high level of integration
offers significant performance benefits compared to multiple discrete devices, while also greatly simplifying board design.
The device SoC includes the following function and features:
•Eight e500-mc Power Architecture Cores, Each with a Backside 128-Kbyte
L2 Cache with ECC
– Three Levels of instructions: User, Supervisor, and Hypervisor
– Independent Boot and Reset
– Secure Boot Capability
•CoreNet Fabric Supporting Coherent and non-coherent Transactions
Amongst CoreNet End-points
•A Frontside 2-Mbyte L3 Cache with ECC
•CoreNet Bridges Between the CoreNet Fabric the I/Os, Data Path
Accelerators, and High and Low
Speed Peripheral Interfaces
•Two 10-Gigabit Ethernet (XAUI) Controllers
•Eight 1-Gigabit Ethernet Controllers
•Two 64-bit DDR2/DDR3 SDRAM Memory Controllers with ECC
•Multicore Programmable Interrupt Controller
•Four I2C Controllers
•Four 2-pin UARTs or two 4-pin UARTs
•Two 4-channel DMA Engines
•Enhanced Local Bus Controller (eLBC)
•Three PCI Express 2.0 Controllers/Ports
•Two Serial RapidIO® 1.2 Controllers/Ports
•Enhanced Secure Digital Host Controller (SD/MMC)
•Enhanced Serial Peripheral Interfaces (eSPI)
•High-speed USB Controller (USB 2.0)
– Host and Device Support
– Enhanced Host Controller Interface (EHCI)
– ULPI Interface to PHY
1066A–HIREL–07/11
2
1066A–HIREL–07/11
P4080
e2v semiconductors SAS 2011
•Data Path Acceleration Architecture (DPAA) Incorporating Acceleration for the Following Functions:
– Frame Manager (FMan) for Packet Parsing, Classification, and Distribution
– Queue Manager (QMan) for Scheduling, Packet Sequencing, and Congestion Management
– Hardware Buffer Manager (BMan) for Buffer Allocation and de-allocation
– Encryption/Decryption (SEC 4.0)
– Regex Pattern Matching (PME 2.0)
•1295 FC-PBGA Package
Figure 0-1 shows the major functional units within the P4080.
Figure 0-1. P4080 QorIQ Preliminary Block Diagram
1. Pin Assignments and Reset States
1.1 1295 FC-PBGA Ball Layout Diagrams
Figure 1-1 shows the top view of the P4080 FC-PBGA ball map diagram.
3
1066A–HIREL–07/11
e2v semiconductors SAS 2011
P4080
Figure 1-1. P4080–1295 BGA Ball Map Diagram (Top View)
29 30 31 321171615141312111098765432 18 19 20 21 22 23 24 25 26 27 28 33 34 3635
AJ
AK
AL
AM
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
AN
AP
AR
AT
D2_
MDQ
[20]
D2_
MDQ
[10]
D2_
MDQS
[1]
D2_
MDQ
[8]
D2_
MDQ
[3]
D2_
MDQ
[7]
D2_
MDQ
[4]
D1_
MDQ
[3]
D1_
MDQ
[6]
D2_
MDQ
[16]
GVDD D2_
MDQ
[17]
D2_
MDM
[1]
D2_
MDQ
[13]
D2_
MDQ
[2]
D2_
MDM
[0]
D2_
MDQ
[5]
D1_
MDQ
[7]
D2_
MDQS
[2]
D2_
MDM
[2]
D2_
MDQ
[14]
D1_
MDQ
[21]
D2_
MDQ
[22]
D2_
MDQ
[23]
D2_
MDQ
[18]
D2_
MDQ
[15]
D2_
MDQ
[9]
D1_
MDQS
[2]
D1_
MDM
[2]
D1_
MDQ
[17]
D1_
MDQ
[20]
D2_
MDQ
[0]
D1_
MDQ
[2]
D1_
MDQ
[8]
D2_
MDQ
[19]
D2_
MDQ
[29]
D1_
MDQ
[18]
D1_
MDQ
[19]
D1_
MDQ
[13]
D1_
MCK
[4]
D2_
MDQ
[24]
D2_
MDQ
[25]
D1_
MDQ
[24]
D1_
MDQ
[28]
D1_
MDQ
[25]
D2_
MCK
[4]
D2_
MDM
[3]
D2_
MDQS
[3]
D1_
MDQ
[11]
D1_
MDQS
[1]
LA
[31]
D2_
MDQ
[31]
D2_
MDQ
[30]
D2_
MDQ
[26]
D2_
MDQ
[27]
D1_
MDQ
[30]
D1_
MDQ
[31]
NC
[34]
NC
[23]
D2_
MECC
[5]
D2_
MECC
[4]
D1_
MECC
[5]
D1_
MDQ
[27]
NC
[14]
NC
[13]
LAD
[15]
D2_
MDM
[8]
D1_
MDM
[8]
D1_
MECC
[0]
NC
[5]
LAD
[14]
D2_
MECC
[6]
D2_
MECC
[7]
D1_
MECC
[6]
D1_
MECC
[7]
D2_
MCKE
[3]
D2_
MECC
[2]
D1_
MBA
[2]
D2_
MECC
[3]
D2_MA
[9]
D2_
MCKE
[2]
D2_MA
[6]
D2_MA
[8]
D2_MA
[7]
D2_
MCKE
[0]
D2_MA
[3]
D2_MA
[4]
D2_MA
[5]
D1_MA
[1]
D1_MA
[2]
D1_MA
[3]
D1_MA
[4]
D1_
MDM
[0]
D1_
MDQ
[0]
D2_
MDQ
[6]
D1_
MDQS
[0]
D1_
MDQ
[5]
D2_
MDQ
[12]
D1_
MDQS
[0]
D1_
MDQ
[4]
D1_
MDM
[1]
D1_
MDQ
[22]
D1_
MDQ
[10]
[1]
GVDD
[12]
GND
[1]
GVDD
[7]
GND
[2]
GVDD
[6]
GND
[5]
GND
[4]
GVDD
[2]
GVDD
[11]
GND
[6]
GVDD
[8]
GND
[12]
GND
[7]
GVDD
[5]
GND
[13]
GVDD
[3]
GVDD
[10]
GND
[14]
GVDD
[9]
NC
[3]
GND
[24]
GND
[31]
GVDD
[4]
NC
[57]
NC
[51]
GND
[3]
GVDD
[13]
D1_
MDQ
[29]
GND
[11]
GVDD
[14]
D1_
MDQ
[15]
GND
[36]
D1_
MDQ
[12]
NC
[52]
NC
[40]
GVDD
[16]
GND
[10]
D1_
MDQS
[3]
GVDD
[17]
GND
[35]
D1_
MDQ
[9]
GVDD
[18]
NC
[37]
GVDD
[21]
GND
[9]
GVDD
[20]
GND
[37]
NC
[21]
NC
[22]
GVDD
[19]
NC
[38]
BVDD
[9]
GND
[8]
GVDD
[22]
D1_
MECC
[4]
GND
[38]
NC
[28]
GVDD
[35]
NC
[1]
NC
[16]
LAD
[13]
D2_
MECC
[1]
GVDD
[24]
D1_
MDQS
[8]
GND
[39]
GVDD
[23]
NC
[30]
NC
[36]
NC
[35]
NC
[33]
SENSE-
VDD_CA
SENSE-
GND_CA
GVDD
[25]
GND
[40]
GVDD
[26]
VDD_PL
[24]
GND
[230]
VDD_PL
[63]
VDD_PL
[64]
VDD_PL
[65]
GND
[141]
GND
[98]
GND
[32]
D2_
MBA
[2]
GND
[41]
GVDD
[27]
GND
[45]
GND
[113]
VDD_PL
[13]
GND
[127]
GND
[142]
GND
[157]
VDD_PL
[89]
VDD_CA
[9]
VDD_CA
[17]
D2_MA
[12]
D2_MA
[14]
GVDD
[28]
GND
[44]
GVDD
[29]
VDD_PL
[8]
VDD_PL
[81]
VDD_CA
[10]
VDD_CA
[16]
GND
[126]
GND
[140]
GND
[156]
GND
[160]
GVDD
[31]
GND
[43]
GVDD
[30]
D1_
MCKE
[0]
GND
[114]
VDD_PL
[14]
GND
[128]
GND
[143]
GND
[158]
VDD_CA
[5]
VDD_CA
[11]
VDD_CA
[18]
GND
[42]
GVDD
[32]
D1_MA
[7]
GND
[47]
VDD_PL
[9]
VDD_PL
[88]
VDD_CA
[15]
VDD_CA
[13]
GND
[125]
GND
[139]
GND
[155]
GND
[161]
GVDD
[34]
D1_
MDIC
[0]
GND
[48]
D1_MA
[6]
GVDD
[33]
GND
[115]
VDD_PL
[15]
GND
[129]
GND
[144]
GND
[159]
VDD_PL
[92]
VDD_CA
[12]
VDD_CA
[14]
GVDD
[36]
GND
[49]
GVDD
[37]
VDD_PL
[26]
VDD_PL
[31]
VDD_PL
[77]
VDD_PL
[90]
GND
[124]
GND
[138]
GND
[154]
GND
[162]
GVDD
[38]
GND
[54]
GND
[116]
VDD_PL
[16]
GND
[130]
GND
[145]
GND
[222]
VDD_PL
[61]
VDD_PL
[22]
VDD_PL
[62]
D2_
MDQ
[21]
SD_RX
[16]
TMS
TMS
SDHC_
DAT
[3]
RSRV
[24]
VDD_CB
[2]
GND
[185]
VDD_PL
[76]
GND
[197]
VDD_PL
[34]
GND
[213]
VDD_PL
[48]
GND
[109]
VDD_PL
[53]
NC
[62]
SD_TX
[12]
SD_TX
[12]
XGND
[36]
SD_RX
[12]
SD_RX
[12]
SGND
[29]
SVDD
[28]
GND
[174]
GND
[189]
GND
[204]
GND
[220]
VDD_CB
[4]
VDD_PL
[85]
VDD_PL
[42]
VDD_PL
[5]
GND
[228]
NC
[26]
SD_TX
[13]
SVDD
[29]
SGND
[30]
SD_RX
[13]
SD_RX
[13]
VDD_CB
[3]
GND
[183]
VDD_CB
[6]
GND
[196]
VDD_PL
[73]
GND
[214]
VDD_PL
[49]
GND
[108]
VDD_PL
[35]
NC
[12]
XVDD
[1]
SD_TX
[14]
SD_RX
[14]
SD_RX
[14]
SGND
[4]
GND
[173]
GND
[188]
GND
[203]
GND
[219]
VDD_CB
[17]
VDD_PL
[86]
VDD_PL
[43]
VDD_PL
[6]
GND
[87]
NC
[2]
NC
[29]
SD_TX
[15]
XGND
[2]
SGND
[5]
SVDD
[4]
AVD D _
SRDS3
AGND_
SRDS3
VDD_CB
[16]
GND
[184]
VDD_PL
[78]
GND
[195]
VDD_PL
[74]
GND
[215]
VDD_PL
[50]
GND
[107]
VDD_PL
[36]
NC
[11]
NC
[4]
XVDD
[4]
GND
[172]
GND
[187]
GND
[202]
GND
[218]
VDD_PL
[96]
VDD_PL
[79]
VDD_PL
[44]
VDD_PL
[7]
GND
[229]
NC
[31]
XGND
[5]
SD_
REF_
CLK3
SD_
REF_
CLK3
SGND
[6]
SVDD
[5]
VDD_PL
[25]
GND
[182]
VDD_PL
[29]
GND
[194]
VDD_PL
[37]
GND
[216]
VDD_PL
[54]
GND
[106]
GND
[97]
NC
[18]
NC
[8]
SVDD
[6]
SGND
[7]
GND
[171]
GND
[186]
GND
[201]
GND
[217]
VDD_PL
[57]
VDD_PL
[56]
VDD_PL
[55]
NC
[19]
NC
[60]
NC
[53]
NC
[10]
SD_RX
[16]
SVDD
[7]
SGND
[8]
DMA2_
DACK
[0]
GPIO
[7]
OVDD
[7]
SDHC_
CMD
RSRV
[19]
NC
[17]
NC
[47]
NC
[50]
NC
[9]
IO_
VSEL
[4]
MSRCID
[0]
GPIO
[4]
GND
[89]
RSRV
[6]
RSRV
[4]
RSRV
[14]
RSRV
[11]
SPI_
MISO
NC
[25]
NC
[24]
GND
[102]
EMI2_
MDIO
EMI2_
MDC
MSRCID
[1]
DMA2_
DREQ
[0]
GPIO
[5]
OVDD
[10]
RSRV
[26]
RSRV
[5]
RSRV
[18]
RSRV
[15]
SPI_CS
[1]
CVDD
[1]
GND
[100]
EMI1_
MDC
LVDD
[5]
GND
[84]
CLK_
OUT
GPIO
[6]
GPIO
[1]
RSRV
[35]
RSRV
[10]
RSRV
[7]
RSRV
[37]
GND
[96]
SPI_
CLK
LVDD
[1]
DMA1_
DACK
[0]
OVDD
[8]
GPIO
[0]
SDHC_
CLK
RSRV
[33]
RSRV
[2]
RSRV
[34]
RSRV
[30]
RSRV
[23]
GND
[91]
LVDD
[3]
EMI1_
MDIO
RSRV
[41]
GND
[104]
TSEC_
1588_CLK
_IN
SDHC_
DAT
[2]
GND
[90]
GPIO
[2]
CKSTP_
OUT
RSRV
[29]
RSRV
[21]
RSRV
[39]
RSRV
[8]
RSRV
[27]
SPI_CS
[3]
GND
[105]
EC1_
RXD
[3]
LVDD
[7]
OVDD
[1]
DMA1_
DDONE
[0]
GPIO
[3]
TMP_
DETECT RTC RSRV
[36]
RSRV
[17]
RSRV
[40]
RSRV
[1]
SPI_CS
[0]
GND
[101]
EC2_
GTX_
CLK
EC2_
RXD
[2]
LVDD
[4]
EC1_
RXD
[2]
EC1_
RXD
[1]
EC1_
RXD
[0]
GND
[88]
DMA2_
DDONE
[0]
DMA1_
DREQ
[0]
GND
[94]
SDHC_
DAT
[0]
RSRV
[38]
RSRV
[25]
RSRV
[20]
RSRV
[22]
CVDD
[2]
EC2_
TXD
[2]
LVDD
[2]
EC2_
RXD
[1]
EC2_
RXD
[3]
GND
[99]
EC1_
GTX_
CLK
EC1_
TXD
[3]
TRST ASLEEP TCK OVDD
[12]
RSRV
[28]
RSRV
[12]
RSRV
[9]
RSRV
[3]
SPI_CS
[2]
EC2_
TXD
[1]
EC2_
TX_EN
GND
[95]
EC1_
RX_DV
EC2_
RX_DV
EC1_
TXD
[1]
LVDD
[6]
EC1_
TX_EN
AVD D _
PLAT
TEST_
SEL
GND
[93] SYSCLK
SDHC_
DAT
[1]
RSRV
[32]
RSRV
[16]
RSRV
[13]
RSRV
[31]
SPI_
MOSI
EC2_
TXD
[0]
EC2_
TXD
[3]
EC2_
RXD
[0]
EC2_
RX_CLK
EC1_
TXD
[2]
EC1_
TXD
[0]
GND
[103]
EC1_
RX_CLK
AVDD_
CC4
EC_XTRNL
_TX_STMP
[2]
EC_XTRNL
_RX_STMP
[2]
TSEC_
1588_CLK_
OUT
TSEC_
1588_PULSE
_OUT[1]
TSEC_
1588_PULSE
_OUT[2]
EC_
GTX_
CLK125
EC_XTRNL
_TX_STMP
[1]
TSEC_
1588_ALARM
_OUT[2]
TSEC_
1588_ALARM
_OUT[1]
TSEC_
1588_TRIG
_IN[2]
TSEC_
1588_TRIG
_IN[1]
SD_IMP_
CAL_TX
LA
[19]
LAD
[11]
GND
[29]
LA
[28]
AVDD _
DDR
MVREF
LBCTL
LCS
[5]
LCS
[0]
LCS
[1]
LA
[21]
LA
[22]
LAD
[4]
SD_TX
[3]
LAD
[7]
LAD
[6]
LA
[29]
LA
[20]
LA
[18]
LAD
[5]
LAD
[3]
LA
[26]
LA
[23]
GND
[27]
LA
[24]
GND
[30]
XGND
[21]
NC
[43]
SD_RX
[4]
SD_RX
[5]
SD_RX
[5]
SGND
[18]
SGND
[20]
SD_RX
[8]
SD_RX
[9]
SD_RX
[9]
SD_RX
[10]
SD_RX
[10]
AVDD _
CC1 LALE AVDD_
SRDS1
TEMP_
CATHODE
AVDD_
CC2
AGND_
SRDS1
SD_
REF_
CLK1
SD_
REF_
CLK1
TEMP_
ANODE
LCS
[3]
LCS
[4]
LWE
[0]
LCS
[2]
LWE
[1]
NC
[56]
NC
[39]
GND
[16]
GND
[18]
GND
[21]
GND
[17]
LCLK
[1]
LCLK
[0]
LAD
[9]
BVDD
[1]
LGPL
[0]
LGPL
[4]
LGPL
[2]
GND
[23]
NC
[6]
NC
[55]
NC
[42]
NC
[58]
SGND
[1]
SVDD
[9]
SD_RX
[0]
SD_RX
[0]
SD_RX
[1]
SD_RX
[1]
SGND
[12]
SVDD
[15]
SVDD
[1]
SD_RX
[3]
SD_RX
[3]
SGND
[2]
XGND
[12]
SD_RX
[2]
SVDD
[13]
SD_RX
[2]
SGND
[14]
SD_TX
[4]
XGND
[9]
BVDD
[6]
LAD
[8]
BVDD
[5]
LGPL
[1]
LGPL
[5]
NC
[7]
XGND
[11]
SD_TX
[3]
XVDD
[8]
XVDD
[9]
SGND
[16]
SVDD
[16]
LAD
[12]
BVDD
[3]
GND
[26]
LCS
[6]
BVDD
[4]
GND
[28]
SD_TX
[1]
SVDD
[17]
LA
[25]
LA
[17]
LCS
[7]
NC
[48]
XVDD
[12]
SVDD
[18]
BVDD
[8]
LGPL
[3]
NC
[20]
XGND
[15]
XGND
[17]
SD_RX
[6]
SD_RX
[6]
GND
[33]
LAD
[10]
GND
[20]
LDP
[0]
LA
[16]
LAD
[2]
SD_TX
[6]
XGND
[18]
SGND
[19]
SVDD
[19]
LA
[27]
BVDD
[2]
LDP
[1]
BVDD
[7]
LAD
[0]
XVDD
[18]
SD_TX
[7]
SD_TX
[7]
SVDD
[20]
SD_RX
[7]
SD_RX
[7]
VDD_PL
[66]
VDD_PL
[67]
GND
[22]
VDD_PL
[68]
VDD_PL
[69]
GND
[19]
GND
[209]
LAD
[1]
SENSE-
GND_PL
[2]
SENSE-
VDD_PL
[2]
XVDD
[20]
XGND
[23]
SD_RX
[8]
SVDD
[21]
SGND
[21]
GND
[178]
GND
[193]
GND
[208]
GND
[225]
VDD_CA
[7]
VDD_PL
[80]
VDD_PL
[38]
VDD_PL
[1]
GND
[34]
XVDD
[21]
XGND
[24]
SD_TX
[8]
SD_TX
[8]
SVDD
[22]
SGND
[22]
VDD_CA
[6]
GND
[179]
VDD_CA
[8]
GND
[200]
VDD_PL
[71]
GND
[210]
VDD_PL
[45]
GND
[112]
VDD_PL
[51]
SD_TX
[9]
SD_TX
[9]
XVDD
[22]
SGND
[23]
SVDD
[23]
GND
[177]
GND
[192]
GND
[207]
GND
[224]
VDD_CA
[2]
VDD_PL
[83]
VDD_PL
[39]
VDD_PL
[2]
GND
[221]
XGND
[28]
XVDD
[23]
SD_TX
[10]
SD_TX
[10]
VDD_CA
[4]
GND
[180]
VDD_CA
[3]
GND
[199]
VDD_PL
[72]
GND
[211]
VDD_PL
[46]
GND
[111]
VDD_PL
[32]
XVDD
[26]
XGND
[31]
SVDD
[24]
SGND
[25]
GND
[176]
GND
[191]
GND
[206]
GND
[223]
VDD_CA
[1]
VDD_PL
[84]
VDD_PL
[40]
VDD_PL
[3]
GND
[226]
NC
[61]
XVDD
[27]
SGND
[26]
AVDD _
SRDS2
AGND_
SRDS2
VDD_PL
[91]
GND
[181]
VDD_PL
[75]
GND
[198]
VDD_PL
[33]
GND
[212]
VDD_PL
[47]
GND
[110]
VDD_PL
[52]
NC
[46]
XGND
[33]
SGND
[27]
GND
[175]
GND
[190]
GND
[205]
GND
[46]
VDD_PL
[28]
VDD_PL
[30]
VDD_PL
[41]
VDD_PL
[4]
GND
[227]
NC
[49]
XGND
[34]
XVDD
[30]
SGND
[28]
SVDD
[27]
XVDD
[16]
SD_IMP_
CAL_RX
29 30 31 321171615141312111098765432 18 19 20 21 22 23 24 25 26 27 28 33 34 3635
AJ
AK
AL
AM
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
AN
AP
AR
AT
D2_
MDQ
[48]
D1_
MDQ
[54]
D1_
MDQ
[50]
D2_
MDQ
[56]
D2_
MDQ
[58]
D2_
MDQS
[6]
D2_
MDQ
[54]
D2_
MDQS
[7]
D1_
MDQ
[62]
D1_
MDQ
[59]
D2_
MDQ
[55]
D2_
MDQ
[61]
D2_
MDQ
[57]
D2_
MDQ
[63]
D2_
MDQ
[59]
D1_
MDQ
[56]
D1_
MDQS
[7]
D1_
MDQ
[58]
D2_
MCK
[0]
D1_
MCK
[0]
D2_
MDIC
[1]
D2_
MCS
[0]
D1_
MDQ
[33]
D1_
MDQ
[32]
D2_
MODT
[2]
D2_
MODT
[0]
D1_
MDM
[4]
D1_
MODT
[0]
D2_
MODT
[3]
D2_
MDQ
[37]
D1_
MDQ
[35]
D2_
MDM
[4]
D2_
MDQ
[32]
D1_
MDQ
[45]
D1_
MDQ
[44]
D1_
MODT
[1]
D2_
MDQ
[38]
D1_
MDQS
[5]
D1_
MDM
[5]
D2_
MDQ
[35]
D2_
MDQ
[34]
D1_
MDQ
[42]
D2_
MDQ
[45]
D2_
MDQ
[44]
D1_
MDQ
[53]
D1_
MCK
[5]
D2_
MDM
[5]
D2_
MDQ
[41]
D2_
MDQ
[40]
D1_
MDQ
[49]
D1_
MDM
[6]
D2_
MDQ
[52]
D2_
MDQS
[5]
D2_
MDQ
[46]
D1_
MDQS
[6]
D1_
MCK
[0]
GND
[53]
D1_
MCK
[3]
D1_
MCK
[3]
GVDD
[40]
VDD_PL
[10]
VDD_PL
[59]
VDD_CB
[1]
VDD_CB
[12]
GND
[123]
GND
[137]
GND
[150]
GND
[167]
GND
[52]
GVDD
[44]
D1_
MBA
[1]
GND
[117]
VDD_PL
[17]
GND
[131]
GND
[146]
GND
[163]
VDD_PL
[97]
VDD_CB
[7]
VDD_CB
[13]
D2_
MAPAR_
OUT
D1_
MDIC
[1]
GVDD
[41]
GND
[55]
VDD_PL
[11]
VDD_PL
[87]
VDD_CB
[8]
VDD_CB
[10]
GND
[122]
GND
[136]
GND
[152]
GND
[169]
D2_
MRAS
GVDD
[51]
GND
[56]
GVDD
[52]
GND
[118]
VDD_PL
[18]
GND
[132]
GND
[147]
GND
[164]
VDD_CB
[5]
VDD_CB
[15]
VDD_CB
[14]
GVDD
[45]
D2_MA
[13]
GND
[57]
GVDD
[53]
D1_
MCS
[0]
VDD_PL
[27]
VDD_PL
[82]
VDD_CB
[9]
VDD_CB
[11]
GND
[121]
GND
[135]
GND
[151]
GND
[168]
GND
[58]
GVDD
[46]
D1_
MODT
[2]
GND
[59]
GND
[119]
VDD_PL
[19]
GND
[133]
GND
[148]
GND
[165]
VDD_PL
[93]
VDD_PL
[94]
VDD_PL
[95]
D1_
MDQ
[39]
GND
[60]
GVDD
[47]
VDD_PL
[12]
VDD_PL
[20]
VDD_PL
[21]
VDD_PL
[23]
GND
[120]
GND
[134]
GND
[153]
GND
[170]
D2_
MODT
[1]
GVDD
[49]
GND
[61]
GVDD
[50]
D1_
MCS
[3]
SENSE-
VDD_PL
[1]
SENSE-
GND_PL
[1]
GND
[85]
GND
[149]
GND
[166]
VDD_PL
[70]
VDD_PL
[58]
VDD_PL
[60]
GND
[62]
D1_
MDQ
[40]
GVDD
[54]
GND
[63]
IRQ
[8]
IIC4_
SCL
SENSE-
VDD_CB
SENSE-
GND_CB
IRQ
[6]
D2_
MDQS
[4]
GVDD
[56]
D1_
MDQS
[5]
GND
[64]
GVDD
[55]
GND
[72]
IRQ
[10]
IIC1_
SCL
IRQ
[1]
IRQ
[4]
GVDD
[57]
D2_
MDQ
[39]
GND
[65]
D1_
MDQ
[46]
GVDD
[58]
GND
[71]
OVDD
[5]
IRQ
[5]
OVDD
[2]
IRQ
[3]
IRQ
[0]
EVT
[0]
OVDD
[3]
D2_
MCK
[5]
GND
[66]
GVDD
[60]
GND
[70]
IRQ
[9]
IRQ
[2]
IIC3_
SCL
IRQ_
OUT
GND
[78]
EVT
[3]
EVT
[1]
IO_
VSEL
[2]
D1_
MCK
[5]
GVDD
[61]
GND
[69]
D1_
MDQ
[48]
GVDD
[62]
IRQ
[11]
GND
[77]
IIC2_
SDA
IIC4_
SDA
OVDD
[4]
SCAN_
MODE
IO_
VSEL
[0]
GVDD
[63]
GND
[68]
GVDD
[64]
GND
[76]
IRQ
[7]
IIC3_
SDA
IIC2_
SCL
EVT
[4]
GND
[83]
IO_
VSEL
[3]
D2_
MDQ
[53]
GND
[67]
D2_
MDQ
[42]
D2_
MDQ
[43]
GVDD
[67]
D1_
MDQ
[55]
GND
[75]
D1_
MDQ
[51]
GVDD
[66]
IIC1_
SDA
GND
[82]
EVT
[2] TDI OVDD
[6]
D2_
MDM
[6]
D2_
MDQ
[49]
GVDD
[68]
D2_
MDM
[7]
GND
[74]
D1_
MDQ
[60]
GVDD
[65]
GND
[81] TDO OVDD
[11]
PORESET
IO_
VSEL
[1]
GVDD
[42]
D2_
MDQ
[60]
GND
[73]
D2_
MDQ
[62]
GVDD
[15]
D1_
MDQ
[61]
D1_
MDQ
[57]
GND
[80]
GVDD
[59] MDVAL GND
[92]
GND
[86]
HRESET
D2_
MDQ
[51]
D2_
MDQS
[7]
OVDD
[9]
RESET_
REQ POVDD
GVDD
[48]
AVDD_
CC3
D2_
MDQS
[1]
D2_
MDQS
[0]
D2_
MDQS
[0]
D2_
MDQ
[1]
D2_
MDQ
[11]
D2_
MDQS
[2]
D1_
MDQ
[16]
D1_
MDQS
[2]
D1_
MDQ
[1]
GND
[25]
D2_
MDQ
[28]
D1_
MDQ
[23]
D1_
MDQ
[14]
D1_
MCK
[4]
D1_
MDQS
[1]
D2_
MCK
[4]
D2_
MDQS
[3]
D1_
MDQS
[3]
D1_
MDM
[3]
D1_
MDQ
[26]
D2_
MECC
[0]
D1_
MECC
[1]
D2_
MDQS
[8]
D1_
MDQS
[8]
D1_MA
[15]
D1_
MECC
[2]
D2_MA
[15]
D1_MA
[14]
D1_
MECC
[3]
D2_
MAPAR_
ERR
D1_MA
[12]
D1_
MAPAR_
ERR
D1_
MCKE
[3]
D2_MA
[11]
D1_MA
[9]
D1_MA
[11]
D1_
MCKE
[2]
D1_MA
[8]
D1_
MCKE
[1]
D2_
MCKE
[1]
D1_MA
[5]
GND
[50]
D2_MA
[1]
D2_MA
[2]
D2_
MCK
[2]
D1_
MCK
[1]
D2_
MCK
[2]
D2_
MCK
[1]
D2_
MCK
[1]
D1_
MCK
[1]
D1_
MCK
[2]
D1_
MCK
[2]
D2_
MCK
[3]
D2_
MCK
[3]
D2_
MCK
[0]
GVDD
[43]
GND
[51]
D2_MA
[0]
D1_
MAPAR_
OUT
D1_MA
[0]
D2_
MBA
[1]
D2_MA
[10]
D2_
MBA
[0]
D2_
MDIC
[0]
D1_MA
[10]
D1_
MBA
[0]
D1_
MRAS
D2_
MWE
D2_
MCS
[2]
D1_
MDQ
[36]
D1_
MDQ
[37]
D1_
MWE
D1_
MCS
[2]
D2_
MCAS
D1_
MCAS
D1_
MDQS
[4]
D1_
MDQS
[4]
D2_
MCS
[1]
D2_
MCS
[3]
D1_
MDQ
[38]
D1_MA
[13]
D1_
MCS
[1]
D2_
MDQ
[36]
D1_
MDQ
[34]
D1_
MODT
[3]
D2_
MDQ
[33]
D2_
MDQS
[4]
D1_
MDQ
[41]
MSRCID
[2]
GND
[79]
D1_
MDQ
[47]
D1_
MDQ
[43]
D2_
MCK
[5]
D1_
MDQ
[52]
GVDD
[39]
D2_
MDQS
[5]
D2_
MDQ
[47]
D1_
MDQS
[6]
NC
[44]
NC
[27]
D2_
MDQS
[6]
NC
[45]
D1_
MDQ
[63]
NC
[54]
D2_
MDQ
[50]
D1_
MDM
[7]
D1_
MDQS
[7]
NC
[41]
NC
[32]
SVDD
[2]
SGND
[3]
NC
[59]
SGND
[10]
SVDD
[10]
SGND
[11]
SVDD
[11]
SVDD
[12]
SD_RX
[4]
SGND
[13]
SVDD
[14]
SGND
[15]
XGND
[10]
SD_TX
[1]
SD_TX
[4]
XVDD
[10]
SD_TX
[5]
XVDD
[11]
SD_TX
[0]
XGND
[13]
XGND
[14]
SD_TX
[5]
SGND
[17]
SD_TX
[0]
SD_TX
[2]
SD_TX
[2]
XVDD
[13]
XGND
[16]
XVDD
[14]
LA
[30]
XVDD
[15]
XGND
[19]
XVDD
[17]
SD_TX
[6]
GND
[15]
XGND
[20]
XGND
[22]
XVDD
[19]
XGND
[25]
XGND
[26]
XGND
[27]
XVDD
[24]
XGND
[29]
XVDD
[25]
XGND
[30]
SGND
[24]
SVDD
[25]
SD_TX
[11]
SD_TX
[11]
XVDD
[28]
SD_RX
[11]
SD_RX
[11]
XGND
[32]
XVDD
[29]
SVDD
[26]
XGND
[35]
XVDD
[31]
SD_
REF_
CLK2
SD_
REF_
CLK2
XVDD
[32]
SD_TX
[13]
XVDD
[33]
XGND
[37]
XGND
[1]
SD_TX
[14]
SVDD
[3]
SD_TX
[15]
XVDD
[2]
XVDD
[3]
XGND
[3]
SD_RX
[15]
SD_RX
[15]
XGND
[4]
XGND
[6]
XVDD
[5]
XVDD
[6]
SD_TX
[16]
SD_TX
[16]
XVDD
[7]
XGND
[7]
XGND
[8]
SD_TX
[17]
SD_TX
[17]
SGND
[9]
SVDD
[8]
SD_RX
[17]
SD_RX
[17]
UART2_
CTS
UART2_
SOUT
UART2_
RTS
UART1_
SOUT
UART1_
RTS
UART2_
SIN
UART1_
CTS
UART1_
SIN
D2_
MDQS
[8]
SEE DETAIL A SEE DETAIL B
SEE DETAIL D
XGND
[38]
XVDD
[34]
SGND
[32]
SGND
[31]
SVDD
[30]
EC_XTRNL
_RX_STMP
[1]
RSRV
[42]
RSRV
[43]
RSRV
[44]
NC
[15]
RSRV
[45]
RSRV
[46]
RSRV
[47]
RSRV
[48]
RSRV
[49]
RSRV
[50]
RSRV
[51]
RSRV
[52]
RSRV
[54]
RSRV
[56]
RSRV
[53]
RSRV
[55]
SEE DETAIL C
OVDD
I/O Supply Voltage
LVDD
I/O Supply Voltage
Local Bus I/O Supply
SerDes Core Power Supply
SVDD
SerDes Transcvr Pad Supply
XVDD
DDR DRAM I/O Supply
GVDD
BVDD
Platform Supply Voltage
VDD_
PL
VDD_
CA
Core Group A Supply Voltage
VDD_
CB
Core Group B Supply Voltage
AVDD_
SRDS1
SerDes 1 PLL Supply Voltage
AVDD_
SRDS2
SerDes 2 PLL Supply Voltage
CVDD
SPI Voltage Supply
Platform Voltage Sense
SENSE-
VDD_PL
SENSE-
VDD_CA
Core Group A Voltage Sense
SENSE-
VDD_CB
Core Group B Voltage Sense
Platform PLL Supply Voltage
Core PLL Supply Voltage
AVDD_
CC
AVDD_
PLAT
Reserved
Signal Groups
Fuse Programming Override Supply
POVDD
RSRV
4
1066A–HIREL–07/11
P4080
e2v semiconductors SAS 2011
Figure 1-2. P4080-1295 BGA Ball Map Diagram (Detail View A)
D2_
MDQ
[20]
D2_
MDQ
[10]
D2_
MDQS
[1]
D2_
MDQ
[8]
D2_
MDQ
[3]
D2_
MDQ
[7]
D2_
MDQ
[4]
D1_
MDQ
[3]
D1_
MDQ
[6]
D2_
MDQ
[16]
GVDD D2_
MDQ
[17]
D2_
MDM
[1]
D2_
MDQ
[13]
D2_
MDQ
[2]
D2_
MDM
[0]
D2_
MDQ
[5]
D1_
MDQ
[7]
D2_
MDQS
[2]
D2_
MDM
[2]
D2_
MDQ
[14]
D1_
MDQ
[21]
D2_
MDQ
[22]
D2_
MDQ
[23]
D2_
MDQ
[18]
D2_
MDQ
[15]
D2_
MDQ
[9]
D1_
MDQS
[2]
D1_
MDM
[2]
D1_
MDQ
[17]
D1_
MDQ
[20]
D2_
MDQ
[0]
D1_
MDQ
[2]
D1_
MDQ
[8]
D2_
MDQ
[19]
D2_
MDQ
[29]
D1_
MDQ
[18]
D1_
MDQ
[19]
D1_
MDQ
[13]
D1_
MCK
[4]
D2_
MDQ
[24]
D2_
MDQ
[25]
D1_
MDQ
[24]
D1_
MDQ
[28]
D1_
MDQ
[25]
D2_
MCK
[4]
D2_
MDM
[3]
D2_
MDQS
[3]
D1_
MDQ
[11]
D1_
MDQS
[1]
LA
[31]
D2_
MDQ
[31]
D2_
MDQ
[30]
D2_
MDQ
[26]
D2_
MDQ
[27]
D1_
MDQ
[30]
D1_
MDQ
[31]
NC
[34]
NC
[23]
D2_
MECC
[5]
D2_
MECC
[4]
D1_
MECC
[5]
D1_
MDQ
[27]
NC
[14]
NC
[13]
LAD
[15]
D2_
MDM
[8]
D1_
MDM
[8]
D1_
MECC
[0]
NC
[5]
LAD
[14]
D2_
MECC
[6]
D2_
MECC
[7]
D1_
MECC
[6]
D1_
MECC
[7]
D2_
MCKE
[3]
D2_
MECC
[2]
D1_
MBA
[2]
D2_
MECC
[3]
D2_MA
[9]
D2_
MCKE
[2]
D2_MA
[6]
D2_MA
[8]
D2_MA
[7]
D2_
MCKE
[0]
D2_MA
[3]
D2_MA
[4]
D2_MA
[5]
D1_MA
[1]
D1_MA
[2]
D1_MA
[3]
D1_MA
[4]
D1_
MDM
[0]
D1_
MDQ
[0]
D2_
MDQ
[6]
D1_
MDQS
[0]
D1_
MDQ
[5]
D2_
MDQ
[12]
D1_
MDQS
[0]
D1_
MDQ
[4]
D1_
MDM
[1]
D1_
MDQ
[22]
D1_
MDQ
[10]
[1]
GVDD
[12]
GND
[1]
GVDD
[7]
GND
[2]
GVDD
[6]
GND
[5]
GND
[4]
GVDD
[2]
GVDD
[11]
GND
[6]
GVDD
[8]
GND
[12]
GND
[7]
GVDD
[5]
GND
[13]
GVDD
[3]
GVDD
[10]
GND
[14]
GVDD
[9]
NC
[3]
GND
[24]
GND
[31]
GVDD
[4]
NC
[57]
NC
[51]
GND
[3]
GVDD
[13]
D1_
MDQ
[29]
GND
[11]
GVDD
[14]
D1_
MDQ
[15]
GND
[36]
D1_
MDQ
[12]
NC
[52]
NC
[40]
GVDD
[16]
GND
[10]
D1_
MDQS
[3]
GVDD
[17]
GND
[35]
D1_
MDQ
[9]
GVDD
[18]
NC
[37]
GVDD
[21]
GND
[9]
GVDD
[20]
GND
[37]
NC
[21]
NC
[22]
GVDD
[19]
NC
[38]
BVDD
[9]
GND
[8]
GVDD
[22]
D1_
MECC
[4]
GND
[38]
NC
[28]
GVDD
[35]
NC
[1]
NC
[16]
LAD
[13]
D2_
MECC
[1]
GVDD
[24]
D1_
MDQS
[8]
GND
[39]
GVDD
[23]
NC
[30]
NC
[36]
NC
[35]
NC
[33]
SENSE-
VDD_CA
SENSE-
GND_CA
GVDD
[25]
GND
[40]
GVDD
[26]
VDD_PL
[24]
GND
[230]
VDD_PL
[63]
VDD_PL
[64]
VDD_PL
[65]
GND
[141]
GND
[98]
GND
[32]
D2_
MBA
[2]
GND
[41]
GVDD
[27]
GND
[45]
GND
[113]
VDD_PL
[13]
GND
[127]
GND
[142]
GND
[157]
VDD_PL
[89]
VDD_CA
[9]
VDD_CA
[17]
D2_MA
[12]
D2_MA
[14]
GVDD
[28]
GND
[44]
GVDD
[29]
VDD_PL
[8]
VDD_PL
[81]
VDD_CA
[10]
VDD_CA
[16]
GND
[126]
GND
[140]
GND
[156]
GND
[160]
GVDD
[31]
GND
[43]
GVDD
[30]
D1_
MCKE
[0]
GND
[114]
VDD_PL
[14]
GND
[128]
GND
[143]
GND
[158]
VDD_CA
[5]
VDD_CA
[11]
VDD_CA
[18]
GND
[42]
GVDD
[32]
D1_MA
[7]
GND
[47]
VDD_PL
[9]
VDD_PL
[88]
VDD_CA
[15]
VDD_CA
[13]
GND
[125]
GND
[139]
GND
[155]
GND
[161]
GVDD
[34]
D1_
MDIC
[0]
GND
[48]
D1_MA
[6]
GVDD
[33]
GND
[115]
VDD_PL
[15]
GND
[129]
GND
[144]
GND
[159]
VDD_PL
[92]
VDD_CA
[12]
VDD_CA
[14]
GVDD
[36]
GND
[49]
GVDD
[37]
VDD_PL
[26]
VDD_PL
[31]
VDD_PL
[77]
VDD_PL
[90]
GND
[124]
GND
[138]
GND
[154]
GND
[162]
GVDD
[38]
GND
[54]
GND
[116]
VDD_PL
[16]
GND
[130]
GND
[145]
GND
[222]
VDD_PL
[61]
VDD_PL
[22]
VDD_PL
[62]
D2_
MDQ
[21]
D2_
MDQS
[1]
D2_
MDQS
[0]
D2_
MDQS
[0]
D2_
MDQ
[1]
D2_
MDQ
[11]
D2_
MDQS
[2]
D1_
MDQ
[16]
D1_
MDQS
[2]
D1_
MDQ
[1]
GND
[25]
D2_
MDQ
[28]
D1_
MDQ
[23]
D1_
MDQ
[14]
D1_
MCK
[4]
D1_
MDQS
[1]
D2_
MCK
[4]
D2_
MDQS
[3]
D1_
MDQS
[3]
D1_
MDM
[3]
D1_
MDQ
[26]
D2_
MECC
[0]
D1_
MECC
[1]
D2_
MDQS
[8]
D1_
MDQS
[8]
D1_MA
[15]
D1_
MECC
[2]
D2_MA
[15]
D1_MA
[14]
D1_
MECC
[3]
D2_
MAPAR_
ERR
D1_MA
[12]
D1_
MAPAR_
ERR
D1_
MCKE
[3]
D2_MA
[11]
D1_MA
[9]
D1_MA
[11]
D1_
MCKE
[2]
D1_MA
[8]
D1_
MCKE
[1]
D2_
MCKE
[1]
D1_MA
[5]
GND
[50]
D2_MA
[1]
D2_MA
[2]
D2_
MCK
[2]
D1_
MCK
[1]
D2_
MCK
[2]
D2_
MCK
[1]
D2_
MCK
[1]
D1_
MCK
[1]
D1_
MCK
[2]
D1_
MCK
[2]
D2_
MDQS
[8]
1181312111098765432
A
B
C
D
E
F
G
H
J
K
L
M
N
T
14 15
P
R
U
V
16 17
DETAIL A
5
1066A–HIREL–07/11
e2v semiconductors SAS 2011
P4080
Figure 1-3. P4080-1295 BGA Ball Map Diagram (Detail View B)
LA
[19]
LAD
[11]
GND
[29]
LA
[28]
AVDD_
DDR
MVREF
LBCTL
LCS
[5]
LCS
[0]
LCS
[1]
LA
[21]
LA
[22]
LAD
[4]
SD_TX
[3]
LAD
[7]
LAD
[6]
LA
[29]
LA
[20]
LA
[18]
LAD
[5]
LAD
[3]
LA
[26]
LA
[23]
GND
[27]
LA
[24]
GND
[30]
XGND
[21]
NC
[43]
SD_RX
[4]
SD_RX
[5]
SD_RX
[5]
SGND
[18]
SGND
[20]
SD_RX
[8]
SD_RX
[9]
SD_RX
[9]
SD_RX
[10]
SD_RX
[10]
AVDD_
CC1 LALE AVDD_
SRDS1
TEMP_
CATHODE
AVDD_
CC2
AGND_
SRDS1
SD_
REF_
CLK1
SD_
REF_
CLK1
TEMP_
ANODE
LCS
[3]
LCS
[4]
LWE
[0]
LCS
[2]
LWE
[1]
NC
[56]
NC
[39]
GND
[16]
GND
[18]
GND
[21]
GND
[17]
LCLK
[1]
LCLK
[0]
LAD
[9]
BVDD
[1]
LGPL
[0]
LGPL
[4]
LGPL
[2]
GND
[23]
NC
[6]
NC
[55]
NC
[42]
NC
[58]
SGND
[1]
SVDD
[9]
SD_RX
[0]
SD_RX
[0]
SD_RX
[1]
SD_RX
[1]
SGND
[12]
SVDD
[15]
SVDD
[1]
SD_RX
[3]
SD_RX
[3]
SGND
[2]
XGND
[12]
SD_RX
[2]
SVDD
[13]
SD_RX
[2]
SGND
[14]
SD_TX
[4]
XGND
[9]
BVDD
[6]
LAD
[8]
BVDD
[5]
LGPL
[1]
LGPL
[5]
NC
[7]
XGND
[11]
SD_TX
[3]
XVDD
[8]
XVDD
[9]
SGND
[16]
SVDD
[16]
LAD
[12]
BVDD
[3]
GND
[26]
LCS
[6]
BVDD
[4]
GND
[28]
SD_TX
[1]
SVDD
[17]
LA
[25]
LA
[17]
LCS
[7]
NC
[48]
XVDD
[12]
SVDD
[18]
BVDD
[8]
LGPL
[3]
NC
[20]
XGND
[15]
XGND
[17]
SD_RX
[6]
SD_RX
[6]
GND
[33]
LAD
[10]
GND
[20]
LDP
[0]
LA
[16]
LAD
[2]
SD_TX
[6]
XGND
[18]
SGND
[19]
SVDD
[19]
LA
[27]
BVDD
[2]
LDP
[1]
BVDD
[7]
LAD
[0]
XVDD
[18]
SD_TX
[7]
SD_TX
[7]
SVDD
[20]
SD_RX
[7]
SD_RX
[7]
VDD_PL
[66]
VDD_PL
[67]
GND
[22]
VDD_PL
[68]
VDD_PL
[69]
GND
[19]
GND
[209]
LAD
[1]
SENSE-
GND_PL
[2]
SENSE-
VDD_PL
[2]
XVDD
[20]
XGND
[23]
SD_RX
[8]
SVDD
[21]
SGND
[21]
GND
[178]
GND
[193]
GND
[208]
GND
[225]
VDD_CA
[7]
VDD_PL
[80]
VDD_PL
[38]
VDD_PL
[1]
GND
[34]
XVDD
[21]
XGND
[24]
SD_TX
[8]
SD_TX
[8]
SVDD
[22]
SGND
[22]
VDD_CA
[6]
GND
[179]
VDD_CA
[8]
GND
[200]
VDD_PL
[71]
GND
[210]
VDD_PL
[45]
GND
[112]
VDD_PL
[51]
SD_TX
[9]
SD_TX
[9]
XVDD
[22]
SGND
[23]
SVDD
[23]
GND
[177]
GND
[192]
GND
[207]
GND
[224]
VDD_CA
[2]
VDD_PL
[83]
VDD_PL
[39]
VDD_PL
[2]
GND
[221]
XGND
[28]
XVDD
[23]
SD_TX
[10]
SD_TX
[10]
VDD_CA
[4]
GND
[180]
VDD_CA
[3]
GND
[199]
VDD_PL
[72]
GND
[211]
VDD_PL
[46]
GND
[111]
VDD_PL
[32]
XVDD
[26]
XGND
[31]
SVDD
[24]
SGND
[25]
GND
[176]
GND
[191]
GND
[206]
GND
[223]
VDD_CA
[1]
VDD_PL
[84]
VDD_PL
[40]
VDD_PL
[3]
GND
[226]
NC
[61]
XVDD
[27]
SGND
[26]
AVDD_
SRDS2
AGND_
SRDS2
VDD_PL
[91]
GND
[181]
VDD_PL
[75]
GND
[198]
VDD_PL
[33]
GND
[212]
VDD_PL
[47]
GND
[110]
VDD_PL
[52]
NC
[46]
XGND
[33]
SGND
[27]
GND
[175]
GND
[190]
GND
[205]
GND
[46]
VDD_PL
[28]
VDD_PL
[30]
VDD_PL
[41]
VDD_PL
[4]
GND
[227]
NC
[49]
XGND
[34]
XVDD
[30]
SGND
[28]
SVDD
[27]
XVDD
[16]
SD_IMP_
CAL_RX
NC
[32]
SVDD
[2]
SGND
[3]
NC
[59]
SGND
[10]
SVDD
[10]
SGND
[11]
SVDD
[11]
SVDD
[12]
SD_RX
[4]
SGND
[13]
SVDD
[14]
SGND
[15]
XGND
[10]
SD_TX
[1]
SD_TX
[4]
XVDD
[10]
SD_TX
[5]
XVDD
[11]
SD_TX
[0]
XGND
[13]
XGND
[14]
SD_TX
[5]
SGND
[17]
SD_TX
[0]
SD_TX
[2]
SD_TX
[2]
XVDD
[13]
XGND
[16]
XVDD
[14]
LA
[30]
XVDD
[15]
XGND
[19]
XVDD
[17]
SD_TX
[6]
GND
[15]
XGND
[20]
XGND
[22]
XVDD
[19]
XGND
[25]
XGND
[26]
XGND
[27]
XVDD
[24]
XGND
[29]
XVDD
[25]
XGND
[30]
SGND
[24]
SVDD
[25]
SD_TX
[11]
SD_TX
[11]
XVDD
[28]
SD_RX
[11]
SD_RX
[11]
XGND
[32]
XVDD
[29]
SVDD
[26]
XGND
[35]
XVDD
[31]
SD_
REF_
CLK2
SD_
REF_
CLK2
3619 24 25 26 27 28 29 30 31 32 33 34 35
A
B
C
D
E
F
G
H
J
K
L
M
N
T
2322
P
R
U
V
2120
DETAIL B
RSRV
[42]
RSRV
[43]
RSRV
[45]
RSRV
[46]
RSRV
[48]
RSRV
[50]
RSRV
[52]
RSRV
[54]
RSRV
[56]
6
1066A–HIREL–07/11
P4080
e2v semiconductors SAS 2011
Figure 1-4. P4080-1295 BGA Ball Map Diagram (Detail View C)
D2_
MDQ
[48]
D1_
MDQ
[54]
D1_
MDQ
[50]
D2_
MDQ
[56]
D2_
MDQ
[58]
D2_
MDQS
[6]
D2_
MDQ
[54]
D2_
MDQS
[7]
D1_
MDQ
[62]
D1_
MDQ
[59]
D2_
MDQ
[55]
D2_
MDQ
[61]
D2_
MDQ
[57]
D2_
MDQ
[63]
D2_
MDQ
[59]
D1_
MDQ
[56]
D1_
MDQS
[7]
D1_
MDQ
[58]
D2_
MCK
[0]
D1_
MCK
[0]
D2_
MDIC
[1]
D2_
MCS
[0]
D1_
MDQ
[33]
D1_
MDQ
[32]
D2_
MODT
[2]
D2_
MODT
[0]
D1_
MDM
[4]
D1_
MODT
[0]
D2_
MODT
[3]
D2_
MDQ
[37]
D1_
MDQ
[35]
D2_
MDM
[4]
D2_
MDQ
[32]
D1_
MDQ
[45]
D1_
MDQ
[44]
D1_
MODT
[1]
D2_
MDQ
[38]
D1_
MDQS
[5]
D1_
MDM
[5]
D2_
MDQ
[35]
D2_
MDQ
[34]
D1_
MDQ
[42]
D2_
MDQ
[45]
D2_
MDQ
[44]
D1_
MDQ
[53]
D1_
MCK
[5]
D2_
MDM
[5]
D2_
MDQ
[41]
D2_
MDQ
[40]
D1_
MDQ
[49]
D1_
MDM
[6]
D2_
MDQ
[52]
D2_
MDQS
[5]
D2_
MDQ
[46]
D1_
MDQS
[6]
D1_
MCK
[0]
GND
[53]
D1_
MCK
[3]
D1_
MCK
[3]
GVDD
[40]
VDD_PL
[10]
VDD_PL
[59]
VDD_CB
[1]
VDD_CB
[12]
GND
[123]
GND
[137]
GND
[150]
GND
[167]
GND
[52]
GVDD
[44]
D1_
MBA
[1]
GND
[117]
VDD_PL
[17]
GND
[131]
GND
[146]
GND
[163]
VDD_PL
[97]
VDD_CB
[7]
VDD_CB
[13]
D2_
MAPAR_
OUT
D1_
MDIC
[1]
GVDD
[41]
GND
[55]
VDD_PL
[11]
VDD_PL
[87]
VDD_CB
[8]
VDD_CB
[10]
GND
[122]
GND
[136]
GND
[152]
GND
[169]
D2_
MRAS
GVDD
[51]
GND
[56]
GVDD
[52]
GND
[118]
VDD_PL
[18]
GND
[132]
GND
[147]
GND
[164]
VDD_CB
[5]
VDD_CB
[15]
VDD_CB
[14]
GVDD
[45]
D2_MA
[13]
GND
[57]
GVDD
[53]
D1_
MCS
[0]
VDD_PL
[27]
VDD_PL
[82]
VDD_CB
[9]
VDD_CB
[11]
GND
[121]
GND
[135]
GND
[151]
GND
[168]
GND
[58]
GVDD
[46]
D1_
MODT
[2]
GND
[59]
GND
[119]
VDD_PL
[19]
GND
[133]
GND
[148]
GND
[165]
VDD_PL
[93]
VDD_PL
[94]
VDD_PL
[95]
D1_
MDQ
[39]
GND
[60]
GVDD
[47]
VDD_PL
[12]
VDD_PL
[20]
VDD_PL
[21]
VDD_PL
[23]
GND
[120]
GND
[134]
GND
[153]
GND
[170]
D2_
MODT
[1]
GVDD
[49]
GND
[61]
GVDD
[50]
D1_
MCS
[3]
SENSE-
VDD_PL
[1]
SENSE-
GND_PL
[1]
GND
[85]
GND
[149]
GND
[166]
VDD_PL
[70]
VDD_PL
[58]
VDD_PL
[60]
GND
[62]
D1_
MDQ
[40]
GVDD
[54]
GND
[63]
IRQ
[8]
IIC4_
SCL
SENSE-
VDD_CB
SENSE-
GND_CB
IRQ
[6]
D2_
MDQS
[4]
GVDD
[56]
D1_
MDQS
[5]
GND
[64]
GVDD
[55]
GND
[72]
IRQ
[10]
IIC1_
SCL
IRQ
[1]
IRQ
[4]
GVDD
[57]
D2_
MDQ
[39]
GND
[65]
D1_
MDQ
[46]
GVDD
[58]
GND
[71]
OVDD
[5]
IRQ
[5]
OVDD
[2]
IRQ
[3]
IRQ
[0]
EVT
[0]
OVDD
[3]
D2_
MCK
[5]
GND
[66]
GVDD
[60]
GND
[70]
IRQ
[9]
IRQ
[2]
IIC3_
SCL
IRQ_
OUT
GND
[78]
EVT
[3]
EVT
[1]
IO_
VSEL
[2]
D1_
MCK
[5]
GVDD
[61]
GND
[69]
D1_
MDQ
[48]
GVDD
[62]
IRQ
[11]
GND
[77]
IIC2_
SDA
IIC4_
SDA
OVDD
[4]
SCAN_
MODE
IO_
VSEL
[0]
GVDD
[63]
GND
[68]
GVDD
[64]
GND
[76]
IRQ
[7]
IIC3_
SDA
IIC2_
SCL
EVT
[4]
GND
[83]
IO_
VSEL
[3]
D2_
MDQ
[53]
GND
[67]
D2_
MDQ
[42]
D2_
MDQ
[43]
GVDD
[67]
D1_
MDQ
[55]
GND
[75]
D1_
MDQ
[51]
GVDD
[66]
IIC1_
SDA
GND
[82]
EVT
[2] TDI OVDD
[6]
D2_
MDM
[6]
D2_
MDQ
[49]
GVDD
[68]
D2_
MDM
[7]
GND
[74]
D1_
MDQ
[60]
GVDD
[65]
GND
[81] TDO OVDD
[11]
PORESET
IO_
VSEL
[1]
GVDD
[42]
D2_
MDQ
[60]
GND
[73]
D2_
MDQ
[62]
GVDD
[15]
D1_
MDQ
[61]
D1_
MDQ
[57]
GND
[80]
GVDD
[59] MDVAL GND
[92]
GND
[86]
HRESET
D2_
MDQ
[51]
D2_
MDQS
[7]
OVDD
[9]
RESET_
REQ POVDD
GVDD
[48]
AVDD_
CC3
D2_
MCK
[3]
D2_
MCK
[3]
D2_
MCK
[0]
GVDD
[43]
GND
[51]
D2_MA
[0]
D1_
MAPAR_
OUT
D1_MA
[0]
D2_
MBA
[1]
D2_MA
[10]
D2_
MBA
[0]
D2_
MDIC
[0]
D1_MA
[10]
D1_
MBA
[0]
D1_
MRAS
D2_
MWE
D2_
MCS
[2]
D1_
MDQ
[36]
D1_
MDQ
[37]
D1_
MWE
D1_
MCS
[2]
D2_
MCAS
D1_
MCAS
D1_
MDQS
[4]
D1_
MDQS
[4]
D2_
MCS
[1]
D2_
MCS
[3]
D1_
MDQ
[38]
D1_MA
[13]
D1_
MCS
[1]
D2_
MDQ
[36]
D1_
MDQ
[34]
D1_
MODT
[3]
D2_
MDQ
[33]
D2_
MDQS
[4]
D1_
MDQ
[41]
MSRCID
[2]
GND
[79]
D1_
MDQ
[47]
D1_
MDQ
[43]
D2_
MCK
[5]
D1_
MDQ
[52]
GVDD
[39]
D2_
MDQS
[5]
D2_
MDQ
[47]
D1_
MDQS
[6]
NC
[44]
NC
[27]
D2_
MDQS
[6]
NC
[45]
D1_
MDQ
[63]
NC
[54]
D2_
MDQ
[50]
D1_
MDM
[7]
D1_
MDQS
[7]
NC
[41]
1181312111098765432
AT
AR
AP
AN
AM
AL
AK
AJ
AH
AG
AF
AE
AD
AA
14 15
AC
AB
Y
W
16 17
DETAIL C
RSRV
[49]
RSRV
[51]
RSRV
[53]
RSRV
[55]
7
1066A–HIREL–07/11
e2v semiconductors SAS 2011
P4080
Figure 1-5. P4080-1295 BGA Ball Map Diagram (Detail View D)
SD_RX
[16]
TMS
TMS
SDHC_
DAT
[3]
RSRV
[24]
VDD_CB
[2]
GND
[185]
VDD_PL
[76]
GND
[197]
VDD_PL
[34]
GND
[213]
VDD_PL
[48]
GND
[109]
VDD_PL
[53]
NC
[62]
SD_TX
[12]
SD_TX
[12]
XGND
[36]
SD_RX
[12]
SD_RX
[12]
SGND
[29]
SVDD
[28]
GND
[174]
GND
[189]
GND
[204]
GND
[220]
VDD_CB
[4]
VDD_PL
[85]
VDD_PL
[42]
VDD_PL
[5]
GND
[228]
NC
[26]
SD_TX
[13]
SVDD
[29]
SGND
[30]
SD_RX
[13]
SD_RX
[13]
VDD_CB
[3]
GND
[183]
VDD_CB
[6]
GND
[196]
VDD_PL
[73]
GND
[214]
VDD_PL
[49]
GND
[108]
VDD_PL
[35]
NC
[12]
XVDD
[1]
SD_TX
[14]
SD_RX
[14]
SD_RX
[14]
SGND
[4]
GND
[173]
GND
[188]
GND
[203]
GND
[219]
VDD_CB
[17]
VDD_PL
[86]
VDD_PL
[43]
VDD_PL
[6]
GND
[87]
NC
[2]
NC
[29]
SD_TX
[15]
XGND
[2]
SGND
[5]
SVDD
[4]
AVDD_
SRDS3
AGND_
SRDS3
VDD_CB
[16]
GND
[184]
VDD_PL
[78]
GND
[195]
VDD_PL
[74]
GND
[215]
VDD_PL
[50]
GND
[107]
VDD_PL
[36]
NC
[11]
NC
[4]
XVDD
[4]
GND
[172]
GND
[187]
GND
[202]
GND
[218]
VDD_PL
[96]
VDD_PL
[79]
VDD_PL
[44]
VDD_PL
[7]
GND
[229]
NC
[31]
NC
[15]
XGND
[5]
SD_
REF_
CLK3
SD_
REF_
CLK3
SGND
[6]
SVDD
[5]
VDD_PL
[25]
GND
[182]
VDD_PL
[29]
GND
[194]
VDD_PL
[37]
GND
[216]
VDD_PL
[54]
GND
[106]
GND
[97]
NC
[18]
NC
[8]
SVDD
[6]
SGND
[7]
GND
[171]
GND
[186]
GND
[201]
GND
[217]
VDD_PL
[57]
VDD_PL
[56]
VDD_PL
[55]
NC
[19]
NC
[60]
NC
[53]
NC
[10]
SD_RX
[16]
SVDD
[7]
SGND
[8]
DMA2_
DACK
[0]
GPIO
[7]
OVDD
[7]
SDHC_
CMD
RSRV
[19]
NC
[17]
NC
[47]
NC
[50]
NC
[9]
IO_
VSEL
[4]
MSRCID
[0]
GPIO
[4]
GND
[89]
RSRV
[6]
RSRV
[4]
RSRV
[14]
RSRV
[11]
SPI_
MISO
NC
[25]
NC
[24]
GND
[102]
EMI2_
MDIO
EMI2_
MDC
MSRCID
[1]
DMA2_
DREQ
[0]
GPIO
[5]
OVDD
[10]
RSRV
[26]
RSRV
[5]
RSRV
[18]
RSRV
[15]
SPI_CS
[1]
CVDD
[1]
GND
[100]
EMI1_
MDC
LVDD
[5]
GND
[84]
CLK_
OUT
GPIO
[6]
GPIO
[1]
RSRV
[35]
RSRV
[10]
RSRV
[7]
RSRV
[37]
GND
[96]
SPI_
CLK
LVDD
[1]
DMA1_
DACK
[0]
OVDD
[8]
GPIO
[0]
SDHC_
CLK
RSRV
[33]
RSRV
[2]
RSRV
[34]
RSRV
[30]
RSRV
[23]
GND
[91]
LV DD
[3]
EMI1_
MDIO
RSRV
[41]
GND
[104]
TSEC_
1588_CLK
_IN
SDHC_
DAT
[2]
GND
[90]
GPIO
[2]
CKSTP_
OUT
RSRV
[29]
RSRV
[21]
RSRV
[39]
RSRV
[8]
RSRV
[27]
SPI_CS
[3]
GND
[105]
EC1_
RXD
[3]
LVDD
[7]
OVDD
[1]
DMA1_
DDONE
[0]
GPIO
[3]
TMP_
DETECT RTC RSRV
[36]
RSRV
[17]
RSRV
[40]
RSRV
[1]
SPI_CS
[0]
GND
[101]
EC2_
GTX_
CLK
EC2_
RXD
[2]
LVDD
[4]
EC1_
RXD
[2]
EC1_
RXD
[1]
EC1_
RXD
[0]
GND
[88]
DMA2_
DDONE
[0]
DMA1_
DREQ
[0]
GND
[94]
SDHC_
DAT
[0]
RSRV
[38]
RSRV
[25]
RSRV
[20]
RSRV
[22]
CVDD
[2]
EC2_
TXD
[2]
LV DD
[2]
EC2_
RXD
[1]
EC2_
RXD
[3]
GND
[99]
EC1_
GTX_
CLK
EC1_
TXD
[3]
TRST ASLEEP TCK OVDD
[12]
RSRV
[28]
RSRV
[12]
RSRV
[9]
RSRV
[3]
SPI_CS
[2]
EC2_
TXD
[1]
EC2_
TX_EN
GND
[95]
EC1_
RX_DV
EC2_
RX_DV
EC1_
TXD
[1]
LVDD
[6]
EC1_
TX_EN
AVDD_
PLAT
TEST_
SEL
GND
[93] SYSCLK
SDHC_
DAT
[1]
RSRV
[32]
RSRV
[16]
RSRV
[13]
RSRV
[31]
SPI_
MOSI
EC2_
TXD
[0]
EC2_
TXD
[3]
EC2_
RXD
[0]
EC2_
RX_CLK
EC1_
TXD
[2]
EC1_
TXD
[0]
GND
[103]
EC1_
RX_CLK
AVDD_
CC4
EC_XTRNL
_TX_STMP
[1]
EC_XTRNL
_TX_STMP
[2]
EC_XTRNL
_RX_STMP
[2]
TSEC_
1588_CLK_
OUT
TSEC_
1588_PULSE
_OUT[1]
TSEC_
1588_PULSE
_OUT[2]
EC_
GTX_
CLK125
EC_XTRNL
_RX_STMP
[1]
TSEC_
1588_ALARM
_OUT[2]
TSEC_
1588_ALARM
_OUT[1]
TSEC_
1588_TRIG
_IN[2]
TSEC_
1588_TRIG
_IN[1]
SD_IMP_
CAL_TX
XVDD
[32]
SD_TX
[13]
XVDD
[33]
XGND
[37]
XGND
[1]
SD_TX
[14]
SVDD
[3]
SD_TX
[15]
XVDD
[2]
XVDD
[3]
XGND
[3]
SD_RX
[15]
SD_RX
[15]
XGND
[4]
XGND
[6]
XVDD
[5]
XVDD
[6]
SD_TX
[16]
SD_TX
[16]
XVDD
[7]
XGND
[7]
XGND
[8]
SD_TX
[17]
SD_TX
[17]
SGND
[9]
SVDD
[8]
SD_RX
[17]
SD_RX
[17]
UART2_
CTS
UART2_
SOUT
UART2_
RTS
UART1_
SOUT
UART1_
RTS
UART2_
SIN
UART1_
CTS
UART1_
SIN
3619 24 25 26 27 28 29 30 31 32 33 34 35
AT
AR
AP
AN
AM
AL
AK
AJ
AH
AG
AF
AE
AD
AA
2322
AC
AB
Y
W
2120
DETAIL D
XGND
[38]
XVDD
[34]
SGND
[32]
SGND
[31]
SVDD
[30]
RSRV
[44]
RSRV
[47]
8
1066A–HIREL–07/11
P4080
e2v semiconductors SAS 2011
1.2 Pinout List
Table 1-1 provides the pinout listing for the P4080 by bus.
Table 1-1. P4080 Pins List by Bus
Signal Signal Description
Package Pin
Number Pin Type
Power
Supply Notes
DDR SDRAM Memory Interface(1)
D1_MDQ00 Data A17 I/O GVDD –
D1_MDQ01 Data D17 I/O GVDD –
D1_MDQ02 Data C14 I/O GVDD –
D1_MDQ03 Data A14 I/O GVDD –
D1_MDQ04 Data C17 I/O GVDD –
D1_MDQ05 Data B17 I/O GVDD –
D1_MDQ06 Data A15 I/O GVDD –
D1_MDQ07 Data B15 I/O GVDD –
D1_MDQ08 Data D15 I/O GVDD –
D1_MDQ09 Data G15 I/O GVDD –
D1_MDQ10 Data E12 I/O GVDD –
D1_MDQ11 Data G12 I/O GVDD –
D1_MDQ12 Data F16 I/O GVDD –
D1_MDQ13 Data E15 I/O GVDD –
D1_MDQ14 Data E13 I/O GVDD –
D1_MDQ15 Data F13 I/O GVDD –
D1_MDQ16 Data C8 I/O GVDD –
D1_MDQ17 Data D12 I/O GVDD –
D1_MDQ18 Data E9 I/O GVDD –
D1_MDQ19 Data E10 I/O GVDD –
D1_MDQ20 Data C11 I/O GVDD –
D1_MDQ21 Data C10 I/O GVDD –
D1_MDQ22 Data E6 I/O GVDD –
D1_MDQ23 Data E7 I/O GVDD –
D1_MDQ24 Data F7 I/O GVDD –
D1_MDQ25 Data F11 I/O GVDD –
D1_MDQ26 Data H10 I/O GVDD –
D1_MDQ27 Data J10 I/O GVDD –
D1_MDQ28 Data F10 I/O GVDD –
D1_MDQ29 Data F8 I/O GVDD –
D1_MDQ30 Data H7 I/O GVDD –
D1_MDQ31 Data H9 I/O GVDD –
D1_MDQ32 Data AC7 I/O GVDD –
D1_MDQ33 Data AC6 I/O GVDD –
9
1066A–HIREL–07/11
e2v semiconductors SAS 2011
P4080
D1_MDQ34 Data AF6 I/O GVDD –
D1_MDQ35 Data AF7 I/O GVDD –
D1_MDQ36 Data AB5 I/O GVDD –
D1_MDQ37 Data AB6 I/O GVDD –
D1_MDQ38 Data AE5 I/O GVDD –
D1_MDQ39 Data AE6 I/O GVDD –
D1_MDQ40 Data AG5 I/O GVDD –
D1_MDQ41 Data AH9 I/O GVDD –
D1_MDQ42 Data AJ9 I/O GVDD –
D1_MDQ43 Data AJ10 I/O GVDD –
D1_MDQ44 Data AG8 I/O GVDD –
D1_MDQ45 Data AG7 I/O GVDD –
D1_MDQ46 Data AJ6 I/O GVDD –
D1_MDQ47 Data AJ7 I/O GVDD –
D1_MDQ48 Data AL9 I/O GVDD –
D1_MDQ49 Data AL8 I/O GVDD –
D1_MDQ50 Data AN10 I/O GVDD –
D1_MDQ51 Data AN11 I/O GVDD –
D1_MDQ52 Data AK8 I/O GVDD –
D1_MDQ53 Data AK7 I/O GVDD –
D1_MDQ54 Data AN7 I/O GVDD –
D1_MDQ55 Data AN8 I/O GVDD –
D1_MDQ56 Data AT9 I/O GVDD –
D1_MDQ57 Data AR10 I/O GVDD –
D1_MDQ58 Data AT13 I/O GVDD –
D1_MDQ59 Data AR13 I/O GVDD –
D1_MDQ60 Data AP9 I/O GVDD –
D1_MDQ61 Data AR9 I/O GVDD –
D1_MDQ62 Data AR12 I/O GVDD –
D1_MDQ63 Data AP12 I/O GVDD –
D1_MECC0 Error Correcting Code K9 I/O GVDD –
D1_MECC1 Error Correcting Code J5 I/O GVDD –
D1_MECC2 Error Correcting Code L10 I/O GVDD –
D1_MECC3 Error Correcting Code M10 I/O GVDD –
D1_MECC4 Error Correcting Code J8 I/O GVDD –
D1_MECC5 Error Correcting Code J7 I/O GVDD –
D1_MECC6 Error Correcting Code L7 I/O GVDD –
Table 1-1. P4080 Pins List by Bus (Continued)
Signal Signal Description
Package Pin
Number Pin Type
Power
Supply Notes
10
1066A–HIREL–07/11
P4080
e2v semiconductors SAS 2011
D1_MECC7 Error Correcting Code L9 I/O GVDD –
D1_MAPAR_ERR Address Parity Error N8 I GVDD (4)
D1_MAPAR_OUT Address Parity Out Y7 O GVDD –
D1_MDM0 Data Mask A16 O GVDD –
D1_MDM1 Data Mask D14 O GVDD –
D1_MDM2 Data Mask D11 O GVDD –
D1_MDM3 Data Mask G11 O GVDD –
D1_MDM4 Data Mask AD7 O GVDD –
D1_MDM5 Data Mask AH8 O GVDD –
D1_MDM6 Data Mask AL11 O GVDD –
D1_MDM7 Data Mask AT10 O GVDD –
D1_MDM8 Data Mask K8 O GVDD –
D1_MDQS0 Data Strobe C16 I/O GVDD –
D1_MDQS1 Data Strobe G14 I/O GVDD –
D1_MDQS2 Data Strobe D9 I/O GVDD –
D1_MDQS3 Data Strobe G9 I/O GVDD –
D1_MDQS4 Data Strobe AD5 I/O GVDD –
D1_MDQS5 Data Strobe AH6 I/O GVDD –
D1_MDQS6 Data Strobe AM10 I/O GVDD –
D1_MDQS7 Data Strobe AT12 I/O GVDD –
D1_MDQS8 Data Strobe K6 I/O GVDD –
D1_MDQS0 Data Strobe B16 I/O GVDD –
D1_MDQS1 Data Strobe F14 I/O GVDD –
D1_MDQS2 Data Strobe D8 I/O GVDD –
D1_MDQS3 Data Strobe G8 I/O GVDD –
D1_MDQS4 Data Strobe AD4 I/O GVDD –
D1_MDQS5 Data Strobe AH5 I/O GVDD –
D1_MDQS6 Data Strobe AM9 I/O GVDD –
D1_MDQS7 Data Strobe AT11 I/O GVDD –
D1_MDQS8 Data Strobe K5 I/O GVDD –
D1_MBA0 Bank Select AA8 O GVDD –
D1_MBA1 Bank Select Y10 O GVDD –
D1_MBA2 Bank Select M8 O GVDD –
D1_MA00 Address Y9 O GVDD –
D1_MA01 Address U6 O GVDD –
D1_MA02 Address U7 O GVDD –
D1_MA03 Address U9 O GVDD –
Table 1-1. P4080 Pins List by Bus (Continued)
Signal Signal Description
Package Pin
Number Pin Type
Power
Supply Notes
11
1066A–HIREL–07/11
e2v semiconductors SAS 2011
P4080
D1_MA04 Address U10 O GVDD –
D1_MA05 Address T8 O GVDD –
D1_MA06 Address T9 O GVDD –
D1_MA07 Address R8 O GVDD –
D1_MA08 Address R7 O GVDD –
D1_MA09 Address P6 O GVDD –
D1_MA10 Address AA7 O GVDD –
D1_MA11 Address P7 O GVDD –
D1_MA12 Address N6 O GVDD –
D1_MA13 Address AE8 O GVDD –
D1_MA14 Address M7 O GVDD –
D1_MA15 Address L6 O GVDD –
D1_MWE Write Enable AB8 O GVDD –
D1_MRAS Row Address Strobe AA10 O GVDD –
D1_MCAS Column Address Strobe AC10 O GVDD –
D1_MCS0 Chip Select AC9 O GVDD –
D1_MCS1 Chip Select AE9 O GVDD –
D1_MCS2 Chip Select AB9 O GVDD –
D1_MCS3 Chip Select AF9 O GVDD –
D1_MCKE0 Clock Enable P10 O GVDD –
D1_MCKE1 Clock Enable R10 O GVDD –
D1_MCKE2 Clock Enable P9 O GVDD –
D1_MCKE3 Clock Enable N9 O GVDD –
D1_MCK0 Clock W6 O GVDD –
D1_MCK1 Clock V6 O GVDD –
D1_MCK2 Clock V8 O GVDD –
D1_MCK3 Clock W9 O GVDD –
D1_MCK4 Clock F1 O GVDD –
D1_MCK5 Clock AL1 O GVDD –
D1_MCK0 Clock Complements W5 O GVDD –
D1_MCK1 Clock Complements V5 O GVDD –
D1_MCK2 Clock Complements V9 O GVDD –
D1_MCK3 Clock Complements W8 O GVDD –
D1_MCK4 Clock Complements F2 O GVDD –
D1_MCK5 Clock Complements AL2 O GVDD –
D1_MODT0 On Die Termination AD10 O GVDD –
D1_MODT1 On Die Termination AG10 O GVDD –
Table 1-1. P4080 Pins List by Bus (Continued)
Signal Signal Description
Package Pin
Number Pin Type
Power
Supply Notes
12
1066A–HIREL–07/11
P4080
e2v semiconductors SAS 2011
D1_MODT2 On Die Termination AD8 O GVDD –
D1_MODT3 On Die Termination AF10 O GVDD –
D1_MDIC0 Driver Impedance Calibration T6 I/O GVDD (16)
D1_MDIC1 Driver Impedance Calibration AA5 I/O GVDD (16)
DDR SDRAM Memory Interface 2
D2_MDQ00 Data C13 I/O GVDD –
D2_MDQ01 Data A12 I/O GVDD –
D2_MDQ02 Data B9 I/O GVDD –
D2_MDQ03 Data A8 I/O GVDD –
D2_MDQ04 Data A13 I/O GVDD –
D2_MDQ05 Data B13 I/O GVDD –
D2_MDQ06 Data B10 I/O GVDD –
D2_MDQ07 Data A9 I/O GVDD –
D2_MDQ08 Data A7 I/O GVDD –
D2_MDQ09 Data D6 I/O GVDD –
D2_MDQ10 Data A4 I/O GVDD –
D2_MDQ11 Data B4 I/O GVDD –
D2_MDQ12 Data C7 I/O GVDD –
D2_MDQ13 Data B7 I/O GVDD –
D2_MDQ14 Data C5 I/O GVDD –
D2_MDQ15 Data D5 I/O GVDD –
D2_MDQ16 Data B1 I/O GVDD –
D2_MDQ17 Data B3 I/O GVDD –
D2_MDQ18 Data D3 I/O GVDD –
D2_MDQ19 Data E1 I/O GVDD –
D2_MDQ20 Data A3 I/O GVDD –
D2_MDQ21 Data A2 I/O GVDD –
D2_MDQ22 Data D1 I/O GVDD –
D2_MDQ23 Data D2 I/O GVDD –
D2_MDQ24 Data F4 I/O GVDD –
D2_MDQ25 Data F5 I/O GVDD –
D2_MDQ26 Data H4 I/O GVDD –
D2_MDQ27 Data H6 I/O GVDD –
D2_MDQ28 Data E4 I/O GVDD –
D2_MDQ29 Data E3 I/O GVDD –
D2_MDQ30 Data H3 I/O GVDD –
D2_MDQ31 Data H1 I/O GVDD –
Table 1-1. P4080 Pins List by Bus (Continued)
Signal Signal Description
Package Pin
Number Pin Type
Power
Supply Notes
13
1066A–HIREL–07/11
e2v semiconductors SAS 2011
P4080
D2_MDQ32 Data AG4 I/O GVDD –
D2_MDQ33 Data AG2 I/O GVDD –
D2_MDQ34 Data AJ3 I/O GVDD –
D2_MDQ35 Data AJ1 I/O GVDD –
D2_MDQ36 Data AF4 I/O GVDD –
D2_MDQ37 Data AF3 I/O GVDD –
D2_MDQ38 Data AH1 I/O GVDD –
D2_MDQ39 Data AJ4 I/O GVDD –
D2_MDQ40 Data AL6 I/O GVDD –
D2_MDQ41 Data AL5 I/O GVDD –
D2_MDQ42 Data AN4 I/O GVDD –
D2_MDQ43 Data AN5 I/O GVDD –
D2_MDQ44 Data AK5 I/O GVDD –
D2_MDQ45 Data AK4 I/O GVDD –
D2_MDQ46 Data AM6 I/O GVDD –
D2_MDQ47 Data AM7 I/O GVDD –
D2_MDQ48 Data AN1 I/O GVDD –
D2_MDQ49 Data AP3 I/O GVDD –
D2_MDQ50 Data AT1 I/O GVDD –
D2_MDQ51 Data AT2 I/O GVDD –
D2_MDQ52 Data AM1 I/O GVDD –
D2_MDQ53 Data AN2 I/O GVDD –
D2_MDQ54 Data AR3 I/O GVDD –
D2_MDQ55 Data AT3 I/O GVDD –
D2_MDQ56 Data AP5 I/O GVDD –
D2_MDQ57 Data AT5 I/O GVDD –
D2_MDQ58 Data AP8 I/O GVDD –
D2_MDQ59 Data AT8 I/O GVDD –
D2_MDQ60 Data AR4 I/O GVDD –
D2_MDQ61 Data AT4 I/O GVDD –
D2_MDQ62 Data AR7 I/O GVDD –
D2_MDQ63 Data AT7 I/O GVDD –
D2_MECC0 Error Correcting Code J1 I/O GVDD –
D2_MECC1 Error Correcting Code K3 I/O GVDD –
D2_MECC2 Error Correcting Code M5 I/O GVDD –
D2_MECC3 Error Correcting Code N5 I/O GVDD –
D2_MECC4 Error Correcting Code J4 I/O GVDD –
Table 1-1. P4080 Pins List by Bus (Continued)
Signal Signal Description
Package Pin
Number Pin Type
Power
Supply Notes
14
1066A–HIREL–07/11
P4080
e2v semiconductors SAS 2011
D2_MECC5 Error Correcting Code J2 I/O GVDD –
D2_MECC6 Error Correcting Code L3 I/O GVDD –
D2_MECC7 Error Correcting Code L4 I/O GVDD –
D2_MAPAR_ERR Address Parity Error N2 I GVDD (4)
D2_MAPAR_OUT Address Parity Out Y1 O GVDD –
D2_MDM0 Data Mask B12 O GVDD –
D2_MDM1 Data Mask B6 O GVDD –
D2_MDM2 Data Mask C4 O GVDD –
D2_MDM3 Data Mask G3 O GVDD –
D2_MDM4 Data Mask AG1 O GVDD –
D2_MDM5 Data Mask AL3 O GVDD –
D2_MDM6 Data Mask AP2 O GVDD –
D2_MDM7 Data Mask AP6 O GVDD –
D2_MDM8 Data Mask K2 O GVDD –
D2_MDQS0 Data Strobe A10 I/O GVDD –
D2_MDQS1 Data Strobe A5 I/O GVDD –
D2_MDQS2 Data Strobe C2 I/O GVDD –
D2_MDQS3 Data Strobe G6 I/O GVDD –
D2_MDQS4 Data Strobe AH2 I/O GVDD –
D2_MDQS5 Data Strobe AM4 I/O GVDD –
D2_MDQS6 Data Strobe AR1 I/O GVDD –
D2_MDQS7 Data Strobe AR6 I/O GVDD –
D2_MDQS8 Data Strobe L1 I/O GVDD –
D2_MDQS0 Data Strobe A11 I/O GVDD –
D2_MDQS1 Data Strobe A6 I/O GVDD –
D2_MDQS2 Data Strobe C1 I/O GVDD –
D2_MDQS3 Data Strobe G5 I/O GVDD –
D2_MDQS4 Data Strobe AH3 I/O GVDD –
D2_MDQS5 Data Strobe AM3 I/O GVDD –
D2_MDQS6 Data Strobe AP1 I/O GVDD –
D2_MDQS7 Data Strobe AT6 I/O GVDD –
D2_MDQS8 Data Strobe K1 I/O GVDD –
D2_MBA0 Bank Select AA3 O GVDD –
D2_MBA1 Bank Select AA1 O GVDD –
D2_MBA2 Bank Select M1 O GVDD –
D2_MA00 Address Y4 O GVDD –
D2_MA01 Address U1 O GVDD –
Table 1-1. P4080 Pins List by Bus (Continued)
Signal Signal Description
Package Pin
Number Pin Type
Power
Supply Notes
15
1066A–HIREL–07/11
e2v semiconductors SAS 2011
P4080
D2_MA02 Address U4 O GVDD –
D2_MA03 Address T1 O GVDD –
D2_MA04 Address T2 O GVDD –
D2_MA05 Address T3 O GVDD –
D2_MA06 Address R1 O GVDD –
D2_MA07 Address R4 O GVDD –
D2_MA08 Address R2 O GVDD –
D2_MA09 Address P1 O GVDD –
D2_MA10 Address AA2 O GVDD –
D2_MA11 Address P3 O GVDD –
D2_MA12 Address N1 O GVDD –
D2_MA13 Address AC4 O GVDD –
D2_MA14 Address N3 O GVDD –
D2_MA15 Address M2 O GVDD –
D2_MWE Write Enable AB2 O GVDD –
D2_MRAS Row Address Strobe AB1 O GVDD –
D2_MCAS Column Address Strobe AC3 O GVDD –
D2_MCS0 Chip Select AC1 O GVDD –
D2_MCS1 Chip Select AE1 O GVDD –
D2_MCS2 Chip Select AB3 O GVDD –
D2_MCS3 Chip Select AE2 O GVDD –
D2_MCKE0 Clock Enable R5 O GVDD –
D2_MCKE1 Clock Enable T5 O GVDD –
D2_MCKE2 Clock Enable P4 O GVDD –
D2_MCKE3 Clock Enable M4 O GVDD –
D2_MCK0 Clock W3 O GVDD –
D2_MCK1 Clock V3 O GVDD –
D2_MCK2 Clock V1 O GVDD –
D2_MCK3 Clock W2 O GVDD –
D2_MCK4 Clock G1 O GVDD –
D2_MCK5 Clock AK2 O GVDD –
D2_MCK0 Clock Complements W4 O GVDD –
D2_MCK1 Clock Complements V4 O GVDD –
D2_MCK2 Clock Complements V2 O GVDD –
D2_MCK3 Clock Complements W1 O GVDD –
D2_MCK4 Clock Complements G2 O GVDD –
D2_MCK5 Clock Complements AK1 O GVDD –
Table 1-1. P4080 Pins List by Bus (Continued)
Signal Signal Description
Package Pin
Number Pin Type
Power
Supply Notes
16
1066A–HIREL–07/11
P4080
e2v semiconductors SAS 2011
D2_MODT0 On Die Termination AD2 O GVDD –
D2_MODT1 On Die Termination AF1 O GVDD –
D2_MODT2 On Die Termination AD1 O GVDD –
D2_MODT3 On Die Termination AE3 O GVDD –
D2_MDIC0 Driver Impedance Calibration AA4 I/O GVDD (16)
D2_MDIC1 Driver Impedance Calibration Y6 I/O GVDD (16)
Local Bus Controller Interface
LAD00 Muxed Data/Address K26 I/O BVDD (3)
LAD01 Muxed Data/Address L26 I/O BVDD (3)
LAD02 Muxed Data/Address J26 I/O BVDD (3)
LAD03 Muxed Data/Address H25 I/O BVDD (3)
LAD04 Muxed Data/Address F25 I/O BVDD (3)
LAD05 Muxed Data/Address H24 I/O BVDD (3)
LAD06 Muxed Data/Address G24 I/O BVDD (3)
LAD07 Muxed Data/Address G23 I/O BVDD (3)
LAD08 Muxed Data/Address E23 I/O BVDD (3)
LAD09 Muxed Data/Address D23 I/O BVDD (3)
LAD10 Muxed Data/Address J22 I/O BVDD (3)
LAD11 Muxed Data/Address G22 I/O BVDD (3)
LAD12 Muxed Data/Address F19 I/O BVDD (3)
LAD13 Muxed Data/Address J18 I/O BVDD (3)
LAD14 Muxed Data/Address K18 I/O BVDD (3)
LAD15 Muxed Data/Address J17 I/O BVDD (3)
LDP0 Data Parity J24 I/O BVDD –
LDP1 Data Parity K23 I/O BVDD –
LA16 Address J25 O BVDD (35)
LA17 Address G25 O BVDD (35)
LA18 Address H23 O BVDD (35)
LA19 Address F22 O BVDD (35)
LA20 Address H22 O BVDD (35)
LA21 Address E21 O BVDD (35)
LA22 Address F21 O BVDD (35)
LA23 Address H21 O BVDD (3)(4)
LA24 Address K21 O BVDD (3)(4)(38)
LA25 Address G20 O BVDD (35)
LA26 Address J20 O BVDD –
LA27 Address K20 O BVDD –
Table 1-1. P4080 Pins List by Bus (Continued)
Signal Signal Description
Package Pin
Number Pin Type
Power
Supply Notes
17
1066A–HIREL–07/11
e2v semiconductors SAS 2011
P4080
LA28 Address G19 O BVDD –
LA29 Address H19 O BVDD –
LA30 Address J19 O BVDD –
LA31 Address G18 O BVDD –
LCS0 Chip Selects D19 O BVDD (5)
LCS1 Chip Selects D20 O BVDD (5)
LCS2 Chip Selects E20 O BVDD (5)
LCS3 Chip Selects D21 O BVDD (5)
LCS4 Chip Selects D22 O BVDD (5)
LCS5 Chip Selects B23 O BVDD (5)
LCS6 Chip Selects F24 O BVDD (5)
LCS7 Chip Selects G26 O BVDD (5)
LWE0 Write Enable D24 O BVDD –
LWE1 Write Enable A24 O BVDD –
LBCTL Buffer Control C22 O BVDD –
LALE Address Latch Enable A23 I/O BVDD –
LGPL0 UPM General Purpose Line 0/ LFCLE–FCM B25 O BVDD (3)(4)
LGPL1 UPM General Purpose Line 1/ LFALE–FCM E25 O BVDD (3)(4)
LGPL2 UPM General Purpose Line 2/ LOE_B–Output
Enable D25 O BVDD (3)(4)
LGPL3 UPM General Purpose LIne 3/ LFWP_B–FCM H26 O BVDD (3)(4)
LGPL4 UPM General Purpose Line 4/ LGTA_B–FCM C25 I/O BVDD –
LGPL5 UPM General Purpose Line 5 / Amux E26 O BVDD (3)(4)
LCLK0 Local Bus Clock C24 O BVDD –
LCLK1 Local Bus Clock C23 O BVDD –
DMA
DMA1_DREQ0/GPIO18 DMA1 Channel 0 Request AP21 I OVDD (27)
DMA1_DACK0/GPIO19 DMA1 Channel 0 Acknowledge AL19 O OVDD (27)
DMA1_DDONE0 DMA1 Channel 0 Done AN21 O OVDD (4)(28)
DMA2_DREQ0/GPIO20/ALT_MDVAL DMA2 Channel 0 Request AJ20 I OVDD (27)
DMA2_DACK0/EV7/ALT_MDSRCID0 DMA2 Channel 0 Acknowledge AG19 O OVDD (27)
DMA2_DDONE0/EVT8/ALT_MDSRCID1 DMA2 Channel 0 Done AP20 O OVDD (27)
USB Host Port 1
USB1_D7/EC1_TXD3 USB1 Data bits AP36 I/O LVDD (35)
USB1_D6/EC1_TXD2 USB1 Data bits AT34 I/O LVDD (35)
USB1_D5/EC1_TXD1 USB1 Data bits AR34 I/O LVDD (35)
USB1_D4/EC1_TXD0 USB1 Data bits AT35 I/O LVDD (35)
Table 1-1. P4080 Pins List by Bus (Continued)
Signal Signal Description
Package Pin
Number Pin Type
Power
Supply Notes
18
1066A–HIREL–07/11
P4080
e2v semiconductors SAS 2011
USB1_D3/EC1_RXD3 USB1 Data bits AM33 I/O LVDD (28)
USB1_D2/EC1_RXD2 USB1 Data bits AN34 I/O LVDD (28)
USB1_D1/EC1_RXD1 USB1 Data bits AN35 I/O LVDD (28)
USB1_D0/EC1_RXD0 USB1 Data bits AN36 I/O LVDD (28)
USB1_STP/EC1_TX_EN USB1 Stop AR36 O LVDD –
USB1_NXT/EC1_RX_DV USB1 Next data AM34 I LVDD (28)
USB1_DIR/EC1_RX_CLK USB1 Data Direction AM36 I LVDD (28)
USB1_CLK/EC1_GTX_CLK USB1 bus clock AP35 I LVDD (27)
USB Host Port 2
USB2_D7/EC2_TXD3 USB2 Data bits AT31 I/O LVDD (35)
USB2_D6/EC2_TXD2 USB2 Data bits AP30 I/O LVDD (35)
USB2_D5/EC2_TXD1 USB2 Data bits AR30 I/O LVDD (35)
USB2_D4/EC2_TXD0 USB2 Data bits AT30 I/O LVDD (35)
USB2_D3/EC2_RXD3 USB2 Data bits AP33 I/O LVDD (28)
USB2_D2/EC2_RXD2 USB2 Data bits AN32 I/O LVDD (28)
USB2_D1/EC2_RXD1 USB2 Data bits AP32 I/O LVDD (28)
USB2_D0/EC2_RXD0 USB2 Data bits AT32 I/O LVDD (28)
USB2_STP/EC2_TX_EN USB2 Stop AR31 O LVDD –
USB2_NXT/EC2_RX_DV USB2 Next data AR33 I LVDD (28)
USB2_DIR/EC2_RX_CLK USB2 Data Direction AT33 I LVDD (28)
USB2_CLK/EC2_GTX_CLK USB2 bus clock AN31 I LVDD (27)
Programmable Interrupt Controller
IRQ00 External Interrupts AJ16 I OVDD –
IRQ01 External Interrupts AH16 I OVDD –
IRQ02 External Interrupts AK12 I OVDD –
IRQ03/GPIO21 External Interrupts AJ15 I OVDD (27)
IRQ04/GPIO22 External Interrupts AH17 I OVDD (27)
IRQ05/GPIO23 External Interrupts AJ13 I OVDD (27)
IRQ06/GPIO24 External Interrupts AG17 I OVDD (27)
IRQ07/GPIO25 External Interrupts AM13 I OVDD (27)
IRQ08/GPIO26 External Interrupts AG13 I OVDD (27)
IRQ09/GPIO27 External Interrupts AK11 I OVDD (27)
IRQ10/GPIO28 External Interrupts AH14 I OVDD (27)
IRQ11/GPIO29 External Interrupts AL12 I OVDD (27)
IRQ_OUT/EVT9 Interrupt Output AK14 O OVDD (1)(2)(27)
TMP_DETECT Tamper Detect AN19 I OVDD (28)
eSDHC
Table 1-1. P4080 Pins List by Bus (Continued)
Signal Signal Description
Package Pin
Number Pin Type
Power
Supply Notes
19
1066A–HIREL–07/11
e2v semiconductors SAS 2011
P4080
SDHC_CMD Command/Response AG23 I/O OVDD –
SDHC_DAT0 Data AP24 I/O OVDD –
SDHC_DAT1 Data AT24 I/O OVDD –
SDHC_DAT2 Data AM23 I/O OVDD –
SDHC_DAT3 Data AG22 I/O OVDD –
SDHC_DAT4/SPI_CS0 Data AN29 I/O CVDD (27)(37)
SDHC_DAT5/SPI_CS1 Data AJ28 I/O CVDD (27)(37)
SDHC_DAT6/SPI_CS2 Data AR29 I/O CVDD (27)(37)
SDHC_DAT7/SPI_CS3 Data AM29 I/O CVDD (27)(37)
SDHC_CLK Host to Card Clock AL23 O OVDD –
SDHC_CD/IIC3_SCL/GPIO16 Card Detection AK13 I OVDD (27)(28)
SDHC_WP/IIC3_SDA/GPIO17 Card Write Protection AM14 I OVDD (27)(28)
eSPI
SPI_MOSI Master Out Slave In AT29 I/O CVDD –
SPI_MISO Master In Slave Out AH28 I CVDD –
SPI_CLK eSPI clock AK29 O CVDD –
SPI_CS0/SDHC_DAT4 eSPI chip select AN29 O CVDD (27)
SPI_CS1/SDHC_DAT5 eSPI chip select AJ28 O CVDD (27)
SPI_CS2/SDHC_DAT6 eSPI chip select AR29 O CVDD (27)
SPI_CS3/SDHC_DAT7 eSPI chip select AM29 O CVDD (27)
IEEE 1588
TSEC_1588_CLK_IN Clock In AL35 I LVDD –
TSEC_1588_TRIG_IN1 Trigger In 1 AL36 I LVDD –
TSEC_1588_TRIG_IN2 Trigger In 2 AK36 I LVDD –
TSEC_1588_ALARM_OUT1 Alarm Out 1 AJ36 O LVDD –
TSEC_1588_ALARM_OUT2/GPIO30 Alarm Out 2 AK35 O LVDD (27)
TSEC_1588_CLK_OUT Clock Out AM30 O LVDD –
TSEC_1588_PULSE_OUT1 Pulse Out1 AL30 O LVDD –
TSEC_1588_PULSE_OUT2/GPIO31 Pulse Out2 AJ34 O LVDD (27)
Ethernet MII Management Interface 1
EMI1_MDC Management Data Clock AJ33 O LVDD –
EMI1_MDIO Management Data In/Out AL32 I/O LVDD –
Ethernet MII Management Interface 2
EMI2_MDC Management Data Clock AK30 O 1.2V
(1)(18)(22
)
EMI2_MDIO Management Data In/Out AJ30 I/O 1.2V
(2)
(18)(22)
Ethernet Reference Clock
Table 1-1. P4080 Pins List by Bus (Continued)
Signal Signal Description
Package Pin
Number Pin Type
Power
Supply Notes
20
1066A–HIREL–07/11
P4080
e2v semiconductors SAS 2011
EC_GTX_CLK125 Reference Clock AK34 I LVDD (28)
Ethernet External Timestamping
EC_XTRNL_TX_STMP1 External Timestamp Transmit 1 AM31 I LVDD –
EC_XTRNL_RX_STMP1 External Timestamp Receive 1 AK32 I LVDD –
EC_XTRNL_TX_STMP2 External Timestamp Transmit 2 AJ31 I LVDD –
EC_XTRNL_RX_STMP2 External Timestamp Receive 2 AK31 I LVDD –
Three-Speed Ethernet Controller 1
EC1_TXD3/USB1_D7 Transmit Data AP36 O LVDD (27)(35)
EC1_TXD2/USB1_D6 Transmit Data AT34 O LVDD (27)(35)
EC1_TXD1/USB1_D5 Transmit Data AR34 O LVDD (27)(35)
EC1_TXD0/USB1_D4 Transmit Data AT35 O LVDD (27)(35)
EC1_TX_EN/USB1_STP Transmit Enable AR36 O LVDD (15)
EC1_GTX_CLK/USB1_CLK Transmit Clock Out AP35 O LVDD (27)
EC1_RXD3/USB1_D3 Receive Data AM33 I LVDD (27)(28)
EC1_RXD2/USB1_D2 Receive Data AN34 I LVDD (27)(28)
EC1_RXD1/USB1_D1 Receive Data AN35 I LVDD (27)(28)
EC1_RXD0/USB1_D0 Receive Data AN36 I LVDD (27)(28)
EC1_RX_DV/USB1_NXT Receive Data Valid AM34 I LVDD (28)
EC1_RX_CLK/USB1_DIR Receive Clock AM36 I LVDD (28)
Three-Speed Ethernet Controller 2
EC2_TXD3/USB2_D7 Transmit Data AT31 O LVDD (27)(35)
EC2_TXD2/USB2_D6 Transmit Data AP30 O LVDD (27)(35)
EC2_TXD1/USB2_D5 Transmit Data AR30 O LVDD (27)(35)
EC2_TXD0/USB2_D4 Transmit Data AT30 O LVDD (27)(35)
EC2_TX_EN/USB2_STP Transmit Enable AR31 O LVDD (15)
EC2_GTX_CLK/USB2_CLK Transmit Clock Out AN31 O LVDD (27)
EC2_RXD3/USB2_D3 Receive Data AP33 I LVDD (27)(28)
EC2_RXD2/USB2_D2 Receive Data AN32 I LVDD (27)(28)
EC2_RXD1/USB2_D1 Receive Data AP32 I LVDD (27)(28)
EC2_RXD0/USB2_D0 Receive Data AT32 I LVDD (27)(28)
EC2_RX_DV/USB2_NXT Receive Data Valid AR33 I LVDD (28)
EC2_RX_CLK/USB2_DIR Receive Clock AT33 I LVDD (28)
DUART
UART1_SOUT/GPIO8 Transmit Data AL22 O OVDD (27)
UART2_SOUT/GPIO9 Transmit Data AJ22 O OVDD (27)
UART1_SIN/GPIO10 Receive Data AR23 I OVDD (27)
UART2_SIN/GPIO11 Receive Data AN23 I OVDD (27)
Table 1-1. P4080 Pins List by Bus (Continued)
Signal Signal Description
Package Pin
Number Pin Type
Power
Supply Notes
21
1066A–HIREL–07/11
e2v semiconductors SAS 2011
P4080
UART1_RTS/UART3_SOUT/GPIO12 Ready to Send AM22 O OVDD (27)
UART2_RTS/UART4_SOUT/GPIO13 Ready to Send AK23 O OVDD (27)
UART1_CTS/UART3_SIN/GPIO14 Clear to Send AP22 I OVDD (27)
UART2_CTS/UART4_SIN/GPIO15 Clear to Send AH23 I OVDD (27)
I2C Interface
IIC1_SCL Serial Clock AH15 I/O OVDD (2)(14)
IIC1_SDA Serial Data AN14 I/O OVDD (2)(14)
IIC2_SCL Serial Clock AM15 I/O OVDD (2)(14)
IIC2_SDA Serial Data AL14 I/O OVDD (2)(14)
IIC3_SCL/GPIO16/SDHC_CD Serial Clock AK13 I/O OVDD (2)(14)
IIC3_SDA/GPIO17/SDHC_WP Serial Data AM14 I/O OVDD (2)(14)
IIC4_SCL/EVT5 Serial Clock AG14 I/O OVDD (2)(14)
IIC4_SDA/EVT6 Serial Data AL15 I/O OVDD (2)(14)
SerDes (x18) PCIe, sRIO, Aurora, 10GE, 1GE
SD_TX17 Transmit Data (positive) AG31 O XVDD –
SD_TX16 Transmit Data (positive) AE31 O XVDD –
SD_TX15 Transmit Data (positive) AB33 O XVDD –
SD_TX14 Transmit Data (positive) AA31 O XVDD –
SD_TX13 Transmit Data (positive) Y29 O XVDD –
SD_TX12 Transmit Data (positive) W31 O XVDD –
SD_TX11 Transmit Data (positive) T30 O XVDD –
SD_TX10 Transmit Data (positive) P31 O XVDD –
SD_TX09 Transmit Data (positive) N33 O XVDD –
SD_TX08 Transmit Data (positive) M31 O XVDD –
SD_TX07 Transmit Data (positive) K31 O XVDD –
SD_TX06 Transmit Data (positive) J33 O XVDD –
SD_TX05 Transmit Data (positive) G33 O XVDD –
SD_TX08 Transmit Data (positive) M31 O XVDD –
SD_TX04 Transmit Data (positive) D34 O XVDD –
SD_TX03 Transmit Data (positive) F31 O XVDD –
SD_TX02 Transmit Data (positive) H30 O XVDD –
SD_TX01 Transmit Data (positive) F29 O XVDD –
SD_TX00 Transmit Data (positive) H28 O XVDD –
SD_TX17 Transmit Data (negative) AG32 O XVDD –
SD_TX16 Transmit Data (negative) AE32 O XVDD –
SD_TX15 Transmit Data (negative) AB34 O XVDD –
SD_TX14 Transmit Data (negative) AA32 O XVDD –
Table 1-1. P4080 Pins List by Bus (Continued)
Signal Signal Description
Package Pin
Number Pin Type
Power
Supply Notes
22
1066A–HIREL–07/11
P4080
e2v semiconductors SAS 2011
SD_TX13 Transmit Data (negative) Y30 O XVDD –
SD_TX12 Transmit Data (negative) W32 O XVDD –
SD_TX11 Transmit Data (negative) T31 O XVDD –
SD_TX10 Transmit Data (negative) P32 O XVDD –
SD_TX09 Transmit Data (negative) N34 O XVDD –
SD_TX08 Transmit Data (negative) M32 O XVDD –
SD_TX07 Transmit Data (negative) K32 O XVDD –
SD_TX06 Transmit Data (negative) J34 O XVDD –
SD_TX05 Transmit Data (negative) F33 O XVDD –
SD_TX04 Transmit Data (negative) E34 O XVDD –
SD_TX03 Transmit Data (negative) E31 O XVDD –
SD_TX02 Transmit Data (negative) G30 O XVDD –
SD_TX01 Transmit Data (negative) E29 O XVDD –
SD_TX00 Transmit Data (negative) G28 O XVDD –
SD_RX17 Receive Data (positive) AG36 I XVDD –
SD_RX16 Receive Data (positive) AF34 I XVDD –
SD_RX15 Receive Data (positive) AC36 I XVDD –
SD_RX14 Receive Data (positive) AA36 I XVDD –
SD_RX13 Receive Data (positive) Y34 I XVDD –
SD_RX12 Receive Data (positive) W36 I XVDD –
SD_RX11 Receive Data (positive) T34 I XVDD –
SD_RX10 Receive Data (positive) P36 I XVDD –
SD_RX09 Receive Data (positive) M36 I XVDD –
SD_RX08 Receive Data (positive) L34 I XVDD –
SD_RX07 Receive Data (positive) K36 I XVDD –
SD_RX06 Receive Data (positive) H36 I XVDD –
SD_RX05 Receive Data (positive) F36 I XVDD –
SD_RX04 Receive Data (positive) D36 I XVDD –
SD_RX03 Receive Data (positive) A31 I XVDD –
SD_RX02 Receive Data (positive) C30 I XVDD –
SD_RX01 Receive Data (positive) A29 I XVDD –
SD_RX00 Receive Data (positive) C28 I XVDD –
SD_RX17 Receive Data (negative) AG35 I XVDD –
SD_RX16 Receive Data (negative) AF33 I XVDD –
SD_RX15 Receive Data (negative) AC35 I XVDD –
SD_RX14 Receive Data (negative) AA35 I XVDD –
SD_RX13 Receive Data (negative) Y33 I XVDD –
Table 1-1. P4080 Pins List by Bus (Continued)
Signal Signal Description
Package Pin
Number Pin Type
Power
Supply Notes
23
1066A–HIREL–07/11
e2v semiconductors SAS 2011
P4080
SD_RX12 Receive Data (negative) W35 I XVDD –
SD_RX11 Receive Data (negative) T33 I XVDD –
SD_RX10 Receive Data (negative) P35 I XVDD –
SD_RX09 Receive Data (negative) M35 I XVDD –
SD_RX08 Receive Data (negative) L33 I XVDD –
SD_RX07 Receive Data (negative) K35 I XVDD –
SD_RX06 Receive Data (negative) H35 I XVDD –
SD_RX05 Receive Data (negative) F35 I XVDD –
SD_RX04 Receive Data (negative) C36 I XVDD –
SD_RX03 Receive Data (negative) B31 I XVDD –
SD_RX02 Receive Data (negative) D30 I XVDD –
SD_RX01 Receive Data (negative) B29 I XVDD –
SD_RX00 Receive Data (negative) D28 I XVDD –
SD_REF_CLK1 SerDes Bank 1 PLL Reference Clock A35 I XVDD –
SD_REF_CLK1 SerDes Bank 1 PLL Reference Clock
Complement B35 I XVDD –
SD_REF_CLK2 SerDes Bank 2 Reference Clock V34 I XVDD –
SD_REF_CLK2 SerDes Bank 2 Reference Clock Complement V33 I XVDD –
SD_REF_CLK3 SerDes Bank 2 and 3 PLL Reference Clock AC32 I XVDD (36)
SD_REF_CLK3 SerDes Bank 2 and 3 PLL Reference Clock
Complement AC31 I XVDD (36)
General-Purpose Input/Output
GPIO00 General Purpose Input / Output AL21 I/O OVDD –
GPIO01 General Purpose Input / Output AK22 I/O OVDD –
GPIO02 General Purpose Input / Output AM20 I/O OVDD –
GPIO03 General Purpose Input / Output AN20 I/O OVDD –
GPIO04 General Purpose Input / Output AH21 I/O OVDD –
GPIO05 General Purpose Input / Output AJ21 I/O OVDD –
GPIO06 General Purpose Input / Output AK21 I/O OVDD –
GPIO07 General Purpose Input / Output AG20 I/O OVDD –
GPIO08/UART1_SOUT General Purpose Input / Output AL22 I/O OVDD –
GPIO09/UART2_SOUT General Purpose Input / Output AJ22 I/O OVDD –
GPIO10/UART1_SIN General Purpose Input / Output AR23 I/O OVDD –
GPIO11/UART2_SIN General Purpose Input / Output AN23 I/O OVDD –
GPIO12/UART1_RTS/UART3_SOUT General Purpose Input / Output AM22 I/O OVDD –
GPIO13/UART2_RTS/UART4_SOUT General Purpose Input / Output AK23 I/O OVDD –
GPIO14/UART1_CTS/UART3_SIN General Purpose Input / Output AP22 I/O OVDD –
GPIO15/UART2_CTS/UART4_SIN General Purpose Input / Output AH23 I/O OVDD –
Table 1-1. P4080 Pins List by Bus (Continued)
Signal Signal Description
Package Pin
Number Pin Type
Power
Supply Notes
24
1066A–HIREL–07/11
P4080
e2v semiconductors SAS 2011
GPIO16/IIC3_SCL/SDHC_CD General Purpose Input / Output AK13 I/O OVDD –
GPIO17/IIC3_SDA/SDHC_WP General Purpose Input / Output AM14 I/O OVDD –
GPIO18/DMA1_DREQ0 General Purpose Input / Output AP21 I/O OVDD –
GPIO19/DMA1_DACK0 General Purpose Input / Output AL19 I/O OVDD –
GPIO20/DMA2_DREQ0/ALT_MDVAL General Purpose Input / Output AJ20 I/O OVDD –
GPIO21/IRQ3 General Purpose Input / Output AJ15 I/O OVDD –
GPIO22/IRQ4 General Purpose Input / Output AH17 I/O OVDD –
GPIO23/IRQ5 General Purpose Input / Output AJ13 I/O OVDD –
GPIO24/IRQ6 General Purpose Input / Output AG17 I/O OVDD –
GPIO25/IRQ7 General Purpose Input / Output AM13 I/O OVDD –
GPIO26/IRQ8 General Purpose Input / Output AG13 I/O OVDD –
GPIO27/IRQ9 General Purpose Input / Output AK11 I/O OVDD –
GPIO28/IRQ10 General Purpose Input / Output AH14 I/O OVDD –
GPIO29/IRQ11 General Purpose Input / Output AL12 I/O OVDD –
GPIO30/TSEC_1588_ALARM_OUT2 General Purpose Input / Output AK35 I/O LVDD (25)
GPIO31/TSEC_1588_PULSE_OUT2 General Purpose Input / Output AJ34 I/O LVDD (25)
System Control
PORESET Power On Reset AP17 I OVDD –
HRESET Hard Reset AR17 I/O OVDD (1)(2)
RESET_REQ Reset Request AT16 O OVDD (35)
CKSTP_OUT Checkstop Out AM19 O OVDD (1)(2)
Debug
EVT0 Event 0 AJ17 I/O OVDD (20)
EVT1 Event 1 AK17 I/O OVDD –
EVT2 Event 2 AN16 I/O OVDD –
EVT3 Event 3 AK16 I/O OVDD –
EVT4 Event 4 AM16 I/O OVDD –
EVT5/IIC4_SCL Event 5 AG14 I/O OVDD –
EVT6/IIC4_SDA Event 6 AL15 I/O OVDD –
EVT7/DMA2_DACK0/ALT_MSRCID0 Event 7 AG19 I/O OVDD –
EVT8/DMA2_DDONE0/ALT_MSRCID1 Event 8 AP20 I/O OVDD –
EVT9/IRQ_OUT Event 9 AK14 I/O OVDD –
MDVAL Debug Data Valid AR15 O OVDD –
MSRCID0 Debug Source ID 0 AH20 O OVDD (4)(20)
MSRCID1 Debug Source ID 1 AJ19 O OVDD (35)
MSRCID2 Debug Source ID 2 AH18 O OVDD (35)
ALT_MDVAL/DMA2_DREQ0/GPIO20 Alternate Debug Data Valid AJ20 O OVDD (27)
Table 1-1. P4080 Pins List by Bus (Continued)
Signal Signal Description
Package Pin
Number Pin Type
Power
Supply Notes
25
1066A–HIREL–07/11
e2v semiconductors SAS 2011
P4080
ALT_MSRCID0/DMA2_DACK0/EVT7 Alternate Debug Source ID 0 AG19 O OVDD (27)
ALT_MSRCID1/DMA2_DDONE0/EVT8 Alternate Debug Source ID 1 AP20 O OVDD (27)
CLK_OUT Clock Out AK20 O OVDD (6)
Clock
RTC Real Time Clock AN24 I OVDD –
SYSCLK System Clock AT23 I OVDD –
JTAG
TCK Test Clock AR22 I OVDD –
TDI Test Data In AN17 I OVDD (7)
TDO Test Data Out AP15 O OVDD (6)
TMS Test Mode Select AR20 I OVDD (7)
TRST Test Reset AR19 I OVDD (7)
DFT
SCAN_MODE Scan Mode AL17 I OVDD (12)
TEST_SEL Test Mode Select AT21 I OVDD (12)(38)
Power Management
ASLEEP Asleep AR21 O OVDD (35)
Input / Output Voltage Select
IO_VSEL0 I/O Voltage Select AL18 I OVDD (30)
IO_VSEL1 I/O Voltage Select AP18 I OVDD (30)
IO_VSEL2 I/O Voltage Select AK18 I OVDD (30)
IO_VSEL3 I/O Voltage Select AM18 I OVDD (30)
IO_VSEL4 I/O Voltage Select AH19 I OVDD (30)
Power and Ground Signals
GND Ground C3 – – –
GND Ground B5 – – –
GND Ground F3 – – –
GND Ground E5 – – –
GND Ground D7 – – –
GND Ground C9 – – –
GND Ground B11 – – –
GND Ground J3 – – –
GND Ground H5 – – –
GND Ground G7 – – –
GND Ground F9 – – –
GND Ground E11 – – –
GND Ground D13 – – –
Table 1-1. P4080 Pins List by Bus (Continued)
Signal Signal Description
Package Pin
Number Pin Type
Power
Supply Notes
26
1066A–HIREL–07/11
P4080
e2v semiconductors SAS 2011
GND Ground C15 – – –
GND Ground K19 – – –
GND Ground B20 – – –
GND Ground B22 – – –
GND Ground E19 – – –
GND Ground L22 – – –
GND Ground J23 – – –
GND Ground A22 – – –
GND Ground L20 – – –
GND Ground A26 – – –
GND Ground A18 – – –
GND Ground E17 – – –
GND Ground F23 – – –
GND Ground J27 – – –
GND Ground F27 – – –
GND Ground G21 – – –
GND Ground K25 – – –
GND Ground B18 – – –
GND Ground L18 – – –
GND Ground J21 – – –
GND Ground M27 – – –
GND Ground G13 – – –
GND Ground F15 – – –
GND Ground H11 – – –
GND Ground J9 – – –
GND Ground K7 – – –
GND Ground L5 – – –
GND Ground M3 – – –
GND Ground R3 – – –
GND Ground P5 – – –
GND Ground N7 – – –
GND Ground M9 – – –
GND Ground V25 – – –
GND Ground R9 – – –
GND Ground T7 – – –
GND Ground U5 – – –
GND Ground U3 – – –
Table 1-1. P4080 Pins List by Bus (Continued)
Signal Signal Description
Package Pin
Number Pin Type
Power
Supply Notes
27
1066A–HIREL–07/11
e2v semiconductors SAS 2011
P4080
GND Ground Y3 – – –
GND Ground Y5 – – –
GND Ground W7 – – –
GND Ground V10 – – –
GND Ground AA9 – – –
GND Ground AB7 – – –
GND Ground AC5 – – –
GND Ground AD3 – – –
GND Ground AD9 – – –
GND Ground AE7 – – –
GND Ground AF5 – – –
GND Ground AG3 – – –
GND Ground AG9 – – –
GND Ground AH7 – – –
GND Ground AJ5 – – –
GND Ground AK3 – – –
GND Ground AN3 – – –
GND Ground AM5 – – –
GND Ground AL7 – – –
GND Ground AK9 – – –
GND Ground AJ11 – – –
GND Ground AH13 – – –
GND Ground AR5 – – –
GND Ground AP7 – – –
GND Ground AN9 – – –
GND Ground AM11 – – –
GND Ground AL13 – – –
GND Ground AK15 – – –
GND Ground AG18 – – –
GND Ground AR11 – – –
GND Ground AP13 – – –
GND Ground AN15 – – –
GND Ground AM17 – – –
GND Ground AK19 – – –
GND Ground AF13 – – –
GND Ground AR18 – – –
GND Ground AB27 – – –
Table 1-1. P4080 Pins List by Bus (Continued)
Signal Signal Description
Package Pin
Number Pin Type
Power
Supply Notes
28
1066A–HIREL–07/11
P4080
e2v semiconductors SAS 2011
GND Ground AP19 – – –
GND Ground AH22 – – –
GND Ground AM21 – – –
GND Ground AL29 – – –
GND Ground AR16 – – –
GND Ground AT22 – – –
GND Ground AP23 – – –
GND Ground AR32 – – –
GND Ground AK28 – – –
GND Ground AE27 – – –
GND Ground L16 – – –
GND Ground AP34 – – –
GND Ground AJ32 – – –
GND Ground AN30 – – –
GND Ground AH34 – – –
GND Ground AT36 – – –
GND Ground AL34 – – –
GND Ground AM32 – – –
GND Ground AE26 – – –
GND Ground AC26 – – –
GND Ground AA26 – – –
GND Ground W26 – – –
GND Ground U26 – – –
GND Ground R26 – – –
GND Ground N26 – – –
GND Ground M11 – – –
GND Ground P11 – – –
GND Ground T11 – – –
GND Ground V11 – – –
GND Ground Y11 – – –
GND Ground AB11 – – –
GND Ground AD11 – – –
GND Ground AE12 – – –
GND Ground AC12 – – –
GND Ground AA12 – – –
GND Ground W12 – – –
GND Ground U12 – – –
Table 1-1. P4080 Pins List by Bus (Continued)
Signal Signal Description
Package Pin
Number Pin Type
Power
Supply Notes
29
1066A–HIREL–07/11
e2v semiconductors SAS 2011
P4080
GND Ground R12 – – –
GND Ground N12 – – –
GND Ground M13 – – –
GND Ground P13 – – –
GND Ground T13 – – –
GND Ground V13 – – –
GND Ground Y13 – – –
GND Ground AB13 – – –
GND Ground AD13 – – –
GND Ground AE14 – – –
GND Ground AC14 – – –
GND Ground AA14 – – –
GND Ground W14 – – –
GND Ground U14 – – –
GND Ground R14 – – –
GND Ground N14 – – –
GND Ground L14 – – –
GND Ground M15 – – –
GND Ground P15 – – –
GND Ground T15 – – –
GND Ground V15 – – –
GND Ground Y15 – – –
GND Ground AB15 – – –
GND Ground AD15 – – –
GND Ground AF15 – – –
GND Ground W16 – – –
GND Ground AC16 – – –
GND Ground AA16 – – –
GND Ground AE16 – – –
GND Ground U16 – – –
GND Ground R16 – – –
GND Ground N16 – – –
GND Ground M17 – – –
GND Ground P17 – – –
GND Ground T17 – – –
GND Ground N18 – – –
GND Ground R18 – – –
Table 1-1. P4080 Pins List by Bus (Continued)
Signal Signal Description
Package Pin
Number Pin Type
Power
Supply Notes
30
1066A–HIREL–07/11
P4080
e2v semiconductors SAS 2011
GND Ground U18 – – –
GND Ground Y17 – – –
GND Ground AB17 – – –
GND Ground AD17 – – –
GND Ground AF17 – – –
GND Ground W18 – – –
GND Ground AC18 – – –
GND Ground AA18 – – –
GND Ground AE18 – – –
GND Ground AF19 – – –
GND Ground AD19 – – –
GND Ground AB19 – – –
GND Ground Y19 – – –
GND Ground V19 – – –
GND Ground T19 – – –
GND Ground P19 – – –
GND Ground M19 – – –
GND Ground N20 – – –
GND Ground R20 – – –
GND Ground U20 – – –
GND Ground AE20 – – –
GND Ground AA20 – – –
GND Ground AC20 – – –
GND Ground W20 – – –
GND Ground AF21 – – –
GND Ground AD21 – – –
GND Ground AB21 – – –
GND Ground Y21 – – –
GND Ground V21 – – –
GND Ground T21 – – –
GND Ground P21 – – –
GND Ground M21 – – –
GND Ground AE22 – – –
GND Ground AC22 – – –
GND Ground AA22 – – –
GND Ground W22 – – –
GND Ground U22 – – –
Table 1-1. P4080 Pins List by Bus (Continued)
Signal Signal Description
Package Pin
Number Pin Type
Power
Supply Notes
31
1066A–HIREL–07/11
e2v semiconductors SAS 2011
P4080
GND Ground R22 – – –
GND Ground N22 – – –
GND Ground AF23 – – –
GND Ground AD23 – – –
GND Ground AB23 – – –
GND Ground Y23 – – –
GND Ground V23 – – –
GND Ground T23 – – –
GND Ground P23 – – –
GND Ground M23 – – –
GND Ground L24 – – –
GND Ground N24 – – –
GND Ground R24 – – –
GND Ground U24 – – –
GND Ground W24 – – –
GND Ground AA24 – – –
GND Ground AC24 – – –
GND Ground AE24 – – –
GND Ground AF25 – – –
GND Ground AD25 – – –
GND Ground AB25 – – –
GND Ground Y25 – – –
GND Ground P27 – – –
GND Ground V17 – – –
GND Ground T25 – – –
GND Ground P25 – – –
GND Ground M25 – – –
GND Ground T27 – – –
GND Ground V27 – – –
GND Ground Y27 – – –
GND Ground AD27 – – –
GND Ground L12 – – –
XGND SerDes Transceiver GND AA30 – – –
XGND SerDes Transceiver GND AB32 – – –
XGND SerDes Transceiver GND AC30 – – –
XGND SerDes Transceiver GND AC34 – – –
XGND SerDes Transceiver GND AD30 – – –
Table 1-1. P4080 Pins List by Bus (Continued)
Signal Signal Description
Package Pin
Number Pin Type
Power
Supply Notes
32
1066A–HIREL–07/11
P4080
e2v semiconductors SAS 2011
XGND SerDes Transceiver GND AD31 – – –
XGND SerDes Transceiver GND AF32 – – –
XGND SerDes Transceiver GND AG30 – – –
XGND SerDes Transceiver GND D33 – – –
XGND SerDes Transceiver GND E28 – – –
XGND SerDes Transceiver GND E30 – – –
XGND SerDes Transceiver GND F32 – – –
XGND SerDes Transceiver GND G29 – – –
XGND SerDes Transceiver GND G31 – – –
XGND SerDes Transceiver GND H29 – – –
XGND SerDes Transceiver GND H32 – – –
XGND SerDes Transceiver GND H34 – – –
XGND SerDes Transceiver GND J29 – – –
XGND SerDes Transceiver GND J31 – – –
XGND SerDes Transceiver GND K28 – – –
XGND SerDes Transceiver GND K29 – – –
XGND SerDes Transceiver GND L29 – – –
XGND SerDes Transceiver GND L32 – – –
XGND SerDes Transceiver GND M30 – – –
XGND SerDes Transceiver GND N29 – – –
XGND SerDes Transceiver GND N30 – – –
XGND SerDes Transceiver GND N32 – – –
XGND SerDes Transceiver GND P29 – – –
XGND SerDes Transceiver GND P34 – – –
XGND SerDes Transceiver GND R30 – – –
XGND SerDes Transceiver GND R32 – – –
XGND SerDes Transceiver GND U29 – – –
XGND SerDes Transceiver GND U31 – – –
XGND SerDes Transceiver GND V29 – – –
XGND SerDes Transceiver GND V31 – – –
XGND SerDes Transceiver GND W30 – – –
XGND SerDes Transceiver GND Y32 – – –
XGND SerDes Transceiver GND AH31 – – –
SGND SerDes Core Logic GND A28 – – –
SGND SerDes Core Logic GND A32 – – –
SGND SerDes Core Logic GND A36 – – –
SGND SerDes Core Logic GND AA34 – – –
Table 1-1. P4080 Pins List by Bus (Continued)
Signal Signal Description
Package Pin
Number Pin Type
Power
Supply Notes
33
1066A–HIREL–07/11
e2v semiconductors SAS 2011
P4080
SGND SerDes Core Logic GND AB36 – – –
SGND SerDes Core Logic GND AD35 – – –
SGND SerDes Core Logic GND AE34 – – –
SGND SerDes Core Logic GND AF36 – – –
SGND SerDes Core Logic GND AG33 – – –
SGND SerDes Core Logic GND B30 – – –
SGND SerDes Core Logic GND B34 – – –
SGND SerDes Core Logic GND C29 – – –
SGND SerDes Core Logic GND C33 – – –
SGND SerDes Core Logic GND D31 – – –
SGND SerDes Core Logic GND D35 – – –
SGND SerDes Core Logic GND E35 – – –
SGND SerDes Core Logic GND G34 – – –
SGND SerDes Core Logic GND G36 – – –
SGND SerDes Core Logic GND J35 – – –
SGND SerDes Core Logic GND K33 – – –
SGND SerDes Core Logic GND L36 – – –
SGND SerDes Core Logic GND M34 – – –
SGND SerDes Core Logic GND N35 – – –
SGND SerDes Core Logic GND R33 – – –
SGND SerDes Core Logic GND R36 – – –
SGND SerDes Core Logic GND T35 – – –
SGND SerDes Core Logic GND U34 – – –
SGND SerDes Core Logic GND V36 – – –
SGND SerDes Core Logic GND W33 – – –
SGND SerDes Core Logic GND Y35 – – –
SGND SerDes Core Logic GND AH35 – – –
SGND SerDes Core Logic GND AH33 – – –
AGND_SRDS1 SerDes PLL1 GND B33 – – –
AGND_SRDS2 SerDes PLL2 GND T36 – – –
AGND_SRDS3 SerDes PLL3 GND AE36 – – –
SENSEGND_PL1 Platform GND Sense 1 AF12 – – (8)
SENSEGND_PL2 Platform GND Sense 2 K27 – – (8)
SENSEGND_CA Core Group A GND Sense K17 – – (8)
SENSEGND_CB Core Group B GND Sense AG16 – – (8)
OVDD General I/O Supply AN22 – OVDD –
OVDD General I/O Supply AJ14 – OVDD –
Table 1-1. P4080 Pins List by Bus (Continued)
Signal Signal Description
Package Pin
Number Pin Type
Power
Supply Notes
34
1066A–HIREL–07/11
P4080
e2v semiconductors SAS 2011
OVDD General I/O Supply AJ18 – OVDD –
OVDD General I/O Supply AL16 – OVDD –
OVDD General I/O Supply AJ12 – OVDD –
OVDD General I/O Supply AN18 – OVDD –
OVDD General I/O Supply AG21 – OVDD –
OVDD General I/O Supply AL20 – OVDD –
OVDD General I/O Supply AT15 – OVDD –
OVDD General I/O Supply AJ23 – OVDD –
OVDD General I/O Supply AP16 – OVDD –
OVDD General I/O Supply AR24 – OVDD –
CVDD eSPI Supply AJ29 – CVDD –
CVDD eSPI Supply AP29 – CVDD –
GVDD DDR Supply B2 – GVDD –
GVDD DDR Supply B8 – GVDD –
GVDD DDR Supply B14 – GVDD –
GVDD DDR Supply C18 – GVDD –
GVDD DDR Supply C12 – GVDD –
GVDD DDR Supply C6 – GVDD –
GVDD DDR Supply D4 – GVDD –
CVDD DDR Supply D10 – GVDD –
GVDD DDR Supply D16 – GVDD –
GVDD DDR Supply E14 – GVDD –
GVDD DDR Supply E8 – GVDD –
CVDD DDR Supply E2 – GVDD –
GVDD DDR Supply F6 – GVDD –
GVDD DDR Supply F12 – GVDD –
GVDD DDR Supply AR8 – GVDD –
CVDD DDR Supply G4 – GVDD –
GVDD DDR Supply G10 – GVDD –
GVDD DDR Supply G16 – GVDD –
GVDD DDR Supply H14 – GVDD –
CVDD DDR Supply H8 – GVDD –
GVDD DDR Supply H2 – GVDD –
GVDD DDR Supply J6 – GVDD –
GVDD DDR Supply K10 – GVDD –
CVDD DDR Supply K4 – GVDD –
GVDD DDR Supply L2 – GVDD –
Table 1-1. P4080 Pins List by Bus (Continued)
Signal Signal Description
Package Pin
Number Pin Type
Power
Supply Notes
35
1066A–HIREL–07/11
e2v semiconductors SAS 2011
P4080
GVDD DDR Supply L8 – GVDD –
GVDD DDR Supply M6 – GVDD –
CVDD DDR Supply N4 – GVDD –
GVDD DDR Supply N10 – GVDD –
GVDD DDR Supply P8 – GVDD –
GVDD DDR Supply P2 – GVDD –
CVDD DDR Supply R6 – GVDD –
GVDD DDR Supply T10 – GVDD –
GVDD DDR Supply T4 – GVDD –
GVDD DDR Supply J12 – GVDD –
CVDD DDR Supply U2 – GVDD –
GVDD DDR Supply U8 – GVDD –
GVDD DDR Supply V7 – GVDD –
GVDD DDR Supply AK10 – GVDD –
CVDD DDR Supply W10 – GVDD –
GVDD DDR Supply AA6 – GVDD –
GVDD DDR Supply AR2 – GVDD –
GVDD DDR Supply Y2 – GVDD –
CVDD DDR Supply Y8 – GVDD –
GVDD DDR Supply AC2 – GVDD –
GVDD DDR Supply AD6 – GVDD –
GVDD DDR Supply AE10 – GVDD –
CVDD DDR Supply AE4 – GVDD –
GVDD DDR Supply AF2 – GVDD –
GVDD DDR Supply AF8 – GVDD –
GVDD DDR Supply AB4 – GVDD –
CVDD DDR Supply AB10 – GVDD –
GVDD DDR Supply AC8 – GVDD –
GVDD DDR Supply AG6 – GVDD –
GVDD DDR Supply AH10 – GVDD –
CVDD DDR Supply AH4 – GVDD –
GVDD DDR Supply AJ2 – GVDD –
GVDD DDR Supply AJ8 – GVDD –
GVDD DDR Supply AR14 – GVDD –
GVDD DDR Supply AK6 – GVDD –
CVDD DDR Supply AL4 – GVDD –
GVDD DDR Supply AL10 – GVDD –
Table 1-1. P4080 Pins List by Bus (Continued)
Signal Signal Description
Package Pin
Number Pin Type
Power
Supply Notes
36
1066A–HIREL–07/11
P4080
e2v semiconductors SAS 2011
GVDD DDR Supply AM2 – GVDD –
GVDD DDR Supply AM8 – GVDD –
CVDD DDR Supply AP10 – GVDD –
GVDD DDR Supply AN12 – GVDD –
GVDD DDR Supply AN6 – GVDD –
GVDD DDR Supply AP4 – GVDD –
BVDD Local Bus Supply B24 – BVDD –
BVDD Local Bus Supply K22 – BVDD –
BVDD Local Bus Supply F20 – BVDD –
BVDD Local Bus Supply F26 – BVDD –
BVDD Local Bus Supply E24 – BVDD –
BVDD Local Bus Supply E22 – BVDD –
BVDD Local Bus Supply K24 – BVDD –
BVDD Local Bus Supply H20 – BVDD –
BVDD Local Bus Supply H18 – BVDD –
SVDD SerDes Core Logic Supply A30 – SVDD –
SVDD SerDes Core Logic Supply A34 – SVDD –
SVDD SerDes Core Logic Supply AA33 – SVDD –
SVDD SerDes Core Logic Supply AB35 – SVDD –
SVDD SerDes Core Logic Supply AD36 – SVDD –
SVDD SerDes Core Logic Supply AE33 – SVDD –
SVDD SerDes Core Logic Supply AF35 – SVDD –
SVDD SerDes Core Logic Supply AG34 – SVDD –
SVDD SerDes Core Logic Supply B28 – SVDD –
SVDD SerDes Core Logic Supply B32 – SVDD –
SVDD SerDes Core Logic Supply B36 – SVDD –
SVDD SerDes Core Logic Supply C31 – SVDD –
SVDD SerDes Core Logic Supply C34 – SVDD –
SVDD SerDes Core Logic Supply C35 – SVDD –
SVDD SerDes Core Logic Supply D29 – SVDD –
SVDD SerDes Core Logic Supply E36 – SVDD –
SVDD SerDes Core Logic Supply F34 – SVDD –
SVDD SerDes Core Logic Supply G35 – SVDD –
SVDD SerDes Core Logic Supply J36 – SVDD –
SVDD SerDes Core Logic Supply K34 – SVDD –
SVDD SerDes Core Logic Supply L35 – SVDD –
SVDD SerDes Core Logic Supply M33 – SVDD –
Table 1-1. P4080 Pins List by Bus (Continued)
Signal Signal Description
Package Pin
Number Pin Type
Power
Supply Notes
37
1066A–HIREL–07/11
e2v semiconductors SAS 2011
P4080
SVDD SerDes Core Logic Supply N36 – SVDD –
SVDD SerDes Core Logic Supply R34 – SVDD –
SVDD SerDes Core Logic Supply R35 – SVDD –
SVDD SerDes Core Logic Supply U33 – SVDD –
SVDD SerDes Core Logic Supply V35 – SVDD –
SVDD SerDes Core Logic Supply W34 – SVDD –
SVDD SerDes Core Logic Supply Y36 – SVDD –
SVDD SerDes Core Logic Supply AH36 – SVDD –
XVDD SerDes Transceiver Supply AA29 – XVDD –
XVDD SerDes Transceiver Supply AB30 – XVDD –
XVDD SerDes Transceiver Supply AB31 – XVDD –
XVDD SerDes Transceiver Supply AC33 – XVDD –
XVDD SerDes Transceiver Supply AD32 – XVDD –
XVDD SerDes Transceiver Supply AE30 – XVDD –
XVDD SerDes Transceiver Supply AF31 – XVDD –
XVDD SerDes Transceiver Supply E32 – XVDD –
XVDD SerDes Transceiver Supply E33 – XVDD –
XVDD SerDes Transceiver Supply F28 – XVDD –
XVDD SerDes Transceiver Supply F30 – XVDD –
XVDD SerDes Transceiver Supply G32 – XVDD –
XVDD SerDes Transceiver Supply H31 – XVDD –
XVDD SerDes Transceiver Supply H33 – XVDD –
XVDD SerDes Transceiver Supply J28 – XVDD –
XVDD SerDes Transceiver Supply J30 – XVDD –
XVDD SerDes Transceiver Supply J32 – XVDD –
XVDD SerDes Transceiver Supply K30 – XVDD –
XVDD SerDes Transceiver Supply L30 – XVDD –
XVDD SerDes Transceiver Supply L31 – XVDD –
XVDD SerDes Transceiver Supply M29 – XVDD –
XVDD SerDes Transceiver Supply N31 – XVDD –
XVDD SerDes Transceiver Supply P30 – XVDD –
XVDD SerDes Transceiver Supply P33 – XVDD –
XVDD SerDes Transceiver Supply R29 – XVDD –
XVDD SerDes Transceiver Supply R31 – XVDD –
XVDD SerDes Transceiver Supply T29 – XVDD –
XVDD SerDes Transceiver Supply T32 – XVDD –
XVDD SerDes Transceiver Supply U30 – XVDD –
Table 1-1. P4080 Pins List by Bus (Continued)
Signal Signal Description
Package Pin
Number Pin Type
Power
Supply Notes
38
1066A–HIREL–07/11
P4080
e2v semiconductors SAS 2011
XVDD SerDes Transceiver Supply V30 – XVDD –
XVDD SerDes Transceiver Supply V32 – XVDD –
XVDD SerDes Transceiver Supply W29 – XVDD –
XVDD SerDes Transceiver Supply Y31 – XVDD –
XVDD SerDes Transceiver Supply AH32 – XVDD –
LVDD Ethernet Controller 1 and 2 Supply AK33 – LVDD –
LVDD Ethernet Controller 1 and 2 Supply AP31 – LVDD –
LVDD Ethernet Controller 1 and 2 Supply AL31 – LVDD –
LVDD Ethernet Controller 1 and 2 Supply AN33 – LVDD –
LVDD Ethernet Controller 1 and 2 Supply AJ35 – LVDD –
LVDD Ethernet Controller 1 and 2 Supply AR35 – LVDD –
LVDD Ethernet Controller 1 and 2 Supply AM35 – LVDD –
POVDD Fuse Programming Override Supply AT17 – POVDD (39)
VDD_PL Platform Supply M26 – VDD_PL –
VDD_PL Platform Supply P26 – VDD_PL –
VDD_PL Platform Supply T26 – VDD_PL –
VDD_PL Platform Supply V26 – VDD_PL –
VDD_PL Platform Supply Y26 – VDD_PL –
VDD_PL Platform Supply AB26 – VDD_PL –
VDD_PL Platform Supply AD26 – VDD_PL –
VDD_PL Platform Supply N11 – VDD_PL –
VDD_PL Platform Supply R11 – VDD_PL –
VDD_PL Platform Supply W11 – VDD_PL –
VDD_PL Platform Supply AA11 – VDD_PL –
VDD_PL Platform Supply AE11 – VDD_PL –
VDD_PL Platform Supply M12 – VDD_PL –
VDD_PL Platform Supply P12 – VDD_PL –
VDD_PL Platform Supply T12 – VDD_PL –
VDD_PL Platform Supply V12 – VDD_PL –
VDD_PL Platform Supply Y12 – VDD_PL –
VDD_PL Platform Supply AB12 – VDD_PL –
VDD_PL Platform Supply AD12 – VDD_PL –
VDD_PL Platform Supply AE13 – VDD_PL –
VDD_PL Platform Supply AE15 – VDD_PL –
VDD_PL Platform Supply V16 – VDD_PL –
VDD_PL Platform Supply AE17 – VDD_PL –
VDD_PL Platform Supply L11 – VDD_PL –
Table 1-1. P4080 Pins List by Bus (Continued)
Signal Signal Description
Package Pin
Number Pin Type
Power
Supply Notes
39
1066A–HIREL–07/11
e2v semiconductors SAS 2011
P4080
VDD_PL Platform Supply AE19 – VDD_PL –
VDD_PL Platform Supply U11 – VDD_PL –
VDD_PL Platform Supply AC11 – VDD_PL –
VDD_PL Platform Supply V20 – VDD_PL –
VDD_PL Platform Supply AE21 – VDD_PL –
VDD_PL Platform Supply V22 – VDD_PL –
VDD_PL Platform Supply U13 – VDD_PL –
VDD_PL Platform Supply R27 – VDD_PL –
VDD_PL Platform Supply U23 – VDD_PL –
VDD_PL Platform Supply W23 – VDD_PL –
VDD_PL Platform Supply AA27 – VDD_PL –
VDD_PL Platform Supply AC27 – VDD_PL –
VDD_PL Platform Supply AE23 – VDD_PL –
VDD_PL Platform Supply M24 – VDD_PL –
VDD_PL Platform Supply P24 – VDD_PL –
VDD_PL Platform Supply T24 – VDD_PL –
VDD_PL Platform Supply V24 – VDD_PL –
VDD_PL Platform Supply Y24 – VDD_PL –
VDD_PL Platform Supply AB24 – VDD_PL –
VDD_PL Platform Supply AD24 – VDD_PL –
VDD_PL Platform Supply N25 – VDD_PL –
VDD_PL Platform Supply R25 – VDD_PL –
VDD_PL Platform Supply U25 – VDD_PL –
VDD_PL Platform Supply W25 – VDD_PL –
VDD_PL Platform Supply AA25 – VDD_PL –
VDD_PL Platform Supply AC25 – VDD_PL –
VDD_PL Platform Supply N27 – VDD_PL –
VDD_PL Platform Supply U27 – VDD_PL –
VDD_PL Platform Supply W28 – VDD_PL –
VDD_PL Platform Supply AE25 – VDD_PL –
VDD_PL Platform Supply AF24 – VDD_PL –
VDD_PL Platform Supply AF22 – VDD_PL –
VDD_PL Platform Supply AF20 – VDD_PL –
VDD_PL Platform Supply AF16 – VDD_PL –
VDD_PL Platform Supply W13 – VDD_PL –
VDD_PL Platform Supply AF18 – VDD_PL –
VDD_PL Platform Supply V14 – VDD_PL –
Table 1-1. P4080 Pins List by Bus (Continued)
Signal Signal Description
Package Pin
Number Pin Type
Power
Supply Notes
40
1066A–HIREL–07/11
P4080
e2v semiconductors SAS 2011
VDD_PL Platform Supply V18 – VDD_PL –
VDD_PL Platform Supply L13 – VDD_PL –
VDD_PL Platform Supply L15 – VDD_PL –
VDD_PL Platform Supply L17 – VDD_PL –
VDD_PL Platform Supply L19 – VDD_PL –
VDD_PL Platform Supply L21 – VDD_PL –
VDD_PL Platform Supply L23 – VDD_PL –
VDD_PL Platform Supply L25 – VDD_PL –
VDD_PL Platform Supply AF14 – VDD_PL –
VDD_PL Platform Supply N23 – VDD_PL –
VDD_PL Platform Supply R23 – VDD_PL –
VDD_PL Platform Supply AA23 – VDD_PL –
VDD_PL Platform Supply AC23 – VDD_PL –
VDD_PL Platform Supply U21 – VDD_PL –
VDD_PL Platform Supply W21 – VDD_PL –
VDD_PL Platform Supply U15 – VDD_PL –
VDD_PL Platform Supply AC21 – VDD_PL –
VDD_PL Platform Supply AD22 – VDD_PL –
VDD_PL Platform Supply M22 – VDD_PL –
VDD_PL Platform Supply N13 – VDD_PL –
VDD_PL Platform Supply AC13 – VDD_PL –
VDD_PL Platform Supply P22 – VDD_PL –
VDD_PL Platform Supply T22 – VDD_PL –
VDD_PL Platform Supply Y22 – VDD_PL –
VDD_PL Platform Supply AB22 – VDD_PL –
VDD_PL Platform Supply AA13 – VDD_PL –
VDD_PL Platform Supply R13 – VDD_PL –
VDD_PL Platform Supply M14 – VDD_PL –
VDD_PL Platform Supply U17 – VDD_PL –
VDD_PL Platform Supply U19 – VDD_PL –
VDD_PL Platform Supply T14 – VDD_PL –
VDD_PL Platform Supply AD14 – VDD_PL –
VDD_PL Platform Supply AD16 – VDD_PL –
VDD_PL Platform Supply AD18 – VDD_PL –
VDD_PL Platform Supply AD20 – VDD_PL –
VDD_PL Platform Supply Y14 – VDD_PL –
VDD_CA Core/L2 Group A (0-3) Supply T20 – VDD_CA –
Table 1-1. P4080 Pins List by Bus (Continued)
Signal Signal Description
Package Pin
Number Pin Type
Power
Supply Notes
41
1066A–HIREL–07/11
e2v semiconductors SAS 2011
P4080
VDD_CA Core/L2 Group A (0-3) Supply P20 – VDD_CA –
VDD_CA Core/L2 Group A (0-3) Supply R21 – VDD_CA –
VDD_CA Core/L2 Group A (0-3) Supply R19 – VDD_CA –
VDD_CA Core/L2 Group A (0-3) Supply P14 – VDD_CA –
VDD_CA Core/L2 Group A (0-3) Supply N19 – VDD_CA –
VDD_CA Core/L2 Group A (0-3) Supply M20 – VDD_CA –
VDD_CA Core/L2 Group A (0-3) Supply N21 – VDD_CA –
VDD_CA Core/L2 Group A (0-3) Supply M16 – VDD_CA –
VDD_CA Core/L2 Group A (0-3) Supply N15 – VDD_CA –
VDD_CA Core/L2 Group A (0-3) Supply P16 – VDD_CA –
VDD_CA Core/L2 Group A (0-3) Supply T16 – VDD_CA –
VDD_CA Core/L2 Group A (0-3) Supply R17 – VDD_CA –
VDD_CA Core/L2 Group A (0-3) Supply T18 – VDD_CA –
VDD_CA Core/L2 Group A (0-3) Supply R15 – VDD_CA –
VDD_CA Core/L2 Group A (0-3) Supply N17 – VDD_CA –
VDD_CA Core/L2 Group A (0-3) Supply M18 – VDD_CA –
VDD_CA Core/L2 Group A (0-3) Supply P18 – VDD_CA –
VDD_CB Core/L2 Group B (4-7) Supply W15 – VDD_CB (29)
VDD_CB Core/L2 Group B (4-7) Supply W19 – VDD_CB (29)
VDD_CB Core/L2 Group B (4-7) Supply AA19 – VDD_CB (29)
VDD_CB Core/L2 Group B (4-7) Supply Y20 – VDD_CB (29)
VDD_CB Core/L2 Group B (4-7) Supply AB14 – VDD_CB (29)
VDD_CB Core/L2 Group B (4-7) Supply AA21 – VDD_CB (29)
VDD_CB Core/L2 Group B (4-7) Supply Y16 – VDD_CB (29)
VDD_CB Core/L2 Group B (4-7) Supply AA15 – VDD_CB (29)
VDD_CB Core/L2 Group B (4-7) Supply AC15 – VDD_CB (29)
VDD_CB Core/L2 Group B (4-7) Supply AA17 – VDD_CB (29)
VDD_CB Core/L2 Group B (4-7) Supply AC17 – VDD_CB (29)
VDD_CB Core/L2 Group B (4-7) Supply W17 – VDD_CB (29)
VDD_CB Core/L2 Group B (4-7) Supply Y18 – VDD_CB (29)
VDD_CB Core/L2 Group B (4-7) Supply AB18 – VDD_CB (29)
VDD_CB Core/L2 Group B (4-7) Supply AB16 – VDD_CB (29)
VDD_CB Core/L2 Group B (4-7) Supply AC19 – VDD_CB (29)
VDD_CB Core/L2 Group B (4-7) Supply AB20 – VDD_CB (29)
AVDD_CC1 Core Cluster PLL1 Supply A20 – – (13)
AVDD_CC2 Core Cluster PLL2 Supply A21 – – (13)
AVDD_CC3 Core Cluster PLL3 Supply AT18 – – (13)
Table 1-1. P4080 Pins List by Bus (Continued)
Signal Signal Description
Package Pin
Number Pin Type
Power
Supply Notes
42
1066A–HIREL–07/11
P4080
e2v semiconductors SAS 2011
AVDD_CC4 Core Cluster PLL4 Supply AT19 – – (13)
AVDD_PLAT Platform PLL Supply AT20 – – (13)
AVDD_DDR DDR PLL Supply A19 – – (13)
AVDD_SRDS1 SerDes PLL1 Supply A33 – – (13)
AVDD_SRDS2 SerDes PLL2 Supply U36 – – (13)
AVDD_SRDS3 SerDes PLL3 Supply AE35 – – (13)
SENSEVDD_PL1 Platform Vdd Sense AF11 – – (8)
SENSEVDD_PL2 Platform Vdd Sense L27 – – (8)
SENSEVDD_CA Core Group A Vdd Sense K16 – – (8)
SENSEVDD_CB Core Group B Vdd Sense AG15 – – (8)
Analog Signals
MVREF SSTL_1.5/1.8 Reference Voltage B19 I GVDD/2 –
SD_IMP_CAL_TX SerDes Tx Impedance Calibration AF30 I
2000
(±1%) to
XVDD
(23)
SD_IMP_CAL_RX SerDes Rx Impedance Calibration B27 I
200O
(±1%) to
SVDD
(24)
TEMP_ANODE Temperature Diode Anode C21 – internal
diode
(9)
TEMP_CATHODE Temperature Diode Cathode B21 – internal
diode
(9)
No Connection Pins
NC01 No Connection J13 – – (11)
NC02 No Connection AB28 – – (11)
NC03 No Connection E16 – – (11)
NC04 No Connection AC29 – – (11)
NC05 No Connection K14 – – (11)
NC06 No Connection C26 – – (11)
NC07 No Connection E27 – – (11)
NC08 No Connection AE29 – – (11)
NC09 No Connection AG26 – – (11)
NC10 No Connection AF26 – – (11)
NC11 No Connection AC28 – – (11)
NC12 No Connection AA28 – – (11)
NC13 No Connection J15 – – (11)
NC14 No Connection J14 – – (11)
NC15 No Connection AD29 – – (11)
NC16 No Connection J16 – – (11)
Table 1-1. P4080 Pins List by Bus (Continued)
Signal Signal Description
Package Pin
Number Pin Type
Power
Supply Notes
43
1066A–HIREL–07/11
e2v semiconductors SAS 2011
P4080
NC17 No Connection AG28 – – (11)
NC18 No Connection AE28 – – (11)
NC19 No Connection AF28 – – (11)
NC20 No Connection H27 – – (11)
NC21 No Connection H12 – – (11)
NC22 No Connection H13 – – (11)
NC23 No Connection H16 – – (11)
NC24 No Connection AH30 – – (11)
NC25 No Connection AH29 – – (11)
NC26 No Connection Y28 – – (11)
NC27 No Connection AN13 – – (11)
NC28 No Connection J11 – – (11)
NC29 No Connection AB29 – – (11)
NC30 No Connection K11 – – (11)
NC31 No Connection AD28 – – (11)
NC32 No Connection A27 – – (11)
NC33 No Connection K15 – – (11)
NC34 No Connection H15 – – (11)
NC35 No Connection K13 – – (11)
NC36 No Connection K12 – – (11)
NC37 No Connection G17 – – (11)
NC38 No Connection H17 – – (11)
NC39 No Connection C20 – – (11)
NC40 No Connection F18 – – (11)
NC41 No Connection AT14 – – (11)
NC42 No Connection C27 – – (11)
NC43 No Connection R28 – – (11)
NC44 No Connection AM12 – – (11)
NC45 No Connection AP11 – – (11)
NC46 No Connection U28 – – (11)
NC47 No Connection AG29 – – (11)
NC48 No Connection G27 – – (11)
NC49 No Connection V28 – – (11)
NC50 No Connection AG27 – – (11)
NC51 No Connection E18 – – (11)
NC52 No Connection F17 – – (11)
NC53 No Connection AF27 – – (11)
Table 1-1. P4080 Pins List by Bus (Continued)
Signal Signal Description
Package Pin
Number Pin Type
Power
Supply Notes
44
1066A–HIREL–07/11
P4080
e2v semiconductors SAS 2011
NC54 No Connection AP14 – – (11)
NC55 No Connection D26 – – (11)
NC56 No Connection C19 – – (11)
NC57 No Connection D18 – – (11)
NC58 No Connection D27 – – (11)
NC59 No Connection B26 – – (11)
NC60 No Connection AF29 – – (11)
NC61 No Connection T28 – – (11)
NC62 No Connection W27 – – (11)
Reserved Pins
Reserve01 – AN28 – – (11)
Reserve02 – AL25 – – (11)
Reserve03 – AR28 – – (11)
Reserve04 – AH25 – – (11)
Reserve05 – AJ25 – – (11)
Reserve06 – AH24 – – (11)
Reserve07 – AK26 – – (11)
Reserve08 – AM27 – – (11)
Reserve09 – AR27 – – (11)
Reserve10 – AK25 – – (11)
Reserve11 – AH27 – – (11)
Reserve12 – AR26 – – (11)
Reserve13 – AT27 – – (11)
Reserve14 – AH26 – – (11)
Reserve15 – AJ27 – – (11)
Reserve16 – AT26 – – (11)
Reserve17 – AN26 – – (11)
Reserve18 – AJ26 – – (11)
Reserve19 – AG25 – – (11)
Reserve20 – AP27 – – (11)
Reserve21 – AM25 – – (11)
Reserve22 – AP28 – – (11)
Reserve23 – AL28 – – (11)
Reserve24 – AG24 – – (11)
Reserve25 – AP26 – – (11)
Reserve26 – AJ24 – – (11)
Reserve27 – AM28 – – (11)
Table 1-1. P4080 Pins List by Bus (Continued)
Signal Signal Description
Package Pin
Number Pin Type
Power
Supply Notes
45
1066A–HIREL–07/11
e2v semiconductors SAS 2011
P4080
Notes: 1. Recommend that a weak pull-up resistor (2–10 KΩ) be placed on this pin to OVDD.
2. This pin is an open drain signal.
3. This pin is a reset configuration pin. It has a weak (~20 KΩ) internal pull-up P-FET that is enabled only when the processor
is in the reset state. This pull-up is designed such that it can be overpowered by an external 4.7-kΩ resistor. However, if the
signal is intended to be high after reset, and if there is any device on the net that might pull down the value of the net at
reset, a pull up or active driver is needed.
4. Functionally, this pin is an output, but structurally it is an I/O because it either samples configuration input during reset or
because it has other manufacturing test functions. This pin will therefore be described as an I/O for boundary scan.
Reserve28 – AR25 – – (11)
Reserve29 – AM24 – – (11)
Reserve30 – AL27 – – (11)
Reserve31 – AT28 – – (11)
Reserve32 – AT25 – – (11)
Reserve33 – AL24 – – (11)
Reserve34 – AL26 – – (11)
Reserve35 – AK24 – – (11)
Reserve36 – AN25 – – (11)
Reserve37 – AK27 – – (11)
Reserve38 – AP25 – – (11)
Reserve39 – AM26 – – (11)
Reserve40 – AN27 – – (11)
Reserve41 – AL33 – – (11)
Reserve42 – C32 – – (11)
Reserve43 – U35 – – (11)
Reserve44 – AD34 – – (11)
Reserve45 – D32 – – (11)
Reserve46 – U32 – – (11)
Reserve47 – AD33 – – (11)
Reserve48 – N28 – GND (21)
Reserve49 – AG11 – GND (21)
Reserve50 – L28 – GND (21)
Reserve51 – AG12 – GND (21)
Reserve52 – M28 – GND (21)
Reserve53 – AH12 – GND (21)
Reserve54 – P28 – GND (21)
Reserve55 – AH11 – GND (21)
Reserve56 – A25 – – (11)
1.
Table 1-1. P4080 Pins List by Bus (Continued)
Signal Signal Description
Package Pin
Number Pin Type
Power
Supply Notes
46
1066A–HIREL–07/11
P4080
e2v semiconductors SAS 2011
5. Recommend that a weak pull-up resistor (2–10 KΩ) be placed on this pin to BVDD in order to ensure no random chip select
assertion due to possible noise, etc.
6. This output is actively driven during reset rather than being three-stated during reset.
7. These JTAG pins have weak (~20 KΩ) internal pull-up P-FETs that are always enabled.
8. These pins are connected to the correspondent power and ground nets internally and may be connected as a differential
pair to be used by the voltage regulators with remote sense function.
9. These pins may be connected to a temperature diode monitoring device such as the Analog Devices, ADT7461A™. If a
temperature diode monitoring device will not be connected, these pins may be connected to test point or left as a no
connect.
10. If this pin is connected to a device that pulls down during reset, an external pull-up is required to drive this pin to a safe state
during reset.
11. Do not connect.
12. These are test signals for factory use only and must be pulled up (100Ω–1 KΩ) to OVDD for normal machine operation.
13. Independent supplies derived from board VDD_PL (core clusters, platform, DDR) or SVDD (SerDes).
14. Recommend that a pull-up resistor (1 KΩ) be placed on this pin to OVDD if I2C interface is used.
15. This pin requires an external 1 KΩ pull-down resistor to prevent PHY from seeing a valid Transmit Enable before it is actively
driven.
16. For DDR2, Dn_MDIC[0] is grounded through an 18.2Ω (full-strength mode) or 36.4Ω (half-strength mode) precision 1%
resistor and Dn_MDIC[1] is connected to GVDD through an 18.2Ω (full-strength mode) or 36.4Ω (half-strength mode)
precision 1% resistor. These pins are used for automatic calibration of the DDR2 IOs. For DDR3, Dn_MDIC[0] is grounded
through an 40Ω (half-strength mode) precision 1% resistor and Dn_MDIC[1] is connected to GVDD through an 40Ω (half-
strength mode) precision 1% resistor. These pins are used for automatic calibration of the DDR3 IOs for half-strength mode.
Full-strength mode should not be calibrated.
17. These pins should be left floating.
18. These pins should be pulled up to 1.2V through a 180Ω ± 1% resistor for EM2_MDC and a 330Ω ± 1% resistor for
EM2_MDIO.
20. Pin has a weak (~20 KΩ) internal pull-up.
21. These pins should be pulled to ground (GND)
22. Ethernet MII Management Interface 2 pins function as open drain I/Os. The interface conforms to 1.2V nominal voltage
levels. LVDD must be powered to use this interface.
23. This pin requires a 200Ω pull-up to XVDD.
24. This pin requires a 200Ω pull-up to SVDD.
25. GPIO is on LVDD power plane, not OVDD.
26. Functionally, this pin is an I/O, but may act as an output only or an input only depending on the pin mux configuration defined
by the RCW.
27. See Section 3.6 ”Connection Recommendations” on page 131 for additional details on this signal.
28. For reduced core (cores 4.7 disabled) P4080 mode, this signal must be pulled low to GND.
29. For reduced core (cores 4.7 disabled) P4080 mode, voltage rail may be connected to GND to reduce power consumption.
30. Warning, incorrect voltage select settings can lead to irreversible device damage. This pin requires an external pull-up or
pulldown resistor to configure IO_VSEL[n] state. Section 3.2 ”Supply Power Setting” on page 128.
35. Pin must NOT be pulled down during power-on reset.
36. SD_REF_CLK3 is required when either bank 2 or bank 3 are enabled. Section 2.20.2 ”SerDes Reference Clocks” on page
95.
37. SDHC_DAT[4:7] require CVDD = 3.3V when muxed extended SDHC data signals are enabled via the RCW[SPI] field.
38. The cfg_dram_type (LA[24]) reset configuration pin must select the correct DRAM type such that the selected DDR
GVDD =XV
DD. Incorrect voltage select settings can lead to irreversible device damage.
39. Section 2.2 ”Power Sequencing” on page 52 and Section 5. ”Security Fuse Processor” on page 144 for additional details on
this signal.
47
1066A–HIREL–07/11
e2v semiconductors SAS 2011
P4080
2. Electrical Characteristics
This section provides the AC and DC electrical specifications for the P4080. The P4080 is currently
targeted to these specifications, some of which are independent of the I/O cell but are included for a
more complete reference. These are not purely I/O buffer design specifications.
2.1 Overall DC Electrical Characteristics
This section describes the ratings, conditions, and other characteristics.
2.1.1 Absolute Maximum Ratings
Table 2-1 provides the absolute maximum ratings.
Table 2-1. Absolute Maximum Ratings(1)
Characteristic Symbol Max Value Unit Notes
Core Group A (cores 0–3) supply voltage SENSEVDD_CA –0.3 to 1.1 V (10)
Core Group B (cores 4–7) supply voltage SENSEVDD_CB –0.3 to 1.1 V (10)
Platform supply voltage SENSEVDD_PLn–0.3 to 1.1 V (10)(11)
PLL supply voltage (Core, Platform, DDR) AVDD –0.3 to 1.1 V –
PLL supply voltage (SerDes, filtered from SVDD) AVDD_SRDS –0.3 to 1.1 V –
Fuse programming override supply POVDD –0.3 to 1.65 V –
DUART, I2C, eSHDC, DMA, MPIC, GPIO, system control and power
management, clocking, debug, I/O voltage select, and JTAG I/O voltage OVDD –0.3 to 3.63 V –
eSPI CVDD
–0.3 to 3.63
–0.3 to 2.75
–0.3 to 1.98
V –
DDR DRAM I/O voltage
DDR2
DDR3
GVDD –0.3 to 1.98
–0.3 to 1.65
V –
Enhanced local bus I/O voltage BVDD
–0.3 to 3.63
–0.3 to 2.75
–0.3 to 1.98
V –
Core power supply for SerDes transceivers SVDD –0.3 to 1.1 V –
Pad power supply for SerDes transceivers XVDD –0.3 to 1.98
–0.3 to 1.65 V (9)
Ethernet I/O, Ethernet Management Interface 1 (EMI1), USB, 1588, GPIO LVDD
–0.3 to 3.63
–0.3 to 2.75
–0.3 to 1.98
V –
Ethernet Management Interface 2 (EMI2) ––0.3 to 1.32 V (8)
48
1066A–HIREL–07/11
P4080
e2v semiconductors SAS 2011
Notes: 1. Functional operating conditions are given in Table 2-2 on page 49. Absolute maximum ratings are stress ratings only, and
functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause
permanent damage to the device.
2. Caution: MVIN must not exceed GVDD by more than 0.3V. This limit may be exceeded for a maximum of 20 ms during power-
on reset and power-down sequences.
3. Caution: OVIN must not exceed OVDD by more than 0.3V. This limit may be exceeded for a maximum of 20 ms during power-
on reset and power-down sequences.
4. Caution: LVIN must not exceed LVDD by more than 0.3V. This limit may be exceeded for a maximum of 20 ms during power-
on reset and power-down sequences.
5. (C,X,B,G,L,O)VIN and MVREFn may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 1-1.
6. Caution: CVIN must not exceed CVDD by more than 0.3V. This limit may be exceeded for a maximum of 20 ms during power-
on reset and power-down sequences.
7. Caution: BVIN must not exceed BVDD by more than 0.3V. This limit may be exceeded for a maximum of 20 ms during power-
on reset and power-down sequences.
8. Ethernet MII Management Interface 2 pins function as open drain I/Os. The interface shall conform to 1.2V nominal voltage
levels. LVDD must be powered to use this interface.
9. XVDD must be at the same voltage level as GVDD. The cfg_dram_type (LA[24]) reset configuration pin must select the correct
DRAM type such that the selected DDR GVDD = XVDD. Incorrect voltage select settings can lead to irreversible device
damage.
10. Supply voltage specified at the voltage sense pin. Voltage input pins should be regulated to provide specified voltage at the
sense pin.
11. Implementation may choose either SENSEVDD_PLn pin for feedback loop. If the platform and core groups are supplied by a
single regulator, it is recommended that SENSEVDD_CA be used.
Input voltage
DDR2/DDR3 DRAM signals MVIN –0.3 to (GVDD + 0.3) V (2)(5)
DDR2/DDR3 DRAM reference MVREFn–0.3 to (GVDD/2 + 0.3) V (2)(5)
Ethernet signals (except EMI2) LVIN –0.3 to (LVDD + 0.3) V (4)(5)
eSPI CVIN –0.3 to (CVDD + 0.3) V (5)(6)
Enhanced local bus signals BVIN –0.3 to (BVDD + 0.3) V (5)(7)
DUART, I2C, eSHDC, DMA, MPIC, GPIO, system
control and power management, clocking, debug,
I/O voltage select, and JTAG I/O voltage
OVIN –0.3 to (OVDD + 0.3) V (3)(5)
SerDes signals XVIN –0.4 to (XVDD + 0.3) V (5)
Ethernet Management Interface 2 signals ––0.3 to (1.2 + 0.3) V –
Storage temperature range TSTG –55 to 150 °C –
Table 2-1. Absolute Maximum Ratings(1) (Continued)
Characteristic Symbol Max Value Unit Notes
49
1066A–HIREL–07/11
e2v semiconductors SAS 2011
P4080
2.1.2 Recommended Operating Conditions
Table 2-2 provides the recommended operating conditions for this device. Note that the values shown
are the recommended operating conditions and proper device operation outside these conditions is not
guaranteed.
Table 2-2. Recommended Operating Conditions
Characteristic Symbol
Recommended
Value Unit Notes
Core Group A (cores 0–3) supply voltage SENSEVDD_CA 1.0V ± 50 mV V –
Core Group B (cores 4–7) supply voltage SENSEVDD_CB 1.0V ± 50 mV V –
Platform supply voltage SENSEVDD_PLn1.0V ± 50 mV V –
PLL supply voltage (Core, Platform, DDR) AVDD 1.0V ± 50 mV V –
PLL supply voltage (SerDes) AVDD_SRDS 1.0V ± 50 mV V –
Fuse Programming Override Supply POVDD 1.5V ± 75 mV V (2)
DUART, I2C, eSHDC, DMA, MPIC, GPIO, system control and power management,
clocking, debug, I/O voltage select, and JTAG I/O voltage OVDD 3.3V ± 165 mV V –
eSPI CVDD
3.3V ± 165 mV
2.5V ± 125 mV
1.8V ± 90 mV
–
DDR DRAM I/O voltage
DDR2
DDR3
GVDD
1.8V ± 90 mV
1.5V ± 75 mV
V–
Enhanced Local bus I/O voltage BVDD
3.3V ± 165 mV
2.5V ± 125 mV
1.8V ± 90 mV
V –
Core power supply for SerDes transceivers SVDD 1.0V ± 50 mV V –
Pad power supply for SerDes transceivers XVDD 1.8V ± 90 mV
1.5V ± 75 mV V –
Ethernet I/O, Ethernet Management Interface 1 (EMI1), USB, 1588, GPIO LVDD
3.3V ± 165 mV
2.5V ± 125 mV
1.8V ± 90 mV
V (1)(4)
50
1066A–HIREL–07/11
P4080
e2v semiconductors SAS 2011
Notes: 1. Selecting RGMII limits to LVDD = 2.5V
2. POVDD must be supplied 1.5V and the P4080 must operate in the specified fuse programming temperature range only
during secure boot fuse programming. For all other operating conditions, POVDD must be tied to GND, subject to the power
sequencing constraints shown in Section 2.2 ”Power Sequencing” on page 52.
3. Ethernet MII Management Interface 2 pins function as open drain I/Os. The interface conforms to 1.2-V nominal voltage
levels. LVDD must be powered to use this interface.
4. If LVDD = 3.3V or 1.8V is selected for USB, all other signals associated with LVDD must meet all VIH requirements associated
with external device inputs. (Standard serial management interfaces support 2.5V or 3.3V).
Input voltage
DDR2/DDR3 DRAM signals MVIN GND to GVDD V –
DDR2 DRAM reference MVREFn GVDD/2 ± 2% V –
DDR3 DRAM reference MVREFn GVDD/2 ± 1% V –
Ethernet signals (except EMI2), USB, 1588, GPIO LVIN GND to LVDD V –
eSPI CVIN GND to CVDD V –
Local bus signals BVIN GND to BVDD V –
DUART, I2C, eSHDC, DMA, MPIC, GPIO, system
control and power management, clocking, debug, I/O
voltage select, and JTAG I/O voltage
OVIN GND to OVDD V –
Serdes signals XVIN GND to XVDD V –
Ethernet Management Interface 2 (EMI2) signals –GND to 1.2V V (3)
Operating temperature range
Normal operation TC,
TJ
TC = –40 to
TJ = 110
TC = –55 to
TJ = 125
°C –
Secure Boot Fuse Programming TA,
TJ
TA = 0 (min) to
TJ = 70 (max) °C (2)
Table 2-2. Recommended Operating Conditions (Continued)
Characteristic Symbol
Recommended
Value Unit Notes
51
1066A–HIREL–07/11
e2v semiconductors SAS 2011
P4080
Figure 2-1 shows the undershoot and overshoot voltages at the interfaces of the P4080.
Figure 2-1. Overshoot/Undershoot Voltage for BVDD/GVDD/LVDD/OVDD/XVDD/CVDD
Note: tCLOCK refers to the clock period associated with the respective interface:
For I2C OVDD, tCLOCK references SYSCLK.
For DDR GVDD, tCLOCK references SYSCLK.
For eSPI CVDD, tCLOCK references SPI_CLK.
For eLBC BVDD, tCLOCK references LCLK.
For SerDes XVDD, tCLOCK references SD_REF_CLK.
For dTSEC LVDD, tCLOCK references EC_GTX_CLK125.
For JTAG OVDD, tCLOCK references TCK.
The core and platform voltages must always be provided at nominal 1.0V. See Table 2-2 on page 49 for
actual recommended core voltage. Voltage to the processor interface I/Os are provided through
separate sets of supply pins and must be provided at the voltages shown in Table 2-2. The input voltage
threshold scales with respect to the associated I/O supply voltage. CVDD, BVDD, OVDD and LVDD based
receivers are simple CMOS I/O circuits and satisfy appropriate LVCMOS type specifications. The DDR
SDRAM interface uses differential receivers referenced by the externally supplied MVREFn signal
(nominally set to GVDD/2) as is appropriate for the SSTL_1.5/SSTL_1.8 electrical signaling standard.
The DDR DQS receivers cannot be operated in single-ended fashion. The complement signal must be
properly driven and cannot be grounded.
GND
GND – 0.3 V
GND – 0.7 V Not to Exceed 10%
Nominal C/X/B/G/L/OVDD + 20%
C/X/B/G/L/OVDD
C/X/B/G/L/OVDD + 5%
of tCLOCK1
V
IH
VIL
52
1066A–HIREL–07/11
P4080
e2v semiconductors SAS 2011
2.1.3 Output Driver Characteristics
Table 2-3 provides information on the characteristics of the output driver strengths. The values are
preliminary estimates.
Note: 1. The drive strength of the DDR2 or DDR3 interface in half-strength mode is at TJ = 105°C and at GVDD
(min).
2.2 Power Sequencing
The P4080 requires its power rails to be applied in a specific sequence in order to ensure proper device
operation. The requirements are as follows for power up:
1. Bring up OVDD, LVDD, BVDD, CVDD. Drive POVDD = GND.
– PORESET input must be driven asserted and held during this step.
– IO_VSEL inputs must be driven during this step and held stable during normal operation.
2. Bring up VDD_PL, VDD_CA, VDD_CB, SVDD, AVDD (cores, platform, DDR, SerDes).
3. Bring up GVDD, XVDD.
4. Deassert PORESET input as long as the required assertion/hold time has been met per Table
2-13 on page 59.
5. For secure boot fuse programming: After deassertion of PORESET, drive POVDD = 1.5V after a
required minimum delay per Table 2-4 on page 53. After fuse programming is completed, it is
required to return POVDD = GND before the system is power cycled (PORESET assertion) or
powered down (VDD_PL ramp down) per the required timing specified in Table 2-4. Section 5.
”Security Fuse Processor” on page 144 for additional details.
Table 2-3. Output Drive Capability
Driver Type Output Impedance (Ω) Supply Voltage Notes
Local bus interface utilities signals 45
BVDD = 3.3V
BVDD = 2.5V
BVDD = 1.8V
–
DDR2 signal 18
35 (half-strength mode) GVDD = 1.8V (1)
DDR3 signal 17
40 (half-strength mode) GVDD = 1.5V (1)
dTSEC/10/100 signals 45
LVDD = 3.3V
LVDD = 2.5V
LVDD = 1.8V
–
DUART, JTAG, System Control 45 OVDD = 3.3V –
I2C 45 OVDD = 3.3V –
eSPI 45
CVDD = 3.3V
CVDD = 2.5V
CVDD = 1.8V
–
53
1066A–HIREL–07/11
e2v semiconductors SAS 2011
P4080
WARNING
Only two secure boot fuse programming events are permitted per lifetime of a device.
No activity other than that required for secure boot fuse programming is permitted while POVDD is
driven to any voltage above GND, including the reading of the fuse block. The reading of the fuse
block may only occur while POVDD = GND.
WARNING
While VDD is ramping, current may be supplied from VDD through the P4080 to GVDD.
Nevertheless, GVDD from an external supply should follow the sequencing described in this section.
Figure 2-2 provides the POVDD timing diagram.
Figure 2-2. POVDD Timing Diagram
Note: POVDD must be stable at 1.5V prior to initiating fuse programming.
Table 2-4 provides information on the power-down and power-up sequence parameters for POVDD.
Notes: 1. Delay required from the deassertion of PORESET to driving POVDD ramp up. Delay measured from
PORESET deassertion at 90% OVDD to 10% POVDD ramp up.
2. Delay required from fuse programming finished to POVDD ramp down start. Fuse programming must
complete while POVDD is stable at 1.5V. No activity other than that required for secure boot fuse
programming is permitted while POVDD driven to any voltage above GND, including the reading of the
fuse block. The reading of the fuse block may only occur while POVDD = GND. After fuse programming
is completed, it is required to return POVDD = GND.
3. Delay required from POVDD ramp down complete to VDD_PL ramp down start. POVDD must be grounded
to minimum 10% POVDD before VDD_PL is at 90% VDD.
4. Delay required from POVDD ramp down complete to PORESET assertion. POVDD must be grounded to
minimum 10% POVDD before PORESET assertion reaches 90% OVDD.
5. Only two secure boot fuse programming events are permitted per lifetime of a device.
Table 2-4. POVDD Timing(5)
Driver Type Min Max Unit Notes
tPOVDD_DELAY 100 –SYSCLKs (1)
tPOVDD_PROG 0 –µs (2)
tPOVDD_VDD 0 –µs (3)
tPOVDD_RST 0 –µs (4)
t
POVDD_PROG
t
POVDD_DELAY
POVDD
VDD_PL
PORESET
t
POVDD_RST
Fuse programming
90%
OV
DD
10% POV
DD
10% POV
DD
90% V
DD_PL
t
POVDD_VDD
90%
OV
DD
54
1066A–HIREL–07/11
P4080
e2v semiconductors SAS 2011
All supplies must be at their stable values within 75 ms.
Items on the same line have no ordering requirement with respect to one another. Items on separate
lines must be ordered sequentially such that voltage rails on a previous step must reach 90% of their
value before the voltage rails on the current step reach 10% of theirs.
WARNING
Incorrect voltage select settings can lead to irreversible device damage. Section 3.2 ”Supply Power
Setting” on page 128.
Note: From a system standpoint, if any of the I/O power supplies ramp prior to the VDD_PL, VDD_CA, or VDD_CB
supplies, the I/Os associated with that I/O supply may drive a logic one or zero during power-up, and extra
current may be drawn by the device.
2.3 Power Down Requirements
The power-down cycle must complete such that power supply values are below 0.4V before a new
power-up cycle can be started.
If performing secure boot fuse programming per Section 2.2 ”Power Sequencing” on page 52 it is
required that POVDD = GND before the system is power cycled (PORESET assertion) or powered down
(VDD_PL ramp down) per the required timing specified in Table 2-4.
2.4 Power Characteristics
Table 2-5 shows the power dissipations of the VDD_CA, VDD_CB, SVDD, and VDD_PL supply for various
operating platform clock frequencies versus the core and DDR clock frequencies.
Notes: 1. Combined power of VDD_PL, VDD_CA, VDD_CB, SVDD at 1.0V with both DDR controllers and all SerDes banks active.
Does not include I/O power.
2. Multicore activity factor of 0.7 relative to Dhrystone and 0.4 platform activity factor.
3. Typical power based on nominal processed device.
4. Maximum power with Dhrystone executing at 100% on all eight cores and executing DMA on the platform.
5. Thermal power assumes multicore activity factor of 0.7 relative to Dhrystone and executing DMA on the platform.
6. Maximum power provided for power supply design sizing.
Table 2-5. P4080 Power Dissipation
Power
Mode
Core
Freq
(MHz)
Plat
Freq
(MHz)
DDR
Data
Rate
(MHz)
PME/
FM
Freq
(MHz)
VDD_CA,
VDD_CB,
VDD_PL,
SVDD (V)
Junction
Temperature
(°C)
Core
and
Platform
Power(1)
(W)
VDD_PL
Power(6)
(W)
VDD_CA
Power(6)
(W)
VDD_CB
Power(6)
(W)
SVDD
Power(6)
(W) Notes
Typ ic al
1200 600 1200 450 1.0
65 14 ––––
(2)(3)
Thermal 105 20.4 ––––
(5)
Maximum 125 22 12.5 5.7 5.7 1.7
(4)
Typ ic al
1333 667 1333 533 1.0
65 15 ––––
(2)(3)
Thermal 105 26.3 ––––
(5)
Maximum 125 28 15.4 7.4 7.4 1.7
(4)
Typ ic al
1500 800 1300 600 1.0
65 16 ––––
(2)(3)
Thermal 105 28 ––––
(5)
Maximum 125 30 16.6 7.8 7.8 1.7
(4)
55
1066A–HIREL–07/11
e2v semiconductors SAS 2011
P4080
Table 2-6 shows the estimated power dissipation on the AVDD and AVDD_SRDS supplies for the P4080
PLLs, at allowable voltage levels.
Notes: 1. VDD_PL, VDD_CA, VDD_CB = 1.0V, TA = 80°C, TJ = 105°C
2. SVDD = 1.0V, TA = 80°C, TJ = 105°C
Table 2-7 shows the estimated power dissipation on the POVDD supply for the P4080, at allowable
voltage levels.
Note: 1. To ensure device reliability, fuse programming must be performed within the recommended fuse pro-
gramming temperature range per Table 2-2 on page 49.
Table 2-6. P4080 AVDD Power Dissipation
AVDDs Typical Maximum Unit Notes
AVDD_DDR1 5 15 mW
(1)
AVDD_CC1 5 15 mW
AVDD_CC2 5 15 mW
AVDD_CC3 5 15 mW
AVDD_CC4 5 15 mW
AVDD_PLAT 5 15 mW
AVDD_SRDS1 –36 mW
(2)
AVDD_SRDS2 –36 mW
AVDD_SRDS3 –36 mW
Table 2-7. P4080 POVDD Power Dissipation
Supply Maximum Unit Notes
POVDD 450 mW (1)
56
1066A–HIREL–07/11
P4080
e2v semiconductors SAS 2011
2.5 Thermal
Table 2-8 shows the thermal characteristics for the P4080.
Notes: 1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
2. Per JEDEC JESD51.3 and JESD51-6 with the board (JESD51.9) horizontal.
3. Thermal resistance between the die and the printed-circuit board per JEDEC JESD51.8. Board temperature is measured on
the top surface of the board near the package.
4. Junction-to-case-top at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is
used for the case temperature. Reported value includes the thermal resistance of the interface layer.
5. Junction-to-lid-top thermal resistance determined using the using MIL-STD 883 Method 1012.1. However, instead of the
cold plate, the lid top temperature is used here for the reference case temperature. Reported value does not include the
thermal resistance of the interface layer between the package and cold plate.
6. Refer to Section 3.8 ”Thermal Management Information” on page 140 for additional details.
2.6 Input Clocks
2.6.1 System Clock (SYSCLK) Timing Specifications
This section provides the system clock DC and AC timing specifications.
2.6.1.1 System Clock DC Timing Specifications
Table 2-9 provides the system clock (SYSCLK) DC specifications.
Notes: 1. The min VIL and max VIH values are based on the respective min and max OVIN values found in
Table 2-2.
2. The symbol OVIN, in this case, represents the OVIN symbol referenced in Section 2.1.2 ”Recommended
Operating Conditions” on page 49.
Table 2-8. Package Thermal Characteristics(6)
Rating Board Symbol Value Unit Notes
Junction to ambient, natural convection Single-layer board (1s) RθJA 13 °C/W
(1)(2)
Junction to ambient, natural convection Four-layer board (2s2p) RθJA 10 °C/W
(1)(3)
Junction to ambient (at 200 ft./min.) Single-layer board (1s) RθJMA 9 °C/W
(1)(2)
Junction to ambient (at 200 ft./min.) Four-layer board (2s2p) RθJMA 7 °C/W
(1)(2)
Junction to board –RθJB 3 °C/W
(3)
Junction to case top –RθJCtop 0.37 °C/W (4)
Junction to lid top –RθJClid 0.15 °C/W (5)
Table 2-9. SYSCLK DC Electrical Characteristics (At Recommended Operating Conditions with
OVDD = 3.3V, see Table 2-2 on page 49)
Parameter Symbol Min Typical Max Unit Notes
Input high voltage VIH 2.0 – – V (1)
Input low voltage VIL – – 0.8 V (1)
Input capacitance CIN – – 15 pf –
Input current (OVIN = 0V or OVIN = OVDD)I
IN – – ±50 µA (2)
57
1066A–HIREL–07/11
e2v semiconductors SAS 2011
P4080
2.6.1.2 System Clock AC Timing Specifications
Table 2-10 provides the system clock (SYSCLK) AC timing specifications.
Notes: 1. Caution: The relevant clock ratio settings must be chosen such that the resulting SYSCLK frequency, do
not exceed their respective maximum or minimum operating frequencies.
2. Measured at the rising edge and/or the falling edge at OVDD/2.
3. Slew rate as measured from ± 0.3 ΔVAC at center of peak to peak voltage at clock input.
4. Phase noise is calculated as FFT of TIE jitter.
2.6.2 Spread Spectrum Sources
Spread spectrum clock sources are an increasingly popular way to control electromagnetic interference
emissions (EMI) by spreading the emitted noise to a wider spectrum and reducing the peak noise
magnitude in order to meet industry and government requirements. These clock sources intentionally
add long-term jitter to diffuse the EMI spectral content. The jitter specification given in Table 2-10
considers short-term (cycle-to-cycle) jitter only. The clock generator’s cycle-to-cycle output jitter should
meet the P4080 input cycle-to-cycle jitter requirement. Frequency modulation and spread are separate
concerns; the P4080 is compatible with spread spectrum sources if the recommendations listed in Table
2-11 are observed.
Notes: 1. SYSCLK frequencies that result from frequency spreading and the resulting core frequency must meet
the minimum and maximum specifications given in Table 2-10.
2. Maximum spread spectrum frequency may not result in exceeding any maximum operating frequency of
the device.
CAUTION
The processor’s minimum and maximum SYSCLK and core/platform/DDR frequencies must not be
exceeded regardless of the type of clock source. Therefore, systems in which the processor is
operated at its maximum rated core/platform/DDR frequency should avoid violating the stated limits
by using down-spreading only.
Table 2-10. SYSCLK AC Timing Specifications (At Recommended Operating Conditions with OVDD =
3.3V, see Table 2-2)
Parameter/Condition Symbol Min Typ Max Unit Notes
SYSCLK frequency fSYSCLK 83.3 –133.3 MHz (1)(2)
SYSCLK cycle time tSYSCLK 7.5 –12 ns
(1)(2)
SYSCLK duty cycle tKHK/tSYSCLK 40 –60 % (2)
SYSCLK slew rate –1 –4 V/ns
(3)
SYSCLK peak period jitter –––150 ps –
SYSCLK jitter phase noise at –56 dBc –––500 KHz (4)
AC Input Swing Limits at 3.3V OVDD ΔVAC 1.9 ––V –
Table 2-11. Spread Spectrum Clock Source Recommendations (At Recommended Operating
Conditions with OVDD = 3.3V, see Table 2-2 on page 49)
Parameter Min Max Unit Notes
Frequency modulation –60 kHz –
Frequency spread –1.0 %
(1)(2)
58
1066A–HIREL–07/11
P4080
e2v semiconductors SAS 2011
2.6.3 Real Time Clock Timing
The real time clock timing (RTC) input is sampled by the platform clock. The output of the sampling latch
is then used as an input to the counters of the PIC and the time base unit of the e500-mc; there is no
need for jitter specification. The minimum period of the RTC signal should be greater than or equal to
16× the period of the platform clock with a 50% duty cycle. There is no minimum RTC frequency; RTC
may be grounded if not needed.
2.6.4 dTSEC Gigabit Reference Clock Timing
Table 2-12 provides the dTSEC gigabit reference clocks AC timing specifications.
Notes: 1. Rise and fall times for EC_GTX_CLK125 are measured from 0.5 and 2.0V for LVDD = 2.5V.
2. EC_GTX_CLK125 is used to generate the GTX clock for the dTSEC transmitter with 2% degradation.
EC_GTX_CLK125 duty cycle can be loosened from 47%/53% as long as the PHY device can tolerate
the duty cycle generated by the dTSEC GTX_CLK. Section 2.12.2.2 ”RGMII AC Timing Specifications”
on page 72 for duty cycle for 10Base-T and 100Base-T reference clock.
2.6.5 Other Input Clocks
A description of the overall clocking of this device is available in the P4080 QorIQ Integrated Multicore
Communication Processor Family Reference Manual in the form of a clock subsystem block diagram.
For information about the input clock requirements of functional blocks sourced external of the device,
such as SerDes, Ethernet Management, eSDHC, Local Bus, see the specific interface section.
Table 2-12. EC_GTX_CLK125 AC Timing Specifications
Parameter/Condition Symbol Min Typical Max Unit Notes
EC_GTX_CLK125 frequency tG125 –125 –MHz –
EC_GTX_CLK125 cycle time tG125 –8 –ns –
EC_GTX_CLK125 rise and fall time
LVDD = 2.5V tG125R/tG125F – – 0.75 ns (1)
EC_GTX_CLK125 duty cycle
1000Base-T for RGMII tG125H/tG125 47 – 53 % (2)
EC_GTX_CLK125 jitter – – – ± 150 ps (2)
59
1066A–HIREL–07/11
e2v semiconductors SAS 2011
P4080
2.7 RESET Initialization
This section describes the AC electrical specifications for the RESET initialization timing requirements.
Table 2-13 describes the AC electrical specifications for the RESET initialization timing.
Notes: 1. SYSCLK is the primary clock input for the P4080.
2. The device will assert HRESET as an output when PORESET is asserted to initiate the power-on reset process. The device
releases HRESET sometime after PORESET is deasserted. The exact sequencing of HRESET deassertion is documented
in Section 4.4.1 Power-On Reset Sequence of the P4080 QorIQ Integrated Multicore Communication Processor Family
Reference Manual.
3. PORESET must be driven asserted before the core and platform power supplies are powered up.
Table 2-14 provides the PLL lock times.
2.8 Power-on Ramp Rate
This section describes the AC electrical specifications for the power-on ramp rate requirements.
Controlling the maximum power-on ramp rate is required to avoid falsely triggering the ESD circuitry.
Table 2-15 provides the power supply ramp rate specifications.
Notes: 1. Ramp rate is specified as a linear ramp from 10 to 90%. If non-linear (e.g. exponential), the maximum
rate of change from 200 to 500 mV is the most critical as this range might falsely trigger the ESD
circuitry.
2. Over full recommended operating temperature range (see Table 2-2 on page 49).
Table 2-13. RESET Initialization Timing Specifications
Parameter/Condition Min Max Unit Notes
Required assertion time of PORESET 1 – ms
(3)
Required input assertion time of HRESET 32 – SYSCLKs
(1)(2)
Input setup time for POR configs with respect to negation of PORESET 4 – SYSCLKs
(1)
Input hold time for all POR configs with respect to negation of PORESET 2 – SYSCLKs
(1)
Maximum valid-to-high impedance time for actively driven POR configs with
respect to negation of PORESET – 5 SYSCLKs
(1)
Table 2-14. PLL Lock Times
Parameter/Condition Min Max Unit Notes
PLL lock times – 100 µs –
Table 2-15. Power Supply Ram Rate
Parameter Min Max Unit Notes
Required ramp rate for all voltage supplies (including OVDD/CVDD/
GVDD/BVDD/SVDD/XVDD/LVDD, all core and platform VDD supplies,
MVREF and all AVDD supplies.)
– 36000 V/s (1)(2)
60
1066A–HIREL–07/11
P4080
e2v semiconductors SAS 2011
2.9 DDR2 and DDR3 SDRAM Controller
This section describes the DC and AC electrical specifications for the DDR2 and DDR3 SDRAM
controller interface. Note that the required GVDD(typ) voltage is 1.8V or 1.5V when interfacing to DDR2 or
DDR3 SDRAM respectively.
2.9.1 DDR2 and DDR3 SDRAM Interface DC Electrical Characteristics
Table 2-16 provides the recommended operating conditions for the DDR SDRAM controller when
interfacing to DDR2 SDRAM.
Notes: 1. GVDD is expected to be within 50 mV of the DRAM’s voltage supply at all times. The DRAM’s and memory controller’s
voltage supply may or may not be from the same source.
2. MVREFn is expected to be equal to 0.5 × GVDD and to track GVDD DC variations as measured at the receiver. Peak-to-peak
noise on MVREFn may not exceed the MVREFn DC level by more than ±2% of the DC value (that is, ±36 mV).
3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made, and it is expected to be
equal to MVREFn with a min value of MVREFn – 0.04 and a max value of MVREFn + 0.04. This rail should track variations
in the DC level of MVREFn.
4. The voltage regulator for MVREFn must meet the specifications stated in Table 2-19 on page 61.
5. Input capacitance load for DQ, DQS, and DQS are available in the IBIS models.
6. Output leakage is measured with all outputs disabled, 0V ≤VOUT ≤GVDD.
7. See the IBIS model for the complete output IV curve characteristics.
8. IOH and IOL are measured at GVDD = 1.7V
Table 2-16. DDR2 SDRAM Interface DC Electrical Characteristics (At Recommended Operating Condition with GVDD =
1.8V(1), see Table 2-2)
Parameter/Condition Symbol Min Max Unit Notes
I/O reference voltage MVREFn 0.49 × GVDD 0.51 × GVDD V (2)(3)(4)
Input high voltage VIH MVREFn + 0.125 – V (5)
Input low voltage VIL – MVREFn – 0.125 V (5)
I/O leakage current IOZ –50 50 µA (6)
Output high current (VOUT = 1.420V) IOH – –13.4 mA (7)(8)
Output low current (VOUT = 0.280V) IOL 13.4 – mA
(7)(8)
61
1066A–HIREL–07/11
e2v semiconductors SAS 2011
P4080
Table 2-17 provides the recommended operating conditions for the DDR SDRAM controller when
interfacing to DDR3 SDRAM.
Notes: 1. GVDD is expected to be within 50 mV of the DRAM’s voltage supply at all times. The DRAM’s and memory controller’s
voltage supply may or may not be from the same source.
2. MVREFn is expected to be equal to 0.5 × GVDD and to track GVDD DC variations as measured at the receiver. Peak-to-peak
noise on MVREFn may not exceed the MVREFn DC level by more than ±1% of the DC value (that is, ±15 mV).
3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made, and it is expected to be
equal to MVREFn with a min value of MVREFn – 0.04 and a max value of MVREFn + 0.04. This rail should track variations
in the DC level of MVREFn.
4. The voltage regulator for MVREFn must meet the specifications stated in Table 2-19.
5. Input capacitance load for DQ, DQS, and DQS are available in the IBIS models.
6. Output leakage is measured with all outputs disabled, 0V ≤VOUT ≤GVDD.
7. See the IBIS model for the complete output IV curve characteristics.
8. IOH and IOL are measured at GVDD = 1.425V.
Table 2-18 provides the DDR controller interface capacitance for DDR2 and DDR3.
Notes: 1. This parameter is sampled. GVDD = 1.8V ± 0.1V (for DDR2), f = 1 MHz, TA = 25°C, VOUT = GVDD/2,
VOUT (peak-to-peak) = 0.2V.
2. This parameter is sampled. GVDD = 1.5V ± 0.075V (for DDR3), f = 1 MHz, TA = 25°C, VOUT = GVDD/2,
VOUT (peak-to-peak) = 0.150V.
Table 2-19 provides the current draw characteristics for MVREFn.
Table 2-17. DDR3 SDRAM Interface DC Electrical Characteristics (At Recommended Operating Condition with
GVDD =1.5V
(1), see Table 2-2 on page 49)
Parameter/Condition Symbol Min Max Unit Notes
I/O reference voltage MVREFn0.49 × GVDD 0.51 × GVDD V (2)(3)(4)
Input high voltage VIH MVREFn + 0.100 GVDD V (5)
Input low voltage VIL GND MVREFn – 0.100 V (5)
I/O leakage current IOZ –50 50 µA (6)
Output high current (VOUT = 1.075V) IOH – –14.0 mA (7)(8)
Output low current (VOUT = 0.350V) IOL 14.0 – mA
(7)(8)
Table 2-18. DDR2 and DDR3 SDRAM Capacitance (At Recommended Operating Conditions with
GVDD of 1.8V for DDR2 or 1.5V for DDR3, see Table 2-2 on page 49).
Parameter/Condition Symbol Min Max Unit Notes
Input/output capacitance: DQ, DQS, DQS C
IO 6 8 pF
(1)(2)
Delta input/output capacitance: DQ, DQS, DQS C
DIO –0.5 pF
(1)(2)
Table 2-19. Current Draw Characteristics for MVREFn (For Recommended Operating Conditions, see
Table 2-2 on page 49)
Parameter/Condition Symbol Min Max Unit Note
Current draw for DDR2 SDRAM for MVREFn MVREFn – 1500 µA –
Current draw for DDR3 SDRAM for MVREFn MVREFn – 1250 µA –
62
1066A–HIREL–07/11
P4080
e2v semiconductors SAS 2011
2.9.2 DDR2 and DDR3 SDRAM Interface AC Timing Specifications
This section provides the AC timing specifications for the DDR SDRAM controller interface. The DDR
controller supports both DDR2 and DDR3 memories. Note that the required GVDD(typ) voltage is 1.8V or
1.5V when interfacing to DDR2 or DDR3 SDRAM respectively.
2.9.2.1 DDR2 and DDR3 SDRAM Interface Input AC Timing Specifications
Table 2-20 provides the input AC timing specifications for the DDR controller when interfacing to DDR2
SDRAM.
Table 2-21 provides the input AC timing specifications for the DDR controller when interfacing to
DDR3 SDRAM.
Table 2-20. DDR2 SDRAM Interface Input AC Timing Specifications (At Recommended Operating
Conditions with GVDD of 1.8V, see Table 2-2 on page 49)
Parameter Symbol Min Max Unit Notes
AC input low voltage VILAC –MVREFn – 0.20 V –
AC input high voltage VIHAC MVREFn + 0.20 – V –
Table 2-21. DDR3 SDRAM Interface Input AC Timing Specifications (At Recommended Operating
Conditions with GVDD of 1.5V, see Table 2-2)
Parameter Symbol Min Max Unit Notes
AC input low voltage > 1200 MHz data rate VILAC – MVREFn – 0.150 V
–
≤1200 MHz data rate – MVREFn – 0.175
AC input high voltage > 1200 MHz data rate VIHAC MVREFn + 0.150 – V
–
≤1200 MHz data rate MVREFn + 0.175 –
63
1066A–HIREL–07/11
e2v semiconductors SAS 2011
P4080
Table 2-22 provides the input AC timing specifications for the DDR controller when interfacing to DDR2
and DDR3 SDRAM.
Notes: 1. tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that
will be captured with MDQS[n]. This should be subtracted from the total timing budget.
2. DDR3 only.
3. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW
. This can be
determined by the following equation: tDISKEW = ±(T ÷ 4 – abs(tCISKEW) where T is the clock period and abs(tCISKEW) is the
absolute value of tCISKEW.
4. DDR2 only.
5. tCISKEW test coverage is derived from tested tDISKEW parameter.
Figure 2-3 shows the DDR2 and DDR3 SDRAM interface input timing diagram.
Figure 2-3. DDR2 and DDR3 SDRAM Interface Input Timing Diagram
Table 2-22. DDR2 and DDR3 SDRAM Interface Input AC Timing Specifications (At Recommended Operating
Conditions with GVDD of 1.8V for DDR2 or 1.5V for DDR3, see Table 2-2 on page 49. Synchronous mode
not supported for data rates above 800 MHz, data rate frequencies above 800 MHz must run in
asynchronous mode)
Parameter Symbol Min Max Unit Notes
Controller Skew for MDQS–MDQ/MECC
tCISKEW
––
ps
(1)(5)
1333 MHz data rate –125 125 (1)(2)(5)
1200 MHz data rate –142 142 (1)(2)(5)
1066 MHz data rate –170 170 (1)(2)(5)
800 MHz data rate –200 200 (1)(5)
667 MHz data rate –240 240 (1)(4)(5)
Tolerated Skew for MDQS–MDQ/MECC
tDISKEW
––
ps
(3)
1333 MHz data rate –250 250 (2)(3)
1200 MHz data rate –275 275 (2)(3)
1066 MHz data rate –300 300 (2)(3)
800 MHz data rate –425 425 (3)
667 MHz data rate –510 510 (3)(4)
MCK[n]
MCK[n] tMCK
MDQ[x]
MDQS[n]
tDISKEW
D1D0
tDISKEW
tDISKEW
64
1066A–HIREL–07/11
P4080
e2v semiconductors SAS 2011
2.9.2.2 DDR2 and DDR3 SDRAM Interface Output AC Timing Specifications
Table 2-23 contains the output AC timing targets for the DDR2 and DDR3 SDRAM interface.
Table 2-23. DDR2 and DDR3 SDRAM Interface Output AC Timing Specifications
(At Recommended Operating Conditions with GVDD of 1.8V for DDR2 or 1.5V for DDR3, see Table 2-2 on
page 49. Synchronous mode not supported above 800 MHz; frequencies above 800 MHz must run in
asynchronous mode)
Parameter Symbol(1) Min Max Unit Notes
MCK[n] cycle time tMCK 1.5 5 ns (2)
ADDR/CMD output setup with respect to MCK tDDKHAS ns (3)
1333 MHz data rate 0.606 –(6)
1200 MHz data rate 0.675 –(6)
1066 MHz data rate 0.744 –(6)
800 MHz data rate 0.917 ––
667 MHz data rate 1.10 –(7)
ADDR/CMD output hold with respect to MCK tDDKHAX ns (3)
1333 MHz data rate 0.606 –(6)
1200 MHz data rate 0.675 –(6)
1066 MHz data rate 0.744 –(6)
800 MHz data rate 0.917 ––
667 MHz data rate 1.10 –(7)
MCS[n] output setup with respect to MCK tDDKHCS ns (3)
1333 MHz data rate 0.606 –(6)
1200 MHz data rate 0.675 –(6)
1066 MHz data rate 0.744 –(6)
800 MHz data rate 0.917 ––
667 MHz data rate 1.10 –(7)
MCS[n] output hold with respect to MCK tDDKHCX ns (3)
1333 MHz data rate 0.606 –(6)
1200 MHz data rate 0.675 –(6)
1066 MHz data rate 0.744 –(6)
800 MHz data rate 0.917 ––
667 MHz data rate 1.10 –(7)
MCK to MDQS Skew tDDKHMH ns (4)
≥1066 MHz data rate -0.245 0.245 (6)(8)
800 MHz data rate –0.375 0.375 –
667 MHz data rate –0.6 0.6 (7)
MDQ/MECC/MDM output setup with respect to MDQS tDDKHDS,
tDDKLDS
ps (5)
65
1066A–HIREL–07/11
e2v semiconductors SAS 2011
P4080
Notes: 1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs
and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. Output hold time can be read as DDR timing (DD) from the
rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example, tDDKHAS
symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes from the high (H) state until outputs (A) are
setup (S) or output valid time. Also, tDDKLDX symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes
low (L) until data outputs (D) are invalid (X) or data output hold time.
2. All MCK/MCK_B and MDQS/MDQS_B referenced measurements are made from the crossing of the two signals.
3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM/MDQS.
4. tDDKHMH follows the symbol conventions described in note 1. For example, tDDKHMH describes the DDR timing (DD) from the
rising edge of the MCK[n] clock (KH) until the MDQS signal is valid (MH). tDDKHMH can be modified through control of the
MDQS override bits (called WR_DATA_DELAY) in the TIMING_CFG_2 register. This is typically set to the same delay as in
DDR_SDRAM_CLK_CNTL[CLK_ADJUST]. The timing parameters listed in the table assume that these two parameters
have been set to the same adjustment value. See the P4080 QorIQ Integrated Multicore Communication Processor Family
Reference Manual for a description and explanation of the timing modifications enabled by use of these bits.
5. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC
(MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the microprocessor.
6. DDR3 only
7. DDR2 only
8. For 1200/1333 frequencies it is required to program the start value of the DQS adjust for write leveling.
Note: For the ADDR/CMD setup and hold specifications in Table 2-23 on page 64, it is assumed that the clock
control register is set to adjust the memory clocks by 1/2 applied cycle.
1333 MHz data rate 250 –(6)
1200 MHz data rate 275 –(6)
1066 MHz data rate 300 –(6)
800 MHz data rate 375 – –
667 MHz data rate 450 – (7)
MDQ/MECC/MDM output hold with respect to MDQS tDDKHDX,
tDDKLDX
ps (5)
1333 MHz data rate 250 – (6)
1200 MHz data rate 275 – (6)
1066 MHz data rate 300 – (6)
800 MHz data rate 375 – –
667 MHz data rate 450 – (7)
MDQS preamble tDDKHMP 0.9 × tMCK –ns –
MDQS postamble tDDKHME 0.4 × tMCK 0.6 × tMCK ns –
Table 2-23. DDR2 and DDR3 SDRAM Interface Output AC Timing Specifications (Continued)
(At Recommended Operating Conditions with GVDD of 1.8V for DDR2 or 1.5V for DDR3, see Table 2-2 on
page 49. Synchronous mode not supported above 800 MHz; frequencies above 800 MHz must run in
asynchronous mode)
Parameter Symbol(1) Min Max Unit Notes
66
1066A–HIREL–07/11
P4080
e2v semiconductors SAS 2011
Figure 2-4 shows the DDR2 and DDR3 SDRAM interface output timing for the MCK to MDQS skew
measurement (tDDKHMH).
Figure 2-4. tDDKHMH Timing Diagram
Figure 2-5 shows the DDR2 and DDR3 SDRAM output timing diagram.
Figure 2-5. DDR2 and DDR3 Output Timing Diagram
MDQS[n]
MCK[n]
MCK[n]
tMCK
tDDKHMH(max)
tDDKHMH(min)
MDQS[n]
ADDR/CMD
tDDKHAS, tDDKHCS
tDDKLDS
tDDKHDS
MDQ[x]
MDQS[n]
MCK[n]
MCK[n]
tMCK
tDDKLDX
tDDKHDX
D1D0
tDDKHAX, tDDKHCX
Write A0 NOOP
tDDKHME
tDDKHMH
tDDKHMP
67
1066A–HIREL–07/11
e2v semiconductors SAS 2011
P4080
Figure 2-6 provides the AC test load for the DDR2 and DDR3 Controller bus.
Figure 2-6. DDR2 and DDR3 Controller Bus AC Test Load
2.9.2.3 DDR2 and DDR3 SDRAM Differential Timing Specifications
This section describes the DC and AC differential timing specifications for the DDR2 and DDR3 SDRAM
controller interface.
Figure 2-7. DDR2 and DDR3 SDRAM Differential Timing Specifications
Note: VTR specifies the true input signal (such as MCK or MDQS) and VCP is the complementary input signal
(such as MCK or MDQS).
Table 2-24 provides the DDR2 differential specifications for the differential signals MDQS/MDQS and
MCK/MCK.
Note: 1. I/O drivers are calibrated before making measurements.
Table 2-25 provides the DDR3 differential specifications for the differential signals MDQS/MDQS and
MCK/MCK.
Note: 1. I/O drivers are calibrated before making measurements.
Output Z0 = 50Ω
RL =50Ω
GVDD/2
VTR
VCP
GND
GVDD
VOX
or V
IX
GV
DD
/2
Table 2-24. DDR2 SDRAM Differential Electrical Characteristics
Parameter/Condition Symbol Min Max Unit Notes
Input AC differential cross-point voltage VIXAC 0.5 × GVDD – 0.175 0.5 × GVDD + 0.175 V –
Output AC differential cross-point voltage VOXAC 0.5 × GVDD – 0.125 0.5 × GVDD + 0.125 V –
Table 2-25. DDR3 SDRAM Differential Electrical Characteristics
Parameter/Condition Symbol Min Max Unit Notes
Input AC Differential Cross-point Voltage VIXAC 0.5 × GVDD – 0.150 0.5 × GVDD + 0.150 V –
Output AC Differential Cross-point Voltage VOXAC 0.5 × GVDD – 0.115 0.5 × GVDD + 0.115 V –
68
1066A–HIREL–07/11
P4080
e2v semiconductors SAS 2011
2.10 eSPI
This section describes the DC and AC electrical specifications for the eSPI interface.
2.10.1 eSPI DC Electrical Characteristics
Table 2-26 provides the DC electrical characteristics for the eSPI interface operating at CVDD = 3.3V.
Notes: 1. The min VIL and max VIH values are based on the respective min and max CVIN values found in
Table 2-2.
2. The symbol VIN, in this case, represents the CVIN symbol referenced in Section 2.1.2 ”Recommended
Operating Conditions” on page 49.
Table 2-27 provides the DC electrical characteristics for the eSPI interface operating at CVDD = 2.5V..
Notes: 1. The min VIL and max VIH values are based on the respective min and max CVIN values found in
Table 2-2.
2. The symbol VIN, in this case, represents the CVIN symbol referenced in Section 2.1.2 ”Recommended
Operating Conditions” on page 49.
Table 2-26. eSPI DC Electrical Characteristics (3.3V) (For Recommended Operating Conditions, see
Table 2-2 on page 49)
Parameter Symbol Min Max Unit
Input high voltage VIH 2 – V
Input low voltage VIL –0.8 V
Input current (VIN = 0V or VIN = CVDD)I
IN – ±40 µA
Output high voltage (CVDD = min, IOH = –2 mA) VOH 2.4 – V
Output low voltage (CVDD = min, IOL = 2 mA) VOL –0.4 V
Table 2-27. eSPI DC Electrical Characteristics (2.5V) (For Recommended Operating Conditions, see
Table 2-2 on page 49)
Parameter Symbol Min Max Unit
Input high voltage VIH 1.7 – V
Input low voltage VIL –0.7 V
Input current (VIN = 0V or VIN = CVDD) IIN – ±40 µA
Output high voltage (CVDD = min, IOH = –1 mA) VOH 2.0 – V
Output low voltage (CVDD = min, IOL = 1 mA) VOL –0.4 V
69
1066A–HIREL–07/11
e2v semiconductors SAS 2011
P4080
Table 2-28 provides the DC electrical characteristics for the eSPI interface operating at CVDD = 1.8V.
Notes: 1. The min VILand max VIH values are based on the respective min and max CVIN values found in
Table 2-2.
2. The symbol VIN, in this case, represents the CVIN symbol referenced in Section 2.1.2 ”Recommended
Operating Conditions” on page 49.
2.10.2 eSPI AC Timing Specifications
Table 2-29 and provide the eSPI input and output AC timing specifications.
Notes: 1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs
and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tNIKHOV symbolizes the NMSI outputs internal
timing (NI) for the time tSPI memory clock reference (K) goes from the high state (H) until outputs (O) are valid (V).
2. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings
are measured at the pin.
3. The greater of the two output timings for tNIKHOX and tNIKHOV are used when SPCOM[RxDelay] of the eSPI command register
is set. For example, the tNIKHOX is 4.0 and tNIKHOV is 7.0 if SPCOM[RxDelay] is set to be 1.
Figure 2-8 provides the AC test load for the eSPI.
Figure 2-8. eSPI AC Test Load
Table 2-28. eSPI DC Electrical Characteristics (1.8V) (For Recommended Operating Conditions, see
Table 2-2 on page 49)
Parameter Symbol Min Max Unit
Input high voltage VIH 1.25 – V
Input low voltage VIL –0.6 V
Input current (VIN = 0V or VIN = CVDD) IIN –±40 µA
Output high voltage (CVDD = min, IOH = –0.5 mA) VOH 1.35 – V
Output low voltage (CVDD = min, IOL = 0.5 mA) VOL –0.4 V
Table 2-29. eSPI AC Timing Specifications(1)
Characteristic Symbol(2) Min Max Unit Note
SPI_MOSI output–Master data (internal clock) hold time tNIKHOX
tNIKHOX
0.5
4.0 –ns
(2)(3)
SPI_MOSI output–Master data (internal clock) delay tNIKHOV
tNIKHOV –6.0
7.0 ns (2)(3)
SPI_CS outputs–Master data (internal clock) hold time tNIKHOX2 0 – ns
(2)
SPI_CS outputs–Master data (internal clock) delay tNIKHOV2 –6.0 ns (2)
SPI inputs–Master data (internal clock) input setup time tNIIVKH 5 – ns –
SPI inputs–Master data (internal clock) input hold time tNIIXKH 0 – ns –
Output Z0 = 50ΩCVDD/2
RL =50Ω
70
1066A–HIREL–07/11
P4080
e2v semiconductors SAS 2011
Figure 2-9 represent the AC timing from Table 2-29 on page 69 in master mode (internal clock). Note
that although the specifications generally reference the rising edge of the clock, these AC timing
diagrams also apply when the falling edge is the active edge. Also, note that the clock edge is selectable
on eSPI.
Figure 2-9. eSPI AC Timing in Master Mode (Internal Clock) Diagram
2.11 DUART
This section describes the DC and AC electrical specifications for the DUART interface.
2.11.1 DUART DC Electrical Characteristics
Table 2-30 provides the DC electrical characteristics for the DUART interface.
Note: 1. The symbol OVIN, in this case, represents the OVIN symbol referenced in Table 2-2.
SPICLK (output)
tNIIXKH
tNIKHOV
Input Signals:
SPIMISO
Output Signals:
SPIMOSI
tNIIVKH
tNIKHOX
Output Signals:
SPI_CS[0:3]
tNIKHOV2
t
NIKHOX2
Table 2-30. DUART DC Electrical Characteristics (For Recommended Operating Conditions, see
Table 2-2 on page 49)
Parameter Symbol Min Max Unit Notes
Input high voltage VIH 2 – V
(1)
Input low voltage VIL –0.8 V (1)
Input current (OVIN = 0V or OVIN = OVDD) IIN –±40 µA (2)
Output high voltage (OVDD = min, IOH = –2 mA) VOH 2.4 – V –
Output low voltage (OVDD = min, IOL = 2 mA) VOL –0.4 V –
71
1066A–HIREL–07/11
e2v semiconductors SAS 2011
P4080
2.11.2 DUART AC Electrical Specifications
Table 2-31 provides the AC timing parameters for the DUART interface.
Notes: 1. fPLAT refers to the internal platform clock.
2. The actual attainable baud rate is limited by the latency of interrupt processing.
3. This parameter is sampled.
2.12 Ethernet: Data Path Three-Speed Ethernet (dTSEC), Management Interface 1 and 2, IEEE
Std 1588™
This section provides the AC and DC electrical characteristics for the data path three-speed Ethernet
controller, and the Ethernet Management Interfaces.
2.12.1 SGMII Timing Specifications
See Section 2.20.8 ”SGMII Interface” on page 115.
2.12.2 RGMII Timing Specifications
This section discusses the electrical characteristics for the RGMII interface.
2.12.2.1 RGMII DC Timing Specifications
Table 2-32 provides the DC electrical characteristics for the RGMII interface.
Notes: 1. The min VIL and max VIH values are based on the respective min and max LVIN values found in
Table 2-2.
2. The symbol LVIN, in this case, represents the LVIN symbol referenced in Section 2.1.2 ”Recommended
Operating Conditions” on page 49.
Table 2-31. DUART AC Timing Specifications
Parameter Value Unit Notes
Minimum baud rate fPLAT/(2 × 1,048,576) baud (1)(3)
Maximum baud rate fPLAT/(2 × 16) baud (1)(2)
Table 2-32. RGMII DC Electrical Characteristics (LVDD = 2.5V) (For Recommended Operating
Conditions, see Table 2-2 on page 49)
Parameters Symbol Min Max Unit Notes
Input high voltage VIH 1.70 – V (1)
Input low voltage VIL –0.70 V (1)
Input current (LVIN = 0V or LVIN = LVDD) IIH –±40 µA (2)
Output high voltage (LVDD = min, IOH = –1.0 mA) VOH 2.00 – V –
Output low voltage (LVDD = min, IOL = 1.0 mA) VOL –0.40 V –
72
1066A–HIREL–07/11
P4080
e2v semiconductors SAS 2011
2.12.2.2 RGMII AC Timing Specifications
Table 2-33 presents the RGMII AC timing specifications.
Notes: 1. In general, the clock reference symbol representation for this section is based on the symbols RGT to represent RGMII
timing. Note that the notation for rise (R) and fall (F) times follows the clock symbol that is being represented. For symbols
representing skews, the subscript is skew (SK) followed by the clock that is being skewed (RGT).
2. This implies that PC board design will require clocks to be routed such that an additional trace delay of greater than 1.5 ns
will be added to the associated clock signal. Many PHY vendors already incorporate the necessary delay inside their chip. If
so, additional PCB delay is probably not needed.
3. For 10 and 100 Mbps, tRGT scales to 400 ns ± 40 ns and 40 ns ± 4 ns, respectively.
4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as
long as the minimum duty cycle is not violated and stretching occurs for no more than three tRGT of the lowest speed
transitioned between.
5. Applies to inputs and outputs.
6. System/board must be designed to ensure this input requirement to the device is achieved. Proper device operation is
guaranteed for inputs meeting this requirement by design, simulation, characterization, or functional testing.
Table 2-33. RGMII AC Timing Specifications (LVDD = 2.5V) (For Recommended Operating Conditions, see Table 2-2 on
page 49)
Parameter/Condition Symbol(1) Min Typ Max Unit Notes
Data to clock output skew (at transmitter) tSKRGT_TX –500 0 500 ps –
Data to clock input skew (at receiver) tSKRGT_RX 1.0 – 2.8 ns (2)
Clock period duration tRGT 7.2 8.0 8.8 ns (3)
Duty cycle for 10BASE-T and 100BASE-TX tRGTH/tRGT 40 50 60 % (3)(4)
Duty cycle for Gigabit tRGTH/tRGT 45 50 55 % –
Rise time (20%–80%) tRGTR – – 0.75 ns (5)(6)
Fall time (20%–80%) tRGTF – – 0.75 ns (5)(6)
73
1066A–HIREL–07/11
e2v semiconductors SAS 2011
P4080
Figure 2-10 shows the RGMII AC timing and multiplexing diagrams.
Figure 2-10. RGMII AC Timing and Multiplexing Diagrams
2.12.3 Ethernet Management Interface
This section discusses the electrical characteristics for the EMI1 and EMI2 interfaces. EMI1 is the PHY
management interface controlled by the MDIO controller associated with Frame Manager 1 dTSEC1.
EMI2 is the XAUI PHY management interface controlled by the MDIO controller associated with Frame
Manager 1 10GEC.
2.12.3.1 Ethernet Management Interface 1 DC Electrical Characteristics
The DC electrical characteristics for EMI1_MDIO and EMI1_MDC are provided in this section.
Notes: 1. The min VIL and max VIH values are based on the min and max LVIN respective values found in Table 2-2.
2. The symbol LVIN, in this case, represents the LVIN symbol referenced in Section 2.1.2 ”Recommended Operating Conditions”
on page 49.
GTX_CLK
tRGT
tRGTH
tSKRGT_TX
TX_CTL
TXD[8:5]
TXD[7:4]
TXD[9]
TXERR
TXD[4]
TXEN
TXD[3:0]
(At Transmitter)
TXD[8:5][3:0]
TXD[7:4][3:0]
TX_CLK
(At PHY)
RX_CTL
RXD[8:5]
RXD[7:4]
RXD[9]
RXERR
RXD[4]
RXDV
RXD[3:0]
RX_CLK
(At PHY)
tSKRGT_TX
tSKRGT_RX
tSKRGT_RX
tRGTH
t
RGT
GTX_CLK
(At Receiver)
RXD[8:5][3:0]
RXD[7:4][3:0]
Table 2-34. Ethernet Management Interface 1 DC Electrical Characteristics (LVDD = 3.3V)
Parameter Symbol Min Max Unit Notes
High-level input voltage VIH 2 – V
(1)
Low-level input voltage VIL –0.8 V (1)
Input high current (LVDD = Max, LVIN = 2.4V) IIH – 40 µA (2)
Input low current (LVDD = Max, LVIN = 0.4V) IIL –600 – µA –
Output high voltage (LVDD = min, IOH = –4 mA) VOH 2.4 – V –
Output low voltage (LVDD = min, IOL = 4 mA) VOL –0.4 V –
74
1066A–HIREL–07/11
P4080
e2v semiconductors SAS 2011
Notes: 1. The min VIL and max VIH values are based on the respective min and max LVIN values found in Table 2-
2.
2. The symbol VIN, in this case, represents the LVIN symbol referenced in Section 2.1.2 ”Recommended
Operating Conditions” on page 49.
2.12.3.2 Ethernet Management Interface 2 DC Electrical Characteristics
Ethernet Management Interface 2 pins function as open drain I/Os. The interface shall conform to 1.2V
nominal voltage levels.
LVDD must be powered to use this interface. The DC electrical characteristics for EMI2_MDIO and
EMI2_MDC are provided in this section.
Table 2-35. Ethernet Management Interface 1 DC Electrical Characteristics (LVDD = 2.5V)
(For Recommended Operating Conditions, see Table 2-2 on page 49)
Parameters Symbol Min Max Unit Notes
Input high voltage VIH 1.70 – V (1)
Input low voltage VIL – 0.70 V (1)
Input high current (VIN = LVDD) IIH – 40 µA (2)
Input low current (VIN = GND) IIL –40 – µA
Output high voltage (LVDD = min, IOH = –1.0 mA) VOH 2.00 – V –
Output low voltage (LVDD = min, IOL = 1.0 mA) VOL – 0.40 V –
Table 2-36. Ethernet Management Interface 2 DC Electrical Characteristics (1.2V) (For
Recommended Operating Conditions, see Table 2-2 on page 49)
Parameter Symbol Min Max Unit Notes
Input high voltage VIH 0.84 – V –
Input low voltage VIL –0.36 V –
Output high voltage (IOH = –100 µA) VOH 1.0 – V –
Output low voltage (IOL = 100 µA) VOL –0.2 V –
Output low current (VOL = 0.2V) IOL 4 – mA –
Input capacitance CIN – 10 pF –
75
1066A–HIREL–07/11
e2v semiconductors SAS 2011
P4080
2.12.3.3 Ethernet Management Interface 1 AC Electrical Specifications
Notes: 1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs
and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX symbolizes management data timing
(MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are invalid (X) or data hold time. Also, tMDDVKH
symbolizes management data timing (MD) with respect to the time data input signals (D) reach the valid state (V) relative to
the tMDC clock reference (K) going to the high (H) state or setup time.
2. This parameter is dependent on the frame manager clock frequency (MIIMCFG [MgmtClk] field determines the clock
frequency of the MgmtClk Clock EC_MDC).
3. This parameter is dependent on the frame manager clock frequency. The delay is equal to 16 frame manager clock periods
± 6 ns. For example, with a frame manager clock of 400 MHz, the min/max delay is 40 ns ± 6 ns.
4. tplb_clk is the frame manager clock period.
2.12.3.4 Ethernet Management Interface 2 AC Electrical Characteristics
Notes: 1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs
and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX symbolizes management data timing
(MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are invalid (X) or data hold time. Also, tMDDVKH
symbolizes management data timing (MD) with respect to the time data input signals (D) reach the valid state (V) relative to
the tMDC clock reference (K) going to the high (H) state or setup time.
2. This parameter is dependent on the frame manager clock frequency (MIIMCFG [MgmtClk] field determines the clock
frequency of the MgmtClk Clock EC_MDC).
3. This parameter is dependent on the management data clock frequency, fMDC. The delay is equal to 0.5 management data
clock period ±6 ns. For example, with a management data clock of 2.5 MHz, the min/max delay is 200 ns ± 6 ns.
Table 2-37. Ethernet Management Interface 1 AC Timing Specifications (For Recommended Operating Conditions, see
Table 2-2 on page 49)
Parameter/Condition Symbol(1) Min Typ Max Unit Notes
MDC frequency fMDC – – 2.5 MHz
(2)
MDC clock pulse width high tMDCH 160 – – ns –
MDC to MDIO delay tMDKHDX (16 × tplb_clk) – 6 – (16 × tplb_clk) + 6 ns (3)(4)
MDIO to MDC setup time tMDDVKH 8 – – ns –
MDIO to MDC hold time tMDDXKH 0 – – ns –
Table 2-38. Ethernet Management Interface 2 AC Electrical Characteristics (For Recommended Operating Conditions,
see Table 2-2 on page 49)
Parameter/Condition Symbol(1) Min Typ Max Unit Notes
MDC frequency fMDC – – 2.5 MHz
(2)
MDC clock pulse width high tMDCH 160 – – ns –
MDC to MDIO delay tMDKHDX (0.5 ×(1/fMDC)) – 6 – (0.5 ×(1/fMDC)) + 6 ns (3)
MDIO to MDC setup time tMDDVKH 8 – – ns –
MDIO to MDC hold time tMDDXKH 0 – – ns –
76
1066A–HIREL–07/11
P4080
e2v semiconductors SAS 2011
Figure 2-11 shows the Ethernet Management Interface timing diagram.
Figure 2-11. Ethernet Management Interface Timing Diagram
2.12.4 dTSEC IEEE 1588 AC Specifications.
Notes: 1. TRX_CLK is the maximum clock period of dTSEC receiving clock selected by TMR_CTRL[CKSEL]. See the P4080 QorIQ
Integrated Multicore Communication Processor Family Reference Manual, for a description of TMR_CTRL registers.
2. It needs to be at least two times the clock period of the clock selected by TMR_CTRL[CKSEL]. See the P4080 QorIQ
Integrated Multicore Communication Processor Family Reference Manual, for a description of TMR_CTRL registers.
3. The maximum value of tT1588CLK is not only defined by the value of TRX_CLK, but also defined by the recovered clock. For
example, for 10/100/1000 Mbps modes, the maximum value of tT1588CLK will be 2800, 280, and 56 ns, respectively.
MDC
tMDDXKH
tMDC
tMDCH
tMDDVKH
tMDKHDX
MDIO
MDIO
(Input)
(Output)
Table 2-39. dTSEC IEEE 1588 AC Timing Specifications (For Recommended Operating Conditions, see Table 2-2 on
page 49)
Parameter/Condition Symbol Min Typ Max Unit Notes
TSEC_1588_CLK clock period tT1588CLK 3.3 – TRX_CLK × 7 ns (1)(3)
TSEC_1588_CLK duty cycle tT1588CLKH/
tT1588CLK
40 50 60 %
(2)
TSEC_1588_CLK peak-to-peak jitter tT1588CLKINJ – – 250 ps –
Rise time TSEC_1588_CLK (20%–80%) tT1588CLKINR 1.0 – 2.0 ns –
Fall time TSEC_1588_CLK (80%–20%) tT1588CLKINF 1.0 – 2.0 ns –
TSEC_1588_CLK_OUT clock period tT1588CLKOUT 2 × tT1588CLK ––ns –
TSEC_1588_CLK_OUT duty cycle tT1588CLKOTH/
tT1588CLKOUT
30 50 70 % –
TSEC_1588_PULSE_OUT tT1588OV 0.5 – 3.0 ns –
TSEC_1588_TRIG_IN pulse width tT1588TRIGH
2 ×
tT1588CLK_MAX
––ns
(3)
77
1066A–HIREL–07/11
e2v semiconductors SAS 2011
P4080
Figure 2-12 shows the data and command output AC timing diagram.
Figure 2-12. dTSEC IEEE 1588 Output AC Timing
Note: The output delay is counted starting at the rising edge if tT1588CLKOUT is noninverting. Otherwise, it is
counted starting at the falling edge.
Figure 2-13 shows the data and command input AC timing diagram.
Figure 2-13. dTSEC IEEE 1588 Input AC Timing
2.13 USB
This section provides the AC and DC electrical specifications for the USB interface.
2.13.1 USB DC Electrical Characteristics
This section provides the DC electrical characteristics for the USB interface.
Notes: 1. The min VIL and max VIH values are based on the respective min and max LVIN values found in
Table 2-2.
2. The symbol LVIN, in this case, represents the LVIN symbol referenced in Section 2.1.2 ”Recommended
Operating Conditions” on page 49.
TSEC_1588_CLK_OUT
TSEC_1588_PULSE_OUT
TSEC_1588_TRIG_OUT
tT1588OV
tT1588CLKOUT
tT1588CLKOUTH
TSEC_1588_TRIG_IN
tT1588TRIGH
tT1588CLK
tT1588CLKH
TSEC_1588_CLK
Table 2-40. USB DC Electrical Characteristics (LVDD = 3.3V) (For Recommended Operating
Conditions, see Table 2-2 on page 49)
Parameter Symbol Min Max Unit Notes
Input high voltage(1) VIH 2.0 – V (1)
Input low voltage VIL –0.8 V (1)
Input current (LVIN = 0V or LVIN = LVDD) IIN –±40 µA
(2)
Output high voltage (LVDD = min, IOH = –2 mA) VOH 2.8 – V –
Output low voltage (LVDD = min, IOL = 2 mA) VOL –0.3 V –
78
1066A–HIREL–07/11
P4080
e2v semiconductors SAS 2011
Notes: 1. The min VIL and max VIH values are based on the respective min and max LVIN values found in Table 2-2.
2. The symbol LVIN, in this case, represents the LVIN symbol referenced in Section 2.1.2 ”Recommended Operating Conditions”
on page 49.
Notes: 1. The min VIL and max VIH values are based on the respective min and max LVIN values found in Table 2-2.
2. The symbol LVIN, in this case, represents the LVIN symbol referenced in Section 2.1.2 on page 49.
2.13.2 USB AC Electrical Specifications
Table 2-43 describes the general timing parameters of the USB interface of the P4080.
Notes: 1. The symbols for timing specifications follow the pattern of t(First two letters of functional block)(signal)(state) (reference)(state) for inputs and
t(First two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tUSIXKH symbolizes usb timing (US) for the input (I)
to go invalid (X) with respect to the time the usb clock reference (K) goes high (H). Also, tUSKHOX symbolizes USB timing (US)
for the USB clock reference (K) to go high (H), with respect to the output (O) going invalid (X) or output hold time.
2. All timings are in reference to USB clock.
3. All signals are measured from LVDD/2 of the rising edge of the USB clock to 0.4 × LVDD of the signal in question for 3.3V
signaling levels.
4. Input timings are measured at the pin.
5. For active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the
component pin is less than or equal to that of the leakage current specification.
Table 2-41. USB DC Electrical Characteristics (LVDD = 2.5V) (For Recommended Operating Conditions, see Table 2-2
on page 49)
Parameter Symbol Min Max Unit Notes
Input high voltage(1) VIH 1.7 – V (1)
Input low voltage VIL –0.7 V (1)
Input current (LVIN = 0V or LVIN = LVDD) IIN – ±40 µA
(2)
Output high voltage (LVDD = min, IOH = –1 mA) VOH 2.0 – V –
Output low voltage (LVDD = min, IOL = 1 mA) VOL –0.4 V –
Table 2-42. USB DC Electrical Characteristics (LVDD = 1.8V)
Parameter Symbol Min Max Unit Notes
Input high voltage(1) VIH 1.25 –V
(1)
Input low voltage VIL –0.6 V (1)
Input current (LVIN = 0V or LVIN = LVDD) IIN – ±40 µA (2)
Output high voltage (LVDD = min, IOH = –0.5 mA) VOH 1.35 – V –
Output low voltage (LVDD = min, IOL = 0.5 mA) VOL –0.4 V –
Table 2-43. USB General Timing Parameters (ULPI Mode Only)
Parameter Symbol Min Max Unit Notes
USB clock cycle time tUSCK 15 – ns
(2)(5)
Input setup to USB clock–all inputs tUSIVKH 4 – ns
(2)(5)
Input hold to USB clock–all inputs tUSIXKH 0 – ns
(2)(5)
USB clock to output valid–all outputs tUSKHOV –8 ns (2)(5)
Output hold from USB clock–all outputs tUSKHOX 2 – ns
(2)(5)
79
1066A–HIREL–07/11
e2v semiconductors SAS 2011
P4080
Figure 2-14 and Figure 2-15 provide the AC test load and signals for the USB, respectively.
Figure 2-14. USB AC Test Load
Figure 2-15. USB Signals
Table 2-44 provides the USB clock input (USBn_CLK) AC timing specifications.
Output Z0 = 50ΩLVDD/2
RL = 50Ω
Output Signals:
tUSKHOV
USB1_CLK/USB2_CLK
Input Signals
tUSIXKH
tUSIVKH
tUSKHOX
Table 2-44. USBn_CLK AC Timing Specifications
Parameter/Condition Conditions Symbol Min Typ Max Unit
Frequency range –fUSB_CLK_IN 59.97 60 60.03 MHz
Clock frequency tolerance –tCLK_TOL –0.05 0 0.05 %
Reference clock duty cycle Measured at 1.6V tCLK_DUTY 40 50 60 %
Total input jitter/time interval error
Peak-to-peak value measured with a
second order high-pass filter of
500 kHz bandwidth
tCLK_PJ ––200 ps
80
1066A–HIREL–07/11
P4080
e2v semiconductors SAS 2011
2.14 Enhanced Local Bus Interface
This section describes the DC and AC electrical specifications for the enhanced local bus interface.
2.14.1 Enhanced Local Bus DC Electrical Characteristics
Table 2-45 provides the DC electrical characteristics for the enhanced local bus interface operating at
BVDD = 3.3V.
Notes: 1. The min VIL and max VIH values are based on the respective min and max BVIN values found in
Table 2-2.
2. The symbol VIN, in this case, represents the BVIN symbol referenced in Section 2.1.2 ”Recommended
Operating Conditions” on page 49.
Table 2-46 provides the DC electrical characteristics for the enhanced local bus interface operating at
BVDD = 2.5V.
Notes: 1. The min VIL and max VIH values are based on the respective min and max BVIN values found in
Table 2-2.
2. The symbol VIN, in this case, represents the BVIN symbol referenced in Section 2.1.2 ”Recommended
Operating Conditions” on page 49.
Table 2-45. Enhanced Local Bus DC Electrical Characteristics (3.3V) (For Recommended Operating
Conditions, see Table 2-2 on page 49)
Parameter Symbol Min Max Unit Notes
Input high voltage VIH 2 – V
(1)
Input low voltage VIL –0.8 V (1)
Input current (VIN = 0V or VIN = BVDD) IIN –±40 µA (2)
Output high voltage (BVDD = min, IOH = –2 mA) VOH 2.4 – V –
Output low voltage (BVDD = min, IOL = 2 mA) VOL –0.4 V –
Table 2-46. Enhanced Local Bus DC Electrical Characteristics (2.5V) (For Recommended Operating
Conditions, see Table 2-2 on page 49).
Parameter Symbol Min Max Unit Notes
Input high voltage VIH 1.7 – V (1)
Input low voltage VIL –0.7 V (1)
Input current (VIN = 0V or VIN = BVDD) IIN – ±40 µA (2)
Output high voltage (BVDD = min, IOH = –1 mA) VOH 2.0 – V –
Output low voltage (BVDD = min, IOL = 1 mA) VOL –0.4 V –
81
1066A–HIREL–07/11
e2v semiconductors SAS 2011
P4080
Table 2-47 provides the DC electrical characteristics for the enhanced local bus interface operating at
BVDD = 1.8V
Notes: 1. The min VIL and max VIH values are based on the respective min and max BVIN values found in
Table 2-2.
2. The symbol VIN, in this case, represents the BVIN symbol referenced in Section 2.1.2 ”Recommended
Operating Conditions” on page 49.
2.14.2 Enhanced Local Bus AC Timing Specifications
This section describes the AC timing specifications for the enhanced local bus interface.
2.14.2.1 Test Condition
Figure 2-16 provides the AC test load for the enhanced local bus.
Figure 2-16. Enhanced Local Bus AC Test Load
Table 2-47. Enhanced Local Bus DC Electrical Characteristics (1.8V) (For Recommended Operating
Conditions, see Table 2-2 on page 49).
Parameter Symbol Min Max Unit Notes
Input high voltage VIH 1.25 – V (1)
Input low voltage VIL –0.6V (1)
Input current (VIN = 0V or VIN = BVDD) IIN – ±40 µA (2)
Output high voltage (BVDD = min, IOH = –0.5 mA) VOH 1.35 – V –
Output low voltage (BVDD = min, IOL = 0.5 mA) VOL –0.4 V –
Output Z0 = 50ΩBVDD/2
RL =50Ω
82
1066A–HIREL–07/11
P4080
e2v semiconductors SAS 2011
2.14.2.2 Local Bus AC Timing Specification
All output signal timings are relative to the falling edge of any LCLKs. The external circuit must use the
rising edge of the LCLKs to latch the data.
All input timings except LGTA/LUPWAIT/LFRB are relative to the rising edge of LCLKs.
LGTA/LUPWAIT/LFRB are relative to the falling edge of LCLKs.
Table 2-48 describes the timing specifications of the local bus interface.
Notes: 1. All signals are measured from BVDD/2 of rising/falling edge of LCLK to BVDD/2 of the signal in question.
2. Skew measured between different LCLKs at BVDD/2.
3. For purposes of active/float timing measurements, the high impedance or off state is defined to be when the total current
delivered through the component pin is less than or equal to the leakage current specification.
4. tLBONOT is a measurement of the minimum time between the negation of LALE and any change in LAD. tLBONOT is determined
by LBCR[AHD]. The unit is the eLBC controller clock cycle, which is the internal clock that runs the local bus controller, not
the external LCLK. After power on reset, LBCR[AHD] defaults to 0.
5. Output hold is negative. This means that output transition happens earlier than the falling edge of LCLK.
Table 2-48. Enhanced Local Bus Timing Specifications (BVDD = 3.3V, 2.5V, and 1.8V)
(For Recommended Operating Conditions, see Table 2-2 on page 49)
Parameter Symbol(1) Min Max Unit Notes
Local bus cycle time tLBK 10 – ns –
Local bus duty cycle tLBKH/tLBK 45 55 % –
LCLK[n] skew to LCLK[m] tLBKSKEW –150 ps
(2)
Input setup (except LGTA/LUPWAIT/LFRB) tLBIVKH 6 – ns –
Input hold (except LGTA/LUPWAIT/LFRB) tLBIXKH 1 – ns –
Input setup (for LGTA/LUPWAIT/LFRB) tLBIVKL 6 – ns –
Input hold (for LGTA/LUPWAIT/LFRB) tLBIXKL 1 – ns –
Output delay (Except LALE) tLBKLOV –1.5 ns –
Output hold (Except LALE) tLBKLOX –3.5 –ns
(5)
Local bus clock to output high impedance for LAD/LDP tLBKLOZ –2 ns (3)
LALE output negation to LAD/LDP output transition
(LATCH hold time) tLBONOT
0.8
(LBCR[AHD] = 1) –eLBC controller
clock cycle
(= 2 platform
clock cycles)
(4)
1.8
(LBCR[AHD] = 0) –
83
1066A–HIREL–07/11
e2v semiconductors SAS 2011
P4080
Figure 2-17 shows the AC timing diagram of the local bus interface.
Figure 2-17. Enhanced Local Bus Signals
Figure 2-18 applies to all three controllers that eLBC supports: GPCM, UPM, and FCM.
For input signals, the AC timing data is used directly for all three controllers.
For output signals, each type of controller provides its own unique method to control the signal timing.
The final signal delay value for output signals is the programmed delay plus the AC timing delay. For
example, for GPCM, LCS can be programmed to delay by tacs (0, ¼, ½, 1, 1 + ¼, 1 + ½, 2, 3 cycles), so
the final delay is tacs + tLBKHOV.
Output Signals
tLBKLOX
LCLK[m]
Input Signals
LALE
tLBIXKH
tLBIVKH
tLBIVKL
tLBIXKL
Input Signal
tLBONOT
(LGTA/LUPWAIT/LFRB)
(Except LGTA/LUPWAIT/LFRB)
(Except LALE)
LAD
(address phase)
LAD/LDP
(data phase)
tLBKLOZ
tLBKLOV
84
1066A–HIREL–07/11
P4080
e2v semiconductors SAS 2011
Figure 2-18 shows how the AC timing diagram applies to GPCM. The same principle applies to UPM and
FCM.
Figure 2-18. GPCM Output Timing Diagram
Notes: 1. taddr is programmable and determined by LCRR[EADC] and ORx[EAD].
2. tarcs, tawcs, taoe, trc, toen, tawe, twc, twen are determined by ORx. See the P4080 QorIQ Integrated Multicore
Communication Processor Family Reference Manual.
tarcs +t
LBKHOV
LCLK
LAD[0:31]
LBCTL
tLBONOT
LCS_B
LGPL2/LOE_B
address
taddr
taoe +t
LBKHOV
LWE_B
tawcs +t
LBKHOV
tLBONOT
address
taddr
tawe +t
LBKHOV
tLBKHOX
t
rc
toen
read data write data
twen
twc
write
read
LALE
85
1066A–HIREL–07/11
e2v semiconductors SAS 2011
P4080
2.15 Enhanced Secure Digital Host Controller (eSDHC)
This section describes the DC and AC electrical specifications for the eSDHC interface.
2.15.1 eSDHC DC Electrical Characteristics
Table 2-49 provides the DC electrical characteristics for the eSDHC interface. The eSDHC interface
operates at OVDD = 3.3V, however, SDHC_DAT[4:7] require CVDD = 3.3V when muxed extended SDHC
data signals are enabled via the RCW[SPI] field.
Notes: 1. The min VIL and max VIH values are based on the respective min and max OVIN values found in Table 2-2.
2. Open drain mode for MMC cards only.
2.15.2 eSDHC AC Timing Specifications
Table 2-50 provides the eSDHC AC timing specifications as defined in Figure 2-19..
Notes: 1. The symbols used for timing specifications herein follow the pattern of t(first three letters of functional block)(signal)(state) (reference)(state) for
inputs and t(first three letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tFHSKHOV symbolizes eSDHC high-
speed mode device timing (SHS) clock reference (K) going to the high (H) state, with respect to the output (O) reaching the
invalid state (X) or output hold time. Note that in general, the clock reference symbol is based on five letters representing the
clock of a particular functional. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F
(fall).
2. In full-speed mode, the clock frequency value can be 0.25 MHz for an SD/SDIO card and 0.20 MHz for an MMC card. In
high-speed mode, the clock frequency value can be 0.50 MHz for an SD/SDIO card and 0.52 MHz for an MMC card.
3. To satisfy setup timing, the delay difference between clock input and cmd/data input must not exceed 2 ns.
4. CCARD ≤10 pF, (1 card), and CL = CBUS + CHOST + CCARD ≤ 40 pF
Table 2-49. eSDHC Interface DC Electrical Characteristics (For Recommended Operating Conditions, see Table 2-2 on
page 49)
Characteristic Symbol Condition Min Max Unit Notes
Input high voltage VIH – 0.625 × OVDD –V
(1)
Input low voltage VIL – – 0.25 × OVDD V (1)
Input/output leakage current IIN/IOZ – –50 50 µA –
Output high voltage VOH I
OH = –100 µA at OVDD min 0.75 × OVDD –V –
Output low voltage VOL IOL = 100µA at OVDD min – 0.125 × OVDD V –
Output high voltage VOH I
OH = –100 µA at OVDD min OVDD –0.2 – V (2)
Output low voltage VOL IOL = 2 mA at OVDD min – 0.3 V (2)
Table 2-50. eSDHC AC Timing Specifications (For Recommended Operating Conditions, see Table 2-2)
Parameter Symbol(1) Min Max Unit Notes
SD_CLK clock frequency:
SD/SDIO Full-speed/high-speed mode
MMC Full-speed/high-speed mode
fSHSCK 0 25/50 20/52 MHz
(2)(4)
SD_CLK clock low time–Full-speed/High-speed mode tSHSCKL 10/7 – ns
(4)
SD_CLK clock high time–Full-speed/High-speed mode tSHSCKH 10/7 – ns
(4)
SD_CLK clock rise and fall times tSHSCKR/ tSHSCKF –3 ns
(4)
Input setup times: SD_CMD, SD_DATx, SD_CD to SD_CLK tSHSIVKH 5 – ns
(4)
Input hold times: SD_CMD, SD_DATx, SD_CD to SD_CLK tSHSIXKH 2.5 – ns
(3)(4)
Output delay time: SD_CLK to SD_CMD, SD_DATx valid tSHSKHOV –3 3 ns
(4)
86
1066A–HIREL–07/11
P4080
e2v semiconductors SAS 2011
Figure 2-19 provides the eSDHC clock input timing diagram.
Figure 2-19. eSDHC Clock Input Timing Diagram
Figure 2-20 provides the data and command input/output timing diagram.
Figure 2-20. eSDHC Data and Command Input/Output Timing Diagram Referenced to Clock
2.16 Programmable Interrupt Controller (PIC) Specifications
This section describes the DC and AC electrical specifications for the programmable interrupt controller
(PIC).
2.16.1 PIC DC specifications
Table 2-51 provides the DC electrical characteristics for the PIC interface.
Notes: 1. The min VIL and max VIH values are based on the min and max OVIN respective values found in
Table 2-2.
2. The symbol OVIN, in this case, represents the OVIN symbol referenced in Table 2-2.
eSDHC
tSHSCKR
External Clock VMVMVM
tSHSCK
tSHSCKF
VM = Midpoint Voltage (OVDD/2)
operational mode tSHSCKL tSHSCKH
VM = Midpoint Voltage (OVDD/2)
SD_CK
External Clock
SD_DAT/CMD
VM VM VM VM
Inputs
SD_DAT/CMD
Outputs
tSHSIVKH tSHSIXKH
tSHSKHOV
Table 2-51. PIC DC Electrical Characteristics (For Recommended Operating Conditions, see Table
2-2)
Parameter Symbol Min Max Unit Notes
Input high voltage VIH 2 –V (1)
Input low voltage VIL –0.8 V (1)
Input current (OVIN = 0V or OVIN = OVDD)I
IN –±40 µA (2)
Output high voltage (OVDD = min, IOH = –2 mA) VOH 2.4 –V –
Output low voltage (OVDD = min, IOL = 2 mA) VOL –0.4 V –
87
1066A–HIREL–07/11
e2v semiconductors SAS 2011
P4080
2.16.2 PIC AC Timing Specifications
Table 2-52 provides the PIC input and output AC timing specifications.
Note: 1. PIC inputs and outputs are asynchronous to any visible clock. PIC outputs should be synchronized
before use by any external synchronous logic. PIC inputs are required to be valid for at least tPIWID ns to
ensure proper operation when working in edge triggered mode.
2.17 JTAG Controller
This section describes the DC and AC electrical specifications for the IEEE 1149.1 (JTAG) interface.
2.17.1 JTAG DC Electrical Characteristics
Table 2-53 provides the JTAG DC electrical characteristics.
Notes: 1. The min VIL and max VIH values are based on the respective min and max OVIN values found in Table 2-
2.
2. The symbol VIN, in this case, represents the OVIN symbol found in Figure 1-2 on page 4.
Table 2-52. PIC Input AC Timing Specifications (At Recommended Operating Conditions at Table 2-
2 on page 49)
Characteristic Symbol Min Max Unit Notes
PIC inputs–minimum pulse width tPIWID 3 –SYSCLKs (1)
Table 2-53. JTAG DC Electrical Characteristics (For Recommended Operating Conditions, see Table
2-2 on page 49)
Parameter Symbol Min Max Unit Notes
Input high voltage VIH 2 –V (1)
Input low voltage VIL –0.8 V (1)
Input current (OVIN = 0V or OVIN = OVDD) IIN –±40 µA (2)
Output high voltage (OVDD = min, IOH = –2 mA) VOH 2.4 –V –
Output low voltage (OVDD = min, IOL = 2 mA) VOL –0.4 V –
88
1066A–HIREL–07/11
P4080
e2v semiconductors SAS 2011
2.17.2 JTAG AC Timing Specifications
Table 2-54 provides the JTAG AC timing specifications as defined in Figure 2-21 on page 88 through
Figure 2-24 on page 89.
Notes: 1. The symbols used for timing specifications follow the pattern t(first two letters of functional
block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For
example, tJTDVKH symbolizes JTAG device timing (JT) with respect to the time data input signals (D)
reaching the valid state (V) relative to the tJTG clock reference (K) going to the high (H) state or setup
time. Also, tJTDXKH symbolizes JTAG timing (JT) with respect to the time data input signals (D) reaching
the invalid state (X) relative to the tJTG clock reference (K) going to the high (H) state. Note that in
general, the clock reference symbol representation is based on three letters representing the clock of a
particular functional. For rise and fall times, the latter convention is used with the appropriate letter: R
(rise) or F (fall).
2. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
3. All outputs are measured from the midpoint voltage of the falling edge of tTCLK to the midpoint of the
signal in question. The output timings are measured at the pins. All output timings assume a purely
resistive 50Ω load. Time-of-flight delays must be added for trace lengths, vias, and connectors in the
system.
Figure 2-21 provides the AC test load for TDO and the boundary-scan outputs of the device.
Figure 2-21. AC Test Load for the JTAG Interface
Figure 2-22 provides the JTAG clock input timing diagram.
Figure 2-22. JTAG Clock Input Timing Diagram
Table 2-54. JTAG AC Timing Specifications (For Recommended Operating Conditions, see Table 2-2
on page 49)
Parameter Symbol(1) Min Max Unit Notes
JTAG external clock frequency of operation fJTG 0 33.3 MHz –
JTAG external clock cycle time tJTG 30 –ns –
JTAG external clock pulse width measured at 1.4V tJTKHKL 15 –ns –
JTAG external clock rise and fall times tJTGR/tJTGF 0 2 ns –
TRST assert time tTRST 25 –ns (2)
Input setup times tJTDVKH 4 –ns –
Input hold times tJTDXKH 10 – ns –
Output valid times tJTKLDV – 10 ns
(3)
Output hold times tJTKLDX 0 – ns
(3)
Output Z0 = 50ΩOVDD/2
RL = 50Ω
JTAG
tJTKHKL tJTGR
External Clock VMVMVM
tJTG tJTGF
VM = Midpoint Voltage (OVDD/2)
89
1066A–HIREL–07/11
e2v semiconductors SAS 2011
P4080
Figure 2-23 provides the TRST timing diagram.
Figure 2-23. TRST Timing Diagram
Figure 2-24 provides the boundary-scan timing diagram.
Figure 2-24. Boundary-Scan Timing Diagram
2.18 I2C
This section describes the DC and AC electrical characteristics for the I2C interface.
2.18.1 I2C DC Electrical Characteristics
Table 2-55 provides the DC electrical characteristics for the I2C interfaces.
Notes: 1. The min VIL and max VIH values are based on the respective min and max OVIN values found in Table 2-2.
2. Output voltage (open drain or open collector) condition = 3 mA sink current.
3. Refer to the P4080 QorIQ Integrated Multicore Communication Processor Family Reference Manual for information about
the digital filter used.
4. I/O pins obstruct the SDA and SCL lines if OVDD is switched off.
TRST
VM = Midpoint Voltage (OV /2)
VM VM
tTRST
VM = Midpoint Voltage (OV
DD
/2)
VM VM
t
JTDVKH
t
JTDXKH
Boundary
Data Outputs
JTAG
External Clock
Boundary
Data Inputs
Output Data Valid
t
JTKLDX
t
JTKLDV
Input
Data Valid
Table 2-55. I2C DC Electrical Characteristics (For Recommended Operating Conditions, see Table 2-2 on page 49)
Parameter Symbol Min Max Unit Notes
Input high voltage VIH 2 – V
(1)
Input low voltage VIL –0.8 V (1)
Output low voltage (OVDD = min, IOL = 2 mA) VOL 0 0.4 V (2)
Pulse width of spikes which must be suppressed by the input filter tI2KHKL 0 50 ns (3)
Input current each I/O pin (input voltage is between 0.1 × OVDD and
0.9 × OVDD(max) II –40 40 µA (4)
Capacitance for each I/O pin CI –10 pF –
90
1066A–HIREL–07/11
P4080
e2v semiconductors SAS 2011
2.18.2 I2C AC Electrical Specifications
Table 2-56 provides the AC timing parameters for the I2C interfaces.
Notes: 1. The symbols used for timing specifications herein follow the pattern t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tI2DVKH symbolizes I2C timing (I2) with
respect to the time data input signals (D) reaching the valid state (V) relative to the tI2C clock reference (K) going to the high
(H) state or setup time. Also, tI2SXKL symbolizes I2C timing (I2) for the time that the data with respect to the START condition
(S) went invalid (X) relative to the tI2C clock reference (K) going to the low (L) state or hold time. Also, tI2PVKH symbolizes I2C
timing (I2) for the time that the data with respect to the STOP condition (P) reaches the valid state (V) relative to the tI2C clock
reference (K) going to the high (H) state or setup time.
2. The requirements for I2C frequency calculation must be followed. Refer to Freescale application note AN2919, “Determining
the I2C Frequency Divider Ratio for SCL”.
3. As a transmitter, the device provides a delay time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL
signal) to bridge the undefined region of the falling edge of SCL to avoid unintended generation of a START or STOP
condition. When the P4080 acts as the I2C bus master while transmitting, it drives both SCL and SDA. As long as the load on
SCL and SDA are balanced, the P4080 does not generate an unintended START or STOP condition. Therefore, the 300 ns
SDA output delay time is not a concern. If, under some rare condition, the 300 ns SDA output delay time is required for the
P4080 as transmitter, refer to application note AN2919, “Determining the I2C Frequency Divider Ratio for SCL”.
4. The maximum tI2OVKL has to be met only if the device does not stretch the LOW period (tI2CL) of the SCL signal.
Table 2-56. I2C AC Timing Specifications (For Recommended Operating Conditions, see Table 2-2 on page 49).
Parameter Symbol(1) Min Max Unit Notes
SCL clock frequency fI2C 0 400 kHz
(2)
Low period of the SCL clock tI2CL 1.3 – µs –
High period of the SCL clock tI2CH 0.6 – µs –
Setup time for a repeated START condition tI2SVKH 0.6 – µs –
Hold time (repeated) START condition (after this period, the
first clock pulse is generated) tI2SXKL 0.6 – µs –
Data setup time tI2DVKH 100 – ns –
Data input hold time:
CBUS compatible masters
I2C bus devices
tI2DXKL –
0
–
–
µs (3)
Data output delay time tI2OVKL –0.9 µs(4)
Setup time for STOP condition tI2PVKH 0.6 – µs –
Bus free time between a STOP and START condition tI2KHDX 1.3 – µs –
Noise margin at the LOW level for each connected device
(including hysteresis) VNL 0.1 × OVDD –V –
Noise margin at the HIGH level for each connected device
(including hysteresis) VNH 0.2 × OVDD –V –
Capacitive load for each bus line Cb – 400 pF –
91
1066A–HIREL–07/11
e2v semiconductors SAS 2011
P4080
Figure 2-25 provides the AC test load for the I2C
Figure 2-25. I2C AC Test Load
Figure 2-26 shows the AC timing diagram for the I2C bus
Figure 2-26. I2C Bus AC Timing Diagram
2.19 GPIO
This section describes the DC and AC electrical characteristics for the GPIO interface. GPIO[0:29]
operate at OVDD =3.3V, while GPIO[30:31] operate at LVDD. Refer to Table 1-1 on page 8.
2.19.1 GPIO DC Electrical Characteristics
Table 2-57 provides the DC electrical characteristics for GPIO pins operating at LVDD or OVDD = 3.3V.
Notes: 1. The min VIL and max VIH values are based on the min and max OVIN respective values found in Table 2-
2.
2. The symbol VIN, in this case, represents the OVIN symbol referenced in Section 2.1.2 ”Recommended
Operating Conditions” on page 49.
Output Z0 = 50ΩOVDD/2
RL =50Ω
SrS
SDA
SCL
tI2SXKL
tI2CL
tI2CH
tI2DXKL,tI2OVKL
tI2DVKH
tI2SXKL
tI2SVKH
tI2KHKL
tI2PVKH
PS
tI2KHDX
Table 2-57. GPIO DC Electrical Characteristics (3.3V) (For Recommended Operating Conditions, see
Table 2-2 on page 49)
Parameter Symbol Min Max Unit Notes
Input high voltage VIH 2 – V
(1)
Input low voltage VIL –0.8 V (1)
Input current (OVIN = 0V or OVIN = OVDD)I
IN – ±40 µA (2)
Output high voltage (OVDD = min, IOH = –2 mA VOH 2.4 – V –
Output low voltage (OVDD = min, IOL = 2 mA) VOL –0.4 V –
92
1066A–HIREL–07/11
P4080
e2v semiconductors SAS 2011
Table 2-58 provides the DC electrical characteristics for GPIO pins operating at LVDD = 2.5V.
Notes: 1. The min VIL and max VIH values are based on the respective min and max LVIN values found in Table 2-
2.
2. The symbol VIN, in this case, represents the LVIN symbol referenced in Section 2.1.2 ”Recommended
Operating Conditions” on page 49.
Table 2-59 provides the DC electrical characteristics for GPIO pins operating at LVDD = 1.8V.
Notes: 1. The min VIL and max VIH values are based on the respective min and max LVIN values found in Table 2-
2.
2. The symbol VIN, in this case, represents the LVIN symbol referenced in Section 2.1.2 ”Recommended
Operating Conditions” on page 49.
2.19.2 GPIO AC Timing Specifications
Table 2-60 provides the GPIO input and output AC timing specifications.
Note: 1. GPIO inputs and outputs are asynchronous to any visible clock. GPIO outputs should be synchronized
before use by any external synchronous logic. GPIO inputs are required to be valid for at least tPIWID to
ensure proper operation.
Table 2-58. GPIO DC Electrical Characteristics (2.5V) (For Recommended Operating Conditions, see
Table 2-2 on page 49).
Parameter Symbol Min Max Unit Notes
Input high voltage VIH 1.7 – V (1)
Input low voltage VIL –0.7 V (1)
Input current (VIN = 0V or VIN = LVDD) IIN – ±40 µA (2)
Output high voltage (LVDD = min, IOH = –1 mA) VOH 2.0 – V –
Output low voltage (LVDD = min, IOL = 1 mA) VOL –0.4 V –
Table 2-59. GPIO DC Electrical Characteristics (1.8V) (For Recommended Operating Conditions, see
Table 2-2 on page 49).
Parameter Symbol Min Max Unit Notes
Input high voltage VIH 1.25 – V (1)
Input low voltage VIL –0.6 V (1)
Input current (VIN = 0V or VIN = LVDD) IIN –±40 µA (2)
Output high voltage (LVDD = min, IOH = –0.5 mA) VOH 1.35 – V –
Output low voltage (LVDD = min, IOL = 0.5 mA) VOL –0.4 V –
Table 2-60. GPIO Input AC Timing Specifications (For Recommended Operating Conditions, see
Table 2-2 on page 49)
Parameter Symbol Min Unit Notes
GPIO inputs–minimum pulse width tPIWID 20 ns
(1)
93
1066A–HIREL–07/11
e2v semiconductors SAS 2011
P4080
Figure 2-27 provides the AC test load for the GPIO.
Figure 2-27. GPIO AC Test Load
2.20 High-Speed Serial Interfaces (HSSI)
The P4080 features a Serializer/Deserializer (SerDes) interface to be used for high-speed serial
interconnect applications. The SerDes interface can be used for PCI Express, Serial RapidIO, XAUI,
Aurora and SGMII data transfers.
This section describes the common portion of SerDes DC electrical specifications: the DC requirement
for SerDes reference clocks. The SerDes data lane’s transmitter (Tx) and receiver (Rx) reference circuits
are also shown.
2.20.1 Signal Terms Definition
The SerDes utilizes differential signaling to transfer data across the serial link. This section defines terms
used in the description and specification of differential signals.
Figure 2-28 shows how the signals are defined. For illustration purposes only, one SerDes lane is used
in the description. Figure 2-28 on page 93 shows the waveform for either a transmitter output (SD_TXn
and SD_TXn) or a receiver input (SD_RXn and SD_RXn). Each signal swings between A volts and B
volts where A > B.
Figure 2-28. Differential Voltage Definitions for Transmitter or Receiver
Output Z0 = 50 (L/O)VDD
/
RL = 50
Differential Swing, VID or VOD = A – B
A Volts
B Volts
SD_TX
n
or
SD_RX
n
SD_TX
n
or
SD_RX
n
Differential Peak Voltage, VDIFFp = |A – B|
Differential Peak-Peak Voltage, VDIFFpp = 2 ×VDIFFp (not shown)
Vcm = (A + B)/2
94
1066A–HIREL–07/11
P4080
e2v semiconductors SAS 2011
Using this waveform, the definitions are as shown in the following list. To simplify the illustration, the
definitions assume that the SerDes transmitter and receiver operate in a fully symmetrical differential
signaling environment:
Single-Ended Swing
The transmitter output signals and the receiver input signals SD_TXn, SD_TXn, SD_RXn and
SD_RXn each have a peak-to-peak swing of A . B volts. This is also referred as each signal wire’s
single-ended swing.
Differential Output Voltage, VOD (or Differential Output Swing):
The differential output voltage (or swing) of the transmitter, VOD, is defined as the difference of the
two complimentary output voltages: VSD_TXn – VSD_TXn. The VOD value can be either positive or
negative.
Differential Input Voltage, VID (or Differential Input Swing):
The differential input voltage (or swing) of the receiver, VID, is defined as the difference of the two
complimentary input voltages: VSD_RXn – VSD_RXn. The VID value can be either positive or negative.
Differential Peak Voltage, VDIFFp
The peak value of the differential transmitter output signal or the differential receiver input signal is
defined as the differential peak voltage, VDIFFp = |A – B| volts.
Differential Peak-to-Peak, VDIFFp-p
Since the differential output signal of the transmitter and the differential input signal of the receiver
each range from A – B to –(A – B) volts, the peak-to-peak value of the differential transmitter
output signal or the differential receiver input signal is defined as differential peak-to-peak voltage,
VDIFFp-p = 2 × VDIFFp = 2 × |(A – B)| volts, which is twice the differential swing in amplitude, or twice of
the differential peak. For example, the output differential peak-peak voltage can also be calculated
as VTX-DIFFp-p = 2 × |VOD|.
Differential Waveform
The differential waveform is constructed by subtracting the inverting signal (SD_TXn, for example)
from the non-inverting signal (SD_TXn, for example) within a differential pair. There is only one sig-
nal trace curve in a differential waveform. The voltage represented in the differential waveform is not
referenced to ground. Refer to Figure 2-33 on page 99 as an example for differential waveform.
Common Mode Voltage, Vcm
The common mode voltage is equal to half of the sum of the voltages between each conductor of a
balanced interchange circuit and ground. In this example, for SerDes output,
Vcm_out = (VSD_TXn + VSD_TXn) ÷ 2 = (A + B) ÷ 2, which is the arithmetic mean of the two complimentary
output voltages within a differential pair. In a system, the common mode voltage may often differ
from one component’s output to the other’s input. It may be different between the receiver input and
driver output circuits within the same component. It is also referred to as the DC offset on some
occasions.
95
1066A–HIREL–07/11
e2v semiconductors SAS 2011
P4080
To illustrate these definitions using real values, consider the example of a current mode logic (CML)
transmitter that has a common mode voltage of 2.25V and outputs, TD and TD. If these outputs have
a swing from 2.0V to 2.5V, the peak-to-peak voltage swing of each signal (TD or TD) is 500 mV p-p,
which is referred to as the single-ended swing for each signal. Because the differential signaling
environment is fully symmetrical in this example, the transmitter output’s differential swing (VOD) has the
same amplitude as each signal’s single-ended swing. The differential output signal ranges between 500
mV and –500 mV.
In other words, VOD is 500 mV in one phase and .500 mV in the other phase. The peak differential
voltage (VDIFFp) is 500 mV. The peak-to-peak differential voltage (VDIFFp-p) is 1000 mV p-p.
2.20.2 SerDes Reference Clocks
The SerDes reference clock inputs are applied to an internal PLL whose output creates the clock used
by the corresponding SerDes lanes. The SerDes reference clocks inputs are SD_REF_CLK1 and
SD_REF_CLK1 for SerDes bank1, SD_REF_CLK3 and SD_REF_CLK3 for SerDes banks 2 and 3.
Note: SerDes bank 2 is driven internally by SD_REF_CLK3 and bank 3's PLL. SD_REF_CLK2 continues to clock
internal logic for bank 2 and therefore, SD_REF_CLK2 and SD_REF_CLK2 are still required when bank 2
is enabled. SD_REF_CLK3 is required when either bank 2 or bank 3 are enabled.
SerDes banks 1–3 may be used for various combinations of the following IP blocks based on the RCW
Configuration field
SRDS_PRTCL:
• SerDes bank 1: PEX1/2/3, sRIO1/2, SGMII, Aurora.
• SerDes bank 2: PEX3, SGMII, or XAUI.
• SerDes bank 3: SGMII, or XAUI.
The following sections describe the SerDes reference clock requirements and provide application
information.
2.20.2.1 SerDes Reference Clock Receiver Characteristics
Figure 2-29 shows a receiver reference diagram of the SerDes reference clocks.
Figure 2-29. Receiver of SerDes Reference Clocks
Input
Amp
50Ω
50Ω
SD_REF_CLK
n
SD_REF_CLK
n
96
1066A–HIREL–07/11
P4080
e2v semiconductors SAS 2011
The characteristics of the clock signals are as follows:
• The SerDes transceivers core power supply voltage requirements (SVDD) are as specified in Section
2.1.2 ”Recommended Operating Conditions” on page 49.
• The SerDes reference clock receiver reference circuit structure is as follows:
– The SD_REF_CLKn and SD_REF_CLKn are internally AC-coupled differential inputs as
shown in Figure 2-29 on page 95. Each differential clock input (SD_REF_CLKn or
SD_REF_CLKn) has on-chip 50Ω termination to SGND followed by on-chip AC-coupling.
– The external reference clock driver must be able to drive this termination.
– The SerDes reference clock input can be either differential or single-ended. Refer to the
differential mode and single-ended mode descriptions below for detailed requirements.
• The maximum average current requirement also determines the common mode voltage range.
– When the SerDes reference clock differential inputs are DC coupled externally with the clock
driver chip, the maximum average current allowed for each input pin is 8 mA. In this case, the
exact common mode input voltage is not critical as long as it is within the range allowed by
the maximum average current of 8 mA because the input is AC-coupled on-chip.
– This current limitation sets the maximum common mode input voltage to be less than 0.4V
(0.4V ÷ 50 = 8 mA) while the minimum common mode input level is 0.1V above SGND. For
example, a clock with a 50/50 duty cycle can be produced by a clock driver with output driven
by its current source from 0 mA to 16 mA (0–0.8V), such that each phase of the differential
input has a single-ended swing from 0V to 800 mV with the common mode voltage at 400
mV.
– If the device driving the SD_REF_CLKn and SD_REF_CLKn inputs cannot drive 50Ω to
SGND DC or the drive strength of the clock driver chip exceeds the maximum input current
limitations, it must be AC-coupled off-chip.
• The input amplitude requirement is described in detail in the following sections.
2.20.2.2 DC Level Requirement for SerDes Reference Clocks
The DC level requirement for the SerDes reference clock inputs is different depending on the signaling
mode used to connect the clock driver chip and SerDes reference clock inputs, as described below:
• Differential Mode
– The input amplitude of the differential clock must be between 400 mV and 1600 mV
differential peak-peak (or between 200 mV and 800 mV differential peak). In other words,
each signal wire of the differential pair must have Input a single-ended swing of less than 800
mV and greater than 200 mV. This requirement is the same for both external DC-coupled or
AC-coupled connection.
– For an external DC-coupled connection, as described in Section 2.20.2.1 ”SerDes Reference
Clock Receiver Characteristics” on page 95 the maximum average current requirements sets
the requirement for average voltage (common mode voltage) as between 100 mV and 400
mV. Figure 2-30 shows the SerDes reference clock input requirement for DC-coupled
connection scheme.
97
1066A–HIREL–07/11
e2v semiconductors SAS 2011
P4080
Figure 2-30. Differential Reference Clock Input DC Requirements (External DC-Coupled)
• For an external AC-coupled connection, there is no common mode voltage requirement for the clock
driver. Because the external AC-coupling capacitor blocks the DC level, the clock driver and the
SerDes reference clock receiver operate in different common mode voltages. The SerDes reference
clock receiver in this connection scheme has its common mode voltage set to SGND. Each signal
wire of the differential inputs is allowed to swing below and above the common mode voltage (SGND).
Figure 2-31 shows the SerDes reference clock input requirement for AC-coupled connection scheme.
Figure 2-31. Differential Reference Clock Input DC Requirements (External AC-Coupled)
• Single-Ended Mode
– The reference clock can also be single-ended. The SD_REF_CLKn input amplitude (single-
ended swing) must be between 400 mV and 800 mV peak-peak (from VMIN to VMAX) with
SD_REF_CLKn either left unconnected or tied to ground.
– The SD_REF_CLKn input average voltage must be between 200 and 400 mV. Figure 2-32
shows the SerDes reference clock input requirement for single-ended signaling mode.
– To meet the input amplitude requirement, the reference clock inputs may need to be DC- or
AC-coupled externally. For the best noise performance, the reference of the clock could be
DC- or AC-coupled into the unused phase (SD_REF_CLKn) through the same source
impedance as the clock input (SD_REF_CLKn) in use.
SD_REF_CLK
n
SD_REF_CLK
n
Vmax < 800 mV
Vmin > 0V
100 mV <Vcm < 400 mV
200 mV < Input Amplitude or Differential Peak < 800 mV
SD_REF_CLK
n
SD_REF_CLK
n
Vcm
200 mV < Input Amplitude or Differential Peak < 800 mV
Vmax <Vcm + 400 mV
Vmin > Vcm – 400 mV
98
1066A–HIREL–07/11
P4080
e2v semiconductors SAS 2011
Figure 2-32. Single-Ended Reference Clock Input DC Requirements
2.20.2.3 AC Requirements for SerDes Reference Clocks
Table 2-61 lists AC requirements for the PCI Express, SGMII, Serial RapidIO and Aurora SerDes
reference clocks to be guaranteed by the customer’s application design.
Notes: 1. Caution: Only 100 and 125 have been tested. In-between values do not work correctly with the rest of the system.
2. Limits from PCI Express CEM Rev 2.0
3. Measured from .200 mV to +200 mV on the differential waveform (derived from SD_REF_CLKn minus SD_REF_CLKn). The
signal must be monotonic through the measurement region for rise and fall time. The 400 mV measurement window is
centered on the differential zero crossing. See Figure 2-33 on page 99.
4. Measurement taken from differential waveform
5. Measurement taken from single-ended waveform
6. Matching applies to rising edge for SD_REF_CLKn and falling edge rate for SD_REF_CLKn. It is measured using a 200 mV
window centered on the median cross point where SD_REF_CLKn rising meets SD_REF_CLKn falling. The median cross
point is used to calculate the voltage thresholds that the oscilloscope uses for the edge rate calculations. The rise edge rate
of SD_REF_CLKn should be compared to the fall edge rate of SD_REF_CLKn, the maximum allowed difference should not
exceed 20% of the slowest edge rate. See Figure 2-34.
SD_REF_CLK
n
SD_REF_CLK
n
400 mV < SD_REF_CLK
n
Input Amplitude < 800 mV
0V
Table 2-61. SD_REF_CLKn and SD_REF_CLKn Input Clock Requirements (At Recommended Operating Conditions
with SVDD = 1.0V)
Parameter Symbol Min Typ Max Unit Notes
SD_REF_CLK/SD_REF_CLK frequency range tCLK_REF – 100/125 – MHz
(1)
SD_REF_CLK/SD_REF_CLK clock frequency
tolerance tCLK_TOL –350 – 350 ppm –
SD_REF_CLK/SD_REF_CLK reference clock duty
cycle (measured at 1.6V) tCLK_DUTY 40 50 60 % –
SD_REF_CLK/SD_REF_CLK max deterministic peak-
peak jitter at 10-6 BER tCLK_DJ – – 42 ps –
SD_REF_CLK/SD_REF_CLK total reference clock
jitter at 10-6 BER (peak-to-peak jitter at refClk input) tCLK_TJ – – 86 ps
(2)
SD_REF_CLK/SD_REF_CLK rising/falling edge rate tCLKRR/tCLKFR 1 – 4 V/ns
(3)
Differential input high voltage VIH 200 – – mV
(4)
Differential input low voltage VIL – – –200 mV
(4)
Rising edge rate (SD_REF_CLKn) to falling edge rate
(SD_REF_CLKn) matching
Rise-Fall
Matching ––20 %
(5)(6)
99
1066A–HIREL–07/11
e2v semiconductors SAS 2011
P4080
Figure 2-33. Differential Measurement Points for Rise and Fall Time
Figure 2-34. Single-Ended Measurement Points for Rise and Fall Time Matching
2.20.2.4 Spread Spectrum Clock
SD_REF_CLK1/SD_REF_CLK1 were designed to work with a spread spectrum clock (+0 to 0.5%
spreading at 30–33 kHz rate is allowed), assuming both ends have same reference clock. For better
results, a source without significant unintended modulation should be used.
SD_REF_CLK2/SD_REF_CLK2 were designed to work with a spread spectrum clock (+0 to 0.5%
spreading at 30–33 kHz rate is allowed), assuming both ends have same reference clock and the
industry protocol specifications supports it. For better results, a source without significant unintended
modulation should be used.
SD_REF_CLK3/SD_REF_CLK3 are not intended to be used with, and should not be clocked by, a
spread spectrum clock source.
2.20.3 SerDes Transmitter and Receiver Reference Circuits
Figure 2-35 shows the reference circuits for SerDes data lane’s transmitter and receiver.
Figure 2-35. SerDes Transmitter and Receiver Reference Circuits
VIH = +200 mV
VIL = –200 mV
0.0 V
SD_REF_CLK
n
–
SD_REF_CLK
n
Fall Edge RateRise Edge Rate
VCROSS MEDIAN
VCROSS MEDIAN -100 mV
VCROSS MEDIAN +100 mV
VCROSS MEDIAN
TFALL TRISE
50 W
50 W Receiver
Transmitter
SD_TXn
SD_TXnSD_RXn
SD_RXn
50 W
50 W
100
1066A–HIREL–07/11
P4080
e2v semiconductors SAS 2011
The DC and AC specification of SerDes data lanes are defined in each interface protocol section below
based on the application usage:
•Section 2.20.4 ”PCI Express” on page 100
•Section 2.20.5 ”Serial RapidIO (sRIO)” on page 107
•Section 2.20.6 ”XAUI” on page 111
•Section 2.20.7 ”Aurora” on page 114
•Section 2.20.8 ”SGMII Interface” on page 115
Note that external AC-coupling capacitor is required for the above serial transmission protocols per the
protocol’s standard requirements.
2.20.4 PCI Express
This section describes the clocking dependencies, DC and AC electrical specifications for the PCI
Express bus.
2.20.4.1 Clocking Dependencies
The ports on the two ends of a link must transmit data at a rate that is within 600 parts per million (ppm)
of each other at all times. This is specified to allow bit rate clock sources with a ±300 ppm tolerance.
2.20.4.2 PCI Express Clocking Requirements for SD_REF_CLKn and SD_REF_CLKn
This section specifies PCI Express requirements for SD_REF_CLKn and SD_REF_CLKn, where n = [1–
3]. SerDes banks 1–2 may be used for various SerDes PCI Express configurations based on the RCW
Configuration field SRDS_PRTCL. PCI Express is not supported on SerDes bank 3. On silicon rev 2.0,
SD_REF_CLK3 and SD_REF_CLK3 must be supplied to use PCI Express on SerDes bank 2.
For more information on these specifications, see Section 2.20.2 ”SerDes Reference Clocks” on page
95.
101
1066A–HIREL–07/11
e2v semiconductors SAS 2011
P4080
2.20.4.3 PCI Express DC Physical Layer Specifications
This section contains the DC specifications for the physical layer of PCI Express on this device.
2.20.4.3.1 PCI Express DC Physical Layer Transmitter Specifications
This section discusses the PCI Express DC physical layer transmitter specifications for 2.5 GT/s and
5 GT/s.
Table 2-62 defines the PCI Express 2.0 (2.5 GT/s) DC specifications for the differential output at all
transmitters. The parameters are specified at the component pins.
Note: 1. Measured at the package pins with a test load of 50Ω to GND on each pin.
Table 2-63 defines the PCI Express 2.0 (5 GT/s) DC specifications for the differential output at all
transmitters. The parameters are specified at the component pins.
Note: 1. Measured at the package pins with a test load of 50Ω to GND on each pin.
Table 2-62. PCI Express 2.0 (2.5 GT/s) Differential Transmitter (Tx) Output DC Specifications (At Recommended
Operating Conditions with XVDD = 1.5V or 1.8V)
Parameter Symbol Min Typical Max Units Notes
Differential peak-to-peak
output voltage VTX-DIFFp-p 800 1000 1200 mV VTX-DIFFp-p = 2 × |VTX-D+ – VTX-D-| See Note (1).
De-emphasized differential
output voltage (ratio) VTX-DE-RATIO 3.0 3.5 4.0 dB
Ratio of the VTX-DIFFp-p of the second and following
bits after a transition divided by the VTX-DIFFp-p of the
first bit after a transition. See Note (1).
DC differential Tx impedance ZTX-DIFF-DC 80 100 120 Ω Tx DC differential mode low Impedance
Transmitter DC impedance ZTX-DC 40 50 60 Ω Required Tx D+ as well as D– DC Impedance during
all states
Table 2-63. PCI Express 2.0 (5 GT/s) Differential Transmitter (Tx) Output DC Specifications (At Recommended
Operating Conditions with XVDD = 1.5V or 1.8V)
Parameter Symbol Min Typical Max Units Notes
Differential peak-to-peak output voltage VTX-DIFFp-p 800 1000 1200 mV VTX-DIFFp-p = 2 × |VTX-D+ – VTX-D-| See Note (1).
Low Power differential peak-to-peak
output voltage VTX-DIFFp-p_low 400 500 1200 mV VTX-DIFFp-p = 2 × |VTX-D+ – VTX-D-| See Note (1).
De-emphasized differential output
voltage (ratio) VTX-DE-RATIO-3.5dB 3.0 3.5 4.0 dB
Ratio of the VTX-DIFFp-p of the second and
following bits after a transition divided by the
VTX-DIFFp-p of the first bit after a transition. See
Note (1).
De-emphasized differential output
voltage (ratio) VTX-DE-RATIO-6.0dB 5.5 6.0 6.5 dB
Ratio of the VTX-DIFFp-p of the second and
following bits after a transition divided by the
VTX-DIFFp-p of the first bit after a transition. See
Note (1).
DC differential Tx impedance ZTX-DIFF-DC 80 100 120 Ω Tx DC differential mode low impedance
Transmitter DC Impedance ZTX-DC 40 50 60 Ω Required Tx D+ as well as D– DC impedance
during all states
102
1066A–HIREL–07/11
P4080
e2v semiconductors SAS 2011
2.20.4.4 PCI Express DC Physical Layer Receiver Specifications
This section discusses the PCI Express DC physical layer receiver specifications 2.5 GT/s, and 5 GT/s
Table 2-64 defines the DC specifications for the PCI Express 2.0 (2.5 GT/s) differential input at all
receivers. The parameters are specified at the component pins.
Notes: 1. Measured at the package pins with a test load of 50Ω to GND on each pin.
2. Impedance during all LTSSM states. When transitioning from a fundamental reset to detect (the initial state of the LTSSM)
there is a 5 ms transition time before receiver termination values must be met on all unconfigured lanes of a port.
3. The Rx DC common mode impedance that exists when no power is present or fundamental reset is asserted. This helps
ensure that the receiver detect circuit does not falsely assume a receiver is powered on when it is not. This term must be
measured at 300 mV above the Rx ground.
Table 2-65 defines the DC specifications for the PCI Express 2.0 (5 GT/s) differential input at all
receivers (RXs). The parameters are specified at the component pins.
Notes: 1. Measured at the package pins with a test load of 50Ω to GND on each pin.
2. Impedance during all LTSSM states. When transitioning from a fundamental reset to detect (the initial state of the LTSSM)
there is a 5 ms transition time before receiver termination values must be met on all unconfigured lanes of a port.
3. The Rx DC common mode impedance that exists when no power is present or fundamental reset is asserted. This helps
ensure that the receiver detect circuit does not falsely assume a receiver is powered on when it is not. This term must be
measured at 300 mV above the Rx ground.
Table 2-64. PCI Express 2.0 (2.5 GT/s) Differential Receiver (Rx) Input DC Specifications (At Recommended Operating
Conditions with XVDD = 1.5V or 1.8V)
Parameter Symbol Min Typical Max Units Notes
Differential input peak-to-peak
voltage VRX-DIFFp-p 120 1000
120
0 mV VRX-DIFFp-p = 2 × |VRX-D+ – VRX-D-|
See Note (1).
DC differential input impedance ZRX-DIFF-DC 80 100 120 ΩRx DC differential mode impedance. See Note (2)
DC input impedance ZRX-DC 40 50 60 Ω Required Rx D+ as well as D– DC Impedance
(50 ±20% tolerance). See Notes (1) and (2).
Powered down DC input
impedance ZRX-HIGH-IMP-DC 50 ––kΩ
Required Rx D+ as well as D– DC Impedance when
the receiver terminations do not have power.
See Note (3).
Electrical idle detect threshold VRX-IDLE-DET-DIFFp-p 65 –175 mV
VRX-IDLE-DET-DIFFp-p = 2 × |VRX-D+ – VRX-D–| Measured
at the package pins of the receiver
Table 2-65. PCI Express 2.0 (5 GT/s) Differential Receiver (Rx) Input DC Specifications (At Recommended Operating
Conditions with XVDD = 1.5V or 1.8V)
Parameter Symbol Min Typical Max Units Notes
Differential input peak-to-peak
voltage VRX-DIFFp-p 120 1000 1200 V
VRX-DIFFp-p = 2 × |VRX-D+ – VRX-D–|
See Note (1).
DC differential input impedance ZRX-DIFF-DC 80 100 120 Ω Rx DC Differential mode impedance.
See Note (2)
DC input impedance ZRX-DC 40 50 60 Ω Required Rx D+ as well as D– DC Impedance
(50 ±20% tolerance). See Notes (1) and (2).
Powered down DC input impedance ZRX-HIGH-IMP-DC 50 ––kΩ
Required Rx D+ as well as D– DC Impedance
when the Receiver terminations do not have
power. See Note (3).
Electrical idle detect threshold VRX-IDLE-DET-DIFFp-p 65 –175 mV
VRX-IDLE-DET-DIFFp-p = 2 × |VRX-D+ –VRX-D–|
Measured at the package pins of the receiver
103
1066A–HIREL–07/11
e2v semiconductors SAS 2011
P4080
2.20.4.5 PCI Express AC Physical Layer Specifications
This section contains the DC specifications for the physical layer of PCI Express on this device.
2.20.4.5.1 PCI Express AC Physical Layer Transmitter Specifications
This section discusses the PCI Express AC physical layer transmitter specifications 2.5 GT/s, and 5
GT/s.
Table 2-66 defines the PCI Express 2.0 (2.5 GT/s) AC specifications for the differential output at all
transmitters (TXs). The parameters are specified at the component pins. The AC timing specifica-
tions do not include RefClk jitter.
Notes: 1. No test load is necessarily associated with this value.
2. Specified at the measurement point into a timing and voltage test load as shown in Figure 2-3 on page 106 and measured
over any 250 consecutive Tx UIs.
3. A TTX-EYE = 0.75 UI provides for a total sum of deterministic and random jitter budget of TTX-MAX-JITTER = 0.25 UI for the
transmitter collected over any 250 consecutive Tx UIs. The TTX-EYE-MEDIAN-to-MAX-JITTER median is less than half of the total Tx
jitter budget collected over any 250 consecutive Tx UIs. It should be noted that the median is not the same as the mean. The
jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed to
the averaged time value.
4. P4080 SerDes transmitter does not have CTX built-in. An external AC coupling capacitor is required.
Table 2-66. PCI Express 2.0 (2.5 GT/s) Differential Transmitter (Tx) Output AC Specifications (At Recommended
Operating Conditions with XVDD = 1.5V or 1.8V)
Parameter Symbol Min Typical Max Units Notes
Unit interval UI 399.88 400 400.12 ps
Each UI is 400 ps ± 300 ppm. UI does not account
for spread spectrum clock dictated variations. See
Note (1).
Minimum Tx eye width TTX-EYE 0.75 ––UI
The maximum transmitter jitter can be derived as
TTX-MAX-JITTER = 1 – TTX-EYE = 0.25 UI. Does not
include spread spectrum or RefCLK jitter. Includes
device random jitter at 10-12. See Notes (2) and (3).
Maximum time between the
jitter median and maximum
deviation from the median.
TTX-EYE-MEDIAN-to-
MAX-JITTER ––0.125 UI
Jitter is defined as the measurement variation of the
crossing points (VTX-DIFFp-p = 0V) in relation to a
recovered Tx UI. A recovered Tx UI is calculated
over 3500 consecutive unit intervals of sample data.
Jitter is measured using all edges of the 250
consecutive UI in the center of the 3500 UI used for
calculating the Tx UI. See Notes (2) and (3).
AC coupling capacitor CTX 75 –200 nF
All transmitters must be AC coupled. The AC
coupling is required either within the media or within
the transmitting component itself. See Note (4).
104
1066A–HIREL–07/11
P4080
e2v semiconductors SAS 2011
Table 2-67 defines the PCI Express 2.0 (5 GT/s) AC specifications for the differential output at all
transmitters. The parameters are specified at the component pins. The AC timing specifications do not
include RefClk jitter.
Notes: 1. No test load is necessarily associated with this value.
2. Specified at the measurement point into a timing and voltage test load as shown in Figure 2-3 on page 106 and measured
over any 250 consecutive Tx UIs.
3. A TTX-EYE = 0.75 UI provides for a total sum of deterministic and random jitter budget of TTX-MAX-JITTER = 0.25 UI for the
Transmitter collected over any 250 consecutive Tx UIs. The TTX-EYE-MEDIAN-to-MAX-JITTER median is less than half of the total Tx
jitter budget collected over any 250 consecutive Tx UIs. It should be noted that the median is not the same as the mean. The
jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed to
the averaged time value.
4. P4080 SerDes transmitter does not have CTX built-in. An external AC coupling capacitor is required.
Table 2-67. PCI Express 2.0 (5 GT/s) Differential Transmitter (Tx) Output AC Specifications (At Recommended
Operating Conditions with XVDD = 1.5V or 1.8V)
Parameter Symbol Min Typical Max Units Notes
Unit Interval UI 199.94 200.00 200.06 ps
Each UI is 400 ps ± 300 ppm. UI does not account
for spread spectrum clock dictated variations. See
Note (1).
Minimum Tx eye width TTX-EYE 0.75 ––UI
The maximum Transmitter jitter can be derived as:
TTX-MAX-JITTER = 1 – TTX-EYE = 0.25 UI.
See Notes (2) and (3).
Tx RMS deterministic jitter > 1.5 MHz TTX-HF-DJ-DD ––0.15 ps –
Tx RMS deterministic jitter < 1.5 MHz TTX-LF-RMS –3.0 –ps Reference input clock RMS jitter (< 1.5 MHz) at pin
< 1 ps
AC coupling capacitor CTX 75 –200 nF
All transmitters must be AC coupled. The AC
coupling is required either within the media or
within the transmitting component itself.
See Note (4).
105
1066A–HIREL–07/11
e2v semiconductors SAS 2011
P4080
2.20.4.5.2 PCI Express AC Physical Layer Receiver Specifications
This section discusses the PCI Express AC physical layer receiver specifications 2.5 GT/s, and 5
GT/s.
Table 2-68 defines the AC specifications for the PCI Express 2.0 (2.5 GT/s) differential input at all
receivers. The parameters are specified at the component pins. The AC timing specifications do not
include RefClk jitter.
Notes: 1. No test load is necessarily associated with this value.
2. Specified at the measurement point and measured over any 250 consecutive UIs. The test load in Figure 2-3 on page 106
should be used as the Rx device when taking measurements. If the clocks to the Rx and Tx are not derived from the same
reference clock, the Tx UI recovered from 3500 consecutive UI must be used as a reference for the eye diagram.
3. A TRX-EYE = 0.40 UI provides for a total sum of 0.60 UI deterministic and random jitter budget for the Transmitter and
interconnect collected any 250 consecutive UIs. The TRX-EYE-MEDIAN-to-MAX-JITTER specification ensures a jitter distribution in
which the median and the maximum deviation from the median is less than half of the total. UI jitter budget collected over
any 250 consecutive Tx UIs. It should be noted that the median is not the same as the mean. The jitter median describes the
point in time where the number of jitter points on either side is approximately equal as opposed to the averaged time value.
If the clocks to the Rx and Tx are not derived from the same reference clock, the Tx UI recovered from 3500 consecutive UI
must be used as the reference for the eye diagram.
4. It is recommended that the recovered Tx UI is calculated using all edges in the 3500 consecutive UI interval with a fit
algorithm using a minimization merit function. Least squares and median deviation fits have worked well with experimental
and simulated data.
Table 2-68. PCI Express 2.0 (2.5 GT/s) Differential Receiver (Rx) Input AC Specifications (At Recommended Operating
Conditions with XVDD = 1.5V or 1.8V)
Parameter Symbol Min Typical Max Units Notes
Unit Interval UI 399.88 400.00 400.12 ps
Each UI is 400 ps ± 300 ppm. UI does not
account for spread spectrum clock dictated
variations. See Note (1).
Minimum receiver eye width TRX-EYE 0.4 ––UI
The maximum interconnect media and
Transmitter jitter that can be tolerated by the
Receiver can be derived as TRX-MAX-JITTER =
1 – TRX-EYE = 0.6 UI.
See Notes (2) and (3).
Maximum time between the
jitter median and maximum
deviation from the median.
TRX-EYE-MEDIAN-to-MAX-JITTER ––0.3 UI
Jitter is defined as the measurement
variation of the crossing points (VRX-DIFFp-p =
0V) in relation to a recovered Tx UI. A
recovered Tx UI is calculated over 3500
consecutive unit intervals of sample data.
Jitter is measured using all edges of the 250
consecutive UI in the center of the 3500 UI
used for calculating the Tx UI.
See Notes (2), (3), and (4).
106
1066A–HIREL–07/11
P4080
e2v semiconductors SAS 2011
Table 2-69 defines the AC specifications for the PCI Express 2.0 (5 GT/s) differential input at all
receivers (RXs). The parameters are specified at the component pins. The AC timing specifications do
not include RefClk jitter.
Note: 1. No test load is necessarily associated with this value.
2.20.4.6 Test and Measurement Load
The AC timing and voltage parameters must be verified at the measurement point. The package pins of
the device must be connected to the test/measurement load within 0.2 inches of that load, as shown in
Figure 2-3.
Note: The allowance of the measurement point to be within 0.2 inches of the package pins is meant to
acknowledge that package/board routing may benefit from D+ and D. not being exactly matched in length at
the package pin boundary. If the vendor does not explicitly state where the measurement point is located,
the measurement point is assumed to be the D+ and D. package pins.
Figure 2-3. Test/Measurement Load
Table 2-69. PCI Express 2.0 (5 GT/s) Differential Receiver (Rx) Input AC Specifications (At Recommended Operating
Conditions with XVDD = 1.5V or 1.8V)
Parameter Symbol Min Typical Max Units Notes
Unit Interval UI 199.40 200.00 200.06 ps
Each UI is 400 ps ±300 ppm. UI does not
account for spread spectrum clock dictated
variations. See Note (1).
Max Rx inherent timing error TRX-TJ-CC ––0.4 UI
The maximum inherent total timing error for
common RefClk Rx architecture
Maximum time between the jitter median
and maximum deviation from the median TRX-TJ-DC ––0.34 UI Max Rx inherent total timing error
Max Rx inherent deterministic timing error TRX-DJ-DD-CC ––0.30 UI
The maximum inherent deterministic timing
error for common RefClk Rx architecture
Max Rx inherent deterministic timing error TRX-DJ-DD-DC ––0.24 UI
The maximum inherent deterministic timing
error for common RefClk Rx architecture
TX
Silicon
+ Package
D+ Package
Pin
D– Package
Pin
C = CTX
C = CTX
R = 50ΩR = 50Ω
107
1066A–HIREL–07/11
e2v semiconductors SAS 2011
P4080
2.20.5 Serial RapidIO (sRIO)
This section describes the DC and AC electrical specifications for the Serial RapidIO interface of the LP-
Serial physical layer. The electrical specifications cover both single and multiple-lane links. Two
transmitters (short run and long run) and a single receiver are specified for each of two baud rates: 2.50
and 3.125 GBaud.
Two transmitter specifications allow for solutions ranging from simple board-to-board interconnect to
driving two connectors across a backplane. A single receiver specification is given that accepts signals
from both the short run and long run transmitter specifications.
The short run transmitter should be used mainly for chip-to-chip connections on either the same printed
circuit board or across a single connector. This covers the case where connections are made to a
mezzanine (daughter) card. The minimum swings of the short run specification reduce the overall power
used by the transceivers.
The long run transmitter specifications use larger voltage swings that are capable of driving signals
across backplanes. This allows a user to drive signals across two connectors and a backplane. The
specifications allow a distance of at least 50 cm at all baud rates.
All unit intervals are specified with a tolerance of ±100 ppm. The worst case frequency difference
between any transmit and receive clock will be 200 ppm.
To ensure interoperability between drivers and receivers of different vendors and technologies, AC
coupling at the receiver input must be used.
2.20.5.1 Signal Definitions
This section defines the terms used in the description and specification of the differential signals used by
the LP-Serial links.
Figure 2-4 shows how the signals are defined. The figures show waveforms for either a transmitter output
(TD and TD) or a receiver input (RD and RD). Each signal swings between A volts and B volts where A >
B. Using these waveforms, the definitions are as follows:
• The transmitter output signals and the receiver input signals.TD, TD, RD, and RD – each have a peak-
to-peak swing of A – B volts.
• The differential output signal of the transmitter, VOD, is defined as VTD – VTD
• The differential input signal of the receiver, VID, is defined as VRD – VRD
• The differential output signal of the transmitter and the differential input signal of the receiver each
range from A – B to –(A – B) volts
• The peak value of the differential transmitter output signal and the differential receiver input signal is
A - B volts.
• The peak-to-peak value of the differential transmitter output signal and the differential receiver input
signal is 2 × (A – B) volts.
108
1066A–HIREL–07/11
P4080
e2v semiconductors SAS 2011
Figure 2-4. Differential Peak-Peak Voltage of Transmitter or Receiver
To illustrate these definitions using real values, consider the case of a CML (current mode logic)
transmitter that has a common mode voltage of 2.25V, and each of its outputs, TD and TD, has a swing
that goes between 2.5V and 2.0V. Using these values, the peak-to-peak voltage swing of the signals TD
and TD is 500 mV p-p. The differential output signal ranges between 500 mV and –500 mV. The peak
differential voltage is 500 mV. The peak-to-peak differential voltage is 1000 mV p-p.
2.20.5.2 Equalization
With the use of high-speed serial links, the interconnect media causes degradation of the signal at the
receiver and produces effects such as inter-symbol interference (ISI) or data-dependent jitter. This loss
can be large enough to degrade the eye opening at the receiver beyond what is allowed in the
specification. To negate a portion of these effects, equalization can be used. The most common
equalization techniques that can be used are as follows:
• Pre-emphasis on the transmitter
• A passive high-pass filter network placed at the receiver, often referred to as passive equalization
• The use of active circuits in the receiver, often referred to as adaptive equalization
2.20.5.3 Serial RapidIO Clocking Requirements for SD_REF_CLKn and SD_REF_CLKn
This section specifies Serial RapidIO DC requirements for SD_REF_CLK1 and SD_REF_CLK1. Only
SerDes bank 1 may beused for various SerDes Serial RapidIO configurations based on the RCW
Configuration field SRDS_PRTCL. Serial RapidIO is not supported on SerDes banks 2–3.
For more information on these specifications, see Section 2.20.2 ”SerDes Reference Clocks” on page
95.
2.20.5.4 DC Requirements for Serial RapidIO
This section explains the DC requirements for the Serial RapidIO interface.
Differential Peak-Peak = 2 × (A – B)
A Volts TD or RD
TD or RD
B Volts
109
1066A–HIREL–07/11
e2v semiconductors SAS 2011
P4080
2.20.5.4.1 DC Serial RapidIO Timing Transmitter Specifications
LP-Serial transmitter electrical and timing specifications are stated in the text and tables of this section.
The differential return loss, S11, of the transmitter in each case shall be better than the following:
• –10 dB for (Baud Frequency) ÷ 10 < Freq(f) < 625 MHz
• –10 dB + 10log(f ÷ 625 MHz) dB for 625 MHz ≤Freq(f) ≤ Baud Frequency
The reference impedance for the differential return loss measurements is 100Ω resistive. Differential
return loss includes contributions from on-chip circuitry, chip packaging, and any off-chip components
related to the driver. The output impedance requirement applies to all valid output levels.
It is recommended that the 20%–80% rise/fall time of the transmitter, as measured at the transmitter
output, have a minimum value 60 ps in each case.
It is recommended that the timing skew at the output of an LP-Serial transmitter between the two signals
that comprise a differential pair not exceed 20 ps at 2.50 GBaud and 15 ps at 3.125 GBaud.
Table 2-70 defines the transmitter DC specifications for Serial RapidIO.
Note: 1. Voltage relative to COMMON of either signal comprising a differential pair.
2.20.5.4.2 DC Serial RapidIO Receiver Specifications
LP-Serial receiver electrical and timing specifications are stated in the text and tables of this section.
Receiver input impedance results in a differential return loss better than 10 dB and a common mode
return loss better than 6 dB from 100 MHz to (0.8) × (Baud Frequency). This includes contributions from
on-chip circuitry, the chip package, and any off-chip components related to the receiver. AC coupling
components are included in this requirement. The reference impedance for return loss measurements is
100Ω resistive for differential return loss and 25Ω resistive for common mode.
Table 2-71 defines the receiver DC specifications for Serial RapidIO.
Note: 1. Measured at receiver.
Table 2-70. sRIO Transmitter DC Timing Specifications.2.5 GBaud, 3.125 GBaud (At Recommended
Operating Conditions with XVDD = 1.5V or 1.8V)
Parameter Symbol Min Typical Max Units Notes
Output Voltage, VO –0.40 – 2.30 V (1)
Long-run differential output voltage VDIFFPP 800 – 1600 mV p-p –
Short-run differential output voltage VDIFFPP 500 – 1000 mV p-p –
Table 2-71. Serial RapidIO Receiver DC Timing Specifications.2.5 GBaud, 3.125 GBaud (At
Recommended Operating Conditions with XVDD = 1.5V or 1.8V)
Parameter Symbol Min Typical Max Units Notes
Differential input voltage VIN 200 – 1600 mV p-p
(1)
110
1066A–HIREL–07/11
P4080
e2v semiconductors SAS 2011
2.20.5.5 AC Requirements for Serial RapidIO
This section explains the AC requirements for the Serial RapidIO interface.
2.20.5.5.1 AC Requirements for Serial RapidIO Transmitter
Table 2-72 defines the transmitter AC specifications for the Serial RapidIO. The AC timing specifications
do not include RefClk jitter.
Table 2-73 defines the receiver AC specifications for Serial RapidIO. The AC timing specifications do not
include RefClk jitter.
Notes: 1. Measured at receiver.
2. Total jitter is composed of three components: deterministic jitter, random jitter and single frequency
sinusoidal jitter. The sinusoidal jitter may have any amplitude and frequency in the unshaded region of
Figure 2-2 on page 111. The sinusoidal jitter component is included to ensure margin for low-frequency
jitter, wander, noise, crosstalk, and other variable system effects.
Table 2-72. Serial RapidIO Transmitter AC Timing Specifications (At Recommended Operating
Conditions with XVDD = 1.5V or 1.8V)
Parameter Symbol Min Typical Max Units Notes
Deterministic jitter JD – – 0.17 UI p-p –
Total jitter JT – – 0.35 UI p-p –
Unit Interval: 2.5 GBaud UI 400 – 100ppm 400 400 + 100ppm ps –
Unit Interval: 3.125 GBaud UI 320 – 100ppm 320 320 + 100ppm ps –
Table 2-73. Serial RapidIO Receiver AC Timing Specifications (At Recommended Operating
Conditions with XVDD = 1.5V or 1.8V)
Parameter Symbol Min Typical Max Units Notes
Deterministic jitter tolerance JD0.37 – – UI p-p
(1)
Combined deterministic and
random jitter tolerance JDR 0.55 – – UI p-p
(1)
Total jitter tolerance2 JT 0.65 – – UI p-p
(1)
Bit error rate BER – – 10–12 ––
Unit Interval: 2.5 GBaud UI 400 – 100ppm 400 400 + 100ppm ps –
Unit Interval: 3.125 GBaud UI 320 – 100ppm 320 320 + 100ppm ps –
111
1066A–HIREL–07/11
e2v semiconductors SAS 2011
P4080
Figure 2-2 shows the single-frequency sinusoidal jitter limits.
Figure 2-2. Single-Frequency Sinusoidal Jitter Limits
2.20.6 XAUI
This section describes the DC and AC electrical specifications for the XAUI bus.
2.20.6.1 XAUI DC Electrical Characteristics
This section discusses the XAUI DC electrical characteristics for the clocking signals, transmitter, and
receiver.
2.20.6.1.1 DC Requirements for XAUI SD_REF_CLKn and SD_REF_CLKn
This section specifies XAUI DC level requirements for SD_REF_CLKn and SD_REF_CLKn, where
n = [2–3]. Only SerDes banks 2–3 may be used for various SerDes XAUI configurations based on the
RCW Configuration field SRDS_PRTCL. XAUI is not supported on SerDes bank 1.
For more information on these specifications, see Section 2.20.2 ”SerDes Reference Clocks” on page
95.
8.5 UI p-p
0.10 UI p-p
Sinusoidal
Jitter
Amplitude
22.1 kHz 1.875 MHz 20 MHzFrequency
112
1066A–HIREL–07/11
P4080
e2v semiconductors SAS 2011
2.20.6.1.2 XAUI Transmitter DC Electrical Characteristics
Table 2-74 defines the XAUI transmitter DC electrical characteristics.
Note: 1. Absolute output voltage limit.
2.20.6.1.3 XAUI Receiver DC Electrical Characteristics
Table 2-75 defines the XAUI receiver DC electrical characteristics.
Note: 1. Measured at receiver.
2.20.6.2 XAUI AC Timing Specifications
This section discusses the XAUI AC timing specifications for the clocking signals, transmitter, and
receiver.
Table 2-74. XAUI Transmitter DC Electrical Characteristics (At Recommended Operating Conditions
with XVDD = 1.5V or 1.8V)
Parameter Symbol Min Typical Max Unit Notes
Output voltage VO –0.40 – 2.30 V (1)
Differential output voltage VDIFFPP 800 1000 1600 mV p-p –
Table 2-75. XAUI Receiver DC Timing Specifications (At Recommended Operating Conditions with
XVDD = 1.5V or 1.8V)
Parameter Symbol Min Typical Max Unit Notes
Differential input voltage VIN 200 900 1600 mV p-p
(1)
113
1066A–HIREL–07/11
e2v semiconductors SAS 2011
P4080
2.20.6.2.1 AC Requirements for XAUI SD_REF_CLKn and SD_REF_CLKn
Table 2-76 specifies AC requirements for SD_REF_CLKn and SD_REF_CLKn, where n = [2–3]. Only
SerDes banks 2–3 may be used for various SerDes XAUI configurations based on the RCW
Configuration field SRDS_PRTCL. XAUI is not supported on SerDes bank 1.
For more information on these specifications, see Section 2.20.2 ”SerDes Reference Clocks” on page
95.
Notes: 1. Measured from –200 mV to +200 mV on the differential waveform (derived from SD_REF_CLKn minus SD_REF_CLKn).
The signal must be monotonic through the measurement region for rise and fall time. The 400 mV measurement window is
centered on the differential zero crossing. See Figure 2-33 on page 99.
2. Measurement taken from differential waveform
3. Measurement taken from single-ended waveform
4. Matching applies to rising edge for SD_REF_CLKn and falling edge rate for SD_REF_CLKn. It is measured using a 200 mV
window centered on the median cross point where SD_REF_CLKn rising meets SD_REF_CLKn falling. The median cross
point is used to calculate the voltage thresholds that the oscilloscope uses for the edge rate calculations. The rise edge rate
of SD_REF_CLKn should be compared to the fall edge rate of SD_REF_CLKn, the maximum allowed difference should not
exceed 20% of the slowest edge rate. See Figure 2-34 on page 99.
2.20.6.2.2 XAUI Transmitter AC Timing Specifications
Table 2-77 defines the XAUI transmitter AC timing specifications. RefClk jitter is not included.
Table 2-76. XAUI AC SD_REF_CLK3 and SD_REF_CLK3 Input Clock Requirements
(At Recommended Operating Conditions with SVDD = 1.0V)
Parameter Symbol Min Typical Max Unit Notes
SD_REF_CLK/SD_REF_CLK frequency range tCLK_REF –125
156.25 –MHz –
SD_REF_CLK/SD_REF_CLK clock frequency
tolerance tCLK_TOL –350 –350 ppm –
SD_REF_CLK/SD_REF_CLK reference clock
duty cycle (measured at 1.6V) tCLK_DUTY 40 50 60 % –
SD_REF_CLK/SD_REF_CLK cycle to cycle jitter
(period jitter at refClk input) tCLK_CJ ––100 ps –
SD_REF_CLK/SD_REF_CLK total reference
clock jitter (peak-to-peak phase jitter at refClk
input)
tCLK_PJ –50 –50 ps –
SD_REF_CLK/SD_REF_CLK rising/falling edge
rate tCLKRR/tCLKFR 1 –4 V/ns
(1)
Differential input high voltage VIH 200 ––mV (2)
Differential input low voltage VIL –––200 mV (2)
Rising edge rate (SD_REF_CLKn) to falling edge
rate (SD_REF_CLKn) matching
Rise-Fall
Matching ––20 %
(3)(4)
Table 2-77. XAUI Transmitter AC Timing Specifications (At Recommended Operating Conditions with
XVDD = 1.5V or 1.8V)
Parameter Symbol Min Typical Max Unit Notes
Deterministic jitter JD – – 0.17 UI p-p –
Total jitter JT – – 0.35 UI p-p –
Unit Interval: 3.125 GBaud UI 320 – 100 ppm 320 320 + 100 ppm ps –
114
1066A–HIREL–07/11
P4080
e2v semiconductors SAS 2011
2.20.6.2.3 XAUI Receiver AC Timing Specifications
Table 2-78 defines the receiver AC specifications for XAUI. RefClk jitter is not included.
Notes: 1. Measured at receiver.
2. Total jitter is composed of three components: deterministic jitter, random jitter, and single frequency sinusoidal jitter. The
sinusoidal jitter may have any amplitude and frequency in the unshaded region of Figure 2-2 on page 111. The sinusoidal
jitter component is included to ensure margin for low frequency jitter, wander, noise, crosstalk, and other variable system
effects.
2.20.7 Aurora
This section describes the Aurora clocking requirements and AC and DC electrical characteristics.
2.20.7.1 Aurora Clocking Requirements for SD_REF_CLKn and SD_REF_CLKn
This section specifies Aurora DC requirements for SD_REF_CLK1 and SD_REF_CLK1. Only SerDes
bank 1 may be used for SerDes Aurora configurations based on the RCW Configuration field
SRDS_PRTCL. Aurora is not supported on SerDes banks 2–3.
For more information on these specifications, see Section 2.20.2 ”SerDes Reference Clocks” on page 95
2.20.7.2 Aurora DC Electrical Characteristics
This section describes the DC electrical characteristics for Aurora.
2.20.7.2.1 Aurora Transmitter DC Electrical Characteristics
Table 2-79 defines the Aurora transmitter DC electrical characteristics.
2.20.7.2.2 Aurora Receiver DC Electrical Characteristics
Table 2-80 defines the Aurora receiver DC electrical characteristics for Aurora.
Note: 1. Measured at receiver.
Table 2-78. XAUI Receiver AC Timing Specifications (At Recommended Operating Conditions with XVDD = 1.5V or
1.8V)
Parameter Symbol Min Typical Max Unit Notes
Deterministic jitter tolerance JD 0.37 ––UI p-p (1)
Combined deterministic and random jitter tolerance JDR 0.55 ––UI p-p (1)
Total jitter tolerance(2) JT 0.65 ––UI p-p (1)
Bit error rate BER ––10–12 ––
Unit Interval: 3.125 GBaud UI 320 – 100 ppm 320 320 + 100 ppm ps –
Table 2-79. Aurora Transmitter DC Electrical Characteristics (At Recommended Operating Conditions
with XVDD = 1.5V or 1.8V)
Parameter Symbol Min Typical Max Unit Notes
Differential output voltage VDIFFPP 800 1000 1600 mV p-p –
Table 2-80. Aurora Receiver DC Electrical Characteristics (At Recommended Operating Conditions
with XVDD = 1.5V or 1.8V)
Parameter Symbol Min Typical Max Unit Notes
Differential input voltage VIN 120 900 1200 mV p-p
(1)
115
1066A–HIREL–07/11
e2v semiconductors SAS 2011
P4080
2.20.7.3 Aurora AC Timing Specifications
This section describes the AC timing specifications for Aurora.
2.20.7.3.1 Aurora Transmitter AC Timing Specifications
Table 2-81 defines the Aurora transmitter AC timing specifications. RefClk jitter is not included.
2.20.7.3.2 Aurora Receiver AC Timing Specifications
Table 2-82 defines the Aurora receiver AC timing specifications. RefClk jitter is not included.
Notes: 1. Measured at receiver.
2. Total jitter is composed of three components: deterministic jitter, random jitter, and single frequency sinusoidal jitter. The
sinusoidal jitter may have any amplitude and frequency in the unshaded region of Figure 2-2 on page 111. The sinusoidal
jitter component is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system
effects.
2.20.8 SGMII Interface
Each SGMII port features a 4-wire AC-coupled serial link from the SerDes interface of the P4080, as
shown in Figure 2-2 on page 117, where CTX is the external (on board) AC-coupled capacitor. Each
output pin of the SerDes transmitter differential pair features 50Ω output impedance. Each input of the
SerDes receiver differential pair features 50Ω on-die termination to XGND. The reference circuit of the
SerDes transmitter and receiver is shown in Figure 2-35 on page 99.
Table 2-81. Aurora Transmitter AC Timing Specifications (At Recommended Operating Conditions
with XVDD = 1.5V or 1.8V)
Parameter Symbol Min Typical Max Unit Notes
Deterministic jitter JD – – 0.17 UI p-p –
Total jitter JT – – 0.35 UI p-p –
Unit Interval: 2.5 GBaud UI 400 – 100 ppm 400 400 + 100 ppm ps –
Unit Interval: 3.125 GBaud UI 320 – 100 ppm 320 320 + 100 ppm ps –
Unit Interval: 5.0 GBaud UI 200 – 100 ppm 200 200 + 100 ppm ps –
Table 2-82. Aurora Receiver AC Timing Specifications (At Recommended Operating Conditions with XVDD = 1.5V or
1.8V)
Parameter Symbol Min Typical Max Unit Notes
Deterministic jitter tolerance JD 0.37 – – UI p-p
(1)
Combined deterministic and random jitter
tolerance JDR 0.55 – – UI p-p
(1)
Total jitter tolerance(2) JT 0.65 – – UI p-p
(1)
Bit error rate BER – – 10–12 ––
Unit Interval: 2.5 GBaud UI 400 – 100 ppm 400 400 + 100 ppm ps –
Unit Interval: 3.125 GBaud UI 320 – 100 ppm 320 320 + 100 ppm ps –
Unit Interval: 5.0 GBaud UI 200 – 100 ppm 200 200 + 100 ppm ps –
116
1066A–HIREL–07/11
P4080
e2v semiconductors SAS 2011
2.20.8.1 SGMII Clocking Requirements for SD_REF_CLKn and SD_REF_CLKn
When operating in SGMII mode, the EC_GTX_CLK125 clock is not required for this port. Instead, a
SerDes reference clock is required on SD_REF_CLKn and SD_REF_CLKn pins. This section specifies
SGMII requirements for SD_REF_CLKn and SD_REF_CLKn, where n = [1–3]. SerDes banks 1–3 may
be used for SerDes SGMII configurations based on the RCW Configuration field SRDS_PRTCL.
For more information on these specifications, see Section 2.20.2 ”SerDes Reference Clocks” on page
95.
2.20.8.2 SGMII DC Electrical Characteristics
This section discusses the electrical characteristics for the SGMII interface.
2.20.8.2.1 SGMII Transmit DC Timing Specifications
Table 2-83 describe the SGMII SerDes transmitter and receiver AC-coupled DC electrical
characteristics. Transmitter DC characteristics are measured at the transmitter outputs (SD_TXn and
SD_TXn) as shown in Figure 2-3 on page 117.
Notes: 1. This does not align to DC-coupled SGMII.
2. |VOD| = |VSD_TXn. VSD_TXn|. |VOD| is also referred to as output differential peak voltage. VTX-DIFFp-p = 2 × |VOD|.
3. Example amplitude reduction setting for SGMII on SerDes bank 1 lane E: B1TECRE0[AMP_RED] = 0b000010 for an output
differential voltage of 459 mV typical.
4. The |VOD| value shown in the Typ column is based on the condition of XVDD_SRDSn-Typ = 1.5V or 1.8V, no common mode
offset variation. SerDes transmitter is terminated with 100Ω differential load between SD_TXn and SD_TXn.
Table 2-83. SGMII DC Transmitter Electrical Characteristics (At Recommended Operating Conditions with XVDD = 1.5V
or 1.8V)
Parameter Symbol Min Typical Max Unit Notes
Output high voltage VOH – – 1.5 × |VOD|-max mV (1)
Output low voltage VOL |VOD|-min/2 – – mV (1)
Output differential voltage(2)(3)(4)
XVDD-Typ at 1.5V and 1.8V) |VOD|
320 500.0 725.0
mV
B(1-3)TECR(lane)0
[AMP_RED] =0b000000
293.8 459.0 665.6 B(1-3)TECR(lane)0
[AMP_RED] =0b000010
266.9 417.0 604.7 B(1-3)TECR(lane)0
[AMP_RED] =0b000101
240.6 376.0 545.2 B(1-3)TECR(lane)0
[AMP_RED] =0b001000
213.1 333.0 482.9 B(1-3)TECR(lane)0
[AMP_RED] =0b001100
186.9 292.0 423.4 B(1-3)TECR(lane)0
[AMP_RED] =0b001111
160.0 250.0 362.5 B(1-3)TECR(lane)0
[AMP_RED] = 0b010011
Output impedance (single-ended) RO40 50 60 Ω–
117
1066A–HIREL–07/11
e2v semiconductors SAS 2011
P4080
Figure 2-2 shows an example of a 4-wire AC-coupled SGMII serial link connection.
Figure 2-2. 4-Wire AC-Coupled SGMII Serial Link Connection Example
Figure 2-3 shows the SGMII transmitter DC measurement circuit.
Figure 2-3. SGMII Transmitter DC Measurement Circuit
SGMII
SerDes Interface
50Ω
50Ω
Transmitter
SD_TX
n
SD_RX
n
SD_TX
n
SD_RX
n
Receiver
CTX
CTX
50Ω
50Ω
SD_RX
n
SD_RX
n
Receiver Transmitter
SD_TX
n
SD_TX
n
CTX
CTX
50Ω
50Ω
50Ω
50Ω
50Ω
Transmitter
SD_TX
n
SD_TX
n
50Ω
VOD
SGMII
SerDes Interface
50Ω
50Ω
118
1066A–HIREL–07/11
P4080
e2v semiconductors SAS 2011
2.20.8.2.4 SGMII DC Receiver Electrical Characteristics
Table 2-84 lists the SGMII DC receiver electrical characteristics. Source synchronous clocking is not
supported. Clock is recovered from the data.
Notes: 1. Input must be externally AC coupled.
2. VRX_DIFFp-p is also referred to as peak-to-peak input differential voltage.
3. The concept of this parameter is equivalent to the electrical idle detect threshold parameter in PCI Express. Refer to Section
2.20.4.4 ”PCI Express DC Physical Layer Receiver Specifications” on page 102 and Section 2.20.4.5.2 ”PCI Express AC
Physical Layer Receiver Specifications” on page 105 for further explanation.
4. The REIDL_CTL shown in the table refers to the P4080 SerDes control register B(1–3)GCR(lane)1[REIDL_CTL] bit field.
2.20.8.3 SGMII AC Timing Specifications
This section discusses the AC timing specifications for the SGMII interface.
2.20.8.3.1 SGMII Transmit AC Timing Specifications
Table 2-85 provides the SGMII transmit AC timing specifications. A source synchronous clock is not
supported. The AC timing specifications do not include RefClk jitter.
Notes: 1. Each UI is 800 ps ± 100 ppm.
2. See Figure 2-5 on page 120 for single frequency sinusoidal jitter limits.
3. The external AC coupling capacitor is required. It is recommended that it be placed near the device
transmitter outputs.
Table 2-84. SGMII DC Receiver Electrical Characteristics (At Recommended Operating Conditions with XVDD = 1.5V or
1.8V)
Parameter Symbol Min Typ Max Unit Notes
DC Input voltage range –N/A –(1)
Input differential voltage REIDL_CTL = 001xx VRX_DIFFp-p
100 –1200 mV
(2)(4)
REIDL_CTL = 100xx 175 –
Loss of signal threshold REIDL_CTL = 001xx VLOS 30 –100 mV
(3)(4)
REIDL_CTL = 100xx 65 –175
Receiver differential input impedance ZRX_DIFF 80 –120 Ω–
Table 2-85. SGMII Transmit AC Timing Specifications (At Recommended Operating Conditions with
XVDD = 1.5V or 1.8V)
Parameter Symbol Min Typical Max Unit Notes
Deterministic jitter JD ––0.17 UI p-p –
Total jitter JT ––0.35 UI p-p (2)
Unit Interval UI 799.92 800 800.08 ps (1)
AC coupling capacitor CTX 75 100 200 nF (3)
119
1066A–HIREL–07/11
e2v semiconductors SAS 2011
P4080
2.20.8.3.2 SGMII AC Measurement details
Transmitter and receiver AC characteristics are measured at the transmitter outputs (SD_TXn and
SD_TXn) or at the receiver inputs (SD_RXn and SD_RXn) respectively, as depicted in Figure 2-3 on
page 117.
Figure 2-3. SGMII AC Test/Measurement Load
2.20.8.3.4 SGMII Receiver AC Timing Specification
Table 2-86 provides the SGMII receiver AC timing specifications. The AC timing specifications do not
include RefClk jitter. Source synchronous clocking is not supported. Clock is recovered from the data.
Notes: 1. Measured at receiver.
2. See the RapidIO™ 1×/4× LP Serial Physical Layer Specification for interpretation of jitter specifications.
3. Each UI is 800 ps ± 100 ppm.
TX
Silicon
+ Package
C = CTX
C = CTX
R = 50ΩR = 50Ω
D+ Package
Pin
D– Package
Pin
D+ Package
Pin
Table 2-86. SGMII Receive AC Timing Specifications (At Recommended Operating Conditions with
XVDD = 1.5V or 1.8V)
Parameter Symbol Min Typical Max Unit Notes
Deterministic jitter tolerance JD 0.37 ––UI p-p (1)(2)
Combined deterministic and random
jitter tolerance JDR 0.55 ––UI p-p (1)(2)
Total jitter tolerance JT 0.65 ––UI p-p (1)(2)
Bit error ratio BER ––10-12 ––
Unit Interval UI 799.92 800.00 800.08 ps (3)
120
1066A–HIREL–07/11
P4080
e2v semiconductors SAS 2011
The sinusoidal jitter in the total jitter tolerance may have any amplitude and frequency in the unshaded
region of Figure 2-5.
Figure 2-5. Single Frequency Sinusoidal Jitter Limits
3. Hardware Design Considerations
3.1 System Clocking
This section describes the PLL configuration of the P4080.
This device includes 9 PLLs, as follows:
• There are 4 selectable core cluster PLLs which generate a core clock from the externally supplied
SYSCLK input. Core complex 0–3 can select from CC1 PLL, CC2 PLL or CC3 PLL. Core complex
4–7 can select from CC3 PLL, CC4 PLL or CC1 PLL. The frequency ratio between each of the 4 core
cluster PLLs and SYSCLK is selected using the configuration bits as described in Section 3.1.3
”e500-mc Core Cluster to SYSCLK PLL Ratio” on page 122 The frequency for each core complex
0–7 is selected using the configuration bits as described in Table 3-4 on page 123 and Table 3-5 on
page 123.
• The platform PLL generates the platform clock from the externally supplied SYSCLK input. The
frequency ratio between the platform and SYSCLK is selected using the platform PLL ratio
configuration bits as described in Section 3.1.2 ”Platform to SYSCLK PLL Ratio” on page 122.
• The DDR block PLL generates the DDR clock from the externally supplied SYSCLK input
(asynchronous mode) or from the platform clock (synchronous mode). The frequency ratio is selected
using the Memory Controller Complex PLL multiplier/ratio configuration bits as described in Section
3.1.5 ”DDR Controller PLL Ratios” on page 123.
8.5 UI p-p
0.10 UI p-p
Sinusoidal
Jitter
Amplitude
22.1 kHz 1.875 MHz 20 MHzFrequency
121
1066A–HIREL–07/11
e2v semiconductors SAS 2011
P4080
• Each of the three SerDes blocks has a PLL which generate a core clock from their respective
externally supplied SD_REF_CLKn/SD_REF_CLKn inputs. The frequency ratio is selected using the
SerDes PLL ratio configuration bits as described in Section 3.1.6 ”SerDes PLL Ratio” on page 124.
3.1.1 Clock Ranges
Table 3-1 provides the clocking specifications for the processor core, platform, memory, and local bus.
Notes: 1. Caution: The platform clock to SYSCLK ratio and e500-mc core to SYSCLK ratio settings must be
chosen such that the resulting SYSCLK frequency, e500-mc (core) frequency, and platform clock
frequency do not exceed their respective maximum or minimum operating frequencies.
2. The memory bus clock speed is half the DDR2/DDR3 data rate. DDR2 memory bus clock frequency is
limited to max = 400 MHz. DDR3 memory bus clock frequency is limited to min = 400 MHz.
3. The local bus clock speed on LCLK[0:1] is determined by the platform clock divided by the local bus
ratio programmed in LCRR[CLKDIV]. Refer to the P4080 QorIQ Integrated Multicore Communication
Processor Family Reference Manual, for more information.
4. The e500-mc core can run at e500-mc core complex PLL/1 or PLL/2. With a minimum core complex
PLL frequency of 800 MHz, this results in a minimum allowable e500-mc core frequency of 400 MHz for
PLL/2.
5. In synchronous mode, the memory bus clock speed is half the platform clock frequency. In other words,
the DDR data rate is the same as the platform frequency. If the desired DDR data rate is higher than the
platform frequency, asynchronous mode must be used.
6. In asynchronous mode, the memory bus clock speed is dictated by its own PLL.
7. DDR data rate frequency must be ≤2× platform frequency.
Table 3-1. Processor Clocking Specifications
Characteristic
Maximum Processor Core Frequency
Unit Notes
1200 MHz 1333 MHz 1500 MHZ
Min Max Min Max Min Max
e500-mc core PLL frequency 800 1200 800 1333 800 1500 MHz (1)(4)
e500-mc core frequency (core
PLL/2) 400 600 400 667 400 750 MHz (4)
Platform clock frequency 600 667 800 MHz
600 600 600 (1)
Memory bus clock frequency 333 600 333 667 333 650 MHz
(1)(2)(5)
(6)(7)
Local bus clock frequency –75 –75 –75 MHz (3)
–75 –83.3 –100 MHz (3)
PME and FMn –450 –542 –600 MHz –
122
1066A–HIREL–07/11
P4080
e2v semiconductors SAS 2011
3.1.2 Platform to SYSCLK PLL Ratio
The allowed platform clock to SYSCLK ratios are shown in Table 3-2.
Note that in synchronous DDR mode, the DDR data rate is the determining factor for selecting the
platform bus frequency because the platform frequency must equal the DDR data rate.
In asynchronous DDR mode, the memory bus clock frequency is decoupled from the platform bus
frequency. The platform frequency must be greater than or equal to ½ the DDR data rate.
For platform clock frequency targeting 667 MHz and above, set the RCW Configuration field
SYS_PLL_CFG = 0b00. For 533–666-MHz frequencies, set SYS_PLL_CFG = 0b01.
3.1.3 e500-mc Core Cluster to SYSCLK PLL Ratio
The clock ratio between SYSCLK and each of the 4 core cluster PLLs is determined by the binary value
of the RCW Configuration field CCn_PLL_RAT. Table 3-2 describes the supported ratios. Note that for
core cluster PLL frequency targeting 1 GHz and above must set RCW Configuration field
CCn_PLL_CFG = b’00, for frequency targeting below 1 GHz set CCn_PLL_CFG = b’01.
Table 3-2 lists the supported Core Cluster to SYSCLK ratios.
Table 3-2. Platform to SYSCLK PLL Ratios
Binary Value of SYS_PLL_RAT Platform:SYSCLK Ratio
0_0101 5:1
0_0110 6:1
0_0111 7:1
0_1000 8:1
0_1001 9:1
0_1010 10:1
0_1011 11:1
0_1100 12:1
All Others Reserved
Table 3-3. e500-mc Core Cluster PLL to SYSCLK Ratios
Binary Value of CCn_PLL_RAT Core Cluster:SYSCLK Ratio
0_1000 8:1
0_1001 9:1
0_1010 10:1
0_1011 11:1
0_1100 12:1
0_1110 14:1
0_1111 15:1
1_0000 16:1
All Others Reserved
123
1066A–HIREL–07/11
e2v semiconductors SAS 2011
P4080
3.1.4 e500-mc Core Complex PLL Select
The clock frequency of each e500-mc core complex is determined by the binary value of the RCW
Configuration field CCn_PLL_SEL. Table 3-4 on page 123 and Table 3-5 on page 123 describe the
supported ratios for each core complex, where each individual core complex can select a frequency from
their respective tables.
Note, for Table 3-4, if CC3 PLL is ever used by any core 0–3, its maximum allowed frequency is 80% of
the maximum rated frequency of the core at nominal voltage.
Note, for Table 3-5, if CC1 PLL is ever used by any core 4–7, its maximum allowed frequency is 80% of
the maximum rated frequency of the core at nominal voltage.
3.1.5 DDR Controller PLL Ratios
The dual DDR memory controller complexes can be synchronous with or asynchronous to the platform,
depending on configuration. Both P4080 DDR controllers operate at the same frequency configuration.
Table 3-6 on page 124 describes the clock ratio between the DDR memory controller PLLs and the
externally supplied SYSCLK input (asynchronous mode) or from the platform clock (synchronous mode).
In asynchronous DDR mode, the DDR data rate to SYSCLK ratios supported are listed in Table 3-6. In
synchronous mode, the DDR data rate to platform clock ratios supported are listed in Table 3-7 on page
124. This ratio is determined by the binary value of the RCW Configuration field MEM_PLL_RAT (bits
10–14).
Table 3-4. e500-mc Core Complex [0–3] PLL Select
Binary Value of Cn_PLL_SEL for n = 0–3 e500-mc:Core Cluster Ratio
0000 CC1 PLL /1
0001 CC1 PLL /2
0100 CC2 PLL /1
0101 CC2 PLL /2
1000 CC3 PLL /1
All Others Reserved
Table 3-5. e500-mc Core Complex [4–7] PLL Select
Binary Value of Cn_PLL_SEL for n = 4–7 e500-mc:Core Cluster Ratio
0000 CC1 PLL /1
1000 CC3 PLL /1
1001 CC3 PLL /2
1100 CC4 PLL /1
1101 CC4 PLL /2
All Others Reserved
124
1066A–HIREL–07/11
P4080
e2v semiconductors SAS 2011
The RCW Configuration field MEM_PLL_CFG (bits 8.9) must be set to MEM_PLL_CFG = 0b01 if the
applied DDR PLL reference clock frequency is greater than the cutoff frequency listed in Table 3-6 on
page 124 and Table 3-7 on page 124 for asynchronous and synchronous DDR clock ratios respectively,
else set MEM_PLL_CFG = 0b00.
Note: The RCW Configuration field DDR_SYNC (bit 184) must be set to 0b0 for asynchronous mode and 0b1 for
synchronous mode.
The RCW Configuration field DDR_RATE (bit 232) must be set to 0b0 for asynchronous mode and 0b1 for
synchronous mode.
The RCW Configuration field DDR_RSV0 (bit 234) must be set to 0b0 for all ratios.
In asynchronous DDR mode, the DDR data rate to SYSCLK ratios supported are listed in Table 3-6.
Notes: 1. Set RCW field MEM_PLL_CFG = 0b01 if the applied DDR PLL reference clock (SYSCLK) frequency is
greater than given cutoff, else set to 0b00 for frequency that is less than or equal to cutoff.
2. DDR data rate frequency must be ≤2× platform frequency. Platform frequency must be ≥½ DDR data
rate.
In synchronous mode, the DDR data rate to platform clock ratios supported are listed in Table 3-7.
Note: 1. Set MEM_PLL_CFG=0b01 if the applied DDR PLL reference clock (Platform clock) frequency is greater
than given cutoff, else set to 0b00 for frequency that is less than or equal to cutoff.
3.1.6 SerDes PLL Ratio
The clock ratio between each of the three SerDes PLLs and their respective externally supplied
SD_REF_CLKn/SD_REF_CLKn inputs is determined by the binary value of the RCW Configuration field
SRDS_RATIO_Bn as shown in Table 3-8. Furthermore, each SerDes lane grouping can be run at a
SerDes PLL frequency divider determined by the binary value of the RCW Configuration field
SRDS_DIV_Bn as shown in Table 3-9 on page 125 and Table 3-10 on page 125.
Table 3-6. Asynchronous DDR Clock Ratio
Binary Value of
MEM_PLL_RAT(2)
DDR Data
Rate:SYSCLK Ratio
Set MEM_PLL_CFG = 01 for SYSCLK Freq(1)
(Rev 2.0 Silicon)
0_0101 5:1 > 96.7 MHz
0_0110 6:1 ≥83.3 MHz
0_1000 8:1 > 120.9 MHz
0_1001 9:1 > 107.4 MHz
0_1010 10:1 > 96.7 MHz
0_1100 12:1 ≥ 83.3 MHz
0_1101 13:1 ≥ 83.3 MHz
1_0000 16:1 ≥ 83.3 MHz
All Others Reserved –
Table 3-7. Synchronous DDR Clock Ratio
Binary Value of MEM_PLL_RAT
DDR Data Rate:Platform CLK
Ratio
Set MEM_PLL_CFG = 01 for
Platform CLK Freq(1)
0_0001 1:1 > 600 MHz
All Others Reserved –
125
1066A–HIREL–07/11
e2v semiconductors SAS 2011
P4080
Table 3-8 lists the supported SerDes PLL Bank n to SD_REF_CLKn ratios.
Note: 1. SerDes bank 1 only.
Table 3-9 and Table 3-10 list the supported SerDes PLL dividers. Table 3-9 shows the PLL divider
support for each pair of lanes on SerDes Bank 1. Table 3-10 shows the PLL dividers supported for each
4 lane group for SerDes Banks 2 and 3.
Note: 1. One bit (of 5 total SRDS_DIV_B1 bits) controls each pair of lanes. Where first bit controls config of
lanes A/B (or 0/1) and last bit controls config of lanes I/J (or 8/9).
Notes: 1. One bit controls all 4 lanes of each bank.
2. n = 2 or 3 (SerDes bank 2 or bank 3)
3.1.7 Frame Manager (FMn) Clock Select
The frame managers, FM1 and FM2, can each be synchronous with or asynchronous to the platform,
depending on configuration.
Table 3-11 describes the clocking options that may be applied to each FM. The clock selection is
determined by the binary value of the RCW Clocking Configuration fields FM1_CLK_SEL and
FM2_CLK_SEL.
Note: 1. For asynchronous mode, max frequency refer to Table 3-1 on page 121.
Table 3-8. SerDes PLL Bank n to SD_REF_CLKn Ratios
Binary Value of SRDS_RATIO_Bn SRDS_PLL_n:SD_REF_CLKn Ratio NOTE
000 10:1 –
001 20:1 –
010 25:1 –
011 40:1
(1)
100 50:1
(1)
All Others Reserved Reserved
Table 3-9. SerDes Bank 1 PLL Dividers
Binary Value of SRDS_DIV_B1[0:4] SerDes Bank 1 PLL Divider
0b0 Divide by 1 off Bank 1 PLL
0b1 Divide by 2 off Bank 1 PLL
Table 3-10. SerDes Banks 2 and 3 PLL Dividers
Binary Value of SRDS_DIV_BnSerDes Bank n PLL Divider
0b0 Divide by 1 off Bank n PLL
0b1 Divide by 2 off Bank n PLL
Table 3-11. Frame Manager (FMn) Clock Select
Binary Value of FMn_CLK_SEL FMn Frequency
0b0 Platform Clock Frequency /2
0b1 Core Cluster 3 Frequency /2(1)
126
1066A–HIREL–07/11
P4080
e2v semiconductors SAS 2011
3.1.8 Pattern Matching Engine (PME) Clock Select
The PME can be synchronous with or asynchronous to the platform, depending on configuration.
Table 3-12 describes the clocking options that may be applied to the PME. The clock selection is
determined by the binary value of the RCW Clocking Configuration field PME_CLK_SEL.
Note: 1. For asynchronous mode, max frequency refer to Table 3-1 on page 121.
3.1.9 Frequency Options
This section discusses interface frequency options.
3.1.9.1 SYSCLK and Platform Frequency Options
Table 3-13 shows the expected frequency options for SYCLK and platform frequencies.
Note: 1. Platform frequency values are shown rounded down to the nearest whole number (decimal place accu-
racy removed).
3.1.9.2 Minimum Platform Frequency Requirements for High-Speed Interfaces
The platform clock frequency must be considered for proper operation of high-speed interfaces as
described below.
Note per Table 3-1, the minimum platform frequency supported on the P4080 will always meet the
minimum platform frequency requirements for high-speed interfaces given in the formulas below.
Table 3-12. Pattern Matching Engine Clock Select
Binary Value of PME_CLK_SEL PME Frequency
0b0 Platform Clock Frequency /2
0b1 Core Cluster 3 Frequency /2(1)
Table 3-13. SYSCLK and Platform Frequency Options
Platform:
SYSCLK Ratio
SYSCLK (MHz)
83.33 100.00 111.11 133.33
Platform Frequency (MHz)(1)
5:1 666
6:1 600 666 799
7:1 700 777
8:1 666 800
9:1 749
10:1
11:1
12:1
127
1066A–HIREL–07/11
e2v semiconductors SAS 2011
P4080
For proper PCI Express operation, the platform clock frequency must be greater than or equal to:
Figure 3-1. Gen 1 PEX Minimum Platform Frequency
Figure 3-2. Gen 2 PEX Minimum Platform Frequency
See the “Link Width” section of the P4080 QorIQ Integrated Multicore Communication Processor Family
Reference Manual for PCI Express interface width details. Note that “PCI Express link width” in the
above equation refers to the negotiated link width as the result of PCI Express link training, which may or
may not be the same as the link width POR selection.
For proper serial RapidIO operation, the platform clock frequency must be greater than or equal to:
Figure 3-3. Serial RapidIO Minimum Platform Frequency
See the “1x/4x LP-Serial Signal Descriptions” section of the P4080 QorIQ Integrated Multicore
Communication Processor
Family Reference Manual for serial RapidIO interface width and frequency details.
527 MHz (PCI Express link width)×
8
------------------------------------------------------------------------------------------------
527 MHz (PCI Express link width)×
4
------------------------------------------------------------------------------------------------
2 (0.8512)×(serial RapidIO interface frequency) (serial RapidIO link)××
64
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
128
1066A–HIREL–07/11
P4080
e2v semiconductors SAS 2011
3.2 Supply Power Setting
P4080 is capable of supporting multiple power supply levels on its I/O supplies. The I/O voltage select
inputs, shown in Table 3-14 on page 128, properly configure the receivers and drivers of the I/Os
associated with the BVDD, CVDD, and LVDD power planes, respectively.
WARNING : Incorrect voltage select settings can lead to irreversible device damage.
Table 3-14. I/O Voltage Selection
Signals Value (Binary)
VDD Voltage Selection
BVDD CVDD LVDD
IO_VSEL[0:4]
0_0000 3.3V 3.3V 3.3V
0_0001 3.3V 3.3V 2.5V
0_0010 3.3V 3.3V 1.8V
0_0011 3.3V 2.5V 3.3V
0_0100 3.3V 2.5V 2.5V
0_0101 3.3V 2.5V 1.8V
0_0110 3.3V 1.8V 3.3V
0_0111 3.3V 1.8V 2.5V
0_1000 3.3V 1.8V 1.8V
0_1001 2.5V 3.3V 3.3V
0_1010 2.5V 3.3V 2.5V
0_1011 2.5V 3.3V 1.8V
0_1100 2.5V 2.5V 3.3V
0_1101 2.5V 2.5V 2.5V
0_1110 2.5V 2.5V 1.8V
0_1111 2.5V 1.8V 3.3V
1_0000 2.5V 1.8V 2.5V
1_0001 2.5V 1.8V 1.8V
1_0010 1.8V 3.3V 3.3V
1_0011 1.8V 3.3V 2.5V
1_0100 1.8V 3.3V 1.8V
1_0101 1.8V 2.5V 3.3V
1_0110 1.8V 2.5V 2.5V
1_0111 1.8V 2.5V 1.8V
1_1000 1.8V 1.8V 3.3V
1_1001 1.8V 1.8V 2.5V
1_1010 1.8V 1.8V 1.8V
1_1011 3.3V 3.3V 3.3V
1_1100 3.3V 3.3V 3.3V
1_1101 3.3V 3.3V 3.3V
1_1110 3.3V 3.3V 3.3V
1_1111 3.3V 3.3V 3.3V
129
1066A–HIREL–07/11
e2v semiconductors SAS 2011
P4080
3.3 Power Supply Design
3.3.1 PLL Power Supply Filtering
Each of the PLLs described in Section 3.1 ”System Clocking” on page 120 is provided with power
through independent power supply pins (AVDD_PLAT, AVDD_CCn, AVDD_DDR, and AVDD_SRDSn). AVDD_PLAT,
AVDD_CCn, and AVDD_DDR voltages must be derived directly from the VDD_PL source through a low
frequency filter scheme. AVDD_SRDSn voltages must be derived directly from the SVDD source through a
low frequency filter scheme.
The recommended solution for PLL filtering is to provide independent filter circuits per PLL power
supply, as illustrated in Figure 3-4, one for each of the AVDD pins. By providing independent filters to
each PLL, the opportunity to cause noise injection from one PLL to the other is reduced.
This circuit is intended to filter noise in the PLL’s resonant frequency range from a 500-kHz to 10-MHz
range.
Each circuit should be placed as close as possible to the specific AVDD pin being supplied to minimize
noise coupled from nearby circuits. It should be possible to route directly from the capacitors to the AVDD
pin, which is on the periphery of the footprint, without the inductance of vias.
Figure 3-4 shows the PLL power supply filter circuit.
Where:
R = 5Ω ± 5%
C1 = 10 µF ± 10%, 0603, X5R, with ESL ≤0.5 nH
C2 = 1.0 µF ± 10%, 0402, X5R, with ESL ≤0.5 nH
Note: A higher capacitance value for C2 may be used to improve the filter as long as the other C2 parameters do
not change (0402 body, X5R, ESL ≤0.5 nH).
Voltage for AVDD is defined at the input of the PLL supply filter and not the pin of AVDD.
Figure 3-4. PLL Power Supply Filter Circuit
The AVDD_SRDS signals provides power for the analog portions of the SerDes PLL. To ensure stability of
the internal clock, the power supplied to the PLL is filtered using a circuit similar to the one shown in
following Figure 3-5 on page 130. For maximum effectiveness, the filter circuit is placed as closely as
possible to the AVDD_SRDSn balls to ensure it filters out as much noise as possible. The ground
connection should be near the AVDD_SRDSn balls. The 0.003 µF capacitor is closest to the balls, followed
by two 2.2 µF capacitors, and finally the 1Ω resistor to the board supply plane. The capacitors are
connected from AVDD_SRDSn to the ground plane. Use ceramic chip capacitors with the highest possible
self-resonant frequency. All traces should be kept short, wide, and direct.
V
DD_PL
AV
DD_PLAT
, AV
DD_CC
n
, AV
DD_DDR
C1 C2
GND Low ESL Surface Mount Capacitors
R
130
1066A–HIREL–07/11
P4080
e2v semiconductors SAS 2011
Figure 3-5. SerDes PLL Power Supply Filter Circuit
Note the following:
•AV
DD_SRDSn should be a filtered version of SVDD
.
• Signals on the SerDes interface are fed from the XVDD power plane.
• Voltage for AVDD_SRDSn is defined at the PLL supply filter and not the pin of AVDD_SRDSn.
• An 0805 sized capacitor is recommended for system initial bring-up.
3.3.2 XVDD Power Supply Filtering
XVDD may be supplied by a linear regulator or sourced by a filtered GVDD. Systems may design in both
options to allow flexibility to address system noise dependencies.
An example solution for XVDD filtering, where XVDD is sourced from GVDD, is illustrated in Figure 3-6. The
component values in this example filter are system dependent and are still under characterization,
component values may need adjustment based on the system or environment noise.
Where:
C1 = 2.2 µF ± 10%, X5R, with ESL ≤0.5 nH
C2 = 2.2 µF ± 10%, X5R, with ESL ≤0.5 nH
F1 = 120Ω at 100-MHz 2A 25% 0603 Ferrite
F2 = 120Ω at 100-MHz 2A 25% 0603 Ferrite
Figure 3-6. XVDD Power Supply Filter Circuit
3.4 Decoupling Recommendations
Due to large address and data buses, and high operating frequencies, the device can generate transient
power surges and high frequency noise in its power supply, especially while driving large capacitive
loads. This noise must be prevented from reaching other components in the P4080 system, and the
device itself requires a clean, tightly regulated source of power. Therefore, it is recommended that the
system designer place at least one decoupling capacitor at each VDD, BVDD, OVDD, CVDD, GVDD, and
LVDD pin of the device. These decoupling capacitors should receive their power from separate VDD,
BVDD, OVDD, CVDD, GVDD, LVDD, and GND power planes in the PCB, utilizing short traces to minimize
inductance. Capacitors may be placed directly under the device using a standard escape pattern. Others
may surround the part.
These capacitors should have a value of 0.01 or 0.1 µF. Only ceramic SMT (surface mount technology)
capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes.
2.2 µF10.003 µF
1.0Ω
AVDD_SRDS
n
2.2 µF1
GND
SVDD
XV
DD
GV
DD
C1 C2
GND
F1
F2
131
1066A–HIREL–07/11
e2v semiconductors SAS 2011
P4080
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB,
feeding the VDD, BVDD, OVDD, CVDD, GVDD, and LVDD planes, to enable quick recharging of the smaller
chip capacitors. These bulk capacitors should have a low ESR (equivalent series resistance) rating to
ensure the quick response time necessary. They should also be connected to the power and ground
planes through two vias to minimize inductance. Suggested bulk capacitors 100-330 µF (AVX TPS
tantalum or Sanyo OSCON).
3.5 SerDes Block Power Supply Decoupling Recommendations
The SerDes block requires a clean, tightly regulated source of power (SVDD and XVDD) to ensure low
jitter on transmit and reliable recovery of data in the receiver. An appropriate decoupling scheme is
outlined below.
Only SMT capacitors should be used to minimize inductance. Connections from all capacitors to power
and ground should be done with multiple vias to further reduce inductance.
• First, the board should have at least 10 × 10-nF SMT ceramic chip capacitors as close as possible to
the supply balls of the device. Where the board has blind vias, these capacitors should be placed
directly below the chip supply and ground connections. Where the board does not have blind vias,
these capacitors should be placed in a ring around the device as close to the supply and ground
connections as possible.
• Second, there should be a 1 µF ceramic chip capacitor on each side of the device. This should be
done for all SerDes supplies.
• Third, between the device and any SerDes voltage regulator there should be a 10 µF, low ESR SMT
tantalum chip capacitor and a 100 µF, low ESR SMT tantalum chip capacitor. This should be done for
all SerDes supplies.
3.6 Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal
level. All unused active low inputs should be tied to VDD, BVDD, CVDD, OVDD, GVDD, and LVDD as
required. All unused active high inputs should be connected to GND. All NC (no-connect) signals must
remain unconnected. Power and ground connections must be made to all external VDD, BVDD, CVDD,
OVDD, GVDD, LVDD, and GND pins of the device.
The Ethernet controllers 1 and/or 2 input pins may be disabled by setting their respective RCW
Configuration field EC1 (bits 360-361) to 0b11, and EC2 (bits 363–365) to 0b111 = No parallel mode
Ethernet, no USB. When disabled, these inputs do not need to be externally pulled to an appropriate
signal level.
EC_GTX_CLK125 is a 125-MHz input clock shared among all dTSEC ports. If the dTSEC ports are not
used for RGMII, the EC_GTX_CLK125 input can be tied off to GND.
If RCW field DMA1 = 0b1 (RCW bit 384), the DMA1 external interface is not enabled and the
DMA1_DDONE0 pin should be left as a no connect.
If RCW field I2C3 = 0b11 (RCW bits 369–370) is selected, the SDHC_WP and SDHC_CD input signals
are enabled for external use. If SDHC_WP and SDHC_CD are selected an not used, they must be
externally pulled low such that SDHC_WP = 0 = write enabled and SDHC_CD = 0 = card detected. If
RCW field I2C3 != 0b11, thereby selecting either I2C3 or GPIO functionality, SDHC_WP and SDHC_CD
are internally driven such that SDHC_WP = write enabled and SDHC_CD = card detected and the
selected I2C3 or GPIO external pin functionality maybe used.
132
1066A–HIREL–07/11
P4080
e2v semiconductors SAS 2011
The P4080 may be run with cores 4–7 disabled by connecting TEST_SEL to GND. In this mode, it is
recommended that the associated power plane, VDD_CB, be tied to the GND plane as well to save static
power. Note that with TEST_SEL = 0, SVR = 0x8201_0010 for 4 core P4080 without security and SVR =
0x8209_0010 for 4 core P4080E with security.
The TMP_DETECT pin is an active low input to the Security Monitor (reference the Secure Boot and
Trust Architecture chapter of the P4080 QorIQ Integrated Multicore Communication Processor Family
Reference Manual). When using Trust Architecture functionality, external logic must ramp
TMP_DETECT with OVDD. If not using Trust Architecture functionality, TMP_DETECT must be tied to
OVDD to prevent the input from going low.
3.6.1 Legacy JTAG Configuration Signals
Correct operation of the JTAG interface requires configuration of a group of system control pins as
demonstrated in Figure 3-8 on page 134. Care must be taken to ensure that these pins are maintained at
a valid deasserted state under normal operating conditions as most have asynchronous behavior and
spurious assertion will give unpredictable results.
Boundary-scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the
IEEE Std 1149.1 specification, but it is provided on all processors built on Power Architecture
technology. The device requires TRST to be asserted during power-on reset flow to ensure that the
JTAG boundary logic does not interfere with normal chip operation. While the TAP controller can be
forced to the reset state using only the TCK and TMS signals, generally systems assert TRST during the
power-on reset flow. Simply tying TRST to PORESET is not practical because the JTAG interface is also
used for accessing the common on-chip processor (COP), which implements the debug interface to the
chip.
The COP function of these processors allow a remote computer system (typically, a PC with dedicated
hardware and debugging software) to access and control the internal operations of the processor. The
COP interface connects primarily through the JTAG port of the processor, with some additional status
monitoring signals. The COP port requires the ability to independently assert PORESET or TRST in
order to fully control the processor. If the target system has independent reset sources, such as voltage
monitors, watchdog timers, power supply failures, or push-button switches, then the COP reset signals
must be merged into these signals with logic.
The arrangement shown in Figure 3-8 allows the COP port to independently assert PORESET or TRST,
while ensuring that the target can drive PORESET as well.
The COP interface has a standard header, shown in Figure 3-7 on page 133, for connection to the target
system, and is based on the 0.025" square-post, 0.100" centered header assembly (often called a Berg
header). The connector typically has pin 14 removed as a connector key.
The COP header adds many benefits such as breakpoints, watchpoints, register and memory
examination/modification, and other standard debugger features. An inexpensive option can be to leave
the COP header unpopulated until needed.
There is no standardized way to number the COP header; so emulator vendors have issued many
different pin numbering schemes. Some COP headers are numbered top-to-bottom then left-to-right,
while others use left-to-right then top-to-bottom. Still others number the pins counter-clockwise from pin
1 (as with an IC). Regardless of the numbering scheme, the signal placement recommended in Figure 3-
7 is common to all known emulators.
133
1066A–HIREL–07/11
e2v semiconductors SAS 2011
P4080
3.6.1.1 Termination of Unused Signals
If the JTAG interface and COP header will not be used, Freescale recommends the following
connections:
•TRST
should be tied to PORESET through a 0 KΩ isolation resistor so that it is asserted when the
system reset signal (PORESET) is asserted, ensuring that the JTAG scan chain is initialized during
the power-on reset flow. Freescale recommends that the COP header be designed into the system as
shown in Figure 3-8 on page 134. If this is not possible, the isolation resistor will allow future access
to TRST in case a JTAG interface may need to be wired onto the system in future debug situations.
• No pull-up/pull-down is required for TDI, TMS or TDO.
Figure 3-7. Legacy COP Connector Physical Pinout
3
13
9
5
1
6
10
15
11
7
16
12
8
4
KEY
No pin
12
COP_TDO
COP_TDI
NC
NC
COP_TRST
COP_VDD_SENSE
COP_CHKSTP_IN
NC
NC
GND
COP_TCK
COP_TMS
COP_SRESET
COP_HRESET
COP_CHKSTP_OUT
134
1066A–HIREL–07/11
P4080
e2v semiconductors SAS 2011
Figure 3-8. Legacy JTAG Interface Connection
Notes: 1. The COP port and target board should be able to independently assert PORESET and TRST to the
processor in order to fully control the processor as shown here.
2. Populate this with a 10Ω resistor for short-circuit/current-limiting protection.
3. The KEY location (pin 14) is not physically present on the COP header.
4. Although pin 12 is defined as a No-Connect, some debug tools may use pin 12 as an additional GND
pin for improved signal integrity.
5. This switch is included as a precaution for BSDL testing. The switch should be closed to position A
during BSDL testing to avoid accidentally asserting the TRST line. If BSDL testing is not being
performed, this switch should be closed to position B.
6. Asserting HRESET causes a hard reset on the device.
PORESET
From Target
Board Sources
COP_HRESET
13
COP_SRESET
HRESET
NC
11
COP_VDD_SENSE(2)
6
15
10Ω
10 kΩ
10 kΩ
COP_CHKSTP_IN
8
COP_TMS
COP_TDO
COP_TDI
COP_TCK
TMS
TDO
TDI
9
1
3
4COP_TRST
7
16
2
10
12
(if any)
COP Header
14(3)
10 kΩ
TRST(1)
10 kΩ
10 kΩ
10 kΩ
CKSTP_OUT
COP_CHKSTP_OUT
3
13
9
5
1
6
10
15
11
7
16
12
8
4
KEY
No pin
COP Connector
Physical Pinout
1
2
NC
HRESET
NC
OVDD
10 kΩPORESET(1)
TCK
(4)
(5) 10 kΩ
(6)
A
B
5
System logic
135
1066A–HIREL–07/11
e2v semiconductors SAS 2011
P4080
3.6.2 Aurora Configuration Signals
Correct operation of the Aurora interface requires configuration of a group of system control pins as
demonstrated in Figure 3-9 and Figure 3-10 on page 136. Care must be taken to ensure that these pins
are maintained at a valid deasserted state under normal operating conditions as most have
asynchronous behavior and spurious assertion will give unpredictable results.
Freescale recommends that the Aurora 22 pin duplex connector be designed into the system as shown
in Figure 3-11 on page 137 or the 70 pin duplex connector be designed into the system as shown in
Figure 3-11 on page 137.
If the Aurora interface will not be used, Freescale recommends the legacy COP header be designed into
the system as described in Section 3.6.1.1 ”Termination of Unused Signals” on page 133.
Figure 3-9. Aurora 22 Pin Connector Duplex Pinout
3
13
9
5
1
6
10
15
11
7
16
12
8
4
12
TX0+
TX0-
GND
VIO (VSense)
TCK
TMS
TDI
TDO
TRST
Vendor I/O 1
TX1+
TX1-
GND
RX0+
RX0-
17 18
20
19
21 22
GND
RX1+
RX1-
Vendor I/O 0
14
Vendor I/O 3
Vendor I/O 2
RESET
136
1066A–HIREL–07/11
P4080
e2v semiconductors SAS 2011
Figure 3-10. Aurora 70 Pin Connector Duplex Pinout
3
13
9
5
1
6
10
15
11
7
16
12
8
4
12
TX0+
TX0-
GND
VIO (VSense)
TCK
TMS
TDI
TDO
TRST
Vendor I/O 1
TX1+
TX1-
GND
RX0+
RX0-
17 18
20
19
21 22
GND
RX1+
RX1-
Vendor I/O 0
14
Vendor I/O 3
Vendor I/O 2
RESET
25
35
31
27
23
28
32
37
33
29
38
34
30
26
24
GND
TX2+
TX2-
GND
CLK+
CLK-
GND
Vendor I/O 4
Vendor I/O 5
N/C
GND
TX3+
TX3-
GND
RX2+
39 40
42
41
43 44
RX2-
GND
RX3+
GND
36
GND
N/C
N/C
47
57
53
49 50
54
59
55
51
60
56
52
48
45 46
RX3-
GND
TX4+
N/C
GND
N/C
N/C
GND
N/C
GND
TX4-
GND
TX5+
TX5-
GND
61 62
64
63
65 66
TX6+
TX6-
GND
N/C
58
N/C
N/C
GND
68
67
69 70
TX7+
TX7-
N/C
N/C
137
1066A–HIREL–07/11
e2v semiconductors SAS 2011
P4080
Figure 3-11. Aurora 22 Pin Connector Duplex Interface Connection
Notes: 1. The Aurora port and target board should be able to independently assert PORESET and TRST to the processor in order to
fully control the processor as shown here.
2. Populate this with a 1 kΩ resistor for short-circuit/current-limiting protection.
3. This switch is included as a precaution for BSDL testing. The switch should be closed to position A during BSDL testing to
avoid accidentally asserting the TRST line. If BSDL testing is not being performed, this switch should be closed to position B.
4. Asserting HRESET causes a hard reset on the device. HRESET is not used by the Aurora 22 pin connector.
PORESET
From Target
Board Sources
RESET
22
HRESET
VIO VSense(2)
2
1 kΩ
COP_TMS
COP_TDO
COP_TDI
COP_TCK
TMS
TDO
TDI
6
10
8
12 TRST
4
17
11
(if any)
COP Header
10 kΩ
TRST(1)
10 kΩ
10 kΩ
10 kΩ
Duplex 22 Connector
Physical Pinout
HRESET
OVDD
10 kΩPORESET(1)
TCK
(3) 10 kΩ
(4)
A
B
3
13
9
5
1
6
10
15
11
7
16
12
8
4
12
17 18
20
19
21 22
14
20 Vendor I/O 3 N/C
18 Vendor I/O 2 (Aurora Event Out)
16 Vendor I/O 1 (Aurora Event In)
14 Vendor I/O 0 (Aurora HALT)
5
EVT[4]
EVT[1]
EVT[0]
1TX0_P
3TX0_N
SD_TX09_P
SD_TX09_N
7TX1_P
9TX1_N
SD_TX08_P
SD_TX08_N
13 RX0_P
15 RX0_N
SD_RX09_P
SD_RX09_N
19 RX1_P
21 RX1_N
SD_RX08_P
SD_RX08_N
138
1066A–HIREL–07/11
P4080
e2v semiconductors SAS 2011
Figure 3-12. Aurora 70 Pin Connector Duplex Interface Connection
Notes: 1. The Aurora port and target board should be able to independently assert PORESET and TRST to the processor in order to
fully control the processor as shown here.
2. Populate this with a 1 kΩ resistor for short-circuit/current-limiting protection.
3. This switch is included as a precaution for BSDL testing. The switch should be closed to position A during BSDL testing to
avoid accidentally asserting the TRST line. If BSDL testing is not being performed, this switch should be closed to position B.
4. Asserting HRESET causes a hard reset on the device.
PORESET
From Target
Board Sources
RESET
22
HRESET
VIO VSense(2)
2
1 kΩ
COP_TMS
COP_TDO
COP_TDI
COP_TCK
TMS
TDO
TDI
6
10
8
12
TRST
4
42,47,48,53,54,
29,30,35,36,41,
(if any)
COP Header
TRST (1)
10 kΩ
10 kΩ
10 kΩ
Duplex 70
HRESET
OVDD
10 kΩPORESET(1)
TCK
(3) 10 kΩ
(4)
A
B
20 Vendor I/O 3 N/C
18 Vendor I/O 2 (Aurora Event Out)
16 Vendor I/O 1 (Aurora Event In)
14 Vendor I/O 0 (Aurora HALT)
5,11,17,23,24,
EVT[4]
EVT[1]
EVT[0]
1TX0_P
3TX0_N
SD_TX09_P
SD_TX09_N
7TX1_P
9TX1_N
SD_TX08_P
SD_TX08_N
13 RX0_P
15 RX0_N
SD_RX09_P
SD_RX09_N
19 RX1_P
21 RX1_N
SD_RX08_P
SD_RX08_N
3
13
9
5
1
6
10
15
11
7
16
12
8
4
12
17 18
20
19
21 22
14
25
35
31
27
23
28
32
37
33
29
38
34
30
26
24
39 40
42
41
43 44
36
47
57
53
49 50
54
59
55
51
60
56
52
48
45 46
61 62
64
63
65 66
58
68
67
69 70
34 Vendor I/O 5 (Aurora HRESET)
32 Vendor I/O 4 N/C EVT[4]
31,33,37,38,
N/C
39,40,43,44,
45,46,49,50,
51,52,55,56,
57,58,61,62,
63,64,67,68,
25,26,27,28,
69,70
59,60,65,66
Connector
Physical Pinout
10 kΩ
10 kΩ
139
1066A–HIREL–07/11
e2v semiconductors SAS 2011
P4080
3.6.3 Guidelines for High-Speed Interface Termination
3.6.3.1 SerDes Interface Entirely Unused
If the high-speed SerDes interface is not used at all, the unused pin should be terminated as described in
this section.
The following pins must be left unconnected:
• SD_TX[17:0]
•SD_TX
[17:0]
The following pins must be connected to SGND:
• SD_RX[17:0]
• SD_RX[17:0]
• SD_REF_CLK1, SD_REF_CLK2, SD_REF_CLK3
• SD_REF_CLK1, SD_REF_CLK2, SD_REF_CLK3
The following pins must be left unconnected:
• SD_IMP_CAL_RX
• SD_IMP_CAL_TX
In the RCW configuration fields SRDS_LPD_B1, SRDS_LPD_B2 and SRDS_LPD_B3, all bits must be
set to power down all the lanes in each bank.
The RCW configuration field SRDS_EN may be cleared to power down the SerDes block for power
saving.
RCW[SRDS_EN] = 0 will powerdown the PLLs of all three banks.
Additionally, software may configure SRDSBnRSTCTL[SDPD] = 1 for the unused banks to power down
the SerDes bank PLLs for power savings.
Note that both SVDD and XVDD must remain powered.
3.6.3.2 SerDes Interface Partly Unused
If only part of the high speed SerDes interface pins are used, the remaining high-speed serial I/O pins
should be terminated as described in this section.
The following unused pins must be left unconnected:
•SD_TX[n]
•SD_TX
[n]
The following unused pins must be connected to SGND:
• SD_RX[n]
• SD_RX[n]
• SD_REF_CLK1, SD_REF_CLK1 (If entire SerDes bank 1 unused)
• SD_REF_CLK2, SD_REF_CLK2 (If entire SerDes bank 2 unused)
• SD_REF_CLK3, SD_REF_CLK3 (If entire SerDes bank 2 and 3 are unused)
In the RCW configuration field SRDS_LPD_Bn for each bank, the respective bit for each unused lane
must be set to power down the lane.
140
1066A–HIREL–07/11
P4080
e2v semiconductors SAS 2011
If an entire SerDes bank is unused, software may configure SRDSBnRSTCTL[SDPD] = 1 for the unused
bank to power down the SerDes bank PLL for power savings, however, SerDes bank 3 PLL may only be
powered down if the entire SerDes bank 2 and 3 are unused.
3.7 Recommended Thermal Model
Information about Flotherm models of the package or thermal data not available in this document can be
obtained from your local Freescale sales office.
3.8 Thermal Management Information
This section provides thermal management information for the flip chip plastic ball grid array (FC-PBGA)
package for air-cooled applications. Proper thermal control design is primarily dependent on the system-
level design–the heat sink, airflow, and thermal interface material. The P4080 implements several
features designed to assist with thermal management, including the temperature diode. The temperature
diode allows an external device to monitor the die temperature in order to detect excessive temperature
conditions and alert the system; see Section 3.8.3 ”Temperature Diode” on page 141 for more
information.
The recommended attachment method to the heat sink is illustrated in Figure 3-13. The heat sink should
be attached to the printed-circuit board with the spring force centered over the die. This spring force
should not exceed 10 pounds force (45 Newton).
Figure 3-13. Package Exploded Cross-Sectional View.FC-PBGA (with Lid) Package
The system board designer can choose between several types of heat sinks to place on the device.
There are several commercially-available thermal interfaces to choose from in the industry. Ultimately,
the final selection of an appropriate heat sink depends on many factors, such as thermal performance at
a given air velocity, spatial volume, mass, attachment method, assembly, and cost.
Adhesive or
Heat Sink FC-PBGA Package (w/ Lid)
Heat Sink
Clip
Printed-Circuit Board
Thermal Interface Material
Die
Die Lid
141
1066A–HIREL–07/11
e2v semiconductors SAS 2011
P4080
3.8.1 Internal Package Conduction Resistance
For the package, the intrinsic internal conduction thermal resistance paths are as follows:
• The die junction-to-case thermal resistance
• The die junction-to-lid-top thermal resistance
• The die junction-to-board thermal resistance
Figure 3-14 depicts the primary heat transfer path for a package with an attached heat sink mounted to a
printed-circuit board.
Figure 3-14. Package with Heat Sink Mounted to a Printed-Circuit Board
Note the internal versus external package resistance.
The heat sink removes most of the heat from the device. Heat generated on the active side of the chip is
conducted through the silicon and through the heat sink attach material (or thermal interface material),
and finally to the heat sink. The junction-to-case thermal resistance is low enough that the heat sink
attach material and heat sink thermal resistance are the dominant terms.
3.8.2 Thermal Interface Materials
A thermal interface material is required at the package-to-heat sink interface to minimize the thermal
contact resistance. The performance of thermal interface materials improves with increasing contact
pressure; this performance characteristic chart is generally provided by the thermal interface vendor.
The recommended method of mounting heat sinks on the package is by means of a spring clip
attachment to the printed-circuit board (see Figure 3-13).
The system board designer can choose among several types of commercially-available thermal interface
materials.
3.8.3 Temperature Diode
The P4080 has a temperature diode on the microprocessor that can be used in conjunction with other
system temperature monitoring devices (such as Analog Devices, ADT7461A™). These devices use the
negative temperature coefficient of a diode operated at a constant current to determine the temperature
of the microprocessor and its environment.
The following are the specifications of the P4080 on-board temperature diode:
Operating range: 10 – 230 µA
Ideality factor over 13.5 – 220 µA: n = 1.007 + 0.008
External Resistance
External Resistance
Internal Resistance
Radiation Convection
Radiation Convection
Heat Sink
Printed-Circuit Board
Thermal Interface Material
Package/Solder balls
Die Junction
Die/Package
Junction to lid top
Junction to case top
142
1066A–HIREL–07/11
P4080
e2v semiconductors SAS 2011
4. Package Information
The following section describes the detailed content and mechanical description of the package.
4.1 Package Parameters for the P4080 FC-PBGA
The package parameters are as provided in the following list. The package type is 37.5 mm × 37.5 mm,
1295 flip chip plastic ball grid array (FC-PBGA).
4.2 Mechanical Dimensions of the P4080 FC-PBGA
Figure 4-1 shows the mechanical dimensions and bottom surface nomenclature of the P4080.
Package outline 37.5 mm × 37.5 mm
Interconnects 1295
Ball Pitch 1.0 mm
Ball Diameter (typical) 0.60 mm
Solder Balls 96.5% Sn, 3% Ag, 0.5% Cu
Module height (typical) 2.88 mm to 3.53 mm (maximum)
143
1066A–HIREL–07/11
e2v semiconductors SAS 2011
P4080
Figure 4-1. Mechanical Dimensions of the P4080 FC-PBGA with Full Lid
Notes: 1. All dimensions are in millimeters.
Top View
Bottom View Side View
Seating
Plane
0.25 A
0.35 A
5
A
0.21295X
B
C
A1 INDEX AREA
A1 CORNER
0 MIN
LID
PLACEMENT
37.5
27.6
27
144
1066A–HIREL–07/11
P4080
e2v semiconductors SAS 2011
2. Dimensioning and tolerancing per ASME Y14.5M-1994.
3. Maximum solder ball diameter measured parallel to datum A.
4. Datum A, the seating plane, is determined by the spherical crowns of the solder balls.
5. Parallelism measurement shall exclude any effect of mark on top surface of package.
5. Security Fuse Processor
The P4080 implements the QorIQ platform’s Trust Architecture, supporting capabilities such as secure
boot. Use of the Trust Architecture features is dependent on programming fuses in the Security Fuse
Processor (SFP). The details of the Trust Architecture and SFP can be found in the P4080 QorIQ
Integrated Multicore Communication Processor Family Reference Manual.
In order to program SFP fuses, the user is required to supply 1.5V to the POVDD pin per Section 2.2
”Power Sequencing” on page 52 POVDD should only be powered for the duration of the fuse
programming cycle, with a per device limit of two fuse programming cycles. All other times POVDD
should be connected to GND. The sequencing requirements for raising and lowering POVDD are shown
in Figure 2-2 on page 53. To ensure device reliability, fuse programming must be performed within the
recommended fuse programming temperature range per Table 2-2 on page 49.
Users not implementing the QorIQ platform’s Trust Architecture features are not required to program
fuses and should connect POVDD to GND.
6. Ordering Information
Table provides the e2v part numbering nomenclature for the P4080. Note that the individual part
numbers correspond to a maximum processor core frequency. For available frequencies, contact your
local e2v sales office. Each part number also contains a revision code which refers to the die mask
revision number.
Notes: 1. For availability of the different versions, contact your local e2v sales office.
2. The letter X in the part number designates a "Prototype" product that has not been qualified by e2v. Reliability of a PCX part-
number is not guaranteed and such part-number shall not be used in Flight Hardware. Product changes may still occur while
shipping prototypes.
3. Processor core frequencies supported by parts addressed by this specification only. Not all parts described in this
specification support all core frequencies. Additionally, parts addressed by part number specifications may support other
maximum core frequencies.
p4nnn t en c d r
Generation
(1) Platform
Number of
Cores Derivative
Temperature
Range Encryption
Package
Type CPU Speed DDR Speed
Die
Revision
P(X)(2) =
45 nm 404 = 4 core
08 = 8 core 0
V: Tc = –40°C
TJ = 110°C
F: Tc = –40°C
TJ = 125°C
M: Tc = –55°C
TJ = 125°C
E = SEC
Present
N = SEC
Not Present
1 = FC-
PBGA
Pb free
3 = FC-
PBGA
SnPb
M= 1200 MHz
N = 1333 MHz
P= 1500 MHz
M = 1200 MHz
N = 1300 or
1333 MHz
B = Rev
2.0
145
1066A–HIREL–07/11
e2v semiconductors SAS 2011
P4080
7. Definitions
7.1 Life Support Applications
These products are not designed for use in life support appliances, devices or systems where
malfunction of these products can reasonably be expected to result in personal injury. e2v customers
using or selling these products for use in such applications do so at their own risk and agree to fully
indemnify e2v for any damages resulting from such improper use or sale.
8. Document Revision History
Table 8-1 provides a revision history for the P2020 hardware specification.
Table 8-1. Document Revision History
Rev. No Date Substantive Change(s)
1066A 04/2011 Initial revision.
146
1066A–HIREL–07/11
P4080
e2v semiconductors SAS 2011
i
1066A–HIREL–07/11
e2v semiconductors SAS 2011
P4080
Table of Contents
1 Pin Assignments and Reset States ........................................................ 2
1.1 1295 FC-PBGA Ball Layout Diagrams ..................................................................2
1.2 Pinout List ..............................................................................................................8
2 Electrical Characteristics ...................................................................... 47
2.1 Overall DC Electrical Characteristics .................................................................. 47
2.2 Power Sequencing ..............................................................................................52
2.3 Power Down Requirements ................................................................................. 54
2.4 Power Characteristics .........................................................................................54
2.5 Thermal ............................................................................................................... 56
2.6 Input Clocks .........................................................................................................56
2.7 RESET Initialization .............................................................................................59
2.8 Power-on Ramp Rate ..........................................................................................59
2.9 DDR2 and DDR3 SDRAM Controller ..................................................................60
2.10 eSPI .....................................................................................................................68
2.11 DUART ................................................................................................................ 70
2.12 Ethernet: Data Path Three-Speed Ethernet (dTSEC), Management Interface 1
and 2, IEEE Std 1588™ ...................................................................................71
2.13 USB ..................................................................................................................... 77
2.14 Enhanced Local Bus Interface ............................................................................80
2.15 Enhanced Secure Digital Host Controller (eSDHC) ............................................ 85
2.16 Programmable Interrupt Controller (PIC) Specifications .....................................86
2.17 JTAG Controller ................................................................................................... 87
2.18 I2C .......................................................................................................................89
2.19 GPIO ...................................................................................................................91
2.20 High-Speed Serial Interfaces (HSSI) ...................................................................93
3 Hardware Design Considerations ...................................................... 120
3.1 System Clocking ................................................................................................120
3.2 Supply Power Setting ........................................................................................ 128
3.3 Power Supply Design ........................................................................................ 129
3.4 Decoupling Recommendations .........................................................................130
3.5 SerDes Block Power Supply Decoupling Recommendations ...........................131
3.6 Connection Recommendations .........................................................................131
3.7 Recommended Thermal Model .........................................................................140
3.8 Thermal Management Information ....................................................................140
ii
1066A–HIREL–07/11
P4080
e2v semiconductors SAS 2011
4 Package Information ........................................................................... 142
4.1 Package Parameters for the P4080 FC-PBGA .................................................142
4.2 Mechanical Dimensions of the P4080 FC-PBGA .............................................. 142
5 Security Fuse Processor ..................................................................... 144
6 Ordering Information ........................................................................... 144
7 Definitions ............................................................................................ 145
7.1 Life Support Applications ................................................................................... 145
8 Document Revision History ................................................................ 145
Table of Contents ...................................................................................... i
1066A–HIREL–07/11
e2v semiconductors SAS 2011
Whilst e2v has taken care to ensure the accuracy of the information contained herein it accepts no responsibility for the consequences of any use thereof
and also reserves the right to change the specification of goods without notice. e2v accepts no liability beyond that set out in its standard conditions of sale
in respect of infringement of third party patents arising from the use of tubes or other devices in accordance with information contained herein.
How to reach us
Home page: www.e2v.com
Sales offices:
Europe Regional sales office
e2v ltd
106 Waterhouse Lane
Chelmsford Essex CM1 2QU
England
Tel: +44 (0)1245 493493
Fax: +44 (0)1245 492492
mailto: enquiries@e2v.com
e2v sas
16 Burospace
F-91572 Bièvres Cedex
France
Tel: +33 (0) 16019 5500
Fax: +33 (0) 16019 5529
mailto: enquiries-fr@e2v.com
e2v gmbh
Industriestraße 29
82194 Gröbenzell
Germany
Tel: +49 (0) 8142 41057-0
Fax: +49 (0) 8142 284547
mailto: enquiries-de@e2v.com
Americas
e2v inc
520 White Plains Road
Suite 450 Tarrytown, NY 10591
USA
Tel: +1 (914) 592 6050 or 1-800-342-5338,
Fax: +1 (914) 592-5148
mailto: enquiries-na@e2v.com
Asia Pacific
e2v ltd
11/F.,
Onfem Tower,
29 Wyndham Street,
Central, Hong Kong
Tel: +852 3679 364 8/9
Fax: +852 3583 1084
mailto: enquiries-ap@e2v.com
Product Contact:
e2v
Avenue de Rochepleine
BP 123 - 38521 Saint-Egrève Cedex
France
Tel: +33 (0)4 76 58 30 00
Hotline:
mailto: std-hotline@e2v.com
iv
1066A–HIREL–07/11
P4080
e2v semiconductors SAS 2011
