Revision 13 ProASIC3L Low Power Flash FPGAs with Flash*Freeze Technology Features and Benefits Low Power * Dramatic Reduction in Dynamic and Static Power Savings * 1.2 V to 1.5 V Core and I/O Voltage Support for Low Power * Low Power Consumption in Flash*Freeze Mode Allows for Instantaneous Entry to / Exit from Low-Power Flash*Freeze Mode * Supports Single-Voltage System Operation * Low-Impedance Switches High Capacity * 250,000 to 3,000,000 System Gates * Up to 504 kbits of True Dual-Port SRAM * Up to 620 User I/Os Reprogrammable Flash Technology * 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process * Instant On Level 0 Support * Single-Chip Solution * Retains Programmed Design when Powered Off High Performance * 350 MHz (1.5 V systems) and 250 MHz (1.2 V systems) System Performance * 3.3 V, 66 MHz, 66-Bit PCI (1.5 V systems) and 66 MHz, 32-Bit PCI (1.2 V systems) In-System Programming (ISP) and Security * ISP Using On-Chip 128-Bit Advanced Encryption Standard (AES) Decryption via JTAG (IEEE 1532-compliant) * FlashLock(R) to Secure FPGA Contents High-Performance Routing Hierarchy * Segmented, Hierarchical Routing and Clock Structure * High-Performance, Low-Skew Global Network * Architecture Supports Ultra-High Utilization Advanced and Pro (Professional) I/Os * 700 Mbps DDR, LVDS-Capable I/Os * 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation * Bank-Selectable I/O Voltages--up to 8 Banks per Chip Table 1 * ProASIC3 Low-Power Product Family ProASIC3L Devices A3P250L VersaTiles (D-flip-flops) RAM Kbits (1,024 bits) 4,608-Bit Blocks FlashROM Kbits Secure (AES) ISP 2 Integrated PLL in CCCs 3 VersaNet Globals I/O Banks Maximum User I/Os Package Pins VQFP PQFP FBGA Clock Conditioning Circuit (CCC) and PLL * Six CCC Blocks, One with Integrated PLL (ProASIC3L) and All with Integrated PLL (ProASIC3EL) * Configurable Phase Shift, Multiply/Divide, Delay Capabilities, and External Feedback * Wide Input Frequency Range 1.5 MHz to 250 MHz (1.2 V systems) and 350 MHz (1.5 V systems)) SRAMs and FIFOs * Variable-Aspect-Ratio 4,608-Bit RAM Blocks (x1, x2, x4, x9, and x18 organizations available) * True Dual-Port SRAM (except x18) * 24 SRAM and FIFO Configurations with Synchronous Operation: - 250 MHz: For 1.2 V systems - 350 MHz: For 1.5 V systems ARM(R) Processor Support in ProASIC3L FPGAs * ARM CortexTM-M1 Soft Processor Available with or without Debug A3P600L A3P1000L A3PE3000L M1A3P600L M1A3P1000L M1A3PE3000L 250,000 6,144 36 8 1 Yes 1 18 4 157 600,000 13,824 108 24 1 Yes 1 18 4 235 1,000,000 24,576 144 32 1 Yes 1 18 4 300 3,000,000 75,264 504 112 1 Yes 6 18 8 620 VQ100 PQ208 FG144, FG256 PQ208 FG144, FG256, FG484 PQ208 FG144, FG256, FG484 PQ208 3 FG324, FG484, FG896 ARM Cortex-M1 Devices 1 System Gates * Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V / 2.5 V / 1.8 V / 1.5 V / 1.2 V, 3.3 V PCI / 3.3 V PCI-X, and LVCMOS 2.5 V / 5.0 V Input * Differential I/O Standards: LVPECL, LVDS, B-LVDS, and M-LVDS * Voltage-Referenced I/O Standards: GTL+ 2.5 V / 3.3 V, GTL 2.5 V / 3.3 V, HSTL Class I and II, SSTL2 Class I and II, SSTL3 Class I and II (A3PE3000L only) * Wide Range Power Supply Voltage Support per JESD8-B, Allowing I/Os to Operate from 2.7 V to 3.6 V * Wide Range Power Supply Voltage Support per JESD8-12, Allowing I/Os to Operate from 1.14 V to 1.575 V * I/O Registers on Input, Output, and Enable Paths * Hot-Swappable and Cold-Sparing I/Os Programmable Output Slew Rate and Drive Strength * Programmable Input Delay (A3PE3000L only) * Schmitt Trigger Option on Single-Ended Inputs (A3PE3000L) * Weak Pull-Up/-Down * IEEE 1149.1 (JTAG) Boundary Scan Test * Pin-Compatible Packages across the ProASIC(R)3L Family (except PQ208) Notes: 1. Refer to the Cortex-M1 product brief for more information. 2. AES is not available for ARM Cortex-M1 ProASIC3L devices. 3. For the A3PE3000L, the PQ208 package has six CCCs and two PLLs. January 2013 (c) 2013 Microsemi Corporation I ProASIC3L Low Power Flash FPGAs I/Os Per Package 1 ProASIC3L Low-Power Devices A3P250L 2 ARM Cortex-M1 Devices A3P600L A3P1000L A3PE3000L M1A3P600L M1A3P1000L M1A3PE3000L 3 I/O Type SingleEnded I/O 4 Differential I/O Pairs Differential I/O Pairs SingleEnded I/O 4 Differential I/O Pairs SingleEnded I/O 4 Differential I/O Pairs VQ100 68 13 - - - - - PQ208 151 34 154 35 154 35 147 65 FG144 97 24 97 25 97 25 FG256 157 38 177 43 177 44 - - FG324 - - - - - - 221 110 FG484 - - 235 60 300 74 341 168 FG896 - - - - - - 620 310 Package SingleEnded I/O 4 Notes: 1. When considering migrating your design to a lower- or higher-density device, refer to the packaging section of the datasheet to ensure you are complying with design and board migration requirements. 2. For A3P250L devices, the maximum number of LVPECL pairs in east and west banks cannot exceed 15. 3. ARM Cortex-M1 support is TBD on this device. 4. Each used differential I/O pair reduces the number of single-ended I/Os available by two. 5. FG256 and FG484 are footprint-compatible packages. 6. "G" indicates RoHS-compliant packages. Refer to "ProASIC3L Ordering Information" on page III for the location of the "G" in the part number. 7. For A3PE3000L devices, the usage of certain I/O standards is limited as follows: - SSTL3(I) and (II): up to 40 I/Os per north or south bank - LVPECL / GTL+ 3.3 V / GTL 3.3 V: up to 48 I/Os per north or south bank - SSTL2(I) and (II) / GTL+ 2.5 V/ GTL 2.5 V: up to 72 I/Os per north or south bank 8. When the Flash*Freeze pin is used to directly enable Flash*Freeze mode and not as a regular I/O, the number of single-ended user I/Os available is reduced by one. Table 2 * ProASIC3L FPGAs Package Sizes Dimensions Package VQ100 PQ208 FG144 FG256 FG324 FG484 FG896 Length x Width (mm\mm) 14 x 14 28 x 28 13 x 13 17 x 17 19 x 19 23 x 23 31 x 31 Nominal Area (mm2) 196 784 169 289 361 529 961 Pitch (mm) 0.5 0.5 1.0 1.0 1.0 1.0 1.0 Height (mm) 1.00 3.40 1.45 1.60 1.63 2.23 2.23 II R evis i o n 13 ProASIC3L Low Power Flash FPGAs ProASIC3L Ordering Information A3P1000L _ 1 FG G 144 Y I Application (Temperature Range) Blank = Commercial (0C to +70C Ambient Temperature) I = Industrial (-40C to +85C Ambient Temperature) Security Feature Y = Device Includes License to Implement IP Based on the Cryptography Research, Inc. (CRI) Patent Portfolio Blank = Device Does Not Include License to Implement IP Based on the Cryptography Research, Inc. (CRI) Patent Portfolio Package Lead Count Lead-Free Packaging Blank = Standard Packaging G= RoHS-Compliant (Green) Packaging Package Type VQ = Very Thin Quad Flat Pack (0.5 mm pitch) PQ = Plastic Quad Flat Pack (0.5 mm pitch) FG = Fine Pitch Ball Grid Array (1.0 mm pitch) Speed Grade Blank = Standard 1 = 15% Faster than Standard Part Number ProASIC3L Devices A3P250L = 250,000 System Gates A3P600L = 600,000 System Gates A3P1000L = 1,000,000 System Gates A3PE3000L = 3,000,000 System Gates ProASIC3L Devices with Cortex-M1 M1A3P600L = 600,000 System Gates M1A3P1000L = 1,000,000 System Gates M1A3PE3000L = 3,000,000 System Gates R ev i si o n 1 3 III ProASIC3L Low Power Flash FPGAs Temperature Grade Offerings Package A3P250L ARM Cortex-M1 Devices A3P600L A3P1000L A3PE3000L M1A3P600L M1A3P1000L M1A3PE3000L VQ100 C, I - - PQ208 C, I C, I C, I FG144 C, I C, I C, I FG256 C, I C, I C, I FG324 - - - C, I FG484 - C, I C, I C, I FG896 - - - C, I C, I Notes: 1. C = Commercial temperature range: 0C to 70C ambient temperature. 2. I = Industrial temperature range: -40C to 85C ambient temperature. Speed Grade and Temperature Grade Matrix Temperature Grade Std. -1 C1 3 3 2 3 3 I Notes: 1. C = Commercial temperature range: 0C to 70C ambient temperature. 2. I = Industrial temperature range: -40C to 85C ambient temperature. ProASIC3L Device Status ProASIC3L Devices Status M1 ProASIC3L Devices Status Production M1A3P600L Production A3P1000L Production M1A3P1000L Production A3P3000L Production M1A3P3000L Production A3P250L Production A3P600L Contact your local Microsemi SoC Products Group representative for device availability: http://www.microsemi.com/soc/contact/default.aspx. IV Revision 13 ProASIC3L Low Power Flash FPGAs Table of Contents ProASIC3L Device Family Overview General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 ProASIC3L DC and Switching Characteristics General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Calculating Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 User I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 VersaTile Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-121 Global Resource Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-127 Clock Conditioning Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-132 Embedded SRAM and FIFO Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-134 Embedded FlashROM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-148 JTAG 1532 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-149 Pin Descriptions and Packaging Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . User Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Special Function Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3-2 3-4 3-5 3-5 3-5 Package Pin Assignments VQ100 PQ208 FG144 FG256 FG324 FG484 FG896 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-50 Datasheet Information List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 R ev i si o n 1 3 V 1 - ProASIC3L Device Family Overview General Description The ProASIC3L family of Microsemi flash FPGAs dramatically reduces dynamic power consumption by 40% and static power by 50% compared to the equivalent ProASIC3 device. These power savings are coupled with performance, density, true single-chip, 1.2 V to 1.5 V core and I/O operation as low as 1.2 V, reprogrammability, and advanced features. Using Microsemi's proven Flash*Freeze technology enables users to shut off dynamic power instantaneously and switch the device to static mode without the need to switch off clocks or power supplies while retaining internal states of the device. This greatly simplifies power management on a board done through I/Os and clocks. In addition, optimized software tools using power-driven layout provide instant push-button power reduction. Nonvolatile flash technology gives ProASIC3L devices the advantage of being a secure, low-power, single-chip solution that is Instant On. ProASIC3L offers dramatic dynamic power savings giving the FPGA users flexibility to combine low power with high performance. These features enable designers to create high-density systems using existing ASIC or FPGA design flows and tools. ProASIC3L devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM storage as well as clock conditioning circuitry (CCC) based on an integrated phase-locked loop (PLL). ProASIC3L devices support devices from 250 k system gates to 3 million system gates with up to 504 kbits of true dual-port SRAM and 620 user I/Os. M1 ProASIC3L devices support the high-performance, 32-bit Cortex-M1 processor developed by ARM for implementation in FPGAs. ARM Cortex-M1 is a soft processor that is fully implemented in the FPGA fabric. It has a three-stage pipeline that offers a good balance between low-power consumption and speed when implemented in an M1 ProASIC3L device. The processor runs the ARMv6-M instruction set, has a configurable nested interrupt controller, and can be implemented with or without the debug block. ARM Cortex-M1 is available for free from Microsemi for use in M1 ProASIC3L FPGAs. The ARM-enabled devices have Microsemi SoC Products Group ordering numbers that begin with M1 and do not support AES decryption. Flash*Freeze Technology The ProASIC3L devices offer Microsemi's proven Flash*Freeze technology, which allows instantaneous switching from an active state to a static state. ProASIC3L devices do not need additional components to turn off I/Os or clocks while retaining the design information, SRAM content, and registers. Flash*Freeze technology is combined with in-system programmability, which enables users to quickly and easily upgrade and update their designs in the final stages of manufacturing or in the field. The ability of ProASIC3L devices to support a wide range core voltage (1.2 V to 1.5 V) allows for an even greater reduction in power consumption, which enables low total system power. When the ProASIC3L device enters Flash*Freeze mode, the device automatically shuts off the clocks and inputs to the FPGA core; when the device exits Flash*Freeze mode, all activity resumes and data is retained. The availability of low-power modes, combined with a reprogrammable, single-chip, single-voltage solution, make ProASIC3L devices suitable for low-power data transfer and manipulation in portable media, secure communications, radio applications as well as high performance portable, industrial, test, scientific, and medical applications. R ev i si o n 1 3 1 -1 ProASIC3L Device Family Overview Flash Advantages Low Power The ProASIC3L family of Microsemi flash-based FPGAs provide a low-power advantage, and when coupled with high performance, enables designers to make power-smart choices using a single-chip, reprogrammable, and Instant On device. ProASIC3L devices offer 40% dynamic power and 50% static power savings compared to the equivalent ProASIC3 device by reducing the core operating voltage to 1.2 V. In addition, the Power Driven Layout (PDL) feature in Libero(R) System-on-Chip (SoC) offers up to 30% additional power reduction over the standard timing-driven place-and-route (TDPR). With Flash*Freeze technology, ProASIC3L devices are able to retain device SRAM and logic while dynamic power is reduced to a minimum, without the need to stop clock or power supplies. Combining these features provides a low-power, feature-rich and highperformance solution. Security Nonvolatile, flash-based ProASIC3L devices do not require a boot PROM, so there is no vulnerable external bitstream that can be easily copied. ProASIC3L devices incorporate FlashLock, which provides a unique combination of reprogrammability and design security without external overhead, advantages that only an FPGA with nonvolatile flash programming can offer. ProASIC3L devices utilize a 128-bit flash-based lock and a separate AES key to provide the highest level of protection in the FPGA industry for programmed intellectual property and configuration data. In addition, all FlashROM data in ProASIC3L devices can be encrypted prior to loading, using the industryleading AES-128 (FIPS192) bit block cipher encryption standard. AES was adopted by the National Institute of Standards and Technology (NIST) in 2000 and replaces the 1977 DES standard. ProASIC3L devices have a built-in AES decryption engine and a flash-based AES key that make them the most comprehensive programmable logic device security solution available today. ProASIC3L devices with AES-based security provide a high level of protection for remote field updates over public networks such as the Internet, and are designed to ensure that valuable IP remains out of the hands of system overbuilders, system cloners, and IP thieves. Security, built into the FPGA fabric, is an inherent component of the ProASIC3L family. The flash cells are located beneath seven metal layers, and many device design and layout techniques have been used to make invasive attacks extremely difficult. The ProASIC3L family, with FlashLock and AES security, is unique in being highly resistant to both invasive and noninvasive attacks. Your valuable IP is protected with industry-standard security, making remote ISP possible. A ProASIC3L device provides the best available security for programmable logic designs. Single Chip Flash-based FPGAs store their configuration information in on-chip flash cells. Once programmed, the configuration data is an inherent part of the FPGA structure, and no external configuration data needs to be loaded at system power-up (unlike SRAM-based FPGAs). Therefore, flash-based ProASIC3L FPGAs do not require system configuration components such as EEPROMs or microcontrollers to load device configuration data. This reduces bill-of-materials costs and PCB area, and increases security and system reliability. Instant On Flash-based ProASIC3L devices support Level 0 of the Instant On classification standard. This feature helps in system component initialization, execution of critical tasks before the processor wakes up, setup and configuration of memory blocks, clock generation, and bus activity management. The Instant On feature of flash-based ProASIC3L devices greatly simplifies total system design and reduces total system cost, often eliminating the need for CPLDs and clock generation PLLs. In addition, glitches and brownouts in system power will not corrupt the ProASIC3L device's flash configuration, and unlike SRAM-based FPGAs, the device will not have to be reloaded when system power is restored. This enables the reduction or complete removal of the configuration PROM, expensive voltage monitor, brownout detection, and clock generator devices from the PCB design. Flash-based ProASIC3L devices simplify total system design and reduce cost and design risk while increasing system reliability and improving system initialization time. 1- 2 R ev isio n 1 3 ProASIC3L Low Power Flash FPGAs Reduced Cost of Ownership Advantages to the designer extend beyond low unit cost, performance, and ease of use. Unlike SRAMbased FPGAs, flash-based ProASIC3L devices allow all functionality to be Instant On; no external boot PROM is required. On-board security mechanisms prevent access to all the programming information and enable secure remote updates of the FPGA logic. Designers can perform secure remote in-system reprogramming to support future design iterations and field upgrades with confidence that valuable intellectual property cannot be compromised or copied. Secure ISP can be performed using the industrystandard AES algorithm. The ProASIC3L family device architecture mitigates the need for ASIC migration at higher user volumes. This makes the ProASIC3L family a cost-effective ASIC replacement solution, manipulation in portable media and secure communications, radio applications as well as high performance portable Industrial, test, scientific and medical applications. Firm-Error Immunity Firm errors occur most commonly when high-energy neutrons, generated in the upper atmosphere, strike a configuration cell of an SRAM FPGA. The energy of the collision can change the state of the configuration cell and thus change the logic, routing, or I/O behavior in an unpredictable way. These errors are impossible to prevent in SRAM FPGAs. The consequence of this type of error can be a complete system failure. Firm errors do not exist in the configuration memory of ProASIC3L flash-based FPGAs. Once it is programmed, the flash cell configuration element of ProASIC3L FPGAs cannot be altered by high-energy neutrons and is therefore immune to them. Recoverable (or soft) errors occur in the user data SRAM of all FPGA devices. These can easily be mitigated by using error detection and correction (EDAC) circuitry built into the FPGA fabric. Advanced Flash Technology The ProASIC3L family offers many benefits, including nonvolatility and reprogrammability, through an advanced flash-based, 130-nm LVCMOS process with 7 layers of metal. Standard CMOS design techniques are used to implement logic and control functions. The combination of fine granularity, enhanced flexible routing resources, and abundant flash switches allows for very high logic utilization without compromising device routability or performance. Logic functions within the device are interconnected through a four-level routing hierarchy. Advanced Architecture The proprietary ProASIC3L architecture provides granularity comparable to standard-cell ASICs. The ProASIC3L device consists of five distinct and programmable architectural features (Figure 1-1 on page 1-4 and Figure 1-2 on page 1-4): * FPGA VersaTiles * Dedicated FlashROM * Dedicated SRAM/FIFO memory * Extensive CCCs and PLLs * I/O structure The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input logic function, a D-flip-flop (with or without enable), or a latch by programming the appropriate flash switch interconnections. The versatility of the ProASIC3L core tile, as either a three-input lookup table (LUT) equivalent or a D-flip-flop/latch with enable, allows for efficient use of the FPGA fabric. The VersaTile capability is unique to the ProASIC family of third-generation-architecture flash FPGAs. VersaTiles are connected with any of the four levels of routing hierarchy. Flash switches are distributed throughout the device to provide nonvolatile, reconfigurable interconnect programming. Maximum core utilization is possible for virtually any design. R ev i si o n 1 3 1 -3 ProASIC3L Device Family Overview Bank 0 Bank 1 Bank 3 CCC RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block I/Os Bank 1 Bank 3 VersaTile ISP AES Decryption* User Nonvolatile FlashRom Flash*Freeze Technology Charge Pumps RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block (A3P600L and A3P1000L) Bank 2 Figure 1-1 * ProASIC3L Device Architecture Overview with Four I/O Banks (A3P250L, A3P600L, and A3P1000L) CCC RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block Pro I/Os VersaTile ISP AES Decryption* Figure 1-2 * 1- 4 User Nonvolatile FlashRom Flash*Freeze Technology Charge Pumps ProASIC3EL Device Architecture Overview R ev isio n 1 3 RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block ProASIC3L Low Power Flash FPGAs Flash*Freeze Technology The ProASIC3L devices offer Microsemi's proven Flash*Freeze technology, which enables designers to instantaneously shut off dynamic power consumption while retaining all SRAM and register information. Flash*Freeze technology enables the user to quickly (within 1 s) enter and exit Flash*Freeze mode by activating the Flash*Freeze (FF) pin while all power supplies are kept at their original values. In addition, I/Os and global I/Os can still be driven and can be toggling without impact on power consumption; clocks can still be driven or can be toggling without impact on power consumption; and the device retains all core registers, SRAM information, and states. I/O states are tristated during Flash*Freeze mode or can be set to a certain state using weak pull-up or pull-down I/O attribute configuration. No power is consumed by the I/O banks, clocks, JTAG pins, or PLL. Flash*Freeze technology allows the user to switch to active mode on demand, thus simplifying the power management of the device. The FF pin (active low) can be routed internally to the core to allow the user's logic to decide when it is safe to transition to this mode. It is also possible to use the FF pin as a regular I/O if Flash*Freeze mode usage is not planned, which is advantageous because of the inherent low-power static and dynamic capabilities of the ProASIC3L device. Refer to Figure 1-3 for an illustration of entering/exiting Flash*Freeze mode. ProASIC3L FPGA Flash*Freeze Mode Control Flash*Freeze Pin Figure 1-3 * ProASIC3L Flash*Freeze Mode VersaTiles The ProASIC3L core consists of VersaTiles, which have been enhanced beyond the ProASICPLUS(R) core tiles. The ProASIC3L VersaTile supports the following: * All 3-input logic functions--LUT-3 equivalent * Latch with clear or set * D-flip-flop with clear or set * Enable D-flip-flop with clear or set Refer to Figure 1-4 for VersaTile configurations. LUT-3 Equivalent X1 X2 X3 LUT-3 Y D-Flip-Flop with Clear or Set Data CLK CLR Y D-FF Enable D-Flip-Flop with Clear or Set Data CLK Y D-FF Enable CLR Figure 1-4 * VersaTile Configurations R ev i si o n 1 3 1 -5 ProASIC3L Device Family Overview User Nonvolatile FlashROM ProASIC3L devices have 1 kbit of on-chip, user-accessible, nonvolatile FlashROM. The FlashROM can be used in diverse system applications: * Internet Protocol addressing (wireless or fixed) * System calibration settings * Device serialization and/or inventory control * Subscription-based business models (for example, set-top boxes) * Secure key storage for secure communications algorithms * Asset management/tracking * Date stamping * Version management The FlashROM is written using the standard ProASIC3L IEEE 1532 JTAG programming interface.The core can be individually programmed (erased and written), and on-chip AES decryption can be used selectively to securely load data over public networks, as in security keys stored in the FlashROM for a user design. The FlashROM can be programmed via the JTAG programming interface, and its contents can be read back either through the JTAG programming interface or via direct FPGA core addressing. Note that the FlashROM can only be programmed from the JTAG interface and cannot be programmed from the internal logic array. The FlashROM is programmed as 8 banks of 128 bits; however, reading is performed on a byte-by-byte basis using a synchronous interface. A 7-bit address from the FPGA core defines which of the 8 banks and which of the 16 bytes within that bank are being read. The three most significant bits (MSBs) of the FlashROM address determine the bank, and the four least significant bits (LSBs) of the FlashROM address define the byte. The ProASIC3L development software solutions, Libero SoC and Designer, have extensive support for the FlashROM. One such feature is auto-generation of sequential programming files for applications requiring a unique serial number in each part. Another feature allows the inclusion of static data for system version control. Data for the FlashROM can be generated quickly and easily using Libero SoC and Designer software tools. Comprehensive programming file support is also included to allow for easy programming of large numbers of parts with differing FlashROM contents. SRAM and FIFO ProASIC3L devices have embedded SRAM blocks along their north and south sides. Each variableaspect-ratio SRAM block is 4,608 bits in size. Available memory configurations are 256x18, 512x9, 1kx4, 2kx2, and 4kx1 bits. The individual blocks have independent read and write ports that can be configured with different bit widths on each port. For example, data can be sent through a 4-bit port and read as a single bitstream. The embedded SRAM blocks can be initialized via the device JTAG port (ROM emulation mode) using the UJTAG macro. In addition, every SRAM block has an embedded FIFO control unit. The control unit allows the SRAM block to be configured as a synchronous FIFO without using additional core VersaTiles. The FIFO width and depth are programmable. The FIFO also features programmable Almost Empty (AEMPTY) and Almost Full (AFULL) flags in addition to the normal Empty and Full flags. The embedded FIFO control unit contains the counters necessary for generation of the read and write address pointers. The embedded SRAM/FIFO blocks can be cascaded to create larger configurations. PLL and CCC ProASIC3L devices provide designers with flexible clock conditioning circuit (CCC) capabilities. Each member of the ProASIC3L family contains six CCCs. One CCC (center west side) has a PLL. The six CCC blocks are located at the four corners and the centers of the east and west sides. One CCC (center west side) has a PLL. All six CCC blocks are usable; the four corner CCCs and the east CCC allow simple clock delay operations as well as clock spine access. The inputs of the six CCC blocks are accessible from the FPGA core or from one of several inputs located near the CCC that have dedicated connections to the CCC block. 1- 6 R ev isio n 1 3 ProASIC3L Low Power Flash FPGAs The CCC block has these key features: * Wide input frequency range (fIN_CCC) = 1.5 MHz up to 250 MHz * Output frequency range (fOUT_CCC) = 0.75 MHz up to 250 MHz * 2 programmable delay types for clock skew minimization * Clock frequency synthesis Additional CCC specifications: * Internal phase shift = 0, 90, 180, and 270. Output phase shift depends on the output divider configuration. * Output duty cycle = 50% 1.5% or better * Low output jitter: worst case < 2.5% x clock period peak-to-peak period jitter when single global network used * Maximum acquisition time is 300 s * Exceptional tolerance to input period jitter-- allowable input jitter is up to 1.5 ns * Four precise phases; maximum misalignment between adjacent phases of 40 ps x 250 MHz / fOUT_CCC Global Clocking ProASIC3L devices have extensive support for multiple clocking domains. In addition to the CCC and PLL support described above, there is a comprehensive global clock distribution network. Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three quadrant global networks. The VersaNets can be driven by the CCC or directly accessed from the core via multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for rapid distribution of high-fanout nets. I/Os with Advanced I/O Standards The ProASIC3L family of FPGAs features a flexible I/O structure, supporting a range of voltages (1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.0 V wide range, and 3.3 V). ProASIC3L FPGAs support different I/O standards, including single-ended, differential, and voltage-referenced (ProASIC3EL only). The I/Os are organized into banks, with two, four, or eight (ProASIC3EL only) banks per device. The configuration of these banks determines the I/O standards supported (Table 1-1). For ProASIC3EL, each I/O bank is subdivided into VREF minibanks, which are used by voltage-referenced I/Os. VREF minibanks contain 8 to 18 I/Os. All the I/Os in a given minibank share a common VREF line. Therefore, if any I/O in a given VREF minibank is configured as a VREF pin, the remaining I/Os in that minibank will be able to use that reference voltage. Table 1-1 * I/O Standards Supported I/O Standards Supported I/O Bank Type Device and Bank Location Pro I/Os A3PE3000L 3 3 3 3 A3P250L, A3P600L, A3P1000L 3 3 3 Not supported Advanced I/Os LVTTL/ PCI/ LVPECL, LVDS, LVCMOS PCI-X B-LVDS, M-LVDS GTL+ 2.5 V/3.3 V, GTL 2.5 V/3.3 V, HSTL I and II, SSTL2 I and II, SSTL3 I and II Each I/O module contains several input, output, and enable registers. These registers allow the implementation of the following: * Single-data-rate applications (e.g., PCI 66 MHz, bidirectional SSTL 2 and 3, Class I and II) * Double-data-Rate applications (e.g., DDR LVDS, B-LVDS, and M-LVDS I/Os for point-to-point communications, and DDR 200 MHz SRAM using bidirectional HSTL Class II). ProASIC3L banks support LVPECL, LVDS, B-LVDS, and M-LVDS. B-LVDS and M-LVDS can support up to 20 loads. R ev i si o n 1 3 1 -7 ProASIC3L Device Family Overview Hot-swap (also called hot-plug, or hot-insertion) is the operation of hot-insertion or hot-removal of a card in a powered-up system. Cold-sparing (also called cold-swap) refers to the ability of a device to leave system data undisturbed when the system is powered up, while the component itself is powered down, or when power supplies are floating. Wide Range I/O Support ProASIC3L devices support JEDEC-defined wide range I/O operation. ProASIC3L devices support both the JESD8-B specification, covering 3 V and 3.3 V supplies, for an effective operating range of 2.7 V to 3.6 V, and JESD8-12 with its 1.2 V nominal, supporting an effective operating range of 1.14 V to 1.575 V. Wider I/O range means designers can eliminate power supplies or power conditioning components from the board or move to less costly components with greater tolerances. Wide range eases I/O bank management and provides enhanced protection from system voltage spikes, while providing the flexibility to easily run custom voltage applications. Specifying I/O States During Programming You can modify the I/O states during programming in FlashPro. In FlashPro, this feature is supported for PDB files generated from Designer v8.5 or greater. See the FlashPro User's Guide for more information. Note: PDB files generated from Designer v8.1 to Designer v8.4 (including all service packs) have limited display of Pin Numbers only. 1. Load a PDB from the FlashPro GUI. You must have a PDB loaded to modify the I/O states during programming. 2. From the FlashPro GUI, click PDB Configuration. A FlashPoint - Programming File Generator window appears. 3. Click the Specify I/O States During Programming button to display the Specify I/O States During Programming dialog box. 4. Sort the pins as desired by clicking any of the column headers to sort the entries by that header. Select the I/Os you wish to modify (Figure 1-5 on page 1-9). 5. Set the I/O Output State. You can set Basic I/O settings if you want to use the default I/O settings for your pins, or use Custom I/O settings to customize the settings for each pin. Basic I/O state settings: 1 - I/O is set to drive out logic High 0 - I/O is set to drive out logic Low Last Known State - I/O is set to the last value that was driven out prior to entering the programming mode, and then held at that value during programming Z -Tri-State: I/O is tristated 6. Click OK to return to the FlashPoint - Programming File Generator window. Note: I/O States during programming are saved to the ADB and resulting programming files after completing programming file generation. 1- 8 R ev isio n 1 3 ProASIC3L Low Power Flash FPGAs Figure 1-5 * I/O States During Programming Window R ev i si o n 1 3 1 -9 2 - ProASIC3L DC and Switching Characteristics General Specifications Operating Conditions Stresses beyond those listed in Table 2-1 may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings are stress ratings only; functional operation of the device at these or any other conditions beyond those listed under the Recommended Operating Conditions specified in Table 2-2 on page 2-2 is not implied. Table 2-1 * Symbol Absolute Maximum Ratings Parameter Limits Units VCC DC core supply voltage -0.3 to 1.65 V VJTAG JTAG DC voltage -0.3 to 3.75 V VPUMP Programming voltage -0.3 to 3.75 V VCCPLL Analog power supply (PLL) -0.3 to 1.65 V -0.3 to 3.75 V VCCI and DC I/O buffer supply voltage VMV 2 VI I/O input voltage -0.3 V to 3.6 V (when I/O hot insertion mode is enabled) V -0.3 V to (VCCI + 1 V) or 3.6 V, whichever voltage is lower (when I/O hot-insertion mode is disabled) TSTG 3 Storage temperature -65 to +150 C TJ 3 Junction temperature +125 C Notes: 1. The device should be operated within the limits specified by the datasheet. During transitions, the input signal may undershoot or overshoot according to the limits shown in Table 2-4 on page 2-3. 2. VMV pins must be connected to the corresponding VCCI pins. See the "VMVx I/O Supply Voltage (quiet)" section on page 3-1 for further information. 3. For flash programming and retention maximum limits, refer to Table 2-3 on page 2-2, and for recommended operating limits, refer to Table 2-2 on page 2-2. R ev i si o n 1 3 2 -1 ProASIC3L DC and Switching Characteristics Table 2-2 * Recommended Operating Conditions 1 Symbol Parameter Commercial Industrial Units 0 to +70 -40 to +85 C 0 to + 85 -40 to +100 C 1.14 to 1.575 1.14 to 1.575 V 1.4 to 3.6 1.4 to 3.6 V 3.15 to 3.45 3.15 to 3.45 V 0 to 3.6 0 to 3.6 V 1.14 to 1.575 1.14 to 1.575 V 1.14 to 1.26 1.14 to 1.26 V 1.5 V DC supply voltage 1.425 to 1.575 1.425 to 1.575 V 1.8 V DC supply voltage 1.7 to 1.9 1.7 to 1.9 V 2.3 to 2.7 2.3 to 2.7 V 2.7 to 3.6 2.7 to 3.6 V 3.0 to 3.6 3.0 to 3.6 V 2.375 to 2.625 2.375 to 2.625 V 3.0 to 3.6 3.0 to 3.6 V TA Ambient temperature TJ Junction Temperature VCC 2 1.2 V-1.5 V wide range core VJTAG JTAG DC voltage VPUMP 5 voltage 3 Programming voltage Programming Mode 4 Operation 5 VCCPLL 6 VCCI VMV 7 Analog power supply (PLL) 1.2 V-1.5 V wide range core voltage 3 and 1.2 V DC supply voltage8 2.5 V DC supply voltage 3.3 V wide range DC supply voltage 9 3.3 V DC supply voltage LVDS differential I/O LVPECL differential I/O Notes: 1. All parameters representing voltages are measured with respect to GND unless otherwise specified. 2. The ranges given here are for power supplies only. The recommended input voltage ranges specific to each I/O standard are given in Table 2-14 on page 2-10. VCCI should be at the same voltage within a given I/O bank. 3. All ProASIC3L devices must be programmed with the VCC core voltage at 1.5 V. 4. The programming temperature range supported is Tambient = 0C to 85C. 5. VPUMP can be left floating during normal operation (not programming mode). 6. VCCPLL pins should be tied to VCC pins. See the "VCCPLA/B/C/D/E/F PLL Supply Voltage" section on page 3-1 for further information. 7. VMV pins must be connected to the corresponding VCCI pins. See the "VMVx I/O Supply Voltage (quiet)" section on page 3-1 for further information. 8. For ProASIC(R)3L devices, VCCI VCC. 9. 3.3 V wide range is compliant to the JESD8-A specification and supports 3.0 V VCCI operation. Table 2-3 * Product Grade Flash Programming Limits - Retention, Storage, and Operating Temperature1 Programming Cycles Maximum Operating Program Retention Maximum Storage (biased/unbiased) Temperature TSTG (C) 2 Junction Temperature TJ (C) 2 Commercial 500 20 years 110 100 Industrial 500 20 years 110 100 Notes: 1. This is a stress rating only; functional operation at any condition other than those indicated is not implied. 2. These limits apply for program/data retention only. Refer to Table 2-1 on page 2-1 and Table 2-2 for device operating conditions and absolute limits. 2- 2 R ev isio n 1 3 ProASIC3L Low Power Flash FPGAs Table 2-4 * VCCI Overshoot and Undershoot Limits 1 Average VCCI-GND Overshoot or Undershoot Duration as a Percentage of Clock Cycle2 Maximum Overshoot/ Undershoot2 10% 1.4 V 5% 1.49 V 2.7 V or less 3V 3.3 V 3.6 V 10% 1.1 V 5% 1.19 V 10% 0.79 V 5% 0.88 V 10% 0.45 V 5% 0.54 V Notes: 1. Based on reliability requirements at junction temperature at 85C. 2. The duration is allowed at one out of six clock cycles. If the overshoot/undershoot occurs at one out of two cycles, the maximum overshoot/undershoot has to be reduced by 0.15 V. 3. This table does not provide PCI overshoot/undershoot limits. I/O Power-Up and Supply Voltage Thresholds for Power-On Reset (Commercial and Industrial) Sophisticated power-up management circuitry is designed into every ProASIC3 device. These circuits ensure easy transition from the powered-off state to the powered-up state of the device. The many different supplies can power up in any sequence with minimized current spikes or surges. In addition, the I/O will be in a known state through the power-up sequence. The basic principle is shown in Figure 2-1 on page 2-4 and Figure 2-2 on page 2-5. There are five regions to consider during power-up. ProASIC3 I/Os are activated only if ALL of the following three conditions are met: 1. VCC and VCCI are above the minimum specified trip points (Figure 2-1 on page 2-4 and Figure 2-2 on page 2-5). 2. VCCI > VCC - 0.75 V (typical) 3. Chip is in the operating mode. VCCI Trip Point: Ramping up: 0.6 V < trip_point_up < 1.2 V Ramping down: 0.5 V < trip_point_down < 1.1 V VCC Trip Point: Ramping up: 0.6 V < trip_point_up < 1.1 V Ramping down: 0.5 V < trip_point_down < 1 V VCC and VCCI ramp-up trip points are about 100 mV higher than ramp-down trip points. This specifically built-in hysteresis prevents undesirable power-up oscillations and current surges. Note the following: * During programming, I/Os become tristated and weakly pulled up to VCCI. * JTAG supply, PLL power supplies, and charge pump VPUMP supply have no influence on I/O behavior. R ev i si o n 1 3 2 -3 ProASIC3L DC and Switching Characteristics PLL Behavior at Brownout Condition Microsemi recommends using monotonic power supplies or voltage regulators to ensure proper powerup behavior. Power ramp-up should be monotonic at least until VCC and VCCPLX exceed brownout activation levels. The VCC activation level is specified as 1.1 V worst-case (see Figure 2-1 and Figure 22 on page 2-5 for more details). When PLL power supply voltage and/or VCC levels drop below the VCC brownout levels (0.75 V 0.25 V), the PLL output lock signal goes low and/or the output clock is lost. Refer to the "Power-Up/-Down Behavior of Low-Power Flash Devices" chapter of the ProASIC3L FPGA Fabric User's Guide for information on clock and lock recovery. Internal Power-Up Activation Sequence 1. Core 2. Input buffers Output buffers, after 200 ns delay from input buffer activation. VCC = VCCI + VT where VT can be from 0.58 V to 0.9 V (typically 0.75 V) VCC VCC = 1.575 V Region 4: I/O buffers are ON. I/Os are functional (except differential but slower because VCCI is below specification. For the same reason, input buffers do not meet VIH / VIL levels, and output buffers do not meet VOH / VOL levels. Region 1: I/O Buffers are OFF Region 5: I/O buffers are ON and power supplies are within specification. I/Os meet the entire datasheet and timer specifications for speed, VIH / VIL, VOH / VOL, etc. VCC = 1.425 V Region 2: I/O buffers are ON. I/Os are functional (except differential inputs) but slower because VCCI / VCC are below specification. For the same reason, input buffers do not meet VIH / VIL levels, and output buffers do not meet VOH / VOL levels. Activation trip point: Va = 0.85 V 0.25 V Deactivation trip point: Vd = 0.75 V 0.25 V Region 1: I/O buffers are OFF Activation trip point: Va = 0.9 V 0.3 V Deactivation trip point: Vd = 0.8 V 0.3 V Figure 2-1 * 2- 4 Region 3: I/O buffers are ON. I/Os are functional; I/O DC specifications are met, but I/Os are slower because the VCC is below specification. Min VCCI datasheet specification voltage at a selected I/O standard; i.e., 1.425 V or 1.7 V or 2.3 V or 3.0 V V5 Devices - I/O State as a Function of VCCI and VCC Voltage Levels R ev isio n 1 3 VCCI ProASIC3L Low Power Flash FPGAs VCC = VCCI + VT where VT can be from 0.58 V to 0.9 V (typically 0.75 V) VCC VCC = 1.575 V Region 4: I/O buffers are ON. I/Os are functional (except differential inputs) but slower because VCCI is below specification. For the same reason, input buffers do not meet VIH / VIL levels, and output buffers do not meet VOH / VOL levels. Region 1: I/O Buffers are OFF Region 5: I/O buffers are ON and power supplies are within specification. I/Os meet the entire datasheet and timer specifications for speed, VIH / VIL , VOH / VOL , etc. VCC = 1.14 V Region 2: I/O buffers are ON. I/Os are functional (except differential inputs) but slower because VCCI/VCC are below specification. For the same reason, input buffers do not meet VIH/VIL levels, and output buffers do not meet VOH/VOL levels. Activation trip point: Va = 0.85 V 0.2 V Deactivation trip point: Vd = 0.75 V 0.2 V Region 1: I/O buffers are OFF Activation trip point: Va = 0.9 V 0.15 V Deactivation trip point: Vd = 0.8 V 0.15 V Figure 2-2 * Region 3: I/O buffers are ON. I/Os are functional; I/O DC specifications are met, but I/Os are slower because the VCC is below specification. Min VCCI datasheet specification voltage at a selected I/O standard; i.e., 1.14 V,1.425 V, 1.7 V, 2.3 V, or 3.0 V VCCI V2 Devices - I/O State as a Function of VCCI and VCC Voltage Levels R ev i si o n 1 3 2 -5 ProASIC3L DC and Switching Characteristics Thermal Characteristics Introduction The temperature variable in the Designer software refers to the junction temperature, not the ambient temperature. This is an important distinction because dynamic and static power consumption cause the chip junction temperature to be higher than the ambient temperature. EQ 1 can be used to calculate junction temperature. TJ = Junction Temperature = T + TA EQ 1 where: TA = Ambient Temperature T = Temperature gradient between junction (silicon) and ambient T = ja * P ja = Junction-to-ambient of the package. ja numbers are located in Table 2-5. P = Power dissipation Package Thermal Characteristics The device junction-to-case thermal resistivity is jc and the junction-to-ambient air thermal resistivity is ja. The thermal characteristics for ja are shown for two air flow rates. The absolute maximum junction temperature is 100C. EQ 2 shows a sample calculation of the absolute maximum power dissipation allowed for a 484-pin FBGA package at commercial temperature and in still air. Max. junction temp. (C) - Max. ambient temp. (C) 100C - 70C Maximum Power Allowed = ------------------------------------------------------------------------------------------------------------------------------------------ = ------------------------------------- = 1.463 W ja (C/W) 20.5C/W EQ 2 Table 2-5 * Package Thermal Resistivities ja Device Pin Count jc Very Thin Quad Flat Pack (VQFP) All devices 100 10.0 35.3 29.4 27.1 C/W Plastic Quad Flat Pack (PQFP) All devices 208 8.0 26.1 22.5 20.8 C/W PQFP with embedded heatspreader All devices 208 3.8 16.2 13.3 11.9 C/W A3P250L 144 12.2 43.8 37.7 35.8 C/W A3P600L 144 8.3 35.8 30.2 28.3 C/W A3P1000L 144 6.3 31.6 26.2 24.2 C/W A3P250L 256 12.0 38.6 34.7 33.0 C/W A3P600L 256 8.5 32.0 27.5 25.8 C/W A3P1000L 256 6.6 28.1 24.4 22.7 C/W AGLE3000 324 TBD TBD TBD TBD C/W A3P600L 484 9.5 27.5 21.9 20.2 C/W A3P1000L 484 8.0 23.3 19.0 16.7 C/W A3PE3000L 484 4.7 20.6 15.7 14.0 C/W A3PE3000L 896 2.4 13.6 10.4 9.4 C/W Package Type Fine Pitch Ball Grid Array (FBGA) 2- 6 R ev isio n 1 3 Still Air 200 ft./min. 500 ft./min. Units ProASIC3L Low Power Flash FPGAs Temperature and Voltage Derating Factors Table 2-6 * Temperature and Voltage Derating Factors for Timing Delays (normalized to TJ = 70C, VCC = 1.14 V) Junction Temperature (C) -40C 0C 25C 70C 85C 110C 1.14 Array Voltage VCC (V) 0.90 0.94 0.96 1.00 1.01 1.03 1.2 0.87 0.90 0.92 0.96 0.97 0.99 1.26 0.83 0.86 0.88 0.92 0.93 0.85 1.3 0.81 0.84 0.86 0.90 0.91 0.93 1.35 0.78 0.81 0.83 0.87 0.88 0.89 1.4 0.75 0.78 0.80 0.83 0.84 0.86 1.425 0.74 0.77 0.78 0.82 0.83 0.85 1.5 0.70 0.72 0.74 0.77 0.79 0.80 1.575 0.67 0.70 0.72 0.75 0.76 0.77 Calculating Power Dissipation Quiescent Supply Current Quiescent supply current (IDD) calculation depends on multiple factors, including operating voltages (VCC, VCCI, and VJTAG), operating temperature, system clock frequency, and power mode usage. Microsemi recommends using the Power Calculator and SmartPower software estimation tools to evaluate the projected static and active power based on the user design, power mode usage, operating voltage, and temperature. Table 2-7 * Power Supply State per Mode Power Supply Configurations Modes/Power Supplies VCC VCCPLL VCCI VJTAG VPUMP Flash*Freeze On On On On On/off/floating Sleep Off Off On Off Off Shutdown Off Off Off Off Off No Flash*Freeze On On On On On/off/floating Note: Off: Power Supply level = 0 V Table 2-8 * Quiescent Supply Current (IDD) Characteristics, ProASIC3L Flash*Freeze Mode* Typical (25C) Core Voltage A3P250L A3P600L A3P1000L A3PE3000L Units 1.2 V 0.33 1.5 V 0.5 0.55 0.88 2.75 mA 0.83 1.33 4.2 mA Note: * IDD includes VCC, VPUMP, VCCI, VJTAG, and VCCPLL currents. R ev i si o n 1 3 2 -7 ProASIC3L DC and Switching Characteristics Table 2-9 * Quiescent Supply Current (IDD) Characteristics, ProASIC3L Sleep Mode* ICCI Current Core Voltage A3P250L A3P600L A3P1000L A3PE3000L Units VCCI/VJTAG = 1.2 V (per bank) Typical (25C) 1.2 V 1.7 1.7 1.7 1.7 A VCCI/VJTAG = 1.5 V (per bank) Typical (25C) 1.2 V/1.5 V 1.8 1.8 1.8 1.8 A VCCI/VJTAG = 1.8 V (per bank) Typical (25C) 1.2 V/1.5 V 1.9 1.9 1.9 1.9 A VCCI/VJTAG = 2.5 V (per bank) Typical (25C) 1.2 V/1.5 V 2.2 2.2 2.2 2.2 A VCCI/VJTAG = 3.3 V (per bank) Typical (25C) 1.2 V/1.5 V 2.5 2.5 2.5 2.5 A Note: *IDD = NBANKS * ICCI Table 2-10 * Quiescent Supply Current (IDD) Characteristics, Shutdown Mode Typical (25C) Core Voltage A3PE3000L Units 1.2 V/1.5 V 0 A Table 2-11 * Quiescent Supply Current (IDD) Characteristics, No Flash*Freeze Mode1 Core Voltage A3P250L ICCA Current A3P600L A3P1000L A3PE3000L Units 2 Typical (25C) 1.2 V 0.33 0.55 0.88 2.75 mA 1.5 V 0.5 0.83 1.33 4.2 mA VCCI/VJTAG = 1.2 V (per bank) Typical (25C) 1.2 V 1.7 1.7 1.7 1.7 A VCCI/VJTAG = 1.5 V (per bank) Typical (25C) 1.2 V/1.5 V 1.8 1.8 1.8 1.8 A VCCI/VJTAG = 1.8 V (per bank) Typical (25C) 1.2 V/1.5 V 1.9 1.9 1.9 1.9 A VCCI/VJTAG = 2.5 V (per bank) Typical (25C) 1.2 V/1.5 V 2.2 2.2 2.2 2.2 A VCCI/VJTAG = 3.3 V (per bank) Typical (25C) 1.2 V/1.5 V 2.5 2.5 2.5 2.5 A ICCI or IJTAG Current Notes: 1. *IDD = NBANKS * ICCI+ICCA. JTAG counts as one bank when powered. 2. Includes VCC and VPUMP and VCCPLL currents. 2- 8 R ev isio n 1 3 ProASIC3L Low Power Flash FPGAs Power per I/O Pin Table 2-12 * Summary of I/O Input Buffer Power (per pin) - Default I/O Software Settings Applicable to Pro I/O Banks VCCI (V) Static Power PDC6 (mW)1 Dynamic Power PAC9 (W/MHz)2 3.3 V LVTTL/LVCMOS 3.3 - 16.34 3.3 V LVTTL/LVCMOS - Schmitt trigger 3.3 - 24.49 2.5 V LVCMOS 2.5 - 4.71 2.5 V LVCMOS - Schmitt trigger 2.5 - 6.13 1.8 V LVCMOS 1.8 - 1.66 1.8 V LVCMOS - Schmitt trigger 1.8 - 1.78 1.5 V LVCMOS (JESD8-11) 1.5 - 1.01 1.5 V LVCMOS (JESD8-11) - Schmitt trigger 1.5 - 0.97 1.2 V LVCMOS 1.2 - 0.60 1.2 V LVCMOS - Schmitt trigger 1.2 - 0.53 3.3 V PCI 3.3 - 17.76 3.3 V PCI - Schmitt trigger 3.3 - 19.10 3.3 V PCI-X 3.3 - 17.76 3.3 V PCI-X - Schmitt trigger 3.3 - 19.10 3.3 V GTL 3.3 2.90 7.07 2.5 V GTL 2.5 2.13 3.62 3.3 V GTL+ 3.3 2.81 2.97 2.5 V GTL+ 2.5 2.57 2.55 HSTL (I) 1.5 0.17 0.85 HSTL (II) 1.5 0.17 0.85 SSTL2 (I) 2.5 1.38 3.30 SSTL2 (II) 2.5 1.38 3.30 SSTL3 (I) 3.3 3.21 8.08 SSTL3 (II) 3.3 3.21 8.08 LVDS 2.5 2.26 0.95 LVPECL 3.3 5.71 1.62 Single-Ended Voltage-Referenced Differential Notes: 1. PDC6 is the static power (where applicable) measured on VCCI. 2. PAC9 is the total dynamic power measured on VCCI. R ev i si o n 1 3 2 -9 ProASIC3L DC and Switching Characteristics Table 2-13 * Summary of I/O Input Buffer Power (per pin) - Default I/O Software Settings1 Applicable to Advanced I/O Banks VCCI (V) Static Power PDC6 (mW)2 Dynamic Power PAC10 (W/MHz)3 3.3 V LVTTL / 3.3 V LVCMOS 3.3 - 16.22 2.5 V LVCMOS 2.5 - 4.65 1.8 V LVCMOS 1.8 - 1.65 1.5 V LVCMOS (JESD8-11) 1.5 - 0.98 1.2 V LVCMOS 1.2 - 0.61 Single-Ended 3.3 V PCI 3.3 - 17.64 3.3 V PCI-X 3.3 - 17.64 LVDS 2.5 2.26 0.95 LVPECL 3.3 5.72 1.63 Differential Notes: 1. Dynamic power consumption is given for standard load and software default drive strength and output slew. 2. PDC6 is the static power (where applicable) measured on VCCI. 3. PAC10 is the total dynamic power measured on VCCI. Table 2-14 * Summary of I/O Input Buffer Power (per pin) - Default I/O Software Settings Applicable to Standard Plus I/O Banks VCCI (V) Static Power PDC6 (mW)1 Dynamic Power PAC9 (W/MHz)2 3.3 V LVTTL / 3.3 V LVCMOS 3.3 - 16.23 2.5 V LVCMOS 2.5 - 4.66 1.8 V LVCMOS 1.8 - 1.64 1.5 V LVCMOS (JESD8-11) 1.5 - 0.99 1.2 V LVCMOS 1.2 - 0.58 3.3 V PCI 3.3 - 17.64 3.3 V PCI-X 3.3 - 17.64 Single-Ended Notes: 1. PDC6 is the static power (where applicable) measured on VCCI. 2. PAC9 is the total dynamic power measured on VCCI. 2- 10 R ev i sio n 1 3 ProASIC3L Low Power Flash FPGAs Table 2-15 * Summary of I/O Output Buffer Power (per pin) - Default I/O Software Settings 1 Applicable to Pro I/Os CLOAD (pF) VCCI (V) Static Power PDC7 (mW)2 Dynamic Power PAC10 (W/MHz)3 3.3 V LVTTL/LVCMOS 5 3.3 - 148.00 2.5 V LVCMOS 5 2.5 - 83.23 1.8 V LVCMOS 5 1.8 - 54.58 1.5 V LVCMOS (JESD8-11) 5 1.5 - 37.05 1.2 V LVCMOS 5 1.2 - 17.94 Single-Ended 3.3 V PCI 10 3.3 - 204.61 3.3 V PCI-X 10 3.3 - 204.61 3.3 V GTL 10 3.3 - 24.08 2.5 V GTL 10 2.5 - 13.52 3.3 V GTL+ 10 3.3 - 24.10 2.5 V GTL+ 10 2.5 - 13.54 HSTL (I) 20 1.5 7.08 26.22 Voltage-Referenced HSTL (II) 20 1.5 13.88 27.22 SSTL2 (I) 30 2.5 16.69 105.56 SSTL2 (II) 30 2.5 25.91 116.60 SSTL3 (I) 30 3.3 26.02 114.87 SSTL3 (II) 30 3.3 42.21 131.76 LVDS - 2.5 7.70 89.62 LVPECL - 3.3 19.42 168.02 Differential Notes: 1. Dynamic power consumption is given for standard load and software default drive strength and output slew. 2. PDC7 is the static power (where applicable) measured on VCCI. 3. PAC10 is the total dynamic power measured on VCCI. R ev i si o n 1 3 2- 11 ProASIC3L DC and Switching Characteristics Table 2-16 * Summary of I/O Output Buffer Power (per pin) - Default I/O Software Settings 1 Applicable to Advanced I/O Banks CLOAD (pF) VCCI (V) Static Power PDC7 (mW)2 Dynamic Power PAC10 (W/MHz)3 3.3 V LVTTL / 3.3 V LVCMOS 5 3.3 - 141.97 2.5 V LVCMOS 5 2.5 - 79.98 1.8 V LVCMOS 5 1.8 - 52.26 1.5 V LVCMOS (JESD8-11) 5 1.5 - 35.62 1.2 V LVCMOS 5 1.2 - 21.29 Single-Ended 3.3 V PCI 10 3.3 - 201.02 3.3 V PCI-X 10 3.3 - 201.02 LVDS - 2.5 7.74 89.71 LVPECL - 3.3 19.54 167.54 Differential Notes: 1. Dynamic power consumption is given for standard load and software default drive strength and output slew. 2. PDC7 is the static power (where applicable) measured on VCCI. 3. PAC10 is the total dynamic power measured on VCCI. Table 2-17 * Summary of I/O Output Buffer Power (per pin) - Default I/O Software Settings 1 Applicable to Standard Plus I/O Banks CLOAD (pF) VCCI (V) Static Power PDC7 (mW)2 Dynamic Power PAC10 (W/MHz)3 Single-Ended 3.3 V LVTTL / 3.3 V LVCMOS 5 3.3 - 125.97 2.5 V LVCMOS 5 2.5 - 70.82 1.8 V LVCMOS 5 1.8 - 36.39 1.5 V LVCMOS (JESD8-11) 5 1.5 - 25.34 1.2 V LVCMOS 5 1.2 - 16.24 3.3 V PCI 10 3.3 - 184.92 3.3 V PCI-X 10 3.3 - 184.92 Notes: 1. Dynamic power consumption is given for standard load and software default drive strength and output slew. 2. PDC7 is the static power (where applicable) measured on VCCI. 3. PAC10 is the total dynamic power measured on VCCI. 2- 12 R ev i sio n 1 3 ProASIC3L Low Power Flash FPGAs Power Consumption of Various Internal Resources Table 2-18 * Different Components Contributing to Dynamic Power Consumption in ProASIC3L Devices at 1.2 V VCC Device Specific Dynamic Power (W/MHz) Parameter Definition A3PE3000L A3P1000L A3P600L A3P250L PAC1 Clock contribution of a Global Rib 12.61 9.28 8.19 7.07 PAC2 Clock contribution of a Global Spine 2.66 1.59 1.19 1.01 PAC3 Clock contribution of a VersaTile row 0.56 PAC4 Clock contribution of a VersaTile used as a sequential module 0.07 PAC5 First contribution of a VersaTile used as a sequential module 0.05 PAC6 Second contribution of a VersaTile used as a sequential module 0.19 PAC7 Contribution of a VersaTile used as a combinatorial Module 0.11 PAC8 Average contribution of a routing net 0.45 PAC9 Contribution of an I/O input pin (standard-dependent) See Table 2-12 on page 2-9. through Table 2-14 on page 2-10. PAC10 Contribution of an I/O output pin (standard-dependent) See Table 2-15 on page 2-11 through Table 2-17 on page 2-12. PAC11 Average contribution of a RAM block during a read operation 25.00 PAC12 Average contribution of a RAM block during a write operation 30.00 PAC13 Dynamic contribution for PLL 1.74 0.52 Note: *For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi power spreadsheet calculator or SmartPower tool in Libero SoC. R ev i si o n 1 3 2- 13 ProASIC3L DC and Switching Characteristics Table 2-19 * Different Components Contributing to Dynamic Power Consumption in ProASIC3L Devices at 1.5 V VCC Device Specific Dynamic Power (W/MHz) Parameter Definition A3PE3000L A3P1000L A3P600L A3P250L PAC1 Clock contribution of a Global Rib 19.7 14.50 12.80 11.00 PAC2 Clock contribution of a Global Spine 4.16 2.48 1.85 1.58 PAC3 Clock contribution of a VersaTile row 0.88 PAC4 Clock contribution of a VersaTile used as a sequential module 0.12 PAC5 First contribution of a VersaTile used as a sequential module 0.07 PAC6 Second contribution of a VersaTile used as a sequential module 0.29 PAC7 Contribution of a VersaTile used as a combinatorial Module 0.29 PAC8 Average contribution of a routing net 0.70 PAC9 Contribution of an I/O input pin (standard-dependent) See Table 2-12 on page 2-9. through Table 2-14 on page 2-10. PAC10 Contribution of an I/O output pin (standard-dependent) See Table 2-15 on page 2-11 through Table 2-17 on page 2-12. PAC11 Average contribution of a RAM block during a read operation 25.00 PAC12 Average contribution of a RAM block during a write operation 30.00 PAC13 Dynamic contribution for PLL 2.60 0.81 Note: *For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi power spreadsheet calculator or SmartPower tool in Libero SoC. Table 2-20 * Different Components Contributing to the Static Power Consumption in ProASIC3L Devices Device Specific Dynamic Power (W) Parameter Definition A3PE3000L A3P1000L A3P600L A3P250L PDC1 Array static power in Active mode See Table 2-11 on page 2-8. PDC2 Array static power in Static (Idle) mode See Table 2-9 on page 2-8. PDC3 Array static power in Flash*Freeze mode See Table 2-8 on page 2-7. PDC4 Static PLL contribution at 1.2 V core (operating mode only) 1.42 mW Static PLL contribution at 1.5 V core (operating mode only) 2.55 mW PDC5 Bank quiescent power (VCCI-dependent) See Table 2-8 on page 2-7, Table 2-9 on page 2-8, Table 2-11 on page 2-8. PDC6 I/O input pin static power (standard-dependent) See Table 2-12 on page 2-9 through Table 2-14 on page 2-10. PDC7 I/O output pin static power (standard-dependent) See Table 2-15 on page 2-11 through Table 2-17 on page 2-12. Note: *For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi power spreadsheet calculator or SmartPower tool in Libero SoC. 2- 14 R ev i sio n 1 3 ProASIC3L Low Power Flash FPGAs Power Calculation Methodology This section describes a simplified method to estimate power consumption of an application. For more accurate and detailed power estimations, use the SmartPower tool in Libero SoC software. The power calculation methodology described below uses the following variables: * The number of PLLs as well as the number and the frequency of each output clock generated * The number of combinatorial and sequential cells used in the design * The internal clock frequencies * The number and the standard of I/O pins used in the design * The number of RAM blocks used in the design * Toggle rates of I/O pins as well as VersaTiles--guidelines are provided in Table 2-21 on page 2-17. * Enable rates of output buffers--guidelines are provided for typical applications in Table 2-22 on page 2-17. * Read rate and write rate to the memory--guidelines are provided for typical applications in Table 2-22 on page 2-17. The calculation should be repeated for each clock domain defined in the design. Methodology Total Power Consumption--PTOTAL PTOTAL = PSTAT + PDYN PSTAT is the total static power consumption. PDYN is the total dynamic power consumption. Total Static Power Consumption--PSTAT PSTAT = (PDC1 or PDC2 or PDC3) + NBANKS* PDC5 + NINPUTS* PDC6 + NOUTPUTS* PDC7 NINPUTS is the number of I/O input buffers used in the design. NOUTPUTS is the number of I/O output buffers used in the design. NBANKS is the number of I/O banks powered in the design. Total Dynamic Power Consumption--PDYN PDYN = PCLOCK + PS-CELL + PC-CELL + PNET + PINPUTS + POUTPUTS + PMEMORY + PPLL Global Clock Contribution--PCLOCK PCLOCK = (PAC1 + NSPINE * PAC2 + NROW * PAC3 + NS-CELL * PAC4) * FCLK NSPINE is the number of global spines used in the user design--guidelines are provided in the "Spine Architecture" section of the ProASIC3L FPGA Fabric User's Guide. NROW is the number of VersaTile rows used in the design--guidelines are provided in the "Spine Architecture" section of the ProASIC3L FPGA Fabric User's Guide. FCLK is the global clock signal frequency. NS-CELL is the number of VersaTiles used as sequential modules in the design. PAC1, PAC2, PAC3, and PAC4 are device-dependent. Sequential Cells Contribution--PS-CELL PS-CELL = NS-CELL * (PAC5 + 1 / 2 * PAC6) * FCLK NS-CELL is the number of VersaTiles used as sequential modules in the design. When a multi-tile sequential cell is used, it should be accounted for as 1. 1 is the toggle rate of VersaTile outputs--guidelines are provided in Table 2-21 on page 2-17. FCLK is the global clock signal frequency. R ev i si o n 1 3 2- 15 ProASIC3L DC and Switching Characteristics Combinatorial Cells Contribution--PC-CELL PC-CELL = NC-CELL* 1 / 2 * PAC7 * FCLK NC-CELL is the number of VersaTiles used as combinatorial modules in the design. 1 is the toggle rate of VersaTile outputs--guidelines are provided in Table 2-21 on page 2-17. FCLK is the global clock signal frequency. Routing Net Contribution--PNET PNET = (NS-CELL + NC-CELL) * 1 / 2 * PAC8 * FCLK NS-CELL is the number of VersaTiles used as sequential modules in the design. NC-CELL is the number of VersaTiles used as combinatorial modules in the design. 1 is the toggle rate of VersaTile outputs--guidelines are provided in Table 2-21 on page 2-17. FCLK is the global clock signal frequency. I/O Input Buffer Contribution--PINPUTS PINPUTS = NINPUTS * 2 / 2 * PAC9 * FCLK NINPUTS is the number of I/O input buffers used in the design. 2 is the I/O buffer toggle rate--guidelines are provided in Table 2-21 on page 2-17. FCLK is the global clock signal frequency. I/O Output Buffer Contribution--POUTPUTS POUTPUTS = NOUTPUTS * 2 / 2 * 1 * PAC10 * FCLK NOUTPUTS is the number of I/O output buffers used in the design. 2 is the I/O buffer toggle rate--guidelines are provided in Table 2-21 on page 2-17. 1 is the I/O buffer enable rate--guidelines are provided in Table 2-22 on page 2-17. FCLK is the global clock signal frequency. RAM Contribution--PMEMORY PMEMORY = PAC11 * NBLOCKS * FREAD-CLOCK * 2 + PAC12 * NBLOCK * FWRITE-CLOCK * 3 NBLOCKS is the number of RAM blocks used in the design. FREAD-CLOCK is the memory read clock frequency. 2 is the RAM enable rate for read operations. FWRITE-CLOCK is the memory write clock frequency. 3 is the RAM enable rate for write operations--guidelines are provided in Table 2-22 on page 2-17. PLL Contribution--PPLL PPLL = PDC4 + PAC13 * FCLKOUT FCLKOUT is the output clock frequency.1 1. 2- 16 If a PLL is used to generate more than one output clock, include each output clock in the formula by adding its corresponding contribution (PAC13* FCLKOUT product) to the total PLL contribution. R ev i sio n 1 3 ProASIC3L Low Power Flash FPGAs Guidelines Toggle Rate Definition A toggle rate defines the frequency of a net or logic element relative to a clock. It is a percentage. If the toggle rate of a net is 100%, this means that this net switches at half the clock frequency. Below are some examples: * The average toggle rate of a shift register is 100% because all flip-flop outputs toggle at half of the clock frequency. * The average toggle rate of an 8-bit counter is 25%: - Bit 0 (LSB) = 100% - Bit 1 = 50% - Bit 2 = 25% - ... - Bit 7 (MSB) = 0.78125% - Average toggle rate = (100% + 50% + 25% + 12.5% + . . . + 0.78125%) / 8 Enable Rate Definition Output enable rate is the average percentage of time during which tristate outputs are enabled. When nontristate output buffers are used, the enable rate should be 100%. Table 2-21 * Toggle Rate Guidelines Recommended for Power Calculation Component 1 2 Definition Guideline Toggle rate of VersaTile outputs 10% I/O buffer toggle rate 10% Table 2-22 * Enable Rate Guidelines Recommended for Power Calculation Component 1 2 3 Definition Guideline I/O output buffer enable rate 100% RAM enable rate for read operations 12.5% RAM enable rate for write operations 12.5% R ev i si o n 1 3 2- 17 ProASIC3L DC and Switching Characteristics User I/O Characteristics Timing Model I/O Module (Non-Registered) Combinational Cell Combinational Cell Y LVPECL (Applicable to Advanced I/O Banks Only)L Y tPD = 0.56 ns tPD = 0.49 ns tDP = 1.34 ns I/O Module (Non-Registered) Combinational Cell Y LVTTL Output drive strength = 12 mA High slew rate tDP = 2.64 ns (Advanced I/O Banks) tPD = 0.87 ns I/O Module (Non-Registered) Combinational Cell I/O Module (Registered) Y LVTTL Output drive strength = 8 mA High slew rate tDP = 3.66 ns (Advanced I/O Banks) tPY = 1.05 ns LVPECL (Applicable to Advanced I/O Banks only) D tPD = 0.47 ns Q I/O Module (Non-Registered) Combinational Cell Y tICLKQ = 0.24 ns tISUD = 0.26 ns LVCMOS 1.5 V Output drive strength = 4 mA High slew rate tDP = 3.97 ns (Advanced I/O Banks) tPD = 0.47 ns Input LVTTL Clock Register Cell tPY = 0.76 ns (Advanced I/O Banks) D Y Q I/O Module (Non-Registered) LVDS, BLVDS, M-LVDS (Applicable for Advanced I/O Banks only) Figure 2-3 * 2- 18 D Q D tPD = 0.47 ns Q LVTTL 3.3 V Output drive strength = 12 mA High slew rate tDP = 2.64 ns (Advanced I/O Banks) tCLKQ = 0.55 ns tSUD = 0.43 ns tPY = 1.20 ns I/O Module (Registered) Combinational Cell Register Cell tCLKQ = 0.55 ns tSUD = 0.43 ns tOCLKQ = 0.59 ns tOSUD = 0.31 ns Input LVTTL Clock Input LVTTL Clock tPY = 0.76 ns (Advanced I/O Banks) tPY = 0.76 ns (Advanced I/O Banks) Timing Model Operating Conditions: -1 Speed, Commercial Temperature Range (TJ = 70C), Worst-Case VCC = 1.14 V R ev i sio n 1 3 ProASIC3L Low Power Flash FPGAs tPY tDIN D PAD Q DIN Y CLK tPY = MAX(tPY(R), tPY(F)) tDIN = MAX(tDIN(R), tDIN(F)) To Array I/O Interface VIH PAD Vtrip Vtrip VIL VCC 50% 50% Y GND tPY (F) tPY (R) VCC 50% DIN GND Figure 2-4 * 50% tDIN tDIN (R) (F) Input Buffer Timing Model and Delays (example) R ev i si o n 1 3 2- 19 ProASIC3L DC and Switching Characteristics tDOUT tDP D Q D PAD DOUT Std Load CLK From Array tDP = MAX(tDP(R), tDP(F)) tDOUT = MAX(tDOUT(R), tDOUT(F)) I/O Interface tDOUT (R) D 50% tDOUT VCC (F) 50% 0V VCC DOUT 50% 50% 0V VOH Vtrip Vtrip VOL PAD tDP (R) Figure 2-5 * 2- 20 Output Buffer Model and Delays (example) R ev i sio n 1 3 tDP (F) ProASIC3L Low Power Flash FPGAs tEOUT D Q CLK E tZL, tZH, tHZ, tLZ, tZLS, tZHS EOUT D Q PAD DOUT CLK D tEOUT = MAX(tEOUT(r), tEOUT(f)) I/O Interface VCC D VCC 50% tEOUT (F) 50% E tEOUT (R) VCC 50% EOUT tZL PAD 50% 50% tHZ Vtrip tZH 50% tLZ VCCI 90% VCCI Vtrip VOL 10% VCCI VCC D VCC E 50% tEOUT (R) 50% tEOUT (F) VCC EOUT PAD 50% tZLS VOH Vtrip Figure 2-6 * 50% 50% tZHS Vtrip VOL Tristate Output Buffer Timing Model and Delays (example) R ev i si o n 1 3 2- 21 ProASIC3L DC and Switching Characteristics Overview of I/O Performance Summary of I/O DC Input and Output Levels - Default I/O Software Settings Table 2-23 * Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial Conditions--Software Default Settings Applicable to Pro I/O Banks Equiv. Software Default Drive Drive Strength Strength Slew Min. I/O Standard (mA) Option1 Rate V VIL VIH VOL VOH IOL3 IOH3 mA mA Max. V Min. V Max.2 V Max. V Min. V 2.4 3.3 V LVTTL / 12 mA 3.3 V LVCMOS 12 mA High -0.3 0.8 2 3.6 0.4 3.3 V 100 A LVCMOS Wide Range4 12 mA High -0.3 0.8 2 3.6 0.2 2.5 V LVCMOS 12 mA 12 mA High -0.3 0.7 1.7 2.7 0.7 1.8 V LVCMOS 12 mA 12 mA High -0.3 0.35 * VCCI 0.65 * VCCI 1.9 0.45 1.5 V LVCMOS 12 mA 1.2 V LVCMOS 2 mA 1.2 V 100 A LVCMOS Wide Range5 12 12 VCCI - 0.2 0.1 0.1 12 12 VCCI - 0.45 12 12 12 mA High -0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 12 12 2 mA High -0.3 0.35 * VCCI 0.65 * VCCI 1.26 0.25 * VCCI 0.75 * VCCI 2 2 mA High -0.3 3.3 V PCI 0.3 * VCCI 0.7 * VCCI 1.575 0.1 1.7 2 VCCI - 0.1 0.1 0.1 Per PCI Specification 3.3 V PCI-X Per PCI-X Specification 3.3 V GTL 20 mA6 mA6 20 mA6 High -0.3 VREF - 0.05 VREF + 0.05 mA6 3.6 0.4 - 20 20 2.5 V GTL 20 High -0.3 VREF - 0.05 VREF + 0.05 2.7 0.4 - 20 20 3.3 V GTL+ 35 mA 35 mA High -0.3 VREF - 0.1 VREF + 0.1 3.6 0.6 - 35 35 2.5 V GTL+ 33 mA 33 mA High -0.3 VREF - 0.1 VREF + 0.1 2.7 0.6 - 33 33 HSTL (I) 8 mA 8 mA High -0.3 VREF - 0.1 VREF + 0.1 1.575 0.4 VCCI - 0.4 8 8 mA6 mA6 20 HSTL (II) 15 High -0.3 VREF - 0.1 VREF + 0.1 1.575 0.4 VCCI - 0.4 15 15 SSTL2 (I) 15 mA 15 mA High -0.3 VREF - 0.1 VREF + 0.1 2.7 0.54 VCCI - 0.62 15 15 SSTL2 (II) 18 mA 18 mA High -0.3 VREF - 0.1 VREF + 0.1 2.7 0.35 VCCI - 0.43 18 18 SSTL3 (I) 14 mA 14 mA High -0.3 VREF - 0.1 VREF + 0.1 3.6 0.7 VCCI - 1.1 14 14 SSTL3 (II) 21 mA 21 mA High -0.3 VREF - 0.1 VREF + 0.1 3.6 0.5 VCCI - 0.9 21 21 15 Notes: 1. Please note that 1.2V LVCMOS and 3.3V LVCMOS wide range is applicable to 100uA drive strength only. The configuration will NOT operate at the equivalent software. 2. Maximum VIH is 3.6 V for all I/O standards with hot-insertion is enabled. 3. Currents are measured at 85C junction temperature. 4. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification. 5. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12 specification. 6. Output drive strength is below JEDEC specification. 7. Output slew rate can be extracted using the IBIS models. 2- 22 R ev i sio n 1 3 ProASIC3L Low Power Flash FPGAs Table 2-24 * Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial Conditions--Software Default Settings Applicable to Advanced I/O Banks I/O Standard 3.3 V LVTTL / 3.3 V LVCMOS Equiv. Software Default Drive Drive Strength Slew Min. Strength Option1 Rate V VIL VIH VOL VOH IOL2 IOH2 mA mA Max. V Min. V Max. V Max. V Min. V 12 mA 12 mA High -0.3 0.8 2 3.6 0.4 2.4 100 A 3.3 V LVCMOS Wide Range3 12 mA High -0.3 0.8 2 3.6 0.2 VCCI - 0.2 2.5 V LVCMOS 12 mA 12 mA High -0.3 0.7 1.7 2.7 0.7 1.7 1.8 V LVCMOS 12 mA 12 mA High -0.3 0.35 * VCCI 0.65 * VCCI 1.9 0.45 1.5 V LVCMOS 12 mA 1.2 V LVCMOS 2 mA 100 A 1.2 V LVCMOS Wide Range4,5 3.3 V PCI 3.3 V PCI-X 12 12 0.1 0.1 12 12 VCCI - 0.45 12 12 12 mA High -0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 12 12 2 mA High -0.3 0.35 * VCCI 0.65 * VCCI 1.26 0.25 * VCCI 0.75 * VCCI 2 2 2 mA High -0.3 0.1 0.1 0.3 * VCCI 0.7 * VCCI 1.575 0.1 VCCI - 0.1 Per PCI specifications Per PCI-X specifications Notes: 1. Please note that 1.2 V LVCMOS and 3.3 V LVCMOS wide range is applicable to 100 A drive strength only. The configuration will NOT operate at the equivalent software. 2. Currents are measured at 85C junction temperature. 3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification. 4. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12 specification. 5. Applicable to devices operating at VCCI VCC. 6. Output slew rate can be extracted using the IBIS models. R ev i si o n 1 3 2- 23 ProASIC3L DC and Switching Characteristics Table 2-25 * Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial Conditions--Software Default Settings Applicable to Standard Plus I/O Banks I/O Standard Equiv. VIL Software Default Drive Drive Strength Slew Min. Max. Strength Option1 Rate V V VIH VOL VOH IOL2 IOH2 Min. V Max. V Max. V Min. V mA mA 3.3 V LVTTL / 12 mA 3.3 V LVCMOS 12 mA High -0.3 0.8 2 3.6 0.4 2.4 12 12 3.3 V LVCMOS 100 A Wide Range3 12 mA High -0.3 0.8 2 3.6 0.2 VCCI - 0.2 0.1 0.1 2.5 V LVCMOS 12 mA 12 mA High -0.3 0.7 1.7 2.7 0.7 1.7 12 12 1.8 V LVCMOS 8 mA 8 mA High -0.3 0.35 * VCCI 0.65 * VCCI 1.9 0.45 VCCI - 0.45 8 8 1.5 V LVCMOS 4 mA 4 mA High -0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 4 4 1.2 V LVCMOS4 2 mA 2 mA High -0.3 0.35 * VCCI 0.65 * VCCI 1.26 0.25 * VCCI 0.75 * VCCI 2 2 2 mA High -0.3 0.3 * VCCI 0.7 * VCCI 1.575 0.1 0.1 1.2 V 100 A LVCMOS Wide Range4,5 3.3 V PCI 3.3 V PCI-X 0.1 VCCI - 0.1 Per PCI specifications Per PCI-X specifications Notes: 1. Please note that 1.2 V LVCMOS and 3.3 V LVCMOS wide range is applicable to 100 A drive strength only. The configuration will NOT operate at the equivalent software. 2. Currents are measured at 85C junction temperature. 3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification. 4. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12 specification. 5. Applicable to devices operating at VCCI VCC. 6. Output slew rate can be extracted using the IBIS models. 2- 24 R ev i sio n 1 3 ProASIC3L Low Power Flash FPGAs Table 2-26 * Summary of Maximum and Minimum DC Input Levels Applicable to Commercial and Industrial Conditions Commercial1 Industrial2 3 IIH4 IIL IIH IIL DC I/O Standard A A A A 3.3 V LVTTL / 3.3 V LVCMOS 10 10 15 15 3.3 V LVCMOS Wide Range 10 10 15 15 2.5 V LVCMOS 10 10 15 15 1.8 V LVCMOS 10 10 15 15 10 10 15 15 1.5 V LVCMOS 5 1.2 V LVCMOS 10 10 15 15 1.2 V LVCMOS Wide Range5 10 10 15 15 3.3 V PCI 10 10 15 15 3.3 V PCI-X 10 10 15 15 3.3 V GTL 10 10 15 15 2.5 V GTL 10 10 15 15 3.3 V GTL+ 10 10 15 15 2.5 V GTL+ 10 10 15 15 HSTL (I) 10 10 15 15 HSTL (II) 10 10 15 15 SSTL2 (I) 10 10 15 15 SSTL2 (II) 10 10 15 15 SSTL3 (I) 10 10 15 15 SSTL3 (II) 10 10 15 15 Notes: 1. Commercial range (0C < TA < 70C) 2. Industrial range (-40C < TA < 85C) 3. IIL is the input leakage current per I/O pin over recommended operation conditions where -0.3V < VIN <VIL. 4. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 5. Applicable to devices operating at VCCI VCC. R ev i si o n 1 3 2- 25 ProASIC3L DC and Switching Characteristics Summary of I/O Timing Characteristics - Default I/O Software Settings Table 2-27 * Summary of AC Measuring Points Standard Input Reference Voltage (VREF_TYP) Board Termination Voltage (VTT_REF) Measuring Trip Point (Vtrip) - - 1.4 V 3.3 V LVTTL / 3.3 V LVCMOS 3.3 V LVCMOS Wide Range - - 1.4 V 2.5 V LVCMOS - - 1.2 V 1.8 V LVCMOS - - 0.90 V 1.5 V LVCMOS - - 0.75 V 1.2 V LVCMOS * - - 0.6 V 1.2 V LVCMOS Wide Range* - - 0.6 V 3.3 V PCI - - 0.285 * VCCI (RR) 0.615 * VCCI (FF)) 3.3 V PCI-X - - 0.285 * VCCI (RR) 0.615 * VCCI (FF) 3.3 V GTL 0.8 V 1.2 V VREF 2.5 V GTL 0.8 V 1.2 V VREF 3.3 V GTL+ 1.0 V 1.5 V VREF 2.5 V GTL+ 1.0 V 1.5 V VREF HSTL (I) 0.75 V 0.75 V VREF HSTL (II) 0.75 V 0.75 V VREF SSTL2 (I) 1.25 V 1.25 V VREF SSTL2 (II) 1.25 V 1.25 V VREF SSTL3 (I) 1.5 V 1.485 V VREF SSTL3 (II) 1.5 V 1.485 V VREF LVDS - - Cross point LVPECL - - Cross point Note: *Applicable only to devices operating in the 1.2 V core range. Table 2-28 * I/O AC Parameter Definitions Parameter Parameter Definition tDP Data to Pad delay through the Output Buffer tPY Pad to Data delay through the Input Buffer tDOUT Data to Output Buffer delay through the I/O interface tEOUT Enable to Output Buffer Tristate Control delay through the I/O interface tDIN Input Buffer to Data delay through the I/O interface tHZ Enable to Pad delay through the Output Buffer--High to Z tZH Enable to Pad delay through the Output Buffer--Z to High tLZ Enable to Pad delay through the Output Buffer--Low to Z tZL Enable to Pad delay through the Output Buffer--Z to Low tZHS Enable to Pad delay through the Output Buffer with delayed enable--Z to High tZLS Enable to Pad delay through the Output Buffer with delayed enable--Z to Low 2- 26 R ev i sio n 1 3 ProASIC3L Low Power Flash FPGAs 1.5 V DC Core Voltage - - - - - - - - - - - - Units tZHS (ns) tZLS (ns) tHZ (ns) tLZ (ns) tZH (ns) tZL (ns) tEO UT (ns) tPYS (ns) - tPY (ns) 5 tDIN (ns) 3.3 V LVCMOS 100 A 12 mA High Wide Range1,2 tDP (ns) - 0.50 1.89 0.03 1.34 1.85 0.33 1.93 1.42 2.51 2.77 3.64 3.13 ns tDOUT (ns) External Resistor () 5 Slew Rate 3.3 V LVTTL / 12 mA 12 mA High 3.3 V LVCMOS Standard Drive Strength (mA) Capacitive Load (pF) Equiv. Software Default Drive Strength Option1 Table 2-29 * Summary of I/O Timing Characteristics--Software Default Settings -1 Speed Grade, Commercial-Case Conditions: TJ = 70C, Worst Case VCC = 1.425V, Worst Case VCCI Pro I/O Banks ns 2.5 V LVCMOS 12 mA 12 mA High 5 - 0.50 1.92 0.03 1.58 1.97 0.33 1.96 1.59 2.58 2.68 3.67 3.30 ns 1.8 V LVCMOS 12 mA 12 mA High 5 - 0.50 2.14 0.03 1.53 2.17 0.33 2.18 1.76 2.86 3.24 3.89 3.47 ns 1.5 V LVCMOS 12 mA 12 mA High 5 - 0.50 2.46 0.03 1.69 2.36 0.33 2.51 2.04 3.03 3.35 4.22 3.75 ns 3.3 V PCI Per PCI spec. - High 5 253 0.50 2.15 0.03 2.10 2.84 0.33 2.19 1.53 2.51 2.77 3.90 3.24 ns 3.3 V PCI-X Per PCI-X spec. - High 10 253 0.50 2.15 0.03 2.10 2.84 0.33 2.19 1.53 2.51 2.77 3.90 3.24 ns 3.3 V GTL 20 mA5 20 mA5 High 10 25 0.50 1.59 0.03 1.80 - 0.33 1.56 1.59 - - 3.27 3.30 ns High 10 25 0.50 1.63 0.03 1.75 - 0.33 1.66 1.63 - - 3.37 3.34 ns 3.3 V GTL+ 35 mA 35 mA High 10 25 0.50 1.57 0.03 1.80 - 0.33 1.60 1.57 - - 3.31 3.29 ns 2.5 V GTL+ 33 mA 33 mA High 10 25 0.50 1.69 0.03 1.75 2.5 V GTL 5 20 mA 20 mA5 - 0.33 1.72 1.61 - - 3.43 3.32 ns High 20 25 0.50 2.43 0.03 2.12 - 0.33 2.48 2.41 - - 4.19 4.12 ns HSTL (II) 15 mA5 15 mA High 20 50 0.50 2.32 0.03 2.12 - 0.33 2.36 2.08 - - 4.07 3.79 ns SSTL2 (I) 15 mA 15 mA High 30 25 0.50 1.63 0.03 1.61 - 0.33 1.66 1.41 - - 1.66 1.41 ns SSTL2 (II) 18 mA 18 mA High 30 50 0.50 1.66 0.03 1.61 - 0.33 1.69 1.36 - - 1.69 1.36 ns SSTL3 (I) 14 mA 14 mA High 30 25 0.50 1.77 0.03 1.54 - 0.33 1.80 1.41 - - 1.80 1.41 ns SSTL3 (II) 21 mA 21 mA High 30 50 0.50 1.58 0.03 1.54 - 0.33 1.61 1.28 - - 1.61 1.28 ns LVDS 24 mA 24 mA High - - 0.50 1.40 0.03 1.85 - - - - - - - - ns LVPECL 24 mA 24 mA High - - 0.50 1.40 0.03 1.67 - - - - - - - - ns HSTL (I) 8 mA 8 mA Notes: 1. The minimum drive strength for any LVCMOS 1.2 V or LVCMOS 3.3 V software configuration when run in wide range is 100 A. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification. 3. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on page 2-81 for connectivity. This resistor is not required during normal operation. 4. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. 5. Output drive strength is below JEDEC specification. R ev i si o n 1 3 2- 27 ProASIC3L DC and Switching Characteristics 5 - 0.46 2.04 0.03 0.93 0.33 2.08 1.73 2.83 3.12 3.79 3.45 ns 1.5 V LVCMOS 12 mA 12 mA High 5 - 0.46 2.33 0.03 1.10 0.33 2.37 2.01 3.02 3.22 4.08 3.72 ns 3.3 V PCI Per PCI spec. - High 5 25 3 0.46 2.05 0.03 0.66 0.33 2.09 1.49 2.46 2.74 3.80 3.21 ns 3.3 V PCI-X Per PCI-X spec. - High 10 253 0.46 2.05 0.03 0.64 0.33 2.09 1.49 2.46 2.74 3.80 3.21 ns LVDS 24 mA - High - - 0.46 1.40 0.03 1.23 N/A N/A N/A N/A N/A N/A N/A ns LVPECL 24 mA - High - - 0.46 1.38 0.03 1.08 N/A N/A N/A N/A N/A N/A N/A ns Units 12 mA 12 mA High tZHS (ns) 1.8 V LVCMOS tZLS (ns) 0.46 1.85 0.03 1.00 0.33 1.88 1.55 2.53 2.63 3.59 3.26 ns tHZ (ns) - tLZ (ns) 5 tZH (ns) 12 mA 12 mA High tZL (ns) 2.5 V LVCMOS tEO UT (ns) - tPY (ns) 5 tDIN (ns) 3.3 V LVCMOS 100 A 12 mA High Wide Range1,2 tDP (ns) - tDOUT (ns) External Resistor () 5 3.3 V LVTTL / 3.3 V LVCMOS Slew Rate 12 mA 12 mA High I/O Standard Drive Strength (mA) Capacitive Load (pF) Equiv. Software Default Drive Strength Option1 Table 2-30 * Summary of I/O Timing Characteristics--Software Default Settings -1 Speed Grade, Commercial-Case Conditions: TJ = 70C, Worst Case VCC = 1.425 V, Worst Case VCCI Advanced I/O Banks 0.46 1.83 0.03 0.78 0.33 1.87 1.39 2.46 2.74 3.58 3.10 ns - - - - - - - - - - - ns Notes: 1. The minimum drive strength for any LVCMOS 1.2 V or LVCMOS 3.3 V software configuration when run in wide range is 100 A. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification. 3. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on page 2-81 for connectivity. This resistor is not required during normal operation. 4. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. 2- 28 R ev i sio n 1 3 ProASIC3L Low Power Flash FPGAs 3.3 V LVTTL / 3.3 V LVCMOS Units tZHS (ns) tZLS (ns) tHZ (ns) tLZ (ns) tZH (ns) tZL (ns) tEOUT (ns) tPY (ns) tDIN (ns) tDP (ns) tDOUT (ns) External Resistor Capacitive Load (pF) Slew Rate Equiv. Software Default Drive Strength Option1 I/O Standard Drive Strength (mA) Table 2-31 * Summary of I/O Timing Characteristics--Software Default Settings -1 Speed Grade, Commercial-Case Conditions: TJ = 70C, Worst Case VCC = 1.425 V, Worst Case VCCI = 3.0 V Standard Plus I/O Banks 12 mA 12 mA High 5 - 3.3 V LVCMOS 100 A 12 mA High Wide Range1,2 5 - 2.5 V LVCMOS 5 - 0.46 1.59 0.03 0.99 0.33 1.61 1.32 2.16 2.38 3.33 3.03 ns 5 - 0.46 1.59 0.03 0.99 0.33 1.61 1.32 2.16 2.38 3.33 3.03 ns - 0.46 2.15 0.03 1.09 0.33 2.19 1.82 2.32 2.40 3.90 3.53 ns 12 mA 12 mA High 0.46 1.56 0.03 0.77 0.33 1.59 1.20 2.14 2.47 3.30 2.91 ns - - - - - - - - - - - ns 1.8 V LVCMOS 8 mA 8 mA High 1.5 V LVCMOS 4 mA 4 mA High 3.3 V PCI Per PCI spec. - High 10 25 3 0.46 1.77 0.03 0.65 0.33 1.80 1.31 2.14 2.47 3.51 3.02 ns 3.3 V PCI-X Per PCI-X spec. - High 10 25 3 0.46 1.77 0.03 0.64 0.33 1.80 1.31 2.14 2.47 3.51 3.02 ns 5 Notes: 1. The minimum drive strength for any LVCMOS 1.2 V or LVCMOS 3.3 V software configuration when run in wide range is 100 A. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification. 3. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on page 2-81 for connectivity. This resistor is not required during normal operation. 4. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. R ev i si o n 1 3 2- 29 ProASIC3L DC and Switching Characteristics 1.2 V DC Core Voltage 3.3 V LVTTL / 12 mA 12 mA High 5 3.3 V LVCMOS - 3.3 V LVCMOS 100 A 12 mA High 5 Wide Range1,2 - Units tZHS (ns) tZLS (ns) tHZ (ns) tLZ (ns) tZH (ns) tZL (ns) tEOUT (ns) tPYS (ns) tPY (ns) tDIN (ns) tDP (ns) tDOUT (ns) External Resistor () Capacitive Load (pF) Slew Rate Equiv. Software Default Drive Strength Option1 Standard Drive Strength (mA) Table 2-32 * Summary of I/O Timing Characteristics--Software Default Settings -1 Speed Grade, Commercial-Case Conditions: TJ = 70C, Worst Case VCC = 1.14 V, Worst Case VCCI Pro I/O Banks 0.66 1.89 0.04 1.34 1.85 0.43 1.93 1.42 2.51 2.77 3.64 3.13 ns - - - - - - - - - - - - ns 2.5 V LVCMOS 12 mA 12 mA High 5 - 0.66 1.92 0.04 1.58 1.97 0.43 1.96 1.59 2.58 2.68 3.67 3.30 ns 1.8 V LVCMOS 12 mA 12 mA High 5 - 0.66 2.14 0.04 1.53 2.17 0.43 2.18 1.76 2.86 3.24 3.89 3.47 ns 1.5 V LVCMOS 12 mA 12 mA High 5 - 0.66 2.46 0.04 1.69 2.36 0.43 2.51 2.04 3.03 3.35 4.22 3.75 ns 2 mA High 5 - 0.66 4.12 0.04 2.02 2.99 0.43 3.83 3.37 4.06 3.84 5.48 5.02 ns 1.2 V LVCMOS 100 A 2 mA High 5 Wide Range1,3 - 1.2 V LVCMOS 2 mA - - - - - - - - - - - - ns 3.3 V PCI Per PCI spec. - High 10 254 0.66 2.15 0.04 2.10 2.84 0.43 2.19 1.53 2.51 2.77 3.90 3.24 ns 3.3 V PCI-X Per PCI-X spec. - High 10 254 0.66 2.15 0.04 2.10 2.84 0.43 2.19 1.53 2.51 2.77 3.90 3.24 ns 3.3 V GTL 20 mA6 - High 10 25 0.66 1.59 0.04 1.80 2.5 V GTL 20 mA6 - High 10 25 0.66 1.63 0.04 1.75 - 0.43 1.66 1.63 - - 3.37 3.34 ns 3.3 V GTL+ 35 mA - High 10 25 0.66 1.57 0.04 1.80 - 0.43 1.60 1.57 - - 3.31 3.29 ns 2.5 V GTL+ - 0.43 1.56 1.59 - - 3.27 3.30 ns 33 mA - High 10 25 0.66 1.69 0.04 1.75 - 0.43 1.72 1.61 - - 3.43 3.32 ns HSTL (I) 8 mA - High 20 25 0.66 2.43 0.04 2.12 - 0.43 2.48 2.41 - - 4.19 4.12 ns HSTL (II) 15 mA6 - High 20 50 0.66 2.32 0.04 2.12 - 0.43 2.36 2.08 - - 4.07 3.79 ns SSTL2 (I) 15 mA - High 30 25 0.66 1.63 0.04 1.61 - 0.43 1.66 1.41 - - 1.66 1.41 ns SSTL2 (II) 18 mA - High 30 50 0.66 1.66 0.04 1.61 - 0.43 1.69 1.36 - - 1.69 1.36 ns SSTL3 (I) 14 mA - High 30 25 0.66 1.77 0.04 1.54 - 0.43 1.80 1.41 - - 1.80 1.41 ns SSTL3 (II) 21 mA - High 30 50 0.66 1.58 0.04 1.54 - 0.43 1.61 1.28 - - 1.61 1.28 ns Notes: 1. The minimum drive strength for any LVCMOS 1.2 V or LVCMOS 3.3 V software configuration when run in wide range is 100 A. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification. 3. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12 specification. 4. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on page 2-81 for connectivity. This resistor is not required during normal operation. 5. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. 6. Output drive strength is below JEDEC specification. 2- 30 R ev i sio n 1 3 ProASIC3L Low Power Flash FPGAs tEOUT (ns) tZL (ns) tZH (ns) tLZ (ns) tHZ (ns) tZLS (ns) tZHS (ns) Units - High - - 0.66 1.43 0.04 1.85 - - - - - - - - ns LVPECL 24 mA - High - - 0.66 1.37 0.04 1.67 - - - - - - - - ns tPY (ns) 24 mA tDIN (ns) LVDS Standard tDP (ns) tPYS (ns) tDOUT (ns) External Resistor () Capacitive Load (pF) Slew Rate Equiv. Software Default Drive Strength Option1 Drive Strength (mA) Table 2-32 * Summary of I/O Timing Characteristics--Software Default Settings -1 Speed Grade, Commercial-Case Conditions: TJ = 70C, Worst Case VCC = 1.14 V, Worst Case VCCI Pro I/O Banks Notes: 1. The minimum drive strength for any LVCMOS 1.2 V or LVCMOS 3.3 V software configuration when run in wide range is 100 A. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification. 3. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12 specification. 4. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on page 2-81 for connectivity. This resistor is not required during normal operation. 5. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. 6. Output drive strength is below JEDEC specification. 3.3 V LVTTL / 3.3 V LVCMOS 12 mA 12 mA High 5 pF - 3.3 V LVCMOS 100 A 12 mA High 5 pF Wide Range1,2 - 2.5 V LVCMOS - 12 mA 12 mA High 5 pF Units tZHS (ns) tZLS (ns) tHZ (ns) tLZ (ns) tZH (ns) tZL (ns) tEO UT (ns) tPY (ns) tDIN (ns) tDP (ns) tDOUT (ns) External Resistor () Capacitive Load (pF) Slew Rate Equiv. Software Default Drive Strength Option1 I/O Standard Drive Strength (mA) Table 2-33 * Summary of I/O Timing Characteristics--Software Default Settings -1 Speed Grade, Commercial-Case Conditions: TJ = 70C, Worst Case VCC = 1.14 V, Worst Case VCCI Advanced I/O Banks 0.60 1.83 0.04 0.78 0.43 1.87 1.39 2.46 2.74 3.58 3.10 ns - - - - - - - - - - - ns 0.60 1.85 0.04 1.00 0.43 1.88 1.55 2.53 2.63 3.59 3.26 ns 1.8 V LVCMOS 12 mA 12 mA High 5 pF - 0.60 2.04 0.04 0.93 0.43 2.08 1.73 2.83 3.12 3.79 3.45 ns 1.5 V LVCMOS 12 mA 12 mA High 5 pF - 0.60 2.33 0.04 1.10 0.43 2.37 2.01 3.02 3.22 4.08 3.72 ns 1.2 V LVCMOS 2 mA High 5pF - 0.60 3.17 0.04 1.55 0.43 2.11 1.76 2.38 2.46 3.76 3.41 ns 1.2 V LVCMOS 100 A 2 mA High 5 pF Wide Range1,3 - 3.3 V PCI Per PCI spec. 2 mA - High 10 pF - - - - - - - - - - - ns 25 4 0.60 2.05 0.04 0.66 0.43 2.09 1.49 2.46 2.74 3.80 3.21 ns R ev i si o n 1 3 2- 31 ProASIC3L DC and Switching Characteristics Units tZHS (ns) tZLS (ns) tHZ (ns) tLZ (ns) tZH (ns) tZL (ns) tEO UT (ns) tPY (ns) tDIN (ns) tDP (ns) tDOUT (ns) External Resistor () Capacitive Load (pF) Slew Rate Equiv. Software Default Drive Strength Option1 I/O Standard Drive Strength (mA) Table 2-33 * Summary of I/O Timing Characteristics--Software Default Settings -1 Speed Grade, Commercial-Case Conditions: TJ = 70C, Worst Case VCC = 1.14 V, Worst Case VCCI Advanced I/O Banks 25 4 0.60 2.05 0.04 0.64 0.43 2.09 1.49 2.46 2.74 3.80 3.21 ns 3.3 V PCI-X Per PCI-X spec. - High 10 pF LVDS 24 mA - High - - 0.60 1.40 0.04 1.23 N/A N/A N/A N/A N/A N/A N/A ns LVPECL 24 mA - High - - 0.60 1.38 0.04 1.08 N/A N/A N/A N/A N/A N/A N/A ns Notes: 1. The minimum drive strength for any LVCMOS 1.2 V or LVCMOS 3.3 V software configuration when run in wide range is 100 A. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification. 3. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12 specification. 4. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on page 2-81 for connectivity. This resistor is not required during normal operation. 5. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. 2- 32 R ev i sio n 1 3 ProASIC3L Low Power Flash FPGAs 3.3 V LVTTL / 3.3 V LVCMOS 12 mA 12 mA High 5 pF Units tZHS (ns) tZLS (ns) tHZ (ns) tLZ (ns) tZH (ns) tZL (ns) tEO UT (ns) tPY (ns) tDIN (ns) tDP (ns) tDOUT (ns) External Resistor Capacitive Load (pF) Slew Rate Equiv. Software Default Drive Strength Option1 I/O Standard Drive Strength (mA) Table 2-34 * Summary of I/O Timing Characteristics--Software Default Settings -1 Speed Grade, Commercial-Case Conditions: TJ = 70C, Worst Case VCC = 1.14 V, Worst Case VCCI = 3.0 V Standard Plus I/O Banks - 0.60 1.56 0.04 0.77 0.43 1.59 1.20 2.14 2.47 3.30 2.91 ns 3.3 V LVCMOS 100 A 12 mA High 5 pF Wide Range1,2 - 2.5 V LVCMOS - 0.60 1.59 0.04 0.99 0.43 1.61 1.32 2.16 2.38 3.33 3.03 ns 1.8 V LVCMOS 12 mA 12 mA High 5 pF - - - - - - - - - - - ns 8 mA 8 mA High 5 pF 1.5 V LVCMOS 4 mA 4 mA High 5 pF - 0.60 2.15 0.04 1.09 0.43 2.19 1.82 2.32 2.40 3.90 3.53 ns 1.2 V LVCMOS 2 mA 2 mA High 5 pF - 0.60 3.54 0.04 1.56 0.43 2.37 2.11 3.60 3.87 4.02 3.76 ns 1.2 V LVCMOS 100 A 2 mA High 5 pF Wide Range1,3 - 0.60 1.59 0.04 0.99 0.43 1.61 1.32 2.16 2.38 3.33 3.03 ns - - - - - - - - - - - - ns 3.3 V PCI Per PCI spec. - High 10 pF 25 4 0.60 1.77 0.04 0.65 0.43 1.80 1.31 2.14 2.47 3.51 3.02 ns 3.3 V PCI-X Per PCI-X spec. - High 10 pF 25 4 0.60 1.77 0.04 0.64 0.43 1.80 1.31 2.14 2.47 3.51 3.02 ns Notes: 1. The minimum drive strength for any LVCMOS 1.2 V or LVCMOS 3.3 V software configuration when run in wide range is 100 A. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification. 3. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12 specification. 4. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on page 2-81 for connectivity. This resistor is not required during normal operation. 5. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Detailed I/O DC Characteristics Table 2-35 * Input Capacitance Symbol Definition Conditions Min. Max. Units CIN Input capacitance VIN = 0, f = 1.0 MHz 8 pF CINCLK Input capacitance on the clock pin VIN = 0, f = 1.0 MHz 8 pF R ev i si o n 1 3 2- 33 ProASIC3L DC and Switching Characteristics Table 2-36 * I/O Output Buffer Maximum Resistances1 Applicable to Pro I/Os Standard 3.3 V LVTTL / 3.3 V LVCMOS 3.3 V LVCMOS Wide Range 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 1.2 V LVCMOS 1.2 V LVCMOS Wide Range 3.3 V PCI/PCI-X Drive Strength RPULL-DOWN () 2 RPULL-UP () 3 4 mA 100 300 8 mA 50 150 12 mA 25 75 16 mA 17 50 24 mA 11 33 100 A Same as regular 3.3 V LVCMOS Same as regular 3.3 V LVCMOS 4 mA 100 200 8 mA 50 100 12 mA 25 50 16 mA 20 40 24 mA 11 22 2 mA 200 225 4 mA 100 112 6 mA 50 56 8 mA 50 56 12 mA 20 22 16 mA 20 22 2 mA 200 224 4 mA 100 112 6 mA 67 75 8 mA 33 37 12 mA 33 37 2 mA 158 164 100 A Per PCI/PCI-X specification Same as regular 1.2 V LVCMOS Same as regular 1.2 V LVCMOS 25 75 3.3 V GTL 20 mA4 11 - 2.5 V GTL 20 mA4 14 - 3.3 V GTL+ 35 mA 12 - 2.5 V GTL+ 33 mA 15 - HSTL (I) 8 mA 50 50 HSTL (II) 15 mA4 25 25 SSTL2 (I) 15 mA 27 31 SSTL2 (II) 18 mA 13 15 SSTL3 (I) 14 mA 44 69 SSTL3 (II) 21 mA 18 32 Notes: 1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend on VCCI, drive strength selection, temperature, and process. For board design considerations and detailed output buffer resistances, use the corresponding IBIS models located at http://www.microsemi.com/soc/download/ibis/default.aspx. 2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec 3. R(PULL-UP-MAX) = (VCCImax - VOHspec) / IOHspec 4. Output drive strength is below JEDEC specification. 2- 34 R ev i sio n 1 3 ProASIC3L Low Power Flash FPGAs Table 2-37 * I/O Output Buffer Maximum Resistances1 Applicable to Advanced I/O Banks Standard 3.3 V LVTTL / 3.3 V LVCMOS 3.3 V LVCMOS Wide Range 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 1.2 V LVCMOS 1.2 V LVCMOS Wide Range 3.3 V PCI/PCI-X Drive Strength RPULL-DOWN () 2 RPULL-UP () 3 2 mA 100 300 4 mA 100 300 6 mA 50 150 8 mA 50 150 12 mA 25 75 16 mA 17 50 24 mA 11 33 100 A Same as regular 3.3 V LVCMOS Same as regular 3.3 V LVCMOS 2 mA 100 300 4 mA 100 300 6 mA 50 150 8 mA 50 150 12 mA 25 75 16 mA 17 50 24 mA 11 33 2 mA 100 200 4 mA 100 200 6 mA 50 100 8 mA 50 100 12 mA 25 50 16 mA 20 40 2 mA 200 224 4 mA 100 112 6 mA 67 75 8 mA 33 37 12 mA 33 37 2 mA 158 164 100 A Same as regular 1.2 V LVCMOS Same as regular 1.2 V LVCMOS Per PCI/PCI-X specification 25 75 Notes: 1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend on VCCI, drive strength selection, temperature, and process. For board design considerations and detailed output buffer resistances, use the corresponding IBIS models located at http://www.microsemi.com/soc/download/ibis/default.aspx. 2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec 3. R(PULL-UP-MAX) = (VCCImax - VOHspec) / IOHspec R ev i si o n 1 3 2- 35 ProASIC3L DC and Switching Characteristics Table 2-38 * I/O Output Buffer Maximum Resistances1 Applicable to Standard Plus I/O Banks Standard 3.3 V LVTTL / 3.3 V LVCMOS 3.3 V LVCMOS Wide Range 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 1.2 V LVCMOS 1.2 V LVCMOS Wide Range 3.3 V PCI/PCI-X Drive Strength RPULL-DOWN () 2 RPULL-UP () 3 2 mA 100 300 4 mA 100 300 6 mA 50 150 8 mA 50 150 12 mA 25 75 16 mA 25 75 100 A Same as regular 3.3 V LVCMOS Same as regular 3.3 V LVCMOS 2 mA 100 200 4 mA 100 200 6 mA 50 100 8 mA 50 100 12 mA 25 50 2 mA 200 225 4 mA 100 112 6 mA 50 56 8 mA 50 56 2 mA 200 224 4 mA 100 112 2 mA 158 164 100 A Per PCI/PCI-X specification Same as regular 1.2 V LVCMOS Same as regular 1.2 V LVCMOS 25 75 Notes: 1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend on VCCI, drive strength selection, temperature, and process. For board design considerations and detailed output buffer resistances, use the corresponding IBIS models located at http://www.microsemi.com/soc/download/ibis/default.aspx. 2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec 3. R(PULL-UP-MAX) = (VCCImax - VOHspec) / IOHspec 2- 36 R ev i sio n 1 3 ProASIC3L Low Power Flash FPGAs Table 2-39 * I/O Weak Pull-Up/Pull-Down Resistances Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values R(WEAK PULL-UP)1 () R(WEAK PULL-DOWN)2 () VCCI Min. Max. Min. Max. 3.3 V 10 k 45 k 10 k 45 k 3.3 V (wide range I/Os) 10 k 45 k 10 k 45 k 2.5 V 11 k 55 k 12 k 74 k 1.8 V 18 k 70 k 17 k 110 k 1.5 V 19 k 90 k 19 k 140 k 1.2 V LVCMOS 25 k 110 k 25 k 150 k 1.2 V (wide range I/Os) 19 k 110 k 19 k 150 k Notes: 1. R(WEAK PULL-UP-MAX) = (VCCImax - VOHspec) / I(WEAK PULL-UP-MIN) 2. R(WEAK PULL-DOWN-MAX) = (VOLspec) / I(WEAK PULL-DOWN-MIN) R ev i si o n 1 3 2- 37 ProASIC3L DC and Switching Characteristics Table 2-40 * I/O Short Currents IOSH/IOSL Applicable to Pro I/Os Standard 3.3 V LVTTL / 3.3 V LVCMOS 3.3 V LVCMOS Wide Range 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 1.2 V LVCMOS 1.2 V LVCMOS Wide Range 3.3 V PCI/PCIX Drive Strength IOSL (mA)* IOSH (mA)* 4 mA 25 27 8 mA 51 54 12 mA 103 109 16 mA 132 127 24 mA 268 181 100 A Same as regular 3.3 V LVCMOS Same as regular 3.3 V LVCMOS 4 mA 16 18 8 mA 32 37 12 mA 65 74 16 mA 83 87 24 mA 169 124 2 mA 9 11 4 mA 17 22 6 mA 35 44 8 mA 45 51 12 mA 91 74 16 mA 91 74 2 mA 13 16 4 mA 25 33 6 mA 32 39 8 mA 66 55 12 mA 66 55 2 mA 20 26 100 A 20 Per PCI/PCI-X Specification 26 Per PCI Curves 3.3 V GTL 20 mA2 2.5 V GTL 2 169 124 3.3 V GTL+ 35 mA 268 181 2.5 V GTL+ 33 mA 169 124 HSTL (I) 8 mA 32 39 20 mA 268 181 HSTL (II) 2 15 mA 66 55 SSTL2 (I) 15 mA 83 87 SSTL2 (II) 18 mA 169 124 SSTL3 (I) 14 mA 51 54 Notes: 1. *TJ = 100C 2. Output drive strength is below JEDEC specification. 2- 38 R ev i sio n 1 3 ProASIC3L Low Power Flash FPGAs Table 2-41 * I/O Short Currents IOSH/IOSL Applicable to Advanced I/O Banks Standard 3.3 V LVTTL / 3.3 V LVCMOS 3.3 V LVCMOS Wide Range 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 1.2 V LVCMOS 1.2 V LVCMOS Wide Range 3.3 V PCI/PCI-X Drive Strength IOSL (mA)* IOSH (mA)* 2 mA 25 27 4 mA 25 27 6 mA 51 54 8 mA 51 54 12 mA 103 109 16 mA 132 127 24 mA 268 181 100 A Same as regular 3.3 V LVCMOS Same as regular 3.3 V LVCMOS 2 mA 16 18 4 mA 16 18 6 mA 32 37 8 mA 32 37 12 mA 65 74 16 mA 83 87 24 mA 169 124 2 mA 9 11 4 mA 17 22 6 mA 35 44 8 mA 45 51 12 mA 91 74 16 mA 91 74 2 mA 13 16 4 mA 25 33 6 mA 32 39 8 mA 66 55 12 mA 66 55 2 mA 20 26 100 A 20 26 Per PCI/PCI-X specification 103 109 Note: *TJ = 100C R ev i si o n 1 3 2- 39 ProASIC3L DC and Switching Characteristics Table 2-42 * I/O Short Currents IOSH/IOSL Applicable to Standard Plus I/O Banks 3.3 V LVTTL LVCMOS / 3.3 V 3.3 V LVCMOS Wide Range 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 1.2 V LVCMOS 1.2 V LVCMOS Wide Range 3.3 V PCI/PCI-X Drive Strength IOSL (mA)* IOSH (mA)* 2 mA 25 27 4 mA 25 27 6 mA 51 54 8 mA 51 54 12 mA 103 109 16 mA 103 109 100 A Same as regular 3.3 V LVCMOS Same as regular 3.3 V LVCMOS 2 mA 16 18 4 mA 16 18 6 mA 32 37 8 mA 32 37 12 mA 65 74 2 mA 9 11 4 mA 17 22 6 mA 35 44 8 mA 35 44 2 mA 13 16 4 mA 25 33 2 mA 20 26 100 A 20 26 Per PCI/PCI-X specification 103 109 Note: TJ = 100C Table 2-43 * Schmitt Trigger Input Hysteresis, Hysteresis Voltage Value (Typ) for Schmitt Mode Input Buffers Input Buffer Configuration Hysteresis Value (typ.) 3.3 V LVTTL/LVCMOS/PCI/PCI-X (Schmitt trigger mode) 240 mV 2.5 V LVCMOS (Schmitt trigger mode) 140 mV 1.8 V LVCMOS (Schmitt trigger mode) 80 mV 1.5 V LVCMOS (Schmitt trigger mode) 60 mV 1.2 V LVCMOS (Schmitt trigger mode) 40 mV The length of time an I/O can withstand IOSH/IOSL events depends on the junction temperature. The reliability data below is based on a 3.3 V, 12 mA I/O setting, which is the worst case for this type of analysis. For example, at 100C, the short current condition would have to be sustained for more than six months to cause a reliability concern. The I/O design does not contain any short circuit protection, but such protection would only be needed in extremely prolonged stress conditions. 2- 40 R ev i sio n 1 3 ProASIC3L Low Power Flash FPGAs Table 2-44 * Duration of Short Circuit Event before Failure Temperature Time before Failure -40C > 20 years 0C > 20 years 25C > 20 years 70C 5 years 85C 2 years 100C 6 months Table 2-45 * I/O Input Rise Time, Fall Time, and Related I/O Reliability Input Buffer Input Rise/Fall Time (min.) Input Rise/Fall Time (max.) Reliability LVTTL/LVCMOS No requirement 10 ns * 20 years (110C) LVDS/B-LVDS/ M-LVDS/LVPECL No requirement 10 ns * 10 years (100C) Note: *The maximum input rise/fall time is related to the noise induced into the input buffer trace. If the noise is low, then the rise time and fall time of input buffers can be increased beyond the maximum value. The longer the rise/fall times, the more susceptible the input signal is to the board noise. Microsemi recommends signal integrity evaluation/characterization of the system to ensure that there is no excessive noise coupling into input signals. R ev i si o n 1 3 2- 41 ProASIC3L DC and Switching Characteristics Single-Ended I/O Characteristics 3.3 V LVTTL / 3.3 V LVCMOS Low voltage transistor-transistor Logic (LVTTL) is a general-purpose standard (EIA/JESD) for 3.3 V applications. This standard uses an LVTTL input buffer and push-pull output buffer. Furthermore, all LVCMOS 3.3 V software macros comply with LVCMOS 3.3 V wide range, as specified in the JESD8-A specification. Table 2-46 * Minimum and Maximum DC Input and Output Levels Applicable to Pro I/O Banks 3.3 V LVTTL / 3.3 V LVCMOS VIL VIH Max. V VOL VOH IOL IOH IOSL IOSH IIL IIH Max. V Min. V mA mA Max. mA1 Max. mA1 A2 A2 Drive Strength Min. V Max. V Min. V 4 mA -0.3 0.8 2 3.6 0.4 2.4 4 4 25 27 10 10 6 mA -0.3 0.8 2 3.6 0.4 2.4 8 8 51 54 10 10 8 mA -0.3 0.8 2 3.6 0.4 2.4 12 12 103 109 10 10 12 mA -0.3 0.8 2 3.6 0.4 2.4 16 16 132 127 10 10 16 mA -0.3 0.8 2 3.6 0.4 2.4 24 24 268 181 10 10 24 mA -0.3 0.8 2 3.6 0.4 2.4 24 24 27 25 10 10 IIH Notes: 1. Currents are measured at 100C junction temperature and maximum voltage. 2. Currents are measured at 85C junction temperature. 3. Software default selection highlighted in gray. Table 2-47 * Minimum and Maximum DC Input and Output Levels Applicable to Advanced I/O Banks 3.3 V LVTTL / 3.3 V LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL mA mA Max. mA1 Max. mA1 A2 A2 Drive Strength Min. V Max. V Min. V Max. V Max. V Min. V 2 mA -0.3 0.8 2 3.6 0.4 2.4 2 2 25 27 10 10 4 mA -0.3 0.8 2 3.6 0.4 2.4 4 4 25 27 10 10 6 mA -0.3 0.8 2 3.6 0.4 2.4 6 6 51 54 10 10 8 mA -0.3 0.8 2 3.6 0.4 2.4 8 8 51 54 10 10 12 mA -0.3 0.8 2 3.6 0.4 2.4 12 12 103 109 10 10 16 mA -0.3 0.8 2 3.6 0.4 2.4 16 16 132 127 10 10 24 mA -0.3 0.8 2 3.6 0.4 2.4 24 24 268 181 10 10 Notes: 1. Currents are measured at 100C junction temperature and maximum voltage. 2. Currents are measured at 85C junction temperature. 3. Software default selection highlighted in gray. 2- 42 R ev i sio n 1 3 ProASIC3L Low Power Flash FPGAs Table 2-48 * Minimum and Maximum DC Input and Output Levels Applicable to Standard Plus I/O Banks 3.3 V LVTTL / 3.3 V LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH mA mA Max. mA1 Max. mA1 A2 A2 Drive Strength Min. V Max. V Min. V Max. V Max. V Min. V 2 mA -0.3 0.8 2 3.6 0.4 2.4 2 2 25 27 10 10 4 mA -0.3 0.8 2 3.6 0.4 2.4 4 4 25 27 10 10 6 mA -0.3 0.8 2 3.6 0.4 2.4 6 6 51 54 10 10 8 mA -0.3 0.8 2 3.6 0.4 2.4 8 8 51 54 10 10 12 mA -0.3 0.8 2 3.6 0.4 2.4 12 12 103 109 10 10 16 mA -0.3 0.8 2 3.6 0.4 2.4 16 16 103 109 10 10 Notes: 1. Currents are measured at 100C junction temperature and maximum voltage. 2. Currents are measured at 85C junction temperature. 3. Software default selection highlighted in gray. R=1k Test Point Enable Path Test Point Datapath Figure 2-7 * 5 pF R to VCCI for tLZ / tZL / tZLS R to GND for tHZ / tZH / tZHS 5 pF for tZH / tZHS / tZL / tZLS 5 pF for tHZ / tLZ AC Loading Table 2-49 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) 0 Input High (V) Measuring Point* (V) CLOAD (pF) 3.3 1.4 5 Note: *Measuring point = Vtrip. See Table 2-27 on page 2-26 for a complete table of trip points. R ev i si o n 1 3 2- 43 ProASIC3L DC and Switching Characteristics Timing Characteristics 1.5 V DC Core Voltage Table 2-50 * 3.3 V LVTTL / 3.3 V LVCMOS Low Slew - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Pro I/O Banks Drive Strength Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units 4 mA Std. 0.59 5.48 0.04 1.58 2.17 0.38 5.58 4.40 2.42 2.20 7.60 6.42 ns -1 0.50 4.66 0.03 1.34 1.85 0.33 4.75 3.75 2.06 1.87 6.46 5.46 ns 8 mA Std. 0.59 4.48 0.04 1.58 2.17 0.38 4.56 3.76 2.73 2.76 6.57 5.78 ns -1 0.50 3.81 0.03 1.34 1.85 0.33 3.88 3.20 2.33 2.35 5.59 4.91 ns 12 mA Std. 0.59 3.77 0.04 1.58 2.17 0.38 3.84 3.28 2.95 3.12 5.85 5.29 ns -1 0.50 3.21 0.03 1.34 1.85 0.33 3.27 2.79 2.51 2.65 4.98 4.50 ns 16 mA Std. 0.59 3.57 0.04 1.58 2.17 0.38 3.63 3.18 2.99 3.22 5.64 5.19 ns -1 0.50 3.03 0.03 1.34 1.85 0.33 3.09 2.70 2.54 2.74 4.80 4.41 ns Std. 0.59 3.46 0.04 1.58 2.17 0.38 3.52 3.19 3.05 3.57 5.54 5.20 ns -1 0.50 2.94 0.03 1.34 1.85 0.33 3.00 2.71 2.59 3.03 4.71 4.42 ns 24 mA Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-51 * 3.3 V LVTTL / 3.3 V LVCMOS High Slew - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Pro I/O Banks Drive Strength Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.59 3.08 0.04 1.58 2.17 0.38 3.14 2.36 2.42 2.33 5.15 4.38 ns -1 0.50 2.62 0.03 1.34 1.85 0.33 2.67 2.01 2.06 1.98 4.38 3.72 ns 8 mA Std. 0.59 2.53 0.04 1.58 2.17 0.38 2.58 1.89 2.74 2.89 4.59 3.90 ns -1 0.50 2.16 0.03 1.34 1.85 0.33 2.20 1.61 2.33 2.46 3.91 3.32 ns 12 mA Std. 0.59 2.22 0.04 1.58 2.17 0.38 2.27 1.67 2.95 3.25 4.28 3.68 ns -1 0.50 1.89 0.03 1.34 1.85 0.33 1.93 1.42 2.51 2.77 3.64 3.13 ns 16 mA Std. 0.59 2.17 0.04 1.58 2.17 0.38 2.21 1.63 3.00 3.35 4.23 3.64 ns -1 0.50 1.85 0.03 1.34 1.85 0.33 1.88 1.38 2.55 2.85 3.59 3.09 ns 24 mA Std. 0.59 2.19 0.04 1.58 2.17 0.38 2.24 1.57 3.05 3.71 4.25 3.58 ns -1 0.50 1.87 0.03 1.34 1.85 0.33 1.90 1.33 2.59 3.16 3.61 3.05 ns 4 mA Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. 2- 44 R ev i sio n 1 3 ProASIC3L Low Power Flash FPGAs Table 2-52 * 3.3 V LVTTL / 3.3 V LVCMOS Low Slew - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Advanced I/O Banks Drive Strength 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.54 5.11 0.04 0.91 0.38 5.21 4.33 2.38 2.21 7.22 6.34 ns -1 0.46 4.35 0.03 0.78 0.33 4.43 3.68 2.02 1.88 6.14 5.40 ns Std. 0.54 4.30 0.04 0.91 0.38 4.38 3.75 2.68 2.74 6.39 5.76 ns -1 0.46 3.66 0.03 0.78 0.33 3.73 3.19 2.28 2.33 5.44 4.90 ns Std. 0.54 4.30 0.04 0.91 0.38 4.38 3.75 2.68 2.74 6.39 5.76 ns -1 0.46 3.66 0.03 0.78 0.33 3.73 3.19 2.28 2.33 5.44 4.90 ns Std. 0.54 3.68 0.04 0.91 0.38 3.75 3.32 2.89 3.07 5.76 5.33 ns -1 0.46 3.13 0.03 0.78 0.33 3.19 2.82 2.45 2.62 4.90 4.53 ns Std. 0.54 3.50 0.04 0.91 0.38 3.56 3.21 2.93 3.16 5.57 5.23 ns -1 0.46 2.97 0.03 0.78 0.33 3.03 2.73 2.49 2.69 4.74 4.45 ns Std. 0.54 3.39 0.04 0.91 0.38 3.45 3.25 2.99 3.50 5.47 5.26 ns -1 0.46 2.88 0.03 0.78 0.33 2.94 2.76 2.54 2.97 4.65 4.48 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-53 * 3.3 V LVTTL / 3.3 V LVCMOS High Slew - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Advanced I/O Banks Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units 4 mA Std. 0.54 2.90 0.04 0.91 0.38 2.96 2.28 2.38 2.35 4.97 4.29 ns -1 0.46 2.47 0.03 0.78 0.33 2.52 1.94 2.03 2.00 4.23 3.65 ns 6 mA Std. 0.54 2.41 0.04 0.91 0.38 2.46 1.84 2.69 2.88 4.47 3.85 ns -1 0.46 2.05 0.03 0.78 0.33 2.09 1.57 2.29 2.45 3.80 3.28 ns 8 mA Std. 0.54 2.41 0.04 0.91 0.38 2.46 1.84 2.69 2.88 4.47 3.85 ns -1 0.46 2.05 0.03 0.78 0.33 2.09 1.57 2.29 2.45 3.80 3.28 ns 12 mA Std. 0.54 2.16 0.04 0.91 0.38 2.20 1.63 2.89 3.22 4.21 3.64 ns --1 0.46 1.83 0.03 0.78 0.33 1.87 1.39 2.46 2.74 3.58 3.10 ns 16 mA Std. 0.54 2.11 0.04 0.91 0.38 2.15 1.59 2.94 3.31 4.17 3.61 ns --1 0.46 1.80 0.03 0.78 0.33 1.83 1.36 2.50 2.82 3.54 3.07 ns 24 mA Std. 0.54 2.14 0.04 0.91 0.38 2.17 1.55 2.99 3.65 4.19 3.56 ns -1 0.46 1.82 0.03 0.78 0.33 1.85 1.32 2.54 3.11 3.56 3.03 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. R ev i si o n 1 3 2- 45 ProASIC3L DC and Switching Characteristics Table 2-54 * 3.3 V LVTTL / 3.3 V LVCMOS Low Slew - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard Plus I/O Banks Drive Strength 4 mA 6 mA 8 mA 12 mA 16 mA Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.54 4.61 0.04 0.90 0.38 4.70 3.91 2.05 1.99 6.71 5.92 ns -1 0.46 3.92 0.03 0.77 0.33 4.00 3.32 1.74 1.69 5.71 5.04 ns Std. 0.54 3.80 0.04 0.90 0.38 3.87 3.40 2.32 2.47 5.88 5.41 ns -1 0.46 3.23 0.03 0.77 0.33 3.29 2.89 1.98 2.10 5.00 4.60 ns Std. 0.54 3.80 0.04 0.90 0.38 3.87 3.40 2.32 2.47 5.88 5.41 ns -1 0.46 3.23 0.03 0.77 0.33 3.29 2.89 1.98 2.10 5.00 4.60 ns Std. 0.54 3.22 0.04 0.90 0.38 3.28 3.00 2.51 2.77 5.30 5.01 ns -1 0.46 2.74 0.03 0.77 0.33 2.79 2.55 2.14 2.36 4.51 4.27 ns Std. 0.54 3.22 0.04 0.90 0.38 3.28 3.00 2.51 2.77 5.30 5.01 ns -1 0.46 2.74 0.03 0.77 0.33 2.79 2.55 2.14 2.36 4.51 4.27 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-55 * 3.3 V LVTTL / 3.3 V LVCMOS High Slew - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard Plus I/O Banks Drive Strength 4 mA 6 mA 8 mA 12 mA 16 mA Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.54 2.51 0.04 0.90 0.38 2.56 2.01 2.05 2.10 4.57 4.02 ns -1 0.46 2.14 0.03 0.77 0.33 2.18 1.71 1.74 1.79 3.89 3.42 ns Std. 0.54 2.05 0.04 0.90 0.38 2.09 1.61 2.32 2.59 4.10 3.62 ns -1 0.46 1.74 0.03 0.77 0.33 1.78 1.37 1.97 2.20 3.49 3.08 ns Std. 0.54 2.05 0.04 0.90 0.38 2.09 1.61 2.32 2.59 4.10 3.62 ns -1 0.46 1.74 0.03 0.77 0.33 1.78 1.37 1.97 2.20 3.49 3.08 ns Std. 0.54 1.83 0.04 0.90 0.38 1.86 1.41 2.51 2.90 3.88 3.42 ns -1 0.46 1.56 0.03 0.77 0.33 1.59 1.20 2.14 2.47 3.30 2.91 ns Std. 0.54 1.83 0.04 0.90 0.38 1.86 1.41 2.51 2.90 3.88 3.42 ns -1 0.46 1.56 0.03 0.77 0.33 1.59 1.20 2.14 2.47 3.30 2.91 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. 2- 46 R ev i sio n 1 3 ProASIC3L Low Power Flash FPGAs 1.2 V DC Core Voltage Table 2-56 * 3.3 V LVTTL / 3.3 V LVCMOS Low Slew - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V Applicable to Pro I/O Banks Drive Strength Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.77 5.48 0.05 1.58 2.17 0.50 5.58 4.40 2.42 2.20 7.60 6.42 ns -1 0.66 4.66 0.04 1.34 1.85 0.43 4.75 3.75 2.06 1.87 6.46 5.46 ns 8 mA Std. 0.77 4.48 0.05 1.58 2.17 0.50 4.56 3.76 2.73 2.76 6.57 5.78 ns -1 0.66 3.81 0.04 1.34 1.85 0.43 3.88 3.20 2.33 2.35 5.59 4.91 ns 12 mA Std. 0.77 3.77 0.05 1.58 2.17 0.50 3.84 3.28 2.95 3.12 5.85 5.29 ns -1 0.66 3.21 0.04 1.34 1.85 0.43 3.27 2.79 2.51 2.65 4.98 4.50 ns 16 mA Std. 0.77 3.57 0.05 1.58 2.17 0.50 3.63 3.18 2.99 3.22 5.64 5.19 ns -1 0.66 3.03 0.04 1.34 1.85 0.43 3.09 2.70 2.54 2.74 4.80 4.41 ns 24 mA Std. 0.77 3.46 0.05 1.58 2.17 0.50 3.52 3.19 3.05 3.57 5.54 5.20 ns -1 0.66 2.94 0.04 1.34 1.85 0.43 3.00 2.71 2.59 3.03 4.71 4.42 ns 4 mA Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-57 * 3.3 V LVTTL / 3.3 V LVCMOS High Slew - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V Applicable to Pro I/O Banks Drive Strength 4 mA 8 mA 12 mA 16 mA 24 mA Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.77 3.08 0.05 1.58 2.17 0.50 3.14 2.36 2.42 2.33 5.15 4.38 ns -1 0.66 2.62 0.04 1.34 1.85 0.43 2.67 2.01 2.06 1.98 4.38 3.72 ns Std. 0.77 2.53 0.05 1.58 2.17 0.50 2.58 1.89 2.74 2.89 4.59 3.90 ns -1 0.66 2.16 0.04 1.34 1.85 0.43 2.20 1.61 2.33 2.46 3.91 3.32 ns Std. 0.77 2.22 0.05 1.58 2.17 0.50 2.27 1.67 2.95 3.25 4.28 3.68 ns -1 0.66 1.89 0.04 1.34 1.85 0.43 1.93 1.42 2.51 2.77 3.64 3.13 ns Std. 0.77 2.17 0.05 1.58 2.17 0.50 2.21 1.63 3.00 3.35 4.23 3.64 ns -1 0.66 1.85 0.04 1.34 1.85 0.43 1.88 1.38 2.55 2.85 3.59 3.09 ns Std. 0.77 2.19 0.05 1.58 2.17 0.50 2.24 1.57 3.05 3.71 4.25 3.58 ns -1 0.66 1.87 0.04 1.34 1.85 0.43 1.90 1.33 2.59 3.16 3.61 3.05 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. R ev i si o n 1 3 2- 47 ProASIC3L DC and Switching Characteristics Table 2-58 * 3.3 V LVTTL / 3.3 V LVCMOS Low Slew - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V Applicable to Advanced I/O Banks Drive Strength 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.70 5.11 0.05 0.91 0.50 5.21 4.33 2.38 2.21 7.22 6.34 ns -1 0.60 4.35 0.04 0.78 0.43 4.43 3.68 2.02 1.88 6.14 5.40 ns Std. 0.70 4.30 0.05 0.91 0.50 4.38 3.75 2.68 2.74 6.39 5.76 ns -1 0.60 3.66 0.04 0.78 0.43 3.73 3.19 2.28 2.33 5.44 4.90 ns Std. 0.70 4.30 0.05 0.91 0.50 4.38 3.75 2.68 2.74 6.39 5.76 ns -1 0.60 3.66 0.04 0.78 0.43 3.73 3.19 2.28 2.33 5.44 4.90 ns Std. 0.70 3.68 0.05 0.91 0.50 3.75 3.32 2.89 3.07 5.76 5.33 ns -1 0.60 3.13 0.04 0.78 0.43 3.19 2.82 2.45 2.62 4.90 4.53 ns Std. 0.70 3.50 0.05 0.91 0.50 3.56 3.21 2.93 3.16 5.57 5.23 ns -1 0.60 2.97 0.04 0.78 0.43 3.03 2.73 2.49 2.69 4.74 4.45 ns Std. 0.70 3.39 0.05 0.91 0.50 3.45 3.25 2.99 3.50 5.47 5.26 ns -1 0.60 2.88 0.04 0.78 0.43 2.94 2.76 2.54 2.97 4.65 4.48 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-59 * 3.3 V LVTTL / 3.3 V LVCMOS High Slew - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V Applicable to Advanced I/O Banks Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units 4 mA Std. 0.70 2.90 0.05 0.91 0.50 2.96 2.28 2.38 2.35 4.97 4.29 ns -1 0.60 2.47 0.04 0.78 0.43 2.52 1.94 2.03 2.00 4.23 3.65 ns 6 mA Std. 0.70 2.41 0.05 0.91 0.50 2.46 1.84 2.69 2.88 4.47 3.85 ns -1 0.60 2.05 0.04 0.78 0.43 2.09 1.57 2.29 2.45 3.80 3.28 ns 8 mA Std. 0.70 2.41 0.05 0.91 0.50 2.46 1.84 2.69 2.88 4.47 3.85 ns -1 0.60 2.05 0.04 0.78 0.43 2.09 1.57 2.29 2.45 3.80 3.28 ns 12 mA Std. 0.70 2.16 0.05 0.91 0.50 2.20 1.63 2.89 3.22 4.21 3.64 ns --1 0.60 1.83 0.04 0.78 0.43 1.87 1.39 2.46 2.74 3.58 3.10 ns 16 mA Std. 0.70 2.11 0.05 0.91 0.50 2.15 1.59 2.94 3.31 4.17 3.61 ns --1 0.60 1.80 0.04 0.78 0.43 1.83 1.36 2.50 2.82 3.54 3.07 ns 24 mA Std. 0.70 2.14 0.05 0.91 0.50 2.17 1.55 2.99 3.65 4.19 3.56 ns -1 0.60 1.82 0.04 0.78 0.43 1.85 1.32 2.54 3.11 3.56 3.03 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. 2- 48 R ev i sio n 1 3 ProASIC3L Low Power Flash FPGAs Table 2-60 * 3.3 V LVTTL / 3.3 V LVCMOS Low Slew - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V Applicable to Standard Plus I/O Banks Drive Strength 4 mA 6 mA 8 mA 12 mA 16 mA Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.70 4.61 0.05 0.90 0.50 4.70 3.91 2.05 1.99 6.71 5.92 ns -1 0.60 3.92 0.04 0.77 0.43 4.00 3.32 1.74 1.69 5.71 5.04 ns Std. 0.70 3.80 0.05 0.90 0.50 3.87 3.40 2.32 2.47 5.88 5.41 ns -1 0.60 3.23 0.04 0.77 0.43 3.29 2.89 1.98 2.10 5.00 4.60 ns Std. 0.70 3.80 0.05 0.90 0.50 3.87 3.40 2.32 2.47 5.88 5.41 ns -1 0.60 3.23 0.04 0.77 0.43 3.29 2.89 1.98 2.10 5.00 4.60 ns Std. 0.70 3.22 0.05 0.90 0.50 3.28 3.00 2.51 2.77 5.30 5.01 ns -1 0.60 2.74 0.04 0.77 0.43 2.79 2.55 2.14 2.36 4.51 4.27 ns Std. 0.70 3.22 0.05 0.90 0.50 3.28 3.00 2.51 2.77 5.30 5.01 ns -1 0.60 2.74 0.04 0.77 0.43 2.79 2.55 2.14 2.36 4.51 4.27 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-61 * 3.3 V LVTTL / 3.3 V LVCMOS High Slew - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V Applicable to Standard Plus I/O Banks Drive Strength 4 mA 6 mA 8 mA 12 mA 16 mA Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.70 2.51 0.05 0.90 0.50 2.56 2.01 2.05 2.10 4.57 4.02 ns -1 0.60 2.14 0.04 0.77 0.43 2.18 1.71 1.74 1.79 3.89 3.42 ns Std. 0.70 2.05 0.05 0.90 0.50 2.09 1.61 2.32 2.59 4.10 3.62 ns -1 0.60 1.74 0.04 0.77 0.43 1.78 1.37 1.97 2.20 3.49 3.08 ns Std. 0.70 2.05 0.05 0.90 0.50 2.09 1.61 2.32 2.59 4.10 3.62 ns -1 0.60 1.74 0.04 0.77 0.43 1.78 1.37 1.97 2.20 3.49 3.08 ns Std. 0.70 1.83 0.05 0.90 0.50 1.86 1.41 2.51 2.90 3.88 3.42 ns -1 0.60 1.56 0.04 0.77 0.43 1.59 1.20 2.14 2.47 3.30 2.91 ns Std. 0.70 1.83 0.05 0.90 0.50 1.86 1.41 2.51 2.90 3.88 3.42 ns -1 0.60 1.56 0.04 0.77 0.43 1.59 1.20 2.14 2.47 3.30 2.91 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. R ev i si o n 1 3 2- 49 ProASIC3L DC and Switching Characteristics 3.3 V LVCMOS Wide Range Table 2-62 * Minimum and Maximum DC Input and Output Levels for LVCMOS 3.3 V Wide Range Applicable to Pro I/O Banks 3.3 V LVCMOS Wide Range Equivalent Software Default Drive Strength Option1 Min. V Max. V Min. V 100 A 2 mA -0.3 0.8 100 A 4 mA -0.3 100 A 6 mA Drive Strength VIL VIH VOL VOH IOL IOH IOSH IOSL IIL IIH Max. V Max. V Min. V A A Max. Max. mA2 mA2 A A 2 3.6 0.2 VDD - 0.2 100 100 25 27 10 10 0.8 2 3.6 0.2 VDD - 0.2 100 100 25 27 10 10 -0.3 0.8 2 3.6 0.2 VDD - 0.2 100 100 51 54 10 10 100 A 8 mA -0.3 0.8 2 3.6 0.2 VDD - 0.2 100 100 51 54 10 10 100 A 12 mA -0.3 0.8 2 3.6 0.2 VDD - 0.2 100 100 103 109 10 10 100 A 16 mA -0.3 0.8 2 3.6 0.2 VDD - 0.2 100 100 132 127 10 10 100 A 24 mA -0.3 0.8 2 3.6 0.2 VDD - 0.2 100 100 268 181 10 10 Notes: 1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is 100 A. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. Currents are measured at 85C junction temperature. 3. All LVMCOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JDEC8-B specification 4. Software default selection highlighted in gray. Table 2-63 * Minimum and Maximum DC Input and Output Levels for LVCMOS 3.3 V Wide Range Applicable to Advanced I/O Banks 3.3 V LVCMOS Wide Range Equivalent Software Default Drive Strength Option1 Min. V Max. V Min. V 100 A 2 mA -0.3 0.8 100 A 4 mA -0.3 0.8 100 A 6 mA -0.3 100 A 8 mA -0.3 Drive Strength VIL VIH VOL VOH IOL IOH IOSH IOSL IIL IIH Max. V Max. V Min. V A A Max. Max. mA2 mA2 A A 2 3.6 0.2 VDD - 0.2 100 100 25 27 10 10 2 3.6 0.2 VDD - 0.2 100 100 25 27 10 10 0.8 2 3.6 0.2 VDD - 0.2 100 100 51 54 10 10 0.8 2 3.6 0.2 VDD - 0.2 100 100 51 54 10 10 100 A 12 mA -0.3 0.8 2 3.6 0.2 VDD - 0.2 100 100 51 54 10 10 100 A 16 mA -0.3 0.8 2 3.6 0.2 VDD - 0.2 100 100 103 109 10 10 100 A 24 mA -0.3 0.8 2 3.6 0.2 VDD - 0.2 100 100 132 127 10 10 Notes: 1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is 100 A. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. Currents are measured at 85C junction temperature. 3. All LVMCOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JDEC8-B specification 4. Software default selection highlighted in gray. 2- 50 R ev i sio n 1 3 ProASIC3L Low Power Flash FPGAs Table 2-64 * Minimum and Maximum DC Input and Output Levels for LVCMOS 3.3 V Wide Range Applicable to Standard Plus I/O Banks 3.3 V LVCMOS Wide Range Equivalent Software Default Drive Strength Option1 Min. V Max. V Min. V 100 A 2 mA -0.3 0.8 100 A 4 mA -0.3 100 A 6 mA 100 A 8 mA 100 A 100 A Drive Strength VIL VIH VOL VOH IOL IOH IOSH IOSL IIL IIH Max. V Max. V Min. V A A Max. Max. mA2 mA2 A A 2 3.6 0.2 VDD - 0.2 100 100 25 27 10 10 0.8 2 3.6 0.2 VDD - 0.2 100 100 25 27 10 10 -0.3 0.8 2 3.6 0.2 VDD - 0.2 100 100 51 54 10 10 -0.3 0.8 2 3.6 0.2 VDD - 0.2 100 100 51 54 10 10 12 mA -0.3 0.8 2 3.6 0.2 VDD - 0.2 100 100 103 109 10 10 16 mA -0.3 0.8 2 3.6 0.2 VDD - 0.2 100 100 103 109 10 10 Notes: 1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is 100 A. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. Currents are measured at 85C junction temperature. 3. All LVMCOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JDEC8-B specification 4. Software default selection highlighted in gray. R ev i si o n 1 3 2- 51 ProASIC3L DC and Switching Characteristics 2.5 V LVCMOS Low-Voltage CMOS for 2.5 V is an extension of the LVCMOS standard (JESD8-5) used for generalpurpose 2.5 V applications. Table 2-65 * Minimum and Maximum DC Input and Output Levels Applicable to Pro I/Os 2.5 V LVCMOS VOL VOH Drive Strength Min. V VIL Max. V Min. V VIH Max. V Max. V Min. V IOL IOH IOSL IOSH IIL mA mA Max. mA1 Max. mA1 A2 A2 4 mA -0.3 0.7 1.7 2.7 0.7 1.7 16 18 8 mA -0.3 0.7 1.7 2.7 0.7 1.7 8 8 32 37 10 10 12 mA -0.3 0.7 1.7 2.7 0.7 1.7 12 12 65 74 10 10 16 mA -0.3 0.7 1.7 2.7 0.7 1.7 16 16 83 87 10 10 24 mA -0.3 0.7 1.7 2.7 0.7 1.7 24 24 169 124 10 10 4 4 10 IIH 10 Notes: 1. Currents are measured at 100C junction temperature and maximum voltage. 2. Currents are measured at 85C junction temperature. 3. Software default selection highlighted in gray. Table 2-66 * Minimum and Maximum DC Input and Output Levels Applicable to Advanced I/O Banks 2.5 V LVCMOS VOL VOH Drive Strength Min. V VIL Max. V Min. V VIH Max. V Max. V Min. V IOL IOH IOSL IOSH IIL IIH mA mA Max. mA1 Max. mA1 A2 A2 2 mA -0.3 0.7 1.7 2.7 0.7 1.7 2 2 16 18 10 10 4 mA -0.3 0.7 1.7 2.7 0.7 1.7 6 mA -0.3 0.7 1.7 2.7 0.7 1.7 4 4 16 18 10 10 6 6 32 37 10 10 8 mA -0.3 0.7 1.7 2.7 0.7 1.7 8 8 32 37 10 10 12 mA -0.3 0.7 1.7 2.7 0.7 1.7 12 12 65 74 10 10 16 mA -0.3 0.7 1.7 2.7 0.7 1.7 16 16 83 87 10 10 24 mA -0.3 0.7 1.7 2.7 0.7 1.7 24 24 169 124 10 10 Notes: 1. Currents are measured at 100C junction temperature and maximum voltage. 2. Currents are measured at 85C junction temperature. 3. Software default selection highlighted in gray. 2- 52 R ev i sio n 1 3 ProASIC3L Low Power Flash FPGAs Table 2-67 * Minimum and Maximum DC Input and Output Levels Applicable to Standard Plus I/O Banks 2.5 V LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH mA mA Max. mA1 Max. mA1 A2 A2 Drive Strength Min. V Max. V Min. V Max. V Max. V Min. V 2 mA -0.3 0.7 1.7 2.7 0.7 1.7 2 2 16 18 10 10 4 mA -0.3 0.7 1.7 2.7 0.7 1.7 4 4 16 18 10 10 6 mA -0.3 0.7 1.7 2.7 0.7 1.7 6 6 32 37 10 10 8 mA -0.3 0.7 1.7 2.7 0.7 1.7 8 8 32 37 10 10 12 mA -0.3 0.7 1.7 2.7 0.7 1.7 12 12 65 74 10 10 Notes: 1. Currents are measured at 100C junction temperature and maximum voltage. 2. Currents are measured at 85C junction temperature. 3. Software default selection highlighted in gray. R=1k Test Point Enable Path Test Point Datapath Figure 2-8 * 5 pF R to VCCI for tLZ / tZL / tZLS R to GND for tHZ / tZH / tZHS 5 pF for tZH / tZHS / tZL / tZLS 5 pF for tHZ / tLZ AC Loading Table 2-68 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) 0 Input High (V) Measuring Point* (V) CLOAD (pF) 2.5 1.2 5 Note: *Measuring point = Vtrip. See Table 2-27 on page 2-26 for a complete table of trip points. R ev i si o n 1 3 2- 53 ProASIC3L DC and Switching Characteristics Timing Characteristics 1.5 V DC Core Voltage Table 2-69 * 2.5 V LVCMOS Low Slew - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Pro I/O Banks Drive Strength 4 mA 8 mA 12 mA 16 mA 24 mA Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.59 6.24 0.04 1.86 2.31 0.38 6.36 5.30 2.45 1.98 8.37 7.31 ns -1 0.50 5.31 0.03 1.58 1.97 0.33 5.41 4.51 2.08 1.68 7.12 6.22 ns Std. 0.59 5.10 0.04 1.86 2.31 0.38 5.20 4.49 2.79 2.64 7.21 6.50 ns -1 0.50 4.34 0.03 1.58 1.97 0.33 4.42 3.82 2.37 2.24 6.13 5.53 ns Std. 0.59 4.29 0.04 1.86 2.31 0.38 4.37 3.91 3.03 3.05 6.39 5.92 ns -1 0.50 3.65 0.03 1.58 1.97 0.33 3.72 3.32 2.58 2.60 5.43 5.04 ns Std. 0.59 4.05 0.04 1.86 2.31 0.38 4.12 3.78 3.08 3.17 6.13 5.79 ns -1 0.50 3.44 0.03 1.58 1.97 0.33 3.51 3.22 2.62 2.70 5.22 4.93 ns Std. 0.59 3.94 0.04 1.86 2.31 0.38 4.01 3.80 3.15 3.60 6.03 5.81 ns -1 0.50 3.35 0.03 1.58 1.97 0.33 3.41 3.23 2.68 3.06 5.13 4.94 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-70 * 2.5 V LVCMOS High Slew - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Pro I/O Banks Drive Strength 4 mA 8 mA 12 mA 16 mA 24 mA Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.59 3.18 0.04 1.86 2.31 0.38 3.24 2.84 2.45 2.06 5.25 4.85 ns -1 0.50 2.71 0.03 1.58 1.97 0.33 2.76 2.42 2.08 1.75 4.47 4.13 ns Std. 0.59 2.61 0.04 1.86 2.31 0.38 2.65 2.19 2.79 2.73 4.67 4.20 ns -1 0.50 2.22 0.03 1.58 1.97 0.33 2.26 1.86 2.37 2.32 3.97 3.57 ns Std. 0.59 2.26 0.04 1.86 2.31 0.38 2.30 1.86 3.03 3.15 4.32 3.88 ns -1 0.50 1.92 0.03 1.58 1.97 0.33 1.96 1.59 2.58 2.68 3.67 3.30 ns Std. 0.59 2.20 0.04 1.86 2.31 0.38 2.24 1.80 3.08 3.26 4.26 3.82 ns -1 0.50 1.87 0.03 1.58 1.97 0.33 1.91 1.54 2.62 2.77 3.62 3.25 ns Std. 0.59 2.21 0.04 1.86 2.31 0.38 2.25 1.73 3.15 3.70 4.27 3.74 ns -1 0.50 1.88 0.03 1.58 1.97 0.33 1.92 1.47 2.68 3.14 3.63 3.18 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. 2- 54 R ev i sio n 1 3 ProASIC3L Low Power Flash FPGAs Table 2-71 * 2.5 V LVCMOS Low Slew - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Advanced I/O Banks Drive Strength 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.54 5.79 0.04 1.18 0.38 5.90 5.18 2.41 1.98 7.91 7.19 ns -1 0.46 4.92 0.03 1.00 0.33 5.01 4.40 2.05 1.69 6.73 6.11 ns Std. 0.54 4.84 0.04 1.18 0.38 4.93 4.43 2.74 2.60 6.94 6.44 ns -1 0.46 4.11 0.03 1.00 0.33 4.19 3.77 2.33 2.21 5.90 5.48 ns Std. 0.54 4.84 0.04 1.18 0.38 4.93 4.43 2.74 2.60 6.94 6.44 ns -1 0.46 4.11 0.03 1.00 0.33 4.19 3.77 2.33 2.21 5.90 5.48 ns Std. 0.54 4.13 0.04 1.18 0.38 4.21 3.92 2.97 2.99 6.22 5.93 ns -1 0.46 3.52 0.03 1.00 0.33 3.58 3.33 2.53 2.54 5.29 5.04 ns Std. 0.54 3.91 0.04 1.18 0.38 3.98 3.80 3.02 3.09 5.99 5.81 ns -1 0.46 3.32 0.03 1.00 0.33 3.39 3.23 2.57 2.63 5.10 4.94 ns Std. 0.54 3.85 0.04 1.18 0.38 3.87 3.85 3.09 3.48 5.88 5.87 ns -1 0.46 3.28 0.03 1.00 0.33 3.29 3.28 2.63 2.96 5.01 4.99 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-72 * 2.5 V LVCMOS High Slew - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Advanced I/O Banks Drive Strength 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.54 2.97 0.04 1.18 0.38 3.03 2.74 2.41 2.07 5.04 4.75 ns -1 0.46 2.53 0.03 1.00 0.33 2.58 2.33 2.05 1.76 4.29 4.04 ns Std. 0.54 2.44 0.04 1.18 0.38 2.49 2.12 2.74 2.70 4.50 4.13 ns -1 0.46 2.08 0.03 1.00 0.33 2.12 1.80 2.33 2.30 3.83 3.51 ns Std. 0.54 2.44 0.04 1.18 0.38 2.49 2.12 2.74 2.70 4.50 4.13 ns -1 0.46 2.08 0.03 1.00 0.33 2.12 1.80 2.33 2.30 3.83 3.51 ns Std. 0.54 2.17 0.04 1.18 0.38 2.21 1.82 2.97 3.09 4.22 3.83 ns -1 0.46 1.85 0.03 1.00 0.33 1.88 1.55 2.53 2.63 3.59 3.26 ns Std. 0.54 2.12 0.04 1.18 0.38 2.16 1.76 3.03 3.19 4.17 3.78 ns -1 0.46 1.81 0.03 1.00 0.33 1.84 1.50 2.57 2.72 3.55 3.21 ns Std. 0.54 2.13 0.04 1.18 0.38 2.17 1.71 3.09 3.60 4.19 3.72 ns -1 0.46 1.81 0.03 1.00 0.33 1.85 1.45 2.63 3.06 3.56 3.16 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. R ev i si o n 1 3 2- 55 ProASIC3L DC and Switching Characteristics Table 2-73 * 2.5 V LVCMOS Low Slew - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Standard Plus I/O Banks Drive Strength 4 mA 6 mA 8 mA 12 mA Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.54 5.27 0.04 1.17 0.38 5.37 4.68 2.03 1.79 7.38 6.69 ns -1 0.46 4.49 0.03 0.99 0.33 4.57 3.98 1.73 1.52 6.28 5.69 ns Std. 0.54 4.32 0.04 1.17 0.38 4.40 4.03 2.33 2.35 6.42 6.04 ns -1 0.46 3.68 0.03 0.99 0.33 3.75 3.43 1.98 2.00 5.46 5.14 ns Std. 0.54 4.32 0.04 1.17 0.38 4.40 4.03 2.33 2.35 6.42 6.04 ns -1 0.46 3.68 0.03 0.99 0.33 3.75 3.43 1.98 2.00 5.46 5.14 ns Std. 0.54 3.66 0.04 1.17 0.38 3.73 3.56 2.54 2.71 5.74 5.57 ns -1 0.46 3.12 0.03 0.99 0.33 3.17 3.03 2.16 2.30 4.89 4.74 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-74 * 2.5 V LVCMOS High Slew - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Standard Plus I/O Banks Drive Strength 4 mA 6 mA 8 mA 12 mA Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.54 2.60 0.04 1.17 0.38 2.65 2.39 2.03 1.87 4.66 4.40 ns -1 0.46 2.21 0.03 0.99 0.33 2.25 2.03 1.72 1.59 3.96 3.74 ns Std. 0.54 2.10 0.04 1.17 0.38 2.14 1.83 2.33 2.44 4.16 3.84 ns -1 0.46 1.79 0.03 0.99 0.33 1.82 1.56 1.98 2.07 3.54 3.27 ns Std. 0.54 2.10 0.04 1.17 0.38 2.14 1.83 2.33 2.44 4.16 3.84 ns -1 0.46 1.79 0.03 0.99 0.33 1.82 1.56 1.98 2.07 3.54 3.27 ns Std. 0.54 1.86 0.04 1.17 0.38 1.90 1.55 2.54 2.80 3.91 3.57 ns -1 0.46 1.59 0.03 0.99 0.33 1.61 1.32 2.16 2.38 3.33 3.03 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. 2- 56 R ev i sio n 1 3 ProASIC3L Low Power Flash FPGAs 1.2 V DC Core Voltage Table 2-75 * 2.5 V LVCMOS Low Slew - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V Applicable to Pro I/O Banks Drive Strength 4 mA 8 mA 12 mA 16 mA 24 mA Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.77 6.24 0.05 1.86 2.31 0.50 6.36 5.30 2.45 1.98 8.37 7.31 ns -1 0.66 5.31 0.04 1.58 1.97 0.43 5.41 4.51 2.08 1.68 7.12 6.22 ns Std. 0.77 5.10 0.05 1.86 2.31 0.50 5.20 4.49 2.79 2.64 7.21 6.50 ns -1 0.66 4.34 0.04 1.58 1.97 0.43 4.42 3.82 2.37 2.24 6.13 5.53 ns Std. 0.77 4.29 0.05 1.86 2.31 0.50 4.37 3.91 3.03 3.05 6.39 5.92 ns -1 0.66 3.65 0.04 1.58 1.97 0.43 3.72 3.32 2.58 2.60 5.43 5.04 ns Std. 0.77 4.05 0.05 1.86 2.31 0.50 4.12 3.78 3.08 3.17 6.13 5.79 ns -1 0.66 3.44 0.04 1.58 1.97 0.43 3.51 3.22 2.62 2.70 5.22 4.93 ns Std. 0.77 3.94 0.05 1.86 2.31 0.50 4.01 3.80 3.15 3.60 6.03 5.81 ns -1 0.66 3.35 0.04 1.58 1.97 0.43 3.41 3.23 2.68 3.06 5.13 4.94 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-76 * 2.5 V LVCMOS High Slew - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V Applicable to Pro I/Os Drive Strength 4 mA 8 mA 12 mA 16 mA 24 mA Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.77 3.18 0.05 1.86 2.31 0.50 3.24 2.84 2.45 2.06 5.25 4.85 ns -1 0.66 2.71 0.04 1.58 1.97 0.43 2.76 2.42 2.08 1.75 4.47 4.13 ns Std. 0.77 2.61 0.05 1.86 2.31 0.50 2.65 2.19 2.79 2.73 4.67 4.20 ns -1 0.66 2.22 0.04 1.58 1.97 0.43 2.26 1.86 2.37 2.32 3.97 3.57 ns Std. 0.77 2.26 0.05 1.86 2.31 0.50 2.30 1.86 3.03 3.15 4.32 3.88 ns -1 0.66 1.92 0.04 1.58 1.97 0.43 1.96 1.59 2.58 2.68 3.67 3.30 ns Std. 0.77 2.20 0.05 1.86 2.31 0.50 2.24 1.80 3.08 3.26 4.26 3.82 ns -1 0.66 1.87 0.04 1.58 1.97 0.43 1.91 1.54 2.62 2.77 3.62 3.25 ns Std. 0.77 2.21 0.05 1.86 2.31 0.50 2.25 1.73 3.15 3.70 4.27 3.74 ns -1 0.66 1.88 0.04 1.58 1.97 0.43 1.92 1.47 2.68 3.14 3.63 3.18 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. R ev i si o n 1 3 2- 57 ProASIC3L DC and Switching Characteristics Table 2-77 * 2.5 V LVCMOS Low Slew - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V Applicable to Advanced I/Os Drive Strength 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.70 5.79 0.05 1.18 0.50 5.90 5.18 2.41 1.98 7.91 7.19 ns -1 0.60 4.92 0.04 1.00 0.43 5.01 4.40 2.05 1.69 6.73 6.11 ns Std. 0.70 4.84 0.05 1.18 0.50 4.93 4.43 2.74 2.60 6.94 6.44 ns -1 0.60 4.11 0.04 1.00 0.43 4.19 3.77 2.33 2.21 5.90 5.48 ns Std. 0.70 4.84 0.05 1.18 0.50 4.93 4.43 2.74 2.60 6.94 6.44 ns -1 0.60 4.11 0.04 1.00 0.43 4.19 3.77 2.33 2.21 5.90 5.48 ns Std. 0.70 4.13 0.05 1.18 0.50 4.21 3.92 2.97 2.99 6.22 5.93 ns -1 0.60 3.52 0.04 1.00 0.43 3.58 3.33 2.53 2.54 5.29 5.04 ns Std. 0.70 3.91 0.05 1.18 0.50 3.98 3.80 3.02 3.09 5.99 5.81 ns -1 0.60 3.32 0.04 1.00 0.43 3.39 3.23 2.57 2.63 5.10 4.94 ns Std. 0.70 3.85 0.05 1.18 0.50 3.87 3.85 3.09 3.48 5.88 5.87 ns -1 0.60 3.28 0.04 1.00 0.43 3.29 3.28 2.63 2.96 5.01 4.99 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-78 * 2.5 V LVCMOS High Slew - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V Applicable to Advanced I/Os Drive Strength 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.70 2.97 0.05 1.18 0.50 3.03 2.74 2.41 2.07 5.04 4.75 ns -1 0.60 2.53 0.04 1.00 0.43 2.58 2.33 2.05 1.76 4.29 4.04 ns Std. 0.70 2.44 0.05 1.18 0.50 2.49 2.12 2.74 2.70 4.50 4.13 ns -1 0.60 2.08 0.04 1.00 0.43 2.12 1.80 2.33 2.30 3.83 3.51 ns Std. 0.70 2.44 0.05 1.18 0.50 2.49 2.12 2.74 2.70 4.50 4.13 ns -1 0.60 2.08 0.04 1.00 0.43 2.12 1.80 2.33 2.30 3.83 3.51 ns Std. 0.70 2.17 0.05 1.18 0.50 2.21 1.82 2.97 3.09 4.22 3.83 ns -1 0.60 1.85 0.04 1.00 0.43 1.88 1.55 2.53 2.63 3.59 3.26 ns Std. 0.70 2.12 0.05 1.18 0.50 2.16 1.76 3.03 3.19 4.17 3.78 ns -1 0.60 1.81 0.04 1.00 0.43 1.84 1.50 2.57 2.72 3.55 3.21 ns Std. 0.70 2.13 0.05 1.18 0.50 2.17 1.71 3.09 3.60 4.19 3.72 ns -1 0.60 1.81 0.04 1.00 0.43 1.85 1.45 2.63 3.06 3.56 3.16 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. 2- 58 R ev i sio n 1 3 ProASIC3L Low Power Flash FPGAs Table 2-79 * 2.5 V LVCMOS Low Slew - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V Applicable to Standard Plus I/Os Drive Strength 4 mA 6 mA 8 mA 12 mA Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.70 5.27 0.05 1.17 0.50 5.37 4.68 2.03 1.79 7.38 6.69 ns -1 0.60 4.49 0.04 0.99 0.43 4.57 3.98 1.73 1.52 6.28 5.69 ns Std. 0.70 4.32 0.05 1.17 0.50 4.40 4.03 2.33 2.35 6.42 6.04 ns -1 0.60 3.68 0.04 0.99 0.43 3.75 3.43 1.98 2.00 5.46 5.14 ns Std. 0.70 4.32 0.05 1.17 0.50 4.40 4.03 2.33 2.35 6.42 6.04 ns -1 0.60 3.68 0.04 0.99 0.43 3.75 3.43 1.98 2.00 5.46 5.14 ns Std. 0.70 3.66 0.05 1.17 0.50 3.73 3.56 2.54 2.71 5.74 5.57 ns -1 0.60 3.12 0.04 0.99 0.43 3.17 3.03 2.16 2.30 4.89 4.74 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-80 * 2.5 V LVCMOS High Slew - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V Applicable to Standard Plus I/Os Drive Strength 4 mA 6 mA 8 mA 12 mA Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.70 2.60 0.05 1.17 0.50 2.65 2.39 2.03 1.87 4.66 4.40 ns -1 0.60 2.21 0.04 0.99 0.43 2.25 2.03 1.72 1.59 3.96 3.74 ns Std. 0.70 2.10 0.05 1.17 0.50 2.14 1.83 2.33 2.44 4.16 3.84 ns -1 0.60 1.79 0.04 0.99 0.43 1.82 1.56 1.98 2.07 3.54 3.27 ns Std. 0.70 2.10 0.05 1.17 0.50 2.14 1.83 2.33 2.44 4.16 3.84 ns -1 0.60 1.79 0.04 0.99 0.43 1.82 1.56 1.98 2.07 3.54 3.27 ns Std. 0.70 1.86 0.05 1.17 0.50 1.90 1.55 2.54 2.80 3.91 3.57 ns -1 0.60 1.59 0.04 0.99 0.43 1.61 1.32 2.16 2.38 3.33 3.03 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. R ev i si o n 1 3 2- 59 ProASIC3L DC and Switching Characteristics 1.8 V LVCMOS Low-voltage CMOS for 1.8 V is an extension of the LVCMOS standard (JESD8-5) used for generalpurpose 1.8 V applications. It uses a 1.8 V input buffer and a push-pull output buffer. Table 2-81 * Minimum and Maximum DC Input and Output Levels Applicable to Pro I/Os 1.8 V LVCMOS VIL VIH VOL VOH IOL IOH IOSL mA mA Max. mA1 IOSH IIL IIH Max. mA1 A2 A2 Drive Strength Min. V Max. V Min. V Max. V Max. V Min. V 2 mA -0.3 0.35 * VCCI 0.65 * VCCI 1.9 0.45 VCCI - 0.45 2 2 9 11 10 10 4 mA -0.3 0.35 * VCCI 0.65 * VCCI 1.9 0.45 VCCI - 0.45 4 4 17 22 10 10 6 mA -0.3 0.35 * VCCI 0.65 * VCCI 1.9 0.45 VCCI - 0.45 6 6 35 44 10 10 8 mA -0.3 0.35 * VCCI 0.65 * VCCI 1.9 0.45 VCCI - 0.45 8 8 45 51 10 10 12 mA -0.3 0.35 * VCCI 0.65 * VCCI 1.9 0.45 VCCI - 0.45 12 12 91 74 10 10 16 mA -0.3 0.35 * VCCI 0.65 * VCCI 1.9 0.45 VCCI - 0.45 16 16 91 74 10 10 Notes: 1. Currents are measured at 100C junction temperature and maximum voltage. 2. Currents are measured at 85C junction temperature. 3. Software default selection highlighted in gray. Table 2-82 * Minimum and Maximum DC Input and Output Levels Applicable to Advanced I/O Banks 1.8 V LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH mA mA Max. mA1 Max. mA1 A2 A2 Drive Strength Min. V Max. V Min. V Max. V Max. V Min. V 2 mA -0.3 0.35 * VCCI 0.65 * VCCI 1.9 0.45 VCCI - 0.45 2 2 9 11 10 10 4 mA -0.3 0.35 * VCCI 0.65 * VCCI 1.9 0.45 VCCI - 0.45 4 4 17 22 10 10 6 mA -0.3 0.35 * VCCI 0.65 * VCCI 1.9 0.45 VCCI - 0.45 6 6 35 44 10 10 8 mA -0.3 0.35 * VCCI 0.65 * VCCI 1.9 0.45 VCCI - 0.45 8 8 45 51 10 10 12 mA -0.3 0.35 * VCCI 0.65 * VCCI 1.9 0.45 VCCI - 0.45 12 12 91 74 10 10 16 mA -0.3 0.35 * VCCI 0.65 * VCCI 1.9 0.45 VCCI - 0.45 16 16 91 74 10 10 Notes: 1. Currents are measured at 100C junction temperature and maximum voltage. 2. Currents are measured at 85C junction temperature. 3. Software default selection highlighted in gray. 2- 60 R ev i sio n 1 3 ProASIC3L Low Power Flash FPGAs Table 2-83 * Minimum and Maximum DC Input and Output Levels Applicable to Standard Plus I/O I/O Banks 1.8 V LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH mA mA Max. mA1 Max. mA1 A2 A2 Drive Strength Min. V Max. V Min. V Max. V Max. V Min. V 2 mA -0.3 0.35 * VCCI 0.65 * VCCI 1.9 0.45 VCCI - 0.45 2 2 9 11 10 10 4 mA -0.3 0.35 * VCCI 0.65 * VCCI 1.9 0.45 VCCI - 0.45 4 4 17 22 10 10 6 mA -0.3 0.35 * VCCI 0.65 * VCCI 1.9 0.45 VCCI - 0.45 6 6 35 44 10 10 8 mA -0.3 0.35 * VCCI 0.65 * VCCI 1.9 0.45 VCCI - 0.45 8 8 35 44 10 10 Notes: 1. Currents are measured at 100C junction temperature and maximum voltage. 2. Currents are measured at 85C junction temperature. 3. Software default selection highlighted in gray. R=1k Test Point Enable Path Test Point Datapath Figure 2-9 * 5 pF R to VCCI for tLZ / tZL / tZLS R to GND for tHZ / tZH / tZHS 5 pF for tZH / tZHS / tZL / tZLS 5 pF for tHZ / tLZ AC Loading Table 2-84 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) 0 Input High (V) Measuring Point* (V) CLOAD (pF) 1.8 0.9 5 Note: *Measuring point = Vtrip. See Table 2-27 on page 2-26 for a complete table of trip points. R ev i si o n 1 3 2- 61 ProASIC3L DC and Switching Characteristics Timing Characteristics 1.5 V DC Core Voltage Table 2-85 * 1.8 V LVCMOS Low Slew - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V Applicable to Pro I/O Banks Drive Strength 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.59 8.32 0.04 1.80 2.55 0.38 8.48 6.99 2.50 1.42 10.49 9.00 ns -1 0.50 7.08 0.03 1.53 2.17 0.33 7.21 5.95 2.13 1.21 8.92 7.66 ns Std. 0.59 6.85 0.04 1.80 2.55 0.38 6.98 5.89 2.93 2.50 8.99 7.90 ns -1 0.50 5.83 0.03 1.53 2.17 0.33 5.94 5.01 2.49 2.12 7.65 6.72 ns Std. 0.59 5.81 0.04 1.80 2.55 0.38 5.92 5.13 3.21 3.02 7.93 7.15 ns -1 0.50 4.94 0.03 1.53 2.17 0.33 5.03 4.37 2.73 2.57 6.75 6.08 ns Std. 0.59 5.46 0.04 1.80 2.55 0.38 5.56 4.99 3.28 3.17 7.57 7.00 ns -1 0.50 4.64 0.03 1.53 2.17 0.33 4.73 4.24 2.79 2.70 6.44 5.95 ns Std. 0.59 5.36 0.04 1.80 2.55 0.38 5.46 4.99 3.37 3.70 7.47 7.01 ns -1 0.50 4.56 0.03 1.53 2.17 0.33 4.64 4.25 2.86 3.14 6.35 5.96 ns Std. 0.59 5.36 0.04 1.80 2.55 0.38 5.46 4.99 3.37 3.70 7.47 7.01 ns -1 0.50 4.56 0.03 1.53 2.17 0.33 4.64 4.25 2.86 3.14 6.35 5.96 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-86 * 1.8 V LVCMOS High Slew - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V Applicable to Pro I/O Banks Drive Strength 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.59 3.76 0.04 1.80 2.55 0.38 3.83 3.68 2.50 1.47 5.84 5.70 ns -1 0.50 3.20 0.03 1.53 2.17 0.33 3.26 3.13 2.13 1.25 4.97 4.85 ns Std. 0.59 3.05 0.04 1.80 2.55 0.38 3.11 2.73 2.92 2.58 5.12 4.75 ns -1 0.50 2.59 0.03 1.53 2.17 0.33 2.64 2.33 2.49 2.19 4.35 4.04 ns Std. 0.59 2.61 0.04 1.80 2.55 0.38 2.66 2.27 3.21 3.12 4.67 4.28 ns -1 0.50 2.22 0.03 1.53 2.17 0.33 2.26 1.93 2.73 2.65 3.98 3.64 ns Std. 0.59 2.53 0.04 1.80 2.55 0.38 2.58 2.18 3.27 3.26 4.59 4.19 ns -1 0.50 2.15 0.03 1.53 2.17 0.33 2.19 1.85 2.78 2.77 3.90 3.57 ns Std. 0.59 2.52 0.04 1.80 2.55 0.38 2.56 2.07 3.36 3.81 4.58 4.08 ns -1 0.50 2.14 0.03 1.53 2.17 0.33 2.18 1.76 2.86 3.24 3.89 3.47 ns Std. 0.59 2.52 0.04 1.80 2.55 0.38 2.56 2.07 3.36 3.81 4.58 4.08 ns -1 0.50 2.14 0.03 1.53 2.17 0.33 2.18 1.76 2.86 3.24 3.89 3.47 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. 2- 62 R ev i sio n 1 3 ProASIC3L Low Power Flash FPGAs Table 2-87 * 1.8 V LVCMOS Low Slew - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V Applicable to Advanced I/O Banks Drive Strength 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.54 7.77 0.04 1.18 0.38 7.92 6.80 2.50 1.44 9.93 8.81 ns -1 0.46 6.61 0.03 1.00 0.33 6.73 5.78 2.13 1.22 8.45 7.49 ns Std. 0.54 6.38 0.04 1.18 0.38 6.50 5.78 2.91 2.46 8.51 7.79 ns -1 0.46 5.43 0.03 1.00 0.33 5.53 4.91 2.47 2.09 7.24 6.63 ns Std. 0.54 5.48 0.04 1.18 0.38 5.58 5.11 3.18 2.94 7.59 7.12 ns -1 0.46 4.66 0.03 1.00 0.33 4.75 4.35 2.71 2.51 6.46 6.06 ns Std. 0.54 5.17 0.04 1.18 0.38 5.26 4.97 3.24 3.07 7.27 6.98 ns -1 0.46 4.40 0.03 1.00 0.33 4.48 4.23 2.76 2.61 6.19 5.94 ns Std. 0.54 5.06 0.04 1.18 0.38 5.15 5.03 3.34 3.55 7.17 7.04 ns -1 0.46 4.30 0.03 1.00 0.33 4.38 4.28 2.84 3.02 6.10 5.99 ns Std. 0.54 5.06 0.04 1.18 0.38 5.15 5.03 3.34 3.55 7.17 7.04 ns -1 0.46 4.30 0.03 1.00 0.33 4.38 4.28 2.84 3.02 6.10 5.99 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-88 * 1.8 V LVCMOS High Slew - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V Applicable to Advanced I/O Banks Drive Strength 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.54 3.60 0.04 1.10 0.38 3.66 3.52 2.49 1.49 5.68 5.53 ns -1 0.46 3.06 0.03 0.93 0.33 3.12 3.00 2.12 1.27 4.83 4.71 ns Std. 0.54 2.81 0.04 1.10 0.38 2.87 2.64 2.90 2.55 4.88 4.65 ns -1 0.46 2.39 0.03 0.93 0.33 2.44 2.25 2.47 2.17 4.15 3.96 ns Std. 0.54 2.47 0.04 1.10 0.38 2.51 2.21 3.18 3.04 4.53 4.22 ns -1 0.46 2.10 0.03 0.93 0.33 2.14 1.88 2.70 2.59 3.85 3.59 ns Std. 0.54 2.40 0.04 1.10 0.38 2.45 2.13 3.24 3.17 4.46 4.14 ns -1 0.46 2.04 0.03 0.93 0.33 2.08 1.81 2.76 2.70 3.79 3.52 ns Std. 0.54 2.39 0.04 1.10 0.38 2.44 2.04 3.33 3.67 4.45 4.05 ns -1 0.46 2.04 0.03 0.93 0.33 2.08 1.73 2.83 3.12 3.79 3.45 ns Std. 0.54 2.39 0.04 1.10 0.38 2.44 2.04 3.33 3.67 4.45 4.05 ns -1 0.46 2.04 0.03 0.93 0.33 2.08 1.73 2.83 3.12 3.79 3.45 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. R ev i si o n 1 3 2- 63 ProASIC3L DC and Switching Characteristics Table 2-89 * 1.8 V LVCMOS Low Slew - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V Applicable to Standard Plus I/O Banks Drive Strength 2 mA 4 mA 6 mA 8 mA Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.54 7.21 0.04 1.17 0.38 7.35 6.14 2.03 1.32 9.36 8.16 ns -1 0.46 6.13 0.03 0.99 0.33 6.25 5.23 1.72 1.12 7.96 6.94 ns Std. 0.54 5.81 0.04 1.17 0.38 5.92 5.26 2.39 2.25 7.93 7.27 ns -1 0.46 4.94 0.03 0.99 0.33 5.03 4.47 2.03 1.91 6.74 6.19 ns Std. 0.54 4.96 0.04 1.17 0.38 5.05 4.65 2.64 2.69 7.06 6.66 ns -1 0.46 4.22 0.03 0.99 0.33 4.30 3.96 2.25 2.29 6.01 5.67 ns Std. 0.54 4.96 0.04 1.17 0.38 5.05 4.65 2.64 2.69 7.06 6.66 ns -1 0.46 4.22 0.03 0.99 0.33 4.30 3.96 2.25 2.29 6.01 5.67 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-90 * 1.8 V LVCMOS High Slew - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V Applicable to Standard Plus I/O Banks Drive Strength 2 mA 4 mA 6 mA 8 mA Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.54 3.22 0.04 1.08 0.38 3.28 3.04 2.02 1.37 5.30 5.06 ns -1 0.46 2.74 0.03 0.92 0.33 2.79 2.59 1.72 1.17 4.50 4.30 ns Std. 0.54 2.48 0.04 1.08 0.38 2.53 2.25 2.38 2.34 4.54 4.26 ns -1 0.46 2.11 0.03 0.92 0.33 2.15 1.92 2.03 1.99 3.86 3.63 ns Std. 0.54 2.17 0.04 1.08 0.38 2.21 1.86 2.64 2.79 4.22 3.87 ns -1 0.46 1.85 0.03 0.92 0.33 1.88 1.58 2.24 2.37 3.59 3.29 ns Std. 0.54 2.17 0.04 1.08 0.38 2.21 1.86 2.64 2.79 4.22 3.87 ns -1 0.46 1.85 0.03 0.92 0.33 1.88 1.58 2.24 2.37 3.59 3.29 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. 2- 64 R ev i sio n 1 3 ProASIC3L Low Power Flash FPGAs 1.2 V DC Core Voltage Table 2-91 * 1.8 V LVCMOS Low Slew - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V Applicable to Pro I/O Banks Drive Strength 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.77 8.32 0.05 1.80 2.55 0.50 8.48 6.99 2.50 1.42 10.49 9.00 ns -1 0.66 7.08 0.04 1.53 2.17 0.43 7.21 5.95 2.13 1.21 8.92 7.66 ns Std. 0.77 6.85 0.05 1.80 2.55 0.50 6.98 5.89 2.93 2.50 8.99 7.90 ns -1 0.66 5.83 0.04 1.53 2.17 0.43 5.94 5.01 2.49 2.12 7.65 6.72 ns Std. 0.77 5.81 0.05 1.80 2.55 0.50 5.92 5.13 3.21 3.02 7.93 7.15 ns -1 0.66 4.94 0.04 1.53 2.17 0.43 5.03 4.37 2.73 2.57 6.75 6.08 ns Std. 0.77 5.46 0.05 1.80 2.55 0.50 5.56 4.99 3.28 3.17 7.57 7.00 ns -1 0.66 4.64 0.04 1.53 2.17 0.43 4.73 4.24 2.79 2.70 6.44 5.95 ns Std. 0.77 5.36 0.05 1.80 2.55 0.50 5.46 4.99 3.37 3.70 7.47 7.01 ns -1 0.66 4.56 0.04 1.53 2.17 0.43 4.64 4.25 2.86 3.14 6.35 5.96 ns Std. 0.77 5.36 0.05 1.80 2.55 0.50 5.46 4.99 3.37 3.70 7.47 7.01 ns -1 0.66 4.56 0.04 1.53 2.17 0.43 4.64 4.25 2.86 3.14 6.35 5.96 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-92 * 1.8 V LVCMOS High Slew - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V Applicable to Pro I/O Banks Drive Strength 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.77 3.76 0.05 1.80 2.55 0.50 3.83 3.68 2.50 1.47 5.84 5.70 ns -1 0.66 3.20 0.04 1.53 2.17 0.43 3.26 3.13 2.13 1.25 4.97 4.85 ns Std. 0.77 3.05 0.05 1.80 2.55 0.50 3.11 2.73 2.92 2.58 5.12 4.75 ns -1 0.66 2.59 0.04 1.53 2.17 0.43 2.64 2.33 2.49 2.19 4.35 4.04 ns Std. 0.77 2.61 0.05 1.80 2.55 0.50 2.66 2.27 3.21 3.12 4.67 4.28 ns -1 0.66 2.22 0.04 1.53 2.17 0.43 2.26 1.93 2.73 2.65 3.98 3.64 ns Std. 0.77 2.53 0.05 1.80 2.55 0.50 2.58 2.18 3.27 3.26 4.59 4.19 ns -1 0.66 2.15 0.04 1.53 2.17 0.43 2.19 1.85 2.78 2.77 3.90 3.57 ns Std. 0.77 2.52 0.05 1.80 2.55 0.50 2.56 2.07 3.36 3.81 4.58 4.08 ns -1 0.66 2.14 0.04 1.53 2.17 0.43 2.18 1.76 2.86 3.24 3.89 3.47 ns Std. 0.77 2.52 0.05 1.80 2.55 0.50 2.56 2.07 3.36 3.81 4.58 4.08 ns -1 0.66 2.14 0.04 1.53 2.17 0.43 2.18 1.76 2.86 3.24 3.89 3.47 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. R ev i si o n 1 3 2- 65 ProASIC3L DC and Switching Characteristics Table 2-93 * 1.8 V LVCMOS Low Slew - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V Applicable to Advanced I/O Banks Drive Strength 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.70 7.77 0.05 1.18 0.50 7.92 6.80 2.50 1.44 9.93 8.81 ns -1 0.60 6.61 0.04 1.00 0.43 6.73 5.78 2.13 1.22 8.45 7.49 ns Std. 0.70 6.38 0.05 1.18 0.50 6.50 5.78 2.91 2.46 8.51 7.79 ns -1 0.60 5.43 0.04 1.00 0.43 5.53 4.91 2.47 2.09 7.24 6.63 ns Std. 0.70 5.48 0.05 1.18 0.50 5.58 5.11 3.18 2.94 7.59 7.12 ns -1 0.60 4.66 0.04 1.00 0.43 4.75 4.35 2.71 2.51 6.46 6.06 ns Std. 0.70 5.17 0.05 1.18 0.50 5.26 4.97 3.24 3.07 7.27 6.98 ns -1 0.60 4.40 0.04 1.00 0.43 4.48 4.23 2.76 2.61 6.19 5.94 ns Std. 0.70 5.06 0.05 1.18 0.50 5.15 5.03 3.34 3.55 7.17 7.04 ns -1 0.60 4.30 0.04 1.00 0.43 4.38 4.28 2.84 3.02 6.10 5.99 ns Std. 0.70 5.06 0.05 1.18 0.50 5.15 5.03 3.34 3.55 7.17 7.04 ns -1 0.60 4.30 0.04 1.00 0.43 4.38 4.28 2.84 3.02 6.10 5.99 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-94 * 1.8 V LVCMOS High Slew - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V Applicable to Advanced I/O Banks Drive Strength 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.70 3.60 0.05 1.10 0.50 3.66 3.52 2.49 1.49 5.68 5.53 ns -1 0.60 3.06 0.04 0.93 0.43 3.12 3.00 2.12 1.27 4.83 4.71 ns Std. 0.70 2.81 0.05 1.10 0.50 2.87 2.64 2.90 2.55 4.88 4.65 ns -1 0.60 2.39 0.04 0.93 0.43 2.44 2.25 2.47 2.17 4.15 3.96 ns Std. 0.70 2.47 0.05 1.10 0.50 2.51 2.21 3.18 3.04 4.53 4.22 ns -1 0.60 2.10 0.04 0.93 0.43 2.14 1.88 2.70 2.59 3.85 3.59 ns Std. 0.70 2.40 0.05 1.10 0.50 2.45 2.13 3.24 3.17 4.46 4.14 ns -1 0.60 2.04 0.04 0.93 0.43 2.08 1.81 2.76 2.70 3.79 3.52 ns Std. 0.70 2.39 0.05 1.10 0.50 2.44 2.04 3.33 3.67 4.45 4.05 ns -1 0.60 2.04 0.04 0.93 0.43 2.08 1.73 2.83 3.12 3.79 3.45 ns Std. 0.70 2.39 0.05 1.10 0.50 2.44 2.04 3.33 3.67 4.45 4.05 ns -1 0.60 2.04 0.04 0.93 0.43 2.08 1.73 2.83 3.12 3.79 3.45 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. 2- 66 R ev i sio n 1 3 ProASIC3L Low Power Flash FPGAs Table 2-95 * 1.8 V LVCMOS Low Slew - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7V Applicable to Standard Plus I/O Banks Drive Strength 2 mA 4 mA 6 mA 8 mA Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.70 7.21 0.05 1.17 0.50 7.35 6.14 2.03 1.32 9.36 8.16 ns -1 0.60 6.13 0.04 0.99 0.43 6.25 5.23 1.72 1.12 7.96 6.94 ns Std. 0.70 5.81 0.05 1.17 0.50 5.92 5.26 2.39 2.25 7.93 7.27 ns -1 0.60 4.94 0.04 0.99 0.43 5.03 4.47 2.03 1.91 6.74 6.19 ns Std. 0.70 4.96 0.05 1.17 0.50 5.05 4.65 2.64 2.69 7.06 6.66 ns -1 0.60 4.22 0.04 0.99 0.43 4.30 3.96 2.25 2.29 6.01 5.67 ns Std. 0.70 4.96 0.05 1.17 0.50 5.05 4.65 2.64 2.69 7.06 6.66 ns -1 0.60 4.22 0.04 0.99 0.43 4.30 3.96 2.25 2.29 6.01 5.67 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-96 * 1.8 V LVCMOS High Slew - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V Applicable to Standard Plus I/O Banks Drive Strength 2 mA 4 mA 6 mA 8 mA Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.70 3.22 0.05 1.08 0.50 3.28 3.04 2.02 1.37 5.30 5.06 ns -1 0.60 2.74 0.04 0.92 0.43 2.79 2.59 1.72 1.17 4.50 4.30 ns Std. 0.70 2.48 0.05 1.08 0.50 2.53 2.25 2.38 2.34 4.54 4.26 ns -1 0.60 2.11 0.04 0.92 0.43 2.15 1.92 2.03 1.99 3.86 3.63 ns Std. 0.70 2.17 0.05 1.08 0.50 2.21 1.86 2.64 2.79 4.22 3.87 ns -1 0.60 1.85 0.04 0.92 0.43 1.88 1.58 2.24 2.37 3.59 3.29 ns Std. 0.70 2.17 0.05 1.08 0.50 2.21 1.86 2.64 2.79 4.22 3.87 ns -1 0.60 1.85 0.04 0.92 0.43 1.88 1.58 2.24 2.37 3.59 3.29 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. R ev i si o n 1 3 2- 67 ProASIC3L DC and Switching Characteristics 1.5 V LVCMOS (JESD8-11) Low-Voltage CMOS for 1.5 V is an extension of the LVCMOS standard (JESD8-5) used for generalpurpose 1.5 V applications. It uses a 1.5 V input buffer and a push-pull output buffer. Table 2-97 * Minimum and Maximum DC Input and Output Levels Applicable to Pro I/Os 1.5 V LVCMOS VIL Drive Min. Strength V VIH Max. V Min. V Max. V VOL VOH IOL IOH IOSL Max. V Min. V mA mA Max. mA1 IOSH IIL IIH Max. mA1 A2 A2 2 mA -0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 2 2 13 16 10 10 4 mA -0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 4 4 25 33 10 10 6 mA -0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 6 6 32 39 10 10 8 mA -0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 8 8 66 55 10 10 12 mA -0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 12 12 66 55 10 10 0.75 * VCCI Notes: 1. Currents are measured at 100C junction temperature and maximum voltage. 2. Currents are measured at 85C junction temperature. 3. Software default selection highlighted in gray. Table 2-98 * Minimum and Maximum DC Input and Output Levels Applicable to Advanced I/O Banks 1.5 V LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH Max. V Min. V Max. mA mA mA1 Drive Strength Min. V Max. V Min. V Max. V 2 mA -0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 2 2 13 16 10 10 4 mA -0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 4 4 25 33 10 10 6 mA -0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 6 6 32 39 10 10 8 mA -0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 8 8 66 55 10 10 12 mA -0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 12 12 66 55 10 10 Notes: 1. Currents are measured at 100C junction temperature and maximum voltage. 2. Currents are measured at 85C junction temperature. 3. Software default selection highlighted in gray. 2- 68 R ev i sio n 1 3 Max. mA1 A2 A2 ProASIC3L Low Power Flash FPGAs Table 2-99 * Minimum and Maximum DC Input and Output Levels Applicable to Standard Plus I/O Banks 1.5 V LVCMOS VIL Drive Min. Strength V VIH Max. V Min. V Max. V VOL VOH IOL IOH IOSL IOSH IIL IIH Max. V Min. V mA mA Max. mA1 Max. mA1 A2 A2 2 mA -0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 2 2 13 16 10 10 4 mA -0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 4 4 25 33 10 10 Notes: 1. Currents are measured at 100C junction temperature and maximum voltage. 2. Currents are measured at 85C junction temperature. 3. Software default selection highlighted in gray. R=1k Test Point Enable Path Test Point Datapath 5 pF R to VCCI for tLZ / tZL / tZLS R to GND for tHZ / tZH / tZHS 5 pF for tZH / tZHS / tZL / tZLS 5 pF for tHZ / tLZ Figure 2-10 * AC Loading Table 2-100 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) 0 Input High (V) Measuring Point* (V) CLOAD (pF) 1.5 0.75 5 Note: *Measuring point = Vtrip. See Table 2-27 on page 2-26 for a complete table of trip points. R ev i si o n 1 3 2- 69 ProASIC3L DC and Switching Characteristics Timing Characteristics 1.5 V DC Core Voltage Table 2-101 * 1.5 V LVCMOS Low Slew - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V Applicable to Pro I/O Banks Drive Strength 2 mA 4 mA 6 mA 8 mA 12 mA Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.59 8.65 0.04 1.99 2.77 0.38 8.81 7.17 3.06 2.41 10.83 9.18 ns -1 0.50 7.36 0.03 1.69 2.36 0.33 7.50 6.10 2.61 2.05 9.21 7.81 ns Std. 0.59 7.40 0.04 1.99 2.77 0.38 7.53 6.26 3.39 3.02 9.55 8.27 ns -1 0.50 6.29 0.03 1.69 2.36 0.33 6.41 5.33 2.89 2.57 8.12 7.04 ns Std. 0.59 6.94 0.04 1.99 2.77 0.38 7.07 6.09 3.46 3.19 9.08 8.11 ns -1 0.50 5.91 0.03 1.69 2.36 0.33 6.01 5.18 2.94 2.72 7.73 6.90 ns Std. 0.59 6.85 0.04 1.99 2.77 0.38 6.98 6.10 3.57 3.80 8.99 8.11 ns -1 0.50 5.83 0.03 1.69 2.36 0.33 5.94 5.19 3.04 3.23 7.65 6.90 ns Std. 0.59 6.85 0.04 1.99 2.77 0.38 6.98 6.10 3.57 3.80 8.99 8.11 ns -1 0.50 5.83 0.03 1.69 2.36 0.33 5.94 5.19 3.04 3.23 7.65 6.90 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-102 * 1.5 V LVCMOS High Slew - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V Applicable to Pro I/O Banks Drive Strength 2 mA 4 mA 6 mA 8 mA 12 mA Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.59 3.55 0.04 1.99 2.77 0.38 3.62 3.22 3.05 2.51 5.63 5.23 ns -1 0.50 3.02 0.03 1.69 2.36 0.33 3.08 2.74 2.60 2.14 4.79 4.45 ns Std. 0.59 3.03 0.04 1.99 2.77 0.38 3.08 2.64 3.38 3.13 5.10 4.65 ns -1 0.50 2.58 0.03 1.69 2.36 0.33 2.62 2.25 2.87 2.66 4.34 3.96 ns Std. 0.59 2.93 0.04 1.99 2.77 0.38 2.98 2.53 3.45 3.30 4.99 4.54 ns -1 0.50 2.49 0.03 1.69 2.36 0.33 2.54 2.15 2.93 2.81 4.25 3.86 ns Std. 0.59 2.90 0.04 1.99 2.77 0.38 2.95 2.39 3.57 3.94 4.96 4.41 ns -1 0.50 2.46 0.03 1.69 2.36 0.33 2.51 2.04 3.03 3.35 4.22 3.75 ns Std. 0.59 2.90 0.04 1.99 2.77 0.38 2.95 2.39 3.57 3.94 4.96 4.41 ns -1 0.50 2.46 0.03 1.69 2.36 0.33 2.51 2.04 3.03 3.35 4.22 3.75 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. 2- 70 R ev i sio n 1 3 ProASIC3L Low Power Flash FPGAs Table 2-103 * 1.5 V LVCMOS Low Slew - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V Applicable to Advanced I/O Banks Drive Strength 2 mA 4 mA 6 mA 8 mA 12 mA Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.54 8.00 0.04 1.18 0.38 8.15 7.01 3.06 2.38 10.16 9.02 ns -1 0.46 6.80 0.03 1.00 0.33 6.93 5.96 2.60 2.02 8.64 7.68 ns Std. 0.54 6.91 0.04 1.18 0.38 7.04 6.21 3.37 2.94 9.05 8.22 ns -1 0.46 5.88 0.03 1.00 0.33 5.99 5.28 2.87 2.50 7.70 7.00 ns Std. 0.54 6.51 0.04 1.18 0.38 6.63 6.05 3.45 3.09 8.64 8.06 ns -1 0.46 5.54 0.03 1.00 0.33 5.64 5.15 2.93 2.63 7.35 6.86 ns Std. 0.54 6.41 0.04 1.18 0.38 6.53 6.11 3.56 3.64 8.54 8.12 ns -1 0.46 5.45 0.03 1.00 0.33 5.56 5.20 3.03 3.10 7.27 6.91 ns Std. 0.54 6.41 0.04 1.18 0.38 6.53 6.11 3.56 3.64 8.54 8.12 ns -1 0.46 5.45 0.03 1.00 0.33 5.56 5.20 3.03 3.10 7.27 6.91 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-104 * 1.5 V LVCMOS High Slew - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V Applicable to Advanced I/O Banks Drive Strength 2 mA 4 mA 6 mA 8 mA 12 mA Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.54 3.60 0.04 1.10 0.38 3.66 3.52 2.49 1.49 5.68 5.53 ns -1 0.46 3.06 0.03 0.93 0.33 3.12 3.00 2.12 1.27 4.83 4.71 ns Std. 0.54 2.81 0.04 1.10 0.38 2.87 2.64 2.90 2.55 4.88 4.65 ns -1 0.46 2.39 0.03 0.93 0.33 2.44 2.25 2.47 2.17 4.15 3.96 ns Std. 0.54 2.47 0.04 1.10 0.38 2.51 2.21 3.18 3.04 4.53 4.22 ns -1 0.46 2.10 0.03 0.93 0.33 2.14 1.88 2.70 2.59 3.85 3.59 ns Std. 0.54 2.40 0.04 1.10 0.38 2.45 2.13 3.24 3.17 4.46 4.14 ns -1 0.46 2.04 0.03 0.93 0.33 2.08 1.81 2.76 2.70 3.79 3.52 ns Std. 0.54 2.39 0.04 1.10 0.38 2.44 2.04 3.33 3.67 4.45 4.05 ns -1 0.46 2.04 0.03 0.93 0.33 2.08 1.73 2.83 3.12 3.79 3.45 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. R ev i si o n 1 3 2- 71 ProASIC3L DC and Switching Characteristics Table 2-105 * 1.5 V LVCMOS Low Slew - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V Applicable to Standard Plus I/O Banks Drive Strength 2 mA 4 mA Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.54 7.32 0.04 1.17 0.38 7.45 6.38 2.44 2.18 9.46 8.40 ns -1 0.46 6.22 0.03 0.99 0.33 6.34 5.43 2.08 1.86 8.05 7.14 ns Std. 0.54 6.29 0.04 1.17 0.38 6.40 5.65 2.73 2.70 8.42 7.67 ns -1 0.46 5.35 0.03 0.99 0.33 5.45 4.81 2.33 2.29 7.16 6.52 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-106 * 1.5 V LVCMOS High Slew - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V Applicable to Standard Plus I/O Banks Drive Strength 2 mA 4 mA Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.54 2.90 0.04 1.28 0.38 2.95 2.63 2.44 2.29 4.97 4.64 ns -1 0.46 2.47 0.03 1.09 0.33 2.51 2.24 2.07 1.95 4.23 3.95 ns Std. 0.54 2.52 0.04 1.28 0.38 2.57 2.14 2.73 2.82 4.58 4.15 ns -1 0.46 2.15 0.03 1.09 0.33 2.19 1.82 2.32 2.40 3.90 3.53 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. 2- 72 R ev i sio n 1 3 ProASIC3L Low Power Flash FPGAs 1.2 V DC Core Voltage Table 2-107 * 1.5 V LVCMOS Low Slew - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V Applicable to Pro I/O Banks Drive Strength 2 mA 4 mA 6 mA 8 mA 12 mA Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.77 8.65 0.05 1.99 2.77 0.50 8.81 7.17 3.06 2.41 10.83 9.18 ns -1 0.66 7.36 0.04 1.69 2.36 0.43 7.50 6.10 2.61 2.05 9.21 7.81 ns Std. 0.77 7.40 0.05 1.99 2.77 0.50 7.53 6.26 3.39 3.02 9.55 8.27 ns -1 0.66 6.29 0.04 1.69 2.36 0.43 6.41 5.33 2.89 2.57 8.12 7.04 ns Std. 0.77 6.94 0.05 1.99 2.77 0.50 7.07 6.09 3.46 3.19 9.08 8.11 ns -1 0.66 5.91 0.04 1.69 2.36 0.43 6.01 5.18 2.94 2.72 7.73 6.90 ns Std. 0.77 6.85 0.05 1.99 2.77 0.50 6.98 6.10 3.57 3.80 8.99 8.11 ns -1 0.66 5.83 0.04 1.69 2.36 0.43 5.94 5.19 3.04 3.23 7.65 6.90 ns Std. 0.77 6.85 0.05 1.99 2.77 0.50 6.98 6.10 3.57 3.80 8.99 8.11 ns -1 0.66 5.83 0.04 1.69 2.36 0.43 5.94 5.19 3.04 3.23 7.65 6.90 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-108 * 1.5 V LVCMOS High Slew - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V Applicable to Pro I/O Banks Drive Strength 2 mA 4 mA 6 mA 8 mA 12 mA Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.77 3.55 0.05 1.99 2.77 0.50 3.62 3.22 3.05 2.51 5.63 5.23 ns -1 0.66 3.02 0.04 1.69 2.36 0.43 3.08 2.74 2.60 2.14 4.79 4.45 ns Std. 0.77 3.03 0.05 1.99 2.77 0.50 3.08 2.64 3.38 3.13 5.10 4.65 ns -1 0.66 2.58 0.04 1.69 2.36 0.43 2.62 2.25 2.87 2.66 4.34 3.96 ns Std. 0.77 2.93 0.05 1.99 2.77 0.50 2.98 2.53 3.45 3.30 4.99 4.54 ns -1 0.66 2.49 0.04 1.69 2.36 0.43 2.54 2.15 2.93 2.81 4.25 3.86 ns Std. 0.77 2.90 0.05 1.99 2.77 0.50 2.95 2.39 3.57 3.94 4.96 4.41 ns -1 0.66 2.46 0.04 1.69 2.36 0.43 2.51 2.04 3.03 3.35 4.22 3.75 ns Std. 0.77 2.90 0.05 1.99 2.77 0.50 2.95 2.39 3.57 3.94 4.96 4.41 ns -1 0.66 2.46 0.04 1.69 2.36 0.43 2.51 2.04 3.03 3.35 4.22 3.75 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. R ev i si o n 1 3 2- 73 ProASIC3L DC and Switching Characteristics Table 2-109 * 1.5 V LVCMOS Low Slew - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V Applicable to Advanced I/O Banks Drive Strength 2 mA 4 mA 6 mA 8 mA 12 mA Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.70 8.00 0.05 1.18 0.50 8.15 7.01 3.06 2.38 10.16 9.02 ns -1 0.60 6.80 0.04 1.00 0.43 6.93 5.96 2.60 2.02 8.64 7.68 ns Std. 0.70 6.91 0.05 1.18 0.50 7.04 6.21 3.37 2.94 9.05 8.22 ns -1 0.60 5.88 0.04 1.00 0.43 5.99 5.28 2.87 2.50 7.70 7.00 ns Std. 0.70 6.51 0.05 1.18 0.50 6.63 6.05 3.45 3.09 8.64 8.06 ns -1 0.60 5.54 0.04 1.00 0.43 5.64 5.15 2.93 2.63 7.35 6.86 ns Std. 0.70 6.41 0.05 1.18 0.50 6.53 6.11 3.56 3.64 8.54 8.12 ns -1 0.60 5.45 0.04 1.00 0.43 5.56 5.20 3.03 3.10 7.27 6.91 ns Std. 0.70 6.41 0.05 1.18 0.50 6.53 6.11 3.56 3.64 8.54 8.12 ns -1 0.60 5.45 0.04 1.00 0.43 5.56 5.20 3.03 3.10 7.27 6.91 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-110 * 1.5 V LVCMOS High Slew - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V Applicable to Advanced I/O Banks Drive Strength 2 mA 4 mA 6 mA 8 mA 12 mA Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.70 3.26 0.05 1.30 0.50 3.32 3.11 3.05 2.49 5.33 5.12 ns -1 0.60 2.77 0.04 1.10 0.43 2.82 2.64 2.59 2.12 4.53 4.36 ns Std. 0.70 2.84 0.05 1.30 0.50 2.89 2.57 3.37 3.06 4.90 4.59 ns -1 0.60 2.41 0.04 1.10 0.43 2.46 2.19 2.86 2.60 4.17 3.90 ns Std. 0.70 2.76 0.05 1.30 0.50 2.81 2.47 3.44 3.21 4.82 4.48 ns -1 0.60 2.35 0.04 1.10 0.43 2.39 2.10 2.92 2.73 4.10 3.81 ns Std. 0.70 2.74 0.05 1.30 0.50 2.79 2.36 3.55 3.78 4.80 4.37 ns -1 0.60 2.33 0.04 1.10 0.43 2.37 2.01 3.02 3.22 4.08 3.72 ns Std. 0.70 2.74 0.05 1.30 0.50 2.79 2.36 3.55 3.78 4.80 4.37 ns -1 0.60 2.33 0.04 1.10 0.43 2.37 2.01 3.02 3.22 4.08 3.72 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. 2- 74 R ev i sio n 1 3 ProASIC3L Low Power Flash FPGAs Table 2-111 * 1.5 V LVCMOS Low Slew - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V Applicable to Standard Plus I/O Banks Drive Strength 2 mA 4 mA Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.70 7.32 0.05 1.17 0.50 7.45 6.38 2.44 2.18 9.46 8.40 ns -1 0.60 6.22 0.04 0.99 0.43 6.34 5.43 2.08 1.86 8.05 7.14 ns Std. 0.70 6.29 0.05 1.17 0.50 6.40 5.65 2.73 2.70 8.42 7.67 ns -1 0.60 5.35 0.04 0.99 0.43 5.45 4.81 2.33 2.29 7.16 6.52 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-112 * 1.5 V LVCMOS High Slew - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V Applicable to Standard Plus I/O Banks Drive Strength 2 mA 4 mA Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.70 2.90 0.05 1.28 0.50 2.95 2.63 2.44 2.29 4.97 4.64 ns -1 0.60 2.47 0.04 1.09 0.43 2.51 2.24 2.07 1.95 4.23 3.95 ns Std. 0.70 2.52 0.05 1.28 0.50 2.57 2.14 2.73 2.82 4.58 4.15 ns -1 0.60 2.15 0.04 1.09 0.43 2.19 1.82 2.32 2.40 3.90 3.53 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. R ev i si o n 1 3 2- 75 ProASIC3L DC and Switching Characteristics 1.2 V LVCMOS (JESD8-12A) Low-Voltage CMOS for 1.2 V complies with the LVCMOS standard JESD8-12A for general purpose 1.2 V applications. It uses a 1.2 V input buffer and a push-pull output buffer. Table 2-113 * Minimum and Maximum DC Input and Output Levels Applicable to Advanced I/O Banks 1.2 V LVCMOS VIL Drive Strength Min. V 2 mA -0.3 VIH Max. V Min. V Max. V 0.35 * VCCI 0.65 * VCCI 1.26 VOL VOH IOL IOH IOSH1 Max. V Min. V mA mA 0.25 * VCCI 0.75 * VCCI 2 2 IOSL1 IIL2 IIH2 Max. mA Max. mA A A TBD TBD 10 10 Notes: 1. Currents are measured at 100C junction temperature and maximum voltage. 2. Currents are measured at 85C junction temperature. 3. Software default selection highlighted in gray. Table 2-114 * Minimum and Maximum DC Input and Output Levels Applicable to Standard Plus I/O Banks 1.2 V LVCMOS VIL Drive Strength Min. V 2 mA -0.3 Max. V VIH Min. V Max. V 0.35 * VCCI 0.65 * VCCI 1.26 VOL VOH IOL IOH IOSH1 IOSL1 IIL2 IIH2 Max. V Min. V mA mA 0.25 * VCCI 0.75 * VCCI 2 2 Max. mA Max. mA A A TBD TBD 10 10 IOSL1 IIL2 IIH2 Max. mA Max. mA A A TBD TBD 10 10 Notes: 1. Currents are measured at 100C junction temperature and maximum voltage. 2. Currents are measured at 85C junction temperature. 3. Software default selection highlighted in gray. Table 2-115 * Minimum and Maximum DC Input and Output Levels Applicable to Standard I/O Banks 1.2 V LVCMOS VIL Drive Strength Min. V 2 mA -0.3 Max. V VIH Min. V Max. V 0.35 * VCCI 0.65 * VCCI 1.26 VOL VOH IOL IOH IOSH1 Max. V Min. V mA mA 0.25 * VCCI 0.75 * VCCI 2 Notes: 1. Currents are measured at 100C junction temperature and maximum voltage. 2. Currents are measured at 85C junction temperature. 3. Software default selection highlighted in gray. 2- 76 R ev i sio n 1 3 2 ProASIC3L Low Power Flash FPGAs R=1k Test Point Enable Path Test Point Datapath 5 pF R to VCCI for tLZ / tZL / tZLS R to GND for tHZ / tZH / tZHS 5 pF for tZH / tZHS / tZL / tZLS 5 pF for tHZ / tLZ Figure 2-11 * AC Loading Table 2-116 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) 0 Input High (V) Measuring Point* (V) CLOAD (pF) 1.2 0.6 5 Note: *Measuring point = Vtrip. See Table 2-27 on page 2-26 for a complete table of trip points. R ev i si o n 1 3 2- 77 ProASIC3L DC and Switching Characteristics Timing Characteristics 1.2 V DC Core Voltage Table 2-117 * 1.2 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V Applicable to Pro I/O Banks Drive Strength 2 mA Speed Grade tDOUT Std. -1 tDP tDIN tPY tPYS tEOUT tZL tZH 0.77 11.80 0.05 2.38 3.52 0.50 10.97 8.61 0.66 10.04 0.04 2.02 2.99 0.43 9.33 7.32 tZLS tZHS Unit s 4.79 4.38 12.91 10.55 ns 4.08 3.72 10.98 8.97 ns tLZ tHZ Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-118 * 1.2 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V Applicable to Pro I/O Banks Drive Strength 2 mA tHZ tZLS tZHS Unit s 3.96 4.78 4.51 6.44 5.90 ns 3.37 4.06 3.84 5.48 5.02 ns Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH Std. 0.77 4.84 0.05 2.38 3.52 0.50 4.50 -1 0.66 4.12 0.04 2.02 2.99 0.43 3.83 tLZ Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-119 * 1.2 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V Applicable to Advanced I/O Banks Drive Strength Speed Grade tDOUT tDP tDIN 2 mA tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.70 8.77 0.05 1.82 0.50 6.17 5.45 2.80 2.77 8.11 7.39 ns -1 0.60 7.46 0.04 1.55 0.43 5.25 4.63 2.39 2.35 6.90 6.28 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-120 * 1.2 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V Applicable to Advanced I/O Banks Drive Strength Speed Grade tDOUT tDP tDIN 2 mA tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.70 3.73 0.05 1.82 0.50 2.48 2.06 2.80 2.89 4.42 4.00 ns -1 0.60 3.17 0.04 1.55 0.43 2.11 1.76 2.38 2.46 3.76 3.41 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-121 * 1.2 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V Applicable to Standard Plus I/O Banks Drive Strength Speed Grade tDOUT tDP tDIN 2 mA tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.70 9.67 0.05 1.83 0.50 6.78 5.99 4.08 4.57 8.72 7.93 ns -1 0.60 8.23 0.04 1.56 0.43 5.77 5.09 3.47 3.88 7.42 6.74 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. 2- 78 R ev i sio n 1 3 ProASIC3L Low Power Flash FPGAs Table 2-122 * 1.2 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V Applicable to Standard Plus I/O Banks Drive Strength Speed Grade tDOUT tDP tDIN 2 mA tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.70 4.17 0.05 1.83 0.50 2.79 2.48 4.23 4.55 4.73 4.42 ns -1 0.60 3.54 0.04 1.56 0.43 2.37 2.11 3.60 3.87 4.02 3.76 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. R ev i si o n 1 3 2- 79 ProASIC3L DC and Switching Characteristics 1.2 V LVCMOS Wide Range Table 2-123 * Minimum and Maximum DC Input and Output Levels for LVCMOS 1.2 V Wide Range Applicable to Pro I/O Banks 1.2 V Equivalent LVCMOS Software Wide Default Range Drive Drive Strength Min. Strength Option1 V 100 A 2 mA VIL Max. V VIH Min. V -0.3 0.35 * VCCI 0.65 * VCCI Max. V VOL VOH IOL IOH IOSH IOSL IIL IIH Max. V Min. V Max. Max. A A mA2 mA2 A A 3.6 0.25 * VCCI 0.75 * VCCI 100 100 20 26 10 10 Notes: 1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is 100 A. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. Currents are measured at 85C junction temperature. 3. All LVMCOS 1.2 V software macros support LVCMOS 3.3 V wide range as specified in the JDEC8-12 specification 4. Software default selection highlighted in gray. Table 2-124 * Minimum and Maximum DC Input and Output Levels for LVCMOS 1.2 Wide Range Applicable to Advanced I/O Banks 1.2 V Equivalent LVCMOS Software Wide Default Range Drive Drive Strength Min. Strength Option1 V 100 A 2 mA VIL Max. V VIH Min. V -0.3 0.35 * VCCI 0.65 * VCCI Max. V VOL VOH IOL IOH IOSH IOSL IIL IIH Max. V Min. V Max. Max. A A mA2 mA2 A A 3.6 0.25 * VCCI 0.75 * VCCI 100 100 20 26 10 10 Notes: 1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is 100 A. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. Currents are measured at 85C junction temperature. 3. All LVMCOS 1.2 V software macros support LVCMOS 3.3 V wide range as specified in the JDEC8-12 specification 4. Software default selection highlighted in gray. Table 2-125 * Minimum and Maximum DC Input and Output Levels for LVCMOS 1.2 V Wide Range Applicable to Standard Plus I/O Banks 1.2 V Equivalent LVCMOS Software Wide Default Range Drive Drive Strength Min. Strength Option1 V 100 A 2 mA VIL Max. V VIH Min. V Max. V VOL VOH IOL IOH IOSH IOSL IIL IIH Max. V Min. V Max. Max. A A mA2 mA2 A A -0.3 0.35 * VCCI 0.65 * VCCI 1.26 0.25 * VCCI 0.75 * VCCI 100 100 20 26 10 10 Notes: 1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is 100 A. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. Currents are measured at 85C junction temperature. 3. All LVMCOS 1.2 V software macros support LVCMOS 3.3 V wide range as specified in the JDEC8-12 specification 4. Software default selection highlighted in gray. 2- 80 R ev i sio n 1 3 ProASIC3L Low Power Flash FPGAs 3.3 V PCI, 3.3 V PCI-X Peripheral Component Interface for 3.3 V standard specifies support for 33 MHz and 66 MHz PCI Bus applications. Table 2-126 * Minimum and Maximum DC Input and Output Levels 3.3 V PCI/PCI-X VIL Min. V Drive Strength VIH Max. V Min. V Max. V Per PCI specification VOL VOH IOL IOH IOSL IOSH IIL IIH Max. V Min. V Max. mA1 Max. mA1 A2 A2 mA mA Per PCI curves 10 10 Notes: 1. Currents are measured at 100C junction temperature and maximum voltage. 2. Currents are measured at 85C junction temperature. AC loadings are defined per the PCI/PCI-X specifications for the database; Microsemi loadings for enable path characterization are described in Figure 2-12. R to VCCI for tDP (F) R to GND for tDP (R) R = 25 Test Point Datapath R to VCCI for tLZ / tZL / tZLS R to GND for tHZ / tZH / tZHS R=1k Test Point Enable Path 10 pF for tZH / tZHS / tZL / tZLS 10 pF for tHZ / tLZ Figure 2-12 * AC Loading AC loadings are defined per PCI/PCI-X specifications for the datapath; Microsemi loading for tristate is described in Table 2-127. Table 2-127 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) CLOAD (pF) 3.3 0.285 * VCCI for tDP(R) 0.615 * VCCI for tDP(F) 10 0 Note: *Measuring point = Vtrip. See Table 2-27 on page 2-26 for a complete table of trip points. Timing Characteristics 1.5 V DC Core Voltage Table 2-128 * 3.3 V PCI/PCI-X - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Pro I/O Banks Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.59 2.52 0.04 2.47 3.33 0.38 2.57 1.80 2.95 3.25 4.58 3.81 ns -1 0.50 2.15 0.03 2.10 2.84 0.33 2.19 1.53 2.51 2.77 3.90 3.24 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. R ev i si o n 1 3 2- 81 ProASIC3L DC and Switching Characteristics Table 2-129 * 3.3 V PCI/PCI-X - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Advanced I/O Banks Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.54 2.41 0.04 0.78 0.38 2.46 1.76 2.89 3.22 4.47 3.77 ns 0.54 -1 0.46 2.05 0.03 0.66 0.33 2.09 1.49 2.46 2.74 3.80 3.21 ns 0.46 Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-130 * 3.3 V PCI/PCI-X - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard Plus I/O Banks Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.54 2.08 0.04 0.77 0.38 2.12 1.53 2.51 2.90 4.13 3.55 ns 0.54 -1 0.46 1.77 0.03 0.65 0.33 1.80 1.31 2.14 2.47 3.51 3.02 ns 0.46 Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. 1.2 V DC Core Voltage Table 2-131 * 3.3 V PCI/PCI-X - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V Applicable to Pro I/O Banks Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.77 2.52 0.05 2.47 3.33 0.50 2.57 1.80 2.95 3.25 4.58 3.81 ns -1 0.66 2.15 0.04 2.10 2.84 0.43 2.19 1.53 2.51 2.77 3.90 3.24 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-132 * 3.3 V PCI/PCI-X - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V Applicable to Advanced I/O Banks Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.70 2.41 0.05 0.78 0.50 2.46 1.76 2.89 3.22 4.47 3.77 0.73 ns -1 0.60 2.05 0.04 0.66 0.43 2.09 1.49 2.46 2.74 3.80 3.21 0.62 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-133 * 3.3 V PCI/PCI-X - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V Applicable to Standard Plus I/O Banks Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.70 2.08 0.05 0.77 0.50 2.12 1.53 2.51 2.90 4.13 3.55 0.73 ns -1 0.60 1.77 0.04 0.65 0.43 1.80 1.31 2.14 2.47 3.51 3.02 0.62 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. 2- 82 R ev i sio n 1 3 ProASIC3L Low Power Flash FPGAs Voltage-Referenced I/O Characteristics 3.3 V GTL Gunning Transceiver Logic is a high-speed bus standard (JESD8-3). It provides a differential amplifier input buffer and an open-drain output buffer. The VCCI pin should be connected to 3.3 V. Table 2-134 * Minimum and Maximum DC Input and Output Levels 3.3 V GTL VIL Drive Strength Min. V 20 mA3 -0.3 Max. V VIH Min. V VOL VOH IOL IOH IOSL IOSH IIL IIH Max. V Max. V Min. V mA mA Max. mA1 Max. mA1 A2 A2 3.6 0.4 - 20 20 268 181 VREF - 0.05 VREF + 0.05 10 10 Notes: 1. Currents are measured at 100C junction temperature and maximum voltage. 2. Currents are measured at 85C junction temperature. 3. Output drive strength is below JEDEC specification. VTT GTL 25 Test Point 10 pF Figure 2-13 * AC Loading Table 2-135 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) VREF - 0.05 Input High (V) Measuring Point* (V) VREF (typ.) (V) VTT (typ.) (V) CLOAD (pF) VREF + 0.05 0.8 0.8 1.2 10 Note: *Measuring point = Vtrip. See Table 2-16 on page 2-12 for a complete table of trip points. R ev i si o n 1 3 2- 83 ProASIC3L DC and Switching Characteristics Timing Characteristics Table 2-136 * 3.3 V GTL - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V VREF = 0.8 V Applicable to Pro I/O Banks Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tZLS tZHS Units Std. 0.59 1.87 0.04 2.12 0.38 1.83 1.87 tLZ tHZ 3.85 3.88 ns -1 0.50 1.59 0.03 1.80 0.33 1.56 1.59 3.27 3.30 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-137 * 3.3 V GTL - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V VREF = 0.8 V Applicable to Pro I/Os Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.77 1.87 0.05 2.12 0.50 1.83 1.87 3.85 3.88 ns -1 0.66 1.59 0.04 1.80 0.43 1.56 1.59 3.27 3.30 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. 2- 84 R ev i sio n 1 3 ProASIC3L Low Power Flash FPGAs 2.5 V GTL Gunning Transceiver Logic is a high-speed bus standard (JESD8-3). It provides a differential amplifier input buffer and an open-drain output buffer. The VCCI pin should be connected to 2.5 V Table 2-138 * Minimum and Maximum DC Input and Output Levels 2.5 GTL VIL Drive Strength Min. V 20 mA3 -0.3 Max. V VIH Min. V VREF - 0.05 VREF + 0.05 VOL VOH IOL IOH IOSL IOSH IIL IIH Max. V Max. V Min. V mA mA Max. mA1 Max. mA1 A2 A2 2.7 0.4 - 20 20 169 124 10 10 Notes: 1. Currents are measured at 100C junction temperature and maximum voltage. 2. Currents are measured at 85C junction temperature. 3. Output drive strength is below JEDEC specification. VTT GTL 25 Test Point 10 pF Figure 2-14 * AC Loading Table 2-139 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) VREF - 0.05 Input High (V) Measuring Point* (V) VREF (typ.) (V) VTT (typ.) (V) CLOAD (pF) VREF + 0.05 0.8 0.8 1.2 10 Note: *Measuring point = Vtrip. See Table 2-16 on page 2-12 for a complete table of trip points. R ev i si o n 1 3 2- 85 ProASIC3L DC and Switching Characteristics Timing Characteristics Table 2-140 * 2.5 V GTL - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V VREF = 0.8 V Applicable to Pro I/O Banks Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tZLS tZHS Units Std. 0.59 1.92 0.04 2.05 0.38 1.95 1.92 tLZ tHZ 3.96 3.93 ns -1 0.50 1.63 0.03 1.75 0.33 1.66 1.63 3.37 3.34 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-141 * 2.5 V GTL - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V VREF = 0.8 V Applicable to Pro I/O Banks Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.77 1.92 0.05 2.05 0.50 1.95 1.92 3.96 3.93 ns -1 0.66 1.63 0.04 1.75 0.43 1.66 1.63 3.37 3.34 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. 2- 86 R ev i sio n 1 3 ProASIC3L Low Power Flash FPGAs 3.3 V GTL+ Gunning Transceiver Logic Plus is a high-speed bus standard (JESD8-3). It provides a differential amplifier input buffer and an open-drain output buffer. The VCCI pin should be connected to 3.3 V Table 2-142 * Minimum and Maximum DC Input and Output Levels 3.3 V GTL+ VIL Drive Strength Min. V 35 mA -0.3 VIH Max. V Min. V VREF - 0.1 VREF + 0.1 VOL VOH IOL IOH IOSL IOSH IIL IIH Max. V Max. V Min. V mA mA Max. mA1 Max. mA1 A2 A2 3.6 0.6 - 35 35 268 181 10 10 Notes: 1. Currents are measured at 100C junction temperature and maximum voltage. 2. Currents are measured at 85C junction temperature. VTT GTL+ 25 Test Point 10 pF Figure 2-15 * AC Loading Table 2-143 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) VREF - 0.1 Input High (V) Measuring Point* (V) VREF (typ.) (V) VTT (typ.) (V) CLOAD (pF) VREF + 0.1 1.0 1.0 1.5 10 Note: *Measuring point = Vtrip. See Table 2-16 on page 2-12 for a complete table of trip points. Timing Characteristics Table 2-144 * 3.3 V GTL+ - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V VREF = 1.0 V Applicable to Pro I/O Banks Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tZLS tZHS Units Std. 0.59 1.85 0.04 2.12 0.38 1.88 1.85 tLZ tHZ 3.90 3.86 ns -1 0.50 1.57 0.03 1.80 0.33 1.60 1.57 3.31 3.29 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-145 * 3.3 V GTL+ - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V VREF = 1.0 V Applicable to Pro I/O Banks Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.77 1.85 0.05 2.12 0.50 1.88 1.85 3.90 3.86 ns -1 0.66 1.57 0.04 1.80 0.43 1.60 1.57 3.31 3.29 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. R ev i si o n 1 3 2- 87 ProASIC3L DC and Switching Characteristics 2.5 V GTL+ Gunning Transceiver Logic Plus is a high-speed bus standard (JESD8-3). It provides a differential amplifier input buffer and an open-drain output buffer. The VCCI pin should be connected to 2.5 V. Table 2-146 * Minimum and Maximum DC Input and Output Levels 2.5 V GTL+ VIL Drive Strength Min. V 33 mA -0.3 Max. V VIH Min. V VREF - 0.1 VREF + 0.1 VOL VOH IOL IOH IOSL IOSH IIL Max. V Max. V Min. V mA mA Max. mA1 Max. mA1 A2 A2 2.7 0.6 - 169 124 33 33 10 Notes: 1. Currents are measured at 100C junction temperature and maximum voltage. 2. Currents are measured at 85C junction temperature. VTT GTL+ 25 Test Point 10 pF Figure 2-16 * AC Loading Table 2-147 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) VREF - 0.1 Input High (V) Measuring Point* (V) VREF (typ.) (V) VTT (typ.) (V) CLOAD (pF) VREF + 0.1 1.0 1.0 1.5 10 Note: *Measuring point = Vtrip. See Table 2-16 on page 2-12 for a complete table of trip points. 2- 88 R ev i sio n 1 3 IIH 10 ProASIC3L Low Power Flash FPGAs Timing Characteristics Table 2-148 * 2.5 V GTL+ - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V VREF = 1.0 V Applicable to Pro I/O Banks Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tZLS tZHS Units Std. 0.59 1.99 0.04 2.05 0.38 2.02 1.89 tLZ tHZ 4.03 3.90 ns -1 0.50 1.69 0.03 1.75 0.33 1.72 1.61 3.43 3.32 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-16 on page 2-12 for derating values. Table 2-149 * 2.5 V GTL+ - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V VREF = 1.0 V Applicable to Pro I/O Banks Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tZLS tZHS Units Std. 0.77 1.99 0.05 2.05 0.50 2.02 1.89 tLZ tHZ 4.03 3.90 ns -1 0.66 1.69 0.04 1.75 0.43 1.72 1.61 3.43 3.32 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-16 on page 2-12 for derating values. R ev i si o n 1 3 2- 89 ProASIC3L DC and Switching Characteristics HSTL Class I High-Speed Transceiver Logic is a general-purpose high-speed 1.5 V bus standard (EIA/JESD8-6). ProASIC3E devices support Class I. This provides a differential amplifier input buffer and a push-pull output buffer. Table 2-150 * Minimum and Maximum DC Input and Output Levels HSTL Class I VIL Drive Strength Min. V 8 mA -0.3 VIH Max. V Min. V VREF - 0.1 VREF + 0.1 VOL VOH IOL IOH IOSL IOSH IIL IIH Max. V Max. V Min. V mA mA Max. mA1 Max. mA1 A2 A2 1.575 0.4 VCCI - 0.4 32 39 8 8 10 Notes: 1. Currents are measured at 100C junction temperature and maximum voltage. 2. Currents are measured at 85C junction temperature. HSTL Class I VTT 50 Test Point 20 pF Figure 2-17 * AC Loading Table 2-151 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) VREF - 0.1 Input High (V) Measuring Point* (V) VREF (typ.) (V) VTT (typ.) (V) CLOAD (pF) VREF + 0.1 0.75 0.75 0.75 20 Note: *Measuring point = Vtrip. See Table 2-16 on page 2-12 for a complete table of trip points. 2- 90 R ev i sio n 1 3 10 ProASIC3L Low Power Flash FPGAs Timing Characteristics Table 2-152 * HSTL Class I - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V VREF = 0.75 V Applicable to Pro I/O Banks Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH Std. 0.59 2.86 0.04 2.50 0.38 2.91 -1 0.50 2.43 0.03 2.12 0.33 2.48 tLZ tHZ tZLS tZHS Units 2.83 4.93 4.84 ns 2.41 4.19 4.12 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-153 * HSTL Class I - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V VREF = 0.75 V Applicable to Pro I/O Banks Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.77 2.86 0.05 2.50 0.50 2.91 2.83 4.93 4.84 ns -1 0.66 2.43 0.04 2.12 0.43 2.48 2.41 4.19 4.12 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. R ev i si o n 1 3 2- 91 ProASIC3L DC and Switching Characteristics HSTL Class II High-Speed Transceiver Logic is a general-purpose high-speed 1.5 V bus standard (EIA/JESD8-6). ProASIC3E devices support Class II. This provides a differential amplifier input buffer and a push-pull output buffer. Table 2-154 * Minimum and Maximum DC Input and Output Levels HSTL Class II VIL Max. V VIH Min. V VOL VOH IOL IOH IOSL IOSH IIL IIH Min. V mA mA Max. mA1 Max. mA1 A2 A2 66 55 Drive Strength Min. V Max. V Max. V 15 mA3 -0.3 VREF - 0.1 VREF + 0.1 1.575 0.4 VCCI - 0.4 15 15 10 Notes: 1. Currents are measured at 100C junction temperature and maximum voltage. 2. Currents are measured at 85C junction temperature. 3. Output drive strength is below JEDEC specification. HSTL Class II VTT 25 Test Point 20 pF Figure 2-18 * AC Loading Table 2-155 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) VREF - 0.1 Input High (V) Measuring Point* (V) VREF (typ.) (V) VTT (typ.) (V) CLOAD (pF) VREF + 0.1 0.75 0.75 0.75 20 Note: *Measuring point = Vtrip. See Table 2-16 on page 2-12 for a complete table of trip points. 2- 92 R ev i sio n 1 3 10 ProASIC3L Low Power Flash FPGAs Timing Characteristics Table 2-156 * HSTL Class II - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V VREF = 0.75 V Applicable to Pro I/O Banks Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tZLS tZHS Units Std. 0.59 2.72 0.04 2.50 0.38 2.77 2.44 tLZ tHZ 4.78 4.45 ns -1 0.50 2.32 0.03 2.12 0.33 2.36 2.08 4.07 3.79 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-157 * HSTL Class II - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V VREF = 0.75 V Applicable to Pro I/O Banks Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.77 2.72 0.05 2.50 0.50 2.77 2.44 4.78 4.45 ns -1 0.66 2.32 0.04 2.12 0.43 2.36 2.08 4.07 3.79 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. R ev i si o n 1 3 2- 93 ProASIC3L DC and Switching Characteristics SSTL2 Class I Stub-Speed Terminated Logic for 2.5 V memory bus standard (JESD8-9). ProASIC3E devices support Class I. This provides a differential amplifier input buffer and a push-pull output buffer. Table 2-158 * Minimum and Maximum DC Input and Output Levels SSTL2 Class I VIL Max. V VIH Drive Strength Min. V Min. V 15 mA -0.3 VREF - 0.2 VREF + 0.2 VOL VOH IOL IOH IOSL IOSH IIL IIH Max. V Max. V Min. V Max. mA mA mA1 Max. mA1 A2 A2 2.7 0.54 87 10 10 VCCI - 0.62 15 15 83 Notes: 1. Currents are measured at 100C junction temperature and maximum voltage. 2. Currents are measured at 85C junction temperature. SSTL2 Class I VTT 50 Test Point 25 30 pF Figure 2-19 * AC Loading Table 2-159 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) VREF - 0.2 Input High (V) Measuring Point* (V) VREF (typ.) (V) VTT (typ.) (V) CLOAD (pF) VREF + 0.2 1.25 1.25 1.25 30 Note: *Measuring point = Vtrip. See Table 2-16 on page 2-12 for a complete table of trip points. 2- 94 R ev i sio n 1 3 ProASIC3L Low Power Flash FPGAs Timing Characteristics Table 2-160 * SSTL2 Class I - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V VREF = 1.25 V Applicable to Pro I/Os Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tZLS tZHS Units Std. 0.59 1.91 0.04 1.89 0.38 1.95 1.66 tLZ tHZ 1.95 1.66 ns -1 0.50 1.63 0.03 1.61 0.33 1.66 1.41 1.66 1.41 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-161 * SSTL2 Class I - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V VREF = 1.25 V Applicable to Pro I/O Banks Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.77 1.91 0.05 1.89 0.50 1.95 1.66 1.95 1.66 ns -1 0.66 1.63 0.04 1.61 0.43 1.66 1.41 1.66 1.41 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. R ev i si o n 1 3 2- 95 ProASIC3L DC and Switching Characteristics SSTL2 Class II Stub-Speed Terminated Logic for 2.5 V memory bus standard (JESD8-9). ProASIC3E devices support Class II. This provides a differential amplifier input buffer and a push-pull output buffer. Table 2-162 * Minimum and Maximum DC Input and Output Levels SSTL2 Class II VIL VIH Drive Strength Min. V Max. V Min. V 18 mA -0.3 VREF - 0.2 VREF + 0.2 VOL VOH IOL IOH IOSL IOSH IIL IIH Max. V Max. V Min. V mA mA Max. mA1 Max. mA1 A2 A2 2.7 0.35 VCCI - 0.43 18 18 169 124 10 10 Notes: 1. Currents are measured at 100C junction temperature and maximum voltage. 2. Currents are measured at 85C junction temperature. SSTL2 Class II VTT 25 Test Point 25 30 pF Figure 2-20 * AC Loading Table 2-163 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) VREF - 0.2 Input High (V) Measuring Point* (V) VREF (typ.) (V) VTT (typ.) (V) CLOAD (pF) VREF + 0.2 1.25 1.25 1.25 30 Note: *Measuring point = Vtrip. See Table 2-16 on page 2-12 for a complete table of trip points. Timing Characteristics Table 2-164 * SSTL2 Class II - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V VREF = 1.25 V Applicable to Pro I/O Banks Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.59 1.95 0.04 1.89 0.38 1.99 1.59 1.99 1.59 ns -1 0.50 1.66 0.03 1.61 0.33 1.69 1.36 1.69 1.36 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-165 * SSTL2 Class II - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V VREF = 1.25 V Applicable to Pro I/O Banks Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH Std. 0.77 1.95 0.05 1.89 0.50 1.99 -1 0.66 1.66 0.04 1.61 0.43 1.69 tLZ tHZ tZLS tZHS Units 1.59 1.99 1.59 ns 1.36 1.69 1.36 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. 2- 96 R ev i sio n 1 3 ProASIC3L Low Power Flash FPGAs SSTL3 Class I Stub-Speed Terminated Logic for 3.3 V memory bus standard (JESD8-8). ProASIC3E devices support Class I. This provides a differential amplifier input buffer and a push-pull output buffer. Table 2-166 * Minimum and Maximum DC Input and Output Levels SSTL3 Class I VIL VIH Drive Strength Min. V Max. V Min. V 14 mA -0.3 VREF - 0.2 VREF + 0.2 VOL VOH IOL IOH IOSL IOSH Max. V Max. V Min. V mA mA Max. mA1 Max. mA1 A2 A2 3.6 0.7 VCCI - 1.1 14 14 51 IIL IIH 54 10 10 Notes: 1. Currents are measured at 100C junction temperature and maximum voltage. 2. Currents are measured at 85C junction temperature. SSTL3 Class I VTT 50 Test Point 25 30 pF Figure 2-21 * AC Loading Table 2-167 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) VREF - 0.2 Input High (V) Measuring Point* (V) VREF (typ.) (V) VTT (typ.) (V) CLOAD (pF) VREF + 0.2 1.5 1.5 1.485 30 Note: *Measuring point = Vtrip. See Table 2-16 on page 2-12 for a complete table of trip points. Timing Characteristics Table 2-168 * SSTL3 Class I - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V VREF = 1.5 V Applicable to Pro I/O Banks Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH Std. 0.59 2.08 0.04 1.81 0.38 2.11 -1 0.50 1.77 0.03 1.54 0.33 1.80 tLZ tHZ tZLS tZHS Units 1.65 2.11 1.65 ns 1.41 1.80 1.41 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-169 * SSTL3 Class I - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V VREF = 1.5 V Applicable to Pro I/O Banks Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH Std. 0.77 2.08 0.05 1.81 0.50 2.11 -1 0.66 1.77 0.04 1.54 0.43 1.80 tLZ tHZ tZLS tZHS Units 1.65 2.11 1.65 ns 1.41 1.80 1.41 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. R ev i si o n 1 3 2- 97 ProASIC3L DC and Switching Characteristics SSTL3 Class II Stub-Speed Terminated Logic for 3.3 V memory bus standard (JESD8-8). ProASIC3E devices support Class II. This provides a differential amplifier input buffer and a push-pull output buffer. Table 2-170 * Minimum and Maximum DC Input and Output Levels SSTL3 Class II VIL VIH Drive Strength Min. V Max. V Min. V 21 mA -0.3 VREF - 0.2 VREF + 0.2 VOL VOH IOL IOH IOSL IOSH IIL IIH Max. V Max. V Min. V mA mA Max. mA1 Max. mA1 A2 A2 3.6 0.5 VCCI - 0.9 21 21 103 109 10 10 Notes: 1. Currents are measured at 100C junction temperature and maximum voltage. 2. Currents are measured at 85C junction temperature. SSTL3 Class II VTT 25 Test Point 25 30 pF Figure 2-22 * AC Loading Table 2-171 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) VREF - 0.2 Input High (V) Measuring Point* (V) VREF (typ.) (V) VTT (typ.) (V) CLOAD (pF) VREF + 0.2 1.5 1.5 1.485 30 Note: *Measuring point = Vtrip. See Table 2-16 on page 2-12 for a complete table of trip points. Timing Characteristics Table 2-172 * SSTL3 Class II - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V VREF = 1.5 V Applicable to Pro I/O Banks Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.59 1.86 0.04 1.81 0.38 1.89 1.50 1.89 1.50 ns -1 0.50 1.58 0.03 1.54 0.33 1.61 1.28 1.61 1.28 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-173 * SSTL3 Class II - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V VREF = 1.5 V Applicable to Pro I/O Banks Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH Std. 0.77 1.86 0.05 1.81 0.50 1.89 -1 0.66 1.58 0.04 1.54 0.43 1.61 tLZ tHZ tZLS tZHS Units 1.50 1.89 1.50 ns 1.28 1.61 1.28 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. 2- 98 R ev i sio n 1 3 ProASIC3L Low Power Flash FPGAs Differential I/O Characteristics Physical Implementation Configuration of the I/O modules as a differential pair is handled by Designer software when the user instantiates a differential I/O macro in the design. Differential I/Os can also be used in conjunction with the embedded Input Register (InReg), Output Register (OutReg), Enable Register (EnReg), and Double Data Rate (DDR). However, there is no support for bidirectional I/Os or tristates with the LVPECL standards. LVDS Low-Voltage Differential Signaling (ANSI/TIA/EIA-644) is a high-speed, differential I/O standard. It requires that one data bit be carried through two signal lines, so two pins are needed. It also requires external resistor termination. The full implementation of the LVDS transmitter and receiver is shown in an example in Figure 2-23. The building blocks of the LVDS transmitter-receiver are one transmitter macro, one receiver macro, three board resistors at the transmitter end, and one resistor at the receiver end. The values for the three driver resistors are different from those used in the LVPECL implementation because the output standard specifications are different. Along with LVDS I/O, ProASIC3 also supports Bus LVDS structure and Multipoint LVDS (M-LVDS) configuration (up to 40 nodes). Bourns Part Number: CAT16-LV4F12 OUTBUF_LVDS FPGA P 165 140 N 165 P Z0 = 50 Z0 = 50 FPGA + - 100 INBUF_LVDS N Figure 2-23 * LVDS Circuit Diagram and Board-Level Implementation R ev i si o n 1 3 2- 99 ProASIC3L DC and Switching Characteristics Table 2-174 * Minimum and Maximum DC Input and Output Levels DC Parameter Description Min. Typ. Max. Units 2.375 2.5 2.625 V VCCI Supply Voltage VOL Output Low Voltage 0.9 1.075 1.25 V VOH Output High Voltage 1.25 1.425 1.6 V Output Lower Current 0.65 0.91 1.16 mA IOH 1 Output High Current 0.65 0.91 1.16 mA VI Input Voltage IOL 1 2.925 V 2 Input High Leakage Current 10 A IIL 2 Input Low Leakage Current 10 A VODIFF Differential Output Voltage VOCM IIH 0 250 350 450 mV Output Common Mode Voltage 1.125 1.25 1.375 V VICM Input Common Mode Voltage 0.05 1.25 2.35 V VIDIFF Input Differential Voltage 100 350 mV Notes: 1. Currents are measured at 85C junction temperature. 2. IOL/IOH is defined by VODIFF/(Resistor Network). Table 2-175 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) 1.075 Input High (V) Measuring Point* (V) 1.325 Cross point Note: *Measuring point = Vtrip. See Table 2-27 on page 2-26 for a complete table of trip points. 2- 10 0 R ev isio n 1 3 ProASIC3L Low Power Flash FPGAs Timing Characteristics 1.5 V DC Core Voltage Table 2-176 * LVDS - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Pro I/O Banks Speed Grade tDOUT tDP tDIN tPY Units Std. 0.59 1.65 0.04 2.18 ns -1 0.50 1.40 0.03 1.85 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-177 * LVDS - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Advanced I/O Banks Speed Grade tDOUT tDP tDIN tPY Units Std. 0.54 1.65 0.04 1.44 ns -1 0.46 1.40 0.03 1.23 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. 1.2 V DC Core Voltage Table 2-178 * LVDS - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V Applicable to Pro I/O Banks Speed Grade tDOUT tDP tDIN tPY Units Std. 0.77 1.68 0.05 2.18 ns -1 0.66 1.43 0.04 1.85 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-179 * LVDS - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V Applicable to Advanced I/O Banks Speed Grade tDOUT tDP tDIN tPY Units Std. 0.70 1.65 0.05 1.44 ns -1 0.60 1.40 0.04 1.23 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. R ev i si o n 1 3 2- 101 ProASIC3L DC and Switching Characteristics B-LVDS/M-LVDS Bus LVDS (B-LVDS) and Multipoint LVDS (M-LVDS) specifications extend the existing LVDS standard to high-performance multipoint bus applications. Multidrop and multipoint bus configurations may contain any combination of drivers, receivers, and transceivers. Microsemi LVDS drivers provide the higher drive current required by B-LVDS and M-LVDS to accommodate the loading. The drivers require series terminations for better signal quality and to control voltage swing. Termination is also required at both ends of the bus since the driver can be located anywhere on the bus. These configurations can be implemented using the TRIBUF_LVDS and BIBUF_LVDS macros along with appropriate terminations. Multipoint designs using Microsemi LVDS macros can achieve up to 200 MHz with a maximum of 20 loads. A sample application is given in Figure 2-24. The input and output buffer delays are available in the LVDS section in Table 2-174 on page 2-100. Example: For a bus consisting of 20 equidistant loads, the following terminations provide the required differential voltage, in worst-case Industrial operating conditions, at the farthest receiver: RS = 60 and RT = 70 , given Z0 = 50 (2") and Zstub = 50 (~1.5"). Receiver Transceiver EN R + RS Zstub Z0 RT Z 0 D EN T - + RS Zstub Driver RS Zstub - Zstub RS Zstub EN Transceiver EN R - + RS Receiver + RS RS Zstub Zstub EN T - + RS Zstub RS RS ... Z0 Z0 Z0 Z0 Z0 Z0 Z0 Z0 Z0 Z0 Figure 2-24 * B-LVDS/M-LVDS Multipoint Application Using LVDS I/O Buffers 2- 10 2 BIBUF_LVDS - R ev isio n 1 3 RT ProASIC3L Low Power Flash FPGAs LVPECL Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It requires that one data bit be carried through two signal lines. Like LVDS, two pins are needed. It also requires external resistor termination. The full implementation of the LVDS transmitter and receiver is shown in an example in Figure 2-25. The building blocks of the LVPECL transmitter-receiver are one transmitter macro, one receiver macro, three board resistors at the transmitter end, and one resistor at the receiver end. The values for the three driver resistors are different from those used in the LVDS implementation because the output standard specifications are different. Bourns Part Number: CAT16-PC4F12 OUTBUF_LVPECL FPGA P 100 Z0 = 50 100 INBUF_LVPECL + - 100 187 W N FPGA P Z0 = 50 N Figure 2-25 * LVPECL Circuit Diagram and Board-Level Implementation Table 2-180 * Minimum and Maximum DC Input and Output Levels DC Parameter Description Min. Max. Min. 3.0 Max. Min. 3.3 Max. VCCI Supply Voltage VOL Output Low Voltage 0.96 1.27 1.06 1.43 1.30 1.57 V VOH Output High Voltage 1.8 2.11 1.92 2.28 2.13 2.41 V VIL, VIH Input Low, Input High Voltages 0 3.6 0 3.6 0 3.6 V VODIFF Differential Output Voltage 0.625 0.97 0.625 0.97 0.625 0.97 V VOCM Output Common-Mode Voltage 1.762 1.98 1.762 1.98 1.762 1.98 V VICM Input Common-Mode Voltage 1.01 2.57 1.01 2.57 1.01 2.57 V VIDIFF Input Differential Voltage 300 300 3.6 Units V 300 mV Table 2-181 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) 1.64 Input High (V) Measuring Point* (V) 1.94 Cross point Note: *Measuring point = Vtrip. See Table 2-27 on page 2-26 for a complete table of trip points. R ev i si o n 1 3 2- 103 ProASIC3L DC and Switching Characteristics Timing Characteristics 1.5 V DC Core Voltage Table 2-182 * LVPECL - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Pro I/O Banks Speed Grade tDOUT tDP tDIN tPY Units Std. 0.59 1.64 0.04 1.97 ns -1 0.50 1.40 0.03 1.67 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-183 * LVPECL - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Advanced I/O Banks Speed Grade tDOUT tDP tDIN tPY Units Std. 0.54 1.62 0.04 1.26 ns -1 0.46 1.38 0.03 1.08 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. 1.2 V DC Core Voltage Table 2-184 * LVPECL - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V Applicable to Pro I/O Banks Speed Grade tDOUT tDP tDIN tPY Units Std. 0.77 1.62 0.05 1.97 ns -1 0.66 1.37 0.04 1.67 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-185 * LVPECL - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V Applicable to Advanced I/O Banks Speed Grade tDOUT tDP tDIN tPY Units Std. 0.70 1.62 0.05 1.26 ns -1 0.60 1.38 0.04 1.08 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. 2- 10 4 R ev isio n 1 3 ProASIC3L Low Power Flash FPGAs I/O Register Specifications Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Preset INBUF Preset L Pad Out D DOUT Data_out E Y F Core Array G PRE D Q DFN1E1P1 TRIBUF CLKBUF CLK INBUF Enable PRE D Q C DFN1E1P1 INBUF Data E E EOUT B H I A J K INBUF INBUF D_Enable CLK CLKBUF Enable Data Input I/O Register with: Active High Enable Active High Preset Positive-Edge Triggered PRE D Q DFN1E1P1 E Data Output Register and Enable Output Register with: Active High Enable Active High Preset Postive-Edge Triggered Figure 2-26 * Timing Model of Registered I/O Buffers with Synchronous Enable and Asynchronous Preset R ev i si o n 1 3 2- 105 ProASIC3L DC and Switching Characteristics Table 2-186 * Parameter Definition and Measuring Nodes Parameter Name Parameter Definition Measuring Nodes (from, to)* tOCLKQ Clock-to-Q of the Output Data Register tOSUD Data Setup Time for the Output Data Register F, H tOHD Data Hold Time for the Output Data Register F, H tOSUE Enable Setup Time for the Output Data Register G, H tOHE Enable Hold Time for the Output Data Register G, H tOPRE2Q Asynchronous Preset-to-Q of the Output Data Register tOREMPRE Asynchronous Preset Removal Time for the Output Data Register L, H tORECPRE Asynchronous Preset Recovery Time for the Output Data Register L, H tOECLKQ Clock-to-Q of the Output Enable Register tOESUD Data Setup Time for the Output Enable Register J, H tOEHD Data Hold Time for the Output Enable Register J, H tOESUE Enable Setup Time for the Output Enable Register K, H tOEHE Enable Hold Time for the Output Enable Register K, H tOEPRE2Q Asynchronous Preset-to-Q of the Output Enable Register tOEREMPRE Asynchronous Preset Removal Time for the Output Enable Register I, H tOERECPRE Asynchronous Preset Recovery Time for the Output Enable Register I, H tICLKQ Clock-to-Q of the Input Data Register A, E tISUD Data Setup Time for the Input Data Register C, A tIHD Data Hold Time for the Input Data Register C, A tISUE Enable Setup Time for the Input Data Register B, A tIHE Enable Hold Time for the Input Data Register B, A tIPRE2Q Asynchronous Preset-to-Q of the Input Data Register D, E tIREMPRE Asynchronous Preset Removal Time for the Input Data Register D, A tIRECPRE Asynchronous Preset Recovery Time for the Input Data Register D, A Note: *See Figure 2-26 on page 2-105 for more information. 2- 10 6 R ev isio n 1 3 H, DOUT L, DOUT H, EOUT I, EOUT ProASIC3L Low Power Flash FPGAs Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Clear D CC Q DFN1E1C1 EE Data_out FF D Q DFN1E1C1 TRIBUF INBUF Data Core Array Pad Out DOUT Y GG INBUF Enable BB EOUT E E CLR CLR LL INBUF CLR CLKBUF CLK HH AA JJ DD KK Data Input I/O Register with Active High Enable Active High Clear Positive-Edge Triggered D Q DFN1E1C1 E INBUF CLKBUF CLK Enable INBUF D_Enable CLR Data Output Register and Enable Output Register with Active High Enable Active High Clear Positive-Edge Triggered Figure 2-27 * Timing Model of the Registered I/O Buffers with Synchronous Enable and Asynchronous Clear R ev i si o n 1 3 2- 107 ProASIC3L DC and Switching Characteristics Table 2-187 * Parameter Definition and Measuring Nodes Parameter Name Parameter Definition Measuring Nodes (from, to)* tOCLKQ Clock-to-Q of the Output Data Register tOSUD Data Setup Time for the Output Data Register FF, HH tOHD Data Hold Time for the Output Data Register FF, HH tOSUE Enable Setup Time for the Output Data Register GG, HH tOHE Enable Hold Time for the Output Data Register GG, HH tOCLR2Q Asynchronous Clear-to-Q of the Output Data Register tOREMCLR Asynchronous Clear Removal Time for the Output Data Register LL, HH tORECCLR Asynchronous Clear Recovery Time for the Output Data Register LL, HH tOECLKQ Clock-to-Q of the Output Enable Register tOESUD Data Setup Time for the Output Enable Register JJ, HH tOEHD Data Hold Time for the Output Enable Register JJ, HH tOESUE Enable Setup Time for the Output Enable Register KK, HH tOEHE Enable Hold Time for the Output Enable Register KK, HH tOECLR2Q Asynchronous Clear-to-Q of the Output Enable Register II, EOUT tOEREMCLR Asynchronous Clear Removal Time for the Output Enable Register II, HH tOERECCLR Asynchronous Clear Recovery Time for the Output Enable Register II, HH tICLKQ Clock-to-Q of the Input Data Register AA, EE tISUD Data Setup Time for the Input Data Register CC, AA tIHD Data Hold Time for the Input Data Register CC, AA tISUE Enable Setup Time for the Input Data Register BB, AA tIHE Enable Hold Time for the Input Data Register BB, AA tICLR2Q Asynchronous Clear-to-Q of the Input Data Register DD, EE tIREMCLR Asynchronous Clear Removal Time for the Input Data Register DD, AA tIRECCLR Asynchronous Clear Recovery Time for the Input Data Register DD, AA Note: *See Figure 2-27 on page 2-107 for more information. 2- 10 8 R ev isio n 1 3 HH, DOUT LL, DOUT HH, EOUT ProASIC3L Low Power Flash FPGAs Input Register tICKMPWH tICKMPWL CLK 50% 50% Enable 50% 1 50% 50% 50% tIHD tISUD Data 50% 50% 50% 0 tIWPRE 50% tIRECPRE tIREMPRE 50% 50% tIHE Preset tISUE 50% tIWCLR 50% Clear tIRECCLR 50% tIREMCLR 50% tIPRE2Q Out_1 50% 50% tICLR2Q 50% tICLKQ Figure 2-28 * Input Register Timing Diagram R ev i si o n 1 3 2- 109 ProASIC3L DC and Switching Characteristics Timing Characteristics 1.5 V DC Core Voltage Table 2-188 * Input Data Register Propagation Delays Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V Parameter Description -1 Std. Units tICLKQ Clock-to-Q of the Input Data Register 0.24 0.29 ns tISUD Data Setup Time for the Input Data Register 0.27 0.31 ns tIHD Data Hold Time for the Input Data Register 0.00 0.00 ns tISUE Enable Setup Time for the Input Data Register 0.38 0.45 ns tIHE Enable Hold Time for the Input Data Register 0.00 0.00 ns tICLR2Q Asynchronous Clear-to-Q of the Input Data Register 0.46 0.54 ns tIPRE2Q Asynchronous Preset-to-Q of the Input Data Register 0.46 0.54 ns tIREMCLR Asynchronous Clear Removal Time for the Input Data Register 0.00 0.00 ns tIRECCLR Asynchronous Clear Recovery Time for the Input Data Register 0.23 0.27 ns tIREMPRE Asynchronous Preset Removal Time for the Input Data Register 0.00 0.00 ns tIRECPRE Asynchronous Preset Recovery Time for the Input Data Register 0.23 0.27 ns tIWCLR Asynchronous Clear Minimum Pulse Width for the Input Data Register 0.19 0.22 ns tIWPRE Asynchronous Preset Minimum Pulse Width for the Input Data Register 0.19 0.22 ns tICKMPWH Clock Minimum Pulse Width High for the Input Data Register 0.31 0.36 ns tICKMPWL Clock Minimum Pulse Width Low for the Input Data Register 0.28 0.32 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. 1.2 V DC Core Voltage Table 2-189 * Input Data Register Propagation Delays Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V Parameter Description -1 Std. Units tICLKQ Clock-to-Q of the Input Data Register 0.32 0.37 ns tISUD Data Setup Time for the Input Data Register 0.35 0.41 ns tIHD Data Hold Time for the Input Data Register 0.00 0.00 ns tISUE Enable Setup Time for the Input Data Register 0.50 0.58 ns tIHE Enable Hold Time for the Input Data Register 0.00 0.00 ns tICLR2Q Asynchronous Clear-to-Q of the Input Data Register 0.60 0.71 ns tIPRE2Q Asynchronous Preset-to-Q of the Input Data Register 0.60 0.71 ns tIREMCLR Asynchronous Clear Removal Time for the Input Data Register 0.00 0.00 ns tIRECCLR Asynchronous Clear Recovery Time for the Input Data Register 0.30 0.35 ns tIREMPRE Asynchronous Preset Removal Time for the Input Data Register 0.00 0.00 ns tIRECPRE Asynchronous Preset Recovery Time for the Input Data Register 0.30 0.35 ns tIWCLR Asynchronous Clear Minimum Pulse Width for the Input Data Register 0.19 0.22 ns tIWPRE Asynchronous Preset Minimum Pulse Width for the Input Data Register 0.19 0.22 ns tICKMPWH Clock Minimum Pulse Width High for the Input Data Register 0.31 0.36 ns tICKMPWL Clock Minimum Pulse Width Low for the Input Data Register 0.28 0.32 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. 2- 11 0 R ev isio n 1 3 ProASIC3L Low Power Flash FPGAs Output Register tOCKMPWH tOCKMPWL CLK 50% 50% 50% 50% 50% 50% 50% tOSUD tOHD 1 Data_out Enable 50% 50% 0 50% tOWPRE tOHE Preset tOSUE tOREMPRE tORECPRE 50% 50% 50% tOWCLR 50% Clear tORECCLR 50% tOREMCLR 50% tOPRE2Q DOUT 50% 50% tOCLR2Q 50% tOCLKQ Figure 2-29 * Output Register Timing Diagram R ev i si o n 1 3 2- 111 ProASIC3L DC and Switching Characteristics Timing Characteristics 1.5 V DC Core Voltage Table 2-190 * Output Data Register Propagation Delays Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V Parameter Description -1 Std. Units tOCLKQ Clock-to-Q of the Output Data Register 0.60 0.71 ns tOSUD Data Setup Time for the Output Data Register 0.32 0.37 ns tOHD Data Hold Time for the Output Data Register 0.00 0.00 ns tOSUE Enable Setup Time for the Output Data Register 0.45 0.53 ns tOHE Enable Hold Time for the Output Data Register 0.00 0.00 ns tOCLR2Q Asynchronous Clear-to-Q of the Output Data Register 0.82 0.96 ns tOPRE2Q Asynchronous Preset-to-Q of the Output Data Register 0.82 0.96 ns tOREMCLR Asynchronous Clear Removal Time for the Output Data Register 0.00 0.00 ns tORECCLR Asynchronous Clear Recovery Time for the Output Data Register 0.23 0.27 ns tOREMPRE Asynchronous Preset Removal Time for the Output Data Register 0.00 0.00 ns tORECPRE Asynchronous Preset Recovery Time for the Output Data Register 0.23 0.27 ns tOWCLR Asynchronous Clear Minimum Pulse Width for the Output Data Register 0.19 0.22 ns tOWPRE Asynchronous Preset Minimum Pulse Width for the Output Data Register 0.19 0.22 ns tOCKMPWH Clock Minimum Pulse Width High for the Output Data Register 0.31 0.36 ns tOCKMPWL Clock Minimum Pulse Width Low for the Output Data Register 0.28 0.32 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. 1.2 V DC Core Voltage Table 2-191 * Output Data Register Propagation Delays Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V Parameter Description -1 Std. Units tOCLKQ Clock-to-Q of the Output Data Register 0.78 0.92 ns tOSUD Data Setup Time for the Output Data Register 0.42 0.49 ns tOHD Data Hold Time for the Output Data Register 0.00 0.00 ns tOSUE Enable Setup Time for the Output Data Register 0.58 0.69 ns tOHE Enable Hold Time for the Output Data Register 0.00 0.00 ns tOCLR2Q Asynchronous Clear-to-Q of the Output Data Register 1.07 1.26 ns tOPRE2Q Asynchronous Preset-to-Q of the Output Data Register 1.07 1.26 ns tOREMCLR Asynchronous Clear Removal Time for the Output Data Register 0.00 0.00 ns tORECCLR Asynchronous Clear Recovery Time for the Output Data Register 0.30 0.35 ns tOREMPRE Asynchronous Preset Removal Time for the Output Data Register 0.00 0.00 ns tORECPRE Asynchronous Preset Recovery Time for the Output Data Register 0.30 0.35 ns tOWCLR Asynchronous Clear Minimum Pulse Width for the Output Data Register 0.19 0.22 ns tOWPRE Asynchronous Preset Minimum Pulse Width for the Output Data Register 0.19 0.22 ns tOCKMPWH Clock Minimum Pulse Width High for the Output Data Register 0.31 0.36 ns tOCKMPWL Clock Minimum Pulse Width Low for the Output Data Register 0.28 0.32 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. 2- 11 2 R ev isio n 1 3 ProASIC3L Low Power Flash FPGAs Output Enable Register tOECKMPWH tOECKMPWL CLK 50% 50% 50% 50% 50% 50% 50% tOESUD tOEHD 1 D_Enable Enable Preset 50% 0 50% 50% tOESUEtOEHE tOEWPRE tOEREMPRE tOERECPRE 50% 50% 50% tOEWCLR 50% Clear tOEPRE2Q EOUT 50% 50% tOERECCLR 50% tOEREMCLR 50% tOECLR2Q 50% tOECLKQ Figure 2-30 * Output Enable Register Timing Diagram R ev i si o n 1 3 2- 113 ProASIC3L DC and Switching Characteristics Timing Characteristics 1.5 V DC Core Voltage Table 2-192 * Output Enable Register Propagation Delays Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V Parameter Description -1 Std. Units tOECLKQ Clock-to-Q of the Output Enable Register 0.45 0.53 ns tOESUD Data Setup Time for the Output Enable Register 0.32 0.37 ns tOEHD Data Hold Time for the Output Enable Register 0.00 0.00 ns tOESUE Enable Setup Time for the Output Enable Register 0.44 0.52 ns tOEHE Enable Hold Time for the Output Enable Register 0.00 0.00 ns tOECLR2Q Asynchronous Clear-to-Q of the Output Enable Register 0.68 0.80 ns tOEPRE2Q Asynchronous Preset-to-Q of the Output Enable Register 0.68 0.80 ns tOEREMCLR Asynchronous Clear Removal Time for the Output Enable Register 0.00 0.00 ns tOERECCLR Asynchronous Clear Recovery Time for the Output Enable Register 0.23 0.27 ns tOEREMPRE Asynchronous Preset Removal Time for the Output Enable Register 0.00 0.00 ns tOERECPRE Asynchronous Preset Recovery Time for the Output Enable Register 0.23 0.27 ns tOEWCLR Asynchronous Clear Minimum Pulse Width for the Output Enable Register 0.19 0.22 ns tOEWPRE Asynchronous Preset Minimum Pulse Width for the Output Enable Register 0.19 0.22 ns tOECKMPWH Clock Minimum Pulse Width High for the Output Enable Register 0.31 0.36 ns Clock Minimum Pulse Width Low for the Output Enable Register 0.28 0.32 ns tOECKMPWL Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. 1.2 V DC Core Voltage Table 2-193 * Output Enable Register Propagation Delays Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V Parameter Description -1 Std. Units tOECLKQ Clock-to-Q of the Output Enable Register 0.59 0.70 ns tOESUD Data Setup Time for the Output Enable Register 0.42 0.49 ns tOEHD Data Hold Time for the Output Enable Register 0.00 0.00 ns tOESUE Enable Setup Time for the Output Enable Register 0.58 0.68 ns tOEHE Enable Hold Time for the Output Enable Register 0.00 0.00 ns tOECLR2Q Asynchronous Clear-to-Q of the Output Enable Register 0.89 1.04 ns tOEPRE2Q Asynchronous Preset-to-Q of the Output Enable Register 0.89 1.04 ns tOEREMCLR Asynchronous Clear Removal Time for the Output Enable Register 0.00 0.00 ns tOERECCLR Asynchronous Clear Recovery Time for the Output Enable Register 0.30 0.35 ns tOEREMPRE Asynchronous Preset Removal Time for the Output Enable Register 0.00 0.00 ns tOERECPRE Asynchronous Preset Recovery Time for the Output Enable Register 0.30 0.35 ns tOEWCLR Asynchronous Clear Minimum Pulse Width for the Output Enable Register 0.19 0.22 ns tOEWPRE Asynchronous Preset Minimum Pulse Width for the Output Enable Register 0.19 0.22 ns tOECKMPWH Clock Minimum Pulse Width High for the Output Enable Register 0.31 0.36 ns Clock Minimum Pulse Width Low for the Output Enable Register 0.28 0.32 ns tOECKMPWL Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. 2- 11 4 R ev isio n 1 3 ProASIC3L Low Power Flash FPGAs DDR Module Specifications Input DDR Module Input DDR INBUF Data A D Out_QF (to core) E Out_QR (to core) FF1 B CLK CLKBUF FF2 C CLR INBUF DDR_IN Figure 2-31 * Input DDR Timing Model Table 2-194 * Parameter Definitions Parameter Name Parameter Definition Measuring Nodes (from, to) tDDRICLKQ1 Clock-to-Out Out_QR B, D tDDRICLKQ2 Clock-to-Out Out_QF B, E tDDRISUD Data Setup Time of DDR input A, B tDDRIHD Data Hold Time of DDR input A, B tDDRICLR2Q1 Clear-to-Out Out_QR C, D tDDRICLR2Q2 Clear-to-Out Out_QF C, E tDDRIREMCLR Clear Removal C, B tDDRIRECCLR Clear Recovery C, B R ev i si o n 1 3 2- 115 ProASIC3L DC and Switching Characteristics CLK tDDRISUD Data 1 2 3 4 5 6 tDDRIHD 7 8 9 tDDRIRECCLR CLR tDDRIREMCLR tDDRICLKQ1 tDDRICLR2Q1 Out_QF 2 6 4 tDDRICLKQ2 tDDRICLR2Q2 Out_QR 3 7 5 Figure 2-32 * Input DDR Timing Diagram Timing Characteristics 1.5 V DC Core Voltage Table 2-195 * Input DDR Propagation Delays Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V Parameter Description -1 Std. Units tDDRICLKQ1 Clock-to-Out Out_QR for Input DDR 0.28 0.33 ns tDDRICLKQ2 Clock-to-Out Out_QF for Input DDR 0.40 0.47 ns tDDRISUD1 Data Setup for Input DDR (fall) 0.29 0.34 ns tDDRISUD2 Data Setup for Input DDR (rise) 0.25 0.29 ns tDDRIHD1 Data Hold for Input DDR (fall) 0.00 0.00 ns tDDRIHD2 Data Hold for Input DDR (rise) 0.00 0.00 ns tDDRICLR2Q1 Asynchronous Clear-to-Out Out_QR for Input DDR 0.47 0.55 ns tDDRICLR2Q2 Asynchronous Clear-to-Out Out_QF for Input DDR 0.58 0.68 ns tDDRIREMCLR Asynchronous Clear Removal Time for Input DDR 0.00 0.00 ns tDDRIRECCLR Asynchronous Clear Recovery Time for Input DDR 0.23 0.27 ns tDDRIWCLR Asynchronous Clear Minimum Pulse Width for Input DDR 0.18 0.22 ns tDDRICKMPWH Clock Minimum Pulse Width High for Input DDR 0.31 0.36 ns tDDRICKMPWL Clock Minimum Pulse Width Low for Input DDR 0.28 0.32 ns FDDRIMAX Maximum Frequency for Input DDR 250.00 250.00 MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. 2- 11 6 R ev isio n 1 3 ProASIC3L Low Power Flash FPGAs 1.2 V DC Core Voltage Table 2-196 * Input DDR Propagation Delays Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V Parameter Description -1 Std. Units tDDRICLKQ1 Clock-to-Out Out_QR for Input DDR 0.43 0.37 ns tDDRICLKQ2 Clock-to-Out Out_QF for Input DDR 0.61 0.52 ns tDDRISUD1 Data Setup for Input DDR (fall) 0.44 0.38 ns tDDRISUD2 Data Setup for Input DDR (rise) 0.39 0.33 ns tDDRIHD1 Data Hold for Input DDR (fall) 0.00 0.00 ns tDDRIHD2 Data Hold for Input DDR (rise) 0.00 0.00 ns tDDRICLR2Q1 Asynchronous Clear-to-Out Out_QR for Input DDR 0.73 0.62 ns tDDRICLR2Q2 Asynchronous Clear-to-Out Out_QF for Input DDR 0.89 0.76 ns tDDRIREMCLR Asynchronous Clear Removal Time for Input DDR 0.00 0.00 ns tDDRIRECCLR Asynchronous Clear Recovery Time for Input DDR 0.35 0.30 ns tDDRIWCLR Asynchronous Clear Minimum Pulse Width for Input DDR 0.22 0.19 ns tDDRICKMPWH Clock Minimum Pulse Width High for Input DDR 0.36 0.31 ns tDDRICKMPWL Clock Minimum Pulse Width Low for Input DDR 0.32 0.28 ns FDDRIMAX Maximum Frequency for Input DDR 160.00 160.00 MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. R ev i si o n 1 3 2- 117 ProASIC3L DC and Switching Characteristics Output DDR Module Output DDR A Data_F (from core) X FF1 B CLK CLKBUF E X C X D Data_R (from core) Out 0 X 1 X OUTBUF FF2 B X CLR INBUF C X DDR_OUT Figure 2-33 * Output DDR Timing Model Table 2-197 * Parameter Definitions Parameter Name 2- 11 8 Parameter Definition Measuring Nodes (from, to) tDDROCLKQ Clock-to-Out B, E tDDROCLR2Q Asynchronous Clear-to-Out C, E tDDROREMCLR Clear Removal C, B tDDRORECCLR Clear Recovery C, B tDDROSUD1 Data Setup Data_F A, B tDDROSUD2 Data Setup Data_R D, B tDDROHD1 Data Hold Data_F A, B tDDROHD2 Data Hold Data_R D, B R ev isio n 1 3 ProASIC3L Low Power Flash FPGAs CLK tDDROSUD2 tDDROHD2 1 Data_F 2 5 tDDROHD1 tDDROREMCLR Data_R 6 4 3 7 8 9 10 11 tDDRORECCLR tDDROREMCLR CLR tDDROCLR2Q tDDROCLKQ Out 2 7 8 3 9 4 10 Figure 2-34 * Output DDR Timing Diagram Timing Characteristics 1.5 V DC Core Voltage Table 2-198 * Output DDR Propagation Delays Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V Parameter Description -1 Std. Units tDDROCLKQ Clock-to-Out of DDR for Output DDR 0.72 0.84 ns tDDRISUD1 Data_F Data Setup for Output DDR 0.39 0.45 ns tDDROSUD2 Data_R Data Setup for Output DDR 0.39 0.45 ns tDDROHD1 Data_F Data Hold for Output DDR 0.00 0.00 ns tDDROHD2 Data_R Data Hold for Output DDR 0.00 0.00 ns tDDROCLR2Q Asynchronous Clear-to-Out for Output DDR 0.82 0.96 ns tDDROREMCLR Asynchronous Clear Removal Time for Output DDR 0.00 0.00 ns tDDRORECCLR Asynchronous Clear Recovery Time for Output DDR 0.23 0.27 ns tDDROWCLR1 Asynchronous Clear Minimum Pulse Width for Output DDR 0.19 0.22 ns tDDROCKMPWH Clock Minimum Pulse Width High for the Output DDR 0.31 0.36 ns tDDROCKMPWL Clock Minimum Pulse Width Low for the Output DDR 0.28 0.32 ns FDDOMAX Maximum Frequency for the Output DDR 250.00 250.00 MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. R ev i si o n 1 3 2- 119 ProASIC3L DC and Switching Characteristics 1.2 V DC Core Voltage Table 2-199 * Output DDR Propagation Delays Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V Parameter Description -1 Std. Units tDDROCLKQ Clock-to-Out of DDR for Output DDR 1.10 0.94 ns tDDRISUD1 Data_F Data Setup for Output DDR 0.59 0.50 ns tDDROSUD2 Data_R Data Setup for Output DDR 0.59 0.50 ns tDDROHD1 Data_F Data Hold for Output DDR 0.00 0.00 ns tDDROHD2 Data_R Data Hold for Output DDR 0.00 0.00 ns tDDROCLR2Q Asynchronous Clear-to-Out for Output DDR 1.26 1.07 ns tDDROREMCLR Asynchronous Clear Removal Time for Output DDR 0.00 0.00 ns tDDRORECCLR Asynchronous Clear Recovery Time for Output DDR 0.35 0.30 ns tDDROWCLR1 Asynchronous Clear Minimum Pulse Width for Output DDR 0.22 0.19 ns tDDROCKMPWH Clock Minimum Pulse Width High for the Output DDR 0.36 0.31 ns tDDROCKMPWL Clock Minimum Pulse Width Low for the Output DDR 0.32 0.28 ns FDDOMAX Maximum Frequency for the Output DDR 160.00 160.00 MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. 2- 12 0 R ev isio n 1 3 ProASIC3L Low Power Flash FPGAs VersaTile Characteristics VersaTile Specifications as a Combinatorial Module The ProASIC3 library offers all combinations of LUT-3 combinatorial functions. In this section, timing characteristics are presented for a sample of the library. For more details, refer to the IGLOO,(R) Fusion, and ProASIC3 Macro Library Guide. A A B A OR2 Y AND2 A Y B B B XOR2 A B C Y A A B C NOR2 B A A Y INV NAND3 A MAJ3 B Y NAND2 XOR3 Y Y 0 MUX2 B Y Y 1 C S Figure 2-35 * Sample of Combinatorial Cells R ev i si o n 1 3 2- 121 ProASIC3L DC and Switching Characteristics tPD A NAND2 or Any Combinatorial Logic B Y tPD = MAX(tPD(RR), tPD(RF), tPD(FF), tPD(FR)) where edges are applicable for the particular combinatorial cell VCC 50% 50% A, B, C GND VCC 50% 50% OUT GND VCC tPD tPD (FF) (RR) OUT tPD (FR) 50% tPD GND (RF) Figure 2-36 * Timing Model and Waveforms 2- 12 2 R ev isio n 1 3 50% ProASIC3L Low Power Flash FPGAs Timing Characteristics 1.5 V DC Core Voltage Table 2-200 * Combinatorial Cell Propagation Delays Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V Combinatorial Cell Equation Parameter -1 Std. Units Y =!A tPD 0.41 0.48 ns Y=A*B tPD 0.48 0.57 ns NAND2 Y =!(A * B) tPD 0.48 0.57 ns OR2 Y=A+B tPD 0.50 0.58 ns NOR2 Y =!(A + B) tPD 0.50 0.58 ns XOR2 Y = A B tPD 0.75 0.88 ns MAJ3 Y = MAJ(A, B, C) tPD 0.71 0.84 ns XOR3 Y = A B C tPD 0.89 1.05 ns MUX2 Y = A !S + B S tPD 0.52 0.61 ns AND3 Y=A*B*C tPD 0.57 0.67 ns INV AND2 Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. 1.2 V DC Core Voltage Table 2-201 * Combinatorial Cell Propagation Delays Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V Combinatorial Cell Equation Parameter -1 Std. Units Y = !A tPD 0.54 0.63 ns Y=A*B tPD 0.63 0.74 ns Y = !(A * B) tPD 0.63 0.74 ns Y=A+B tPD 0.65 0.76 ns NOR2 Y = !(A + B) tPD 0.65 0.76 ns XOR2 Y = A B tPD 0.98 1.16 ns MAJ3 Y = MAJ(A , B, C) tPD 0.93 1.09 ns XOR3 Y = A B C tPD 1.17 1.37 ns MUX2 Y = A !S + B S tPD 0.68 0.79 ns AND3 Y=A*B*C tPD 0.75 0.88 ns INV AND2 NAND2 OR2 Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. R ev i si o n 1 3 2- 123 ProASIC3L DC and Switching Characteristics VersaTile Specifications as a Sequential Module The ProASIC3 library offers a wide variety of sequential cells, including flip-flops and latches. Each has a data input and optional enable, clear, or preset. In this section, timing characteristics are presented for a representative sample from the library. For more details, refer to the IGLOO, Fusion, and ProASIC3 Macro Library Guide. Data D Q Data Out En DFN1 Out D Q DFN1E1 CLK CLK PRE Data Out Q D Data D En DFN1C1 Q Out DFI1E1P1 CLK CLK CLR Figure 2-37 * Sample of Sequential Cells tCKMPWH tCKMPWL CLK 50% 50% tSUD 50% Data EN PRE 50% tRECPRE tREMPRE 50% 50% tRECCLR tWCLR 50% CLR tPRE2Q 50% Out 50% tCLR2Q 50% 50% tCLKQ Figure 2-38 * Timing Model and Waveforms 2- 12 4 50% 50% 0 tWPRE tSUE 50% 50% tHD 50% tHE 50% 50% R ev isio n 1 3 tREMCLR 50% ProASIC3L Low Power Flash FPGAs Timing Characteristics 1.5 V DC Core Voltage Table 2-202 * Register Delays Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V Parameter Description -1 Std. Units tCLKQ Clock-to-Q of the Core Register 0.56 0.66 ns tSUD Data Setup Time for the Core Register 0.44 0.51 ns tHD Data Hold Time for the Core Register 0.00 0.00 ns tSUE Enable Setup Time for the Core Register 0.46 0.55 ns tHE Enable Hold Time for the Core Register 0.00 0.00 ns tCLR2Q Asynchronous Clear-to-Q of the Core Register 0.41 0.48 ns tPRE2Q Asynchronous Preset-to-Q of the Core Register 0.41 0.48 ns tREMCLR Asynchronous Clear Removal Time for the Core Register 0.00 0.00 ns tRECCLR Asynchronous Clear Recovery Time for the Core Register 0.23 0.27 ns tREMPRE Asynchronous Preset Removal Time for the Core Register 0.00 0.00 ns tRECPRE Asynchronous Preset Recovery Time for the Core Register 0.23 0.27 ns tWCLR Asynchronous Clear Minimum Pulse Width for the Core Register 0.30 0.34 ns tWPRE Asynchronous Preset Minimum Pulse Width for the Core Register 0.30 0.34 ns tCKMPWH Clock Minimum Pulse Width High for the Core Register 0.56 0.64 ns tCKMPWL Clock Minimum Pulse Width Low for the Core Register 0.56 0.64 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. R ev i si o n 1 3 2- 125 ProASIC3L DC and Switching Characteristics 1.2 V DC Core Voltage Table 2-203 * Register Delays Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V Parameter Description -1 Std. Units tCLKQ Clock-to-Q of the Core Register 0.73 0.86 ns tSUD Data Setup Time for the Core Register 0.57 0.67 ns tHD Data Hold Time for the Core Register 0.00 0.00 ns tSUE Enable Setup Time for the Core Register 0.61 0.71 ns tHE Enable Hold Time for the Core Register 0.00 0.00 ns tCLR2Q Asynchronous Clear-to-Q of the Core Register 0.53 0.63 ns tPRE2Q Asynchronous Preset-to-Q of the Core Register 0.53 0.63 ns tREMCLR Asynchronous Clear Removal Time for the Core Register 0.00 0.00 ns tRECCLR Asynchronous Clear Recovery Time for the Core Register 0.30 0.35 ns tREMPRE Asynchronous Preset Removal Time for the Core Register 0.00 0.00 ns tRECPRE Asynchronous Preset Recovery Time for the Core Register 0.30 0.35 ns tWCLR Asynchronous Clear Minimum Pulse Width for the Core Register 0.30 0.34 ns tWPRE Asynchronous Preset Minimum Pulse Width for the Core Register 0.30 0.34 ns tCKMPWH Clock Minimum Pulse Width High for the Core Register 0.56 0.64 ns tCKMPWL Clock Minimum Pulse Width Low for the Core Register 0.56 0.64 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. 2- 12 6 R ev isio n 1 3 ProASIC3L Low Power Flash FPGAs Global Resource Characteristics A3P250L Clock Tree Topology Clock delays are device-specific. Figure 2-39 is an example of a global tree used for clock routing. The global tree presented in Figure 2-39 is driven by a CCC located on the west side of the A3P250L device. It is used to drive all D-flip-flops in the device. Central Global Rib VersaTile Rows CCC Global Spine Figure 2-39 * Example of Global Tree Use in an A3P250L Device for Clock Routing R ev i si o n 1 3 2- 127 ProASIC3L DC and Switching Characteristics Global Tree Timing Characteristics Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not include I/O input buffer clock delays, as these are I/O standard-dependent, and the clock may be driven and conditioned internally by the CCC module. For more details on clock conditioning capabilities, refer to the "Clock Conditioning Circuits" section on page 2-132. Table 2-204 to Table 2-210 on page 2-131 present minimum and maximum global clock delays within each device. Minimum and maximum delays are measured with minimum and maximum loading. Timing Characteristics Table 2-204 * A3P250L Global Resource - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, VCC = 1.425 V -1 Parameter Description Std. Min.1 Max.2 Min.1 Max.2 Units tRCKL Input Low Delay for Global Clock 0.82 1.06 0.96 1.25 ns tRCKH Input High Delay for Global Clock 0.80 1.09 0.94 1.28 ns tRCKMPWH Minimum Pulse Width High for Global Clock 0.75 0.88 ns tRCKMPWL Minimum Pulse Width Low for Global Clock 0.85 1.00 ns tRCKSW Maximum Skew for Global Clock 0.29 0.34 ns Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-205 * A3P250L Global Resource - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, VCC = 1.14 V -1 Std. Description Min.1 Max.2 Min.1 tRCKL Input Low Delay for Global Clock 1.40 1.68 1.64 1.97 ns tRCKH Input High Delay for Global Clock 1.38 1.71 1.62 2.01 ns tRCKMPWH Minimum Pulse Width High for Global Clock 1.05 1.24 ns tRCKMPWL Minimum Pulse Width Low for Global Clock 1.23 1.44 ns tRCKSW Maximum Skew for Global Clock Parameter 0.33 Max.2 Units 0.39 ns Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. 2- 12 8 R ev isio n 1 3 ProASIC3L Low Power Flash FPGAs Table 2-206 * A3P600L Global Resource - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, VCC = 1.425 V -1 Parameter Description Std. Min.1 Max.2 Min.1 Max.2 Units tRCKL Input Low Delay for Global Clock 0.90 1.14 1.06 1.34 ns tRCKH Input High Delay for Global Clock 0.89 1.17 1.04 1.38 ns tRCKMPWH Minimum Pulse Width High for Global Clock 0.75 0.88 ns tRCKMPWL Minimum Pulse Width Low for Global Clock 0.85 1.00 ns tRCKSW Maximum Skew for Global Clock 0.28 0.33 ns Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-207 * A3P600L Global Resource - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, VCC = 1.14 V -1 Std. Description Min.1 Max.2 Min.1 tRCKL Input Low Delay for Global Clock 1.48 1.76 1.74 2.07 ns tRCKH Input High Delay for Global Clock 1.47 1.80 1.72 2.11 ns tRCKMPWH Minimum Pulse Width High for Global Clock 1.05 1.24 ns tRCKMPWL Minimum Pulse Width Low for Global Clock 1.23 1.44 ns tRCKSW Maximum Skew for Global Clock Parameter 0.33 Max.2 Units 0.39 ns Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. R ev i si o n 1 3 2- 129 ProASIC3L DC and Switching Characteristics Table 2-208 * A3P1000L Global Resource - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, VCC = 1.425 V -1 Parameter 1 Std. 2 1 Max.2 Units Description Min. Max. Min. tRCKL Input Low Delay for Global Clock 1.02 1.26 1.20 1.48 ns tRCKH Input High Delay for Global Clock 1.01 1.29 1.18 1.52 ns tRCKMPWH Minimum Pulse Width High for Global Clock 0.75 0.88 ns tRCKMPWL Minimum Pulse Width Low for Global Clock 0.85 1.00 ns tRCKSW Maximum Skew for Global Clock 0.28 0.33 ns Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-209 * A3P1000L Global Resource - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, VCC = 1.14 V -1 Std. Description Min.1 Max.2 Min.1 tRCKL Input Low Delay for Global Clock 1.61 1.89 1.89 2.22 ns tRCKH Input High Delay for Global Clock 1.60 1.92 1.88 2.26 ns tRCKMPWH Minimum Pulse Width High for Global Clock 1.05 1.24 ns tRCKMPWL Minimum Pulse Width Low for Global Clock 1.23 1.44 ns tRCKSW Maximum Skew for Global Clock Parameter 0.33 Max.2 Units 0.39 ns Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. 2- 13 0 R ev isio n 1 3 ProASIC3L Low Power Flash FPGAs Table 2-210 * A3PE3000L Global Resource - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, VCC = 1.425 V -1 Parameter 1 Std. 2 1 Max.2 Units Description Min. Max. Min. tRCKL Input Low Delay for Global Clock 1.53 1.75 1.79 2.06 ns tRCKH Input High Delay for Global Clock 1.51 1.77 1.78 2.08 ns tRCKMPWH Minimum Pulse Width High for Global Clock 0.75 0.88 ns tRCKMPWL Minimum Pulse Width Low for Global Clock 0.85 1.00 ns tRCKSW Maximum Skew for Global Clock 0.26 0.30 ns Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-211 * A3PE3000L Global Resource - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, VCC = 1.14 V -1 Std. Description Min.1 Max.2 Min.1 tRCKL Input Low Delay for Global Clock 1.52 1.94 1.78 2.28 ns tRCKH Input High Delay for Global Clock 1.49 1.96 1.76 2.30 ns tRCKMPWH Minimum Pulse Width High for Global Clock 1.05 1.24 ns tRCKMPWL Minimum Pulse Width Low for Global Clock 1.23 1.44 ns tRCKSW Maximum Skew for Global Clock Parameter 0.47 Max.2 Units 0.55 ns Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. R ev i si o n 1 3 2- 131 ProASIC3L DC and Switching Characteristics Clock Conditioning Circuits CCC Electrical Specifications Timing Characteristics Table 2-212 * ProASIC3L CCC/PLL Specification CCC/PLL Operating at 1.2 V Parameter Min. Clock Conditioning Circuitry Input Frequency fIN_CCC 1.5 Clock Conditioning Circuitry Output Frequency fOUT_CCC Delay Increments in Programmable Delay Blocks Typ. 0.75 1, 2 Units 250 MHz 250 MHz 3 270 Number of Programmable Values in Each Programmable Delay Block Serial Clock (SCLK) for Dynamic Max. 32 PLL4 Input Cycle-to-Cycle Jitter (peak magnitude) CCC Output Peak-to-Peak Period Jitter FCCC_OUT ps 100 MHz 1 ns Max Peak-to-Peak Period Jitter 1 Global Network Used External FB Used 3 Global Networks Used 0.75 MHz to 24 MHz 0.50% 0.75% 0.70% 24 MHz to 100 MHz 1.00% 1.50% 1.20% 100 MHz to 250 MHz 2.50% 3.75% 2.75% Acquisition Time Tracking LockControl = 0 300 s LockControl = 1 6.0 ms LockControl = 0 2 ns LockControl = 1 1 ns 48.5 51.5 % 1.2 15.65 ns 0.025 15.65 ns Jitter5 Output Duty Cycle Delay Range in Block: Programmable Delay 1 1, 2 Delay Range in Block: Programmable Delay 2 Delay Range in Block: Fixed Delay 1, 2 1, 2 3.1 ns Notes: 1. This delay is a function of voltage and temperature. See Table 2-6 on page 2-7 for deratings. 2. TJ = 25C, VCC = 1.2 V 3. When the CCC/PLL core is generated by Microsemi core generator software, not all delay values of the specified delay increments are available. Refer to the Libero SoC Online Help for more information. 4. Maximum value obtained for a -1 speed grade device in worst-case commercial conditions. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. 5. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to PLL input clock edge. Tracking jitter does not measure the variation in PLL output period, which is covered by the period jitter parameter. 2- 13 2 R ev isio n 1 3 ProASIC3L Low Power Flash FPGAs Table 2-213 * ProASIC3L CCC/PLL Specification CCC/PLL Operating at 1.5 V Parameter Min. Clock Conditioning Circuitry Input Frequency fIN_CCC 1.5 Clock Conditioning Circuitry Output Frequency fOUT_CCC Delay Increments in Programmable Delay Blocks Serial Clock (SCLK) for Dynamic PLL Typ. 0.75 1, 2 Max. Units 350 MHz 350 MHz 3 160 4 ps 110 Number of Programmable Values in Each Programmable Delay Block 32 Input Period Jitter 1.5 CCC Output Peak-to-Peak Period Jitter FCCC_OUT ns Max Peak-to-Peak Period Jitter 1 Global Network Used 3 Global Networks Used 0.75 MHz to 24 MHz 0.50% 0.70% 24 MHz to 100 MHz 1.00% 1.20% 100 MHz to 250 MHz 1.75% 2.00 250 MHz to 350 MHz 2.50% 5.60% Acquisition Time Tracking LockControl = 0 300 s LockControl = 1 6.0 ms LockControl = 0 1.6 ns LockControl = 1 0.8 ns 48.5 51.5 % 0.6 5.56 ns 0.025 5.56 ns Jitter5 Output Duty Cycle Delay Range in Block: Programmable Delay 1 1, 2 Delay Range in Block: Programmable Delay 2 Delay Range in Block: Fixed Delay 1, 2 1, 2 2.2 ns Notes: 1. This delay is a function of voltage and temperature. See Table 2-6 on page 2-7 for deratings. 2. TJ = 25C, VCC = 1.5 V 3. When the CCC/PLL core is generated by Microsemi core generator software, not all delay values of the specified delay increments are available. Refer to the Libero SoC Online Help for more information. 4. Maximum value obtained for a -1 speed grade device in worst-case commercial conditions. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. 5. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to PLL input clock edge. Tracking jitter does not measure the variation in PLL output period, which is covered by the period jitter parameter. Output Signal Tperiod_max Tperiod_min Note: Peak-to-peak jitter measurements are defined by Tpeak-to-peak = Tperiod_max - Tperiod_min. Figure 2-40 * Peak-to-Peak Jitter Definition R ev i si o n 1 3 2- 133 ProASIC3L DC and Switching Characteristics Embedded SRAM and FIFO Characteristics SRAM RAM512X18 RAM4K9 ADDRA11 ADDRA10 DOUTA8 DOUTA7 RADDR8 RADDR7 RD17 RD16 ADDRA0 DINA8 DINA7 DOUTA0 RADDR0 RD0 RW1 RW0 DINA0 WIDTHA1 WIDTHA0 PIPEA WMODEA BLKA WENA CLKA PIPE REN RCLK ADDRB11 ADDRB10 DOUTB8 DOUTB7 ADDRB0 DOUTB0 DINB8 DINB7 WADDR8 WADDR7 WADDR0 WD17 WD16 WD0 DINB0 WW1 WW0 WIDTHB1 WIDTHB0 PIPEB WMODEB BLKB WENB CLKB WEN WCLK RESET RESET Figure 2-41 * RAM Models 2- 13 4 R ev isio n 1 3 ProASIC3L Low Power Flash FPGAs Timing Waveforms tCYC tCKH tCKL CLK tAS tAH A1 A0 [R|W]ADD A2 tBKS tBKH BLK tENS tENH WEN tCKQ1 DOUT|RD Dn D0 D1 D2 tDOH1 Figure 2-42 * RAM Read for Pass-Through Output. Applicable to Both RAM4K9 and RAM512x18. tCYC tCKH tCKL CLK t AS tAH A0 [R|W]ADD A1 A2 tBKS tBKH BLK tENH tENS WEN tCKQ2 DOUT|RD Dn D0 D1 tDOH2 Figure 2-43 * RAM Read for Pipelined Output. Applicable to both RAM4K9 and RAM512x18. R ev i si o n 1 3 2- 135 ProASIC3L DC and Switching Characteristics tCYC tCKH tCKL CLK tAS tAH A0 [R|W]ADD A1 A2 tBKS tBKH BLK tENS tENH WEN tDS DI0 DIN|WD tDH DI1 Dn DOUT|RD D2 Figure 2-44 * RAM Write, Output Retained. Applicable to both RAM4K9 and RAM512x18. tCYC tCKH tCKL CLK tAS tAH A0 ADDR A1 A2 tBKS tBKH BLK tENS WEN tDS DI0 DIN DOUT (pass-through) DOUT (pipelined) tDH DI1 Dn DI2 DI0 DI1 DI0 Dn Figure 2-45 * RAM Write, Output as Write Data (WMODE = 1). Applicable to RAM4K9 Only. 2- 13 6 R ev isio n 1 3 DI1 ProASIC3L Low Power Flash FPGAs tCYC tCKH tCKL CLK RESET tRSTBQ DOUT|RD Dm Dn Figure 2-46 * RAM Reset. Applicable to Both RAM4K9 and RAM512x18. R ev i si o n 1 3 2- 137 ProASIC3L DC and Switching Characteristics Timing Characteristics Table 2-214 * RAM4K9 - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V Parameter Description -1 Std. Units tAS Address setup time 0.25 0.30 ns tAH Address hold time 0.00 0.00 ns tENS REN, WEN setup time 0.15 0.17 ns tENH REN, WEN hold time 0.10 0.12 ns tBKS BLK setup time 0.24 0.28 ns tBKH BLK hold time 0.02 0.02 ns tDS Input data (DIN) setup time 0.19 0.22 ns tDH Input data (DIN) hold time 0.00 0.00 ns tCKQ1 Clock High to new data valid on DOUT (output retained, WMODE = 0) 1.82 2.14 ns Clock High to new data valid on DOUT (flow-through, WMODE = 1) 2.40 2.83 ns Clock High to new data valid on DOUT (pipelined) tCKQ2 0.91 1.07 ns 1 Address collision clk-to-clk delay for reliable write after write on same address - 0.24 0.29 applicable to closing edge ns tC2CRWH1 Address collision clk-to-clk delay for reliable read access after write on same 0.20 0.24 address - applicable to opening edge ns tC2CWRH1 Address collision clk-to-clk delay for reliable write access after read on same 0.25 0.30 address - applicable to opening edge ns tRSTBQ RESET Low to data out Low on DOUT (flow-through) 0.94 1.11 ns RESET Low to data out Low on DOUT (pipelined) 0.94 1.11 ns tREMRSTB RESET removal 0.29 0.34 ns tRECRSTB RESET recovery 1.53 1.80 ns tMPWRSTB RESET minimum pulse width 0.55 0.64 ns tCYC Clock cycle time 5.10 5.87 ns FMAX Maximum frequency 196 tC2CWWL 170 MHz Notes: 1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for FlashBased cSoCs and FPGAs. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. 2- 13 8 R ev isio n 1 3 ProASIC3L Low Power Flash FPGAs Table 2-215 * RAM4K9 - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V Parameter Description -1 Std. Units tAS Address setup time 0.33 0.39 ns tAH Address hold time 0.00 0.00 ns tENS REN, WEN setup time 0.19 0.22 ns tENH REN, WEN hold time 0.13 0.15 ns tBKS BLK setup time 0.31 0.36 ns tBKH BLK hold time 0.02 0.03 ns tDS Input data (DIN) setup time 0.24 0.29 ns tDH Input data (DIN) hold time 0.00 0.00 ns tCKQ1 Clock High to new data valid on DOUT (output retained, WMODE = 0) 2.38 2.80 ns Clock High to new data valid on DOUT (flow-through, WMODE = 1) 3.14 3.69 ns Clock High to new data valid on DOUT (pipelined) tCKQ2 1.19 1.40 ns 1 Address collision clk-to-clk delay for reliable write after write on same address - 0.25 0.30 applicable to closing edge ns tC2CRWH1 Address collision clk-to-clk delay for reliable read access after write on same 0.27 0.32 address - applicable to opening edge ns tC2CWRH1 Address collision clk-to-clk delay for reliable write access after read on same 0.37 0.44 address - applicable to opening edge ns tRSTBQ RESET Low to data out Low on DOUT (flow-through) 1.23 1.45 ns RESET Low to data out Low on DOUT (pipelined) 1.23 1.45 ns tREMRSTB RESET removal 0.38 0.45 ns tRECRSTB RESET recovery 2.00 2.35 ns tMPWRSTB RESET minimum pulse width 0.63 0.72 ns tCYC Clock cycle time 5.75 6.61 ns FMAX Maximum frequency 174 tC2CWWL 151 MHz Notes: 1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for FlashBased cSoCs and FPGAs. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. R ev i si o n 1 3 2- 139 ProASIC3L DC and Switching Characteristics Table 2-216 * RAM512X18 - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V Parameter Description -1 Std. Units tAS Address setup time 0.25 0.30 ns tAH Address hold time 0.00 0.00 ns tENS REN, WEN setup time 0.09 0.11 ns tENH REN, WEN hold time 0.06 0.07 ns tDS Input data (WD) setup time 0.19 0.22 ns tDH Input data (WD) hold time 0.00 0.00 ns tCKQ1 Clock High to new data valid on DO (output retained, WMODE = 0) 2.20 2.59 ns Clock High to new data valid on DO (pipelined) 0.91 1.07 ns 1 Address collision clk-to-clk delay for reliable read access after write on same 0.18 0.21 address - applicable to opening edge ns tC2CWRH1 Address collision clk-to-clk delay for reliable write access after read on same 0.21 0.25 address - applicable to opening edge ns tRSTBQ RESET Low to data out Low on RD (flow through) 0.94 1.11 ns RESET Low to data out Low on RD (pipelined) 0.94 1.11 ns tREMRSTB RESET removal 0.29 0.34 ns tRECRSTB RESET recovery 1.53 1.80 ns tMPWRSTB RESET minimum pulse width 0.55 0.64 ns tCYC Clock cycle time 5.10 5.87 ns FMAX Maximum frequency 196 tCKQ2 tC2CRWH 170 MHz Notes: 1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for FlashBased cSoCs and FPGAs. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. 2- 14 0 R ev isio n 1 3 ProASIC3L Low Power Flash FPGAs Table 2-217 * RAM512X18 - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V Parameter Description -1 Std. Units tAS Address setup time 0.33 0.39 ns tAH Address hold time 0.00 0.00 ns tENS REN, WEN setup time 0.12 0.14 ns tENH REN, WEN hold time 0.08 0.09 ns tDS Input data (WD) setup time 0.24 0.29 ns tDH Input data (WD) hold time 0.00 0.00 ns tCKQ1 Clock High to new data valid on RD (output retained, WMODE = 0) 2.88 3.39 ns Clock High to new data valid on RD (pipelined) 1.19 1.40 ns 1 Address collision clk-to-clk delay for reliable read access after write on same 0.25 0.29 address - applicable to opening edge ns tC2CWRH1 Address collision clk-to-clk delay for reliable write access after read on same 0.31 0.36 address - applicable to opening edge ns tRSTBQ RESET Low to data out Low on RD (flow-through) 1.23 1.45 ns RESET Low to data out Low on RD (pipelined) 1.23 1.45 ns tREMRSTB RESET removal 0.38 0.45 ns tRECRSTB RESET recovery 2.00 2.35 ns tMPWRSTB RESET minimum pulse width 0.63 0.72 ns tCYC Clock cycle time 5.75 6.61 ns FMAX Maximum frequency 174 tCKQ2 tC2CRWH 151 MHz Notes: 1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for FlashBased cSoCs and FPGAs. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values R ev i si o n 1 3 2- 141 ProASIC3L DC and Switching Characteristics FIFO FIFO4K18 RW2 RW1 RW0 WW2 WW1 WW0 ESTOP FSTOP RD17 RD16 RD0 FULL AFULL EMPTY AEMPTY AEVAL11 AEVAL10 AEVAL0 AFVAL11 AFVAL10 AFVAL0 REN RBLK RCLK WD17 WD16 WD0 WEN WBLK WCLK RPIPE RESET Figure 2-47 * FIFO Model 2- 14 2 R ev isio n 1 3 ProASIC3L Low Power Flash FPGAs Timing Waveforms tCYC RCLK tENH tENS REN tBKH tBKS RBLK tCKQ1 RD (flow-through) Dn D0 D1 D2 D0 D1 tCKQ2 RD (pipelined) Dn Figure 2-48 * FIFO Read tCYC WCLK tENS tENH WEN WBLK tBKS tBKH tDS WD DI0 tDH DI1 Figure 2-49 * FIFO Write R ev i si o n 1 3 2- 143 ProASIC3L DC and Switching Characteristics RCLK/ WCLK tMPWRSTB tRSTCK RESET tRSTFG EMPTY tRSTAF AEMPTY tRSTFG FULL tRSTAF AFULL WA/RA (Address Counter) MATCH (A0) Figure 2-50 * FIFO Reset tCYC RCLK tRCKEF EMPTY tCKAF AEMPTY WA/RA (Address Counter) NO MATCH NO MATCH Figure 2-51 * FIFO EMPTY Flag and AEMPTY Flag Assertion 2- 14 4 R ev isio n 1 3 Dist = AEF_TH MATCH (EMPTY) ProASIC3L Low Power Flash FPGAs tCYC WCLK tWCKFF FULL tCKAF AFULL WA/RA NO MATCH (Address Counter) NO MATCH Dist = AFF_TH MATCH (FULL) Figure 2-52 * FIFO FULL Flag and AFULL Flag Assertion WCLK WA/RA MATCH (Address Counter) (EMPTY) RCLK NO MATCH 1st Rising Edge After 1st Write NO MATCH NO MATCH NO MATCH Dist = AEF_TH + 1 2nd Rising Edge After 1st Write tRCKEF EMPTY tCKAF AEMPTY Figure 2-53 * FIFO EMPTY Flag and AEMPTY Flag Deassertion RCLK WA/RA (Address Counter) WCLK MATCH (FULL) NO MATCH 1st Rising Edge After 1st Read NO MATCH NO MATCH NO MATCH Dist = AFF_TH - 1 1st Rising Edge After 2nd Read tWCKF FULL tCKAF AFULL Figure 2-54 * FIFO FULL Flag and AFULL Flag Deassertion R ev i si o n 1 3 2- 145 ProASIC3L DC and Switching Characteristics Timing Characteristics Table 2-218 * FIFO - Applies to 1.5 V DC Core Voltage Worst Commercial-Case Conditions: TJ = 70C, VCC = 1.425 V Parameter Description -1 Std. Units tENS REN, WEN Setup Time 1.40 1.65 ns tENH REN, WEN Hold Time 0.02 0.02 ns tBKS BLK Setup Time 0.40 0.47 ns tBKH BLK Hold Time 0.00 0.00 ns tDS Input Data (WD) Setup Time 0.19 0.22 ns tDH Input Data (WD) Hold Time 0.00 0.00 ns tCKQ1 Clock High to New Data Valid on RD (flow-through) 2.40 2.83 ns tCKQ2 Clock High to New Data Valid on RD (pipelined) 0.91 1.07 ns tRCKEF RCLK High to Empty Flag Valid 1.75 2.06 ns tWCKFF WCLK High to Full Flag Valid 1.66 1.96 ns tCKAF Clock High to Almost Empty/Full Flag Valid 6.31 7.42 ns tRSTFG RESET Low to Empty/Full Flag Valid 1.73 2.03 ns tRSTAF RESET Low to Almost Empty/Full Flag Valid 6.25 7.35 ns tRSTBQ RESET Low to Data Out Low on RD (flow-through) 0.94 1.11 ns RESET Low to Data Out Low on RD (pipelined) 0.94 1.11 ns tREMRSTB RESET Removal 0.29 0.34 ns tRECRSTB RESET Recovery 1.53 1.80 ns tMPWRSTB RESET Minimum Pulse Width 0.55 0.64 ns tCYC Clock Cycle Time 5.10 5.87 ns FMAX Maximum Frequency for FIFO 196 170 MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. 2- 14 6 R ev isio n 1 3 ProASIC3L Low Power Flash FPGAs Table 2-219 * FIFO - Applies to 1.2 V DC Core Voltage Worst Commercial-Case Conditions: TJ = 70C, VCC = 1.14 V Parameter Description -1 Std. Units tENS REN, WEN Setup Time 1.84 2.16 ns tENH REN, WEN Hold Time 0.02 0.03 ns tBKS BLK Setup Time 0.40 0.47 ns tBKH BLK Hold Time 0.00 0.00 ns tDS Input Data (WD) Setup Time 0.24 0.29 ns tDH Input Data (WD) Hold Time 0.00 0.00 ns tCKQ1 Clock High to New Data Valid on RD (flow-through) 3.14 3.69 ns tCKQ2 Clock High to New Data Valid on RD (pipelined) 1.19 1.40 ns tRCKEF RCLK High to Empty Flag Valid 2.29 2.69 ns tWCKFF WCLK High to Full Flag Valid 2.18 2.56 ns tCKAF Clock High to Almost Empty/Full Flag Valid 8.25 9.70 ns tRSTFG RESET Low to Empty/Full Flag Valid 2.26 2.65 ns tRSTAF RESET Low to Almost Empty/Full Flag Valid 8.17 9.60 ns tRSTBQ RESET Low to Data Out Low on RD (flow-through) 1.23 1.45 ns RESET Low to Data Out Low on RD (pipelined) 1.23 1.45 ns tREMRSTB RESET Removal 0.38 0.45 ns tRECRSTB RESET Recovery 2.00 2.35 ns tMPWRSTB RESET Minimum Pulse Width 0.63 0.72 ns tCYC Clock Cycle Time 5.75 6.61 ns FMAX Maximum Frequency for FIFO 174 151 MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. R ev i si o n 1 3 2- 147 ProASIC3L DC and Switching Characteristics Embedded FlashROM Characteristics tSU CLK tSU tHOLD Address tSU tHOLD A0 tHOLD A1 tCKQ2 tCKQ2 D0 Data tCKQ2 D0 D1 Figure 2-55 * Timing Diagram Timing Characteristics Table 2-220 * Embedded FlashROM Access Time - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V Parameter Description -1 Std. Units tSU Address Setup Time 0.54 0.64 ns tHOLD Address Hold Time 0.00 0.00 ns tCK2Q Clock to Out 16.55 19.46 ns FMAX Maximum Clock Frequency 15 15 MHz Table 2-221 * Embedded FlashROM Access Time- Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V Parameter 2- 14 8 Description -1 Std. Units tSU Address Setup Time 0.71 0.83 ns tHOLD Address Hold Time 0.00 0.00 ns tCK2Q Clock to Out 21.64 25.44 ns FMAX Maximum Clock Frequency 15 15 MHz R ev isio n 1 3 ProASIC3L Low Power Flash FPGAs JTAG 1532 Characteristics JTAG timing delays do not include JTAG I/Os. To obtain complete JTAG timing, add I/O buffer delays to the corresponding standard selected; refer to the I/O timing characteristics in the "User I/O Characteristics" section on page 2-18 for more details. Timing Characteristics Table 2-222 * JTAG 1532 - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V Parameter Description -1 Std. Units tDISU Test Data Input Setup Time 0.57 0.67 ns tDIHD Test Data Input Hold Time 1.13 1.33 ns tTMSSU Test Mode Select Setup Time 0.57 0.67 ns tTMDHD Test Mode Select Hold Time 1.13 1.33 ns tTCK2Q Clock to Q (data out) 5.67 6.67 ns tRSTB2Q Reset to Q (data out) 22.67 26.67 ns FTCKMAX TCK Maximum Frequency 24.00 21.00 MHz tTRSTREM ResetB Removal Time 0.00 0.00 ns tTRSTREC ResetB Recovery Time 0.23 0.27 ns tTRSTMPW ResetB Minimum Pulse TBD TBD ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-223 * JTAG 1532 - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V Parameter Description -1 Std. Units tDISU Test Data Input Setup Time 0.75 0.88 ns tDIHD Test Data Input Hold Time 1.50 1.76 ns tTMSSU Test Mode Select Setup Time 0.75 0.88 ns tTMDHD Test Mode Select Hold Time 1.50 1.76 ns tTCK2Q Clock to Q (data out) 6.00 7.06 ns tRSTB2Q Reset to Q (data out) 25.00 29.41 ns FTCKMAX TCK Maximum Frequency 20.00 17.00 MHz tTRSTREM ResetB Removal Time 0.45 0.53 ns tTRSTREC ResetB Recovery Time 0.00 0.00 ns tTRSTMPW ResetB Minimum Pulse TBD TBD ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. R ev i si o n 1 3 2- 149 3 - Pin Descriptions and Packaging Supply Pins GND Ground Ground supply voltage to the core, I/O outputs, and I/O logic. GNDQ Ground (quiet) Quiet ground supply voltage to input buffers of I/O banks. Within the package, the GNDQ plane is decoupled from the simultaneous switching noise originated from the output buffer ground domain. This minimizes the noise transfer within the package and improves input signal integrity. GNDQ must always be connected to GND on the board. VCC Core Supply Voltage Supply voltage to the FPGA core, nominally 1.2 V or 1.5 V. VCC is required for powering the JTAG state machine in addition to VJTAG. Even when a device is in bypass mode in a JTAG chain of interconnected devices, both VCC and VJTAG must remain powered to allow JTAG signals to pass through the device. VCC can be switched dynamically from 1.2 V to 1.5 V or vice versa. This allows in-system programming (ISP) when VCC is at 1.5 V and the benefit of low power operation when VCC is at 1.2 V. VCCIBx I/O Supply Voltage Supply voltage to the bank's I/O output buffers and I/O logic. Bx is the I/O bank number. There are up to eight I/O banks on ProASIC3L low power flash devices plus a dedicated VJTAG bank. Each bank can have a separate VCCI connection. All I/Os in a bank will run off the same VCCIBx supply. VCCI can be 1.2 V, 1.5 V, 1.8 V, 2.5 V, or 3.3 V, nominal voltage. Unused I/O banks should have their corresponding VCCI pins tied to GND. VMVx I/O Supply Voltage (quiet) Quiet supply voltage to the input buffers of each I/O bank. x is the bank number. Within the package, the VMV plane biases the input stage of the I/Os in the I/O banks. This minimizes the noise transfer within the package and improves input signal integrity. Each bank must have at least one VMV connection, and no VMV should be left unconnected. All I/Os in a bank run off the same VMVx supply. VMV is used to provide a quiet supply voltage to the input buffers of each I/O bank. VMVx can be 1.2 V, 1.5 V, 1.8 V, 2.5 V, or 3.3 V, nominal voltage. Unused I/O banks should have their corresponding VMV pins tied to GND. VMV and VCCI should be at the same voltage within a given I/O bank. Used VMV pins must be connected to the corresponding VCCI pins of the same bank (i.e., VMV0 to VCCIB0, VMV1 to VCCIB1, etc.). VCCPLA/B/C/D/E/F PLL Supply Voltage Supply voltage to analog PLL, nominally 1.5 V or 1.2 V for ProASIC3 devices When the PLLs are not used, the Designer place-and-route tool automatically disables the unused PLLs to lower power consumption. The user should tie unused VCCPLx and VCOMPLx pins to ground. Microsemi recommends tying VCCPLx to VCC and using proper filtering circuits to decouple VCC noise from the PLLs. Refer to the PLL Power Supply Decoupling section of the "Clock Conditioning Circuits in IGLOO and ProASIC3 Devices" chapter of the ProASIC3L FPGA Fabric User's Guide for a complete board solution for the PLL analog power supply and ground. There is one VCCPLF pin on ProASIC3L devices. VCOMPLA/B/C/D/E/F PLL Ground Ground to analog PLL power supplies. When the PLLs are not used, the Designer place-and-route tool automatically disables the unused PLLs to lower power consumption. The user should tie unused VCCPLx and VCOMPLx pins to ground. There is one VCOMPLF pin on ProASIC3L devices. R ev i si o n 1 3 3 -1 Pin Descriptions and Packaging VJTAG JTAG Supply Voltage ProASIC3L devices have a separate bank for the dedicated JTAG pins. The JTAG pins can be run at any voltage from 1.5 V to 3.3 V (nominal). Isolating the JTAG power supply in a separate I/O bank gives greater flexibility in supply selection and simplifies power supply and PCB design. If the JTAG interface is neither used nor planned for use, the VJTAG pin together with the TRST pin could be tied to GND. It should be noted that VCC is required to be powered for JTAG operation; VJTAG alone is insufficient. If a device is in a JTAG chain of interconnected boards, the board containing the device can be powered down, provided both VJTAG and VCC to the part remain powered; otherwise, JTAG signals will not be able to transition the device, even in bypass mode. Microsemi recommends that VPUMP and VJTAG power supplies be kept separate with independent filtering capacitors rather than supplying them from a common rail. VPUMP Programming Supply Voltage ProASIC3Ldevices support single-voltage ISP of the configuration flash and FlashROM. For programming, VPUMP should be 3.3 V nominal. During normal device operation, VPUMP can be left floating or can be tied (pulled up) to any voltage between 0 V and the VPUMP maximum. Programming power supply voltage (VPUMP) range is listed in the datasheet. When the VPUMP pin is tied to ground, it will shut off the charge pump circuitry, resulting in no sources of oscillation from the charge pump circuitry. For proper programming, 0.01 F and 0.33 F capacitors (both rated at 16 V) are to be connected in parallel across VPUMP and GND, and positioned as close to the FPGA pins as possible. Microsemi recommends that VPUMP and VJTAG power supplies be kept separate with independent filtering capacitors rather than supplying them from a common rail. User Pins I/O User Input/Output The I/O pin functions as an input, output, tristate, or bidirectional buffer. Input and output signal levels are compatible with the I/O standard selected. During programming, I/Os become tristated and weakly pulled up to VCCI. With VCCI, VMV, and VCC supplies continuously powered up, when the device transitions from programming to operating mode, the I/Os are instantly configured to the desired user configuration. Unused I/Os are configured as follows: GL * Output buffer is disabled (with tristate value of high impedance) * Input buffer is disabled (with tristate value of high impedance) * Weak pull-up is programmed Globals GL I/Os have access to certain clock conditioning circuitry (and the PLL) and/or have direct access to the global network (spines). Additionally, the global I/Os can be used as regular I/Os, since they have identical capabilities. Unused GL pins are configured as inputs with pull-up resistors. See more detailed descriptions of global I/O connectivity in the "Clock Conditioning Circuits in IGLOO and ProASIC3 Devices" chapter of the ProASIC3L FPGA Fabric User's Guide. All inputs labeled GC/GF are direct inputs into the quadrant clocks. For example, if GAA0 is used for an input, GAA1 and GAA2 are no longer available for input to the quadrant globals. All inputs labeled GC/GF are direct inputs into the chip-level globals, and the rest are connected to the quadrant globals. The inputs to the global network are multiplexed, and only one input can be used as a global input. Refer to the "I/O Structures in IGLOO and ProASIC3 Devices" chapter of the ProASIC3L FPGA Fabric User's Guide for an explanation of the naming of global pins. FF Flash*Freeze Mode Activation Pin Flash*Freeze mode is available on ProASIC3L devices. The FF pin is a dedicated input pin used to enter and exit Flash*Freeze mode. The FF pin is active low, has the same characteristics as a single-ended I/O, and must meet the maximum rise and fall times. When Flash*Freeze mode is not used in the design, the FF pin is available as a regular I/O. 3- 2 R ev isio n 1 3 ProASIC3L Low Power Flash FPGAs When Flash*Freeze mode is used, the FF pin must not be left floating, to avoid accidentally entering Flash*Freeze mode. While in Flash*Freeze mode, the Flash*Freeze pin should be constantly asserted. The Flash*Freeze pin can be used with any single-ended I/O standard supported by the I/O bank in which the pin is located, and input signal levels compatible with the I/O standard selected. The FF pin should be treated as a sensitive asynchronous signal. When defining pin placement and board layout, simultaneously switching outputs (SSOs) and their effects on sensitive asynchronous pins must be considered. Unused FF or I/O pins are tristated with weak pull-up. This default configuration applies to both Flash*Freeze mode and normal operation mode. No user intervention is required. Table 3-1 shows the Flash*Freeze pin location on the available packages ProASIC3L devices. The Flash*Freeze pin location is independent of device (except for the PQ208 package), allowing migration to larger or smaller devices while maintaining the same pin location on the board. Refer to the "Flash*Freeze Technology and Low Power Modes" chapter of the ProASIC3L FPGA Fabric User's Guide for more information on I/O states during Flash*Freeze mode. Table 3-1 * Flash*Freeze Pin Location ProASIC3L Package Flash*Freeze Pin VQ100 27 FG144 L3 FG256 T3 FG324 R5 FG484 W6 FG896 AH4 PQ208 56 55 55 58 PQ208-A3P250 PQ208-A3P600L PQ208-A3P1000L PQ208-A3P3000L R ev i si o n 1 3 3 -3 Pin Descriptions and Packaging JTAG Pins ProASIC3L devices have a separate bank for the dedicated JTAG pins. The JTAG pins can be run at any voltage from 1.5 V to 3.3 V (nominal). VCC must also be powered for the JTAG state machine to operate, even if the device is in bypass mode; VJTAG alone is insufficient. Both VJTAG and VCC to the part must be supplied to allow JTAG signals to transition the device. Isolating the JTAG power supply in a separate I/O bank gives greater flexibility in supply selection and simplifies power supply and PCB design. If the JTAG interface is neither used nor planned for use, the VJTAG pin together with the TRST pin could be tied to GND. TCK Test Clock Test clock input for JTAG boundary scan, ISP, and UJTAG. The TCK pin does not have an internal pull-up/-down resistor. If JTAG is not used, Microsemi recommends tying off TCK to GND through a resistor placed close to the FPGA pin. This prevents JTAG operation in case TMS enters an undesired state. Note that to operate at all VJTAG voltages, 500 to 1 k will satisfy the requirements. Refer to Table 3-2 for more information. Table 3-2 * Recommended Tie-Off Values for the TCK and TRST Pins VJTAG Tie-Off Resistance VJTAG at 3.3 V 200 to 1 k VJTAG at 2.5 V 200 to 1 k VJTAG at 1.8 V 500 to 1 k VJTAG at 1.5 V 500 to 1 k Notes: 1. Equivalent parallel resistance if more than one device is on the JTAG chain 2. The TCK pin can be pulled up/down. 3. The TRST pin is pulled down. TDI Test Data Input Serial input for JTAG boundary scan, ISP, and UJTAG usage. There is an internal weak pull-up resistor on the TDI pin. TDO Test Data Output Serial output for JTAG boundary scan, ISP, and UJTAG usage. TMS Test Mode Select The TMS pin controls the use of the IEEE 1532 boundary scan pins (TCK, TDI, TDO, TRST). There is an internal weak pull-up resistor on the TMS pin. TRST Boundary Scan Reset Pin The TRST pin functions as an active-low input to asynchronously initialize (or reset) the boundary scan circuitry. There is an internal weak pull-up resistor on the TRST pin. If JTAG is not used, an external pulldown resistor could be included to ensure the test access port (TAP) is held in reset mode. The resistor values must be chosen from Table 3-2 and must satisfy the parallel resistance value requirement. The values in Table 3-2 correspond to the resistor recommended when a single device is used, and the equivalent parallel resistor when multiple devices are connected via a JTAG chain. In critical applications, an upset in the JTAG circuit could allow entrance to an undesired JTAG state. In such cases, Microsemi recommends tying off TRST to GND through a resistor placed close to the FPGA pin. Note that to operate at all VJTAG voltages, 500 to 1 k will satisfy the requirements. 3- 4 R ev isio n 1 3 ProASIC3L Low Power Flash FPGAs Special Function Pins NC No Connect This pin is not connected to circuitry within the device. These pins can be driven to any voltage or can be left floating with no effect on the operation of the device. DC Do Not Connect This pin should not be connected to any signals on the PCB. These pins should be left unconnected. Packaging Semiconductor technology is constantly shrinking in size while growing in capability and functional integration. To enable next-generation silicon technologies, semiconductor packages have also evolved to provide improved performance and flexibility. Microsemi consistently delivers packages that provide the necessary mechanical and environmental protection to ensure consistent reliability and performance. Microsemi IC packaging technology efficiently supports high-density FPGAs with large-pin-count Ball Grid Arrays (BGAs), but is also flexible enough to accommodate stringent form factor requirements for Chip Scale Packaging (CSP). In addition, Microsemi offers a variety of packages designed to meet your most demanding application and economic requirements for today's embedded and mobile systems. Related Documents User's Guides ProASICL FPGA Fabric User's Guide http://www.microsemi.com/soc/documents/PA3L_UG.pdf Packaging The following documents provide packaging information and device selection for low power flash devices. Product Catalog http://www.microsemi.com/soc/documents/ProdCat_PIB.pdf Lists devices currently recommended for new designs and the packages available for each member of the family. Use this document or the datasheet tables to determine the best package for your design, and which package drawing to use. Package Mechanical Drawings http://www.microsemi.com/soc/documents/PckgMechDrwngs.pdf This document contains the package mechanical drawings for all packages currently or previously supplied by Microsemi. Use the bookmarks to navigate to the package mechanical drawings. Additional packaging materials: http://www.microsemi.com/soc/products/solutions/package/docs.aspx. R ev i si o n 1 3 3 -5 4 - Package Pin Assignments VQ100 100 1 Note: This is the top view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.microsemi.com./soc/products/solutions/package/docs.aspx. R ev i si o n 1 3 4 -1 Package Pin Assignments VQ100 VQ100 VQ100 Pin Number A3P250L Function Pin Number A3P250L Function Pin Number A3P250L Function 1 GND 37 VCC 73 GBA2/IO41PDB1 2 GAA2/IO118UDB3 38 GND 74 VMV1 3 IO118VDB3 39 VCCIB2 75 GNDQ 4 GAB2/IO117UDB3 40 IO77RSB2 76 GBA1/IO40RSB0 5 IO117VDB3 41 IO74RSB2 77 GBA0/IO39RSB0 6 GAC2/IO116UDB3 42 IO71RSB2 78 GBB1/IO38RSB0 7 IO116VDB3 43 GDC2/IO63RSB2 79 GBB0/IO37RSB0 8 IO112PSB3 44 GDB2/IO62RSB2 80 GBC1/IO36RSB0 9 GND 45 GDA2/IO61RSB2 81 GBC0/IO35RSB0 10 GFB1/IO109PDB3 46 GNDQ 82 IO29RSB0 11 GFB0/IO109NDB3 47 TCK 83 IO27RSB0 12 VCOMPLF 48 TDI 84 IO25RSB0 13 GFA0/IO108NPB3 49 TMS 85 IO23RSB0 14 VCCPLF 50 VMV2 86 IO21RSB0 15 GFA1/IO108PPB3 51 GND 87 VCCIB0 16 GFA2/IO107PSB3 52 VPUMP 88 GND 17 VCC 53 NC 89 VCC 18 VCCIB3 54 TDO 90 IO15RSB0 19 GFC2/IO105PSB3 55 TRST 91 IO13RSB0 20 GEC1/IO100PDB3 56 VJTAG 92 IO11RSB0 21 GEC0/IO100NDB3 57 GDA1/IO60USB1 93 GAC1/IO05RSB0 22 GEA1/IO98PDB3 58 GDC0/IO58VDB1 94 GAC0/IO04RSB0 23 GEA0/IO98NDB3 59 GDC1/IO58UDB1 95 GAB1/IO03RSB0 24 VMV3 60 IO52NDB1 96 GAB0/IO02RSB0 25 GNDQ 61 GCB2/IO52PDB1 97 GAA1/IO01RSB0 26 GEA2/IO97RSB2 62 GCA1/IO50PDB1 98 GAA0/IO00RSB0 27 FF/GEB2/IO96RSB2 63 GCA0/IO50NDB1 99 GNDQ 28 GEC2/IO95RSB2 64 GCC0/IO48NDB1 100 VMV0 29 IO93RSB2 65 GCC1/IO48PDB1 30 IO92RSB2 66 VCCIB1 31 IO91RSB2 67 GND 32 IO90RSB2 68 VCC 33 IO88RSB2 69 IO43NDB1 34 IO86RSB2 70 GBC2/IO43PDB1 35 IO85RSB2 71 GBB2/IO42PSB1 36 IO84RSB2 72 IO41NDB1 4- 2 R ev isio n 1 3 ProASIC3L Low Power Flash FPGAs PQ208 1 208 208-Pin PQFP Note: This is the top view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.microsemi.com/soc/products/solutions/package/docs.aspx. R ev i si o n 1 3 4 -3 Package Pin Assignments PQ208 PQ208 PQ208 Pin Number A3PL250 Function Pin Number A3PL250 Function Pin Number A3PL250 Function 1 GND 37 IO104PDB3 73 IO83RSB2 2 GAA2/IO118UDB3 38 IO104NDB3 74 IO82RSB2 3 IO118VDB3 39 IO103PSB3 75 IO81RSB2 4 GAB2/IO117UDB3 40 VCCIB3 76 IO80RSB2 5 IO117VDB3 41 GND 77 IO79RSB2 6 GAC2/IO116UDB3 42 IO101PDB3 78 IO78RSB2 7 IO116VDB3 43 IO101NDB3 79 IO77RSB2 8 IO115UDB3 44 GEC1/IO100PDB3 80 IO76RSB2 9 IO115VDB3 45 GEC0/IO100NDB3 81 GND 10 IO114UDB3 46 GEB1/IO99PDB3 82 IO75RSB2 11 IO114VDB3 47 GEB0/IO99NDB3 83 IO74RSB2 12 IO113PDB3 48 GEA1/IO98PDB3 84 IO73RSB2 13 IO113NDB3 49 GEA0/IO98NDB3 85 IO72RSB2 14 IO112PDB3 50 VMV3 86 IO71RSB2 15 IO112NDB3 51 GNDQ 87 IO70RSB2 16 VCC 52 GND 88 VCC 17 GND 53 NC 89 VCCIB2 18 VCCIB3 54 NC 90 IO69RSB2 19 IO111PDB3 55 GEA2/IO97RSB2 91 IO68RSB2 20 IO111NDB3 56 FF/GEB2/IO96RSB2 92 IO67RSB2 21 GFC1/IO110PDB3 57 GEC2/IO95RSB2 93 IO66RSB2 22 GFC0/IO110NDB3 58 IO94RSB2 94 IO65RSB2 23 GFB1/IO109PDB3 59 IO93RSB2 95 IO64RSB2 24 GFB0/IO109NDB3 60 IO92RSB2 96 GDC2/IO63RSB2 25 VCOMPLF 61 IO91RSB2 97 GND 26 GFA0/IO108NPB3 62 VCCIB2 98 GDB2/IO62RSB2 27 VCCPLF 63 IO90RSB2 99 GDA2/IO61RSB2 28 GFA1/IO108PPB3 64 IO89RSB2 100 GNDQ 29 GND 65 GND 101 TCK 30 GFA2/IO107PDB3 66 IO88RSB2 102 TDI 31 IO107NDB3 67 IO87RSB2 103 TMS 32 GFB2/IO106PDB3 68 IO86RSB2 104 VMV2 33 IO106NDB3 69 IO85RSB2 105 GND 34 GFC2/IO105PDB3 70 IO84RSB2 106 VPUMP 35 IO105NDB3 71 VCC 107 NC 36 NC 72 VCCIB2 108 TDO 4- 4 R ev isio n 1 3 ProASIC3L Low Power Flash FPGAs PQ208 PQ208 PQ208 Pin Number A3PL250 Function Pin Number A3PL250 Function Pin Number A3PL250 Function 109 TRST 145 IO45PDB1 181 IO21RSB0 110 VJTAG 146 IO44NDB1 182 IO20RSB0 111 GDA0/IO60VDB1 147 IO44PDB1 183 IO19RSB0 112 GDA1/IO60UDB1 148 IO43NDB1 184 IO18RSB0 113 GDB0/IO59VDB1 149 GBC2/IO43PDB1 185 IO17RSB0 114 GDB1/IO59UDB1 150 IO42NDB1 186 VCCIB0 115 GDC0/IO58VDB1 151 GBB2/IO42PDB1 187 VCC 116 GDC1/IO58UDB1 152 IO41NDB1 188 IO16RSB0 117 IO57VDB1 153 GBA2/IO41PDB1 189 IO15RSB0 118 IO57UDB1 154 VMV1 190 IO14RSB0 119 IO56NDB1 155 GNDQ 191 IO13RSB0 120 IO56PDB1 156 GND 192 IO12RSB0 121 IO55RSB1 157 NC 193 IO11RSB0 122 GND 158 GBA1/IO40RSB0 194 IO10RSB0 123 VCCIB1 159 GBA0/IO39RSB0 195 GND 124 NC 160 GBB1/IO38RSB0 196 IO09RSB0 125 NC 161 GBB0/IO37RSB0 197 IO08RSB0 126 VCC 162 GND 198 IO07RSB0 127 IO53NDB1 163 GBC1/IO36RSB0 199 IO06RSB0 128 GCC2/IO53PDB1 164 GBC0/IO35RSB0 200 VCCIB0 129 GCB2/IO52PSB1 165 IO34RSB0 201 GAC1/IO05RSB0 130 GND 166 IO33RSB0 202 GAC0/IO04RSB0 131 GCA2/IO51PSB1 167 IO32RSB0 203 GAB1/IO03RSB0 132 GCA1/IO50PDB1 168 IO31RSB0 204 GAB0/IO02RSB0 133 GCA0/IO50NDB1 169 IO30RSB0 205 GAA1/IO01RSB0 134 GCB0/IO49NDB1 170 VCCIB0 206 GAA0/IO00RSB0 135 GCB1/IO49PDB1 171 VCC 207 GNDQ 136 GCC0/IO48NDB1 172 IO29RSB0 208 VMV0 137 GCC1/IO48PDB1 173 IO28RSB0 138 IO47NDB1 174 IO27RSB0 139 IO47PDB1 175 IO26RSB0 140 VCCIB1 176 IO25RSB0 141 GND 177 IO24RSB0 142 VCC 178 GND 143 IO46RSB1 179 IO23RSB0 144 IO45NDB1 180 IO22RSB0 R ev i si o n 1 3 4 -5 Package Pin Assignments PQ208 PQ208 PQ208 Pin Number A3PL600 Function Pin Number A3PL600 Function Pin Number A3PL600 Function 1 GND 37 IO152PDB3 73 IO120RSB2 2 GAA2/IO174PDB3 38 IO152NDB3 74 IO119RSB2 3 IO174NDB3 39 IO150PSB3 75 IO118RSB2 4 GAB2/IO173PDB3 40 VCCIB3 76 IO117RSB2 5 IO173NDB3 41 GND 77 IO116RSB2 6 GAC2/IO172PDB3 42 IO147PDB3 78 IO115RSB2 7 IO172NDB3 43 IO147NDB3 79 IO114RSB2 8 IO171PDB3 44 GEC1/IO146PDB3 80 IO112RSB2 9 IO171NDB3 45 GEC0/IO146NDB3 81 GND 10 IO170PDB3 46 GEB1/IO145PDB3 82 IO111RSB2 11 IO170NDB3 47 GEB0/IO145NDB3 83 IO110RSB2 12 IO169PDB3 48 GEA1/IO144PDB3 84 IO109RSB2 13 IO169NDB3 49 GEA0/IO144NDB3 85 IO108RSB2 14 IO168PDB3 50 VMV3 86 IO107RSB2 15 IO168NDB3 51 GNDQ 87 IO106RSB2 16 VCC 52 GND 88 VCC 17 GND 53 VMV2 89 VCCIB2 18 VCCIB3 54 GEA2/IO143RSB2 90 IO104RSB2 19 IO166PDB3 55 FF/GEB2/IO142RSB2 91 IO102RSB2 20 IO166NDB3 56 GEC2/IO141RSB2 92 IO100RSB2 21 GFC1/IO164PDB3 57 IO140RSB2 93 IO98RSB2 22 GFC0/IO164NDB3 58 IO139RSB2 94 IO96RSB2 23 GFB1/IO163PDB3 59 IO138RSB2 95 IO92RSB2 24 GFB0/IO163NDB3 60 IO137RSB2 96 GDC2/IO91RSB2 25 VCOMPLF 61 IO136RSB2 97 GND 26 GFA0/IO162NPB3 62 VCCIB2 98 GDB2/IO90RSB2 27 VCCPLF 63 IO135RSB2 99 GDA2/IO89RSB2 28 GFA1/IO162PPB3 64 IO133RSB2 100 GNDQ 29 GND 65 GND 101 TCK 30 GFA2/IO161PDB3 66 IO131RSB2 102 TDI 31 IO161NDB3 67 IO129RSB2 103 TMS 32 GFB2/IO160PDB3 68 IO127RSB2 104 VMV2 33 IO160NDB3 69 IO125RSB2 105 GND 34 GFC2/IO159PDB3 70 IO123RSB2 106 VPUMP 35 IO159NDB3 71 VCC 107 GNDQ 36 VCC 72 VCCIB2 108 TDO 4- 6 R ev isio n 1 3 ProASIC3L Low Power Flash FPGAs PQ208 PQ208 PQ208 Pin Number A3PL600 Function Pin Number A3PL600 Function Pin Number A3PL600 Function 109 TRST 145 IO64PDB1 181 IO27RSB0 110 VJTAG 146 IO63NDB1 182 IO26RSB0 111 GDA0/IO88NDB1 147 IO63PDB1 183 IO25RSB0 112 GDA1/IO88PDB1 148 IO62NDB1 184 IO24RSB0 113 GDB0/IO87NDB1 149 GBC2/IO62PDB1 185 IO23RSB0 114 GDB1/IO87PDB1 150 IO61NDB1 186 VCCIB0 115 GDC0/IO86NDB1 151 GBB2/IO61PDB1 187 VCC 116 GDC1/IO86PDB1 152 IO60NDB1 188 IO20RSB0 117 IO84NDB1 153 GBA2/IO60PDB1 189 IO19RSB0 118 IO84PDB1 154 VMV1 190 IO18RSB0 119 IO82NDB1 155 GNDQ 191 IO17RSB0 120 IO82PDB1 156 GND 192 IO16RSB0 121 IO81PSB1 157 VMV0 193 IO14RSB0 122 GND 158 GBA1/IO59RSB0 194 IO12RSB0 123 VCCIB1 159 GBA0/IO58RSB0 195 GND 124 IO77NDB1 160 GBB1/IO57RSB0 196 IO10RSB0 125 IO77PDB1 161 GBB0/IO56RSB0 197 IO09RSB0 126 NC 162 GND 198 IO08RSB0 127 IO74NDB1 163 GBC1/IO55RSB0 199 IO07RSB0 128 GCC2/IO74PDB1 164 GBC0/IO54RSB0 200 VCCIB0 129 GCB2/IO73PSB1 165 IO52RSB0 201 GAC1/IO05RSB0 130 GND 166 IO50RSB0 202 GAC0/IO04RSB0 131 GCA2/IO72PSB1 167 IO48RSB0 203 GAB1/IO03RSB0 132 GCA1/IO71PDB1 168 IO46RSB0 204 GAB0/IO02RSB0 133 GCA0/IO71NDB1 169 IO44RSB0 205 GAA1/IO01RSB0 134 GCB0/IO70NDB1 170 VCCIB0 206 GAA0/IO00RSB0 135 GCB1/IO70PDB1 171 VCC 207 GNDQ 136 GCC0/IO69NDB1 172 IO36RSB0 208 VMV0 137 GCC1/IO69PDB1 173 IO35RSB0 138 IO67NDB1 174 IO34RSB0 139 IO67PDB1 175 IO33RSB0 140 VCCIB1 176 IO32RSB0 141 GND 177 IO31RSB0 142 VCC 178 GND 143 IO65PSB1 179 IO29RSB0 144 IO64NDB1 180 IO28RSB0 R ev i si o n 1 3 4 -7 Package Pin Assignments PQ208 PQ208 PQ208 Pin Number APL1000 Function Pin Number APL1000 Function Pin Number APL1000 Function 1 GND 37 IO199PDB3 73 IO162RSB2 2 GAA2/IO225PDB3 38 IO199NDB3 74 IO160RSB2 3 IO225NDB3 39 IO197PSB3 75 IO158RSB2 4 GAB2/IO224PDB3 40 VCCIB3 76 IO156RSB2 5 IO224NDB3 41 GND 77 IO154RSB2 6 GAC2/IO223PDB3 42 IO191PDB3 78 IO152RSB2 7 IO223NDB3 43 IO191NDB3 79 IO150RSB2 8 IO222PDB3 44 GEC1/IO190PDB3 80 IO148RSB2 9 IO222NDB3 45 GEC0/IO190NDB3 81 GND 10 IO220PDB3 46 GEB1/IO189PDB3 82 IO143RSB2 11 IO220NDB3 47 GEB0/IO189NDB3 83 IO141RSB2 12 IO218PDB3 48 GEA1/IO188PDB3 84 IO139RSB2 13 IO218NDB3 49 GEA0/IO188NDB3 85 IO137RSB2 14 IO216PDB3 50 VMV3 86 IO135RSB2 15 IO216NDB3 51 GNDQ 87 IO133RSB2 16 VCC 52 GND 88 VCC 17 GND 53 VMV2 89 VCCIB2 18 VCCIB3 54 GEA2/IO187RSB2 90 IO128RSB2 19 IO212PDB3 55 FF/GEB2/IO186RSB2 91 IO126RSB2 20 IO212NDB3 56 GEC2/IO185RSB2 92 IO124RSB2 21 GFC1/IO209PDB3 57 IO184RSB2 93 IO122RSB2 22 GFC0/IO209NDB3 58 IO183RSB2 94 IO120RSB2 23 GFB1/IO208PDB3 59 IO182RSB2 95 IO118RSB2 24 GFB0/IO208NDB3 60 IO181RSB2 96 GDC2/IO116RSB2 25 VCOMPLF 61 IO180RSB2 97 GND 26 GFA0/IO207NPB3 62 VCCIB2 98 GDB2/IO115RSB2 27 VCCPLF 63 IO178RSB2 99 GDA2/IO114RSB2 28 GFA1/IO207PPB3 64 IO176RSB2 100 GNDQ 29 GND 65 GND 101 TCK 30 GFA2/IO206PDB3 66 IO174RSB2 102 TDI 31 IO206NDB3 67 IO172RSB2 103 TMS 32 GFB2/IO205PDB3 68 IO170RSB2 104 VMV2 33 IO205NDB3 69 IO168RSB2 105 GND 34 GFC2/IO204PDB3 70 IO166RSB2 106 VPUMP 35 IO204NDB3 71 VCC 107 GNDQ 36 VCC 72 VCCIB2 108 TDO 4- 8 R ev isio n 1 3 ProASIC3L Low Power Flash FPGAs PQ208 PQ208 PQ208 Pin Number APL1000 Function Pin Number APL1000 Function Pin Number APL1000 Function 109 TRST 145 IO84PDB1 181 IO33RSB0 110 VJTAG 146 IO82NDB1 182 IO31RSB0 111 GDA0/IO113NDB1 147 IO82PDB1 183 IO29RSB0 112 GDA1/IO113PDB1 148 IO80NDB1 184 IO27RSB0 113 GDB0/IO112NDB1 149 GBC2/IO80PDB1 185 IO25RSB0 114 GDB1/IO112PDB1 150 IO79NDB1 186 VCCIB0 115 GDC0/IO111NDB1 151 GBB2/IO79PDB1 187 VCC 116 GDC1/IO111PDB1 152 IO78NDB1 188 IO22RSB0 117 IO109NDB1 153 GBA2/IO78PDB1 189 IO20RSB0 118 IO109PDB1 154 VMV1 190 IO18RSB0 119 IO106NDB1 155 GNDQ 191 IO16RSB0 120 IO106PDB1 156 GND 192 IO15RSB0 121 IO104PSB1 157 VMV0 193 IO14RSB0 122 GND 158 GBA1/IO77RSB0 194 IO13RSB0 123 VCCIB1 159 GBA0/IO76RSB0 195 GND 124 IO99NDB1 160 GBB1/IO75RSB0 196 IO12RSB0 125 IO99PDB1 161 GBB0/IO74RSB0 197 IO11RSB0 126 NC 162 GND 198 IO10RSB0 127 IO96NDB1 163 GBC1/IO73RSB0 199 IO09RSB0 128 GCC2/IO96PDB1 164 GBC0/IO72RSB0 200 VCCIB0 129 GCB2/IO95PSB1 165 IO70RSB0 201 GAC1/IO05RSB0 130 GND 166 IO67RSB0 202 GAC0/IO04RSB0 131 GCA2/IO94PSB1 167 IO63RSB0 203 GAB1/IO03RSB0 132 GCA1/IO93PDB1 168 IO60RSB0 204 GAB0/IO02RSB0 133 GCA0/IO93NDB1 169 IO57RSB0 205 GAA1/IO01RSB0 134 GCB0/IO92NDB1 170 VCCIB0 206 GAA0/IO00RSB0 135 GCB1/IO92PDB1 171 VCC 207 GNDQ 136 GCC0/IO91NDB1 172 IO54RSB0 208 VMV0 137 GCC1/IO91PDB1 173 IO51RSB0 138 IO88NDB1 174 IO48RSB0 139 IO88PDB1 175 IO45RSB0 140 VCCIB1 176 IO42RSB0 141 GND 177 IO40RSB0 142 VCC 178 GND 143 IO86PSB1 179 IO38RSB0 144 IO84NDB1 180 IO35RSB0 R ev i si o n 1 3 4 -9 Package Pin Assignments PQ208 PQ208 PQ208 Pin Number A3PE3000L Function Pin Number A3PE3000L Function Pin Number A3PE3000L Function 1 GND 36 VCC 71 VCC 2 GNDQ 37 IO252PDB6V2 72 VCCIB5 3 VMV7 38 IO252NDB6V2 73 IO202NDB5V1 4 GAB2/IO308PSB7V4 39 IO248PSB6V1 74 IO202PDB5V1 5 GAA2/IO309PDB7V4 40 VCCIB6 75 IO198NDB5V0 6 IO309NDB7V4 41 GND 76 IO198PDB5V0 7 GAC2/IO307PDB7V4 42 IO244PDB6V1 77 IO197NDB5V0 8 IO307NDB7V4 43 IO244NDB6V1 78 IO197PDB5V0 9 IO303PDB7V3 44 GEC1/IO236PDB6V0 79 IO194NDB5V0 10 IO303NDB7V3 45 GEC0/IO236NDB6V0 80 IO194PDB5V0 11 IO299PDB7V3 46 GEB1/IO235PPB6V0 81 GND 12 IO299NDB7V3 47 GEA1/IO234PPB6V0 82 IO184NDB4V3 13 IO295PDB7V2 48 GEB0/IO235NPB6V0 83 IO184PDB4V3 14 IO295NDB7V2 49 GEA0/IO234NPB6V0 84 IO180NDB4V3 15 IO291PSB7V2 50 VMV6 85 IO180PDB4V3 16 VCC 51 GNDQ 86 IO176NDB4V2 17 GND 52 GND 87 IO176PDB4V2 18 VCCIB7 53 VMV5 88 VCC 19 IO285PDB7V1 54 GNDQ 89 VCCIB4 20 IO285NDB7V1 55 IO233NDB5V4 90 IO170NDB4V2 21 IO279PSB7V0 56 GEA2/IO233PDB5V4 91 IO170PDB4V2 22 GFC1/IO275PSB7V0 57 IO232NDB5V4 92 IO166NDB4V1 23 GFB1/IO274PDB7V0 58 FF/GEB2/IO232PDB5V4 93 IO166PDB4V1 24 GFB0/IO274NDB7V0 59 IO231NDB5V4 94 IO156NDB4V0 25 VCOMPLF 60 GEC2/IO231PDB5V4 95 GDC2/IO156PDB4V0 26 GFA0/IO273NPB6V4 61 IO230PSB5V4 96 IO154NPB4V0 27 VCCPLF 62 VCCIB5 97 GND 28 GFA1/IO273PPB6V4 62 VCCIB5 98 GDB2/IO155PSB4V0 29 GND 63 IO218NDB5V3 99 GDA2/IO154PPB4V0 30 GFA2/IO272PDB6V4 64 IO218PDB5V3 100 GNDQ 31 IO272NDB6V4 65 GND 101 TCK 32 GFB2/IO271PPB6V4 66 IO214PSB5V2 102 TDI 33 GFC2/IO270PPB6V4 67 IO212NDB5V2 103 TMS 34 IO271NPB6V4 68 IO212PDB5V2 104 VMV4 35 IO270NPB6V4 69 IO208NDB5V1 105 GND 36 VCC 70 IO208PDB5V1 106 VPUMP 4- 10 R ev i sio n 1 3 ProASIC3L Low Power Flash FPGAs PQ208 PQ208 PQ208 Pin Number A3PE3000L Function Pin Number A3PE3000L Function Pin Number A3PE3000L Function 107 GNDQ 143 IO99NDB2V2 178 GND 108 TDO 144 IO99PDB2V2 179 IO40NDB0V4 109 TRST 145 IO96NDB2V1 180 IO37PDB0V4 110 VJTAG 146 IO96PDB2V1 181 IO37NDB0V4 111 VMV3 147 IO91NDB2V1 182 IO35PDB0V4 112 GDA0/IO153NPB3V4 148 IO91PDB2V1 183 IO35NDB0V4 113 GDB0/IO152NPB3V4 149 IO88NDB2V0 184 IO32PDB0V3 114 GDA1/IO153PPB3V4 150 IO88PDB2V0 185 IO32NDB0V3 115 GDB1/IO152PPB3V4 151 GBC2/IO84PSB2V0 186 VCCIB0 116 GDC0/IO151NDB3V4 152 GBA2/IO82PSB2V0 187 VCC 117 GDC1/IO151PDB3V4 153 GBB2/IO83PSB2V0 188 IO28PDB0V3 118 IO134NDB3V2 154 VMV2 189 IO28NDB0V3 119 IO134PDB3V2 155 GNDQ 190 IO24PDB0V2 120 IO132NDB3V2 156 GND 191 IO24NDB0V2 121 IO132PDB3V2 157 VMV1 192 IO21PSB0V2 122 GND 158 GNDQ 193 IO16PDB0V1 123 VCCIB3 159 GBA1/IO81PDB1V4 194 IO16NDB0V1 124 GCC2/IO117PSB3V0 160 GBA0/IO81NDB1V4 195 GND 125 GCB2/IO116PSB3V0 161 GBB1/IO80PDB1V4 196 IO11PDB0V1 126 NC 162 GND 197 IO11NDB0V1 127 IO115NDB3V0 163 GBB0/IO80NDB1V4 198 IO08PDB0V0 128 GCA2/IO115PDB3V0 164 GBC1/IO79PDB1V4 199 IO08NDB0V0 129 GCA1/IO114PPB3V0 165 GBC0/IO79NDB1V4 200 VCCIB0 130 GND 166 IO74PDB1V4 201 GAC1/IO02PDB0V0 131 VCCPLC 167 IO74NDB1V4 202 GAC0/IO02NDB0V0 132 GCA0/IO114NPB3V0 168 IO70PDB1V3 203 GAB1/IO01PDB0V0 133 VCOMPLC 169 IO70NDB1V3 204 GAB0/IO01NDB0V0 134 GCB0/IO113NDB2V3 170 VCCIB1 205 GAA1/IO00PDB0V0 135 GCB1/IO113PDB2V3 171 VCC 206 GAA0/IO00NDB0V0 136 GCC1/IO112PSB2V3 171 VCC 207 GNDQ 137 IO110NDB2V3 172 IO56PSB1V1 208 VMV0 138 IO110PDB2V3 173 IO55PDB1V1 139 IO106PSB2V3 174 IO55NDB1V1 140 VCCIB2 175 IO54PDB1V1 141 GND 176 IO54NDB1V1 142 VCC 177 IO40PDB0V4 R ev i si o n 1 3 4- 11 Package Pin Assignments FG144 A1 Ball Pad Corner 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M Note: This is the bottom view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.microsemi.com/soc/products/solutions/package/docs.aspx. 4- 12 R ev i sio n 1 3 ProASIC3L Low Power Flash FPGAs FG144 FG144 FG144 Pin Number A3P250L Function Pin Number A3P250L Function Pin Number A3P250L Function A1 GNDQ D1 IO112NDB3 G1 GFA1/IO108PPB3 A2 VMV0 D2 IO112PDB3 G2 GND A3 GAB0/IO02RSB0 D3 IO116VDB3 G3 VCCPLF A4 GAB1/IO03RSB0 D4 GAA2/IO118UPB3 G4 GFA0/IO108NPB3 A5 IO16RSB0 D5 GAC0/IO04RSB0 G5 GND A6 GND D6 GAC1/IO05RSB0 G6 GND A7 IO29RSB0 D7 GBC0/IO35RSB0 G7 GND A8 VCC D8 GBC1/IO36RSB0 G8 GDC1/IO58UPB1 A9 IO33RSB0 D9 GBB2/IO42PDB1 G9 IO53NDB1 A10 GBA0/IO39RSB0 D10 IO42NDB1 G10 GCC2/IO53PDB1 A11 GBA1/IO40RSB0 D11 IO43NPB1 G11 IO52NDB1 A12 GNDQ D12 GCB1/IO49PPB1 G12 GCB2/IO52PDB1 B1 GAB2/IO117UDB3 E1 VCC H1 VCC B2 GND E2 GFC0/IO110NDB3 H2 GFB2/IO106PDB3 B3 GAA0/IO00RSB0 E3 GFC1/IO110PDB3 H3 GFC2/IO105PSB3 B4 GAA1/IO01RSB0 E4 VCCIB3 H4 GEC1/IO100PDB3 B5 IO14RSB0 E5 IO118VPB3 H5 VCC B6 IO19RSB0 E6 VCCIB0 H6 IO79RSB2 B7 IO22RSB0 E7 VCCIB0 H7 IO65RSB2 B8 IO30RSB0 E8 GCC1/IO48PDB1 H8 GDB2/IO62RSB2 B9 GBB0/IO37RSB0 E9 VCCIB1 H9 GDC0/IO58VPB1 B10 GBB1/IO38RSB0 E10 VCC H10 VCCIB1 B11 GND E11 GCA0/IO50NDB1 H11 IO54PSB1 B12 VMV1 E12 IO51NDB1 H12 VCC C1 IO117VDB3 F1 GFB0/IO109NPB3 J1 GEB1/IO99PDB3 C2 GFA2/IO107PPB3 F2 VCOMPLF J2 IO106NDB3 C3 GAC2/IO116UDB3 F3 GFB1/IO109PPB3 J3 VCCIB3 C4 VCC F4 IO107NPB3 J4 GEC0/IO100NDB3 C5 IO12RSB0 F5 GND J5 IO88RSB2 C6 IO17RSB0 F6 GND J6 IO81RSB2 C7 IO24RSB0 F7 GND J7 VCC C8 IO31RSB0 F8 GCC0/IO48NDB1 J8 TCK C9 IO34RSB0 F9 GCB0/IO49NPB1 J9 GDA2/IO61RSB2 C10 GBA2/IO41PDB1 F10 GND J10 TDO C11 IO41NDB1 F11 GCA1/IO50PDB1 J11 GDA1/IO60UDB1 C12 GBC2/IO43PPB1 F12 GCA2/IO51PDB1 J12 GDB1/IO59UDB1 R ev i si o n 1 3 4- 13 Package Pin Assignments FG144 Pin Number A3P250L Function K1 GEB0/IO99NDB3 K2 GEA1/IO98PDB3 K3 GEA0/IO98NDB3 K4 GEA2/IO97RSB2 K5 IO90RSB2 K6 IO84RSB2 K7 GND K8 IO66RSB2 K9 GDC2/IO63RSB2 K10 GND K11 GDA0/IO60VDB1 K12 GDB0/IO59VDB1 L1 GND L2 VMV3 L3 FF/GEB2/IO96RSB2 L4 IO91RSB2 L5 VCCIB2 L6 IO82RSB2 L7 IO80RSB2 L8 IO72RSB2 L9 TMS L10 VJTAG L11 VMV2 L12 TRST M1 GNDQ M2 GEC2/IO95RSB2 M3 IO92RSB2 M4 IO89RSB2 M5 IO87RSB2 M6 IO85RSB2 M7 IO78RSB2 M8 IO76RSB2 M9 TDI M10 VCCIB2 M11 VPUMP M12 GNDQ 4- 14 R ev i sio n 1 3 ProASIC3L Low Power Flash FPGAs FG144 FG144 FG144 Pin Number A3P600L Function Pin Number A3P600L Function Pin Number A3P600L Function A1 GNDQ D1 IO169PDB3 G1 GFA1/IO162PPB3 A2 VMV0 D2 IO169NDB3 G2 GND A3 GAB0/IO02RSB0 D3 IO172NDB3 G3 VCCPLF A4 GAB1/IO03RSB0 D4 GAA2/IO174PPB3 G4 GFA0/IO162NPB3 A5 IO10RSB0 D5 GAC0/IO04RSB0 G5 GND A6 GND D6 GAC1/IO05RSB0 G6 GND A7 IO34RSB0 D7 GBC0/IO54RSB0 G7 GND A8 VCC D8 GBC1/IO55RSB0 G8 GDC1/IO86PPB1 A9 IO50RSB0 D9 GBB2/IO61PDB1 G9 IO74NDB1 A10 GBA0/IO58RSB0 D10 IO61NDB1 G10 GCC2/IO74PDB1 A11 GBA1/IO59RSB0 D11 IO62NPB1 G11 IO73NDB1 A12 GNDQ D12 GCB1/IO70PPB1 G12 GCB2/IO73PDB1 B1 GAB2/IO173PDB3 E1 VCC H1 VCC B2 GND E2 GFC0/IO164NDB3 H2 GFB2/IO160PDB3 B3 GAA0/IO00RSB0 E3 GFC1/IO164PDB3 H3 GFC2/IO159PSB3 B4 GAA1/IO01RSB0 E4 VCCIB3 H4 GEC1/IO146PDB3 B5 IO13RSB0 E5 IO174NPB3 H5 VCC B6 IO19RSB0 E6 VCCIB0 H6 IO80PDB1 B7 IO31RSB0 E7 VCCIB0 H7 IO80NDB1 B8 IO39RSB0 E8 GCC1/IO69PDB1 H8 GDB2/IO90RSB2 B9 GBB0/IO56RSB0 E9 VCCIB1 H9 GDC0/IO86NPB1 B10 GBB1/IO57RSB0 E10 VCC H10 VCCIB1 B11 GND E11 GCA0/IO71NDB1 H11 IO84PSB1 B12 VMV1 E12 IO72NDB1 H12 VCC C1 IO173NDB3 F1 GFB0/IO163NPB3 J1 GEB1/IO145PDB3 C2 GFA2/IO161PPB3 F2 VCOMPLF J2 IO160NDB3 C3 GAC2/IO172PDB3 F3 GFB1/IO163PPB3 J3 VCCIB3 C4 VCC F4 IO161NPB3 J4 GEC0/IO146NDB3 C5 IO16RSB0 F5 GND J5 IO129RSB2 C6 IO25RSB0 F6 GND J6 IO131RSB2 C7 IO28RSB0 F7 GND J7 VCC C8 IO42RSB0 F8 GCC0/IO69NDB1 J8 TCK C9 IO45RSB0 F9 GCB0/IO70NPB1 J9 GDA2/IO89RSB2 C10 GBA2/IO60PDB1 F10 GND J10 TDO C11 IO60NDB1 F11 GCA1/IO71PDB1 J11 GDA1/IO88PDB1 C12 GBC2/IO62PPB1 F12 GCA2/IO72PDB1 J12 GDB1/IO87PDB1 R ev i si o n 1 3 4- 15 Package Pin Assignments FG144 Pin Number A3P600L Function K1 GEB0/IO145NDB3 K2 GEA1/IO144PDB3 K3 GEA0/IO144NDB3 K4 GEA2/IO143RSB2 K5 IO119RSB2 K6 IO111RSB2 K7 GND K8 IO94RSB2 K9 GDC2/IO91RSB2 K10 GND K11 GDA0/IO88NDB1 K12 GDB0/IO87NDB1 L1 GND L2 VMV3 L3 FF/GEB2/IO142RSB2 L4 IO136RSB2 L5 VCCIB2 L6 IO115RSB2 L7 IO103RSB2 L8 IO97RSB2 L9 TMS L10 VJTAG L11 VMV2 L12 TRST M1 GNDQ M2 GEC2/IO141RSB2 M3 IO138RSB2 M4 IO123RSB2 M5 IO126RSB2 M6 IO134RSB2 M7 IO108RSB2 M8 IO99RSB2 M9 TDI M10 VCCIB2 M11 VPUMP M12 GNDQ 4- 16 R ev i sio n 1 3 ProASIC3L Low Power Flash FPGAs FG144 FG144 FG144 Pin Number A3P1000L Function Pin Number A3P1000L Function Pin Number A3P1000L Function A1 GNDQ D1 IO213PDB3 G1 GFA1/IO207PPB3 A2 VMV0 D2 IO213NDB3 G2 GND A3 GAB0/IO02RSB0 D3 IO223NDB3 G3 VCCPLF A4 GAB1/IO03RSB0 D4 GAA2/IO225PPB3 G4 GFA0/IO207NPB3 A5 IO10RSB0 D5 GAC0/IO04RSB0 G5 GND A6 GND D6 GAC1/IO05RSB0 G6 GND A7 IO44RSB0 D7 GBC0/IO72RSB0 G7 GND A8 VCC D8 GBC1/IO73RSB0 G8 GDC1/IO111PPB1 A9 IO69RSB0 D9 GBB2/IO79PDB1 G9 IO96NDB1 A10 GBA0/IO76RSB0 D10 IO79NDB1 G10 GCC2/IO96PDB1 A11 GBA1/IO77RSB0 D11 IO80NPB1 G11 IO95NDB1 A12 GNDQ D12 GCB1/IO92PPB1 G12 GCB2/IO95PDB1 B1 GAB2/IO224PDB3 E1 VCC H1 VCC B2 GND E2 GFC0/IO209NDB3 H2 GFB2/IO205PDB3 B3 GAA0/IO00RSB0 E3 GFC1/IO209PDB3 H3 GFC2/IO204PSB3 B4 GAA1/IO01RSB0 E4 VCCIB3 H4 GEC1/IO190PDB3 B5 IO13RSB0 E5 IO225NPB3 H5 VCC B6 IO26RSB0 E6 VCCIB0 H6 IO105PDB1 B7 IO35RSB0 E7 VCCIB0 H7 IO105NDB1 B8 IO60RSB0 E8 GCC1/IO91PDB1 H8 GDB2/IO115RSB2 B9 GBB0/IO74RSB0 E9 VCCIB1 H9 GDC0/IO111NPB1 B10 GBB1/IO75RSB0 E10 VCC H10 VCCIB1 B11 GND E11 GCA0/IO93NDB1 H11 IO101PSB1 B12 VMV1 E12 IO94NDB1 H12 VCC C1 IO224NDB3 F1 GFB0/IO208NPB3 J1 GEB1/IO189PDB3 C2 GFA2/IO206PPB3 F2 VCOMPLF J2 IO205NDB3 C3 GAC2/IO223PDB3 F3 GFB1/IO208PPB3 J3 VCCIB3 C4 VCC F4 IO206NPB3 J4 GEC0/IO190NDB3 C5 IO16RSB0 F5 GND J5 IO160RSB2 C6 IO29RSB0 F6 GND J6 IO157RSB2 C7 IO32RSB0 F7 GND J7 VCC C8 IO63RSB0 F8 GCC0/IO91NDB1 J8 TCK C9 IO66RSB0 F9 GCB0/IO92NPB1 J9 GDA2/IO114RSB2 C10 GBA2/IO78PDB1 F10 GND J10 TDO C11 IO78NDB1 F11 GCA1/IO93PDB1 J11 GDA1/IO113PDB1 C12 GBC2/IO80PPB1 F12 GCA2/IO94PDB1 J12 GDB1/IO112PDB1 R ev i si o n 1 3 4- 17 Package Pin Assignments FG144 Pin Number A3P1000L Function 4- 18 K1 GEB0/IO189NDB3 K2 GEA1/IO188PDB3 K3 GEA0/IO188NDB3 K4 GEA2/IO187RSB2 K5 IO169RSB2 K6 IO152RSB2 K7 GND K8 IO117RSB2 K9 GDC2/IO116RSB2 K10 GND K11 GDA0/IO113NDB1 K12 GDB0/IO112NDB1 L1 GND L2 VMV3 L3 FF/GEB2/IO186RSB2 L4 IO172RSB2 L5 VCCIB2 L6 IO153RSB2 L7 IO144RSB2 L8 IO140RSB2 L9 TMS L10 VJTAG L11 VMV2 L12 TRST M1 GNDQ M2 GEC2/IO185RSB2 M3 IO173RSB2 M4 IO168RSB2 M5 IO161RSB2 M6 IO156RSB2 M7 IO145RSB2 M8 IO141RSB2 M9 TDI M10 VCCIB2 M11 VPUMP M12 GNDQ R ev i sio n 1 3 ProASIC3L Low Power Flash FPGAs FG256 A1 Ball Pad Corner 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T Note: This is the bottom view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.microsemi.com/soc/products/solutions/package/docs.aspx. R ev i si o n 1 3 4- 19 Package Pin Assignments FG256 FG256 FG256 Pin Number A3P250L Function Pin Number A3P250L Function Pin Number A3P250L Function A1 GND C5 GAC0/IO04RSB0 E9 IO24RSB0 A2 GAA0/IO00RSB0 C6 GAC1/IO05RSB0 E10 VCCIB0 A3 GAA1/IO01RSB0 C7 IO13RSB0 E11 VCCIB0 A4 GAB0/IO02RSB0 C8 IO17RSB0 E12 VMV1 A5 IO07RSB0 C9 IO22RSB0 E13 GBC2/IO43PDB1 A6 IO10RSB0 C10 IO27RSB0 E14 IO46RSB1 A7 IO11RSB0 C11 IO31RSB0 E15 NC A8 IO15RSB0 C12 GBC0/IO35RSB0 E16 IO45PDB1 A9 IO20RSB0 C13 IO34RSB0 F1 IO113NDB3 A10 IO25RSB0 C14 NC F2 IO112PPB3 A11 IO29RSB0 C15 IO42NPB1 F3 NC A12 IO33RSB0 C16 IO44PDB1 F4 IO115VDB3 A13 GBB1/IO38RSB0 D1 IO114VDB3 F5 VCCIB3 A14 GBA0/IO39RSB0 D2 IO114UDB3 F6 GND A15 GBA1/IO40RSB0 D3 GAC2/IO116UDB3 F7 VCC A16 GND D4 NC F8 VCC B1 GAB2/IO117UDB3 D5 GNDQ F9 VCC B2 GAA2/IO118UDB3 D6 IO08RSB0 F10 VCC B3 NC D7 IO14RSB0 F11 GND B4 GAB1/IO03RSB0 D8 IO18RSB0 F12 VCCIB1 B5 IO06RSB0 D9 IO23RSB0 F13 IO43NDB1 B6 IO09RSB0 D10 IO28RSB0 F14 NC B7 IO12RSB0 D11 IO32RSB0 F15 IO47PPB1 B8 IO16RSB0 D12 GNDQ F16 IO45NDB1 B9 IO21RSB0 D13 NC G1 IO111NDB3 B10 IO26RSB0 D14 GBB2/IO42PPB1 G2 IO111PDB3 B11 IO30RSB0 D15 NC G3 IO112NPB3 B12 GBC1/IO36RSB0 D16 IO44NDB1 G4 GFC1/IO110PPB3 B13 GBB0/IO37RSB0 E1 IO113PDB3 G5 VCCIB3 B14 NC E2 NC G6 VCC B15 GBA2/IO41PDB1 E3 IO116VDB3 G7 GND B16 IO41NDB1 E4 IO115UDB3 G8 GND C1 IO117VDB3 E5 VMV0 G9 GND C2 IO118VDB3 E6 VCCIB0 G10 GND C3 NC E7 VCCIB0 G11 VCC C4 NC E8 IO19RSB0 G12 VCCIB1 4- 20 R ev i sio n 1 3 ProASIC3L Low Power Flash FPGAs FG256 FG256 FG256 Pin Number A3P250L Function Pin Number A3P250L Function Pin Number A3P250L Function G13 GCC1/IO48PPB1 K1 GFC2/IO105PDB3 M5 VMV3 G14 IO47NPB1 K2 IO107NPB3 M6 VCCIB2 G15 IO54PDB1 K3 IO104PPB3 M7 VCCIB2 G16 IO54NDB1 K4 NC M8 NC H1 GFB0/IO109NPB3 K5 VCCIB3 M9 IO74RSB2 H2 GFA0/IO108NDB3 K6 VCC M10 VCCIB2 H3 GFB1/IO109PPB3 K7 GND M11 VCCIB2 H4 VCOMPLF K8 GND M12 VMV2 H5 GFC0/IO110NPB3 K9 GND M13 NC H6 VCC K10 GND M14 GDB1/IO59UPB1 H7 GND K11 VCC M15 GDC1/IO58UDB1 H8 GND K12 VCCIB1 M16 IO56NDB1 H9 GND K13 IO52NPB1 N1 IO103NDB3 H10 GND K14 IO55RSB1 N2 IO101PPB3 H11 VCC K15 IO53NPB1 N3 GEC1/IO100PPB3 H12 GCC0/IO48NPB1 K16 IO51NDB1 N4 NC H13 GCB1/IO49PPB1 L1 IO105NDB3 N5 GNDQ H14 GCA0/IO50NPB1 L2 IO104NPB3 N6 GEA2/IO97RSB2 H15 NC L3 NC N7 IO86RSB2 H16 GCB0/IO49NPB1 L4 IO102RSB3 N8 IO82RSB2 J1 GFA2/IO107PPB3 L5 VCCIB3 N9 IO75RSB2 J2 GFA1/IO108PDB3 L6 GND N10 IO69RSB2 J3 VCCPLF L7 VCC N11 IO64RSB2 J4 IO106NDB3 L8 VCC N12 GNDQ J5 GFB2/IO106PDB3 L9 VCC N13 NC J6 VCC L10 VCC N14 VJTAG J7 GND L11 GND N15 GDC0/IO58VDB1 J8 GND L12 VCCIB1 N16 GDA1/IO60UDB1 J9 GND L13 GDB0/IO59VPB1 P1 GEB1/IO99PDB3 J10 GND L14 IO57VDB1 P2 GEB0/IO99NDB3 J11 VCC L15 IO57UDB1 P3 NC J12 GCB2/IO52PPB1 L16 IO56PDB1 P4 NC J13 GCA1/IO50PPB1 M1 IO103PDB3 P5 IO92RSB2 J14 GCC2/IO53PPB1 M2 NC P6 IO89RSB2 J15 NC M3 IO101NPB3 P7 IO85RSB2 J16 GCA2/IO51PDB1 M4 GEC0/IO100NPB3 P8 IO81RSB2 R ev i si o n 1 3 4- 21 Package Pin Assignments FG256 FG256 Pin Number A3P250L Function Pin Number A3P250L Function P9 IO76RSB2 T13 IO67RSB2 P10 IO71RSB2 T14 GDA2/IO61RSB2 P11 IO66RSB2 T15 TMS P12 NC T16 GND P13 TCK P14 VPUMP P15 TRST P16 GDA0/IO60VDB1 R1 GEA1/IO98PDB3 R2 GEA0/IO98NDB3 R3 NC R4 GEC2/IO95RSB2 R5 IO91RSB2 R6 IO88RSB2 R7 IO84RSB2 R8 IO80RSB2 R9 IO77RSB2 R10 IO72RSB2 R11 IO68RSB2 R12 IO65RSB2 R13 GDB2/IO62RSB2 R14 TDI R15 NC R16 TDO T1 GND T2 IO94RSB2 T3 FF/GEB2/IO96RSB2 T4 IO93RSB2 T5 IO90RSB2 T6 IO87RSB2 T7 IO83RSB2 T8 IO79RSB2 T9 IO78RSB2 T10 IO73RSB2 T11 IO70RSB2 T12 GDC2/IO63RSB2 4- 22 R ev i sio n 1 3 ProASIC3L Low Power Flash FPGAs FG256 FG256 FG256 Pin Number A3P600L Function Pin Number A3P600L Function Pin Number A3P600L Function A1 GND C5 GAC0/IO04RSB0 E9 IO31RSB0 A2 GAA0/IO00RSB0 C6 GAC1/IO05RSB0 E10 VCCIB0 A3 GAA1/IO01RSB0 C7 IO20RSB0 E11 VCCIB0 A4 GAB0/IO02RSB0 C8 IO24RSB0 E12 VMV1 A5 IO11RSB0 C9 IO33RSB0 E13 GBC2/IO62PDB1 A6 IO16RSB0 C10 IO39RSB0 E14 IO67PPB1 A7 IO18RSB0 C11 IO44RSB0 E15 IO64PPB1 A8 IO28RSB0 C12 GBC0/IO54RSB0 E16 IO66PDB1 A9 IO34RSB0 C13 IO51RSB0 F1 IO166NDB3 A10 IO37RSB0 C14 VMV0 F2 IO168NPB3 A11 IO41RSB0 C15 IO61NPB1 F3 IO167PPB3 A12 IO43RSB0 C16 IO63PDB1 F4 IO169PDB3 A13 GBB1/IO57RSB0 D1 IO171NDB3 F5 VCCIB3 A14 GBA0/IO58RSB0 D2 IO171PDB3 F6 GND A15 GBA1/IO59RSB0 D3 GAC2/IO172PDB3 F7 VCC A16 GND D4 IO06RSB0 F8 VCC B1 GAB2/IO173PDB3 D5 GNDQ F9 VCC B2 GAA2/IO174PDB3 D6 IO10RSB0 F10 VCC B3 GNDQ D7 IO19RSB0 F11 GND B4 GAB1/IO03RSB0 D8 IO26RSB0 F12 VCCIB1 B5 IO13RSB0 D9 IO30RSB0 F13 IO62NDB1 B6 IO14RSB0 D10 IO40RSB0 F14 IO64NPB1 B7 IO21RSB0 D11 IO45RSB0 F15 IO65PPB1 B8 IO27RSB0 D12 GNDQ F16 IO66NDB1 B9 IO32RSB0 D13 IO50RSB0 G1 IO165NDB3 B10 IO38RSB0 D14 GBB2/IO61PPB1 G2 IO165PDB3 B11 IO42RSB0 D15 IO53RSB0 G3 IO168PPB3 B12 GBC1/IO55RSB0 D16 IO63NDB1 G4 GFC1/IO164PPB3 B13 GBB0/IO56RSB0 E1 IO166PDB3 G5 VCCIB3 B14 IO52RSB0 E2 IO167NPB3 G6 VCC B15 GBA2/IO60PDB1 E3 IO172NDB3 G7 GND B16 IO60NDB1 E4 IO169NDB3 G8 GND C1 IO173NDB3 E5 VMV0 G9 GND C2 IO174NDB3 E6 VCCIB0 G10 GND C3 VMV3 E7 VCCIB0 G11 VCC C4 IO07RSB0 E8 IO25RSB0 G12 VCCIB1 R ev i si o n 1 3 4- 23 Package Pin Assignments FG256 FG256 FG256 Pin Number A3P600L Function Pin Number A3P600L Function Pin Number A3P600L Function G13 GCC1/IO69PPB1 K1 GFC2/IO159PDB3 M5 VMV3 G14 IO65NPB1 K2 IO161NPB3 M6 VCCIB2 G15 IO75PDB1 K3 IO156PPB3 M7 VCCIB2 G16 IO75NDB1 K4 IO129RSB2 M8 IO117RSB2 H1 GFB0/IO163NPB3 K5 VCCIB3 M9 IO110RSB2 H2 GFA0/IO162NDB3 K6 VCC M10 VCCIB2 H3 GFB1/IO163PPB3 K7 GND M11 VCCIB2 H4 VCOMPLF K8 GND M12 VMV2 H5 GFC0/IO164NPB3 K9 GND M13 IO94RSB2 H6 VCC K10 GND M14 GDB1/IO87PPB1 H7 GND K11 VCC M15 GDC1/IO86PDB1 H8 GND K12 VCCIB1 M16 IO84NDB1 H9 GND K13 IO73NPB1 N1 IO150NDB3 H10 GND K14 IO80NPB1 N2 IO147PPB3 H11 VCC K15 IO74NPB1 N3 GEC1/IO146PPB3 H12 GCC0/IO69NPB1 K16 IO72NDB1 N4 IO140RSB2 H13 GCB1/IO70PPB1 L1 IO159NDB3 N5 GNDQ H14 GCA0/IO71NPB1 L2 IO156NPB3 N6 GEA2/IO143RSB2 H15 IO67NPB1 L3 IO151PPB3 N7 IO126RSB2 H16 GCB0/IO70NPB1 L4 IO158PSB3 N8 IO120RSB2 J1 GFA2/IO161PPB3 L5 VCCIB3 N9 IO108RSB2 J2 GFA1/IO162PDB3 L6 GND N10 IO103RSB2 J3 VCCPLF L7 VCC N11 IO99RSB2 J4 IO160NDB3 L8 VCC N12 GNDQ J5 GFB2/IO160PDB3 L9 VCC N13 IO92RSB2 J6 VCC L10 VCC N14 VJTAG J7 GND L11 GND N15 GDC0/IO86NDB1 J8 GND L12 VCCIB1 N16 GDA1/IO88PDB1 J9 GND L13 GDB0/IO87NPB1 P1 GEB1/IO145PDB3 J10 GND L14 IO85NDB1 P2 GEB0/IO145NDB3 J11 VCC L15 IO85PDB1 P3 VMV2 J12 GCB2/IO73PPB1 L16 IO84PDB1 P4 IO138RSB2 J13 GCA1/IO71PPB1 M1 IO150PDB3 P5 IO136RSB2 J14 GCC2/IO74PPB1 M2 IO151NPB3 P6 IO131RSB2 J15 IO80PPB1 M3 IO147NPB3 P7 IO124RSB2 J16 GCA2/IO72PDB1 M4 GEC0/IO146NPB3 P8 IO119RSB2 4- 24 R ev i sio n 1 3 ProASIC3L Low Power Flash FPGAs FG256 FG256 Pin Number A3P600L Function Pin Number A3P600L Function P9 IO107RSB2 T12 GDC2/IO91RSB2 P10 IO104RSB2 T13 IO93RSB2 P11 IO97RSB2 T14 GDA2/IO89RSB2 P12 VMV1 T15 TMS P13 TCK T16 GND P14 VPUMP P15 TRST P16 GDA0/IO88NDB1 R1 GEA1/IO144PDB3 R2 GEA0/IO144NDB3 R3 IO139RSB2 R4 GEC2/IO141RSB2 R5 IO132RSB2 R6 IO127RSB2 R7 IO121RSB2 R8 IO114RSB2 R9 IO109RSB2 R10 IO105RSB2 R11 IO98RSB2 R12 IO96RSB2 R13 GDB2/IO90RSB2 R14 TDI R15 GNDQ R16 TDO T1 GND T2 IO137RSB2 T3 FF/GEB2/IO142RSB 2 T4 IO134RSB2 T5 IO125RSB2 T6 IO123RSB2 T7 IO118RSB2 T8 IO115RSB2 T9 IO111RSB2 T10 IO106RSB2 T11 IO102RSB2 R ev i si o n 1 3 4- 25 Package Pin Assignments FG256 FG256 FG256 Pin Number A3P1000L Function Pin Number A3P1000L Function Pin Number A3P1000L Function 4- 26 A1 GND C5 GAC0/IO04RSB0 E9 IO47RSB0 A2 GAA0/IO00RSB0 C6 GAC1/IO05RSB0 E10 VCCIB0 A3 GAA1/IO01RSB0 C7 IO25RSB0 E11 VCCIB0 A4 GAB0/IO02RSB0 C8 IO36RSB0 E12 VMV1 A5 IO16RSB0 C9 IO42RSB0 E13 GBC2/IO80PDB1 A6 IO22RSB0 C10 IO49RSB0 E14 IO83PPB1 A7 IO28RSB0 C11 IO56RSB0 E15 IO86PPB1 A8 IO35RSB0 C12 GBC0/IO72RSB0 E16 IO87PDB1 A9 IO45RSB0 C13 IO62RSB0 F1 IO217NDB3 A10 IO50RSB0 C14 VMV0 F2 IO218NDB3 A11 IO55RSB0 C15 IO78NDB1 F3 IO216PDB3 A12 IO61RSB0 C16 IO81NDB1 F4 IO216NDB3 A13 GBB1/IO75RSB0 D1 IO222NDB3 F5 VCCIB3 A14 GBA0/IO76RSB0 D2 IO222PDB3 F6 GND A15 GBA1/IO77RSB0 D3 GAC2/IO223PDB3 F7 VCC A16 GND D4 IO223NDB3 F8 VCC B1 GAB2/IO224PDB3 D5 GNDQ F9 VCC B2 GAA2/IO225PDB3 D6 IO23RSB0 F10 VCC B3 GNDQ D7 IO29RSB0 F11 GND B4 GAB1/IO03RSB0 D8 IO33RSB0 F12 VCCIB1 B5 IO17RSB0 D9 IO46RSB0 F13 IO83NPB1 B6 IO21RSB0 D10 IO52RSB0 F14 IO86NPB1 B7 IO27RSB0 D11 IO60RSB0 F15 IO90PPB1 B8 IO34RSB0 D12 GNDQ F16 IO87NDB1 B9 IO44RSB0 D13 IO80NDB1 G1 IO210PSB3 B10 IO51RSB0 D14 GBB2/IO79PDB1 G2 IO213NDB3 B11 IO57RSB0 D15 IO79NDB1 G3 IO213PDB3 B12 GBC1/IO73RSB0 D16 IO82NSB1 G4 GFC1/IO209PPB3 B13 GBB0/IO74RSB0 E1 IO217PDB3 G5 VCCIB3 B14 IO71RSB0 E2 IO218PDB3 G6 VCC B15 GBA2/IO78PDB1 E3 IO221NDB3 G7 GND B16 IO81PDB1 E4 IO221PDB3 G8 GND C1 IO224NDB3 E5 VMV0 G9 GND C2 IO225NDB3 E6 VCCIB0 G10 GND C3 VMV3 E7 VCCIB0 G11 VCC C4 IO11RSB0 E8 IO38RSB0 G12 VCCIB1 R ev i sio n 1 3 ProASIC3L Low Power Flash FPGAs FG256 FG256 FG256 Pin Number A3P1000L Function Pin Number A3P1000L Function Pin Number A3P1000L Function G13 GCC1/IO91PPB1 K1 GFC2/IO204PDB3 M5 VMV3 G14 IO90NPB1 K2 IO204NDB3 M6 VCCIB2 G15 IO88PDB1 K3 IO203NDB3 M7 VCCIB2 G16 IO88NDB1 K4 IO203PDB3 M8 IO147RSB2 H1 GFB0/IO208NPB3 K5 VCCIB3 M9 IO136RSB2 H2 GFA0/IO207NDB3 K6 VCC M10 VCCIB2 H3 GFB1/IO208PPB3 K7 GND M11 VCCIB2 H4 VCOMPLF K8 GND M12 VMV2 H5 GFC0/IO209NPB3 K9 GND M13 IO110NDB1 H6 VCC K10 GND M14 GDB1/IO112PPB1 H7 GND K11 VCC M15 GDC1/IO111PDB1 H8 GND K12 VCCIB1 M16 IO107NDB1 H9 GND K13 IO95NPB1 N1 IO194PSB3 H10 GND K14 IO100NPB1 N2 IO192PPB3 H11 VCC K15 IO102NDB1 N3 GEC1/IO190PPB3 H12 GCC0/IO91NPB1 K16 IO102PDB1 N4 IO192NPB3 H13 GCB1/IO92PPB1 L1 IO202NDB3 N5 GNDQ H14 GCA0/IO93NPB1 L2 IO202PDB3 N6 GEA2/IO187RSB2 H15 IO96NPB1 L3 IO196PPB3 N7 IO161RSB2 H16 GCB0/IO92NPB1 L4 IO193PPB3 N8 IO155RSB2 J1 GFA2/IO206PSB3 L5 VCCIB3 N9 IO141RSB2 J2 GFA1/IO207PDB3 L6 GND N10 IO129RSB2 J3 VCCPLF L7 VCC N11 IO124RSB2 J4 IO205NDB3 L8 VCC N12 GNDQ J5 GFB2/IO205PDB3 L9 VCC N13 IO110PDB1 J6 VCC L10 VCC N14 VJTAG J7 GND L11 GND N15 GDC0/IO111NDB1 J8 GND L12 VCCIB1 N16 GDA1/IO113PDB1 J9 GND L13 GDB0/IO112NPB1 P1 GEB1/IO189PDB3 J10 GND L14 IO106NDB1 P2 GEB0/IO189NDB3 J11 VCC L15 IO106PDB1 P3 VMV2 J12 GCB2/IO95PPB1 L16 IO107PDB1 P4 IO179RSB2 J13 GCA1/IO93PPB1 M1 IO197NSB3 P5 IO171RSB2 J14 GCC2/IO96PPB1 M2 IO196NPB3 P6 IO165RSB2 J15 IO100PPB1 M3 IO193NPB3 P7 IO159RSB2 J16 GCA2/IO94PSB1 M4 GEC0/IO190NPB3 P8 IO151RSB2 R ev i si o n 1 3 4- 27 Package Pin Assignments FG256 FG256 Pin Number A3P1000L Function Pin Number A3P1000L Function 4- 28 P9 IO137RSB2 T12 GDC2/IO116RSB2 P10 IO134RSB2 T13 IO120RSB2 P11 IO128RSB2 T14 GDA2/IO114RSB2 P12 VMV1 T15 TMS P13 TCK T16 GND P14 VPUMP P15 TRST P16 GDA0/IO113NDB1 R1 GEA1/IO188PDB3 R2 GEA0/IO188NDB3 R3 IO184RSB2 R4 GEC2/IO185RSB2 R5 IO168RSB2 R6 IO163RSB2 R7 IO157RSB2 R8 IO149RSB2 R9 IO143RSB2 R10 IO138RSB2 R11 IO131RSB2 R12 IO125RSB2 R13 GDB2/IO115RSB2 R14 TDI R15 GNDQ R16 TDO T1 GND T2 IO183RSB2 T3 FF/GEB2/IO186RSB 2 T4 IO172RSB2 T5 IO170RSB2 T6 IO164RSB2 T7 IO158RSB2 T8 IO153RSB2 T9 IO142RSB2 T10 IO135RSB2 T11 IO130RSB2 R ev i sio n 1 3 ProASIC3L Low Power Flash FPGAs FG324 A1 Ball Pad Corner 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V Note: This is the bottom view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.microsemi.com/soc/products/solutions/package/docs.aspx. R ev i si o n 1 3 4- 29 Package Pin Assignments FG324 FG324 FG324 Pin Number A3PE3000L Function Pin Number A3PE3000L Function Pin Number A3PE3000L Function A1 GND B18 IO88PDB2V0 D17 VCCIB2 A2 IO08NDB0V0 C1 IO305NDB7V3 D18 IO90PDB2V1 A3 IO08PDB0V0 C2 IO308NDB7V4 E1 IO303NDB7V3 A4 IO10NDB0V1 C3 GAA2/IO309PPB7V4 E2 GNDQ A5 IO10PDB0V1 C4 GAA1/IO00PPB0V0 E2 GNDQ A6 IO12PDB0V1 C5 VMV0 E3 VMV7 A7 GND C6 IO14NDB0V1 E3 VMV7 A8 IO32NDB0V3 C7 IO18PDB0V2 E4 IO307NPB7V4 A9 IO32PDB0V3 C8 IO40NDB0V4 E5 VCCPLA A10 IO42PPB1V0 C9 IO40PDB0V4 E6 GAB0/IO01NPB0V0 A11 IO52NPB1V1 C10 IO44PDB1V0 E7 VCCIB0 A12 GND C11 IO56NDB1V1 E8 GND A13 IO66NDB1V3 C12 IO64NDB1V2 E9 IO28NDB0V3 A14 IO72NDB1V3 C13 IO64PDB1V2 E10 IO48PDB1V0 A15 IO72PDB1V3 C14 VMV1 E11 GND A16 IO74NDB1V4 C15 GBC0/IO79NDB1V4 E12 VCCIB1 A17 IO74PDB1V4 C16 GBC1/IO79PDB1V4 E13 IO60NPB1V2 A18 GND C17 GBB2/IO83PPB2V0 E14 VCCPLB B1 IO305PDB7V3 C18 IO88NDB2V0 E15 IO82NDB2V0 B2 GAB2/IO308PDB7V4 D1 IO303PDB7V3 E16 VMV2 B3 GAA0/IO00NPB0V0 D2 VCCIB7 E16 VMV2 B4 VCCIB0 D3 GAC2/IO307PPB7V4 E17 GNDQ B5 GNDQ D4 IO309NPB7V4 E17 GNDQ B6 IO12NDB0V1 D5 GAB1/IO01PPB0V0 E18 IO90NDB2V1 B7 IO18NDB0V2 D6 IO14PDB0V1 F1 IO299NDB7V3 B8 VCCIB0 D7 IO24NDB0V2 F2 IO299PDB7V3 B9 IO42NPB1V0 D8 IO24PDB0V2 F3 IO295PDB7V2 B10 IO44NDB1V0 D9 IO28PDB0V3 F4 IO295NDB7V2 B11 VCCIB1 D10 IO48NDB1V0 F5 VCOMPLA B12 IO52PPB1V1 D11 IO56PDB1V1 F6 IO291PPB7V2 B13 IO66PDB1V3 D12 IO60PPB1V2 F7 GAC0/IO02NDB0V0 B14 GNDQ D13 GBB0/IO80NDB1V4 F8 GAC1/IO02PDB0V0 B15 VCCIB1 D14 GBB1/IO80PDB1V4 F9 IO26PDB0V3 B16 GBA0/IO81NDB1V4 D15 GBA2/IO82PDB2V0 F10 IO34PDB0V4 B17 GBA1/IO81PDB1V4 D16 IO83NPB2V0 F11 IO58NDB1V2 4- 30 R ev i sio n 1 3 ProASIC3L Low Power Flash FPGAs FG324 FG324 FG324 Pin Number A3PE3000L Function Pin Number A3PE3000L Function Pin Number A3PE3000L Function F12 IO58PDB1V2 H11 VCC K10 GND F13 IO94PPB2V1 H12 VCC K11 GND F14 VCOMPLB H13 IO98NDB2V2 K12 IO115NDB3V0 F15 GBC2/IO84PDB2V0 H14 GND K13 GCB2/IO116PDB3V0 F16 IO84NDB2V0 H15 GCB1/IO113PDB2V3 K14 IO116NDB3V0 F17 IO92NDB2V1 H16 GCC1/IO112PPB2V3 K15 GCC2/IO117PDB3V0 F18 IO92PDB2V1 H17 VCCIB2 K16 VCCPLC G1 GND H18 IO108PDB2V3 K17 IO124NPB3V1 G2 IO287PDB7V1 J1 IO267NDB6V4 K18 IO120PPB3V0 G3 IO287NDB7V1 J2 GFA0/IO273NDB6V4 L1 IO263NDB6V3 G4 IO283PPB7V1 J3 VCOMPLF L2 VCCIB6 G5 VCCIB7 J4 GFA2/IO272PDB6V4 L3 IO259PDB6V3 G6 IO279PDB7V0 J5 GFB0/IO274NPB7V0 L4 IO259NDB6V3 G7 IO291NPB7V2 J6 GFC0/IO275NDB7V0 L5 GND G8 VCC J7 GFC1/IO275PDB7V0 L6 IO270NPB6V4 G9 IO26NDB0V3 J8 GND L7 VCC G10 IO34NDB0V4 J9 GND L8 VCC G11 VCC J10 GND L9 GND G12 IO94NPB2V1 J11 GND L10 GND G13 IO98PDB2V2 J12 GCA2/IO115PDB3V0 L11 VCC G14 VCCIB2 J13 GCA1/IO114PDB3V0 L12 VCC G15 GCC0/IO112NPB2V3 J14 GCA0/IO114NDB3V0 L13 IO132PDB3V2 G16 IO104PDB2V2 J15 GCB0/IO113NDB2V3 L14 GND G17 IO104NDB2V2 J16 VCOMPLC L15 IO117NDB3V0 G18 GND J17 IO120NPB3V0 L16 IO128NPB3V1 H1 IO267PDB6V4 J18 IO108NDB2V3 L17 VCCIB3 H2 VCCIB7 K1 IO263PDB6V3 L18 IO124PPB3V1 H3 IO283NPB7V1 K2 GFA1/IO273PDB6V4 M1 GND H4 GFB1/IO274PPB7V0 K3 VCCPLF M2 IO255PDB6V2 H5 GND K4 IO272NDB6V4 M3 IO255NDB6V2 H6 IO279NDB7V0 K5 GFC2/IO270PPB6V4 M4 IO251PPB6V2 H7 VCC K6 GFB2/IO271PDB6V4 M5 VCCIB6 H8 VCC K7 IO271NDB6V4 M6 GEB0/IO235NDB6V0 H9 GND K8 GND M7 GEB1/IO235PDB6V0 H10 GND K9 GND M8 VCC R ev i si o n 1 3 4- 31 Package Pin Assignments FG324 FG324 FG324 Pin Number A3PE3000L Function Pin Number A3PE3000L Function Pin Number A3PE3000L Function M9 IO192PPB4V4 P6 IO214PDB5V2 T5 VMV5 M10 IO154NPB4V0 P7 VCCIB5 T6 IO208NDB5V1 M11 VCC P8 GND T7 IO202NDB5V1 M12 GDA0/IO153NPB3V4 P9 IO174NDB4V2 T8 IO194NDB5V0 M13 IO132NDB3V2 P10 IO170NDB4V2 T9 IO186NDB4V4 M14 VCCIB3 P11 GND T10 IO178NDB4V3 M15 IO134NDB3V2 P12 VCCIB4 T11 IO166NPB4V1 M16 IO134PDB3V2 P13 IO155NPB4V0 T12 IO164NDB4V1 M17 IO128PPB3V1 P14 VCCPLD T13 IO156NDB4V0 M18 GND P15 VJTAG T14 VMV4 N1 IO247NDB6V1 P16 GDC0/IO151NDB3V4 T15 TDI N2 IO247PDB6V1 P17 GDC1/IO151PDB3V4 T16 GNDQ N3 IO251NPB6V2 P18 IO142PDB3V3 T16 GNDQ N4 GEC0/IO236NDB6V0 R1 IO245NDB6V1 T17 TDO N5 VCOMPLE R2 VCCIB6 T18 IO146PDB3V4 N6 IO212NDB5V2 R3 GEA1/IO234PPB6V0 U1 IO241NDB6V0 N7 IO212PDB5V2 R4 IO232NDB5V4 U2 GEA2/IO233PPB5V4 N8 IO192NPB4V4 R5 FF/GEB2/IO232PDB5V4 U3 GEC2/IO231PPB5V4 N9 IO174PDB4V2 R6 IO214NDB5V2 U4 VCCIB5 N10 IO170PDB4V2 R7 IO202PDB5V1 U5 GNDQ N11 GDA2/IO154PPB4V0 R8 IO194PDB5V0 U6 IO208PDB5V1 N12 GDB2/IO155PPB4V0 R9 IO186PDB4V4 U7 IO198PPB5V0 N13 GDA1/IO153PPB3V4 R10 IO178PDB4V3 U8 VCCIB5 N14 VCOMPLD R11 IO168NSB4V1 U9 IO182NPB4V3 N15 GDB0/IO152NDB3V4 R12 IO164PDB4V1 U10 IO180NPB4V3 N16 GDB1/IO152PDB3V4 R13 GDC2/IO156PDB4V0 U11 VCCIB4 N17 IO138NDB3V3 R14 TCK U12 IO166PPB4V1 N18 IO138PDB3V3 R15 VPUMP U13 IO162PDB4V1 P1 IO245PDB6V1 R16 TRST U14 GNDQ P2 GNDQ R17 VCCIB3 U15 VCCIB4 P2 GNDQ R18 IO142NDB3V3 U16 TMS P3 VMV6 T1 IO241PDB6V0 U17 VMV3 P3 VMV6 T2 GEA0/IO234NPB6V0 U17 VMV3 P4 GEC1/IO236PDB6V0 T3 IO233NPB5V4 U18 IO146NDB3V4 P5 VCCPLE T4 IO231NPB5V4 V1 GND 4- 32 R ev i sio n 1 3 ProASIC3L Low Power Flash FPGAs FG324 Pin Number A3PE3000L Function V2 IO218NDB5V3 V3 IO218PDB5V3 V4 IO206NDB5V1 V5 IO206PDB5V1 V6 IO198NPB5V0 V7 GND V8 IO190NDB4V4 V9 IO190PDB4V4 V10 IO182PPB4V3 V11 IO180PPB4V3 V12 GND V13 IO162NDB4V1 V14 IO160NDB4V0 V15 IO160PDB4V0 V16 IO158NDB4V0 V17 IO158PDB4V0 V18 GND R ev i si o n 1 3 4- 33 Package Pin Assignments FG484 A1 Ball Pad Corner 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y AA AB Note: This is the bottom view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.microsemi.com/soc/products/solutions/package/docs.aspx. 4- 34 R ev i sio n 1 3 ProASIC3L Low Power Flash FPGAs FG484 FG484 FG484 Pin Number A3P600L Function Pin Number A3P600L Function Pin Number A3P600L Function A1 GND AA15 NC B7 IO12RSB0 A2 GND AA16 IO101RSB2 B8 NC A3 VCCIB0 AA17 NC B9 NC A4 NC AA18 NC B10 IO17RSB0 A5 NC AA19 NC B11 NC A6 IO09RSB0 AA20 NC B12 NC A7 IO15RSB0 AA21 VCCIB1 B13 IO36RSB0 A8 NC AA22 GND B14 NC A9 NC AB1 GND B15 NC A10 IO22RSB0 AB2 GND B16 IO47RSB0 A11 IO23RSB0 AB3 VCCIB2 B17 IO49RSB0 A12 IO29RSB0 AB4 NC B18 NC A13 IO35RSB0 AB5 NC B19 NC A14 NC AB6 IO130RSB2 B20 NC A15 NC AB7 IO128RSB2 B21 VCCIB1 A16 IO46RSB0 AB8 IO122RSB2 B22 GND A17 IO48RSB0 AB9 IO116RSB2 C1 VCCIB3 A18 NC AB10 NC C2 NC A19 NC AB11 NC C3 NC A20 VCCIB0 AB12 IO113RSB2 C4 NC A21 GND AB13 IO112RSB2 C5 GND A22 GND AB14 NC C6 NC AA1 GND AB15 NC C7 NC AA2 VCCIB3 AB16 IO100RSB2 C8 VCC AA3 NC AB17 IO95RSB2 C9 VCC AA4 NC AB18 NC C10 NC AA5 NC AB19 NC C11 NC AA6 IO135RSB2 AB20 VCCIB2 C12 NC AA7 IO133RSB2 AB21 GND C13 NC AA8 NC AB22 GND C14 VCC AA9 NC B1 GND C15 VCC AA10 NC B2 VCCIB3 C16 NC AA11 NC B3 NC C17 NC AA12 NC B4 NC C18 GND AA13 NC B5 NC C19 NC AA14 NC B6 IO08RSB0 C20 NC R ev i si o n 1 3 4- 35 Package Pin Assignments FG484 FG484 FG484 Pin Number A3P600L Function Pin Number A3P600L Function Pin Number A3P600L Function C21 NC E13 IO38RSB0 G5 IO171PDB3 C22 VCCIB1 E14 IO42RSB0 G6 GAC2/IO172PDB3 D1 NC E15 GBC1/IO55RSB0 G7 IO06RSB0 D2 NC E16 GBB0/IO56RSB0 G8 GNDQ D3 NC E17 IO52RSB0 G9 IO10RSB0 D4 GND E18 GBA2/IO60PDB1 G10 IO19RSB0 D5 GAA0/IO00RSB0 E19 IO60NDB1 G11 IO26RSB0 D6 GAA1/IO01RSB0 E20 GND G12 IO30RSB0 D7 GAB0/IO02RSB0 E21 NC G13 IO40RSB0 D8 IO11RSB0 E22 NC G14 IO45RSB0 D9 IO16RSB0 F1 NC G15 GNDQ D10 IO18RSB0 F2 NC G16 IO50RSB0 D11 IO28RSB0 F3 NC G17 GBB2/IO61PPB1 D12 IO34RSB0 F4 IO173NDB3 G18 IO53RSB0 D13 IO37RSB0 F5 IO174NDB3 G19 IO63NDB1 D14 IO41RSB0 F6 VMV3 G20 NC D15 IO43RSB0 F7 IO07RSB0 G21 NC D16 GBB1/IO57RSB0 F8 GAC0/IO04RSB0 G22 NC D17 GBA0/IO58RSB0 F9 GAC1/IO05RSB0 H1 NC D18 GBA1/IO59RSB0 F10 IO20RSB0 H2 NC D19 GND F11 IO24RSB0 H3 VCC D20 NC F12 IO33RSB0 H4 IO166PDB3 D21 NC F13 IO39RSB0 H5 IO167NPB3 D22 NC F14 IO44RSB0 H6 IO172NDB3 E1 NC F15 GBC0/IO54RSB0 H7 IO169NDB3 E2 NC F16 IO51RSB0 H8 VMV0 E3 GND F17 VMV0 H9 VCCIB0 E4 GAB2/IO173PDB3 F18 IO61NPB1 H10 VCCIB0 E5 GAA2/IO174PDB3 F19 IO63PDB1 H11 IO25RSB0 E6 GNDQ F20 NC H12 IO31RSB0 E7 GAB1/IO03RSB0 F21 NC H13 VCCIB0 E8 IO13RSB0 F22 NC H14 VCCIB0 E9 IO14RSB0 G1 IO170NDB3 H15 VMV1 E10 IO21RSB0 G2 IO170PDB3 H16 GBC2/IO62PDB1 E11 IO27RSB0 G3 NC H17 IO67PPB1 E12 IO32RSB0 G4 IO171NDB3 H18 IO64PPB1 4- 36 R ev i sio n 1 3 ProASIC3L Low Power Flash FPGAs FG484 FG484 FG484 Pin Number A3P600L Function Pin Number A3P600L Function Pin Number A3P600L Function H19 IO66PDB1 K11 GND M3 IO158NPB3 H20 VCC K12 GND M4 GFA2/IO161PPB3 H21 NC K13 GND M5 GFA1/IO162PDB3 H22 NC K14 VCC M6 VCCPLF J1 NC K15 VCCIB1 M7 IO160NDB3 J2 NC K16 GCC1/IO69PPB1 M8 GFB2/IO160PDB3 J3 NC K17 IO65NPB1 M9 VCC J4 IO166NDB3 K18 IO75PDB1 M10 GND J5 IO168NPB3 K19 IO75NDB1 M11 GND J6 IO167PPB3 K20 NC M12 GND J7 IO169PDB3 K21 IO76NDB1 M13 GND J8 VCCIB3 K22 IO76PDB1 M14 VCC J9 GND L1 NC M15 GCB2/IO73PPB1 J10 VCC L2 IO155PDB3 M16 GCA1/IO71PPB1 J11 VCC L3 NC M17 GCC2/IO74PPB1 J12 VCC L4 GFB0/IO163NPB3 M18 IO80PPB1 J13 VCC L5 GFA0/IO162NDB3 M19 GCA2/IO72PDB1 J14 GND L6 GFB1/IO163PPB3 M20 IO79PPB1 J15 VCCIB1 L7 VCOMPLF M21 IO78PPB1 J16 IO62NDB1 L8 GFC0/IO164NPB3 M22 NC J17 IO64NPB1 L9 VCC N1 IO154NDB3 J18 IO65PPB1 L10 GND N2 IO154PDB3 J19 IO66NDB1 L11 GND N3 NC J20 NC L12 GND N4 GFC2/IO159PDB3 J21 IO68PDB1 L13 GND N5 IO161NPB3 J22 IO68NDB1 L14 VCC N6 IO156PPB3 K1 IO157PDB3 L15 GCC0/IO69NPB1 N7 IO129RSB2 K2 IO157NDB3 L16 GCB1/IO70PPB1 N8 VCCIB3 K3 NC L17 GCA0/IO71NPB1 N9 VCC K4 IO165NDB3 L18 IO67NPB1 N10 GND K5 IO165PDB3 L19 GCB0/IO70NPB1 N11 GND K6 IO168PPB3 L20 IO77PDB1 N12 GND K7 GFC1/IO164PPB3 L21 IO77NDB1 N13 GND K8 VCCIB3 L22 IO78NPB1 N14 VCC K9 VCC M1 NC N15 VCCIB1 K10 GND M2 IO155NDB3 N16 IO73NPB1 R ev i si o n 1 3 4- 37 Package Pin Assignments FG484 FG484 FG484 Pin Number A3P600L Function Pin Number A3P600L Function Pin Number A3P600L Function N17 IO80NPB1 R9 VCCIB2 U1 IO149PDB3 N18 IO74NPB1 R10 VCCIB2 U2 IO149NDB3 N19 IO72NDB1 R11 IO117RSB2 U3 NC N20 NC R12 IO110RSB2 U4 GEB1/IO145PDB3 N21 IO79NPB1 R13 VCCIB2 U5 GEB0/IO145NDB3 N22 NC R14 VCCIB2 U6 VMV2 P1 NC R15 VMV2 U7 IO138RSB2 P2 IO153PDB3 R16 IO94RSB2 U8 IO136RSB2 P3 IO153NDB3 R17 GDB1/IO87PPB1 U9 IO131RSB2 P4 IO159NDB3 R18 GDC1/IO86PDB1 U10 IO124RSB2 P5 IO156NPB3 R19 IO84NDB1 U11 IO119RSB2 P6 IO151PPB3 R20 VCC U12 IO107RSB2 P7 IO158PPB3 R21 IO81NDB1 U13 IO104RSB2 P8 VCCIB3 R22 IO82PDB1 U14 IO97RSB2 P9 GND T1 IO152PDB3 U15 VMV1 P10 VCC T2 IO152NDB3 U16 TCK P11 VCC T3 NC U17 VPUMP P12 VCC T4 IO150NDB3 U18 TRST P13 VCC T5 IO147PPB3 U19 GDA0/IO88NDB1 P14 GND T6 GEC1/IO146PPB3 U20 NC P15 VCCIB1 T7 IO140RSB2 U21 IO83NDB1 P16 GDB0/IO87NPB1 T8 GNDQ U22 NC P17 IO85NDB1 T9 GEA2/IO143RSB2 V1 NC P18 IO85PDB1 T10 IO126RSB2 V2 NC P19 IO84PDB1 T11 IO120RSB2 V3 GND P20 NC T12 IO108RSB2 V4 GEA1/IO144PDB3 P21 IO81PDB1 T13 IO103RSB2 V5 GEA0/IO144NDB3 P22 NC T14 IO99RSB2 V6 IO139RSB2 R1 NC T15 GNDQ V7 GEC2/IO141RSB2 R2 NC T16 IO92RSB2 V8 IO132RSB2 R3 VCC T17 VJTAG V9 IO127RSB2 R4 IO150PDB3 T18 GDC0/IO86NDB1 V10 IO121RSB2 R5 IO151NPB3 T19 GDA1/IO88PDB1 V11 IO114RSB2 R6 IO147NPB3 T20 NC V12 IO109RSB2 R7 GEC0/IO146NPB3 T21 IO83PDB1 V13 IO105RSB2 R8 VMV3 T22 IO82NDB1 V14 IO98RSB2 4- 38 R ev i sio n 1 3 ProASIC3L Low Power Flash FPGAs FG484 FG484 Pin Number A3P600L Function Pin Number A3P600L Function V15 IO96RSB2 Y7 NC V16 GDB2/IO90RSB2 Y8 VCC V17 TDI Y9 VCC V18 GNDQ Y10 NC V19 TDO Y11 NC V20 GND Y12 NC V21 NC Y13 NC V22 NC Y14 VCC W1 NC Y15 VCC W2 IO148PDB3 Y16 NC W3 NC Y17 NC W4 GND Y18 GND W5 IO137RSB2 Y19 NC W6 FF/GEB2/IO142RSB2 Y20 NC W7 IO134RSB2 Y21 NC W8 IO125RSB2 Y22 VCCIB1 W9 IO123RSB2 W10 IO118RSB2 W11 IO115RSB2 W12 IO111RSB2 W13 IO106RSB2 W14 IO102RSB2 W15 GDC2/IO91RSB2 W16 IO93RSB2 W17 GDA2/IO89RSB2 W18 TMS W19 GND W20 NC W21 NC W22 NC Y1 VCCIB3 Y2 IO148NDB3 Y3 NC Y4 NC Y5 GND Y6 NC R ev i si o n 1 3 4- 39 Package Pin Assignments FG484 FG484 FG484 Pin Number A3P1000L Function Pin Number A3P1000L Function Pin Number A3P1000L Function 4- 40 A1 GND AA15 NC B7 IO15RSB0 A2 GND AA16 IO122RSB2 B8 IO19RSB0 A3 VCCIB0 AA17 IO119RSB2 B9 IO24RSB0 A4 IO07RSB0 AA18 IO117RSB2 B10 IO31RSB0 A5 IO09RSB0 AA19 NC B11 IO39RSB0 A6 IO13RSB0 AA20 NC B12 IO48RSB0 A7 IO18RSB0 AA21 VCCIB1 B13 IO54RSB0 A8 IO20RSB0 AA22 GND B14 IO58RSB0 A9 IO26RSB0 AB1 GND B15 IO63RSB0 A10 IO32RSB0 AB2 GND B16 IO66RSB0 A11 IO40RSB0 AB3 VCCIB2 B17 IO68RSB0 A12 IO41RSB0 AB4 IO180RSB2 B18 IO70RSB0 A13 IO53RSB0 AB5 IO176RSB2 B19 NC A14 IO59RSB0 AB6 IO173RSB2 B20 NC A15 IO64RSB0 AB7 IO167RSB2 B21 VCCIB1 A16 IO65RSB0 AB8 IO162RSB2 B22 GND A17 IO67RSB0 AB9 IO156RSB2 C1 VCCIB3 A18 IO69RSB0 AB10 IO150RSB2 C2 IO220PDB3 A19 NC AB11 IO145RSB2 C3 NC A20 VCCIB0 AB12 IO144RSB2 C4 NC A21 GND AB13 IO132RSB2 C5 GND A22 GND AB14 IO127RSB2 C6 IO10RSB0 AA1 GND AB15 IO126RSB2 C7 IO14RSB0 AA2 VCCIB3 AB16 IO123RSB2 C8 VCC AA3 NC AB17 IO121RSB2 C9 VCC AA4 IO181RSB2 AB18 IO118RSB2 C10 IO30RSB0 AA5 IO178RSB2 AB19 NC C11 IO37RSB0 AA6 IO175RSB2 AB20 VCCIB2 C12 IO43RSB0 AA7 IO169RSB2 AB21 GND C13 NC AA8 IO166RSB2 AB22 GND C14 VCC AA9 IO160RSB2 B1 GND C15 VCC AA10 IO152RSB2 B2 VCCIB3 C16 NC AA11 IO146RSB2 B3 NC C17 NC AA12 IO139RSB2 B4 IO06RSB0 C18 GND AA13 IO133RSB2 B5 IO08RSB0 C19 NC AA14 NC B6 IO12RSB0 C20 NC R ev i sio n 1 3 ProASIC3L Low Power Flash FPGAs FG484 FG484 FG484 Pin Number A3P1000L Function Pin Number A3P1000L Function Pin Number A3P1000L Function C21 NC E13 IO51RSB0 G5 IO222PDB3 C22 VCCIB1 E14 IO57RSB0 G6 GAC2/IO223PDB3 D1 IO219PDB3 E15 GBC1/IO73RSB0 G7 IO223NDB3 D2 IO220NDB3 E16 GBB0/IO74RSB0 G8 GNDQ D3 NC E17 IO71RSB0 G9 IO23RSB0 D4 GND E18 GBA2/IO78PDB1 G10 IO29RSB0 D5 GAA0/IO00RSB0 E19 IO81PDB1 G11 IO33RSB0 D6 GAA1/IO01RSB0 E20 GND G12 IO46RSB0 D7 GAB0/IO02RSB0 E21 NC G13 IO52RSB0 D8 IO16RSB0 E22 IO84PDB1 G14 IO60RSB0 D9 IO22RSB0 F1 NC G15 GNDQ D10 IO28RSB0 F2 IO215PDB3 G16 IO80NDB1 D11 IO35RSB0 F3 IO215NDB3 G17 GBB2/IO79PDB1 D12 IO45RSB0 F4 IO224NDB3 G18 IO79NDB1 D13 IO50RSB0 F5 IO225NDB3 G19 IO82NPB1 D14 IO55RSB0 F6 VMV3 G20 IO85PDB1 D15 IO61RSB0 F7 IO11RSB0 G21 IO85NDB1 D16 GBB1/IO75RSB0 F8 GAC0/IO04RSB0 G22 NC D17 GBA0/IO76RSB0 F9 GAC1/IO05RSB0 H1 NC D18 GBA1/IO77RSB0 F10 IO25RSB0 H2 NC D19 GND F11 IO36RSB0 H3 VCC D20 NC F12 IO42RSB0 H4 IO217PDB3 D21 NC F13 IO49RSB0 H5 IO218PDB3 D22 NC F14 IO56RSB0 H6 IO221NDB3 E1 IO219NDB3 F15 GBC0/IO72RSB0 H7 IO221PDB3 E2 NC F16 IO62RSB0 H8 VMV0 E3 GND F17 VMV0 H9 VCCIB0 E4 GAB2/IO224PDB3 F18 IO78NDB1 H10 VCCIB0 E5 GAA2/IO225PDB3 F19 IO81NDB1 H11 IO38RSB0 E6 GNDQ F20 IO82PPB1 H12 IO47RSB0 E7 GAB1/IO03RSB0 F21 NC H13 VCCIB0 E8 IO17RSB0 F22 IO84NDB1 H14 VCCIB0 E9 IO21RSB0 G1 IO214NDB3 H15 VMV1 E10 IO27RSB0 G2 IO214PDB3 H16 GBC2/IO80PDB1 E11 IO34RSB0 G3 NC H17 IO83PPB1 E12 IO44RSB0 G4 IO222NDB3 H18 IO86PPB1 R ev i si o n 1 3 4- 41 Package Pin Assignments FG484 FG484 FG484 Pin Number A3P1000L Function Pin Number A3P1000L Function Pin Number A3P1000L Function 4- 42 H19 IO87PDB1 K11 GND M3 IO206NDB3 H20 VCC K12 GND M4 GFA2/IO206PDB3 H21 NC K13 GND M5 GFA1/IO207PDB3 H22 NC K14 VCC M6 VCCPLF J1 IO212NDB3 K15 VCCIB1 M7 IO205NDB3 J2 IO212PDB3 K16 GCC1/IO91PPB1 M8 GFB2/IO205PDB3 J3 NC K17 IO90NPB1 M9 VCC J4 IO217NDB3 K18 IO88PDB1 M10 GND J5 IO218NDB3 K19 IO88NDB1 M11 GND J6 IO216PDB3 K20 IO94NPB1 M12 GND J7 IO216NDB3 K21 IO98NDB1 M13 GND J8 VCCIB3 K22 IO98PDB1 M14 VCC J9 GND L1 NC M15 GCB2/IO95PPB1 J10 VCC L2 IO200PDB3 M16 GCA1/IO93PPB1 J11 VCC L3 IO210NPB3 M17 GCC2/IO96PPB1 J12 VCC L4 GFB0/IO208NPB3 M18 IO100PPB1 J13 VCC L5 GFA0/IO207NDB3 M19 GCA2/IO94PPB1 J14 GND L6 GFB1/IO208PPB3 M20 IO101PPB1 J15 VCCIB1 L7 VCOMPLF M21 IO99PPB1 J16 IO83NPB1 L8 GFC0/IO209NPB3 M22 NC J17 IO86NPB1 L9 VCC N1 IO201NDB3 J18 IO90PPB1 L10 GND N2 IO201PDB3 J19 IO87NDB1 L11 GND N3 NC J20 NC L12 GND N4 GFC2/IO204PDB3 J21 IO89PDB1 L13 GND N5 IO204NDB3 J22 IO89NDB1 L14 VCC N6 IO203NDB3 K1 IO211PDB3 L15 GCC0/IO91NPB1 N7 IO203PDB3 K2 IO211NDB3 L16 GCB1/IO92PPB1 N8 VCCIB3 K3 NC L17 GCA0/IO93NPB1 N9 VCC K4 IO210PPB3 L18 IO96NPB1 N10 GND K5 IO213NDB3 L19 GCB0/IO92NPB1 N11 GND K6 IO213PDB3 L20 IO97PDB1 N12 GND K7 GFC1/IO209PPB3 L21 IO97NDB1 N13 GND K8 VCCIB3 L22 IO99NPB1 N14 VCC K9 VCC M1 NC N15 VCCIB1 K10 GND M2 IO200NDB3 N16 IO95NPB1 R ev i sio n 1 3 ProASIC3L Low Power Flash FPGAs FG484 FG484 FG484 Pin Number A3P1000L Function Pin Number A3P1000L Function Pin Number A3P1000L Function N17 IO100NPB1 R9 VCCIB2 U1 IO195PDB3 N18 IO102NDB1 R10 VCCIB2 U2 IO195NDB3 N19 IO102PDB1 R11 IO147RSB2 U3 IO194NPB3 N20 NC R12 IO136RSB2 U4 GEB1/IO189PDB3 N21 IO101NPB1 R13 VCCIB2 U5 GEB0/IO189NDB3 N22 IO103PDB1 R14 VCCIB2 U6 VMV2 P1 NC R15 VMV2 U7 IO179RSB2 P2 IO199PDB3 R16 IO110NDB1 U8 IO171RSB2 P3 IO199NDB3 R17 GDB1/IO112PPB1 U9 IO165RSB2 P4 IO202NDB3 R18 GDC1/IO111PDB1 U10 IO159RSB2 P5 IO202PDB3 R19 IO107NDB1 U11 IO151RSB2 P6 IO196PPB3 R20 VCC U12 IO137RSB2 P7 IO193PPB3 R21 IO104NDB1 U13 IO134RSB2 P8 VCCIB3 R22 IO105PDB1 U14 IO128RSB2 P9 GND T1 IO198PDB3 U15 VMV1 P10 VCC T2 IO198NDB3 U16 TCK P11 VCC T3 NC U17 VPUMP P12 VCC T4 IO194PPB3 U18 TRST P13 VCC T5 IO192PPB3 U19 GDA0/IO113NDB1 P14 GND T6 GEC1/IO190PPB3 U20 NC P15 VCCIB1 T7 IO192NPB3 U21 IO108NDB1 P16 GDB0/IO112NPB1 T8 GNDQ U22 IO109PDB1 P17 IO106NDB1 T9 GEA2/IO187RSB2 V1 NC P18 IO106PDB1 T10 IO161RSB2 V2 NC P19 IO107PDB1 T11 IO155RSB2 V3 GND P20 NC T12 IO141RSB2 V4 GEA1/IO188PDB3 P21 IO104PDB1 T13 IO129RSB2 V5 GEA0/IO188NDB3 P22 IO103NDB1 T14 IO124RSB2 V6 IO184RSB2 R1 NC T15 GNDQ V7 GEC2/IO185RSB2 R2 IO197PPB3 T16 IO110PDB1 V8 IO168RSB2 R3 VCC T17 VJTAG V9 IO163RSB2 R4 IO197NPB3 T18 GDC0/IO111NDB1 V10 IO157RSB2 R5 IO196NPB3 T19 GDA1/IO113PDB1 V11 IO149RSB2 R6 IO193NPB3 T20 NC V12 IO143RSB2 R7 GEC0/IO190NPB3 T21 IO108PDB1 V13 IO138RSB2 R8 VMV3 T22 IO105NDB1 V14 IO131RSB2 R ev i si o n 1 3 4- 43 Package Pin Assignments FG484 FG484 Pin Number A3P1000L Function Pin Number A3P1000L Function 4- 44 V15 IO125RSB2 Y7 IO174RSB2 V16 GDB2/IO115RSB2 Y8 VCC V17 TDI Y9 VCC V18 GNDQ Y10 IO154RSB2 V19 TDO Y11 IO148RSB2 V20 GND Y12 IO140RSB2 V21 NC Y13 NC V22 IO109NDB1 Y14 VCC W1 NC Y15 VCC W2 IO191PDB3 Y16 NC W3 NC Y17 NC W4 GND Y18 GND W5 IO183RSB2 Y19 NC W6 FF/GEB2/IO186RSB2 Y20 NC W7 IO172RSB2 Y21 NC W8 IO170RSB2 Y22 VCCIB1 W9 IO164RSB2 W10 IO158RSB2 W11 IO153RSB2 W12 IO142RSB2 W13 IO135RSB2 W14 IO130RSB2 W15 GDC2/IO116RSB2 W16 IO120RSB2 W17 GDA2/IO114RSB2 W18 TMS W19 GND W20 NC W21 NC W22 NC Y1 VCCIB3 Y2 IO191NDB3 Y3 NC Y4 IO182RSB2 Y5 GND Y6 IO177RSB2 R ev i sio n 1 3 ProASIC3L Low Power Flash FPGAs FG484 FG484 FG484 Pin Number A3PE3000L Function Pin Number A3PE3000L Function Pin Number A3PE3000L Function A1 GND AA14 IO170NDB4V2 B5 IO08PDB0V0 A2 GND AA15 IO170PDB4V2 B6 IO14NDB0V1 A3 VCCIB0 AA16 IO166NDB4V1 B7 IO14PDB0V1 A4 IO10NDB0V1 AA17 IO166PDB4V1 B8 IO18NDB0V2 A5 IO10PDB0V1 AA18 IO160NDB4V0 B9 IO24NDB0V2 A6 IO16NDB0V1 AA19 IO160PDB4V0 B10 IO34PDB0V4 A7 IO16PDB0V1 AA20 IO158NPB4V0 B11 IO40PDB0V4 A8 IO18PDB0V2 AA21 VCCIB3 B12 IO46NDB1V0 A9 IO24PDB0V2 AA22 GND B13 IO54NDB1V1 A10 IO28NDB0V3 AB1 GND B14 IO62NDB1V2 A11 IO28PDB0V3 AB2 GND B15 IO62PDB1V2 A12 IO46PDB1V0 AB3 VCCIB5 B16 IO68NDB1V3 A13 IO54PDB1V1 AB4 IO216NDB5V2 B17 IO68PDB1V3 A14 IO56NDB1V1 AB5 IO216PDB5V2 B18 IO72PDB1V3 A15 IO56PDB1V1 AB6 IO210NDB5V2 B19 IO74PDB1V4 A16 IO64NDB1V2 AB7 IO210PDB5V2 B20 IO76NPB1V4 A17 IO64PDB1V2 AB8 IO208NDB5V1 B21 VCCIB2 A18 IO72NDB1V3 AB9 IO208PDB5V1 B22 GND A19 IO74NDB1V4 AB10 IO197NDB5V0 C1 VCCIB7 A20 VCCIB1 AB11 IO197PDB5V0 C2 IO303PDB7V3 A21 GND AB12 IO174NDB4V2 C3 IO305PDB7V3 A22 GND AB13 IO174PDB4V2 C4 IO06NPB0V0 AA1 GND AB14 IO172NDB4V2 C5 GND AA2 VCCIB6 AB15 IO172PDB4V2 C6 IO12NDB0V1 AA3 IO228PDB5V4 AB16 IO168NDB4V1 C7 IO12PDB0V1 AA4 IO224PDB5V3 AB17 IO168PDB4V1 C8 VCC AA5 IO218NDB5V3 AB18 IO162NDB4V1 C9 VCC AA6 IO218PDB5V3 AB19 IO162PDB4V1 C10 IO34NDB0V4 AA7 IO212NDB5V2 AB20 VCCIB4 C11 IO40NDB0V4 AA8 IO212PDB5V2 AB21 GND C12 IO48NDB1V0 AA9 IO198PDB5V0 AB22 GND C13 IO48PDB1V0 AA10 IO198NDB5V0 B1 GND C14 VCC AA11 IO188PPB4V4 B2 VCCIB7 C15 VCC AA12 IO180NDB4V3 B3 IO06PPB0V0 C16 IO70NDB1V3 AA13 IO180PDB4V3 B4 IO08NDB0V0 C17 IO70PDB1V3 R ev i si o n 1 3 4- 45 Package Pin Assignments FG484 FG484 FG484 Pin Number A3PE3000L Function Pin Number A3PE3000L Function Pin Number A3PE3000L Function C18 GND E9 IO22NDB0V2 F22 IO98NDB2V2 C19 IO76PPB1V4 E10 IO30NDB0V3 G1 IO289NDB7V1 C20 IO88NDB2V0 E11 IO38PDB0V4 G2 IO289PDB7V1 C21 IO94PPB2V1 E12 IO44NDB1V0 G3 IO291PPB7V2 C22 VCCIB2 E13 IO58NDB1V2 G4 IO295PDB7V2 D1 IO293PDB7V2 E14 IO58PDB1V2 G5 IO297PDB7V2 D2 IO303NDB7V3 E15 GBC1/IO79PDB1V4 G6 GAC2/IO307PDB7V4 D3 IO305NDB7V3 E16 GBB0/IO80NDB1V4 G7 VCOMPLA D4 GND E17 GNDQ G8 GNDQ D5 GAA0/IO00NDB0V0 E18 GBA2/IO82PDB2V0 G9 IO26NDB0V3 D6 GAA1/IO00PDB0V0 E19 IO86NDB2V0 G10 IO26PDB0V3 D7 GAB0/IO01NDB0V0 E20 GND G11 IO36PDB0V4 D8 IO20PDB0V2 E21 IO90NDB2V1 G12 IO42PDB1V0 D9 IO22PDB0V2 E22 IO98PDB2V2 G13 IO50PDB1V1 D10 IO30PDB0V3 F1 IO299NPB7V3 G14 IO60NDB1V2 D11 IO38NDB0V4 F2 IO301NDB7V3 G15 GNDQ D12 IO52NDB1V1 F3 IO301PDB7V3 G16 VCOMPLB D13 IO52PDB1V1 F4 IO308NDB7V4 G17 GBB2/IO83PDB2V0 D14 IO66NDB1V3 F5 IO309NDB7V4 G18 IO92PDB2V1 D15 IO66PDB1V3 F6 VMV7 G19 IO92NDB2V1 D16 GBB1/IO80PDB1V4 F7 VCCPLA G20 IO102PDB2V2 D17 GBA0/IO81NDB1V4 F8 GAC0/IO02NDB0V0 G21 IO102NDB2V2 D18 GBA1/IO81PDB1V4 F9 GAC1/IO02PDB0V0 G22 IO105NDB2V2 D19 GND F10 IO32NDB0V3 H1 IO286PSB7V1 D20 IO88PDB2V0 F11 IO32PDB0V3 H2 IO291NPB7V2 D21 IO90PDB2V1 F12 IO44PDB1V0 H3 VCC D22 IO94NPB2V1 F13 IO50NDB1V1 H4 IO295NDB7V2 E1 IO293NDB7V2 F14 IO60PDB1V2 H5 IO297NDB7V2 E2 IO299PPB7V3 F15 GBC0/IO79NDB1V4 H6 IO307NDB7V4 E3 GND F16 VCCPLB H7 IO287PDB7V1 E4 GAB2/IO308PDB7V4 F17 VMV2 H8 VMV0 E5 GAA2/IO309PDB7V4 F18 IO82NDB2V0 H9 VCCIB0 E6 GNDQ F19 IO86PDB2V0 H10 VCCIB0 E7 GAB1/IO01PDB0V0 F20 IO96PDB2V1 H11 IO36NDB0V4 E8 IO20NDB0V2 F21 IO96NDB2V1 H12 IO42NDB1V0 4- 46 R ev i sio n 1 3 ProASIC3L Low Power Flash FPGAs FG484 FG484 FG484 Pin Number A3PE3000L Function Pin Number A3PE3000L Function Pin Number A3PE3000L Function H13 VCCIB1 K4 IO279NDB7V0 L17 GCA0/IO114NPB3V0 H14 VCCIB1 K5 IO283NDB7V1 L18 VCOMPLC H15 VMV1 K6 IO281NDB7V0 L19 GCB0/IO113NPB2V3 H16 GBC2/IO84PDB2V0 K7 GFC1/IO275PPB7V0 L20 IO110PPB2V3 H17 IO83NDB2V0 K8 VCCIB7 L21 IO111NDB2V3 H18 IO100NDB2V2 K9 VCC L22 IO111PDB2V3 H19 IO100PDB2V2 K10 GND M1 GNDQ H20 VCC K11 GND M2 IO255NPB6V2 H21 VMV2 K12 GND M3 IO272NDB6V4 H22 IO105PDB2V2 K13 GND M4 GFA2/IO272PDB6V4 J1 IO285NDB7V1 K14 VCC M5 GFA1/IO273PDB6V4 J2 IO285PDB7V1 K15 VCCIB2 M6 VCCPLF J3 VMV7 K16 GCC1/IO112PPB2V3 M7 IO271NDB6V4 J4 IO279PDB7V0 K17 IO108NDB2V3 M8 GFB2/IO271PDB6V4 J5 IO283PDB7V1 K18 IO108PDB2V3 M9 VCC J6 IO281PDB7V0 K19 IO110NPB2V3 M10 GND J7 IO287NDB7V1 K20 IO106NPB2V3 M11 GND J8 VCCIB7 K21 IO109NDB2V3 M12 GND J9 GND K22 IO107NDB2V3 M13 GND J10 VCC L1 IO257PSB6V2 M14 VCC J11 VCC L2 IO276PDB7V0 M15 GCB2/IO116PPB3V0 J12 VCC L3 IO276NDB7V0 M16 GCA1/IO114PPB3V0 J13 VCC L4 GFB0/IO274NPB7V0 M17 GCC2/IO117PPB3V0 J14 GND L5 GFA0/IO273NDB6V4 M18 VCCPLC J15 VCCIB2 L6 GFB1/IO274PPB7V0 M19 GCA2/IO115PDB3V0 J16 IO84NDB2V0 L7 VCOMPLF M20 IO115NDB3V0 J17 IO104NDB2V2 L8 GFC0/IO275NPB7V0 M21 IO126PDB3V1 J18 IO104PDB2V2 L9 VCC M22 IO124PSB3V1 J19 IO106PPB2V3 L10 GND N1 IO255PPB6V2 J20 GNDQ L11 GND N2 IO253NDB6V2 J21 IO109PDB2V3 L12 GND N3 VMV6 J22 IO107PDB2V3 L13 GND N4 GFC2/IO270PPB6V4 K1 IO277NDB7V0 L14 VCC N5 IO261PPB6V3 K2 IO277PDB7V0 L15 GCC0/IO112NPB2V3 N6 IO263PDB6V3 K3 GNDQ L16 GCB1/IO113PPB2V3 N7 IO263NDB6V3 R ev i si o n 1 3 4- 47 Package Pin Assignments FG484 FG484 FG484 Pin Number A3PE3000L Function Pin Number A3PE3000L Function Pin Number A3PE3000L Function N8 VCCIB6 P21 IO130PDB3V2 T12 IO194NDB5V0 N9 VCC P22 IO128NDB3V1 T13 IO186NDB4V4 N10 GND R1 IO247NDB6V1 T14 IO186PDB4V4 N11 GND R2 IO245PDB6V1 T15 GNDQ N12 GND R3 VCC T16 VCOMPLD N13 GND R4 IO249NPB6V1 T17 VJTAG N14 VCC R5 IO251NDB6V2 T18 GDC0/IO151NDB3V4 N15 VCCIB3 R6 IO251PDB6V2 T19 GDA1/IO153PDB3V4 N16 IO116NPB3V0 R7 GEC0/IO236NPB6V0 T20 IO144PDB3V3 N17 IO132NPB3V2 R8 VMV5 T21 IO140PDB3V3 N18 IO117NPB3V0 R9 VCCIB5 T22 IO134NDB3V2 N19 IO132PPB3V2 R10 VCCIB5 U1 IO240PPB6V0 N20 GNDQ R11 IO196NDB5V0 U2 IO238PDB6V0 N21 IO126NDB3V1 R12 IO196PDB5V0 U3 IO238NDB6V0 N22 IO128PDB3V1 R13 VCCIB4 U4 GEB1/IO235PDB6V0 P1 IO247PDB6V1 R14 VCCIB4 U5 GEB0/IO235NDB6V0 P2 IO253PDB6V2 R15 VMV3 U6 VMV6 P3 IO270NPB6V4 R16 VCCPLD U7 VCCPLE P4 IO261NPB6V3 R17 GDB1/IO152PPB3V4 U8 IO233NPB5V4 P5 IO249PPB6V1 R18 GDC1/IO151PDB3V4 U9 IO222PPB5V3 P6 IO259PDB6V3 R19 IO138NDB3V3 U10 IO206PDB5V1 P7 IO259NDB6V3 R20 VCC U11 IO202PDB5V1 P8 VCCIB6 R21 IO130NDB3V2 U12 IO194PDB5V0 P9 GND R22 IO134PDB3V2 U13 IO176NDB4V2 P10 VCC T1 IO243PPB6V1 U14 IO176PDB4V2 P11 VCC T2 IO245NDB6V1 U15 VMV4 P12 VCC T3 IO243NPB6V1 U16 TCK P13 VCC T4 IO241PDB6V0 U17 VPUMP P14 GND T5 IO241NDB6V0 U18 TRST P15 VCCIB3 T6 GEC1/IO236PPB6V0 U19 GDA0/IO153NDB3V4 P16 GDB0/IO152NPB3V4 T7 VCOMPLE U20 IO144NDB3V3 P17 IO136NDB3V2 T8 GNDQ U21 IO140NDB3V3 P18 IO136PDB3V2 T9 GEA2/IO233PPB5V4 U22 IO142PDB3V3 P19 IO138PDB3V3 T10 IO206NDB5V1 V1 IO239PDB6V0 P20 VMV3 T11 IO202NDB5V1 V2 IO240NPB6V0 4- 48 R ev i sio n 1 3 ProASIC3L Low Power Flash FPGAs FG484 FG484 Pin Number A3PE3000L Function Pin Number A3PE3000L Function V3 GND W16 IO154NDB4V0 V4 GEA1/IO234PDB6V0 W17 GDA2/IO154PDB4V0 V5 GEA0/IO234NDB6V0 W18 TMS V6 GNDQ W19 GND V7 GEC2/IO231PDB5V4 W20 IO150NDB3V4 V8 IO222NPB5V3 W21 IO146NDB3V4 V9 IO204NDB5V1 W22 IO148PPB3V4 V10 IO204PDB5V1 Y1 VCCIB6 V11 IO195NDB5V0 Y2 IO237NDB6V0 V12 IO195PDB5V0 Y3 IO228NDB5V4 V13 IO178NDB4V3 Y4 IO224NDB5V3 V14 IO178PDB4V3 Y5 GND V15 IO155NDB4V0 Y6 IO220NDB5V3 V16 GDB2/IO155PDB4V0 Y7 IO220PDB5V3 V17 TDI Y8 VCC V18 GNDQ Y9 VCC V19 TDO Y10 IO200PDB5V0 V20 GND Y11 IO192PDB4V4 V21 IO146PDB3V4 Y12 IO188NPB4V4 V22 IO142NDB3V3 Y13 IO187PSB4V4 W1 IO239NDB6V0 Y14 VCC W2 IO237PDB6V0 Y15 VCC W3 IO230PSB5V4 Y16 IO164NDB4V1 W4 GND Y17 IO164PDB4V1 W5 IO232NDB5V4 Y18 GND W6 FF/GEB2/IO232PDB5V4 Y19 IO158PPB4V0 W7 IO231NDB5V4 Y20 IO150PDB3V4 W8 IO214NDB5V2 Y21 IO148NPB3V4 W9 IO214PDB5V2 Y22 VCCIB3 W10 IO200NDB5V0 W11 IO192NDB4V4 W12 IO184NDB4V3 W13 IO184PDB4V3 W14 IO156NDB4V0 W15 GDC2/IO156PDB4V0 R ev i si o n 1 3 4- 49 Package Pin Assignments FG896 A1 Ball Pad Corner 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK Note: This is the bottom view. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.microsemi.com/soc/products/solutions/package/docs.aspx. 4- 50 R ev i sio n 1 3 ProASIC3L Low Power Flash FPGAs FG896 FG896 FG896 Pin Number A3PE3000L Function Pin Number A3PE3000L Function Pin Number A3PE3000L Function A2 GND AA8 IO245NDB6V1 AB13 IO206PDB5V1 A3 GND AA9 GEB1/IO235PPB6V0 AB14 IO198NDB5V0 A4 IO14NPB0V1 AA10 VCC AB15 IO198PDB5V0 A5 GND AA11 IO226PPB5V4 AB16 IO192NDB4V4 A6 IO07NPB0V0 AA12 VCCIB5 AB17 IO192PDB4V4 A7 GND AA13 VCCIB5 AB18 IO178NDB4V3 A8 IO09NDB0V1 AA14 VCCIB5 AB19 IO178PDB4V3 A9 IO17NDB0V2 AA15 VCCIB5 AB20 IO174NDB4V2 A10 IO17PDB0V2 AA16 VCCIB4 AB21 IO162NPB4V1 A11 IO21NDB0V2 AA17 VCCIB4 AB22 VCC A12 IO21PDB0V2 AA18 VCCIB4 AB23 VCCPLD A13 IO33NDB0V4 AA19 VCCIB4 AB24 VCCIB3 A14 IO33PDB0V4 AA20 IO174PDB4V2 AB25 IO150PDB3V4 A15 IO35NDB0V4 AA21 VCC AB26 IO148PDB3V4 A16 IO35PDB0V4 AA22 IO142NPB3V3 AB27 IO147NDB3V4 A17 IO41NDB1V0 AA23 IO144NDB3V3 AB28 IO145PDB3V3 A18 IO43NDB1V0 AA24 IO144PDB3V3 AB29 IO143PDB3V3 A19 IO43PDB1V0 AA25 IO146NDB3V4 AB30 IO137PDB3V2 A20 IO45NDB1V0 AA26 IO146PDB3V4 AC1 IO254PDB6V2 A21 IO45PDB1V0 AA27 IO147PDB3V4 AC2 IO254NDB6V2 A22 IO57NDB1V2 AA28 IO139NDB3V3 AC3 IO240PDB6V0 A23 IO57PDB1V2 AA29 IO139PDB3V3 AC4 GEC1/IO236PDB6V0 A24 GND AA30 IO133NDB3V2 AC5 IO237PDB6V0 A25 IO69PPB1V3 AB1 IO256NDB6V2 AC6 IO237NDB6V0 A26 GND AB2 IO244PDB6V1 AC7 VCOMPLE A27 GBC1/IO79PPB1V4 AB3 IO244NDB6V1 AC8 GND A28 GND AB4 IO241PDB6V0 AC9 IO226NPB5V4 A29 GND AB5 IO241NDB6V0 AC10 IO222NDB5V3 AA1 IO256PDB6V2 AB6 IO243NPB6V1 AC11 IO216NPB5V2 AA2 IO248PDB6V1 AB7 VCCIB6 AC12 IO210NPB5V2 AA3 IO248NDB6V1 AB8 VCCPLE AC13 IO204NDB5V1 AA4 IO246NDB6V1 AB9 VCC AC14 IO204PDB5V1 AA5 GEA1/IO234PDB6V0 AB10 IO222PDB5V3 AC15 IO194NDB5V0 AA6 GEA0/IO234NDB6V0 AB11 IO218PPB5V3 AC16 IO188NDB4V4 AA7 IO243PPB6V1 AB12 IO206NDB5V1 AC17 IO188PDB4V4 R ev i si o n 1 3 4- 51 Package Pin Assignments FG896 FG896 FG896 Pin Number A3PE3000L Function Pin Number A3PE3000L Function Pin Number A3PE3000L Function AC18 IO182PPB4V3 AD22 VCCIB4 AE26 GDB0/IO152NDB3V4 AC19 IO170NPB4V2 AD23 TCK AE27 GDB1/IO152PDB3V4 AC20 IO164NDB4V1 AD24 VCC AE28 VMV3 AC21 IO164PDB4V1 AD25 TRST AE28 VMV3 AC22 IO162PPB4V1 AD26 VCCIB3 AE29 VCC AC23 GND AD27 GDA0/IO153NDB3V4 AE30 IO149PDB3V4 AC24 VCOMPLD AD28 GDC0/IO151NDB3V4 AF1 GND AC25 IO150NDB3V4 AD29 GDC1/IO151PDB3V4 AF2 IO238PPB6V0 AC26 IO148NDB3V4 AD30 GND AF3 VCCIB6 AC27 GDA1/IO153PDB3V4 AE1 IO242PPB6V1 AF4 IO220NPB5V3 AC28 IO145NDB3V3 AE2 VCC AF5 VCC AC29 IO143NDB3V3 AE3 IO239PDB6V0 AF6 IO228NDB5V4 AC30 IO137NDB3V2 AE4 IO239NDB6V0 AF7 VCCIB5 AD1 GND AE5 VMV6 AF8 IO230PDB5V4 AD2 IO242NPB6V1 AE5 VMV6 AF9 IO229NDB5V4 AD3 IO240NDB6V0 AE6 GND AF10 IO229PDB5V4 AD4 GEC0/IO236NDB6V0 AE7 GNDQ AF11 IO214PPB5V2 AD5 VCCIB6 AE8 IO230NDB5V4 AF12 IO208NDB5V1 AD6 GNDQ AE9 IO224NPB5V3 AF13 IO208PDB5V1 AD6 GNDQ AE10 IO214NPB5V2 AF14 IO200PDB5V0 AD7 VCC AE11 IO212NDB5V2 AF15 IO196NDB5V0 AD8 VMV5 AE12 IO212PDB5V2 AF16 IO186NDB4V4 AD9 VCCIB5 AE13 IO202NPB5V1 AF17 IO186PDB4V4 AD10 IO224PPB5V3 AE14 IO200NDB5V0 AF18 IO180NDB4V3 AD11 IO218NPB5V3 AE15 IO196PDB5V0 AF19 IO180PDB4V3 AD12 IO216PPB5V2 AE16 IO190NDB4V4 AF20 IO168NDB4V1 AD13 IO210PPB5V2 AE17 IO184PDB4V3 AF21 IO168PDB4V1 AD14 IO202PPB5V1 AE18 IO184NDB4V3 AF22 IO160NDB4V0 AD15 IO194PDB5V0 AE19 IO172PDB4V2 AF23 IO158NPB4V0 AD16 IO190PDB4V4 AE20 IO172NDB4V2 AF24 VCCIB4 AD17 IO182NPB4V3 AE21 IO166NDB4V1 AF25 IO154NPB4V0 AD18 IO176NDB4V2 AE22 IO160PDB4V0 AF26 VCC AD19 IO176PDB4V2 AE23 GNDQ AF27 TDO AD20 IO170PPB4V2 AE24 VMV4 AF28 VCCIB3 AD21 IO166PDB4V1 AE25 GND AF29 GNDQ 4- 52 R ev i sio n 1 3 ProASIC3L Low Power Flash FPGAs FG896 FG896 FG896 Pin Number A3PE3000L Function Pin Number A3PE3000L Function Pin Number A3PE3000L Function AF29 GNDQ AH4 FF/GEB2/IO232PPB5V4 AJ9 IO213PDB5V2 AF30 GND AH5 VCCIB5 AJ10 IO209NDB5V1 AG1 IO238NPB6V0 AH6 IO219NDB5V3 AJ11 IO209PDB5V1 AG2 VCC AH7 IO219PDB5V3 AJ12 IO203NDB5V1 AG3 IO232NPB5V4 AH8 IO227NDB5V4 AJ13 IO203PDB5V1 AG4 GND AH9 IO227PDB5V4 AJ14 IO197NDB5V0 AG5 IO220PPB5V3 AH10 IO225PPB5V3 AJ15 IO195PDB5V0 AG6 IO228PDB5V4 AH11 IO223PPB5V3 AJ16 IO183NDB4V3 AG7 IO231NDB5V4 AH12 IO211NDB5V2 AJ17 IO183PDB4V3 AG8 GEC2/IO231PDB5V4 AH13 IO211PDB5V2 AJ18 IO179NPB4V3 AG9 IO225NPB5V3 AH14 IO205PPB5V1 AJ19 IO177PDB4V2 AG10 IO223NPB5V3 AH15 IO195NDB5V0 AJ20 IO173NDB4V2 AG11 IO221PDB5V3 AH16 IO185NDB4V3 AJ21 IO173PDB4V2 AG12 IO221NDB5V3 AH17 IO185PDB4V3 AJ22 IO163NDB4V1 AG13 IO205NPB5V1 AH18 IO181PDB4V3 AJ23 IO163PDB4V1 AG14 IO199NDB5V0 AH19 IO177NDB4V2 AJ24 IO167NPB4V1 AG15 IO199PDB5V0 AH20 IO171NPB4V2 AJ25 VCC AG16 IO187NDB4V4 AH21 IO165PPB4V1 AJ26 IO156NPB4V0 AG17 IO187PDB4V4 AH22 IO161PPB4V0 AJ27 VCC AG18 IO181NDB4V3 AH23 IO157NDB4V0 AJ28 TMS AG19 IO171PPB4V2 AH24 IO157PDB4V0 AJ29 GND AG20 IO165NPB4V1 AH25 IO155NDB4V0 AJ30 GND AG21 IO161NPB4V0 AH26 VCCIB4 AK2 GND AG22 IO159NDB4V0 AH27 TDI AK3 GND AG23 IO159PDB4V0 AH28 VCC AK4 IO217PPB5V2 AG24 IO158PPB4V0 AH29 VPUMP AK5 GND AG25 GDB2/IO155PDB4V0 AH30 GND AK6 IO215PPB5V2 AG26 GDA2/IO154PPB4V0 AJ1 GND AK7 GND AG27 GND AJ2 GND AK8 IO207NDB5V1 AG28 VJTAG AJ3 GEA2/IO233PPB5V4 AK9 IO207PDB5V1 AG29 VCC AJ4 VCC AK10 IO201NDB5V0 AG30 IO149NDB3V4 AJ5 IO217NPB5V2 AK11 IO201PDB5V0 AH1 GND AJ6 VCC AK12 IO193NDB4V4 AH2 IO233NPB5V4 AJ7 IO215NPB5V2 AK13 IO193PDB4V4 AH3 VCC AJ8 IO213NDB5V2 AK14 IO197PDB5V0 R ev i si o n 1 3 4- 53 Package Pin Assignments FG896 FG896 FG896 Pin Number A3PE3000L Function Pin Number A3PE3000L Function Pin Number A3PE3000L Function AK15 IO191NDB4V4 B21 IO53NDB1V1 C26 VCCIB1 AK16 IO191PDB4V4 B22 IO61NDB1V2 C27 IO64PPB1V2 AK17 IO189NDB4V4 B23 IO61PDB1V2 C28 VCC AK18 IO189PDB4V4 B24 IO69NPB1V3 C29 GBA1/IO81PPB1V4 AK19 IO179PPB4V3 B25 VCC C30 GND AK20 IO175NDB4V2 B26 GBC0/IO79NPB1V4 D1 IO303PPB7V3 AK21 IO175PDB4V2 B27 VCC D2 VCC AK22 IO169NDB4V1 B28 IO64NPB1V2 D3 IO305NPB7V3 AK23 IO169PDB4V1 B29 GND D4 GND AK24 GND B30 GND D5 GAA1/IO00PPB0V0 AK25 IO167PPB4V1 C1 GND D6 GAC1/IO02PDB0V0 AK26 GND C2 IO309NPB7V4 D7 IO06NPB0V0 AK27 GDC2/IO156PPB4V0 C3 VCC D8 GAB0/IO01NDB0V0 AK28 GND C4 GAA0/IO00NPB0V0 D9 IO05NDB0V0 AK29 GND C5 VCCIB0 D10 IO11NDB0V1 B1 GND C6 IO03PDB0V0 D11 IO11PDB0V1 B2 GND C7 IO03NDB0V0 D12 IO23NDB0V2 B3 GAA2/IO309PPB7V4 C8 GAB1/IO01PDB0V0 D13 IO23PDB0V2 B4 VCC C9 IO05PDB0V0 D14 IO27PDB0V3 B5 IO14PPB0V1 C10 IO15NPB0V1 D15 IO40PDB0V4 B6 VCC C11 IO25NDB0V3 D16 IO47NDB1V0 B7 IO07PPB0V0 C12 IO25PDB0V3 D17 IO47PDB1V0 B8 IO09PDB0V1 C13 IO31NPB0V3 D18 IO55NPB1V1 B9 IO15PPB0V1 C14 IO27NDB0V3 D19 IO65NDB1V3 B10 IO19NDB0V2 C15 IO39NDB0V4 D20 IO65PDB1V3 B11 IO19PDB0V2 C16 IO39PDB0V4 D21 IO71NDB1V3 B12 IO29NDB0V3 C17 IO55PPB1V1 D22 IO71PDB1V3 B13 IO29PDB0V3 C18 IO51PDB1V1 D23 IO73NDB1V4 B14 IO31PPB0V3 C19 IO59NDB1V2 D24 IO73PDB1V4 B15 IO37NDB0V4 C20 IO63NDB1V2 D25 IO74NDB1V4 B16 IO37PDB0V4 C21 IO63PDB1V2 D26 GBB0/IO80NPB1V4 B17 IO41PDB1V0 C22 IO67NDB1V3 D27 GND B18 IO51NDB1V1 C23 IO67PDB1V3 D28 GBA0/IO81NPB1V4 B19 IO59PDB1V2 C24 IO75NDB1V4 D29 VCC B20 IO53PDB1V1 C25 IO75PDB1V4 D30 GBA2/IO82PPB2V0 4- 54 R ev i sio n 1 3 ProASIC3L Low Power Flash FPGAs FG896 FG896 FG896 Pin Number A3PE3000L Function Pin Number A3PE3000L Function Pin Number A3PE3000L Function E1 GND F5 VMV7 G8 VMV0 E2 IO303NPB7V3 F6 GND G9 VCCIB0 E3 VCCIB7 F7 GNDQ G10 IO10NDB0V1 E4 IO305PPB7V3 F8 IO12NDB0V1 G11 IO16NDB0V1 E5 VCC F9 IO12PDB0V1 G12 IO22PDB0V2 E6 GAC0/IO02NDB0V0 F10 IO10PDB0V1 G13 IO26PPB0V3 E7 VCCIB0 F11 IO16PDB0V1 G14 IO38NPB0V4 E8 IO06PPB0V0 F12 IO22NDB0V2 G15 IO36NDB0V4 E9 IO24NDB0V2 F13 IO30NDB0V3 G16 IO46NDB1V0 E10 IO24PDB0V2 F14 IO30PDB0V3 G17 IO46PDB1V0 E11 IO13NDB0V1 F15 IO36PDB0V4 G18 IO56NDB1V1 E12 IO13PDB0V1 F16 IO48NDB1V0 G19 IO56PDB1V1 E13 IO34NDB0V4 F17 IO48PDB1V0 G20 IO66NDB1V3 E14 IO34PDB0V4 F18 IO50NDB1V1 G21 IO66PDB1V3 E15 IO40NDB0V4 F19 IO58NDB1V2 G22 VCCIB1 E16 IO49NDB1V1 F20 IO60PDB1V2 G23 VMV1 E17 IO49PDB1V1 F21 IO77NDB1V4 G24 VCC E18 IO50PDB1V1 F22 IO72NDB1V3 G25 GNDQ E19 IO58PDB1V2 F23 IO72PDB1V3 G25 GNDQ E20 IO60NDB1V2 F24 GNDQ G26 VCCIB2 E21 IO77PDB1V4 F25 GND G27 IO86NDB2V0 E22 IO68NDB1V3 F26 VMV2 G28 IO92NDB2V1 E23 IO68PDB1V3 F26 VMV2 G29 IO100PPB2V2 E24 VCCIB1 F27 IO86PDB2V0 G30 GND E25 IO74PDB1V4 F28 IO92PDB2V1 H1 IO294PDB7V2 E26 VCC F29 VCC H2 IO294NDB7V2 E27 GBB1/IO80PPB1V4 F30 IO100NPB2V2 H3 IO300NDB7V3 E28 VCCIB2 G1 GND H4 IO300PDB7V3 E29 IO82NPB2V0 G2 IO296NPB7V2 H5 IO295PDB7V2 E30 GND G3 IO306NDB7V4 H6 IO299PDB7V3 F1 IO296PPB7V2 G4 IO297NDB7V2 H7 VCOMPLA F2 VCC G5 VCCIB7 H8 GND F3 IO306PDB7V4 G6 GNDQ H9 IO08NDB0V0 F4 IO297PDB7V2 G6 GNDQ H10 IO08PDB0V0 F5 VMV7 G7 VCC H11 IO18PDB0V2 R ev i si o n 1 3 4- 55 Package Pin Assignments FG896 FG896 FG896 Pin Number A3PE3000L Function Pin Number A3PE3000L Function Pin Number A3PE3000L Function H12 IO26NPB0V3 J17 IO44NDB1V0 K22 IO78PPB1V4 H13 IO28NDB0V3 J18 IO44PDB1V0 K23 IO88NDB2V0 H14 IO28PDB0V3 J19 IO54NDB1V1 K24 IO88PDB2V0 H15 IO38PPB0V4 J20 IO54PDB1V1 K25 IO94PDB2V1 H16 IO42NDB1V0 J21 IO76NPB1V4 K26 IO94NDB2V1 H17 IO52NDB1V1 J22 VCC K27 IO85PDB2V0 H18 IO52PDB1V1 J23 VCCPLB K28 IO85NDB2V0 H19 IO62NDB1V2 J24 VCCIB2 K29 IO93PDB2V1 H20 IO62PDB1V2 J25 IO90PDB2V1 K30 IO93NDB2V1 H21 IO70NDB1V3 J26 IO90NDB2V1 L1 IO286NDB7V1 H22 IO70PDB1V3 J27 GBB2/IO83PDB2V0 L2 IO286PDB7V1 H23 GND J28 IO83NDB2V0 L3 IO298NDB7V3 H24 VCOMPLB J29 IO91PDB2V1 L4 IO298PDB7V3 H25 GBC2/IO84PDB2V0 J30 IO91NDB2V1 L5 IO283PDB7V1 H26 IO84NDB2V0 K1 IO288NDB7V1 L6 IO291NDB7V2 H27 IO96PDB2V1 K2 IO288PDB7V1 L7 IO291PDB7V2 H28 IO96NDB2V1 K3 IO304NDB7V3 L8 IO293PDB7V2 H29 IO89PDB2V0 K4 IO304PDB7V3 L9 IO293NDB7V2 H30 IO89NDB2V0 K5 GAB2/IO308PDB7V4 L10 IO307NPB7V4 J1 IO290NDB7V2 K6 IO308NDB7V4 L11 VCC J2 IO290PDB7V2 K7 IO301PDB7V3 L12 VCC J3 IO302NDB7V3 K8 IO301NDB7V3 L13 VCC J4 IO302PDB7V3 K9 GAC2/IO307PPB7V4 L14 VCC J5 IO295NDB7V2 K10 VCC L15 VCC J6 IO299NDB7V3 K11 IO04PPB0V0 L16 VCC J7 VCCIB7 K12 VCCIB0 L17 VCC J8 VCCPLA K13 VCCIB0 L18 VCC J9 VCC K14 VCCIB0 L19 VCC J10 IO04NPB0V0 K15 VCCIB0 L20 VCC J11 IO18NDB0V2 K16 VCCIB1 L21 IO78NPB1V4 J12 IO20NDB0V2 K17 VCCIB1 L22 IO104NPB2V2 J13 IO20PDB0V2 K18 VCCIB1 L23 IO98NDB2V2 J14 IO32NDB0V3 K19 VCCIB1 L24 IO98PDB2V2 J15 IO32PDB0V3 K20 IO76PPB1V4 L25 IO87PDB2V0 J16 IO42PDB1V0 K21 VCC L26 IO87NDB2V0 4- 56 R ev i sio n 1 3 ProASIC3L Low Power Flash FPGAs FG896 FG896 FG896 Pin Number A3PE3000L Function Pin Number A3PE3000L Function Pin Number A3PE3000L Function L27 IO97PDB2V1 N2 IO278PDB7V0 P7 GFC0/IO275NDB7V0 L28 IO101PDB2V2 N3 IO280PDB7V0 P8 IO277PDB7V0 L29 IO103PDB2V2 N4 IO284PDB7V1 P9 IO277NDB7V0 L30 IO119NDB3V0 N5 IO279PDB7V0 P10 VCCIB7 M1 IO282NDB7V1 N6 IO285NDB7V1 P11 VCC M2 IO282PDB7V1 N7 IO287NDB7V1 P12 GND M3 IO292NDB7V2 N8 IO281NDB7V0 P13 GND M4 IO292PDB7V2 N9 IO281PDB7V0 P14 GND M5 IO283NDB7V1 N10 VCCIB7 P15 GND M6 IO285PDB7V1 N11 VCC P16 GND M7 IO287PDB7V1 N12 GND P17 GND M8 IO289PDB7V1 N13 GND P18 GND M9 IO289NDB7V1 N14 GND P19 GND M10 VCCIB7 N15 GND P20 VCC M11 VCC N16 GND P21 VCCIB2 M12 GND N17 GND P22 GCC1/IO112PDB2V3 M13 GND N18 GND P23 IO110PDB2V3 M14 GND N19 GND P24 IO110NDB2V3 M15 GND N20 VCC P25 IO109PPB2V3 M16 GND N21 VCCIB2 P26 IO111NPB2V3 M17 GND N22 IO106NDB2V3 P27 IO105PDB2V2 M18 GND N23 IO106PDB2V3 P28 IO105NDB2V2 M19 GND N24 IO108PDB2V3 P29 GCC2/IO117PDB3V0 M20 VCC N25 IO108NDB2V3 P30 IO117NDB3V0 M21 VCCIB2 N26 IO95NDB2V1 R1 GFC2/IO270PDB6V4 M22 NC N27 IO99NDB2V2 R2 GFB1/IO274PPB7V0 M23 IO104PPB2V2 N28 IO99PDB2V2 R3 VCOMPLF M24 IO102PDB2V2 N29 IO107PDB2V3 R4 GFA0/IO273NDB6V4 M25 IO102NDB2V2 N30 IO107NDB2V3 R5 GFB0/IO274NPB7V0 M26 IO95PDB2V1 P1 IO276NDB7V0 R6 IO271NDB6V4 M27 IO97NDB2V1 P2 IO278NDB7V0 R7 GFB2/IO271PDB6V4 M28 IO101NDB2V2 P3 IO280NDB7V0 R8 IO269PDB6V4 M29 IO103NDB2V2 P4 IO284NDB7V1 R9 IO269NDB6V4 M30 IO119PDB3V0 P5 IO279NDB7V0 R10 VCCIB7 N1 IO276PDB7V0 P6 GFC1/IO275PDB7V0 R11 VCC R ev i si o n 1 3 4- 57 Package Pin Assignments FG896 FG896 FG896 Pin Number A3PE3000L Function Pin Number A3PE3000L Function Pin Number A3PE3000L Function R12 GND T17 GND U22 IO120PDB3V0 R13 GND T18 GND U23 IO128PDB3V1 R14 GND T19 GND U24 IO124PDB3V1 R15 GND T20 VCC U25 IO124NDB3V1 R16 GND T21 VCCIB3 U26 IO126PDB3V1 R17 GND T22 IO109NPB2V3 U27 IO129PDB3V1 R18 GND T23 IO116NDB3V0 U28 IO127PDB3V1 R19 GND T24 IO118NDB3V0 U29 IO125PDB3V1 R20 VCC T25 IO122NPB3V1 U30 IO121NDB3V0 R21 VCCIB2 T26 GCA1/IO114PPB3V0 V1 IO268NDB6V4 R22 GCC0/IO112NDB2V3 T27 GCB0/IO113NPB2V3 V2 IO262PDB6V3 R23 GCB2/IO116PDB3V0 T28 GCA2/IO115PPB3V0 V3 IO260PDB6V3 R24 IO118PDB3V0 T29 VCCPLC V4 IO252PDB6V2 R25 IO111PPB2V3 T30 IO121PDB3V0 V5 IO257NPB6V2 R26 IO122PPB3V1 U1 IO268PDB6V4 V6 IO261NPB6V3 R27 GCA0/IO114NPB3V0 U2 IO264NDB6V3 V7 IO255PDB6V2 R28 VCOMPLC U3 IO264PDB6V3 V8 IO259PDB6V3 R29 GCB1/IO113PPB2V3 U4 IO258PDB6V3 V9 IO259NDB6V3 R30 IO115NPB3V0 U5 IO258NDB6V3 V10 VCCIB6 T1 IO270NDB6V4 U6 IO257PPB6V2 V11 VCC T2 VCCPLF U7 IO261PPB6V3 V12 GND T3 GFA2/IO272PPB6V4 U8 IO265NDB6V3 V13 GND T4 GFA1/IO273PDB6V4 U9 IO263NDB6V3 V14 GND T5 IO272NPB6V4 U10 VCCIB6 V15 GND T6 IO267NDB6V4 U11 VCC V16 GND T7 IO267PDB6V4 U12 GND V17 GND T8 IO265PDB6V3 U13 GND V18 GND T9 IO263PDB6V3 U14 GND V19 GND T10 VCCIB6 U15 GND V20 VCC T11 VCC U16 GND V21 VCCIB3 T12 GND U17 GND V22 IO120NDB3V0 T13 GND U18 GND V23 IO128NDB3V1 T14 GND U19 GND V24 IO132PDB3V2 T15 GND U20 VCC V25 IO130PPB3V2 T16 GND U21 VCCIB3 V26 IO126NDB3V1 4- 58 R ev i sio n 1 3 ProASIC3L Low Power Flash FPGAs FG896 FG896 Pin Number A3PE3000L Function Pin Number A3PE3000L Function V27 IO129NDB3V1 Y2 IO250PDB6V2 V28 IO127NDB3V1 Y3 IO250NDB6V2 V29 IO125NDB3V1 Y4 IO246PDB6V1 V30 IO123PDB3V1 Y5 IO247NDB6V1 W1 IO266NDB6V4 Y6 IO247PDB6V1 W2 IO262NDB6V3 Y7 IO249NPB6V1 W3 IO260NDB6V3 Y8 IO245PDB6V1 W4 IO252NDB6V2 Y9 IO253NDB6V2 W5 IO251NDB6V2 Y10 GEB0/IO235NPB6V0 W6 IO251PDB6V2 Y11 VCC W7 IO255NDB6V2 Y12 VCC W8 IO249PPB6V1 Y13 VCC W9 IO253PDB6V2 Y14 VCC W10 VCCIB6 Y15 VCC W11 VCC Y16 VCC W12 GND Y17 VCC W13 GND Y18 VCC W14 GND Y19 VCC W15 GND Y20 VCC W16 GND Y21 IO142PPB3V3 W17 GND Y22 IO134NDB3V2 W18 GND Y23 IO138NDB3V3 W19 GND Y24 IO140NDB3V3 W20 VCC Y25 IO140PDB3V3 W21 VCCIB3 Y26 IO136PPB3V2 W22 IO134PDB3V2 Y27 IO141NDB3V3 W23 IO138PDB3V3 Y28 IO135NDB3V2 W24 IO132NDB3V2 Y29 IO131NDB3V2 W25 IO136NPB3V2 Y30 IO133PDB3V2 W26 IO130NPB3V2 W27 IO141PDB3V3 W28 IO135PDB3V2 W29 IO131PDB3V2 W30 IO123NDB3V1 Y1 IO266PDB6V4 R ev i si o n 1 3 4- 59 5 - Datasheet Information List of Changes The following table lists critical changes that were made in each version of the ProASIC3L datasheet. Revision Revision 13 (January 2013) Changes Page The "ProASIC3L Ordering Information" section has been updated to mention "Y" as "Blank" mentioning "Device Does Not Include License to Implement IP Based on the Cryptography Research, Inc. (CRI) Patent Portfolio" (SAR 43221). 1-III Added following notes to Table 2-2 * Recommended Operating Conditions 1: "All ProASIC3L devices must be programmed with the VCC core voltage at 1.5 V" (SAR 39910) and "The programming temperature range supported is Tambient = 0C to 85C" (SAR 43645). 2-2 The note in Table 2-212 * ProASIC3L CCC/PLL Specification and Table 2-213 * 2-132, ProASIC3L CCC/PLL Specification referring the reader to SmartGen was revised to 2-133 refer instead to the online help associated with the core (SAR 42572). Signal names have been made consistent (SAR 38910). NA Libero Integrated Design Environment (IDE) was changed to Libero System-on-Chip (SoC) throughout the document (SAR 40286). NA Live at Power-Up (LAPU) has been replaced with 'Instant On'. Revision 12 The "Security" section was modified to clarify that Microsemi does not support read(September 2012) back of programmed data. 1-2 Revision 11 (August 2012) 2-1 2-2 Added a Note stating "VMV pins must be connected to the corresponding VCCI pins. See the "VMVx I/O Supply Voltage (quiet)" section on page 3-1 for further information." to Table 2-1 * Absolute Maximum Ratings and Table 2-2 * Recommended Operating Conditions 1 (SAR 38316). The "Quiescent Supply Current" section was updated. Table 2-7 * Power Supply State per Mode is new, and Table 2-9 * Quiescent Supply Current (IDD) Characteristics, ProASIC3L Sleep Mode* and Table 2-11 * Quiescent Supply Current (IDD) Characteristics, No Flash*Freeze Mode1 were updated for Core Voltage 1.2 V. Notes were also updated for Table 2-9, Table 2-10, and Table 2-11 (SAR 34746). 2-7 2-8 The drive strength, IOL, and IOH value for 3.3 V GTL and 2.5 V GTL was changed from 25 mA to 20 mA in the following tables (SAR 37364): Table 2-23 * Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial Conditions--Software Default Settings 2-22 Table 2-29 * Summary of I/O Timing Characteristics--Software Default Settings 2-27 2-30 2-34 2-38 2-83 2-85 Table 2-32 * Summary of I/O Timing Characteristics--Software Default Settings Table 2-36 * I/O Output Buffer Maximum Resistances1 Table 2-40 * I/O Short Currents IOSH/IOSL Table 2-134 * Minimum and Maximum DC Input and Output Levels Table 2-138 * Minimum and Maximum DC Input and Output Levels Also added note stating "Output drive strength is below JEDEC specification." for Tables Table 2-29, Table 2-32, Table 2-36, and Table 2-40. Additionally, the IOL and IOH values for 3.3 V GTL+ and 2.5 V GTL+ were corrected from 51 to 35 (for 3.3 V GTL+) and from 40 to 33 (for 2.5 V GTL+) in table Table 2-23 (SAR 39715). R ev i si o n 1 3 5 -1 Datasheet Information Revision Revision 11 continued Revision 10 (May 2012) Changes Page Figure 2-12 * AC Loading in the "3.3 V PCI, 3.3 V PCI-X" section was updated to match Table 2-127 * AC Waveforms, Measuring Points, and Capacitive Loads (SAR 34890). 2-81 In Table 2-180 * Minimum and Maximum DC Input and Output Levels, VIL and VIH were revised so that the maximum is 3.6 V for all listed values of VCCI (SAR 37690). 2-103 The following sentence was removed from the "VMVx I/O Supply Voltage (quiet)" section in the "Pin Descriptions and Packaging" chapter: "Within the package, the VMV plane is decoupled from the simultaneous switching noise originating from the output buffer VCCI domain" and replaced with "Within the package, the VMV plane biases the input stage of the I/Os in the I/O banks" (SAR 38316). The datasheet mentions that "VMV pins must be connected to the corresponding VCCI pins" for an ESD enhancement. 3-1 Pin K15 of the "FG484" pin table for A3P600L was corrected from VvB1 to VCCIB1 (SAR 38788). 4-35 The "In-System Programming (ISP) and Security" section and "Security" section were revised to clarify that although no existing security measures can give an absolute guarantee, Microsemi FPGAs implement the best security available in the industry (SAR 34670). I, 1-2 The Y security option and Licensed DPA Logo were added to the "ProASIC3L Ordering Information" section. The trademarked Licensed DPA Logo identifies that a product is covered by a DPA counter-measures license from Cryptography Research (SAR 34728). III The "ProASIC3L Device Status" table was updated to show that all ProASIC3L devices have changed in status from Advance to Production (SAR 38198). IV The opening sentence of the "General Description" section was revised for clarity to "The ProASIC3L family of Microsemi flash FPGAs dramatically reduces dynamic power consumption by 40% and static power by 50% compared to the equivalent ProASIC3 device" (SAR 22661). 1-1 The following sentence was removed from the "Advanced Architecture" section: 1-3 "In addition, extensive on-chip programming circuitry allows for rapid, single-voltage (3.3 V) programming of ProASIC3L devices via an IEEE 1532 JTAG interface" (SAR 34690). 5- 2 The "Specifying I/O States During Programming" section is new (SAR 34700). 1-8 Table 1-1 * I/O Standards Supported is new. The "I/Os with Advanced I/O Standards" section was revised to add definitions of hot-swap and cold-sparing (SAR 37732). 1-7 In Table 2-2 * Recommended Operating Conditions 1, VPUMP programming voltage for operation was changed from "0 to 3.45 V" to "0 to 3.6 V" (SAR 32257). 2-2 Values for 1.5 V were added to Table 2-8 * Quiescent Supply Current (IDD) Characteristics, ProASIC3L Flash*Freeze Mode* and Table 2-11 * Quiescent Supply Current (IDD) Characteristics, No Flash*Freeze Mode1 (SAR 30578). 2-7, 2-8 The reference to guidelines for global spines and VersaTile rows, given in the "Global Clock Contribution--PCLOCK" section, was corrected to the "Spine Architecture" section of the Global Resources chapter in the ProASIC3L FPGA Fabric User's Guide (SAR 34737). 2-15 tDOUT was corrected to tDIN in Figure 2-4 * Input Buffer Timing Model and Delays (example) (SAR 37110). 2-19 R ev isio n 1 3 ProASIC3L Low Power Flash FPGAs Revision Revision 10 continued Changes Page 3.3 V LVCMOS and 1.2 V LVCMOS wide range were added to applicable tables in the "Overview of I/O Performance" section and "Detailed I/O DC Characteristics" section. Values for 1.2 V LVCMOS were added to tables in the "Detailed I/O DC Characteristics" section. The "3.3 V LVCMOS Wide Range" section and "1.2 V LVCMOS Wide Range" section, with Minimum and Maximum DC Input and Output Levels tables, are new. 2-22, 2-33, 2-50, 2-80 Complete timing data for wide range will be available in a later revision of the datasheet (SARs 37161, 38188). The notes regarding drive strength in the "Summary of I/O Timing Characteristics - Default I/O Software Settings" section tables were revised for clarification. They now state that the minimum drive strength for the default software configuration when run in wide range is 100 A. The drive strength displayed in software is supported in normal range only. For a detailed I/V curve, refer to the IBIS models (SAR 34761). 2-26 Table 2-39 * I/O Weak Pull-Up/Pull-Down Resistances was updated with additional values and the definitions of RWEAK PULL-UP-MAX and RWEAK PULL-DOWN-MAX were corrected (SAR 34756). 2-37 The paragraph above Table 2-44 * Duration of Short Circuit Event before Failure was revised to change the maximum temperature from 110C to 100C, with an example of six months instead of three months. The row for 110C was removed from the table for consistency with Table 2-2 * Recommended Operating Conditions 1 (SAR 34744). 2-41 The AC Loading figures in the "Single-Ended I/O Characteristics" section were updated to match tables in the "Summary of I/O Timing Characteristics - Default I/O Software Settings" section (SAR 34890). 2-42, 2-26 The following sentence was deleted from the "2.5 V LVCMOS" section (SAR 34797): "It uses a 5 V-tolerant input buffer and push-pull output buffer." 2-52 The table notes were revised for LVDS Table 2-174 * Minimum and Maximum DC Input and Output Levels (SAR 34813). 2-100 Values for the maximum frequency for input and output DDR were added to tables in the "DDR Module Specifications" section (SAR 34805). 2-115 Minimum pulse width High and Low values were added to the tables in the "Global Tree Timing Characteristics" section. The maximum frequency for global clock parameter was removed from these tables because a frequency on the global is only an indication of what the global network can do. There are other limiters such as the SRAM, I/Os, and PLL. SmartTime software should be used to determine the design frequency (SAR 36965). 2-128 Table 2-212 * ProASIC3L CCC/PLL Specification and Table 2-212 * ProASIC3L 2-132, CCC/PLL Specification were updated. A note was added to indicate that when the 2-133 CCC/PLL core is generated by Microsemi core generator software, not all delay values of the specified delay increments are available (SAR 34825). Figure 2-46 * Write Access after Write onto Same Address, Figure 2-47 * Read Access 2-135, after Write onto Same Address, and Figure 2-48 * Write Access after Read onto Same 2-138, Address were deleted. Reference was made to a new application note, Simultaneous 2-144, Read-Write Operations in Dual-Port SRAM for Flash-Based cSoCs and FPGAs, which 2-146 covers these cases in detail (SAR 34873). The port names in the SRAM "Timing Waveforms", SRAM "Timing Characteristics" tables, Figure 2-50 * FIFO Reset, and the FIFO "Timing Characteristics" tables were revised to ensure consistency with the software names (SAR 35751). Figure 2-48 * FIFO Read and Figure 2-49 * FIFO Write are new (SAR 34849). The "Pin Descriptions and Packaging" chapter is new (SAR 34773). R ev i si o n 1 3 2-143 3-1 5 -3 Datasheet Information Revision Changes Page Revision 10 (continued) Package names used in the "Package Pin Assignments" section were revised to match standards given in Package Mechanical Drawings (SAR 34773). 4-1 July 2010 The versioning system for datasheets has been changed. Datasheets are assigned a revision number that increments each time the datasheet is revised. The "ProASIC3L Device Status" table on page IV indicates the status for each device in the device family. N/A 5- 4 R ev isio n 1 3 ProASIC3L Low Power Flash FPGAs Revision Changes Page The "I/Os Per Package 1" table was revised to change the number of differential I/O pairs for A3PE3000L from 300 to 310. II Table 2 * ProASIC3L FPGAs Package Sizes Dimensions is new. II The "Advanced and Pro (Professional) I/Os" section was revised to add two bullets regarding wide range power supply voltage support. I 3.0 V wide range was added to the list of supported voltages in the "I/Os with Advanced I/O Standards" section. The "Wide Range I/O Support" section is new. 1-7 Revision 7 (Aug 2008) 3.0 V LVCMOS wide range support data was added to Table 2-2 * Recommended DC and Switching Operating Conditions 1. 2-2 Revision 9 (Feb 2009) Product Brief v1.3 Revision 8 (Feb 2009) Product Brief v1.2 Characteristics Advance v0.6 3.3 V LVCMOS wide range support data was added to Table 2-23 * Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial Conditions--Software Default Settings to Table 2-25 * Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial Conditions--Software Default Settings. 2-22 to 2-24 3.3 V LVCMOS wide range support data was added to Table 2-27 * Summary of AC Measuring Points. 2-26 3.3 V LVCMOS wide range support text was added to the "3.3 V LVTTL / 3.3 V LVCMOS" section. 2-42 Table 2-62 * Minimum and Maximum DC Input and Output Levels for LVCMOS 3.3 V Wide Range is new. 2-50 Revision 6 (Aug 2008) Table 2-6 * Temperature and Voltage Derating Factors for Timing Delays was updated to add several new rows of values. DC and Switching 2-7 Characteristics Advance v0.5 Table 2-8 * Quiescent Supply Current (IDD) Characteristics, ProASIC3L 2-7 to 2-8 Flash*Freeze Mode* through Table 2-11 * Quiescent Supply Current (IDD) Characteristics, No Flash*Freeze Mode1 were updated to add 1.5 V core voltage. Revision 5 (Jul 2008) Product Brief v1.1 DC and Switching Characteristics Advance v0.4 Table 2-19 * Different Components Contributing to Dynamic Power Consumption in ProASIC3L Devices at 1.5 V VCC is new. 2-14 Table 2-20 * Different Components Contributing to the Static Power Consumption in ProASIC3L Devices was updated to add the static PLL contribution at 1.5 V core operation. 2-14 Timing tables were updated to include tables for 1.5 V core voltage. N/A Table 2-212 * ProASIC3L CCC/PLL Specification was updated for core voltage 1.2 V and Table 2-213 * ProASIC3L CCC/PLL Specification for 1.5 V is new. 2-132, 2-133 As a result of the Libero IDE v8.4 release, Actel now offers a wide range of core voltage support. The document was updated to change 1.2 V / 1.5 V to 1.2 V to 1.5 V. N/A R ev i si o n 1 3 5 -5 Datasheet Information Revision Changes Revision 4 (June 2008) Tables have been updated to include the LVCMOS 1.2 V I/O set. DC and Switching Characteristics Advance v0.3 Page N/A DDR Tables have two additional data points added to reflect both edges for Input DDR setup and hold time. Power data table has been updated to match SmartPower data rather then simulation values. Table 2-1 * Absolute Maximum Ratings was updated to add VMV to the VCCI parameter row and to remove the word "output" from the parameter description for VCCI. Table note 3 was added. 2-1 Table 2-2 * Recommended Operating Conditions 1 was updated to add table note references and rearrange the order of notes. VMV was added to the VCCI parameter row. A new row was added for VCC, 1.5 V DC core supply voltage. The table note stating that 1.5 V data will be released at a later date is new. The table note on VMV pins is new. 2-2 Table 2-4 * Overshoot and Undershoot Limits 1. The title was revised to remove "as measured on quiet I/Os." Table note 2 was revised to remove "estimated SSO density over cycles." Table note 3 was revised to remove "refers only to overshoot/undershoot limits for simultaneous switching I/Os." 2-3 EQ 2 was updated. The temperature was changed to 100C, and therefore the end result changed. 2-6 The table notes for Table 2-8 * Quiescent Supply Current (IDD) Characteristics, ProASIC3L Flash*Freeze Mode* and Table 2-9 * Quiescent Supply Current (IDD) Characteristics, ProASIC3L Sleep Mode* were updated to remove VMV and include PDC6 and PDC7. The table note for Table 2-8 * Quiescent Supply Current (IDD) Characteristics, ProASIC3L Flash*Freeze Mode* was updated to include VJTAG. 2-7 Table 2-10 * Quiescent Supply Current (IDD) Characteristics, Shutdown Mode is new. 2-8 Note 2 of Table 2-11 * Quiescent Supply Current (IDD) Characteristics, No Flash*Freeze Mode1 was updated to include VCCPLL. Note 4 was updated to include PDC6 and PDC7. 2-8 Table 2-12 * Summary of I/O Input Buffer Power (per pin) - Default I/O Software Settings through Table 2-17 * Summary of I/O Output Buffer Power (per pin) - Default I/O Software Settings 1were updated to change PDC2 to PDC6 and PDC3 to PDC7. The table notes were updated to reflect that power was measured on VCCI. The subtitle of the table was changed from "Applicable to Advanced I/O Banks" to "Applicable to Pro I/O Banks." 2-9 through 2-12 The word "input" in the titles of Table 2-15 * Summary of I/O Output Buffer Power 2-11, 2-12 (per pin) - Default I/O Software Settings 1 and Table 2-16 * Summary of I/O Output Buffer Power (per pin) - Default I/O Software Settings 1, was changed to "output." The value of CLOAD for single-ended 3.3 V PCI was changed to 10 from 5 in Table 2-15 * Summary of I/O Output Buffer Power (per pin) - Default I/O Software Settings 1 through Table 2-17 * Summary of I/O Output Buffer Power (per pin) - Default I/O Software Settings 1. 5- 6 R ev isio n 1 3 2-11 through 2-12 ProASIC3L Low Power Flash FPGAs Revision Changes Page The last section of Table 2-18 * Different Components Contributing to Dynamic Power Consumption in ProASIC3L Devices at 1.2 V VCC was made into a new table: Table 2-19 * Different Components Contributing to Dynamic Power Consumption in ProASIC3L Devices at 1.5 V VCC. The table numbers referenced for device-specific dynamic power for PAC9 and PAC10 were changed in Table 2-18 * Different Components Contributing to Dynamic Power Consumption in ProASIC3L Devices at 1.2 V VCC. The definition of PDC5 was updated and parameters PDC6 and PDC7 were added to Table 2-20 * Different Components Contributing to the Static Power Consumption in ProASIC3L Devices. 2-13 The "Total Static Power Consumption--PSTAT" section was updated to revise the calculation of PSTAT, including PDC6 and PDC7. 2-15 Footnote 1 was updated to include information about PAC13. 2-16 Table 2-43 * Schmitt Trigger Input Hysteresis, Hysteresis Voltage Value (Typ) for Schmitt Mode Input Buffers was updated to include the hysteresis value for 1.2 V LVCMOS. 2-40 The "1.2 V LVCMOS (JESD8-12A)" section is new. 2-76 The product brief was divided into two sections and given a version number, starting at v1.0. The first section of the document includes features, benefits, ordering information, and temperature and speed grade offerings. The second section is a device family overview. N/A Product Brief v1.0 Packaging v1.1 The "FG324" package diagram was replaced. 4-29 Revision 2 (Apr 2008) Product Brief rev. 1 Reference to M1A3P250L was removed from Table 1 * ProASIC3 Low-Power I, II, III, IV Product Family, the "I/Os Per Package 1" table, the "ProASIC3L Ordering Information" section, and the "Temperature Grade Offerings" table. The table note regarding M1A3P250L was removed from the "I/Os Per Package 1" table. Revision 1 (Feb 2008) The "PLL Behavior at Brownout Condition" section is new. DC and Switching Characteristics Advance v0.2 Table 2-204 * A3P250L Global Resource - Applies to 1.5 V DC Core Voltage, Table 2-206 * A3P600L Global Resource - Applies to 1.5 V DC Core Voltage, Table 2-208 * A3P1000L Global Resource - Applies to 1.5 V DC Core Voltage, and Table 2-210 * A3PE3000L Global Resource - Applies to 1.5 V DC Core Voltage were updated with values for tRCKL, tRCKH, and tRCKSW. 2-128 - 2-131 The worst-case commercial conditions were added to Table 2-221 * Embedded FlashROM Access Time- Applies to 1.2 V DC Core Voltage. 2-148 Table 2-18 * Different Components Contributing to Dynamic Power Consumption in ProASIC3L Devices at 1.2 V VCC was updated to revise the value for PAC14 and add parameters PDC1 through PDC5 to the table. 2-13 Revision 4 (cont'd) Revision 3 (Apri2008) R ev i si o n 1 3 2-4 5 -7 Datasheet Information Datasheet Categories Categories In order to provide the latest information to designers, some datasheet parameters are published before data has been fully characterized from silicon devices. The data provided for a given device, as highlighted in the "ProASIC3L Device Status" table on page IV, is designated as either "Product Brief," "Advance," "Preliminary," or "Production." The definitions of these categories are as follows: Product Brief The product brief is a summarized version of a datasheet (advance or production) and contains general product information. This document gives an overview of specific device and family information. Advance This version contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production. This label only applies to the DC and Switching Characteristics chapter of the datasheet and will only be used when the data has not been fully characterized. Preliminary The datasheet contains information based on simulation and/or initial characterization. The information is believed to be correct, but changes are possible. Production This version contains information that is considered to be final. Export Administration Regulations (EAR) The products described in this document are subject to the Export Administration Regulations (EAR). They could require an approved export license prior to export from the United States. An export includes release of product or disclosure of technology to a foreign national inside or outside the United States. Safety Critical, Life Support, and High-Reliability Applications Policy The products described in this advance status document may not have completed the Microsemi qualification process. Products may be amended or enhanced during the product introduction and qualification process, resulting in changes in device functionality or performance. It is the responsibility of each customer to ensure the fitness of any product (but especially a new product) for a particular purpose, including appropriateness for safety-critical, life-support, and other high-reliability applications. Consult the Microsemi SoC Products Group Terms and Conditions for specific liability exclusions relating to life-support applications. A reliability report covering all of the SoC Products Group's products is available at http://www.microsemi.com/soc/documents/ORT_Report.pdf. Microsemi also offers a variety of enhanced qualification and lot acceptance screening procedures. Contact your local sales office for additional reliability information. 5- 8 R ev isio n 1 3 Microsemi Corporation (NASDAQ: MSCC) offers a comprehensive portfolio of semiconductor solutions for: aerospace, defense and security; enterprise and communications; and industrial and alternative energy markets. Products include high-performance, high-reliability analog and RF devices, mixed signal and RF integrated circuits, customizable SoCs, FPGAs, and complete subsystems. Microsemi is headquartered in Aliso Viejo, Calif. Learn more at www.microsemi.com. Microsemi Corporate Headquarters One Enterprise, Aliso Viejo CA 92656 USA Within the USA: +1 (949) 380-6100 Sales: +1 (949) 380-6136 Fax: +1 (949) 215-4996 (c) 2012 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are trademarks of Microsemi Corporation. All other trademarks and service marks are the property of their respective owners. 51700100-13/01.13