©2012-2015 Peregrine Semiconductor Corp. All rights reserved.
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Document No. DOC-33314-2 | www.psemi.com
Product Specification
UltraCMOS® SPDT RF Switch
5–6000 MHz
PE42422
Features
Symmetric SPDT reflective switch
Low insertion loss
0.25 dB typical @ 1000 MHz
0.40 dB typical @ 3000 MHz
0.65 dB typical @ 5000 MHz
0.90 dB typical @ 6000 MHz
Wide supply range of 2.3V to 5.5V
Excellent linearity
IIP2 of 115 dBm
IIP3 of 70 dBm
High ESD tolerance
4kV HBM on RF pins to GND
1kV on all other pins
Logic Select (LS) pin provides
maximum flexibility of control logic
12-lead 2x2 mm QFN package
Figure 2. Package Type
12-lead 2x2x0.55 mm QFN
Figure 1. Functional Diagram
Product Description
The PE42422 is a HaRP™ technology-enhanced
SPDT RF switch designed to cover a broad range of
applications from 5–6000 MHz. This reflective switch
integrates on-board CMOS control logic with a low
voltage CMOS-compatible control interface and
requires no external components.
Peregrine’s HaRP technology enhancements deliver
high linearity and exceptional harmonics performance.
It is an innovative feature of the UltraCMOS® process,
providing performance superior to GaAs with the
economy and integration of conventional CMOS.
71-0068
Product Specification
PE42422
Document No. DOC-33314-2 | UltraCMOS® RFIC Solutions
Page 2 of 13
©2012-2015 Peregrine Semiconductor Corp. All rights reserved.
Table 1. Electrical Specifications Temp = +25°C1, VDD = 2.3V to 5.5V (ZS = ZL = 50Ω)
Parameter Path Condition Min Typ Max Units
Operational Frequency 5 6000 MHz
Insertion Loss2 RFX to RFC
100–1000 MHz 0.25 0.35 dB
1000–2000 MHz 0.30 0.40 dB
2000–3000 MHz 0.40 0.50 dB
3000–4000 MHz 0.50 0.70 dB
4000–5000 MHz 0.65 0.902 dB
5000–6000 MHz 0.90 1.252 dB
Isolation RFX to RFC
100–1000 MHz 42 44 dB
1000–2000 MHz 33 35 dB
2000–3000 MHz 27 29 dB
3000–4000 MHz 22 24 dB
4000–5000 MHz 18 20 dB
5000–6000 MHz 15 17 dB
Isolation RFX to RFX
100–1000 MHz 40 41 dB
1000–2000 MHz 32 33 dB
2000–3000 MHz 26 28 dB
3000–4000 MHz 22 24 dB
4000–5000 MHz 18 20 dB
5000–6000 MHz 15 16 dB
Return Loss2 RFX to RFC
100-1000 MHz 28 dB
1000–2000 MHz 21 dB
2000–3000 MHz 20 dB
3000–4000 MHz 18 dB
4000–5000 MHz 162 dB
5000–6000 MHz 132 dB
2nd Harmonic RFX-RFC +32 dBm output power, 850 / 900 MHz –99 dBc
+32 dBm output power, 1800 / 1900 MHz –101 dBc
3rd Harmonic RFX-RFC +32 dBm output power, 850 / 900 MHz –93 dBc
+32 dBm output power, 1800 / 1900 MHz –87 dBc
IMD3 RF-RFC
Bands I, II, V, VIII +17 dBm CW @ TX freq at RFC,
–15 dBm CW @ 2Tx-Rx at RFC, 50Ω –115 dBm
IIP23 RFX 100–6000 MHz 115 dBm
IIP33 RFX 100–6000 MHz 70 dBm
Input 0.1 dB Compression3 RFX or RFC 100–6000 MHz 34 dBm
Switching Time 50% CTRL to (10%–90%) or (90%–10%) RF 2 4 μs
5–100 MHz 0.23 dB
5–100 MHz 68 dB
5–100 MHz 61 dB
5–100 MHz 33 dB
Notes: 1. Typical performance over temperature and VDD shown in Figure 4 through Figure 20.
2. High frequency performance can be improved by external matching (see Figure 21 through Figure 26 and Figure 29).
3. Device linearity will begin to degrade below 25 MHz.
Product Specification
PE42422
©2012-2015 Peregrine Semiconductor Corp. All rights reserved.
Page 3 of 13
Document No. DOC-33314-2 | www.psemi.com
Table 5. Absolute Maximum Ratings
Notes: 1. VDD within operating range specified in Table 4.
2. HBM ESD Voltage (MIL_STD 883 Method 3015.7).
3. MM ESD Voltage (JEDEC JESD22-A115-A).
4. Device linearity will begin to degrade below 25 MHz.
Table 4. Operating Ranges
Parameter Min Typ Max Units
VDD Supply Voltage 2.3 3.3 5.5 V
IDD Power Supply Current 120 200 µA
RFX–RFC input power (50Ω) +32 dBm
Control Voltage High 1.2 1.5 3.3 V
Control Voltage Low 0 0 0.5 V
Operating temperature range –40 +25 +85 °C
Parameter/Conditions Min Units
PMAX Input Power1,4 dBm
ESD Voltage HBM2
RF pins to GND
All other pins
V
V
ESD Voltage MM, all pins3 V
Max
+32
4000
1000
200
TST Storage Temperature -65 +150 °C
Figure 3. Pin Configuration (Top View)
Table 2. Pin Descriptions
Pin No. Pin Name Description
1 GND Ground
2 RF21 RF Port 2
3 GND Ground
4 GND Ground
5 RFC1 RF Common
6 GND Ground
7 GND Ground
8 RF11 RF Port 1
9 DGND Digital Ground
10 V1 Switch control input, CMOS logic level
11 LS Logic Select, CMOS logic level
12 VDD Supply
Paddle GND Ground for proper device operation
Note 1: Blocking capacitors needed only when non-zero DC voltage present.
Table 3. Truth Table
Path V1 LS
RFC–RF2 1 1
RFC–RF1 0 1
RFC–RF1 1 0
RFC–RF2 0 0
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS®
devices are immune to latch-up.
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS® device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the specified rating.
Moisture Sensitivity Level
The Moisture Sensitivity Level rating for the
PE42422 in the 12-lead 2x2x0.55 mm QFN
package is MSL1.
Exceeding absolute maximum ratings may cause
permanent damage. Operation should be restricted
to the limits in the Operating Ranges table.
Product Specification
PE42422
Document No. DOC-33314-2 | UltraCMOS® RFIC Solutions
Page 4 of 13
©2012-2015 Peregrine Semiconductor Corp. All rights reserved.
Typical Performance Data @ +25°C and VDD = 3.3V unless otherwise specified
Figure 4. Insertion Loss RFX1
Figure 5. Insertion Loss vs Temp (RF1-RFC)1
Figure 6. Insertion Loss vs Temp (RF2-RFC)1
Note 1: High frequency performance can be improved by external matching (see Figure 21 through Figure 26 and Figure 29).
Figure 7. Insertion Loss vs VDD (RF1-RFC)1
Figure 8. Insertion Loss vs VDD (RF2-RFC)1
Product Specification
PE42422
©2012-2015 Peregrine Semiconductor Corp. All rights reserved.
Page 5 of 13
Document No. DOC-33314-2 | www.psemi.com
Figure 9. RFX-RFX Isolation vs Temp
Figure 11. RFC-RFX Isolation vs Temp Figure 12. RFC-RFX Isolation vs VDD
Figure 10. RFX-RFX Isolation vs VDD
Typical Performance Data @ +25°C and VDD = 3.3V unless otherwise specified
Product Specification
PE42422
Document No. DOC-33314-2 | UltraCMOS® RFIC Solutions
Page 6 of 13
©2012-2015 Peregrine Semiconductor Corp. All rights reserved.
Figure 13. RFC Port Return Loss vs Temp
(RF1 Active)1
Figure 14. RFC Port Return Loss vs VDD
(RF1 Active)1
Figure 15. RFC Port Return Loss vs Temp
(RF2 Active)1
Figure 16. RFC Port Return Loss vs VDD
(RF2 Active)1
Typical Performance Data @ +25°C and VDD = 3.3V unless otherwise specified
Note 1: High frequency performance can be improved by external matching (see Figure 21 through Figure 26 and Figure 29).
Product Specification
PE42422
©2012-2015 Peregrine Semiconductor Corp. All rights reserved.
Page 7 of 13
Document No. DOC-33314-2 | www.psemi.com
Typical Performance Data @ +25°C and VDD = 3.3V unless otherwise specified
Figure 17. Active Port Return Loss vs Temp
(RF1 Active)1
Figure 18. Active Port Return Loss vs VDD
(RF1 Active)1
Figure 20. Active Port Return Loss vs VDD
(RF2 Active)1
Figure 19. Active Port Return Loss vs Temp
(RF2 Active)1
Note 1: High frequency performance can be improved by external matching (see Figure 21 through Figure 26 and Figure 29).
Product Specification
PE42422
Document No. DOC-33314-2 | UltraCMOS® RFIC Solutions
Page 8 of 13
©2012-2015 Peregrine Semiconductor Corp. All rights reserved.
Performance Comparison @ +25°C and VDD = 3.3V with or without matching
Note 1: High frequency performance can be improved by external matching (see Figure 21 through Figure 26 and Figure 29).
Figure 21. Insertion Loss RF11 Figure 22. Insertion Loss RF21
Figure 24. Active Port Return Loss (RF2 Active)1 Figure 23. Active Port Return Loss (RF1 Active)1
Figure 25. RFC Port Return Loss (RF1 Active)1 Figure 26. RFC Port Return Loss (RF2 Active)1
Product Specification
PE42422
©2012-2015 Peregrine Semiconductor Corp. All rights reserved.
Page 9 of 13
Document No. DOC-33314-2 | www.psemi.com
Evaluation Board Figure 27. Evaluation Board Layout
The SPDT switch evaluation board was designed to
ease customer evaluation of Peregrine’s PE42422.
The RF common port is connected through a 50Ω
transmission line via the top SMA connector, J2.
RF1 and RF2 ports are connected through 50Ω
transmission lines via SMA connectors J1 and J3,
respectively. A through 50Ω transmission is
available via SMA connectors J4 and J5. This
transmission line can be used to estimate the loss
of the PCB over the environmental conditions being
evaluated. J8 provides DC and digital inputs to the
device.
The board is constructed of a four metal layer
material with a total thickness of 62 mils. The top
and bottom RF layers are Rogers RO4350 material
with a 10 mil RF core. The middle layers provide
ground for the transmission lines. The transmission
lines were designed using a coplanar waveguide
with ground plane model using a trace width of
22 mils, trace gaps of 7 mils, and metal thickness of
2.1 mils.
PRT-29005
Product Specification
PE42422
Document No. DOC-33314-2 | UltraCMOS® RFIC Solutions
Page 10 of 13
©2012-2015 Peregrine Semiconductor Corp. All rights reserved.
Figure 28. Evaluation Board Schematic
50 OHM 50 OHM
50 OHM
V1
V2
V3
V4
V5
V5
V4
V3
V2
V1 V1
V2
MUX2
MUX1
VDD
50 OHM
1
1
3
3
5
5
7
7
22
44
66
88
10 10 9
9
J8
HEADER 10
R2 S.A.T.
J2
SMA
J1
SMA
J3
SMA
R1 S.A.T.
7GND
9DGND
11 LS
12 VDD
2
RF2
3
GND
4
GND
1
GND
8RF1
10 V1
5
RFC
6
GND
U1
PE42422_QFN_12L_2X2
C3
DNI
C2
DNI
C1
DNI
C5
DNI
C4
DNI
J4
SMA
J5
SMA
RF1 RF2
RFC/ANT
DOC-33327
Product Specification
PE42422
©2012-2015 Peregrine Semiconductor Corp. All rights reserved.
Page 11 of 13
Document No. DOC-33314-2 | www.psemi.com
50 OHM 50 OHM
50 OHM
V1
V2
V3
V4
V5
V5
V4
V3
V2
V1 V1
V2
MUX2
MUX1
VDD
50 OHM
DIST. FROM PART EDGE TO C6 = 134 mils
1
1
3
3
5
5
7
7
22
44
66
88
10 10 9
9
J8
HEADER 10
R2 S.A.T.
J2
SMA
J1
SMA
J3
SMA
R1 S.A.T.
7GND
9DGND
11 LS
12 VDD
2
RF2
3
GND
4
GND
1
GND
8RF1
10 V1
5
RFC
6
GND
U1
PE42422_QFN_12L_2X2
C3
DNI
C2
DNI
C1
DNI
C5
DNI
C4
DNI
J4
SMA
J5
SMA
C6
0.25pF
RF1 RF2
RFC/ANT
Figure 29. Evaluation Board Schematic with Matching
DOC-33327
Product Specification
PE42422
Document No. DOC-33314-2 | UltraCMOS® RFIC Solutions
Page 12 of 13
©2012-2015 Peregrine Semiconductor Corp. All rights reserved.
2.00
2.00
A
0.10 C
C
0.10 C
TOP VIEW
SIDE VIEW
BOTTOM VIEW
0.05 C
SEATING PLANE
PIN #1 Identifier
B
(X2)
0.10 C A B
0.05 C
ALL FEATURES
RECOMMENDED LAND PATTERN
0.10 C
(X2)
1.10±0.05
1.10±0.05
0.50
0.20±0.05
(X12) 0.275±0.05
(X12)
1.00
1
3
4
6
79
10
12
2.40
0.475
(X12)
0.25
(X12)
0.50
1.10
2.40
1.10
0.152 REF. 0.05 MAX
0.60 MAX
Figure 30. Package Drawing
12-lead 2x2x0.55 mm QFN
DOC-01882
Figure 31. Top Marking Specifications
PPZZ
YWW
Marking Spec
Symbol
Package
Marking Definition
PP DE Part number marking for PE42422
ZZ 00-99 Last two digits of lot code
Y 0-9 Last digit of year, starting from 2009
(0 for 2010, 1 for 2011, etc)
WW 01-53 Work week
17-0112
Product Specification
PE42422
©2012-2015 Peregrine Semiconductor Corp. All rights reserved.
Page 13 of 13
Document No. DOC-33314-2 | www.psemi.com
Figure 32. Tape and Reel Specifications
12-lead 2x2x0.55 mm QFN
Device Orientation in Tape
Top of
Device
Pin 1
Nominal Tolerance
Ao 2.20 ±0.1
Bo 2.20 ±0.1
Ko 0.75 ±0.1
Tape Feed Direction
Table 6. Ordering Information
Order Code Description Package Shipping Method
PE42422MLAA-Z PE42422 SPDT RF Switch Green 12-lead 2x2mm QFN 3000 units T/R
EK42422-01 PE42422 Evaluation board Evaluation Kit 1/Box
Advance Information:
The product is in a formative or design stage. The datasheet contains design target
specifications for product development. Specifications and features may change in any manner without notice.
Preliminary Specification:
The datasheet contains preliminary data. Additional data may be added at a later
date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best
possible product.
Product Specification:
The datasheet contains final data. In the event Peregrine decides to
change the specifications, Peregrine will notify customers of the intended changes by issuing a CNF (Customer
Notification Form).
The information in this datasheet is believed to be reliable. However, Peregrine assumes no liability for the use
of this information. Use shall be entirely at the user’s own risk.
No patent rights or licenses to any circuits described in this datasheet are implied or granted to any third party.
Peregrine’s products are not designed or intended for use in devices or systems intended for surgical implant,
or in other applications intended to support or sustain life, or in any application in which the failure of the
Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no
liability for damages, including consequential or incidental damages, arising out of the use of its products in
such applications.
The Peregrine name, logo, UltraCMOS and UTSi are registered trademarks and HaRP, MultiSwitch and DuNE
are trademarks of Peregrine Semiconductor Corp.
Peregrine products are protected under one or more of
the following U.S. Patents: http://patents.psemi.com.
Sales Contact and Information
For sales and contact information please visit www.psemi.com.
