Product Specification PE42422 UltraCMOS(R) SPDT RF Switch 5-6000 MHz Product Description The PE42422 is a HaRPTM technology-enhanced SPDT RF switch designed to cover a broad range of applications from 5-6000 MHz. This reflective switch integrates on-board CMOS control logic with a low voltage CMOS-compatible control interface and requires no external components. Peregrine's HaRP technology enhancements deliver high linearity and exceptional harmonics performance. It is an innovative feature of the UltraCMOS(R) process, providing performance superior to GaAs with the economy and integration of conventional CMOS. Features Symmetric SPDT reflective switch Low insertion loss 0.25 dB typical @ 0.40 dB typical @ 0.65 dB typical @ 0.90 dB typical @ Figure 1. Functional Diagram 1000 MHz 3000 MHz 5000 MHz 6000 MHz Wide supply range of 2.3V to 5.5V Excellent linearity IIP2 of 115 dBm IIP3 of 70 dBm High ESD tolerance 4kV HBM on RF pins to GND 1kV on all other pins Logic Select (LS) pin provides maximum flexibility of control logic 12-lead 2x2 mm QFN package Figure 2. Package Type 12-lead 2x2x0.55 mm QFN 71-0068 Document No. DOC-33314-2 | www.psemi.com (c)2012-2015 Peregrine Semiconductor Corp. All rights reserved. Page 1 of 13 PE42422 Product Specification Table 1. Electrical Specifications Temp = +25C1, VDD = 2.3V to 5.5V (ZS = ZL = 50) Parameter Path Condition Min Operational Frequency Insertion Loss Typ 5 2 RFX to RFC 100-1000 MHz 0.25 0.35 dB 1000-2000 MHz 0.30 0.40 dB 2000-3000 MHz 0.40 0.50 dB 3000-4000 MHz 0.50 0.70 dB 0.65 2 dB 2 dB 0.90 5-100 MHz RFX to RFX Return Loss2 RFX to RFC dB 0.90 1.25 68 dB 100-1000 MHz 42 44 dB 1000-2000 MHz 33 35 dB 2000-3000 MHz 27 29 dB 3000-4000 MHz 22 24 dB 4000-5000 MHz 18 20 dB 5000-6000 MHz 15 5-100 MHz Isolation MHz 0.23 5000-6000 MHz RFX to RFC Units 5-100 MHz 4000-5000 MHz Isolation Max 6000 17 dB 61 dB 100-1000 MHz 40 41 dB 1000-2000 MHz 32 33 dB 2000-3000 MHz 26 28 dB 3000-4000 MHz 22 24 dB 4000-5000 MHz 18 20 dB 5000-6000 MHz 15 16 dB 5-100 MHz 33 dB 100-1000 MHz 28 dB 1000-2000 MHz 21 dB 2000-3000 MHz 20 dB 3000-4000 MHz 18 dB 4000-5000 MHz 2 dB 2 13 dB +32 dBm output power, 850 / 900 MHz -99 dBc +32 dBm output power, 1800 / 1900 MHz -101 dBc +32 dBm output power, 850 / 900 MHz -93 dBc +32 dBm output power, 1800 / 1900 MHz -87 dBc 16 5000-6000 MHz 2nd Harmonic RFX-RFC 3rd Harmonic RFX-RFC IMD3 RF-RFC Bands I, II, V, VIII +17 dBm CW @ TX freq at RFC, -15 dBm CW @ 2Tx-Rx at RFC, 50 -115 dBm IIP23 RFX 100-6000 MHz 115 dBm RFX 100-6000 MHz 70 dBm RFX or RFC 100-6000 MHz 34 dBm 50% CTRL to (10%-90%) or (90%-10%) RF 2 IIP3 3 Input 0.1 dB Compression Switching Time Notes: 3 4 s 1. Typical performance over temperature and VDD shown in Figure 4 through Figure 20. 2. High frequency performance can be improved by external matching (see Figure 21 through Figure 26 and Figure 29). 3. Device linearity will begin to degrade below 25 MHz. (c)2012-2015 Peregrine Semiconductor Corp. All rights reserved. Page 2 of 13 Document No. DOC-33314-2 | UltraCMOS(R) RFIC Solutions PE42422 Product Specification Figure 3. Pin Configuration (Top View) Table 4. Operating Ranges Parameter VDD Supply Voltage Min Typ Max Units 2.3 3.3 5.5 V 120 200 A +32 dBm IDD Power Supply Current RFX-RFC input power (50 ) Control Voltage High 1.2 1.5 3.3 V Control Voltage Low 0 0 0.5 V -40 +25 +85 C Operating temperature range Table 5. Absolute Maximum Ratings Parameter/Conditions Table 2. Pin Descriptions Min Max Units PMAX Input Power1,4 +32 dBm 4000 1000 V V 200 V +150 C Pin No. Pin Name 1 GND Ground ESD Voltage HBM2 RF pins to GND All other pins 2 RF21 RF Port 2 ESD Voltage MM, all pins3 3 GND Ground 4 GND Ground 5 RFC1 RF Common 6 GND Ground 7 GND Ground 8 1 RF1 9 DGND 10 V1 Switch control input, CMOS logic level 11 LS Logic Select, CMOS logic level 12 VDD Supply Electrostatic Discharge (ESD) Precautions Paddle GND Ground for proper device operation When handling this UltraCMOS(R) device, observe the same precautions that you would use with other ESD-sensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the specified rating. Description TST Storage Temperature Notes: -65 1. VDD within operating range specified in Table 4. 2. HBM ESD Voltage (MIL_STD 883 Method 3015.7). 3. MM ESD Voltage (JEDEC JESD22-A115-A). 4. Device linearity will begin to degrade below 25 MHz. RF Port 1 Digital Ground Note 1: Blocking capacitors needed only when non-zero DC voltage present. Table 3. Truth Table Path V1 LS RFC-RF2 1 1 RFC-RF1 0 1 RFC-RF1 1 0 RFC-RF2 0 0 Exceeding absolute maximum ratings may cause permanent damage. Operation should be restricted to the limits in the Operating Ranges table. Latch-Up Avoidance Unlike conventional CMOS devices, UltraCMOS(R) devices are immune to latch-up. Moisture Sensitivity Level The Moisture Sensitivity Level rating for the PE42422 in the 12-lead 2x2x0.55 mm QFN package is MSL1. Document No. DOC-33314-2 | www.psemi.com (c)2012-2015 Peregrine Semiconductor Corp. All rights reserved. Page 3 of 13 PE42422 Product Specification Typical Performance Data @ +25C and VDD = 3.3V unless otherwise specified Figure 4. Insertion Loss RFX1 Figure 5. Insertion Loss vs Temp (RF1-RFC)1 Figure 7. Insertion Loss vs VDD (RF1-RFC)1 Figure 6. Insertion Loss vs Temp (RF2-RFC)1 Figure 8. Insertion Loss vs VDD (RF2-RFC)1 Note 1: High frequency performance can be improved by external matching (see Figure 21 through Figure 26 and Figure 29). (c)2012-2015 Peregrine Semiconductor Corp. All rights reserved. Page 4 of 13 Document No. DOC-33314-2 | UltraCMOS(R) RFIC Solutions PE42422 Product Specification Typical Performance Data @ +25C and VDD = 3.3V unless otherwise specified Figure 9. RFX-RFX Isolation vs Temp Figure 10. RFX-RFX Isolation vs VDD Figure 11. RFC-RFX Isolation vs Temp Figure 12. RFC-RFX Isolation vs VDD Document No. DOC-33314-2 | www.psemi.com (c)2012-2015 Peregrine Semiconductor Corp. All rights reserved. Page 5 of 13 PE42422 Product Specification Typical Performance Data @ +25C and VDD = 3.3V unless otherwise specified Figure 13. RFC Port Return Loss vs Temp (RF1 Active)1 Figure 14. RFC Port Return Loss vs VDD (RF1 Active)1 Figure 15. RFC Port Return Loss vs Temp (RF2 Active)1 Figure 16. RFC Port Return Loss vs VDD (RF2 Active)1 Note 1: High frequency performance can be improved by external matching (see Figure 21 through Figure 26 and Figure 29). (c)2012-2015 Peregrine Semiconductor Corp. All rights reserved. Page 6 of 13 Document No. DOC-33314-2 | UltraCMOS(R) RFIC Solutions PE42422 Product Specification Typical Performance Data @ +25C and VDD = 3.3V unless otherwise specified Figure 17. Active Port Return Loss vs Temp (RF1 Active)1 Figure 18. Active Port Return Loss vs VDD (RF1 Active)1 Figure 19. Active Port Return Loss vs Temp (RF2 Active)1 Figure 20. Active Port Return Loss vs VDD (RF2 Active)1 Note 1: High frequency performance can be improved by external matching (see Figure 21 through Figure 26 and Figure 29). Document No. DOC-33314-2 | www.psemi.com (c)2012-2015 Peregrine Semiconductor Corp. All rights reserved. Page 7 of 13 PE42422 Product Specification Performance Comparison @ +25C and VDD = 3.3V with or without matching Figure 21. Insertion Loss RF11 Figure 22. Insertion Loss RF21 Figure 23. Active Port Return Loss (RF1 Active)1 Figure 24. Active Port Return Loss (RF2 Active)1 Figure 25. RFC Port Return Loss (RF1 Active)1 Figure 26. RFC Port Return Loss (RF2 Active)1 Note 1: High frequency performance can be improved by external matching (see Figure 21 through Figure 26 and Figure 29). (c)2012-2015 Peregrine Semiconductor Corp. All rights reserved. Page 8 of 13 Document No. DOC-33314-2 | UltraCMOS(R) RFIC Solutions PE42422 Product Specification Evaluation Board The SPDT switch evaluation board was designed to ease customer evaluation of Peregrine's PE42422. The RF common port is connected through a 50 transmission line via the top SMA connector, J2. RF1 and RF2 ports are connected through 50 transmission lines via SMA connectors J1 and J3, respectively. A through 50 transmission is available via SMA connectors J4 and J5. This transmission line can be used to estimate the loss of the PCB over the environmental conditions being evaluated. J8 provides DC and digital inputs to the device. Figure 27. Evaluation Board Layout The board is constructed of a four metal layer material with a total thickness of 62 mils. The top and bottom RF layers are Rogers RO4350 material with a 10 mil RF core. The middle layers provide ground for the transmission lines. The transmission lines were designed using a coplanar waveguide with ground plane model using a trace width of 22 mils, trace gaps of 7 mils, and metal thickness of 2.1 mils. PRT-29005 Document No. DOC-33314-2 | www.psemi.com (c)2012-2015 Peregrine Semiconductor Corp. All rights reserved. Page 9 of 13 PE42422 Product Specification Figure 28. Evaluation Board Schematic SMA RFC/ANT J2 GND GND 3 VDD V1 V2 V3 V4 V5 V1 V2 MUX2 MUX1 VDD DOC-33327 C1 DNI C2 DNI (c)2012-2015 Peregrine Semiconductor Corp. All rights reserved. Page 10 of 13 RF2 12 LS 11 V1 J8 V5 V4 V3 V2 V1 S.A.T. 10 HEADER10 9 7 5 3 1 R2 9 7 5 3 1 S.A.T. 10 8 6 4 2 J3 SMA 50 OHM U1 2 RF1 RF2 PE42422_QFN_12L_2X2 9 1 DGND GND R1 10 8 6 4 2 RFC GND 8 RF1 J5 SMA 4 DNI 5 DNI 6 C4 7 50 OHM 50 OHM 50 OHM C5 GND J1 SMA J4 SMA C3 DNI Document No. DOC-33314-2 | UltraCMOS(R) RFIC Solutions PE42422 Product Specification Figure 29. Evaluation Board Schematic with Matching SMA RFC/ANT J2 J4 SMA 50 OHM J5 SMA 50 OHM C4 C5 DNI DNI J1 SMA 7 50 OHM 4 GND 5 DIST. FROMPARTEDGE TOC6 = 134 mils 0.25pF GND GND 3 Document No. DOC-33314-2 | VDD RF2 12 11 V1 J8 S.A.T. 10 HEADER10 R2 V5 V4 V3 V2 V1 S.A.T. 9 7 5 3 1 R1 9 7 5 3 1 LS U1 2 RF1 RF2 PE42422_QFN_12L_2X2 1 9 GND DGND 10 8 6 4 2 J3 SMA 50 OHM 8 RF1 10 8 6 4 2 RFC GND 6 C6 V1 V2 V3 V4 V5 V1 V2 MUX2 MUX1 VDD DOC-33327 C1 DNI www.psemi.com C2 DNI C3 DNI (c)2012-2015 Peregrine Semiconductor Corp. All rights reserved. Page 11 of 13 PE42422 Product Specification Figure 30. Package Drawing 12-lead 2x2x0.55 mm QFN 0.25 (X12) 0.10 C A 2.00 (X2) 0.475 (X12) B 1.100.05 9 7 0.50 10 6 1.100.05 2.00 0.200.05 (X12) 0.10 C 0.50 4 1.10 2.40 12 1 3 (X2) 1.00 0.2750.05 (X12) 1.10 2.40 PIN #1 Identifier TOP VIEW BOTTOM VIEW RECOMMENDED LAND PATTERN DOC-01882 0.10 C 0.60 MAX 0.05 C 0.10 C A B 0.05 C ALL FEATURES SEATING PLANE 0.152 REF. SIDE VIEW 0.05 MAX C Figure 31. Top Marking Specifications PPZZ YWW Marking Spec Symbol Package Marking PP DE ZZ 00-99 Y 0-9 WW 01-53 Definition Part number marking for PE42422 Last two digits of lot code Last digit of year, starting from 2009 (0 for 2010, 1 for 2011, etc) Work week 17-0112 (c)2012-2015 Peregrine Semiconductor Corp. All rights reserved. Page 12 of 13 Document No. DOC-33314-2 | UltraCMOS(R) RFIC Solutions PE42422 Product Specification Figure 32. Tape and Reel Specifications 12-lead 2x2x0.55 mm QFN Tape Feed Direction Pin 1 Nominal Tolerance Ao 2.20 0.1 Bo 2.20 0.1 Ko 0.75 0.1 Top of Device Device Orientation in Tape Table 6. Ordering Information Order Code Description Package Shipping Method PE42422MLAA-Z PE42422 SPDT RF Switch Green 12-lead 2x2mm QFN 3000 units T/R EK42422-01 PE42422 Evaluation board Evaluation Kit 1/Box Sales Contact and Information For sales and contact information please visit www.psemi.com. Advance Information: The product is in a formative or design stage. The datasheet contains design target specifications for product development. Specifications and features may change in any manner without notice. Preliminary Specification: The datasheet contains preliminary data. Additional data may be added at a later date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. Product Specification: The datasheet contains final data. In the event Peregrine decides to change the specifications, Peregrine will notify customers of the intended changes by issuing a CNF (Customer Notification Form). The information in this datasheet is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be entirely at the user's own risk. Document No. DOC-33314-2 | www.psemi.com No patent rights or licenses to any circuits described in this datasheet are implied or granted to any third party. Peregrine's products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. The Peregrine name, logo, UltraCMOS and UTSi are registered trademarks and HaRP, MultiSwitch and DuNE are trademarks of Peregrine Semiconductor Corp. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com. (c)2012-2015 Peregrine Semiconductor Corp. All rights reserved. Page 13 of 13