PD69104B1/F 4 Port PSE PoE Manager D ATASHEET Introduction DESCRIPTION KEY FEATURES The PD69104B1 device is a 4 port, mixed-signal, high-voltage PoE Manager. The PD69104B1 supports 2 modes of operation: MSCC Extended Auto mode - this is a stand-alone mode in which the PD69104B detects IEEE802.3af-2003 compliant PDs (Powered Devices) and IEEE802.3at-2009 High Power devices, ensuring safe power feeding and disconnection of ports based on a power management algorithm while employing a minimum of external components. Semi Auto mode - allows the host to control which devices are powered and which are not, as well as to communicate with the PD69104B1 and to configure it Auto mode - allows turning PDs on and off automatically. Used for systems with a full power supply. The PD69104B1 executes all real time functions as specified in the IEEE802.3af-2003 ("AF") and IEEE802.3at High Power ("AT") standards, including load detection, "AF" and "AT" classifications, and using Multiple Classification Attempts (MCA). The PD69104B1, supports detect legacy/pre-standard PD devices. It also provides PD real-time protection through the following mechanisms: overload, under-load, over-voltage, over-temperature, and short-circuit. The PD69104B1 supports supply voltages between 44V and 57V with no need for additional power supply sources and has a built-in thermal protection. The PD69104B1 is a low power device that uses internal MOSFETs and external 0.36 sense resistors. Supports IEEE802.3af and IEEE802.3at, including two-event classification MSCC Extended Auto, Semi Auto, and Auto modes Supports pre-standard PD detection Supports Cisco devices detection Single DC voltage input (44V to 57V) Wide temperature range: -10 to +85C PD69104B1F version covering -40C to +85C Low power dissipation (0.36 sense resistor) Drives independent 4/2-pairs power port Supports Extended PoE Protocol and Register Map Includes 2 selectable communication modes (I2C and UART) Includes Reset command pin integrated with an RPD/MRPD mechanism Continuous monitoring port and system data Parameter setting using input pins Parameters setting from external serial EEPROM device Built-in Dynamic Power Management and Emergency Power Management mechanisms with 4 x Power Supply Power Good pins Power soft start mechanism On-chip thermal protection On-chip continual thermal monitoring Voltage/current and temperature monitoring/protection Built-in 3.3V and 5V regulators Internal power on reset MSL1, RoHS compliant W W W. Microsemi .CO M Microsemi's PD69104B1 Power over Ethernet (PoE) Manager enables network devices to share power and data over a single cable. The PD69104B1 PoE Manager chip is employed by both Ethernet switches and Midspans. The device integrates power, analog circuitry and state of the art control logic into a single 48-pin plastic QFN package. The PD69104B1 is available in 48 leads, 8 mm x 8 mm QFN package. IMPORTANT: For the most current data, consult MICROSEMI's website: http://www.microsemi.com T H ERM AL D AT A Plastic 48 pin QFN 8x8 mm THERMAL RESISTANCE-JUNCTION TO AMBIENT RoHS Compliant / Pb-free, MSL1 THERMAL RESISTANCE-JUNCTION TO CASE -10 to +85 PD69104B1ILQ Junction Temperature Calculation: T J = TA + (PD x JA). -40 to +85 PD69104B1FILQ TA (C) Note: Available in Tape and Reel. Append the letters "TR" to the part number. ( i.e. PD69104B1ILQ-TR ) 25 C/W 4 C/W The JA numbers are guidelines for the thermal performance of the device/pc-board system. All of the above assume no ambient airflow. Copyright (c) 2013 Microsemi Rev. 1.3 Analog Mixed Signal Group 1 Enterprise, Aliso Viejo, CA 92656, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308 1 PD69104B1/F P AC K AG E O R D ER IN FO PD69104B1/F 4 Port PSE PoE Manager D ATASHEET TYPICAL POWER DISSIPATION INFORMATION 2 W W W. Microsemi .CO M Rsense Power Dissipation: 0.36 x Iport 2 Rds_ON Power Dissipation: 0.3 x Iport Pport_AF = 15.4W ==> Port Power Dissipation @ Rsense = 37mW (320mA) Port Power Dissipation @ Rds_ON = 31mW (320mA) Pport_AT = 30W ==> Port Power Dissipation @ Rsense = 130mW (600mA) Port Power Dissipation @ Rds_ON = 108mW (600mA) Using Internal 3.3V regulator Typical PD69104B1 self power dissipation (including internal regulations) = 0.5W (50V) Typical PD69104B1 @ 4 x Port AF application power dissipation = 0.5W + 4 x 31mW + 4 x 37mW = 0.77W Typical PD69104B1 @ 4 x Port AT application power dissipation = 0.5W + 4 x 108mW + 4 x 130mW = 1.45W Using External 3.3V regulator Typical PD69104B1 self power dissipation (external 3.3V source) = 0.25W (50V) Typical PD69104B1 @ 4 x Port AF application power dissipation = 0.25W + 4 x 31mW + 4 x 37mW = 0.52W Typical PD69104B1 @ 4 x Port AT application power dissipation = 0.25W + 4 x 108mW + 4 x 130mW = 1.2W I2C_SDA_in / Rx I2C_SDA_out / Tx I2C_SCL DGND DVDD E2_SDA PS_PGD3 / E2_SCL PS_PGD2 PS_PGD1 PS_PGD0 MODE1 MODE0 48 47 46 45 44 43 42 41 40 39 38 37 24 12 MAX_LED VPORT_NEG1 Date Code 23 11 TRIM PORT_SENSE1 22 10 IREF VPORT_NEG0 21 9 QGND PORT_SENSE0 20 8 VAUX3P3 LED1 PD69104B1/F 19 7 VAUX3P3_INT LED0 18 6 AGND AGND MSC 17 5 DRV_VAUX5 ADD3 16 4 VAUX5 ADD2 14 3 13 +160C 2 ADD1 15 -40 to +85C 1 ADD0 NC -10 to +85C RESET_N VMAIN -0.3VDC to 74VDC -0.3VDC to 74VDC -0.3VDC to 74VDC -0.3VDC to 3.6VDC -0.3VDC to 0.3VDC -0.3VDC to 5.5VDC -0.3VDC to 3.6VDC 36 RES_CAP/INT_OUT 35 ALT A/B 34 COMM_MODE 33 Current_SET 32 4 Pair Mode 31 AGND 30 LED2 29 LED3 28 PORT_SENSE2 27 VPORT_NEG2 26 PORT_SENSE3 25 VPORT_NEG3 2KV HBM -65 to +150C (Top View) RoHS / Pb-free 100% Matte Tin Finish Notes: Exceeding these ratings can cause damage to the device. All voltages are with respect to ground. Currents are marked positive when flowing into specified terminals and marked negative when flowing out of specified terminals. Copyright (c) 2013 Microsemi Rev. 1.3 Analog Mixed Signal Group 1 Enterprise, Aliso Viejo, CA 92656, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308 2 PD69104B1/F Supply Input Voltage (VMAIN) Port_Neg [0..7] pins LED pins Port_Sense[0..7] pins QGND, GND pins VAUX5, DRV_VAUX5 All other pins PD69104B1 Operating Ambient Temperature Range PD69104B1F Operating Ambient Temperature Range Maximum Operating Junction Temperature ESD Protection at all I/O pins Storage Temperature Range P AC K AG E PIN O UT REG_EN_N / NC AB SO L UT E M AXIM UM R AT ING S PD69104B1/F 4 Port PSE PoE Manager D ATASHEET ROHS AND SOLDER REFLOW INFORMATION W W W. Microsemi .CO M RoHS 6/6 Pb-free 100% Matte Tin Finish Package Peak Temperature for Solder Reflow (40 seconds maximum exposure) 260 C (+0 C, -5 C) Notes: Exceeding these ratings can cause damage to the device. PD69104B1/F Copyright (c) 2013 Microsemi Rev. 1.3 Analog Mixed Signal Group 1 Enterprise, Aliso Viejo, CA 92656, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308 3 PD69104B1/F 4 Port PSE PoE Manager D ATASHEET PARAMETER SYMBOL TEST CONDITIONS / COMMENT Input Voltage VMAIN Supports Full IEEE802.3 functionality Power Supply Current @ Operating Mode IMAIN VMAIN = 55V 5V Output Voltage VAUX5 PD69104B1 MANAGER MIN TYP MAX UNITS W W W. Microsemi .CO M Electrical Characteristics POWER SUPPLY 3.3V Output Voltage VAUX3P3 3.3V Output Current 3.3V Input Voltage VAUX3P3 44 55 57 10 VDC mA 4.5 5 5.5 2.97 3.3 3.63 VDC VDC Without external NPN 5 mA With external NPN transistor on VAUX5 30 mA REG_EN_N pin = 3.3V (internal reg. is disabled) VAUX3P3_INT pin=5V 3 3.3 3.6 VDC Threshold 2.575 2.775 2.975 VDC Hysteresis 0.2 0.25 0.3 VDC Delay 10 50 100 S POWER ON RESET (POR) PD69104B1/F Copyright (c) 2013 Microsemi Rev. 1.3 Analog Mixed Signal Group 1 Enterprise, Aliso Viejo, CA 92656, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308 4 PD69104B1/F 4 Port PSE PoE Manager D ATASHEET PARAMETER SYMBOL TEST CONDITIONS / COMMENT PD69104B1 MANAGER MIN TYP MAX UNITS Input Logic High Threshold VIH Input Logic Low Threshold VIL 2 Input Hysteresis Voltage 0.4 VDC 0.6 0.8 VDC 0.8 VDC Input High Current IIH -10 10 A Input Low Current IIL -10 10 A Output High Voltage VOH For IOH = -1 mA Output Low Voltage VOL IOH = 1 mA 2.4 W W W. Microsemi .CO M DIGITAL I/O VDC 0.4 VDC POE LOAD CURRENTS AT Limit Mode AT_LIM_LOW Tested With Sense Resistance = 0.366 706 722 767 mA AT_LIM_HIGH 847 874 919 mA AT configurable 537 1200 mA AF_LIM 410 425 448 mA 808 850 892 mA (Rsense+Traces = 0.36 +6m=0.366 ) connected at port_sense pin AF Limit Mode PoE Tech High Power Port MAIN POWER SWITCHING FET On Resistance RDSON Internal Thermal Protection Threshold 0.3 200 C LINE DETECTION According to IEEE802.3 standard 19 26.5 K CLASSIFICATION Class Event Output Voltage Measured between VMAIN and VPORT_NEG pins 16.5 18 19.5 VDC Mark Event Output Voltage Measured between VMAIN and VPORT_NEG pins 7.5 8.5 9.5 VDC Copyright (c) 2013 Microsemi Rev. 1.3 Analog Mixed Signal Group 1 Enterprise, Aliso Viejo, CA 92656, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308 5 PD69104B1/F Range PD69104B1/F 4 Port PSE PoE Manager D ATASHEET PARAMETER SYMBOL TEST CONDITIONS / COMMENT PD69104B1 MANAGER MIN TYP MAX UNITS Current Sink I sink (from VMAIN to AGND) 3 5 mA 3 STATES ANALOG INPUT PINS (CURRENT SET, COMM_MODE) High Level input voltage Open Low level input voltage 80% VAUX3P3 Not Connected 40% VAUX3P3 W W W. Microsemi .CO M LED0 TO 3, MAX_LED DRIVERS VDC 60% VAUX3P3 VDC 20% VAUX3P3 VDC PD69104B1/F Copyright (c) 2013 Microsemi Rev. 1.3 Analog Mixed Signal Group 1 Enterprise, Aliso Viejo, CA 92656, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308 6 PD69104B1/F 4 Port PSE PoE Manager D ATASHEET Dynamic Characteristics The PD69104B1 utilizes three current level thresholds (Imin, Icut, Ilim) and three timers (Tmin, Tcut, Tlim). Loads that consume Ilim current for more than Tlim are labeled as 'short circuit state' and are shutdown. Loads that dissipate more than Icut for longer than Tcut are labeled as `overloads' and are shutdown. If output power is below Imin for more than Tmin, the PD is labeled as `no-load' and is shutdown. Automatic recovery from overload and no-load conditions is attempted every TOVLREC period (typically 1 second). Output power is limited to Ilim, which is the maximum peak current allowed at the port. Table 1: Operational Mode Parameters PARAMETER CONDITIONS MIN. TYP. Automatic Recovery from No-load Shutdown TUDLREC value; measured from port shutdown point (can be modified through control port) 1 s Cutoff Timers Accuracy Typical accuracy of Tcut 2 ms Inrush Current IInrsh For t = 50ms, Cload = 180F max. 400 450 mA Output Current Operating Range Iport Continuous operation after startup period 10 725 mA Output Power Available, Operating Range Pport Continuous operation after startup period at port output 0.57 36 W Off Mode Current Imin1 Must disconnect where T is greater than TUVL 0 5 mA Imin2 May or may not disconnect where T is greater than TUVL 5 10 mA PD Power Maintenance request drop-out time limit TPMDO Buffer period to handle transitions 300 400 ms Overload Time Limit TOVL 50 75 ms Turn-on Rise Time Trise 7.5 MAX. UNIT W W W. Microsemi .CO M From 10% to 90% of Vport (Specified for PD load consisting of 100F capacitor parallel to 200 resistor) Turn-off Time Toff From Vport to 2.8VDC Time Maintain Power Signature TMPS DC modulation time for DC disconnect 15 us 500 49 ms ms PD69104B1/F Copyright (c) 2013 Microsemi Rev. 1.3 Analog Mixed Signal Group 1 Enterprise, Aliso Viejo, CA 92656, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308 7 PD69104B1/F 4 Port PSE PoE Manager D ATASHEET Table 2: IEEE802.3 AT Mode Parameters CONDITIONS MIN. TYP. Automatic Recovery from No-load Shutdown TUDLREC value; measured from port shutdown point (can be modified through control port) 1 s Cutoff Timers Accuracy Typical accuracy of Tcut 2 ms Inrush Current IInrsh For t = 50ms, Cload = 180F max. 400 450 mA Output Current Operating range Iport Continuous operation after startup period 10 725 mA Output Power Available, Operating Range Pport Continuous operation after startup period at port output 0.57 36 W Off Mode Current Imin1 Must disconnect where T is greater than TUVL 0 5 mA Imin2 May or may not disconnect where T is greater than TUVL 5 10 mA PD Power Maintenance request drop-out time limit TPMDO Buffer period to handle transitions 300 400 ms Overload Time Limit TOVL 50 75 ms Turn-on Rise Time Trise 7.5 MAX. UNIT W W W. Microsemi .CO M PARAMETER From 10% to 90% of Vport (Specified for PD load consisting of 100F capacitor parallel to 200 resistor) Turn-off Time Toff From Vport to 2.8VDC Time Maintain Power Signature TMPS DC modulation time for DC disconnect 15 us 500 49 ms ms PD69104B1/F Copyright (c) 2013 Microsemi Rev. 1.3 Analog Mixed Signal Group 1 Enterprise, Aliso Viejo, CA 92656, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308 8 PD69104B1/F 4 Port PSE PoE Manager D ATASHEET I2C_SDA_in / Rx I2C_SDA_out / Tx I2C_SCL DGND DVDD E2_SDA PS_PGD3 / E2_SCL PS_PGD2 PS_PGD1 PS_PGD0 MODE1 MODE0 47 46 45 44 43 42 41 40 39 38 37 24 36 RES_CAP/INT_OUT 35 ALT A/B 34 COMM_MODE 33 Current_SET 32 4 Pair Mode 31 AGND 30 LED2 29 LED3 28 PORT_SENSE2 27 VPORT_NEG2 26 PORT_SENSE3 25 VPORT_NEG3 PD69104B1/F MAX_LED 12 23 VPORT_NEG1 TRIM 11 22 PORT_SENSE1 IREF 10 21 VPORT_NEG0 Date Code QGND 9 20 PORT_SENSE0 VAUX3P3 8 19 LED1 PD69104B1/F VAUX3P3_INT 7 18 LED0 AGND 6 17 AGND DRV_VAUX5 5 16 ADD3 MSC VAUX5 4 15 ADD2 VMAIN 3 14 ADD1 Microsemi LOGO NC 2 13 ADD0 REG_EN_N / NC 1 W W W. Microsemi .CO M RESET_N 48 Package and Pinout PD69104B1 for -10 to +85C Operating Ambient Temperature Range PD69104B1F for -40 to +85C Operating Ambient Temperature Range Copyright (c) 2013 Microsemi Rev. 1.3 Analog Mixed Signal Group 1 Enterprise, Aliso Viejo, CA 92656, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308 9 PD69104B1/F 4 Port PSE PoE Manager D ATASHEET Detailed Pinout Description PIN PAD PIN TYPE DESCRIPTION Analog GND Exposed PAD: Connect to analog ground (AGND). A decent ground plane should be deployed around this pin whenever possible (refer to PD69104B Layout Design Guidelines) 1. RESET_N Digital Input Reset input - active low ('0' = reset) This Pin is also used for RPD / MRPD Function as Described later on this document. Note: This pin should be free of large capacitance in order to prevent RPD & MRPD pulses distortion (please refer to MSCC PD69104B Application Note) 2. ADDR0 Digital Input Address bus for setting the address of the chip. See Table 3. 3. ADDR1 Digital Input Address bus for setting the address of the chip. See Table 3. 4. ADDR2 Digital Input Address bus for setting the address of the chip. See Table 3. 5. ADDR3 Digital Input Address bus for setting the address of the chip. See Table 3. 6. AGND Power Analog ground 7. LED 0 Open Drain Output See Open Drain Output See 8. LED 1 Port 0 LED indication - active low ('0' = LED on) Table 6 Port 1 LED indication - active low ('0' = LED on) Table 6 9. PORT_SENSE0 Analog Input Sense resistor port input (Connected to 0.36 , 1% resistor to QGND with ~6 m trace for measurements accuracy). 10. VPORT_NEG0 Analog I/O Negative port output 11. PORT_SENSE1 Analog Input Sense resistor port input (Connected to 0.36 , 1% resistor to QGND with ~6 m trace for measurements accuracy). 12. VPORT_NEG1 Analog I/O Negative port output REG_EN_N/NC Analog I/O 14. NC Analog I/O A test pin used only during production. Keep unconnected. 15. VMAIN Power Supplies voltage for the internal analog circuitry. A 1F (or higher) low ESR bypass capacitor, connected to AGND, should be placed as close as possible to this pin through low resistance traces. Power Regulated 5VDC output voltage source, needs to be connected to a filtering capacitor of 4.7F or higher. If an external NPN is used to regulate the voltage, connect this pin to the "Emitter" (the "collector" should be connected to VMAIN). VAUX5 Copyright (c) 2013 Microsemi Rev. 1.3 Analog Mixed Signal Group 1 Enterprise, Aliso Viejo, CA 92656, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308 10 PD69104B1/F 13. An input pin that enables control of the 3.3VDC internal regulator. Disables internal 3.3VDC regulator in case external 3.3VDC is used to supply the chip. If connected to GND or unconnected - internal regulator is enabled. If connected to 3.3VDC - internal regulator is disabled 16. W W W. Microsemi .CO M 0. PIN N AM E PD69104B1/F 4 Port PSE PoE Manager D ATASHEET PIN PIN N AM E PIN TYPE DESCRIPTION DRV_VAUX5 Power 18. AGND Power Analog ground 19. VAUX3P3_INT Power In case internal 3.3 VDC regulator is used, connected to VAX3P3 (pin 20). In case external 3.3VDC regulator is used, connect to VAUX5 (pin 16). 20. VAUX3P3 Power Regulated 3.3VDC output voltage source. A 4.7F or higher filtering capacitor should be connected between this pin and AGND. When an external 3.3VDC regulator is used, connect it to this pin to supply the chip. 21. QGND Power Quiet analog ground 22. IREF Analog Input A reference resistor pin. A 30.1k, 1% resistor should be connected between this pin and QGND. 23. TRIM Test Input Trimming input for IC production. Should be connected to VAUX3P3. 24. MAX_LED Open Drain Output W W W. Microsemi .CO M 17. Driven outputs for 5VDC external regulations. In case internal regulation is used, connect to pin 16. In case an external NPN is used to regulate the voltage, connect this pin to the "Base". MAX LED analog output. Indicates the device has exceeded maximum power budget. See Table 6. 25. VPORT_NEG3 Analog I/O Negative port output 26. PORT_SENSE3 Analog Input Sense resistor port input (Connected to 0.36 , 1% resistor to QGND with ~6 m trace for measurements accuracy). 27. VPORT_NEG2 Analog I/O Negative port output 28. PORT_SENSE2 Analog Input Sense resistor port input (Connected to 0.36 , 1% resistor to QGND with ~6 m trace for measurements accuracy). 29. LED 3 Open Drain Output See Open Drain Output See Analog ground 3 state input pin. - select 4 pairs mode 30. LED 2 AGND Power 32. 4 pairs mode Analog Input Table 6 Port 2 LED indication - active low ('0' = LED on) Table 6 "0" (GND) - 4 ports of 2 pairs. "open" (N.C) - 2 ports of 2 pair & 1 of 4 pair. "1" (VCC) - 2 ports of 4 pair. 3 state input pin, used for selecting output current and AF/AT mode. 33. Current_SET Analog Input "0" (AGND) - AF mode "open" (N.C) - Low AT mode 600mA "1" (VDD) - High AT mode 720mA Copyright (c) 2013 Microsemi Rev. 1.3 Analog Mixed Signal Group 1 Enterprise, Aliso Viejo, CA 92656, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308 11 PD69104B1/F 31. Port 3 LED indication - active low ('0' = LED on) PD69104B1/F 4 Port PSE PoE Manager D ATASHEET PIN PIN N AM E PIN TYPE DESCRIPTION 3 state input pin communication. Following options are available: COMM_MODE Analog Input "0" (AGND) - UART active "open" (N.C) - E2PROM connected "1" (VDD) - I2C active User input pin, used for setting the chip working mode. 35. ALT A/B Digital Input GND - ALT B mode = Midspan mode (midsp [1:4] bits ="1") DVDD - ALT A mode = Endspan mode (midsp [1:4] bits ="0") In MSCC Extended Auto mode: User input pin. Used for setting the chip legacy detection mode: 36. INT_OUT Digital I/O (open drain) 37. Mode0 Digital Input "1" (VDD) - IEEE802.3af compliant resistor detection only "0" (GND) - AF / AT Detection and Legacy (non-standard) line detection In Auto or Semi-Auto modes: Interrupt out pin. Indicates an interruption event has occurred. An external 10K pull-up resistor should be connected between this pin and DVDD. Used for IC operational mode selection - see Table 4: Mode of Operation Used for IC operational mode selection - See 38. Mode1 Digital Input 39. PS_PGD0 Digital input Power Supply Power Good 0; Power Budget Set pin - for Fast Power Control. (See Table 7) 40. PS_PGD1 Digital input Power Supply Power Good 1; Power Budget Set pin - for Fast Power Control. (See Table 7) 41. PS_PGD2 Digital input Power Supply Power Good 2; Power Budget Set pin - for Fast Power Control. (See Table 7) PS_PGD3 / E2_SCL Digital I/O (open drain) Power Supply Power good 3; Power Budget Set Pin - for initial configuration (See Table 7) Or (refer to COMM MODE PIN) E2_SCL: I2C Clock Out to EEPROM When working with EPROM - An external 10K pull-up resistor should be connected between this pin and DVDD. 43. E2 SDA Digital I/O (open drain) EEPROM I2C data I/O pin. Used for Power Up configuration in Stand Alone Auto-Mode systems. An external 10K pull-up resistor should be connected between this pin and DVDD. 44. DVDD Power Digital 3.3VDC power input 45. DGND Power Digital GND 46. I2C SCL Digital Input I2C bus, serial clock input. An external 10K pull-up resistor should be connected between this pin and DVDD. 42. W W W. Microsemi .CO M 34. Table 4: Mode of Operation 12 PD69104B1/F Copyright (c) 2013 Microsemi Rev. 1.3 Analog Mixed Signal Group 1 Enterprise, Aliso Viejo, CA 92656, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308 PD69104B1/F 4 Port PSE PoE Manager D ATASHEET PIN PIN N AM E PIN TYPE I2C_SDA_out 48. I2C_SDA_in Digital I/O (open drain) I2C bus, data output / UART Tx output An external 10K pull-up resistor should be connected between this pin and DVDD. I2C bus, data input / UART Rx input An external 10K pull-up resistor should be connected between this pin and DVDD. W W W. Microsemi .CO M 47. Digital I/O (open drain) DESCRIPTION Note: "0" = Connect to DGND "1" = Connect to DVDD PD69104B1/F Copyright (c) 2013 Microsemi Rev. 1.3 Analog Mixed Signal Group 1 Enterprise, Aliso Viejo, CA 92656, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308 13 PD69104B1/F 4 Port PSE PoE Manager D ATASHEET ADDR1 ID1 BIT 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 ADDR0 ID0 BIT 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 I2C/ UART ADDRESS W W W. Microsemi .CO M Table 3: I2C Address Selection Table ADDR3 ADDR2 CONST SLAVE SLAVE BITS 1 BIT 0 BIT 010 0 0 010 0 0 010 0 0 010 0 0 010 0 1 010 0 1 010 0 1 010 0 1 010 1 0 010 1 0 010 1 0 010 1 0 010 1 1 010 1 1 010 1 1 010 1 1 Notes: 0100000b 0100001b 0100010b 0100011b 0100100b 0100101b 0100110b 0100111b 0101000b 0101001b 0101010b 0101011b 0101100b 0101101b 0101110b 0101111b Address 0000000b is the global address in Extended mode operation I2C (MODE<1:0>='00') Address 0110000b is the global address in Auto mode and Semi Auto mode operations (MODE<1:0>='01' or '11') All the slaves respond to the global address Avoid global read transactions Address 0001100b is used for Extended POE address (Alert Response Address) in Auto mode and Semi Auto mode operations When reading from this Alert Response address, only slaves that assert the Int_out pin will send bytes that consist of their own addresses PD69104B1/F Copyright (c) 2013 Microsemi Rev. 1.3 Analog Mixed Signal Group 1 Enterprise, Aliso Viejo, CA 92656, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308 14 PD69104B1/F 4 Port PSE PoE Manager D ATASHEET Table 4: Mode of Operation Mode 1 Mode 0 0 MSCC Extended Auto Mode Comm. to the IC I2C or UART (see COMM_MODE pin) Functionality Fully autonomous operation without a need for Host Controller (MCU) This Mode Supports Extended Registers Map. Default Operation: With No Interrupt Function (Interrupt can be Remarks I2C or UART Protocol to Host with extended register map and PM (Power Management) support enabled by communication command) 0 1 1 0 1 1 Semi Auto mode Test mode Auto mode I2C or UART (see COMM_MODE pin) Host should manage the ports I2C Protocol to Host W W W. Microsemi .CO M 0 Mode For internal use only I2C or UART (see COMM_MODE pin) Fully autonomous operation without a need for Host Controller. Default Operation: Interrupt Out Function - Enabled (Supported) I2C Protocol to Host PD69104B1/F Copyright (c) 2013 Microsemi Rev. 1.3 Analog Mixed Signal Group 1 Enterprise, Aliso Viejo, CA 92656, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308 15 PD69104B1/F 4 Port PSE PoE Manager D ATASHEET P AC K AG E D R AW IN G W W W. Microsemi .CO M E2 D L b D2 E K e A A1 A3 Dim A A1 A3 K e L b D2 E2 D E MILLIMETERS Min. Max. 0.80 1.00 0.00 0.05 0.20 Ref. 0.20 Min. 0.50 BSC 0.30 0.50 0.18 0.30 6.35 6.60 6.35 6.60 8.00 BSC 8.00 BSC INCHES Min. Max. 0.031 0.039 0 0.002 0.008 Ref. 0.008 Min. 0.02 BSC 0.012 0.02 0.007 0.012 0.250 0.260 0.250 0.260 0.315 BSC 0.315 BSC Note: 1. Dimensions do not include protrusions; these shall not exceed 0.155mm (.006") on any side. Lead dimension shall not include solder coverage. PD69104B1/F Copyright (c) 2013 Microsemi Rev. 1.3 Analog Mixed Signal Group 1 Enterprise, Aliso Viejo, CA 92656, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308 16 PD69104B1/F 4 Port PSE PoE Manager PD69104B1 - Internal Block Diagram D ATASHEET Vaux SCL SDA_out SDA_in I2C slave Tx CRG MCM MODE0 MODE1 sync VCM PoE Tec zone addr decod er x ALU Power clalculation POR x + / Power management Startup Power CLK startup fsm Current_SET COMM_MODE ongoing logic Voltage Generator for Line Detection & Classification Icut calculation Management block detection fsm Analog Mesurment Thermal Protection - ALT A/B INT_OUT SPEAR 4 Tool Box SPEAR 3 Toool Box SPEAR 2 Tool Box SPEAR 1 Tool Box fsm AIR (Analog Interface) UART slave Rx Voltage Regulat or 3.3V ADC I/F (CPU/Control Registers) SCL A/D Ic error logic Controlled Reference Current Limiter mcm logic Res det start Cap start class up det up Main MOSFET AGND ALU RTP RTP RTP RTP DGND Clk & Reset logic DGND clk_d POR Sense Resistor RESET PMU (poe macro unit) W W W. Microsemi .CO M I2C master SDA_out SDA_in Analog Power Banks COM ADDR0 ADDR1 ADDR2 ADDR3 Vmain Logic Main Control Module Line Detection Generator The Logic Main Control block includes the Digital Timing mechanisms and the State Machines, synchronizing and activating PoE functions such as: Real Time Protection (RTP) Start Up Macro (DVDT) Classification Generator Load Signature Detection (RES DET) Classification Macro (CLASS) Voltage and Current Monitoring Registers (VMC) Upon request from the Main Control module, the State Machine applies regulated Class Event and Mark Event voltages to the ports, as required by the IEEE standard. ADC Interfacing Direct Digital Signals with Analog Block Current Limiter This circuit continuously monitors the current of the powered ports and limits it to a specific value, according to pre-defined limits set using the Current_Set pin. In case the current exceeds this specific level, the system starts measuring the elapsed time. If this period is longer than the preset threshold, the port is disconnected. 17 Microsemi Copyright (c) 2013 Rev. 1.3 Analog Mixed Signal Group 1 Enterprise, Aliso Viejo, CA 92656, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308 PD69104B1/F Upon request from the Main Control module, the Line Detection Generator creates four different voltage levels. Thus it ensures robust AF / AT Line Detection functionality. PD69104B1/F 4 Port PSE PoE Manager D ATASHEET Main MOSFET Main power switching FET used for controlling the PoE current that streams into the load. A 10-Bit Analog to Digital converter used for converting analog signals into digital registers. IC main voltage monitoring: The chip main voltage is sampled every 1mS. Each measurement is an average of 4 consecutive ADC measurements and stored in the relevant register. Main voltage measurement resolution is 5.835mV/count 5%. Power on Reset (POR) This element monitors the internal 3.3VDC voltage DC levels. If this voltage drops below specific thresholds, a reset signal is generated and the PD69104B1 is reset. Voltage Regulator IC Thermal monitoring: The PD69104B1 contains a thermal sensor that is sampled to register every 1mS so the PD69104B1 die temperature can be monitored at all time. Port current/voltage monitoring: W W W. Microsemi .CO M IC and port parameters monitoring After port is delivering power each port current/voltage is sampled every 1mS. Each measurement is an average of 4 consecutive ADC measurements and stored in the relevant register. Current measurement resolution is 122.07uA/count 5% and voltage measurement resolution is 5.835mV/count 5% (refer to the PD69104B1 user Guide register map document for more details) The voltage regulator generates 3.3VDC and 5VDC for the internal circuitry. These voltages are derived from the Vmain supply. CLK An internal 8MHz CLK oscillator PD69104B1/F Copyright (c) 2013 Microsemi Rev. 1.3 Analog Mixed Signal Group 1 Enterprise, Aliso Viejo, CA 92656, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308 18 PD69104B1/F 4 Port PSE PoE Manager D ATASHEET Theory of Operation Line Detection The Line Detection feature detects a valid AF or AT load, as specified in the IEEE802.3 standard. The resistance Power "ON" v 2 Events Classification Phase W W W. Microsemi .CO M The PD69104B1 meets the IEEE802.3af and IEEE802.3at functionality standards, as well as legacy (capacitor) and Cisco's PDs detection standards. Moreover, it supports additional protections such as short circuit, and dV/dT protection upon port startup. value should range from 19k to 26.5k. Line detection is based on four different voltage levels generated over the PD (the load), as illustrated in Figure 1. The first 2 levels (low voltage level <3v) are for detecting if load up to 200K is connected to the PSE; preventing from applying high voltages on the PSE when there is no-load, and eliminating potential risk to the DTE. If first detection passes next 2 levels of resistor detection are applied. If the POE detects a valid resistor signature value the detection is passed else the detection fails and moves to IDLE. Power "OFF" Start-Up (Inrush) Detection Phase t Figure 1: Typical PoE Voltage vs. Time Diagram Legacy (Cap) Detection Classification The classification process takes place right after the resistor detection is successfully completed. The main goal of the classification process is to detect the PD class, as specified in the IEEE802.3AF and AT standards. The process is being done by applying a voltage to the PD nodes and measuring the port current. PD69104B1/F In case pin 36 (RES_CAP / INT_OUT) is set to "0", the detection mechanism of the PD69104B is configured to detect and power LEGACY PDs, as well as AF/AT compliant PDs. This mechanism also detects and powers CISCO Legacy PDs. In the AF mode the classification mechanism is based on a single voltage level step (single finger). In the AT mode classification mechanism is based on two voltage level steps (dual finger) as defined in the IEEE802.3at standard. Port Start Up Upon a successful Detection and Classification process, power is applied to the load via a controlled Start Up mechanism. During this period current is limited to 425mA for a typical duration of 65ms. This enables the PD load to charge and to enter a steady state power condition. Copyright (c) 2013 Microsemi Rev. 1.3 Analog Mixed Signal Group 1 Enterprise, Aliso Viejo, CA 92656, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308 19 PD69104B1/F 4 Port PSE PoE Manager D ATASHEET Over-temperature Protection After power up, the PD69104B1 automatically initializes its internal protection mechanisms. These mechanisms are utilized to monitor and disconnect the power from the load in case of an extreme conditions scenario. Scenarios such as over-current or short ports terminals, as specified in the IEEE802.3AF/AT standard. The PD69104B1 has internal temperature sensors that continuously monitor the junction temperature and set alarm bit when exceeds 120C or disconnect load power when it exceeds 200C. This mechanism protects the device from extreme events, such as high ambient temperature or other thermo-mechanical failures that may damage the PD69104B1. The Alarm threshold can be set by register. Disconnect Detection The PD69104B1 supports the DC Disconnect function as per the IEEE802.3AF/AT standard. This mechanism continuously monitors the load current and disconnects the power in case it drops below 7.5mA (typical) for more than 322ms. VMAIN Out of Range Protection The PD69104B1 automatically disconnects the ports power when Vmain exceeds 58.5v threshold (with 180mV hysteresis) or drops below 40V threshold (with 180mV hysteresis). This extremely valuable feature protects the load in case the main power source is faulty or damaged. W W W. Microsemi .CO M Over-Load Detection and Port Shut Down TYPICAL APPLICATION This typical application illustrates a simple "plug and play" Power over Ethernet solution for a single Ethernet port, switch or hub. 1. Plug the "POS" and "NEG" signals into the RJ45 switch jack. +Vmain Vport_Pos0 47nF VAUX 5v Vmain VAUX 3.3v VAUX5 DRV_VAUX5 VAUX3P3 VAUX3P3_INT DVDD Vport_Neg Vport_Sense Addr0 Addr1 Addr2 Addr3 To Opto 10K x4 Vport_Neg SDA_OUT/Tx SDA_IN/Rx SCL DVDD 10K To Vmain Sense_Neg LED0 LED1 LED2 LED3 RES_CAP/INT_out MODE0 MODE1 COMM_MODE Current_SET ALT A/B Vport_Neg3 Vport_Sense Iref PS_PG0 PS_PG1 PS_PG2 Active Low Pulled From Vmain PD69104B1/F DVDD 0.36ohm x4 E2_SCL PS_PG3/E2_SDA Communication Bus I2C/UART Vport_Neg0 To Power Supply 30.1Kohm 1% EEPROM (optional) * For detailed schematics of application and layout recommendations contact sales_AMSG@microsemi.com. Copyright (c) 2013 Microsemi Rev. 1.3 Analog Mixed Signal Group 1 Enterprise, Aliso Viejo, CA 92656, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308 20 PD69104B1/F 4 Port PSE PoE Manager D ATASHEET Communication Function Description The following diagram describes the I2C Communication format of the data write/read access: W W W. Microsemi .CO M Write cycle ( and write after write) Start bit 7 bit address W bit ack 8 bit Reg address ack Reg address (byte) Commannd byte 8bit Reg data Stop bit ack Data (byte/word) Read cycle (change of dircation) Start bit 7 bit address W bit ack 8 bit Reg address ack Reg address (byte) Commannd byte Start bit 7 bit address RD bit Repeat Commannd start byte ack 8/16 bit Reg data Stop bit Data (byte/word) Short Read Start bit 7 bit address RD bit ack 8/16 Reg data Stop bit Commannd byte - Master transmitts - Slave transmitts Figure 2: Packet Structure Address Phase This phase is common to both read and write accesses: Both accesses (read and write) begin with a START indication. The address of the slave is following the START indication. In case of a miss match, the slave ignores the rest of the access and waits for the 'STOP' indication to close the current access. However, in case the slave address matches, the next bit indicates the type of the access (read or write). The matched slave acknowledges the first byte. The following byte is the internal register address. The slave should acknowledge the byte. PD69104B1/F Data Phase In this phase the read and write accesses behave differently. Write access 1. Byte of write data is transmitted to the slave; the slave acknowledges it. 2. A stop indication from the master closes the current access. Read access 1. Another command byte is received, comprised of the slave address and the real command type (in this case read). The slave acknowledges the byte. Copyright (c) 2013 Microsemi Rev. 1.3 Analog Mixed Signal Group 1 Enterprise, Aliso Viejo, CA 92656, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308 21 PD69104B1/F 4 Port PSE PoE Manager D ATASHEET 2. At this stage, the master is ready to continue the communication and to sample the read data; hence, the read data must be ready on the next rise of the clock pulse. 3. A byte of data is transmitted to the master; the master acknowledges it. W W W. Microsemi .CO M I2C High Level Layer The following diagram describes the supported I2C high-level packet structure. Control byte 7 bits address Address Register Data R/W bit Figure 3: High Level Packet Structure Byte/Word Read/Write Transaction 1. The first byte is the control byte that consists of the chip address and a read/write operation indication. 2. The second byte is the internal chip's address register. 3. The following bytes/words are data bytes. In case of a read operation they are read from the slave and in case of a write operation they are written to the slave. Successive Read/Write Transaction The master can continue sending bytes that the slaves write, or continue receiving data from a slave during the address phase. The slave will continue to send/receive data bytes from/to the master until a 'stop bit' is asserted by the master. Each byte received by the slave (or each byte to be read from the registers) is received from the next register address (each byte address is increased by 1). Read Byte Transaction PD69104B1/F The slave supports a 'send byte' transaction. 1. The master begins with a start bit. The following byte consists of the chip address and a read bit. 2. If the chip address is correct the slave acknowledges the byte and immediately (at the next sck phase) sends a data byte from a constant address (addr 7'h00) 3. A send byte transaction continues with successive read transactions (address 1 address 2 and so on) until the master asserts a stop bit. Broadcast Support All slaves answer a general address sent by the master. In case of Auto or Semi-Auto modes the general address is 7'h30 and in case of MSCC Extended Auto mode the general address is 7'h0. The broadcast is for master writing only; read access is ignored in a broadcast transaction. Copyright (c) 2013 Microsemi Rev. 1.3 Analog Mixed Signal Group 1 Enterprise, Aliso Viejo, CA 92656, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308 22 PD69104B1/F 4 Port PSE PoE Manager D ATASHEET Time Out Mechanism I2C Timing Constraints Table 5: Characteristics of the SDA and SCL Bus Lines for F/S-mode I2C-Bus W W W. Microsemi .CO M The I2C has an internal counter of 14ms. The counter resets each time the SCL rises or falls. If the SCL is "stuck" for 14ms, the I2C returns to IDLE state and transaction is ignored (the Time Out mechanism is active between the start bit and the stop bit). Notes Copyright (c) 2013 Microsemi Rev. 1.3 Analog Mixed Signal Group 1 Enterprise, Aliso Viejo, CA 92656, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308 23 PD69104B1/F 1. All values refer to VIHmin and VILmax levels (see Electrical Characteristics, page 4). 2. A device must internally provide a hold time of at least 300ns for the SDA signal (refers to the VIHmin of the SCL signal) to bridge the undefined region of the falling edge of the SCL. 3. The maximum tHD;DAT has to be met only if the device does not stretch the LOW period (tLOW) of the SCL signal. 4. A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tSU;DAT 250ns must then be met. This is the in case the device does not stretch the LOW period of the SCL signal. 5. If the device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + tSU;DAT = 1000 + 250 = 1250ns (according to the Standard-mode I2C-bus specification) before the SCL line can be released. 6. n/a = not applicable PD69104B1/F 4 Port PSE PoE Manager D ATASHEET W W W. Microsemi .CO M Figure 4: Definition of Timing for F/S-mode Devices on the I2C-bus UART Communication Mode - Functional Description The UART (Universal Asynchronous Receive Transmit) is supported by the PD69104B platform in order to allow communication between PD69104B IC's and an external host, at Auto mode only. The PD69104B platform supports UART only as a slave. Features List Slave mode. Supports 4,800 to115,200 Baud rate, auto learning mechanism Supports 8 bit address. Supports 8 bit data access. Supports general broadcast transmission. 8N1: o 8 bits data o No parity o 1 stop bit Frame transaction - header, payload and suffix. Time out mechanism (time out for frame and per byte). No successive read/write - one transaction per register (read/write). Half duplex implementation - Rx starts after Tx ends A filter for glitches cancelling on the RX pin. The Physical Layer Figure 5: UART Read/Write Frame Copyright (c) 2013 Microsemi Rev. 1.3 Analog Mixed Signal Group 1 Enterprise, Aliso Viejo, CA 92656, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308 24 PD69104B1/F The UART protocol has two data lines; the Rx, from where the PD69104B receives its data, and the Tx, throughout where data is transmitted. The UART is a byte protocol in which every byte starts with a 'start bit' and ends with a 'stop bit'. PD69104B1/F 4 Port PSE PoE Manager D ATASHEET Data is sent in a constant frame in order to be synchronized. Figure 6 and Figure 7 describe the data read frame. 1 1 0 1 01 0 1 0 Chip_id R Reg addr (7'hxx) (1'b1) (8'hxx) Rx a W W W. Microsemi .CO M Header (8'h55) 1 0 10 1 111 Suffix (8'hf5) Tx 1 1 01 01 010 Header (8'h55) Chip_id (7'hxx) 1 0 101111 R Data bytes (8'hxx) Suffix (8'hf5) Figure 6: Master's Read Packet Structure 10 101 0 10 D Header (8'h55) 0 1 0101 1 11 Chip_id W Reg addr (7'hxx) (1'b0) (8'hxx) data word (8'hxx) Rx a Suffix (8'hf5) Tx 0 1 0 101 1 11 1 01 01 010 Header (8'h55) Chip_id (7'hxx) W Suffix (8'hf5) Figure 7: Master's Write Packet Structure 1. The first byte is the control byte consists of the chip address and a read/write operation indication. 2. The second byte is the internal ram address of the chip. 3. The following bytes are data bytes. In a case of read operations they are read from the slave and in case of a write operation they are written onto the slave. Broadcast Support All slaves answer a general address sent by the master. The general address is 7'h0. The broadcast is for master writing only; read accesses are ignored in a broadcast transaction. Auto Baud Rate Learning The PD69104B has a self-learning baud rate mechanism that allows synchronizing all PD69104B slaves to the master's "real" baud rate and thus working with a higher baud rate. Copyright (c) 2013 Microsemi Rev. 1.3 Analog Mixed Signal Group 1 Enterprise, Aliso Viejo, CA 92656, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308 25 PD69104B1/F The first byte received by the slave is 8'hAA. At the rising or falling edge of each bit, an 8MHz counter starts counting the bit width (in a 125ns resolution). The average width of the 8 header bits is the actual bits rate. By using this mechanism, the PD69104B slaves can be synchronized with the master and set back data at that rate. The header is a preamble bit that facilitates synchronization. PD69104B1/F 4 Port PSE PoE Manager D ATASHEET Header bit (8'hAA) W W W. Microsemi .CO M start bit stop bit 1 0 1 0 1 0 1 0 ...... . T0 T1 T7 7 Bit width = Tn / 8 n =0 Figure 8: Header Bit Width Timeout Mechanisms The UART protocol has a frame timeout mechanism. This mechanism has two purposes: Distinguishing between the frame's suffix of 8'f5 and a payload byte with the same value. The mechanism identifies a frame suffix only when it arrives as 2-bytes in a read access or as 4-bytes in a write access; otherwise it is treated as a data byte. Preventing UART communication from getting stuck. A 1 second timeout counter is activated beginning with a start frame (the end of header byte) till a suffix arrival. If a suffix byte does not arrive within that time the transaction is ignored and the slave moves into an IDLE state. measure bit width 1 0 1 01 0 1 0 Header (8'hAA) 1 0 1 01 0 1 0 Chip_id (7'hxx) 1 0 1 01 0 1 0 R ' (1'b1) 1 1 1 10 1 0 1 Reg addr Suffix (8'hxx) (8'hf5) timeout of max 1sec PD69104B1/F - start bit - stop bit Figure 9: Timeout Mechanism Copyright (c) 2013 Microsemi Rev. 1.3 Analog Mixed Signal Group 1 Enterprise, Aliso Viejo, CA 92656, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308 26 PD69104B1/F 4 Port PSE PoE Manager D ATASHEET Serial EEPROM Load Mechanism The PD69104B is capable of loading its registers values from an external serial EEPROM during a boot slot time. W W W. Microsemi .CO M To utilize the EEPROM boot, the COMM_MODE pin must be set to E2PROM_MODE (not connected). Features List: The PD69104B utilizes MASTER I2C communication. 7 bit addressing 250KHz frequency EEPROM constant address: 7'hA0 EEPROM must support read byte and read after read. Two repeated transactions in case the EEPROM does not acknowledge the transaction A FIR filter for glitches cancelling There are 5 consecutive read transaction (MASTER transactions) made by the PD69104B for reading data from the EEPROM and uploading it to the PD69104B registers. The first transaction reads all registers from address 8'h70 to address 8'h9F. The second transaction reads registers HPEN and HPMD1 (from addresses 8'h44 and 8'h46) The third transaction reads register HPMD2 (from address 8'h4b) The fourth transaction reads register HPMD3 (from address 8'h50) The fifth transaction reads register mp_hpmd4 (from address 8'h55) The read transaction format is as follows: 8'hxx (reg addr) Ack EEPRROM transmits (slave) Chip id [6:0] Rd Ack Sr Wr S Chip id [6:0] Ack Data byte0 Ack [7:0] ..... Data byteN Nack P [7:0] PD69104A transmits (master) Figure 10: I2C EEPROM High Level Packet Structure. For the I2C timing constraint, refer to Table 5 The EEPROM registers mapping should be identical to the PD69104B registers mapping. PD69104B1/F Copyright (c) 2013 Microsemi Rev. 1.3 Analog Mixed Signal Group 1 Enterprise, Aliso Viejo, CA 92656, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308 27 PD69104B1/F 4 Port PSE PoE Manager D ATASHEET Table 6: LED Indications PIN MAX_LED Port Power On Power Management event Port Over Load Port Short Circuit Port failed at Startup Vmain_Out of Range or Over Temp Port Off Total power consumption is below Power Guard Band determined by the user Total power consumption is above Power Guard Band but below total budget. Total power consumption is above total budget, or Power Integral is still positive LED On 0.4Hz Blink 0.8Hz Blink All LEDs :3.3Hz Blink Off Off W W W. Microsemi .CO M LED<3:0> Status On Blink Notes: MAX_LED: Both Max Power Budget and Max LED Guard Band (GB) can be configured through internal registers : o Max Power Budget registers: PWR_BNK0 to PWR_BNK7 (address 0x89 to 0x90) o Max LED Guard Band register: PoE_MAX_LED_GB (address 0x9F) PoE_MAX_LED_GB Register LSB = 1 watt Max LED reflects total power for all 4 ports When Total Power consumption < (Max Power - Guard Band) Max LED is OFF (below the bottom line) When Total Power consumption > (Max Power - Guard Band) Max LED is ON (Between the lines) When Total Power consumption > (Max Power) => LED is BLINKING (above top line) Also, when Total Power > Budget (above top line): o An internal Digital Power Integration Calc. machine starts integrating power o When this Integrated total power is larger than Budget + 12.5% (RED LINE) => lowest priority port is turned OFF o This specific port LED is OFF o Max LED will reflect the NEW Total Power status o If ports turn off due to PM their per port LEDs will blink (in PM frequency) and MAX_LED will turn off o Timing to shut down this port is proportional to the Over Power (above budget) but limited to max. of 2 sec. - see example: In 4 pairs mode, please use only the master led per port (Led 0 and led 2 are masters in 4 pairs mode). In 4 pairs mode, the port's led is blinking when the ports enters to UDL condition, unlike 2 pairs condition. PD69104B1/F Copyright (c) 2013 Microsemi Rev. 1.3 Analog Mixed Signal Group 1 Enterprise, Aliso Viejo, CA 92656, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308 28 PD69104B1/F 4 Port PSE PoE Manager D ATASHEET Over Power Zone Over Power Level Max LED = Blinking W W W. Microsemi .CO M Port OFF Threshold (12.5% over Budget) Max Power = Budget Set Guard Band Max LED = ON Max LED Threshold Max LED = OFF Power [watt] Port (n) - Off Max Power = Budget Set Max LED Threshold Total Power Plot Time [Sec] Max LED OFF Max LED ON Max LED Blink Max LED OFF Total Area > Power Budget x 12.5% Lowest Priority Port - turned OFF Figure 11: MAX_LED Behavior Description For Example: o Budget = 100w, GB = 20w o When total power = 70w - MAX LED is OFF o When total power = 85w - MAX LED is ON (Power Integrator is NOT activated) o When total power = 110w - MAX LED BLINKS (Power Integrator is activated) - Port at Lowest Priority is shut off o Timing to shut off is based on : delta(P) x Toff = Power Budget x 1.125 o In this example 10watt x Toff = 100watt x 0.125 Toff = 1.25 sec. o If Total Power = 105 watt delta (P) = 5 Then Toff = 2 sec. (which is the Max Timer) Copyright (c) 2013 Microsemi Rev. 1.3 Analog Mixed Signal Group 1 Enterprise, Aliso Viejo, CA 92656, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308 29 PD69104B1/F PD69104B1/F 4 Port PSE PoE Manager D ATASHEET Table 7: Power Budget: PS_PG2 PS_PG1 PS_PG0 Total Power Budget [W] Remarks 0 0 0 0 144 (default value in AT low mode) 176 (default value in AT high mode) 0 0 0 1 140 (default value) 0 0 1 0 136 (default value) 0 0 1 1 132 (default value) 0 1 0 0 128 (default value) 0 1 0 1 124 (default value) 0 1 1 0 120 (default value) 0 1 1 1 116 (default value) 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 112 108 104 100 96 92 88 84 Register PWR_BNK0 Register PWR_BNK1 Register PWR_BNK2 Register PWR_BNK3 Register PWR_BNK4 Register PWR_BNK5 Register PWR_BNK6 Register PWR_BNK7 Constant Constant Constant Constant Constant Constant Constant Constant W W W. Microsemi .CO M PS_PG3 / Bank Range Select There are 16 power levels, whereas the first 8 levels are registers that can be configured by users. During operation a change in one of the PG pins will change PD69104B's total power budget and may result in turning off ports. The power level can be set either by PS_PG0 to PS_PG3 pins or by Host via communication. Reset Mechanism PD69104B1/F To reset the PD69104B1, the RESET line should be pulled low for more than 16s. Copyright (c) 2013 Microsemi Rev. 1.3 Analog Mixed Signal Group 1 Enterprise, Aliso Viejo, CA 92656, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308 30 PD69104B1/F 4 Port PSE PoE Manager D ATASHEET Tape and Reel - Packaging Information W W W. Microsemi .CO M REEL MECHANICAL DATA mm. inch Tape size 16.00 0.3 0.630 0.012 A max. 330 13" B max. 1.5 0.059 C 13.0 0.20 0.512 0.008 D min. 20.2 0.795 N min. 50 1.968 G 16.4+2.0/-0.0 0.645+0.079/-0.0 T max. 29 1.142 BASE QUANTITY 2000 pcs. PD69104B1/F Copyright (c) 2013 Microsemi Rev. 1.3 Analog Mixed Signal Group 1 Enterprise, Aliso Viejo, CA 92656, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308 31 PD69104B1/F 4 Port PSE PoE Manager D ATASHEET Microsemi reserves the right to change the configuration, functionality and performance of its products at anytime without any notice. This product has been subject to limited testing and should not be used in conjunction with lifesupport or other mission-critical equipment or applications. Microsemi assumes no liability whatsoever, and Microsemi disclaims any express or implied warranty, relating to sale and/or use of Microsemi products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Any performance specifications believed to be reliable but are not verified and customer or user must conduct and complete all performance and other testing of this product as well as any user or customers final application. User or customer shall not rely on any data and performance specifications or parameters provided by Microsemi. It is the customer's and user's responsibility to independently determine suitability of any Microsemi product and to test and verify the same. The information contained herein is provided "AS IS, WHERE IS" and with all faults, and the entire risk associated with such information is entirely with the User. Microsemi specifically disclaims any liability of any kind including for consequential, incidental and punitive damages as well as lost profit. The product is subject to other terms and conditions which can be located on the web at http://www.microsemi.com/legal/tnc.asp W W W. Microsemi .CO M The information contained in the document (unless it is publicly available on the Web without access restrictions) is PROPRIETARY AND CONFIDENTIAL information of Microsemi and cannot be copied, published, uploaded, posted, transmitted, distributed or disclosed or used without the express duly signed written consent of Microsemi. If the recipient of this document has entered into a disclosure agreement with Microsemi, then the terms of such Agreement will also apply . This document and the information contained herein may not be modified, by any person other than authorized personnel of Microsemi. No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the information, either expressly, by implication, inducement, estoppels or otherwise. Any license under such intellectual property rights must be approved by Microsemi in writing signed by an officer of Microsemi. Revision History Revision Level / Date Para. Affected Description 1.0 / Dec 2012 First release 1.1/March 2013 Adding full temperature rang P/N 1.2 /June 2013 General update Typo Fixes - Current Set Signal, LED Description in 4 Pair PD69104B1/F 1.3 /Nov 2013 Mode (c) 2013 Microsemi Corp. All rights reserved. For support contact: sales_AMSG@microsemi.com Visit our web site at: www.microsemi.com Catalog Number: DS_PD69104B1/F Copyright (c) 2013 Microsemi Rev. 1.3 Analog Mixed Signal Group 1 Enterprise, Aliso Viejo, CA 92656, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308 32