Features * High Performance, Low Power AVR(R) 8-Bit Microcontroller * Advanced RISC Architecture * * * * * * * * - 131 Powerful Instructions - Most Single Clock Cycle Execution - 32 x 8 General Purpose Working Registers - Fully Static Operation - Up to 16MIPS Throughput at 16MHz - On-chip 2-cycle Multiplier High Endurance Non-volatile Memory Segments - 4/8/16Kbytes of In-System Self-Programmable Flash program memory - 256/512/512Kbytes EEPROM - 512/1K/1Kbytes Internal SRAM - Write/Erase Cycles: 10,000 Flash/100,000 EEPROM - Optional Boot Code Section with Independent Lock Bits * In-System Programming by On-chip Boot Program * True Read-While-Write Operation - Programming Lock for Software Security Peripheral Features - Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode - One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode - Real Time Counter with Separate Oscillator - Six PWM Channels - 8-channel 10-bit ADC * Temperature Measurement - Programmable Serial USART - Master/Slave SPI Serial Interface - Byte-oriented 2-wire Serial Interface (Philips I2C compatible) - Programmable Watchdog Timer with Separate On-chip Oscillator - On-chip Analog Comparator - Interrupt and Wake-up on Pin Change Special Microcontroller Features - Power-on Reset and Programmable Brown-out Detection - Internal Calibrated Oscillator - External and Internal Interrupt Sources - Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby, and Extended Standby I/O and Packages - 23 Programmable I/O Lines - 32-lead TQFP, and 32-pad QFN Operating Voltage: - 1.8V to 5.5V Temperature Range: - -40C to +125C Speed Grade: - 0 to 4MHz at 1.8V to 5.5V, 0 to 8MHz at 2.7V to 5.5V, 0 to 16MHz at 4.5V to 5.5V Power Consumption - Active Mode: 1.4mA at 4MHz 3V 25C - Power-down Mode: 0.8A 8-bit Microcontroller with 4/8/16K Bytes In-System Programmable Flash Atmel ATmega48PA ATmega88PA ATmega168PA Automotive Preliminary 9223B-AVR-09/11 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 (PCINT19/OC2B/INT1) PD3 (PCINT20/XCK/T0) PD4 GND VCC GND VCC (PCINT6/XTAL1/TOSC1) PB6 (PCINT7/XTAL2/TOSC2) PB7 2 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 PD2 (INT0/PCINT18) PD1 (TXD/PCINT17) PD0 (RXD/PCINT16) PC6 (RESET/PCINT14) PC5 (ADC5/SCL/PCINT13) PC4 (ADC4/SDA/PCINT12) PC3 (ADC3/PCINT11) PC2 (ADC2/PCINT10) 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 PD2 (INT0/PCINT18) PD1 (TXD/PCINT17) PD0 (RXD/PCINT16) PC6 (RESET/PCINT14) PC5 (ADC5/SCL/PCINT13) PC4 (ADC4/SDA/PCINT12) PC3 (ADC3/PCINT11) PC2 (ADC2/PCINT10) Figure 1-1. (PCINT19/OC2B/INT1) PD3 (PCINT20/XCK/T0) PD4 GND VCC GND VCC (PCINT6/XTAL1/TOSC1) PB6 (PCINT7/XTAL2/TOSC2) PB7 NOTE: Bottom pad should be soldered to ground. (PCINT21/OC0B/T1) PD5 (PCINT22/OC0A/AIN0) PD6 (PCINT23/AIN1) PD7 (PCINT0/CLKO/ICP1) PB0 (PCINT1/OC1A) PB1 (PCINT2/SS/OC1B) PB2 (PCINT3/OC2A/MOSI) PB3 (PCINT4/MISO) PB4 (PCINT21/OC0B/T1) PD5 (PCINT22/OC0A/AIN0) PD6 (PCINT23/AIN1) PD7 (PCINT0/CLKO/ICP1) PB0 (PCINT1/OC1A) PB1 (PCINT2/SS/OC1B) PB2 (PCINT3/OC2A/MOSI) PB3 (PCINT4/MISO) PB4 1. Pin Configurations Pinout Atmel(R) ATmega48PA/88PA/168PA 32 TQFP Top View PC1 (ADC1/PCINT9) PC0 (ADC0/PCINT8) ADC7 GND AREF ADC6 AVCC PB5 (SCK/PCINT5) 32 QFN Top View 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 PC1 (ADC1/PCINT9) PC0 (ADC0/PCINT8) ADC7 GND AREF ADC6 AVCC PB5 (SCK/PCINT5) Atmel ATmega48PA/88PA/168PA [Preliminary] 9223B-AVR-09/11 Atmel ATmega48PA/88PA/168PA [Preliminary] 1.1 1.1.1 Pin Descriptions VCC Digital supply voltage. 1.1.2 GND Ground. 1.1.3 Port B (PB7:0) XTAL1/XTAL2/TOSC1/TOSC2 Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Depending on the clock selection fuse settings, PB6 can be used as input to the inverting Oscillator amplifier and input to the internal clock operating circuit. Depending on the clock selection fuse settings, PB7 can be used as output from the inverting Oscillator amplifier. If the Internal Calibrated RC Oscillator is used as chip clock source, PB7...6 is used as TOSC2...1 input for the Asynchronous Timer/Counter2 if the AS2 bit in ASSR is set. The various special features of Port B are elaborated in "Alternate Functions of Port B" on page 81 and "System Clock and Clock Options" on page 26. 1.1.4 Port C (PC5:0) Port C is a 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The PC5...0 output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running. 1.1.5 PC6/RESET If the RSTDISBL Fuse is programmed, PC6 is used as an I/O pin. Note that the electrical characteristics of PC6 differ from those of the other pins of Port C. If the RSTDISBL Fuse is unprogrammed, PC6 is used as a Reset input. A low level on this pin for longer than the minimum pulse length will generate a Reset, even if the clock is not running. The minimum pulse length is given in Table 29-5 on page 318. Shorter pulses are not guaranteed to generate a Reset. The various special features of Port C are elaborated in "Alternate Functions of Port C" on page 85. 3 9223B-AVR-09/11 1.1.6 Port D (PD7:0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. The various special features of Port D are elaborated in "Alternate Functions of Port D" on page 88. 1.1.7 AVCC AVCC is the supply voltage pin for the A/D Converter, PC3:0, and ADC7:6. It should be externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter. Note that PC6...4 use digital supply voltage, VCC. 1.1.8 AREF AREF is the analog reference pin for the A/D Converter. 1.1.9 4 ADC7:6 (TQFP and QFN Package Only) In the TQFP and QFN package, ADC7:6 serve as analog inputs to the A/D converter. These pins are powered from the analog supply and serve as 10-bit ADC channels. Atmel ATmega48PA/88PA/168PA [Preliminary] 9223B-AVR-09/11 Atmel ATmega48PA/88PA/168PA [Preliminary] 2. Overview The Atmel(R) ATmega48PA/88PA/168PA is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the Atmel ATmega48PA/88PA/168PA achieves throughputs approaching 1 MIPS perMHz allowing the system designer to optimize power consumption versus processing speed. Block Diagram Block Diagram GND Figure 2-1. VCC 2.1 Watchdog Timer Watchdog Oscillator Oscillator Circuits / Clock Generation Power Supervision POR / BOD & RESET debugWIRE Flash SRAM PROGRAM LOGIC CPU EEPROM AVCC AREF DATABUS GND 8bit T/C 0 16bit T/C 1 A/D Conv. 8bit T/C 2 Analog Comp. Internal Bandgap USART 0 SPI TWI PORT D (8) PORT B (8) PORT C (7) 2 6 RESET XTAL[1..2] PD[0..7] PB[0..7] PC[0..6] ADC[6..7] The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. 5 9223B-AVR-09/11 The Atmel (R) ATmega48PA/88PA/168PA provides the following features: 4K/8K bytes of In-System Programmable Flash with Read-While-Write capabilities, 256/512/512K bytes EEPROM, 512/1K/1K bytes SRAM, 23 general purpose I/O lines, 32 general purpose working registers, three flexible Timer/Counters with compare modes, internal and external interrupts, a serial programmable USART, a byte-oriented 2-wire Serial Interface, an SPI serial port, a 8-channel 10-bit ADC, a programmable Watchdog Timer with internal Oscillator, and five software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, USART, 2-wire Serial Interface, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or hardware reset. In Power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except asynchronous timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low power consumption. The device is manufactured using Atmel's high density non-volatile memory technology. The On-chip ISP Flash allows the program memory to be reprogrammed In-System through an SPI serial interface, by a conventional non-volatile memory programmer, or by an On-chip Boot program running on the AVR core. The Boot program can use any interface to download the application program in the Application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega48PA/88PA/168PA is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The Atmel ATmega48PA/88PA/168PA AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kits. 2.2 Comparison Between Processors The Atmel ATmega48PA/88PA/168PA differ only in memory sizes, boot loader support, and interrupt vector sizes. Table 2-1 summarizes the different memory and interrupt vector sizes for the devices. Table 2-1. Memory Size Summary Device Flash EEPROM RAM Interrupt Vector Size 4K Bytes 256 Bytes 512 Bytes 1 instruction word/vector Atmel ATmega88PA 8K Bytes 512 Bytes 1K Bytes 1 instruction word/vector Atmel ATmega168PA 16K Bytes 512 Bytes 1K Bytes 2 instruction words/vector Atmel ATmega48PA/ The Atmel ATmega48PA/88PA/168PA support a real Read-While-Write Self-Programming mechanism. There is a separate Boot Loader Section, and the SPM instruction can only execute from there. In the Atmel ATmega48PA there is no Read-While-Write support and no separate Boot Loader Section. The SPM instruction can execute from the entire Flash. 6 Atmel ATmega48PA/88PA/168PA [Preliminary] 9223B-AVR-09/11 Atmel ATmega48PA/88PA/168PA [Preliminary] 3. Automotive Quality Grade The Atmel(R) ATmega48PA/88PA/168PA have been developed and manufactured according to the most stringent requirements of the international standard ISO-TS-16949. This data sheet contains limit values extracted from the results of extensive characterization (Temperature and Voltage). The quality and reliability of the Atmel ATmega48PA/88PA/168PA have been verified during regular product qualification as per AEC-Q100 grade 1 (-40C to +125C). Table 3-1. Temperature Grade Identification for Automotive Products Temperature (C) Temperature Identifier Comments -40; +125 Z Full Automotive Temperature Range 4. Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. Note: 1. 5. Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85C. 6. About Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details. For I/O Registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI" instructions must be replaced with instructions that allow access to extended I/O. Typically "LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and "CBR". 7 9223B-AVR-09/11 7. AVR CPU Core 7.1 Overview This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. Figure 7-1. Block Diagram of the AVR Architecture Data Bus 8-bit Flash Program Memory Program Counter Status and Control 32 x 8 General Purpose Registrers Control Lines Direct Addressing Instruction Decoder Indirect Addressing Instruction Register Interrupt Unit SPI Unit Watchdog Timer ALU Analog Comparator I/O Module1 Data SRAM I/O Module 2 I/O Module n EEPROM I/O Lines In order to maximize performance and parallelism, the AVR uses a Harvard architecture - with separate memories and buses for program and data. Instructions in the program memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is In-System Reprogrammable Flash memory. 8 Atmel ATmega48PA/88PA/168PA [Preliminary] 9223B-AVR-09/11 Atmel ATmega48PA/88PA/168PA [Preliminary] The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File - in one clock cycle. Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing - enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section. The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect information about the result of the operation. Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions have a single 16-bit word format. Every program memory address contains a 16- or 32-bit instruction. Program Flash memory space is divided in two sections, the Boot Program section and the Application Program section. Both sections have dedicated Lock bits for write and read/write protection. The SPM instruction that writes into the Application Flash memory section must reside in the Boot Program section. During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture. The memory spaces in the AVR architecture are all linear and regular memory maps. A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority. The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition, the Atmel (R) ATmega48PA/88PA/168PA has Extended I/O space from 0x60 - 0xFF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used. 7.2 ALU - Arithmetic Logic Unit The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. The ALU operations are divided into three main categories - arithmetic, logical, and bit-functions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See the "Instruction Set" section for a detailed description. 9 9223B-AVR-09/11 7.3 Status Register The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software. 7.3.1 SREG - AVR Status Register The AVR Status Register - SREG - is defined as: Bit 7 6 5 4 3 2 1 0 0x3F (0x5F) I T H S V N Z C Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SREG * Bit 7 - I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI instructions, as described in the instruction set reference. * Bit 6 - T: Bit Copy Storage The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction. * Bit 5 - H: Half Carry Flag The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Is useful in BCD arithmetic. See the "Instruction Set Description" for detailed information. * Bit 4 - S: Sign Bit, S = N V The S-bit is always an exclusive or between the Negative Flag N and the Two's Complement Overflow Flag V. See the "Instruction Set Description" for detailed information. * Bit 3 - V: Two's Complement Overflow Flag The Two's Complement Overflow Flag V supports two's complement arithmetic. See the "Instruction Set Description" for detailed information. * Bit 2 - N: Negative Flag The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the "Instruction Set Description" for detailed information. 10 Atmel ATmega48PA/88PA/168PA [Preliminary] 9223B-AVR-09/11 Atmel ATmega48PA/88PA/168PA [Preliminary] * Bit 1 - Z: Zero Flag The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the "Instruction Set Description" for detailed information. * Bit 0 - C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the "Instruction Set Description" for detailed information. 7.4 General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File: * One 8-bit output operand and one 8-bit result input * Two 8-bit output operands and one 8-bit result input * Two 8-bit output operands and one 16-bit result input * One 16-bit output operand and one 16-bit result input Figure 7-2 shows the structure of the 32 general purpose working registers in the CPU. Figure 7-2. AVR CPU General Purpose Working Registers 7 0 Addr. R0 0x00 R1 0x01 R2 0x02 ... R13 0x0D General R14 0x0E Purpose R15 0x0F Working R16 0x10 Registers R17 0x11 ... R26 0x1A X-register Low Byte R27 0x1B X-register High Byte R28 0x1C Y-register Low Byte R29 0x1D Y-register High Byte R30 0x1E Z-register Low Byte R31 0x1F Z-register High Byte Most of the instructions operating on the Register File have direct access to all registers, and most of them are single cycle instructions. As shown in Figure 7-2, each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file. 11 9223B-AVR-09/11 7.4.1 The X-register, Y-register, and Z-register The registers R26...R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure 7-3. Figure 7-3. The X-, Y-, and Z-registers 15 X-register XH 7 XL 0 R27 (0x1B) 15 Y-register 0 R26 (0x1A) YH 7 YL 0 R29 (0x1D) Z-register 0 7 0 7 0 R28 (0x1C) 15 ZH 7 0 R31 (0x1F) ZL 7 0 0 R30 (0x1E) In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details). 7.5 Stack Pointer The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. Note that the Stack is implemented as growing from higher to lower memory locations. The Stack Pointer Register always points to the top of the Stack. The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. A Stack PUSH command will decrease the Stack Pointer. The Stack in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. Initial Stack Pointer value equals the last address of the internal SRAM and the Stack Pointer must be set to point above start of the SRAM, see Table 8-3 on page 18. See Table 7-1 for Stack Pointer details. Table 7-1. Stack Pointer Instructions Instruction Stack pointer Description PUSH Decremented by 1 Data is pushed onto the stack CALL ICALL RCALL Decremented by 2 Return address is pushed onto the stack with a subroutine call or interrupt POP Incremented by 1 Data is popped from the stack RET RETI Incremented by 2 Return address is popped from the stack with return from subroutine or return from interrupt The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some implementations of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present. 12 Atmel ATmega48PA/88PA/168PA [Preliminary] 9223B-AVR-09/11 Atmel ATmega48PA/88PA/168PA [Preliminary] 7.5.1 SPH and SPL - Stack Pointer High and Stack Pointer Low Register Bit 15 14 13 12 11 10 9 8 0x3E (0x5E) SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH 0x3D (0x5D) SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND Read/Write Initial Value 7.6 Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used. Figure 7-4 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS perMHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit. Figure 7-4. The Parallel Instruction Fetches and Instruction Executions T1 T2 T3 T4 clkCPU 1st Instruction Fetch 1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch Figure 7-5 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register. Figure 7-5. Single Cycle ALU Operation T1 T2 T3 T4 clkCPU Total Execution Time Register Operands Fetch ALU Operation Execute Result Write Back 13 9223B-AVR-09/11 7.7 Reset and Interrupt Handling The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate program vector in the program memory space. All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt. Depending on the Program Counter value, interrupts may be automatically disabled when Boot Lock bits BLB02 or BLB12 are programmed. This feature improves software security. See the section "Memory Programming" on page 294 for details. The lowest addresses in the program memory space are by default defined as the Reset and Interrupt Vectors. The complete list of vectors is shown in "Interrupts" on page 58. The list also determines the priority levels of the different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next is INT0 - the External Interrupt Request 0. The Interrupt Vectors can be moved to the start of the Boot Flash section by setting the IVSEL bit in the MCU Control Register (MCUCR). Refer to "Interrupts" on page 58 for more information. The Reset Vector can also be moved to the start of the Boot Flash section by programming the BOOTRST Fuse, see "Boot Loader Support - Read-While-Write Self-Programming" on page 277. When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction - RETI - is executed. There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the Global Interrupt Enable bit is set, and will then be executed by order of priority. The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered. When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served. Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by software. When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence. 14 Atmel ATmega48PA/88PA/168PA [Preliminary] 9223B-AVR-09/11 Atmel ATmega48PA/88PA/168PA [Preliminary] Assembly Code Example in r16, SREG cli ; store SREG value ; disable interrupts during timed sequence sbi EECR, EEMPE ; start EEPROM write sbi EECR, EEPE out SREG, r16 ; restore SREG value (I-bit) C Code Example char cSREG; cSREG = SREG; /* store SREG value */ /* disable interrupts during timed sequence */ _CLI(); EECR |= (1< ... ... ; Set Stack Pointer to top of RAM xxx ... 59 9223B-AVR-09/11 12.2 Interrupt Vectors in the Atmel ATmega88PA Table 12-2. Vector No. Reset and Interrupt Vectors in the Atmel ATmega88PA Program Address(2) Source Interrupt Definition RESET External Pin, Power-on Reset, Brown-out Reset and Watchdog System Reset 0x001 INT0 External Interrupt Request 0 3 0x002 INT1 External Interrupt Request 1 4 0x003 PCINT0 Pin Change Interrupt Request 0 5 0x004 PCINT1 Pin Change Interrupt Request 1 6 0x005 PCINT2 Pin Change Interrupt Request 2 7 0x006 WDT Watchdog Time-out Interrupt 8 0x007 TIMER2 COMPA Timer/Counter2 Compare Match A 1 0x000(1) 2 9 0x008 TIMER2 COMPB Timer/Counter2 Compare Match B 10 0x009 TIMER2 OVF Timer/Counter2 Overflow 11 0x00A TIMER1 CAPT Timer/Counter1 Capture Event 12 0x00B TIMER1 COMPA Timer/Counter1 Compare Match A 13 0x00C TIMER1 COMPB Timer/Coutner1 Compare Match B 14 0x00D TIMER1 OVF Timer/Counter1 Overflow 15 0x00E TIMER0 COMPA Timer/Counter0 Compare Match A 16 0x00F TIMER0 COMPB Timer/Counter0 Compare Match B 17 0x010 TIMER0 OVF Timer/Counter0 Overflow 18 0x011 SPI, STC SPI Serial Transfer Complete 19 0x012 USART, RX USART Rx Complete 20 0x013 USART, UDRE USART, Data Register Empty 21 0x014 USART, TX USART, Tx Complete 22 0x015 ADC ADC Conversion Complete 23 0x016 EE READY EEPROM Ready 24 0x017 ANALOG COMP Analog Comparator 25 0x018 TWI 2-wire Serial Interface 26 0x019 SPM READY Store Program Memory Ready Notes: 1. When the BOOTRST Fuse is programmed, the device will jump to the Boot Loader address at reset, see "Boot Loader Support - Read-While-Write Self-Programming" on page 277. 2. When the IVSEL bit in MCUCR is set, Interrupt Vectors will be moved to the start of the Boot Flash Section. The address of each Interrupt Vector will then be the address in this table added to the start address of the Boot Flash Section. Table 12-3 on page 61 shows reset and Interrupt Vectors placement for the various combinations of BOOTRST and IVSEL settings. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. This is also the case if the Reset Vector is in the Application section while the Interrupt Vectors are in the Boot section or vice versa. 60 Atmel ATmega48PA/88PA/168PA [Preliminary] 9223B-AVR-09/11 Atmel ATmega48PA/88PA/168PA [Preliminary] Table 12-3. Reset and Interrupt Vectors Placement in the Atmel ATmega88PA(1) BOOTRST IVSEL Reset Address Interrupt Vectors Start Address 1 0 0x000 0x001 1 1 0x000 Boot Reset Address + 0x001 0 0 Boot Reset Address 0x001 1 Boot Reset Address Boot Reset Address + 0x001 0 Note: 1. The Boot Reset Address is shown in Table 27-7 on page 290. For the BOOTRST Fuse "1" means unprogrammed while "0" means programmed. The most typical and general program setup for the Reset and Interrupt Vector Addresses in the Atmel(R) ATmega88PA is: Address Labels Code Comments 0x000 rjmp RESET ; Reset Handler 0x001 rjmp EXT_INT0 ; IRQ0 Handler 0x002 rjmp EXT_INT1 ; IRQ1 Handler 0x003 rjmp PCINT0 ; PCINT0 Handler 0x004 rjmp PCINT1 ; PCINT1 Handler 0x005 rjmp PCINT2 ; PCINT2 Handler 0x006 rjmp WDT ; Watchdog Timer Handler 0x007 rjmp TIM2_COMPA ; Timer2 Compare A Handler 0X008 rjmp TIM2_COMPB ; Timer2 Compare B Handler 0x009 rjmp TIM2_OVF ; Timer2 Overflow Handler 0x00A rjmp TIM1_CAPT ; Timer1 Capture Handler 0x00B rjmp TIM1_COMPA ; Timer1 Compare A Handler 0x00C rjmp TIM1_COMPB ; Timer1 Compare B Handler 0x00D rjmp TIM1_OVF ; Timer1 Overflow Handler 0x00E rjmp TIM0_COMPA ; Timer0 Compare A Handler 0x00F rjmp TIM0_COMPB ; Timer0 Compare B Handler 0x010 rjmp TIM0_OVF ; Timer0 Overflow Handler 0x011 rjmp SPI_STC ; SPI Transfer Complete Handler 0x012 rjmp USART_RXC ; USART, RX Complete Handler 0x013 rjmp USART_UDRE ; USART, UDR Empty Handler 0x014 rjmp USART_TXC ; USART, TX Complete Handler 0x015 rjmp ADC ; ADC Conversion Complete Handler 0x016 rjmp EE_RDY ; EEPROM Ready Handler 0x017 rjmp ANA_COMP ; Analog Comparator Handler 0x018 rjmp TWI ; 2-wire Serial Interface Handler 0x019 rjmp SPM_RDY ; Store Program Memory Ready Handler 0x01ARESET: ldi r16, high(RAMEND); Main program start 0x01B out SPH,r16 0x01C ldi r16, low(RAMEND) 0x01D 0x01E out sei SPL,r16 0x01F ; ; Set Stack Pointer to top of RAM ; Enable interrupts xxx 61 9223B-AVR-09/11 When the BOOTRST Fuse is unprogrammed, the Boot section size set to 2K bytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses in the Atmel (R) ATmega88PA is: Address Labels Code Comments 0x000 RESET: ldi r16,high(RAMEND); Main program start 0x001 out SPH,r16 0x002 ldi r16,low(RAMEND) 0x003 0x004 out sei SPL,r16 0x005 ; Set Stack Pointer to top of RAM ; Enable interrupts xxx ; .org 0xC01 0xC01 rjmp EXT_INT0 ; IRQ0 Handler 0xC02 rjmp EXT_INT1 ; IRQ1 Handler ... ... ... ; 0xC19 rjmp SPM_RDY ; Store Program Memory Ready Handler When the BOOTRST Fuse is programmed and the Boot section size set to 2K bytes, the most typical and general program setup for the Reset and Interrupt Vector Addresses in the Atmel ATmega88PA is: Address Labels Code Comments .org 0x001 0x001 rjmp EXT_INT0 ; IRQ0 Handler 0x002 rjmp EXT_INT1 ; IRQ1 Handler ... ... ... ; 0x019 rjmp SPM_RDY ; Store Program Memory Ready Handler ; .org 0xC00 0xC00 RESET: ldi r16,high(RAMEND); Main program start 0xC01 out SPH,r16 0xC02 ldi r16,low(RAMEND) 0xC03 0xC04 out sei SPL,r16 0xC05 ; Set Stack Pointer to top of RAM ; Enable interrupts xxx When the BOOTRST Fuse is programmed, the Boot section size set to 2K bytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses in the Atmel ATmega88PA is: Address Labels Code Comments ; 62 .org 0xC00 0xC00 rjmp RESET ; Reset handler 0xC01 rjmp EXT_INT0 ; IRQ0 Handler 0xC02 rjmp EXT_INT1 ; IRQ1 Handler ... ... ... ; Atmel ATmega48PA/88PA/168PA [Preliminary] 9223B-AVR-09/11 Atmel ATmega48PA/88PA/168PA [Preliminary] 0xC19 rjmp SPM_RDY ; Store Program Memory Ready Handler ; 12.3 0xC1A RESET: ldi r16,high(RAMEND); Main program start 0xC1B out SPH,r16 0xC1C ldi r16,low(RAMEND) 0xC1D 0xC1E out sei SPL,r16 0xC1F ; Set Stack Pointer to top of RAM ; Enable interrupts xxx Interrupt Vectors in the Atmel ATmega168PA Table 12-4. Reset and Interrupt Vectors in the Atmel ATmega168PA VectorNo. Program Address(2) Source Interrupt Definition 1 0x0000(1) RESET External Pin, Power-on Reset, Brown-out Reset and Watchdog System Reset 2 0x0002 INT0 External Interrupt Request 0 3 0x0004 INT1 External Interrupt Request 1 4 0x0006 PCINT0 Pin Change Interrupt Request 0 5 0x0008 PCINT1 Pin Change Interrupt Request 1 6 0x000A PCINT2 Pin Change Interrupt Request 2 7 0x000C WDT Watchdog Time-out Interrupt 8 0x000E TIMER2 COMPA Timer/Counter2 Compare Match A 9 0x0010 TIMER2 COMPB Timer/Counter2 Compare Match B 10 0x0012 TIMER2 OVF Timer/Counter2 Overflow 11 0x0014 TIMER1 CAPT Timer/Counter1 Capture Event 12 0x0016 TIMER1 COMPA Timer/Counter1 Compare Match A 13 0x0018 TIMER1 COMPB Timer/Coutner1 Compare Match B 14 0x001A TIMER1 OVF Timer/Counter1 Overflow 15 0x001C TIMER0 COMPA Timer/Counter0 Compare Match A 16 0x001E TIMER0 COMPB Timer/Counter0 Compare Match B 17 0x0020 TIMER0 OVF Timer/Counter0 Overflow 18 0x0022 SPI, STC SPI Serial Transfer Complete 19 0x0024 USART, RX USART Rx Complete 20 0x0026 USART, UDRE USART, Data Register Empty 21 0x0028 USART, TX USART, Tx Complete 22 0x002A ADC ADC Conversion Complete 23 0x002C EE READY EEPROM Ready 24 0x002E ANALOG COMP Analog Comparator 25 0x0030 TWI 2-wire Serial Interface 26 0x0032 SPM READY Store Program Memory Ready Notes: 1. When the BOOTRST Fuse is programmed, the device will jump to the Boot Loader address at reset, see "Boot Loader Support - Read-While-Write Self-Programming" on page 277. 2. When the IVSEL bit in MCUCR is set, Interrupt Vectors will be moved to the start of the Boot Flash Section. The address of each Interrupt Vector will then be the address in this table added to the start address of the Boot Flash Section. 63 9223B-AVR-09/11 Table 12-5 on page 64 shows reset and Interrupt Vectors placement for the various combinations of BOOTRST and IVSEL settings. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. This is also the case if the Reset Vector is in the Application section while the Interrupt Vectors are in the Boot section or vice versa. Table 12-5. Reset and Interrupt Vectors Placement in the Atmel ATmega168PA(1) BOOTRST IVSEL 1 1 Note: Reset Address Interrupt Vectors Start Address 0 0x000 0x002 1 0x000 Boot Reset Address + 0x0002 0 0 Boot Reset Address 0x002 0 1 Boot Reset Address Boot Reset Address + 0x0002 1. The Boot Reset Address is shown in Table 27-7 on page 290. For the BOOTRST Fuse "1" means unprogrammed while "0" means programmed. The most typical and general program setup for the Reset and Interrupt Vector Addresses in the Atmel(R) ATmega168PA is: Address Labels Code Comments 0x0000 jmp RESET ; Reset Handler 0x0002 jmp EXT_INT0 ; IRQ0 Handler 0x0004 jmp EXT_INT1 ; IRQ1 Handler 0x0006 jmp PCINT0 ; PCINT0 Handler 0x0008 jmp PCINT1 ; PCINT1 Handler 0x000A jmp PCINT2 ; PCINT2 Handler 0x000C jmp WDT ; Watchdog Timer Handler 0x000E jmp TIM2_COMPA ; Timer2 Compare A Handler 0x0010 jmp TIM2_COMPB ; Timer2 Compare B Handler 0x0012 jmp TIM2_OVF ; Timer2 Overflow Handler 0x0014 jmp TIM1_CAPT ; Timer1 Capture Handler 0x0016 jmp TIM1_COMPA ; Timer1 Compare A Handler 0x0018 jmp TIM1_COMPB ; Timer1 Compare B Handler 0x001A jmp TIM1_OVF ; Timer1 Overflow Handler 0x001C jmp TIM0_COMPA ; Timer0 Compare A Handler 0x001E jmp TIM0_COMPB ; Timer0 Compare B Handler 0x0020 jmp TIM0_OVF ; Timer0 Overflow Handler 0x0022 jmp SPI_STC ; SPI Transfer Complete Handler 0x0024 jmp USART_RXC ; USART, RX Complete Handler 0x0026 jmp USART_UDRE ; USART, UDR Empty Handler 0x0028 jmp USART_TXC ; USART, TX Complete Handler 0x002A jmp ADC ; ADC Conversion Complete Handler 0x002C jmp EE_RDY ; EEPROM Ready Handler 0x002E jmp ANA_COMP ; Analog Comparator Handler 0x0030 jmp TWI ; 2-wire Serial Interface Handler 0x0032 jmp SPM_RDY ; Store Program Memory Ready Handler ; 64 Atmel ATmega48PA/88PA/168PA [Preliminary] 9223B-AVR-09/11 Atmel ATmega48PA/88PA/168PA [Preliminary] 0x0033RESET: ldi r16, high(RAMEND); Main program start 0x0034 out SPH,r16 0x0035 ldi r16, low(RAMEND) 0x0036 out SPL,r16 0x0037 sei 0x0038 ... ; Enable interrupts ... ... ; Set Stack Pointer to top of RAM xxx ... When the BOOTRST Fuse is unprogrammed, the Boot section size set to 2K bytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses in the Atmel (R) ATmega168PA is: Address Labels Code Comments 0x0000 RESET: ldi 0x0001 out r16,high(RAMEND); Main program start SPH,r16 0x0002 ldi r16,low(RAMEND) 0x0003 0x0004 out sei SPL,r16 0x0005 ; Set Stack Pointer to top of RAM ; Enable interrupts xxx ; .org 0x1C02 0x1C02 jmp EXT_INT0 ; IRQ0 Handler 0x1C04 jmp EXT_INT1 ; IRQ1 Handler ... ... ... ; 0x1C32 jmp SPM_RDY ; Store Program Memory Ready Handler When the BOOTRST Fuse is programmed and the Boot section size set to 2K bytes, the most typical and general program setup for the Reset and Interrupt Vector Addresses in the Atmel ATmega168PA is: Address Labels Code Comments .org 0x0002 0x0002 jmp EXT_INT0 ; IRQ0 Handler 0x0004 jmp EXT_INT1 ; IRQ1 Handler ... ... ... ; 0x0032 jmp SPM_RDY ; Store Program Memory Ready Handler ; .org 0x1C00 0x1C00 RESET: ldi r16,high(RAMEND); Main program start 0x1C01 out SPH,r16 0x1C02 ldi r16,low(RAMEND) 0x1C03 0x1C04 out sei SPL,r16 0x1C05 ; Set Stack Pointer to top of RAM ; Enable interrupts xxx 65 9223B-AVR-09/11 When the BOOTRST Fuse is programmed, the Boot section size set to 2K bytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses in the Atmel (R) ATmega168PA is: Address Labels Code Comments ; .org 0x1C00 0x1C00 jmp RESET ; Reset handler 0x1C02 jmp EXT_INT0 ; IRQ0 Handler 0x1C04 jmp EXT_INT1 ; IRQ1 Handler ... ... ... ; 0x1C32 jmp SPM_RDY ; Store Program Memory Ready Handler ; 12.4 12.4.1 0x1C33 RESET: ldi r16,high(RAMEND); Main program start 0x1C34 out SPH,r16 0x1C35 ldi r16,low(RAMEND) 0x1C36 0x1C37 out sei SPL,r16 0x1C38 ; Set Stack Pointer to top of RAM ; Enable interrupts xxx Register Description Moving Interrupts Between Application and Boot Space, Atmel ATmega88PA, ATmega168PA The MCU Control Register controls the placement of the Interrupt Vector table. MCUCR - MCU Control Register Bit 7 6 5 4 3 2 1 0 0x35 (0x55) - BODS(1) BODSE(1) PUD - - IVSEL IVCE Read/Write R R/W R/W R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 Note: MCUCR 1. BODS and BODSE only available for picoPower devices ATmega48PA/88PA/168PA * Bit 1 - IVSEL: Interrupt Vector Select When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash memory. When this bit is set (one), the Interrupt Vectors are moved to the beginning of the Boot Loader section of the Flash. The actual address of the start of the Boot Flash Section is determined by the BOOTSZ Fuses. Refer to the section "Boot Loader Support - Read-While-Write Self-Programming" on page 277 for details. To avoid unintentional changes of Interrupt Vector tables, a special write procedure must be followed to change the IVSEL bit: a. Write the Interrupt Vector Change Enable (IVCE) bit to one. b. 66 Within four cycles, write the desired value to IVSEL while writing a zero to IVCE. Atmel ATmega48PA/88PA/168PA [Preliminary] 9223B-AVR-09/11 Atmel ATmega48PA/88PA/168PA [Preliminary] Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled in the cycle IVCE is set, and they remain disabled until after the instruction following the write to IVSEL. If IVSEL is not written, interrupts remain disabled for four cycles. The I-bit in the Status Register is unaffected by the automatic disabling. Note: If Interrupt Vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is programmed, interrupts are disabled while executing from the Application section. If Interrupt Vectors are placed in the Application section and Boot Lock bit BLB12 is programed, interrupts are disabled while executing from the Boot Loader section. Refer to the section "Boot Loader Support - Read-While-Write Self-Programming" on page 277 for details on Boot Lock bits. * Bit 0 - IVCE: Interrupt Vector Change Enable The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable interrupts, as explained in the IVSEL description above. See Code Example below. Assembly Code Example Move_interrupts: ; Enable change of Interrupt Vectors ldi r16, (1< CSn2:0 > 1). The number of system clock cycles from when the timer is enabled to the first count occurs can be from 1 to N+1 system clock cycles, where N equals the prescaler divisor (8, 64, 256, or 1024). It is possible to use the prescaler reset for synchronizing the Timer/Counter to program execution. However, care must be taken if the other Timer/Counter that shares the same prescaler also uses prescaling. A prescaler reset will affect the prescaler period for all Timer/Counters it is connected to. 17.3 External Clock Source An external clock source applied to the T1/T0 pin can be used as Timer/Counter clock (clkT1/clkT0). The T1/T0 pin is sampled once every system clock cycle by the pin synchronization logic. The synchronized (sampled) signal is then passed through the edge detector. Figure 17-1 shows a functional equivalent block diagram of the T1/T0 synchronization and edge detector logic. The registers are clocked at the positive edge of the internal system clock (clkI/O). The latch is transparent in the high period of the internal system clock. The edge detector generates one clkT1/clkT0 pulse for each positive (CSn2:0 = 7) or negative (CSn2:0 = 6) edge it detects. Figure 17-1. T1/T0 Pin Sampling Tn D Q D Q D Tn_sync (To Clock Select Logic) Q LE clk I/O Synchronization Edge Detector The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles from an edge has been applied to the T1/T0 pin to the counter is updated. 140 Atmel ATmega48PA/88PA/168PA [Preliminary] 9223B-AVR-09/11 Atmel ATmega48PA/88PA/168PA [Preliminary] Enabling and disabling of the clock input must be done when T1/T0 has been stable for at least one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated. Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling. The external clock must be guaranteed to have less than half the system clock frequency (fExtClk < fclk_I/O/2) given a 50/50% duty cycle. Since the edge detector uses sampling, the maximum frequency of an external clock it can detect is half the sampling frequency (Nyquist sampling theorem). However, due to variation of the system clock frequency and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is recommended that maximum frequency of an external clock source is less than fclk_I/O/2.5. An external clock source can not be prescaled. Figure 17-2. Prescaler for Timer/Counter0 and Timer/Counter1(1) clk I/O Clear PSRSYNC T0 Synchronization T1 Synchronization clkT1 Note: clkT0 1. The synchronization logic on the input pins (T1/T0) is shown in Figure 17-1. 141 9223B-AVR-09/11 17.4 17.4.1 Register Description GTCCR - General Timer/Counter Control Register Bit 7 6 5 4 3 2 1 0 0x23 (0x43) TSM - - - - - PSRASY PSRSYNC Read/Write R/W R R R R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 GTCCR * Bit 7 - TSM: Timer/Counter Synchronization Mode Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value that is written to the PSRASY and PSRSYNC bits is kept, hence keeping the corresponding prescaler reset signals asserted. This ensures that the corresponding Timer/Counters are halted and can be configured to the same value without the risk of one of them advancing during configuration. When the TSM bit is written to zero, the PSRASY and PSRSYNC bits are cleared by hardware, and the Timer/Counters start counting simultaneously. * Bit 0 - PSRSYNC: Prescaler Reset When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both timers. 142 Atmel ATmega48PA/88PA/168PA [Preliminary] 9223B-AVR-09/11 Atmel ATmega48PA/88PA/168PA [Preliminary] 18. 8-bit Timer/Counter2 with PWM and Asynchronous Operation 18.1 Features * * * * * * * 18.2 Single Channel Counter Clear Timer on Compare Match (Auto Reload) Glitch-free, Phase Correct Pulse Width Modulator (PWM) Frequency Generator 10-bit Clock Prescaler Overflow and Compare Match Interrupt Sources (TOV2, OCF2A and OCF2B) Allows Clocking from External 32kHz Watch Crystal Independent of the I/O Clock Overview Timer/Counter2 is a general purpose, single channel, 8-bit Timer/Counter module. A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 18-1. For the actual placement of I/O pins, refer to "Pinout Atmel(R) ATmega48PA/88PA/168PA" on page 2. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the "Register Description" on page 158. The PRTIM2 bit in "Minimizing Power Consumption" on page 42 must be written to zero to enable Timer/Counter2 module. Figure 18-1. 8-bit Timer/Counter Block Diagram Count Clear Direction TOVn (Int.Req.) Control Logic clkTn Clock Select Edge Detector TOP Tn BOTTOM ( From Prescaler ) Timer/Counter TCNTn = =0 OCnA (Int.Req.) Waveform Generation = OCnA DATA BUS OCRnA Fixed TOP Value OCnB (Int.Req.) Waveform Generation = OCnB OCRnB TCCRnA TCCRnB 143 9223B-AVR-09/11 18.2.1 Registers The Timer/Counter (TCNT2) and Output Compare Register (OCR2A and OCR2B) are 8-bit registers. Interrupt request (shorten as Int.Req.) signals are all visible in the Timer Interrupt Flag Register (TIFR2). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK2). TIFR2 and TIMSK2 are not shown in the figure. The Timer/Counter can be clocked internally, via the prescaler, or asynchronously clocked from the TOSC1/2 pins, as detailed later in this section. The asynchronous operation is controlled by the Asynchronous Status Register (ASSR). The Clock Select logic block controls which clock source he Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select logic is referred to as the timer clock (clkT2). The double buffered Output Compare Register (OCR2A and OCR2B) are compared with the Timer/Counter value at all times. The result of the compare can be used by the Waveform Generator to generate a PWM or variable frequency output on the Output Compare pins (OC2A and OC2B). See "Output Compare Unit" on page 146 for details. The compare match event will also set the Compare Flag (OCF2A or OCF2B) which can be used to generate an Output Compare interrupt request. 18.2.2 Definitions Many register and bit references in this document are written in general form. A lower case "n" replaces the Timer/Counter number, in this case 2. However, when using the register or bit defines in a program, the precise form must be used, i.e., TCNT2 for accessing Timer/Counter2 counter value and so on. The definitions in Table 18-1 are also used extensively throughout the section. Table 18-1. BOTTOM 18.3 Definitions The counter reaches the BOTTOM when it becomes zero (0x00). MAX The counter reaches its MAXimum when it becomes 0xFF (decimal 255). TOP The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be the fixed value 0xFF (MAX) or the value stored in the OCR2A Register. The assignment is dependent on the mode of operation. Timer/Counter Clock Sources The Timer/Counter can be clocked by an internal synchronous or an external asynchronous clock source. The clock source clkT2 is by default equal to the MCU clock, clkI/O. When the AS2 bit in the ASSR Register is written to logic one, the clock source is taken from the Timer/Counter Oscillator connected to TOSC1 and TOSC2. For details on asynchronous operation, see "ASSR - Asynchronous Status Register" on page 164. For details on clock sources and prescaler, see "Timer/Counter Prescaler" on page 157. 144 Atmel ATmega48PA/88PA/168PA [Preliminary] 9223B-AVR-09/11 Atmel ATmega48PA/88PA/168PA [Preliminary] 18.4 Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure 18-2 on page 145 shows a block diagram of the counter and its surrounding environment. Figure 18-2. Counter Unit Block Diagram TOVn (Int.Req.) DATA BUS TOSC1 count TCNTn clear Control Logic clk Tn Prescaler T/C Oscillator direction bottom TOSC2 top clk I/O Signal description (internal signals): count Increment or decrement TCNT2 by 1. direction Selects between increment and decrement. clear Clear TCNT2 (set all bits to zero). clkTn Timer/Counter clock, referred to as clkT2 in the following. top Signalizes that TCNT2 has reached maximum value. bottom Signalizes that TCNT2 has reached minimum value (zero). Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkT2). clkT2 can be generated from an external or internal clock source, selected by the Clock Select bits (CS22:0). When no clock source is selected (CS22:0 = 0) the timer is stopped. However, the TCNT2 value can be accessed by the CPU, regardless of whether clkT2 is present or not. A CPU write overrides (has priority over) all counter clear or count operations. The counting sequence is determined by the setting of the WGM21 and WGM20 bits located in the Timer/Counter Control Register (TCCR2A) and the WGM22 located in the Timer/Counter Control Register B (TCCR2B). There are close connections between how the counter behaves (counts) and how waveforms are generated on the Output Compare outputs OC2A and OC2B. For more details about advanced counting sequences and waveform generation, see "Modes of Operation" on page 149. The Timer/Counter Overflow Flag (TOV2) is set according to the mode of operation selected by the WGM22:0 bits. TOV2 can be used for generating a CPU interrupt. 145 9223B-AVR-09/11 18.5 Output Compare Unit The 8-bit comparator continuously compares TCNT2 with the Output Compare Register (OCR2A and OCR2B). Whenever TCNT2 equals OCR2A or OCR2B, the comparator signals a match. A match will set the Output Compare Flag (OCF2A or OCF2B) at the next timer clock cycle. If the corresponding interrupt is enabled, the Output Compare Flag generates an Output Compare interrupt. The Output Compare Flag is automatically cleared when the interrupt is executed. Alternatively, the Output Compare Flag can be cleared by software by writing a logical one to its I/O bit location. The Waveform Generator uses the match signal to generate an output according to operating mode set by the WGM22:0 bits and Compare Output mode (COM2x1:0) bits. The max and bottom signals are used by the Waveform Generator for handling the special cases of the extreme values in some modes of operation ("Modes of Operation" on page 149). Figure 18-3 shows a block diagram of the Output Compare unit. Figure 18-3. Output Compare Unit, Block Diagram DATA BUS OCRnx TCNTn = (8-bit Comparator ) OCFnx (Int.Req.) top bottom Waveform Generator OCnx FOCn WGMn1:0 COMnX1:0 The OCR2x Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR2x Compare Register to either top or bottom of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free. The OCR2x Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCR2x Buffer Register, and if double buffering is disabled the CPU will access the OCR2x directly. 146 Atmel ATmega48PA/88PA/168PA [Preliminary] 9223B-AVR-09/11 Atmel ATmega48PA/88PA/168PA [Preliminary] 18.5.1 Force Output Compare In non-PWM waveform generation modes, the match output of the comparator can be forced by writing a one to the Force Output Compare (FOC2x) bit. Forcing compare match will not set the OCF2x Flag or reload/clear the timer, but the OC2x pin will be updated as if a real compare match had occurred (the COM2x1:0 bits settings define whether the OC2x pin is set, cleared or toggled). 18.5.2 Compare Match Blocking by TCNT2 Write All CPU write operations to the TCNT2 Register will block any compare match that occurs in the next timer clock cycle, even when the timer is stopped. This feature allows OCR2x to be initialized to the same value as TCNT2 without triggering an interrupt when the Timer/Counter clock is enabled. 18.5.3 Using the Output Compare Unit Since writing TCNT2 in any mode of operation will block all compare matches for one timer clock cycle, there are risks involved when changing TCNT2 when using the Output Compare channel, independently of whether the Timer/Counter is running or not. If the value written to TCNT2 equals the OCR2x value, the compare match will be missed, resulting in incorrect waveform generation. Similarly, do not write the TCNT2 value equal to BOTTOM when the counter is downcounting. The setup of the OC2x should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC2x value is to use the Force Output Compare (FOC2x) strobe bit in Normal mode. The OC2x Register keeps its value even when changing between Waveform Generation modes. Be aware that the COM2x1:0 bits are not double buffered together with the compare value. Changing the COM2x1:0 bits will take effect immediately. 18.6 Compare Match Output Unit The Compare Output mode (COM2x1:0) bits have two functions. The Waveform Generator uses the COM2x1:0 bits for defining the Output Compare (OC2x) state at the next compare match. Also, the COM2x1:0 bits control the OC2x pin output source. Figure 18-4 shows a simplified schematic of the logic affected by the COM2x1:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O Port Control Registers (DDR and PORT) that are affected by the COM2x1:0 bits are shown. When referring to the OC2x state, the reference is for the internal OC2x Register, not the OC2x pin. 147 9223B-AVR-09/11 Figure 18-4. Compare Match Output Unit, Schematic COMnx1 COMnx0 FOCnx Waveform Generator D Q 1 OCnx DATA BUS D 0 OCnx Pin Q PORT D Q DDR clk I/O The general I/O port function is overridden by the Output Compare (OC2x) from the Waveform Generator if either of the COM2x1:0 bits are set. However, the OC2x pin direction (input or output) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction Register bit for the OC2x pin (DDR_OC2x) must be set as output before the OC2x value is visible on the pin. The port override function is independent of the Waveform Generation mode. The design of the Output Compare pin logic allows initialization of the OC2x state before the output is enabled. Note that some COM2x1:0 bit settings are reserved for certain modes of operation. See "Register Description" on page 158. 18.6.1 Compare Output Mode and Waveform Generation The Waveform Generator uses the COM2x1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COM2x1:0 = 0 tells the Waveform Generator that no action on the OC2x Register is to be performed on the next compare match. For compare output actions in the non-PWM modes refer to Table 18-5 on page 159. For fast PWM mode, refer to Table 18-6 on page 159, and for phase correct PWM refer to Table 18-7 on page 160. A change of the COM2x1:0 bits state will have effect at the first compare match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOC2x strobe bits. 148 Atmel ATmega48PA/88PA/168PA [Preliminary] 9223B-AVR-09/11 Atmel ATmega48PA/88PA/168PA [Preliminary] 18.7 Modes of Operation The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined by the combination of the Waveform Generation mode (WGM22:0) and Compare Output mode (COM2x1:0) bits. The Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do. The COM2x1:0 bits control whether the PWM output generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes the COM2x1:0 bits control whether the output should be set, cleared, or toggled at a compare match (See "Compare Match Output Unit" on page 147.). For detailed timing information refer to "Timer/Counter Timing Diagrams" on page 154. 18.7.1 Normal Mode The simplest mode of operation is the Normal mode (WGM22:0 = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bottom (0x00). In normal operation the Timer/Counter Overflow Flag (TOV2) will be set in the same timer clock cycle as the TCNT2 becomes zero. The TOV2 Flag in this case behaves like a ninth bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt that automatically clears the TOV2 Flag, the timer resolution can be increased by software. There are no special cases to consider in the Normal mode, a new counter value can be written anytime. The Output Compare unit can be used to generate interrupts at some given time. Using the Output Compare to generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time. 18.7.2 Clear Timer on Compare Match (CTC) Mode In Clear Timer on Compare or CTC mode (WGM22:0 = 2), the OCR2A Register is used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter value (TCNT2) matches the OCR2A. The OCR2A defines the top value for the counter, hence also its resolution. This mode allows greater control of the compare match output frequency. It also simplifies the operation of counting external events. The timing diagram for the CTC mode is shown in Figure 18-5. The counter value (TCNT2) increases until a compare match occurs between TCNT2 and OCR2A, and then counter (TCNT2) is cleared. Figure 18-5. CTC Mode, Timing Diagram OCnx Interrupt Flag Set TCNTn OCnx (Toggle) Period (COMnx1:0 = 1) 1 2 3 4 149 9223B-AVR-09/11 An interrupt can be generated each time the counter value reaches the TOP value by using the OCF2A Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing TOP to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature. If the new value written to OCR2A is lower than the current value of TCNT2, the counter will miss the compare match. The counter will then have to count to its maximum value (0xFF) and wrap around starting at 0x00 before the compare match can occur. For generating a waveform output in CTC mode, the OC2A output can be set to toggle its logical level on each compare match by setting the Compare Output mode bits to toggle mode (COM2A1:0 = 1). The OC2A value will not be visible on the port pin unless the data direction for the pin is set to output. The waveform generated will have a maximum frequency of fOC2A = fclk_I/O/2 when OCR2A is set to zero (0x00). The waveform frequency is defined by the following equation: f clk_I/O f OCnx = ------------------------------------------------------2 x N x ( 1 + OCRnx ) The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). As for the Normal mode of operation, the TOV2 Flag is set in the same timer clock cycle that the counter counts from MAX to 0x00. 18.7.3 Fast PWM Mode The fast Pulse Width Modulation or fast PWM mode (WGM22:0 = 3 or 7) provides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM option by its single-slope operation. The counter counts from BOTTOM to TOP then restarts from BOTTOM. TOP is defined as 0xFF when WGM2:0 = 3, and OCR2A when MGM2:0 = 7. In non-inverting Compare Output mode, the Output Compare (OC2x) is cleared on the compare match between TCNT2 and OCR2x, and set at BOTTOM. In inverting Compare Output mode, the output is set on compare match and cleared at BOTTOM. Due to the single-slope operation, the operating frequency of the fast PWM mode can be twice as high as the phase correct PWM mode that uses dual-slope operation. This high frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC applications. High frequency allows physically small sized external components (coils, capacitors), and therefore reduces total system cost. In fast PWM mode, the counter is incremented until the counter value matches the TOP value. The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in Figure 18-6. The TCNT2 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes represent compare matches between OCR2x and TCNT2. 150 Atmel ATmega48PA/88PA/168PA [Preliminary] 9223B-AVR-09/11 Atmel ATmega48PA/88PA/168PA [Preliminary] Figure 18-6. Fast PWM Mode, Timing Diagram OCRnx Interrupt Flag Set OCRnx Update and TOVn Interrupt Flag Set TCNTn OCnx (COMnx1:0 = 2) OCnx (COMnx1:0 = 3) Period 1 2 3 4 5 6 7 The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches TOP. If the interrupt is enabled, the interrupt handler routine can be used for updating the compare value. In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC2x pin. Setting the COM2x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM2x1:0 to three. TOP is defined as 0xFF when WGM2:0 = 3, and OCR2A when MGM2:0 = 7. (See Table 18-3 on page 158). The actual OC2x value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is generated by setting (or clearing) the OC2x Register at the compare match between OCR2x and TCNT2, and clearing (or setting) the OC2x Register at the timer clock cycle the counter is cleared (changes from TOP to BOTTOM). The PWM frequency for the output can be calculated by the following equation: f clk_I/O f OCnxPWM = -------------------N x 256 The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). The extreme values for the OCR2A Register represent special cases when generating a PWM waveform output in the fast PWM mode. If the OCR2A is set equal to BOTTOM, the output will be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR2A equal to MAX will result in a constantly high or low output (depending on the polarity of the output set by the COM2A1:0 bits.) A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OC2x to toggle its logical level on each compare match (COM2x1:0 = 1). The waveform generated will have a maximum frequency of foc2 = fclk_I/O/2 when OCR2A is set to zero. This feature is similar to the OC2A toggle in CTC mode, except the double buffer feature of the Output Compare unit is enabled in the fast PWM mode. 151 9223B-AVR-09/11 18.7.4 Phase Correct PWM Mode The phase correct PWM mode (WGM22:0 = 1 or 5) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly from BOTTOM to TOP and then from TOP to BOTTOM. TOP is defined as 0xFF when WGM2:0 = 3, and OCR2A when MGM2:0 = 7. In non-inverting Compare Output mode, the Output Compare (OC2x) is cleared on the compare match between TCNT2 and OCR2x while upcounting, and set on the compare match while downcounting. In inverting Output Compare mode, the operation is inverted. The dual-slope operation has lower maximum operation frequency than single slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. In phase correct PWM mode the counter is incremented until the counter value matches TOP. When the counter reaches TOP, it changes the count direction. The TCNT2 value will be equal to TOP for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown on Figure 18-7. The TCNT2 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes represent compare matches between OCR2x and TCNT2. Figure 18-7. Phase Correct PWM Mode, Timing Diagram OCnx Interrupt Flag Set OCRnx Update TOVn Interrupt Flag Set TCNTn OCnx (COMnx1:0 = 2) OCnx (COMnx1:0 = 3) Period 1 2 3 The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches BOTTOM. The Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM value. 152 Atmel ATmega48PA/88PA/168PA [Preliminary] 9223B-AVR-09/11 Atmel ATmega48PA/88PA/168PA [Preliminary] In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC2x pin. Setting the COM2x1:0 bits to two will produce a non-inverted PWM. An inverted PWM output can be generated by setting the COM2x1:0 to three. TOP is defined as 0xFF when WGM2:0 = 3, and OCR2A when MGM2:0 = 7 (See Table 18-4 on page 159). The actual OC2x value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is generated by clearing (or setting) the OC2x Register at the compare match between OCR2x and TCNT2 when the counter increments, and setting (or clearing) the OC2x Register at compare match between OCR2x and TCNT2 when the counter decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the following equation: f clk_I/O f OCnxPCPWM = -------------------N x 510 The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). The extreme values for the OCR2A Register represent special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCR2A is set equal to BOTTOM, the output will be continuously low and if set equal to MAX the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. At the very start of period 2 in Figure 18-7 OCnx has a transition from high to low even though there is no Compare Match. The point of this transition is to guarantee symmetry around BOTTOM. There are two cases that give a transition without Compare Match. * OCR2A changes its value from MAX, like in Figure 18-7. When the OCR2A value is MAX the OCn pin value is the same as the result of a down-counting compare match. To ensure symmetry around BOTTOM the OCn value at MAX must correspond to the result of an up-counting Compare Match. * The timer starts counting from a value higher than the one in OCR2A, and for that reason misses the Compare Match and hence the OCn change that would have happened on the way up. 153 9223B-AVR-09/11 18.8 Timer/Counter Timing Diagrams The following figures show the Timer/Counter in synchronous mode, and the timer clock (clkT2) is therefore shown as a clock enable signal. In asynchronous mode, clkI/O should be replaced by the Timer/Counter Oscillator clock. The figures include information on when Interrupt Flags are set. Figure 18-8 contains timing data for basic Timer/Counter operation. The figure shows the count sequence close to the MAX value in all modes other than phase correct PWM mode. Figure 18-8. Timer/Counter Timing Diagram, no Prescaling clkI/O clkTn (clkI/O /1) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn Figure 18-9 shows the same timing data, but with the prescaler enabled. Figure 18-9. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn Figure 18-10 shows the setting of OCF2A in all modes except CTC mode. Figure 18-10. Timer/Counter Timing Diagram, Setting of OCF2A, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn OCRnx OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2 OCRnx Value OCFnx 154 Atmel ATmega48PA/88PA/168PA [Preliminary] 9223B-AVR-09/11 Atmel ATmega48PA/88PA/168PA [Preliminary] Figure 18-11 shows the setting of OCF2A and the clearing of TCNT2 in CTC mode. Figure 18-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn (CTC) TOP - 1 OCRnx TOP BOTTOM BOTTOM + 1 TOP OCFnx 18.9 Asynchronous Operation of Timer/Counter2 When Timer/Counter2 operates asynchronously, some considerations must be taken. * Warning: When switching between asynchronous and synchronous clocking of Timer/Counter2, the Timer Registers TCNT2, OCR2x, and TCCR2x might be corrupted. A safe procedure for switching clock source is: a. Disable the Timer/Counter2 interrupts by clearing OCIE2x and TOIE2. b. Select clock source by setting AS2 as appropriate. c. Write new values to TCNT2, OCR2x, and TCCR2x. d. To switch to asynchronous operation: Wait for TCN2xUB, OCR2xUB, and TCR2xUB. e. Clear the Timer/Counter2 Interrupt Flags. f. Enable interrupts, if needed. * The CPU main clock frequency must be more than four times the Oscillator frequency. * When writing to one of the registers TCNT2, OCR2x, or TCCR2x, the value is transferred to a temporary register, and latched after two positive edges on TOSC1. The user should not write a new value before the contents of the temporary register have been transferred to its destination. Each of the five mentioned registers have their individual temporary register, which means that e.g. writing to TCNT2 does not disturb an OCR2x write in progress. To detect that a transfer to the destination register has taken place, the Asynchronous Status Register - ASSR has been implemented. * When entering Power-save or ADC Noise Reduction mode after having written to TCNT2, OCR2x, or TCCR2x, the user must wait until the written register has been updated if Timer/Counter2 is used to wake up the device. Otherwise, the MCU will enter sleep mode before the changes are effective. This is particularly important if any of the Output Compare2 interrupt is used to wake up the device, since the Output Compare function is disabled during writing to OCR2x or TCNT2. If the write cycle is not finished, and the MCU enters sleep mode before the corresponding OCR2xUB bit returns to zero, the device will never receive a compare match interrupt, and the MCU will not wake up. 155 9223B-AVR-09/11 * If Timer/Counter2 is used to wake the device up from Power-save or ADC Noise Reduction mode, precautions must be taken if the user wants to re-enter one of these modes: If re-entering sleep mode within the TOSC1 cycle, the interrupt will immediately occur and the device wake up again. The result is multiple interrupts and wake-ups within one TOSC1 cycle from the first interrupt. If the user is in doubt whether the time before re-entering Power-save or ADC Noise Reduction mode is sufficient, the following algorithm can be used to ensure that one TOSC1 cycle has elapsed: a. Write a value to TCCR2x, TCNT2, or OCR2x. b. Wait until the corresponding Update Busy Flag in ASSR returns to zero. c. Enter Power-save or ADC Noise Reduction mode. * When the asynchronous operation is selected, the 32.768kHz Oscillator for Timer/Counter2 is always running, except in Power-down and Standby modes. After a Power-up Reset or wake-up from Power-down or Standby mode, the user should be aware of the fact that this Oscillator might take as long as one second to stabilize. The user is advised to wait for at least one second before using Timer/Counter2 after power-up or wake-up from Power-down or Standby mode. The contents of all Timer/Counter2 Registers must be considered lost after a wake-up from Power-down or Standby mode due to unstable clock signal upon start-up, no matter whether the Oscillator is in use or a clock signal is applied to the TOSC1 pin. * Description of wake up from Power-save or ADC Noise Reduction mode when the timer is clocked asynchronously: When the interrupt condition is met, the wake up process is started on the following cycle of the timer clock, that is, the timer is always advanced by at least one before the processor can read the counter value. After wake-up, the MCU is halted for four cycles, it executes the interrupt routine, and resumes execution from the instruction following SLEEP. * Reading of the TCNT2 Register shortly after wake-up from Power-save may give an incorrect result. Since TCNT2 is clocked on the asynchronous TOSC clock, reading TCNT2 must be done through a register synchronized to the internal I/O clock domain. Synchronization takes place for every rising TOSC1 edge. When waking up from Power-save mode, and the I/O clock (clkI/O) again becomes active, TCNT2 will read as the previous value (before entering sleep) until the next rising TOSC1 edge. The phase of the TOSC clock after waking up from Power-save mode is essentially unpredictable, as it depends on the wake-up time. The recommended procedure for reading TCNT2 is thus as follows: a. Write any value to either of the registers OCR2x or TCCR2x. b. Wait for the corresponding Update Busy Flag to be cleared. c. Read TCNT2. During asynchronous operation, the synchronization of the Interrupt Flags for the asynchronous timer takes 3 processor cycles plus one timer cycle. The timer is therefore advanced by at least one before the processor can read the timer value causing the setting of the Interrupt Flag. The Output Compare pin is changed on the timer clock and is not synchronized to the processor clock. 156 Atmel ATmega48PA/88PA/168PA [Preliminary] 9223B-AVR-09/11 Atmel ATmega48PA/88PA/168PA [Preliminary] 18.10 Timer/Counter Prescaler Figure 18-12. Prescaler for Timer/Counter2 PSRASY clkT2S/1024 clkT2S/256 clkT2S/128 AS2 clkT2S/64 10-BIT T/C PRESCALER Clear clkT2S/32 TOSC1 clkT2S clkT2S/8 clkI/O 0 CS20 CS21 CS22 TIMER/COUNTER2 CLOCK SOURCE clkT2 The clock source for Timer/Counter2 is named clkT2S. clkT2S is by default connected to the main system I/O clock clkIO. By setting the AS2 bit in ASSR, Timer/Counter2 is asynchronously clocked from the TOSC1 pin. This enables use of Timer/Counter2 as a Real Time Counter (RTC). When AS2 is set, pins TOSC1 and TOSC2 are disconnected from Port B. A crystal can then be connected between the TOSC1 and TOSC2 pins to serve as an independent clock source for Timer/Counter2. The Oscillator is optimized for use with a 32.768kHz crystal. For Timer/Counter2, the possible prescaled selections are: clk T2S/8, clkT2S/32, clk T2S/64, clk T2S /128, clk T2S /256, and clk T2S /1024. Additionally, clk T2S as well as 0 (stop) may be selected. Setting the PSRASY bit in GTCCR resets the prescaler. This allows the user to operate with a predictable prescaler. 157 9223B-AVR-09/11 18.11 Register Description 18.11.1 TCCR2A - Timer/Counter Control Register A Bit 7 6 5 4 3 2 1 0 COM2A1 COM2A0 COM2B1 COM2B0 - - WGM21 WGM20 Read/Write R/W R/W R/W R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0xB0) TCCR2A * Bits 7:6 - COM2A1:0: Compare Match Output A Mode These bits control the Output Compare pin (OC2A) behavior. If one or both of the COM2A1:0 bits are set, the OC2A output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to the OC2A pin must be set in order to enable the output driver. When OC2A is connected to the pin, the function of the COM2A1:0 bits depends on the WGM22:0 bit setting. Table 18-2 shows the COM2A1:0 bit functionality when the WGM22:0 bits are set to a normal or CTC mode (non-PWM). Table 18-2. Compare Output Mode, non-PWM Mode COM2A1 COM2A0 Description 0 0 Normal port operation, OC0A disconnected. 0 1 Toggle OC2A on Compare Match 1 0 Clear OC2A on Compare Match 1 1 Set OC2A on Compare Match Table 18-3 shows the COM2A1:0 bit functionality when the WGM21:0 bits are set to fast PWM mode. Table 18-3. COM2A1 COM2A0 0 0 Normal port operation, OC2A disconnected. 0 1 WGM22 = 0: Normal Port Operation, OC0A Disconnected. WGM22 = 1: Toggle OC2A on Compare Match. 1 0 Clear OC2A on Compare Match, set OC2A at BOTTOM, (non-inverting mode). 1 1 Set OC2A on Compare Match, clear OC2A at BOTTOM, (inverting mode). Note: 158 Compare Output Mode, Fast PWM Mode(1) Description 1. A special case occurs when OCR2A equals TOP and COM2A1 is set. In this case, the Compare Match is ignored, but the set or clear is done at BOTTOM. See "Fast PWM Mode" on page 150 for more details. Atmel ATmega48PA/88PA/168PA [Preliminary] 9223B-AVR-09/11 Atmel ATmega48PA/88PA/168PA [Preliminary] Table 18-4 shows the COM2A1:0 bit functionality when the WGM22:0 bits are set to phase correct PWM mode. Table 18-4. Compare Output Mode, Phase Correct PWM Mode(1) COM2A1 COM2A0 0 0 Normal port operation, OC2A disconnected. 0 1 WGM22 = 0: Normal Port Operation, OC2A Disconnected. WGM22 = 1: Toggle OC2A on Compare Match. 1 0 Clear OC2A on Compare Match when up-counting. Set OC2A on Compare Match when down-counting. 1 1 Set OC2A on Compare Match when up-counting. Clear OC2A on Compare Match when down-counting. Note: Description 1. A special case occurs when OCR2A equals TOP and COM2A1 is set. In this case, the Compare Match is ignored, but the set or clear is done at TOP. See "Phase Correct PWM Mode" on page 152 for more details. * Bits 5:4 - COM2B1:0: Compare Match Output B Mode These bits control the Output Compare pin (OC2B) behavior. If one or both of the COM2B1:0 bits are set, the OC2B output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to the OC2B pin must be set in order to enable the output driver. When OC2B is connected to the pin, the function of the COM2B1:0 bits depends on the WGM22:0 bit setting. Table 18-5 shows the COM2B1:0 bit functionality when the WGM22:0 bits are set to a normal or CTC mode (non-PWM). Table 18-5. Compare Output Mode, non-PWM Mode COM2B1 COM2B0 Description 0 0 Normal port operation, OC2B disconnected. 0 1 Toggle OC2B on Compare Match 1 0 Clear OC2B on Compare Match 1 1 Set OC2B on Compare Match Table 18-6 shows the COM2B1:0 bit functionality when the WGM22:0 bits are set to fast PWM mode. Table 18-6. Compare Output Mode, Fast PWM Mode(1) COM2B1 COM2B0 0 0 Normal port operation, OC2B disconnected. 0 1 Reserved 1 0 Clear OC2B on Compare Match, set OC2B at BOTTOM, (non-inverting mode). 1 1 Set OC2B on Compare Match, clear OC2B at BOTTOM, (inverting mode). Note: Description 1. A special case occurs when OCR2B equals TOP and COM2B1 is set. In this case, the Compare Match is ignored, but the set or clear is done at BOTTOM. See "Phase Correct PWM Mode" on page 152 for more details. 159 9223B-AVR-09/11 Table 18-7 shows the COM2B1:0 bit functionality when the WGM22:0 bits are set to phase correct PWM mode. Compare Output Mode, Phase Correct PWM Mode(1) Table 18-7. COM2B1 COM2B0 0 0 Normal port operation, OC2B disconnected. 0 1 Reserved 1 0 Clear OC2B on Compare Match when up-counting. Set OC2B on Compare Match when down-counting. 1 1 Set OC2B on Compare Match when up-counting. Clear OC2B on Compare Match when down-counting. Note: Description 1. A special case occurs when OCR2B equals TOP and COM2B1 is set. In this case, the Compare Match is ignored, but the set or clear is done at TOP. See "Phase Correct PWM Mode" on page 152 for more details. * Bits 3, 2 - Reserved These bits are reserved bits in the Atmel(R) ATmega48PA/88PA/168PA and will always read as zero. * Bits 1:0 - WGM21:0: Waveform Generation Mode Combined with the WGM22 bit found in the TCCR2B Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used, see Table 18-8. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare Match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes (see "Modes of Operation" on page 149). Table 18-8. Waveform Generation Mode Bit Description Timer/Counter Mode of Operation TOP Update of OCRx at TOV Flag Set on(1)(2) 0 Normal 0xFF Immediate MAX 0 1 PWM, Phase Correct 0xFF TOP BOTTOM 0 1 0 CTC OCRA Immediate MAX 3 0 1 1 Fast PWM 0xFF BOTTOM MAX 4 1 0 0 Reserved - - - 5 1 0 1 PWM, Phase Correct OCRA TOP BOTTOM 6 1 1 0 Reserved - - - 7 1 1 1 Fast PWM OCRA BOTTOM TOP Mode WGM2 WGM1 WGM0 0 0 0 1 0 2 Notes: 1. MAX = 0xFF 2. BOTTOM = 0x00 160 Atmel ATmega48PA/88PA/168PA [Preliminary] 9223B-AVR-09/11 Atmel ATmega48PA/88PA/168PA [Preliminary] 18.11.2 TCCR2B - Timer/Counter Control Register B Bit 7 6 5 4 3 2 1 0 FOC2A FOC2B - - WGM22 CS22 CS21 CS20 Read/Write W W R R R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0xB1) TCCR2B * Bit 7 - FOC2A: Force Output Compare A The FOC2A bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR2B is written when operating in PWM mode. When writing a logical one to the FOC2A bit, an immediate Compare Match is forced on the Waveform Generation unit. The OC2A output is changed according to its COM2A1:0 bits setting. Note that the FOC2A bit is implemented as a strobe. Therefore it is the value present in the COM2A1:0 bits that determines the effect of the forced compare. A FOC2A strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR2A as TOP. The FOC2A bit is always read as zero. * Bit 6 - FOC2B: Force Output Compare B The FOC2B bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR2B is written when operating in PWM mode. When writing a logical one to the FOC2B bit, an immediate Compare Match is forced on the Waveform Generation unit. The OC2B output is changed according to its COM2B1:0 bits setting. Note that the FOC2B bit is implemented as a strobe. Therefore it is the value present in the COM2B1:0 bits that determines the effect of the forced compare. A FOC2B strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR2B as TOP. The FOC2B bit is always read as zero. * Bits 5:4 - Reserved These bits are reserved bits in the Atmel(R) ATmega48PA/88PA/168PA and will always read as zero. * Bit 3 - WGM22: Waveform Generation Mode See the description in the "TCCR2A - Timer/Counter Control Register A" on page 158. * Bit 2:0 - CS22:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter, see Table 18-9 on page 162. 161 9223B-AVR-09/11 Table 18-9. Clock Select Bit Description CS22 CS21 CS20 0 0 0 Description No clock source (Timer/Counter stopped). 0 0 1 clkT2S/(No prescaling) 0 1 0 clkT2S/8 (From prescaler) 0 1 1 clkT2S/32 (From prescaler) 1 0 0 clkT2S/64 (From prescaler) 1 0 1 clkT2S/128 (From prescaler) 1 1 0 clkT2S/256 (From prescaler) 1 1 1 clkT2S/1024 (From prescaler) If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the counter even if the pin is configured as an output. This feature allows software control of the counting. 18.11.3 TCNT2 - Timer/Counter Register Bit 7 6 5 (0xB2) 4 3 2 1 0 TCNT2[7:0] TCNT2 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter. Writing to the TCNT2 Register blocks (removes) the Compare Match on the following timer clock. Modifying the counter (TCNT2) while the counter is running, introduces a risk of missing a Compare Match between TCNT2 and the OCR2x Registers. 18.11.4 OCR2A - Output Compare Register A Bit 7 6 5 (0xB3) 4 3 2 1 0 OCR2A[7:0] OCR2A Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The Output Compare Register A contains an 8-bit value that is continuously compared with the counter value (TCNT2). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC2A pin. 18.11.5 OCR2B - Output Compare Register B Bit 7 6 5 (0xB4) 4 3 2 1 0 OCR2B[7:0] OCR2B Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The Output Compare Register B contains an 8-bit value that is continuously compared with the counter value (TCNT2). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC2B pin. 162 Atmel ATmega48PA/88PA/168PA [Preliminary] 9223B-AVR-09/11 Atmel ATmega48PA/88PA/168PA [Preliminary] 18.11.6 TIMSK2 - Timer/Counter2 Interrupt Mask Register Bit 7 6 5 4 3 2 1 0 (0x70) - - - - - OCIE2B OCIE2A TOIE2 Read/Write R R R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TIMSK2 * Bit 2 - OCIE2B: Timer/Counter2 Output Compare Match B Interrupt Enable When the OCIE2B bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2 Compare Match B interrupt is enabled. The corresponding interrupt is executed if a compare match in Timer/Counter2 occurs, i.e., when the OCF2B bit is set in the Timer/Counter 2 Interrupt Flag Register - TIFR2. * Bit 1 - OCIE2A: Timer/Counter2 Output Compare Match A Interrupt Enable When the OCIE2A bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2 Compare Match A interrupt is enabled. The corresponding interrupt is executed if a compare match in Timer/Counter2 occurs, i.e., when the OCF2A bit is set in the Timer/Counter 2 Interrupt Flag Register - TIFR2. * Bit 0 - TOIE2: Timer/Counter2 Overflow Interrupt Enable When the TOIE2 bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter2 occurs, i.e., when the TOV2 bit is set in the Timer/Counter2 Interrupt Flag Register - TIFR2. 18.11.7 TIFR2 - Timer/Counter2 Interrupt Flag Register Bit 7 6 5 4 3 2 1 0 0x17 (0x37) - - - - - OCF2B OCF2A TOV2 Read/Write R R R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TIFR2 * Bit 2 - OCF2B: Output Compare Flag 2 B The OCF2B bit is set (one) when a compare match occurs between the Timer/Counter2 and the data in OCR2B - Output Compare Register2. OCF2B is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF2B is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE2B (Timer/Counter2 Compare match Interrupt Enable), and OCF2B are set (one), the Timer/Counter2 Compare match Interrupt is executed. * Bit 1 - OCF2A: Output Compare Flag 2 A The OCF2A bit is set (one) when a compare match occurs between the Timer/Counter2 and the data in OCR2A - Output Compare Register2. OCF2A is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF2A is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE2A (Timer/Counter2 Compare match Interrupt Enable), and OCF2A are set (one), the Timer/Counter2 Compare match Interrupt is executed. 163 9223B-AVR-09/11 * Bit 0 - TOV2: Timer/Counter2 Overflow Flag The TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV2 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE2A (Timer/Counter2 Overflow Interrupt Enable), and TOV2 are set (one), the Timer/Counter2 Overflow interrupt is executed. In PWM mode, this bit is set when Timer/Counter2 changes counting direction at 0x00. 18.11.8 ASSR - Asynchronous Status Register Bit 7 6 5 4 3 2 1 0 (0xB6) - EXCLK AS2 TCN2UB OCR2AUB OCR2BUB TCR2AUB TCR2BUB Read/Write R R/W R/W R R R R R Initial Value 0 0 0 0 0 0 0 0 ASSR * Bit 7 - Reserved This bit is reserved and will always read as zero. * Bit 6 - EXCLK: Enable External Clock Input When EXCLK is written to one, and asynchronous clock is selected, the external clock input buffer is enabled and an external clock can be input on Timer Oscillator 1 (TOSC1) pin instead of a 32kHz crystal. Writing to EXCLK should be done before asynchronous operation is selected. Note that the crystal Oscillator will only run when this bit is zero. * Bit 5 - AS2: Asynchronous Timer/Counter2 When AS2 is written to zero, Timer/Counter2 is clocked from the I/O clock, clkI/O. When AS2 is written to one, Timer/Counter2 is clocked from a crystal Oscillator connected to the Timer Oscillator 1 (TOSC1) pin. When the value of AS2 is changed, the contents of TCNT2, OCR2A, OCR2B, TCCR2A and TCCR2B might be corrupted. * Bit 4 - TCN2UB: Timer/Counter2 Update Busy When Timer/Counter2 operates asynchronously and TCNT2 is written, this bit becomes set. When TCNT2 has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that TCNT2 is ready to be updated with a new value. * Bit 3 - OCR2AUB: Output Compare Register2 Update Busy When Timer/Counter2 operates asynchronously and OCR2A is written, this bit becomes set. When OCR2A has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that OCR2A is ready to be updated with a new value. * Bit 2 - OCR2BUB: Output Compare Register2 Update Busy When Timer/Counter2 operates asynchronously and OCR2B is written, this bit becomes set. When OCR2B has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that OCR2B is ready to be updated with a new value. 164 Atmel ATmega48PA/88PA/168PA [Preliminary] 9223B-AVR-09/11 Atmel ATmega48PA/88PA/168PA [Preliminary] * Bit 1 - TCR2AUB: Timer/Counter Control Register2 Update Busy When Timer/Counter2 operates asynchronously and TCCR2A is written, this bit becomes set. When TCCR2A has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that TCCR2A is ready to be updated with a new value. * Bit 0 - TCR2BUB: Timer/Counter Control Register2 Update Busy When Timer/Counter2 operates asynchronously and TCCR2B is written, this bit becomes set. When TCCR2B has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that TCCR2B is ready to be updated with a new value. If a write is performed to any of the five Timer/Counter2 Registers while its update busy flag is set, the updated value might get corrupted and cause an unintentional interrupt to occur. The mechanisms for reading TCNT2, OCR2A, OCR2B, TCCR2A and TCCR2B are different. When reading TCNT2, the actual timer value is read. When reading OCR2A, OCR2B, TCCR2A and TCCR2B the value in the temporary storage register is read. 18.11.9 GTCCR - General Timer/Counter Control Register Bit 7 6 5 4 3 2 1 0 0x23 (0x43) TSM - - - - - PSRASY PSRSYNC Read/Write R/W R R R R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 GTCCR * Bit 1 - PSRASY: Prescaler Reset Timer/Counter2 When this bit is one, the Timer/Counter2 prescaler will be reset. This bit is normally cleared immediately by hardware. If the bit is written when Timer/Counter2 is operating in asynchronous mode, the bit will remain one until the prescaler has been reset. The bit will not be cleared by hardware if the TSM bit is set. Refer to the description of the "Bit 7 - TSM: Timer/Counter Synchronization Mode" on page 142 for a description of the Timer/Counter Synchronization mode. 165 9223B-AVR-09/11 19. SPI - Serial Peripheral Interface 19.1 Features * * * * * * * * 19.2 Full-duplex, Three-wire Synchronous Data Transfer Master or Slave Operation LSB First or MSB First Data Transfer Seven Programmable Bit Rates End of Transmission Interrupt Flag Write Collision Flag Protection Wake-up from Idle Mode Double Speed (CK/2) Master SPI Mode Overview The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the Atmel(R) ATmega48PA/88PA/168PA and peripheral devices or between several AVR devices. The USART can also be used in Master SPI mode, see "USART in SPI Mode" on page 202. The PRSPI bit in "Minimizing Power Consumption" on page 42 must be written to zero to enable SPI module. Figure 19-1. SPI Block Diagram(1) SPI2X SPI2X DIVIDER /2/4/8/16/32/64/128 Note: 166 1. Refer to Figure 1-1 on page 2, and Table 14-3 on page 81 for SPI pin placement. Atmel ATmega48PA/88PA/168PA [Preliminary] 9223B-AVR-09/11 Atmel ATmega48PA/88PA/168PA [Preliminary] The interconnection between Master and Slave CPUs with SPI is shown in Figure 19-2 on page 167. The system consists of two shift Registers, and a Master clock generator. The SPI Master initiates the communication cycle when pulling low the Slave Select SS pin of the desired Slave. Master and Slave prepare the data to be sent in their respective shift Registers, and the Master generates the required clock pulses on the SCK line to interchange data. Data is always shifted from Master to Slave on the Master Out - Slave In, MOSI, line, and from Slave to Master on the Master In - Slave Out, MISO, line. After each data packet, the Master will synchronize the Slave by pulling high the Slave Select, SS, line. When configured as a Master, the SPI interface has no automatic control of the SS line. This must be handled by user software before communication can start. When this is done, writing a byte to the SPI Data Register starts the SPI clock generator, and the hardware shifts the eight bits into the Slave. After shifting one byte, the SPI clock generator stops, setting the end of Transmission Flag (SPIF). If the SPI Interrupt Enable bit (SPIE) in the SPCR Register is set, an interrupt is requested. The Master may continue to shift the next byte by writing it into SPDR, or signal the end of packet by pulling high the Slave Select, SS line. The last incoming byte will be kept in the Buffer Register for later use. When configured as a Slave, the SPI interface will remain sleeping with MISO tri-stated as long as the SS pin is driven high. In this state, software may update the contents of the SPI Data Register, SPDR, but the data will not be shifted out by incoming clock pulses on the SCK pin until the SS pin is driven low. As one byte has been completely shifted, the end of Transmission Flag, SPIF is set. If the SPI Interrupt Enable bit, SPIE, in the SPCR Register is set, an interrupt is requested. The Slave may continue to place new data to be sent into SPDR before reading the incoming data. The last incoming byte will be kept in the Buffer Register for later use. Figure 19-2. SPI Master-slave Interconnection SHIFT ENABLE The system is single buffered in the transmit direction and double buffered in the receive direction. This means that bytes to be transmitted cannot be written to the SPI Data Register before the entire shift cycle is completed. When receiving data, however, a received character must be read from the SPI Data Register before the next character has been completely shifted in. Otherwise, the first byte is lost. 167 9223B-AVR-09/11 In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To ensure correct sampling of the clock signal, the minimum low and high periods should be: Low periods: Longer than 2 CPU clock cycles. High periods: Longer than 2 CPU clock cycles. When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to Table 19-1 on page 168. For more details on automatic port overrides, refer to "Alternate Port Functions" on page 79. Table 19-1. Pin SPI Pin Overrides(1) Direction, Master SPI Direction, Slave SPI MOSI User Defined Input MISO Input User Defined SCK User Defined Input SS User Defined Input Note: 1. See "Alternate Functions of Port B" on page 81 for a detailed description of how to define the direction of the user defined SPI pins. The following code examples show how to initialize the SPI as a Master and how to perform a simple transmission. DDR_SPI in the examples must be replaced by the actual Data Direction Register controlling the SPI pins. DD_MOSI, DD_MISO and DD_SCK must be replaced by the actual data direction bits for these pins. E.g. if MOSI is placed on pin PB5, replace DD_MOSI with DDB5 and DDR_SPI with DDRB. 168 Atmel ATmega48PA/88PA/168PA [Preliminary] 9223B-AVR-09/11 Atmel ATmega48PA/88PA/168PA [Preliminary] Assembly Code Example(1) SPI_MasterInit: ; Set MOSI and SCK output, all others input ldi r17,(1<>8); UBRR0L = (unsigned char)ubrr; Enable receiver and transmitter */ UCSR0B = (1<> 1) & 0x01; return ((resh << 8) | resl); } Note: 1. See Section 6. "About Code Examples" on page 7 For I/O Registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI" instructions must be replaced with instructions that allow access to extended I/O. Typically "LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and "CBR". The receive function example reads all the I/O Registers into the Register File before any computation is done. This gives an optimal receive buffer utilization since the buffer location read will be free to accept new data as early as possible. 187 9223B-AVR-09/11 20.7.3 Receive Compete Flag and Interrupt The USART Receiver has one flag that indicates the Receiver state. The Receive Complete (RXCn) Flag indicates if there are unread data present in the receive buffer. This flag is one when unread data exist in the receive buffer, and zero when the receive buffer is empty (i.e., does not contain any unread data). If the Receiver is disabled (RXENn = 0), the receive buffer will be flushed and consequently the RXCn bit will become zero. When the Receive Complete Interrupt Enable (RXCIEn) in UCSRnB is set, the USART Receive Complete interrupt will be executed as long as the RXCn Flag is set (provided that global interrupts are enabled). When interrupt-driven data reception is used, the receive complete routine must read the received data from UDRn in order to clear the RXCn Flag, otherwise a new interrupt will occur once the interrupt routine terminates. 20.7.4 Receiver Error Flags The USART Receiver has three Error Flags: Frame Error (FEn), Data OverRun (DORn) and Parity Error (UPEn). All can be accessed by reading UCSRnA. Common for the Error Flags is that they are located in the receive buffer together with the frame for which they indicate the error status. Due to the buffering of the Error Flags, the UCSRnA must be read before the receive buffer (UDRn), since reading the UDRn I/O location changes the buffer read location. Another equality for the Error Flags is that they can not be altered by software doing a write to the flag location. However, all flags must be set to zero when the UCSRnA is written for upward compatibility of future USART implementations. None of the Error Flags can generate interrupts. The Frame Error (FEn) Flag indicates the state of the first stop bit of the next readable frame stored in the receive buffer. The FEn Flag is zero when the stop bit was correctly read (as one), and the FEn Flag will be one when the stop bit was incorrect (zero). This flag can be used for detecting out-of-sync conditions, detecting break conditions and protocol handling. The FEn Flag is not affected by the setting of the USBSn bit in UCSRnC since the Receiver ignores all, except for the first, stop bits. For compatibility with future devices, always set this bit to zero when writing to UCSRnA. The Data OverRun (DORn) Flag indicates data loss due to a receiver buffer full condition. A Data OverRun occurs when the receive buffer is full (two characters), it is a new character waiting in the Receive Shift Register, and a new start bit is detected. If the DORn Flag is set there was one or more serial frame lost between the frame last read from UDRn, and the next frame read from UDRn. For compatibility with future devices, always write this bit to zero when writing to UCSRnA. The DORn Flag is cleared when the frame received was successfully moved from the Shift Register to the receive buffer. The Parity Error (UPEn) Flag indicates that the next frame in the receive buffer had a Parity Error when received. If Parity Check is not enabled the UPEn bit will always be read zero. For compatibility with future devices, always set this bit to zero when writing to UCSRnA. For more details see "Parity Bit Calculation" on page 181 and "Parity Checker" on page 189. 188 Atmel ATmega48PA/88PA/168PA [Preliminary] 9223B-AVR-09/11 Atmel ATmega48PA/88PA/168PA [Preliminary] 20.7.5 Parity Checker The Parity Checker is active when the high USART Parity mode (UPMn1) bit is set. Type of Parity Check to be performed (odd or even) is selected by the UPMn0 bit. When enabled, the Parity Checker calculates the parity of the data bits in incoming frames and compares the result with the parity bit from the serial frame. The result of the check is stored in the receive buffer together with the received data and stop bits. The Parity Error (UPEn) Flag can then be read by software to check if the frame had a Parity Error. The UPEn bit is set if the next character that can be read from the receive buffer had a Parity Error when received and the Parity Checking was enabled at that point (UPMn1 = 1). This bit is valid until the receive buffer (UDRn) is read. 20.7.6 Disabling the Receiver In contrast to the Transmitter, disabling of the Receiver will be immediate. Data from ongoing receptions will therefore be lost. When disabled (i.e., the RXENn is set to zero) the Receiver will no longer override the normal function of the RxDn port pin. The Receiver buffer FIFO will be flushed when the Receiver is disabled. Remaining data in the buffer will be lost 20.7.7 Flushing the Receive Buffer The receiver buffer FIFO will be flushed when the Receiver is disabled, i.e., the buffer will be emptied of its contents. Unread data will be lost. If the buffer has to be flushed during normal operation, due to for instance an error condition, read the UDRn I/O location until the RXCn Flag is cleared. The following code example shows how to flush the receive buffer. Assembly Code Example(1) USART_Flush: in r16, UCSRnA sbrs r16, RXCn ret in r16, UDRn rjmp USART_Flush C Code Example(1) void USART_Flush( void ) { unsigned char dummy; while ( UCSRnA & (1< 2 CPU clock cycles for fck < 12MHz, 3 CPU clock cycles for fck >= 12MHz High: > 2 CPU clock cycles for fck < 12MHz, 3 CPU clock cycles for fck >= 12MHz 309 9223B-AVR-09/11 28.8.1 Serial Programming Pin Mapping Table 28-17. Pin Mapping Serial Programming 28.8.2 Symbol Pins I/O Description MOSI PB3 I Serial Data in MISO PB4 O Serial Data out SCK PB5 I Serial Clock Serial Programming Algorithm When writing serial data to the Atmel(R) ATmega48PA/88PA/168PA, data is clocked on the rising edge of SCK. When reading data from the Atmel ATmega48PA/88PA/168PA, data is clocked on the falling edge of SCK. See Figure 28-9 for timing details. To program and verify the Atmel ATmega48PA/88PA/168PA in the serial programming mode, the following sequence is recommended (See Serial Programming Instruction set in Table 28-19 on page 312): 1. Power-up sequence: Apply power between VCC and GND while RESET and SCK are set to "0". In some systems, the programmer can not guarantee that SCK is held low during power-up. In this case, RESET must be given a positive pulse of at least two CPU clock cycles duration after SCK has been set to "0". 2. Wait for at least 20ms and enable serial programming by sending the Programming Enable serial instruction to pin MOSI. 3. The serial programming instructions will not work if the communication is out of synchronization. When in sync. the second byte (0x53), will echo back when issuing the third byte of the Programming Enable instruction. Whether the echo is correct or not, all four bytes of the instruction must be transmitted. If the 0x53 did not echo back, give RESET a positive pulse and issue a new Programming Enable command. 4. The Flash is programmed one page at a time. The memory page is loaded one byte at a time by supplying the 6 LSB of the address and data together with the Load Program Memory Page instruction. To ensure correct loading of the page, the data low byte must be loaded before data high byte is applied for a given address. The Program Memory Page is stored by loading the Write Program Memory Page instruction with the 7 MSB of the address. If polling (RDY/BSY) is not used, the user must wait at least tWD_FLASH before issuing the next page (See Table 28-18). Accessing the serial programming interface before the Flash write operation completes can result in incorrect programming. 310 Atmel ATmega48PA/88PA/168PA [Preliminary] 9223B-AVR-09/11 Atmel ATmega48PA/88PA/168PA [Preliminary] 5. A: The EEPROM array is programmed one byte at a time by supplying the address and data together with the appropriate Write instruction. An EEPROM memory location is first automatically erased before new data is written. If polling (RDY/BSY) is not used, the user must wait at least tWD_EEPROM before issuing the next byte (See Table 28-18). In a chip erased device, no 0xFFs in the data file(s) need to be programmed. B: The EEPROM array is programmed one page at a time. The Memory page is loaded one byte at a time by supplying the 6 LSB of the address and data together with the Load EEPROM Memory Page instruction. The EEPROM Memory Page is stored by loading the Write EEPROM Memory Page Instruction with the 7 MSB of the address. When using EEPROM page access only byte locations loaded with the Load EEPROM Memory Page instruction is altered. The remaining locations remain unchanged. If polling (RDY/BSY) is not used, the used must wait at least tWD_EEPROM before issuing the next byte (See Table 28-18). In a chip erased device, no 0xFF in the data file(s) need to be programmed. 6. Any memory location can be verified by using the Read instruction which returns the content at the selected address at serial output MISO. 7. At the end of the programming session, RESET can be set high to commence normal operation. 8. Power-off sequence (if needed): Set RESET to "1". Turn VCC power off. Table 28-18. Typical Wait Delay Before Writing the Next Flash or EEPROM Location Symbol Minimum Wait Delay tWD_FLASH 4.5ms tWD_EEPROM 3.6ms tWD_ERASE 9.0ms 311 9223B-AVR-09/11 28.8.3 Serial Programming Instruction set Table 28-19 on page 312 and Figure 28-8 on page 313 describes the Instruction set. Table 28-19. Serial Programming Instruction Set (Hexadecimal values) Instruction Format Instruction/Operation Byte 1 Byte 2 Byte 3 Byte4 Programming Enable $AC $53 $00 $00 Chip Erase (Program Memory/EEPROM) $AC $80 $00 $00 Poll RDY/BSY $F0 $00 $00 data byte out Load Extended Address byte(1) $4D $00 Extended adr $00 Load Program Memory Page, High byte $48 $00 adr LSB high data byte in Load Program Memory Page, Low byte $40 $00 adr LSB low data byte in Load EEPROM Memory Page (page access) $C1 $00 0000 000aa data byte in Read Program Memory, High byte $28 adr MSB adr LSB high data byte out Read Program Memory, Low byte $20 adr MSB adr LSB low data byte out Read EEPROM Memory $A0 0000 00aa aaaa aaaa data byte out Read Lock bits $58 $00 $00 data byte out Read Signature Byte $30 $00 0000 000aa data byte out Read Fuse bits $50 $00 $00 data byte out Read Fuse High bits $58 $08 $00 data byte out Read Extended Fuse Bits $50 $08 $00 data byte out Read Calibration Byte $38 $00 $00 data byte out Write Program Memory Page $4C adr MSB(8) adr LSB(8) $00 Write EEPROM Memory $C0 0000 00aa aaaa aaaa data byte in Write EEPROM Memory Page (page access) $C2 0000 00aa aaaa aa00 $00 Write Lock bits $AC $E0 $00 data byte in Write Fuse bits $AC $A0 $00 data byte in Write Fuse High bits $AC $A8 $00 data byte in Write Extended Fuse Bits $AC $A4 $00 data byte in Load Instructions Read Instructions Write Instructions(6) Notes: 1. Not all instructions are applicable for all parts. 2. a = address. 3. Bits are programmed `0', unprogrammed `1'. 4. To ensure future compatibility, unused Fuses and Lock bits should be unprogrammed (`1'). 5. Refer to the corresponding section for Fuse and Lock bits, Calibration and Signature bytes and Page size. 6. Instructions accessing program memory use a word address. This address may be random within the page range. 7. See http://www.atmel.com/avr for Application Notes regarding programming and programmers. 8. WORDS 312 Atmel ATmega48PA/88PA/168PA [Preliminary] 9223B-AVR-09/11 Atmel ATmega48PA/88PA/168PA [Preliminary] If the LSB in RDY/BSY data byte out is `1', a programming operation is still pending. Wait until this bit returns `0' before the next instruction is carried out. Within the same page, the low data byte must be loaded prior to the high data byte. After data is loaded to the page buffer, program the EEPROM page, see Figure 28-8 on page 313. Figure 28-8. Serial Programming Instruction example Serial Programming Instruction Load Program Memory Page (High/Low Byte)/ Load EEPROM Memory Page (page access) Byte 1 Byte 2 Adr M A MSB SB Byte 3 Write Program Memory Page/ Write EEPROM Memory Page Byte 1 Byte 4 Byte 2 Adr MSB Adr LSB Bit 15 B Bit 15 B 0 Byte 3 Byte 4 Adr Adrr LSB LSB B 0 Page Buffer Page Offset Page 0 Page 1 Page 2 Page Number Page N-1 Program Memory/ EEPROM Memory 28.8.4 SPI Serial Programming Characteristics Figure 28-9. Serial Programming Waveforms SERIAL DATA INPUT (MOSI) MSB LSB SERIAL DATA OUTPUT (MISO) MSB LSB SERIAL CLOCK INPUT (SCK) SAMPLE For characteristics of the SPI module see "SPI Timing Characteristics" on page 319. 313 9223B-AVR-09/11 29. Electrical Characteristics All AC/DC characteristics contained in this datasheet are based on characterization of the Atmel(R) ATmega48PA/88PA/168PA AVR microcontroller manufactured in an automotive process technology. 29.1 Absolute Maximum Ratings(1) Operating Temperature..................................-55C to +125C Storage Temperature .....................................-65C to +150C Voltage on any Pin except RESET with respect to Ground ...............................-0.5V to VCC+0.5V Voltage on RESET with respect to Ground..... -0.5V to +13.0V Note: 1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum Operating Voltage ............................................ 6.0V DC Current per I/O Pin ................................................ 40.0mA DC Current VCC and GND Pins ................................. 200.0mA 314 Atmel ATmega48PA/88PA/168PA [Preliminary] 9223B-AVR-09/11 Atmel ATmega48PA/88PA/168PA [Preliminary] 29.2 DC Characteristics Table 29-1. Symbol Common DC characteristics TA = -40C to 125C, VCC = 1.8V to 5.5V (unless otherwise noted) Parameter Condition Min. Typ. Max. Units (1) VIL Input Low Voltage, except XTAL1 and RESET pin VCC = 1.8V - 2.5V VCC = 2.7V - 5.5V -0.5 -0.5 0.1VCC 0.3VCC(1) V VIH Input High Voltage, except XTAL1 and RESET pins VCC = 1.8V - 2.4V VCC = 2.4V - 5.5V 0.7VCC(2) 0.6VCC(2) VCC + 0.5 VCC + 0.5 V VIL1 Input Low Voltage, XTAL1 pin VCC = 1.8V - 5.5V -0.5 0.1VCC(1) V VIH1 Input High Voltage, XTAL1 pin VCC = 1.8V - 2.4V VCC = 2.4V - 5.5V 0.8VCC(2) 0.7VCC(2) VCC + 0.5 VCC + 0.5 V VIL2 Input Low Voltage, RESET pin VCC = 1.8V - 5.5V -0.5 0.1VCC(1) V VIH2 Input High Voltage, RESET pin VCC = 1.8V - 5.5V 0.9VCC(2) VCC + 0.5 V VOL Output Low Voltage(4) except RESET pin IOL = 20mA, VCC = 5V IOL = 5mA, VCC = 3V IOL = 0.5mA, VCC = 1.8V 0.8 0.5 0.25 V VOH Output High Voltage(3) except Reset pin IOH = -20mA, VCC = 5V IOH = -10mA, VCC = 3V IOH = -0.5mA, VCC = 1.8V IIL Input Leakage Current I/O Pin VCC = 5.5V, pin low (absolute value) 1 A IIH Input Leakage Current I/O Pin VCC = 5.5V, pin high (absolute value) 1 A RRST Reset Pull-up Resistor VCC = 5V, Vin = 0V 30 60 k RPU I/O Pin Pull-up Resistor 20 50 k VACIO Analog Comparator Input Offset Voltage VCC = 5V 0.1VCC 12MHz 2. All DC Characteristics contained in this datasheet are based on simulation and characterization of other AVR microcontrollers manufactured in the same process technology. These values are preliminary values representing design targets, and will be updated after characterization of actual silicon. 319 9223B-AVR-09/11 Figure 29-3. SPI Interface Timing Requirements (Master Mode) SS 6 1 SCK (CPOL = 0) 2 2 SCK (CPOL = 1) 4 MISO (Data Input) 5 3 MSB ... LSB 7 MOSI (Data Output) MSB 8 ... LSB Figure 29-4. SPI Interface Timing Requirements (Slave Mode) SS 10 9 16 SCK (CPOL = 0) 11 11 SCK (CPOL = 1) 13 MOSI (Data Input) 14 12 MSB ... LSB 17 15 MISO (Data Output) 320 MSB ... LSB X Atmel ATmega48PA/88PA/168PA [Preliminary] 9223B-AVR-09/11 Atmel ATmega48PA/88PA/168PA [Preliminary] 29.7 Two-wire Serial Interface Characteristics Table 29-8 describes the requirements for devices connected to the 2-wire Serial Bus. The Atmel(R) ATmega48PA/88PA/168PA 2-wire Serial Interface meets or exceeds these requirements under the noted conditions. Timing symbols refer to Figure 29-5. Table 29-8. Two-wire Serial Bus Requirements Symbol Parameter Min. Max Units VIL Input Low-voltage -0.5 0.3 VCC V VIH Input High-voltage 0.7 VCC VCC + 0.5 V Vhys(1) VOL(1) tr(1) tof(1) tSP(1) Hysteresis of Schmitt Trigger Inputs Ii Input Current each I/O Pin Ci(1) Capacitance for each I/O Pin fSCL Rp 0.05 Output Low-voltage Output Fall Time from VIHmin to VILmax 10 pF < Cb < 400 pF (3) SCL Clock Frequency Value of Pull-up resistor Hold Time (repeated) START Condition tLOW Low Period of the SCL Clock tHIGH High period of the SCL clock tSU;STA Set-up time for a repeated START condition tHD;DAT Data hold time tSU;DAT Data setup time tSU;STO Setup time for STOP condition tBUF Bus free time between a STOP and START condition - V 0.4 V 20 + 0.1Cb(3)(2) 300 ns 0.1Cb(3)(2) 250 ns 20 + Spikes Suppressed by Input Filter VCC(2) 0 3 mA sink current Rise Time for both SDA and SCL tHD;STA Notes: Condition 0 0.1VCC < Vi < 0.9VCC fCK(4) (5) > max(16fSCL, 250kHz) (2) 50 ns -10 10 A - 10 pF 0 400 kHz fSCL 100kHz V CC - 0,4V ---------------------------3mA 1000ns ------------------Cb fSCL > 100kHz V CC - 0,4V ---------------------------3mA 300ns ---------------Cb fSCL 100kHz 4.0 - s fSCL > 100kHz 0.6 - s fSCL 100kHz 4.7 - s fSCL > 100kHz 1.3 - s fSCL 100kHz 4.0 - s fSCL > 100kHz 0.6 - s fSCL 100kHz 4.7 - s fSCL > 100kHz 0.6 - s fSCL 100kHz 0 3.45 s fSCL > 100kHz 0 0.9 s fSCL 100kHz 250 - ns fSCL > 100kHz 100 - ns fSCL 100kHz 4.0 - s fSCL > 100kHz 0.6 - s fSCL 100kHz 4.7 - s fSCL > 100kHz 1.3 - s 1. In the Atmel ATmega48PA/88PA/168PA, this parameter is characterized and not 100% tested. 2. Required only for fSCL > 100kHz. 3. Cb = capacitance of one bus line in pF. 4. fCK = CPU clock frequency 5. This requirement applies to all Atmel ATmega48PA/88PA/168PA 2-wire Serial Interface operation. Other devices connected to the 2-wire Serial Bus need only obey the general fSCL requirement. 321 9223B-AVR-09/11 Figure 29-5. Two-wire Serial Bus Timing tHIGH tof tLOW tr tLOW SCL tSU;STA tHD;STA tHD;DAT tSU;DAT tSU;STO SDA tBUF 29.8 ADC Characteristics Table 29-9. Symbol ADC Characteristics Parameter Condition Resolution -40C to 125C, 2.70V to 5.50V ADC clock = 200kHz 10 TUE Absolute accuracy VCC = 4V, VREF = 4V 2.2 3.5 LSB INL Integral Non-Linearity VCC = 4V, VREF = 4V 0.6 1.5 LSB DNL Differential Non-Linearity VCC = 4V, VREF = 4V 0.7 LSB Gain Error VCC = 4V, VREF = 4V -4.0 3.0 LSB Offset Error VCC = 4V, VREF = 4V -3.5 3.5 LSB 50 200 kHz VCC - 0.3 VCC + 0.3 V 1.0 AVCC V GND VREF V Clock Frequency AVCC (1) VREF VIN Analog Supply Voltage Reference Voltage Input Voltage Min. Typ Max Bits 0.3 Input Bandwidth 38.5 VINT Internal Voltage Reference Reference Input Resistance 32 k RAIN Analog Input Resistance 100 M 322 1.1 kHz RREF Note: 1.0 Units 1.2 V 1. AVCC absolute min./max: 1.8V/5.5V Atmel ATmega48PA/88PA/168PA [Preliminary] 9223B-AVR-09/11 Atmel ATmega48PA/88PA/168PA [Preliminary] 29.9 Parallel Programming Characteristics Table 29-10. Parallel Programming Characteristics, VCC = 5V 10% Symbol Parameter Min. VPP Programming Enable Voltage 11.5 IPP Programming Enable Current tDVXH Data and Control Valid before XTAL1 High 67 ns tXLXH XTAL1 Low to XTAL1 High 200 ns tXHXL XTAL1 Pulse Width High 150 ns tXLDX Data and Control Hold after XTAL1 Low 67 ns tXLWL XTAL1 Low to WR Low 0 ns tXLPH XTAL1 Low to PAGEL high 0 ns tPLXH PAGEL low to XTAL1 high 150 ns tBVPH BS1 Valid before PAGEL High 67 ns tPHPL PAGEL Pulse Width High 150 ns tPLBX BS1 Hold after PAGEL Low 67 ns tWLBX BS2/1 Hold after WR Low 67 ns tPLWL PAGEL Low to WR Low 67 ns tBVWL BS1 Valid to WR Low 67 ns tWLWH WR Pulse Width Low 150 ns tWLRL WR Low to RDY/BSY Low (1) WR Low to RDY/BSY High tWLRH (2) Units 12.5 V 250 A 1 s 3.7 4.5 ms 7.5 9 ms WR Low to RDY/BSY High for Chip Erase tXLOL XTAL1 Low to OE Low 0 tBVDV BS1 Valid to DATA valid 0 tOLDV Notes: Max 0 tWLRH_CE tOHDZ Typ ns 250 ns OE Low to DATA Valid 250 ns OE High to DATA Tri-stated 250 ns 1. tWLRH is valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lock bits commands. 2. tWLRH_CE is valid for the Chip Erase command. Figure 29-6. Parallel Programming Timing, Including some General Timing Requirements tXLWL tXHXL XTAL1 tDVXH tXLDX tBVPH tPLBX t BVWL Data & Contol (DATA, XA0/1, BS1, BS2) PAGEL tWLBX tPHPL tWLWH WR tPLWL WLRL RDY/BSY tWLRH 323 9223B-AVR-09/11 Figure 29-7. Parallel Programming Timing, Loading Sequence with Timing Requirements(1) LOAD ADDRESS (LOW BYTE) LOAD DATA LOAD DATA (HIGH BYTE) LOAD DATA (LOW BYTE) tXLPH t XLXH LOAD ADDRESS (LOW BYTE) tPLXH XTAL1 BS1 PAGEL DATA ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte) XA0 XA1 Note: 1. The timing requirements shown in Figure 29-6 (i.e., tDVXH, tXHXL, and tXLDX) also apply to loading operation. Figure 29-8. Parallel Programming Timing, Reading Sequence (within the Same Page) with Timing Requirements(1) LOAD ADDRESS (LOW BYTE) READ DATA (LOW BYTE) READ DATA (HIGH BYTE) LOAD ADDRESS (LOW BYTE) tXLOL XTAL1 tBVDV BS1 tOLDV OE DATA tOHDZ ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte) XA0 XA1 Note: 324 1. The timing requirements shown in Figure 29-6 (i.e., tDVXH, tXHXL, and tXLDX) also apply to reading operation. Atmel ATmega48PA/88PA/168PA [Preliminary] 9223B-AVR-09/11 Atmel ATmega48PA/88PA/168PA [Preliminary] 30. Typical Characteristics The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A square wave generator with rail-to-rail output is used as clock source. 30.1 30.1.1 ATmega48PA Typical Characteristics Active Supply Current Figure 30-1. Active Supply Current versus Low Frequency (0.1-1.0MHz) 1.4 6 1.2 5.5 5 ICC [mA] 1 4.5 0.8 4 3.6 0.6 3.3 3 0.4 2.7 0.2 2.4 2.1 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 2 1 1.8 Frequency [MHz] 1.5 1.4 Figure 30-2. Active Supply Current versus Frequency (1-16MHz) 20 18 6 16 5.5 ICC [mA] 14 5 12 4.5 10 4 8 3.6 6 3.3 4 3 2 2.7 2.5 0 0 2 4 6 8 10 Frequency [MHz] 12 14 16 18 20 2.2 2 1.8 325 9223B-AVR-09/11 30.1.2 Idle Supply Current Figure 30-3. Idle Supply Current versus Low Frequency (0.1-1.0MHz) ICC [mA] 0.18 0.16 6 0.14 5.5 5 0.12 4.5 0. 1 0.08 4 3.6 0.06 3.3 0.04 3 2.7 0.02 2.5 0 0 0. 1 0.2 0.3 0.4 0.5 0.6 0.7 0. 8 0.9 1 Frequenc y [ MHz] 2.2 2 1.8 1.62 Figure 30-4. Idle Supply Current versus Frequency (1-16MHz) 4 ICC [mA] 3.5 6 3 5.5 5 2.5 4.5 2 4 3.6 1.5 3.3 1 3 2.7 0.5 2.5 0 0 2 4 6 8 10 12 14 16 18 Frequenc y [MHz ] 20 2.2 2 1.8 1.62 326 Atmel ATmega48PA/88PA/168PA [Preliminary] 9223B-AVR-09/11 Atmel ATmega48PA/88PA/168PA [Preliminary] 30.1.3 Supply Current of IO Modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register. See "Power Reduction Register" on page 42 for details. Table 30-1. PRR bit PRUSART0 Additional Current Consumption for the Different I/O Modules (Absolute Values) Typical Numbers VCC = 2V, F = 1MHz VCC = 3V, F = 4MHz VCC = 5V, F = 8MHz 2.9A 20.7A 97.4A PRTWI 6.0A 44.8A 219.7A PRTIM2 5.0A 34.5A 141.3A PRTIM1 3.6A 24.4A 107.7A PRTIM0 1.4A 9.5A 38.4A PRSPI 5.0A 38.0A 190.4A PRADC 6.1A 47.4A 244.7A Table 30-2. Additional Current Consumption (Percentage) in Active and Idle Mode Additional Current consumption compared to Active with external clock (see Figure 30-1 on page 325 and Figure 30-2 on page 325) Additional Current consumption compared to Idle with external clock (see Figure 30-3 on page 326 and Figure 30-4 on page 326) PRUSART0 1.8% 11.4% PRTWI 3.9% 20.6% PRTIM2 2.9% 15.7% PRTIM1 2.1% 11.2% PRTIM0 0.8% 4.2% PRR bit PRSPI 3.3% 17.6% PRADC 4.2% 22.1% It is possible to calculate the typical current consumption based on the numbers from Table 30-2 for other VCC and frequency settings than listed in Table 30-1. 30.1.3.1 Example Calculate the expected current consumption in idle mode with TIMER1, ADC, and SPI enabled at VCC = 2.0V and F = 1MHz. From Table 30-2, third column, we see that we need to add 11.2% for the TIMER1, 22.1% for the ADC, and 17.6% for the SPI module. Reading from Figure 30-3 on page 326, we find that the idle current consumption is ~0.028mA at VCC = 2.0V and F = 1MHz. The total current consumption in idle mode with TIMER1, ADC, and SPI enabled, gives: I CC total 0.028 mA (1 + 0.112 + 0.221 + 0.176) 0.042 mA 327 9223B-AVR-09/11 30.1.4 Power-down Supply Current Figure 30-5. Power-Down Supply Current versus VCC (Watchdog Timer Disabled) 60 ICC [A] 50 40 150 30 125 85 20 25 10 -40 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 VCC [V] Figure 30-6. Power-Down Supply Current versus VCC (Watchdog Timer Enabled) 100 90 80 ICC [A] 70 60 150 50 125 40 85 30 25 20 -40 10 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 VCC [V] 30.1.5 Pin Pull-Up Figure 30-7. I/O Pin Pull-up Resistor Current versus Input Voltage (VCC = 5.0V) 160 140 IOP [A] 120 100 150 80 125 85 60 25 40 -40 20 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VOP [V] 328 Atmel ATmega48PA/88PA/168PA [Preliminary] 9223B-AVR-09/11 Atmel ATmega48PA/88PA/168PA [Preliminary] Figure 30-8. Reset Pull-up Resistor Current versus Reset Pin Voltage (VCC = 5V) 140 IRE S ET [A] 120 100 80 150 60 125 40 85 25 20 -40 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 -20 VRE S E T [V] 30.1.6 Pin Driver Strength Figure 30-9. I/O Pin Output Voltage versus Sink Current (VCC = 1.8V) 0.5 0.45 0.4 Current [V] 0.35 0.3 0.25 150 0.2 125 0.15 85 0.1 25 -40 0.05 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 IOL [mA] Figure 30-10. I/O Pin Output Voltage versus Sink Current (VCC = 3V) 0.3 0.25 VOL [V] 0.2 0.15 150 125 0.1 85 25 0.05 -40 0 0 1 2 3 4 5 IOL [mA] 329 9223B-AVR-09/11 Figure 30-11. I/O Pin Output Voltage versus Sink Current (VCC = 5V) 0.8 0.7 VOL [V] 0.6 0.5 0.4 150 0.3 125 85 0.2 25 -40 0.1 0 0 2 4 6 8 10 12 14 16 18 20 IOL [mA] Figure 30-12. I/O Pin Output Voltage versus Source Current (Vcc = 1.8V) 2 Current [V] 1.8 1.6 150 1.4 125 85 25 1.2 -40 1 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 IOH [mA] Figure 30-13. I/O Pin Output Voltage versus Source Current (Vcc = 3V) 3.1 3 2.9 VOH [V] 2.8 2.7 150 2.6 125 2.5 85 2.4 25 2.3 -40 2.2 0 1 2 3 4 5 6 7 8 9 10 IOH [mA] 330 Atmel ATmega48PA/88PA/168PA [Preliminary] 9223B-AVR-09/11 Atmel ATmega48PA/88PA/168PA [Preliminary] Figure 30-14. I/O Pin Output Voltage versus Source Current (VCC = 5V) 5.2 5 VOH [V] 4.8 4.6 150 4.4 125 4.2 85 25 4 -40 3.8 0 2 4 6 8 10 12 14 16 18 20 IOH [mA] 30.1.7 Pin Threshold and Hysteresis Figure 30-15. I/O Pin Input Threshold Voltage versus VCC (VIH, I/O Pin read as `1') 4 3.5 Threshold [V] 3 2.5 2 150 125 1.5 85 1 25 0.5 -40 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 30-16. I/O Pin Input Threshold Voltage versus VCC (VIL, I/O Pin read as `0') 2.5 Thr eshold [V] 2 1.5 150 1 125 85 25 0.5 -40 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] 331 9223B-AVR-09/11 Figure 30-17. Reset Input Threshold Voltage versus VCC (VIH, I/O Pin read as `1') 5 4.5 4 Thr eshold [V] 3.5 3 2.5 150 2 125 1.5 85 1 25 -40 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 30-18. Reset Input Threshold Voltage versus VCC (VIL, I/O Pin read as `0') 2.5 Threshold [V] 2 1.5 150 1 125 85 25 0.5 -40 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] 30.1.8 BOD Threshold Figure 30-19. BOD Thresholds versus Temperature (BODLEVEL is 1.8V) 2 1.95 Thr eshold [V] 1.9 1.85 1 1.8 0 1.75 1.7 1.65 1.6 - 50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 Temper ature [C] 332 Atmel ATmega48PA/88PA/168PA [Preliminary] 9223B-AVR-09/11 Atmel ATmega48PA/88PA/168PA [Preliminary] Figure 30-20. BOD Thresholds versus Temperature (BODLEVEL is 2.7V) 2.9 2.85 Thr eshold [V] 2.8 2.75 1 2.7 0 2.65 2.6 2.55 2.5 - 50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 Temperatur e [C] Figure 30-21. BOD Thresholds versus Temperature (BODLEVEL is 4.3V) 4.5 Threshold [V] 4.4 4.3 1 4.2 0 4.1 4 3.9 - 50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 Temperature [C] Figure 30-22. Bandgap Voltage versus VCC 1.15 Bandgap Voltage [V] 1.125 1.1 1.075 1.05 150 1.025 125 1 85 0.975 25 -40 0.95 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] 333 9223B-AVR-09/11 30.1.9 Internal Oscillator Speed Figure 30-23. Watchdog Oscillator Frequency versus Temperature 150 6 140 5. 5 FRC [kHz] 5 4. 5 130 4 3. 6 120 3. 3 3 110 2. 7 2. 4 100 -40 2. 2 -30 - 20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 2 Temperature [ ] 1. 8 1. 6 Figure 30-24. Watchdog Oscillator Frequency versus VCC 160 FRC [kHz] 150 140 150 130 125 85 120 25 -40 110 100 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 30-25. Calibrated 8MHz RC Oscillator Frequency versus VCC 8.4 8.3 FRC [MHz] 8.2 8.1 150 8 125 85 7.9 25 7.8 -40 7.7 7.6 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 V CC [V] 334 Atmel ATmega48PA/88PA/168PA [Preliminary] 9223B-AVR-09/11 Atmel ATmega48PA/88PA/168PA [Preliminary] Figure 30-26. Calibrated 8MHz RC Oscillator Frequency versus Temperature 8.4 8.3 6 5.5 8.2 FRC [MHz] 5 8.1 4.5 4 8 3.6 7.9 3.3 7.8 3 7.7 2.7 2.5 7.6 - 40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 2.2 2 Temperature [ ] 1.8 Figure 30-27. Calibrated 8MHz RC Oscillator Frequency versus OSCCAL Value 16 14 FRC [MHz] 12 10 150 8 125 85 6 25 4 -40 2 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 OSCCAL [X1] 30.1.10 Reset Pulse width Figure 30-28. Minimum Reset Pulse width versus VCC 2500 Puls ewidt h [ns] 2000 1500 150 1000 125 85 500 25 -40 0 1.8 2. 3 2.8 3.3 3.8 4.3 4.8 5. 3 5.8 V CC [ V] 335 9223B-AVR-09/11 30.2 30.2.1 ATmega88PA Typical Characteristics Active Supply Current Figure 30-29. Active Supply Current versus Low Frequency (0.1-1.0MHz) 1.6 6 1.4 5. 5 1.2 5 4. 5 ICC [mA] 1 4 0.8 3. 6 0.6 3. 3 3 0.4 2. 7 2. 4 0.2 2. 1 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 2 1. 8 Frequency [MHz] 1. 5 1. 4 Figure 30-30. Active Supply Current versus Frequency (1-16MHz) 20 ICC [mA] 18 6 16 5.5 14 5 12 4.5 10 4 3.6 8 3.3 6 3 2.7 4 2 2.5 0 0 2 4 6 8 10 12 14 16 18 Frequenc y [MHz ] 20 2.2 2 1.8 1.62 336 Atmel ATmega48PA/88PA/168PA [Preliminary] 9223B-AVR-09/11 Atmel ATmega48PA/88PA/168PA [Preliminary] 30.2.2 Idle Supply Current Figure 30-31. Idle Supply Current versus Low Frequency (0.1-1.0MHz) 0.18 0.16 6 0.14 5.5 5 ICC [mA] 0.12 4.5 0. 1 0.08 4 3.6 0.06 3.3 0.04 3 2.7 0.02 2.5 0 2.2 0 0. 1 0.2 0.3 0.4 0.5 0.6 0.7 0. 8 0.9 1 Frequenc y [MHz] 2 1.8 1.62 Figure 30-32. Idle Supply Current versus Frequency (1-16MHz) 4 3.5 6 3 5.5 5 ICC [mA] 2.5 4.5 2 4 3.6 1.5 3.3 1 3 2.7 0.5 2.5 0 0 2 4 6 8 10 Frequenc y [MHz ] 12 14 16 18 20 2.2 2 1.8 337 9223B-AVR-09/11 30.2.3 Supply Current of IO Modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register. See "Power Reduction Register" on page 42 for details. Table 30-3. PRR bit PRUSART0 Additional Current Consumption for the Different I/O Modules (Absolute Values) Typical numbers VCC = 2V, F = 1MHz VCC = 3V, F = 4MHz VCC = 5V, F = 8MHz 2.9A 20.7A 97.4A PRTWI 6.0A 44.8A 219.7A PRTIM2 5.0A 34.5A 141.3A PRTIM1 3.6A 24.4A 107.7A PRTIM0 1.4A 9.5A 38.4A PRSPI 5.0A 38.0A 190.4A PRADC 6.1A 47.4A 244.7A Table 30-4. PRR bit Additional Current Consumption (percentage) in Active and Idle mode Additional Current consumption compared to Active with external clock (see Figure 30-1 on page 325 and Figure 30-2 on page 325) Additional Current consumption compared to Idle with external clock (see Figure 30-3 on page 326 and Figure 30-4 on page 326) PRUSART0 1.8% 11.4% PRTWI 3.9% 20.6% PRTIM2 2.9% 15.7% PRTIM1 2.1% 11.2% PRTIM0 0.8% 4.2% PRSPI 3.3% 17.6% PRADC 4.2% 22.1% It is possible to calculate the typical current consumption based on the numbers from Table 30-2 on page 327 for other VCC and frequency settings than listed in Table 30-1 on page 327. 30.2.3.1 Example Calculate the expected current consumption in idle mode with TIMER1, ADC, and SPI enabled at VCC = 2.0V and F = 1MHz. From Table 30-2 on page 327, third column, we see that we need to add 11.2% for the TIMER1, 22.1% for the ADC, and 17.6% for the SPI module. Reading from Figure 30-3 on page 326, we find that the idle current consumption is ~0.028mA at VCC = 2.0V and F = 1MHz. The total current consumption in idle mode with TIMER1, ADC, and SPI enabled, gives: I CC total 0.028 mA (1 + 0.112 + 0.221 + 0.176) 0.042 mA 338 Atmel ATmega48PA/88PA/168PA [Preliminary] 9223B-AVR-09/11 Atmel ATmega48PA/88PA/168PA [Preliminary] 30.2.4 Power-down Supply Current Figure 30-33. Power-Down Supply Current versus VCC (Watchdog Timer Disabled) 100 90 80 70 ICC [uA] 60 150 50 125 40 85 30 25 20 -40 10 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 V CC [V] Figure 30-34. Power-Down Supply Current versus VCC (Watchdog Timer Enabled) 100 90 80 70 ICC [uA] 60 150 50 125 40 85 30 25 20 -40 10 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 V CC [V] 30.2.5 Pin Pull-Up Figure 30-35. I/O Pin Pull-up Resistor Current versus Input Voltage (VCC = 5.0V) 160 140 120 IOP [uA] 100 150 80 125 85 60 25 40 -40 20 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 V OP [V] 339 9223B-AVR-09/11 Figure 30-36. Reset Pull-up Resistor Current versus Reset Pin Voltage (VCC = 5V) 140 120 IRE S ET [uA] 100 80 150 125 60 85 40 25 -40 20 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VRE S E T [V] 30.2.6 Pin Driver Strength Figure 30-37. I/O Pin Output Voltage versus Sink Current (VCC = 1.8V) 0.5 0.45 0.4 Curr ent [V] 0.35 0.3 0.25 150 0.2 125 0.15 85 0.1 25 -40 0.05 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 IOL [mA] Figure 30-38. I/O Pin Output Voltage versus Sink Current (VCC = 3V) 340 Atmel ATmega48PA/88PA/168PA [Preliminary] 9223B-AVR-09/11 Atmel ATmega48PA/88PA/168PA [Preliminary] Figure 30-39. I/O Pin Output Voltage versus Sink Current (VCC = 5V) 0.8 0.7 0.6 V OL [V] 0.5 0.4 150 0.3 125 85 0.2 25 -40 0.1 0 0 2 4 6 8 10 12 14 16 18 20 IOL [mA] Figure 30-40. I/O Pin Output Voltage versus Source Current (Vcc = 1.8V) 2 Current [V] 1.8 1.6 150 1.4 125 85 25 1.2 -40 1 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 IOH [mA] Figure 30-41. I/O Pin Output Voltage versus Source Current (Vcc = 3V) 341 9223B-AVR-09/11 Figure 30-42. I/O Pin Output Voltage versus Source Current (VCC = 5V) 5.2 5 V OH [V] 4.8 4.6 150 4.4 125 4.2 85 25 4 -40 3.8 0 2 4 6 8 10 12 14 16 18 20 IOH [mA] 30.2.7 Pin Threshold and Hysteresis Figure 30-43. I/O Pin Input Threshold Voltage versus VCC (VIH, I/O Pin read as `1') 3.5 3 Threshold [V] 2.5 2 150 1.5 125 85 1 25 0.5 -40 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 V CC [V ] Figure 30-44. I/O Pin Input Threshold Voltage versus VCC (VIL, I/O Pin read as `0') 2.5 Thr eshold [V] 2 1.5 150 1 125 85 25 0.5 -40 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 V CC [V] 342 Atmel ATmega48PA/88PA/168PA [Preliminary] 9223B-AVR-09/11 Atmel ATmega48PA/88PA/168PA [Preliminary] Figure 30-45. Reset Input Threshold Voltage versus VCC (VIH, I/O Pin read as `1') Figure 30-46. Reset Input Threshold Voltage versus VCC (VIL, I/O Pin read as `0') 2.5 Threshold [V] 2 1.5 150 1 125 85 25 0.5 -40 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 V CC [V ] 30.2.8 BOD Threshold Figure 30-47. BOD Thresholds versus Temperature (BODLEVEL is 1.8V) 2 1.95 Thr eshold [V] 1.9 1.85 1 1.8 0 1.75 1.7 1.65 1.6 - 50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 Temper ature [C] 343 9223B-AVR-09/11 Figure 30-48. BOD Thresholds versus Temperature (BODLEVEL is 2.7V) 2.9 2.85 Thr es hold [ V] 2.8 2.75 1 2.7 0 2.65 2.6 2.55 2.5 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 Temper ature [C] Figure 30-49. BOD Thresholds versus Temperature (BODLEVEL is 4.3V) 4.6 4.5 Threshold [V] 4.4 1 4.3 0 4.2 4.1 4 - 50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 Temperature [C] Figure 30-50. Bandgap Voltage versus VCC 1.1 1.098 Bandgap Voltage [V] 1.096 1.094 1.092 1.09 150 1.088 125 1.086 85 1.084 25 1.082 -40 1.08 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Vcc [V] 344 Atmel ATmega48PA/88PA/168PA [Preliminary] 9223B-AVR-09/11 Atmel ATmega48PA/88PA/168PA [Preliminary] 30.2.9 Internal Oscillator Speed Figure 30-51. Watchdog Oscillator Frequency versus Temperature Figure 30-52. Watchdog Oscillator Frequency versus VCC 140 135 130 FRC [kHz] 125 120 150 115 125 110 85 105 25 100 -40 95 90 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 V CC [V] Figure 30-53. Calibrated 8MHz RC Oscillator Frequency versus VCC 8.4 8.3 FRC [MHz] 8.2 8.1 150 8 125 85 7.9 25 7.8 -40 7.7 7.6 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 V CC [V] 345 9223B-AVR-09/11 Figure 30-54. Calibrated 8MHz RC Oscillator Frequency versus Temperature 8.4 8.3 6 5.5 8.2 FRC [MHz] 5 8.1 4.5 4 8 3.6 7.9 3.3 7.8 3 7.7 2.7 2.5 7.6 - 40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 2.2 100 110 120 130 140 150 2 Temperature [ ] 1.8 Figure 30-55. Calibrated 8MHz RC Oscillator Frequency versus OSCCAL Value 16 14 FRC [MHz] 12 10 150 8 125 85 6 25 4 -40 2 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 OSCCA L [X1] 30.2.10 Reset Pulse width Figure 30-56. Minimum Reset Pulse width versus VCC 1800 1600 Puls ewidth [ns] 1400 1200 1000 800 150 600 125 85 400 25 200 -40 0 1 .8 2.8 3 .8 4. 8 V CC [V] 346 Atmel ATmega48PA/88PA/168PA [Preliminary] 9223B-AVR-09/11 Atmel ATmega48PA/88PA/168PA [Preliminary] 30.3 30.3.1 ATmega168PA Typical Characteristics Active Supply Current Figure 30-57. Active Supply Current versus Low Frequency (0.1-1.0MHz) 1.6 1.4 6 1.2 5.5 5 ICC [mA] 1 4.5 0.8 4 0.6 3.6 3.3 0.4 3 2.7 0.2 2.4 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 2.2 2 Fr equency [MHz] 1.8 Figure 30-58. Active Supply Current versus Frequency (1-16MHz) 20 18 6 16 5.5 14 5 ICC [mA] 12 4.5 10 4 8 3.6 6 3.3 4 3 2 2.7 2.4 0 0 2 4 6 8 10 Frequency [MHz] 12 14 16 18 20 2.2 2 1.8 347 9223B-AVR-09/11 30.3.2 Idle Supply Current Figure 30-59. Idle Supply Current versus Low Frequency (0.1-1.0MHz) 0. 2 0.18 6 0.16 5.5 ICC [mA] 0.14 5 0.12 4.5 0. 1 4 0.08 0.06 3.6 3.3 0.04 3 0.02 2.7 2.4 0 0 0.1 0.2 0.3 0.4 0. 5 0.6 0.7 0.8 0.9 1 2.2 2 Frequenc y [MHz ] 1.8 Figure 30-60. Idle Supply Current versus Frequency (1-16MHz) 6 5 6 5.5 ICC [mA] 4 5 4.5 3 4 3.6 3.3 2 3 1 2.7 2.4 0 0 2 4 6 8 10 12 14 16 18 Frequenc y [MHz] 20 2.2 2 1.8 348 Atmel ATmega48PA/88PA/168PA [Preliminary] 9223B-AVR-09/11 Atmel ATmega48PA/88PA/168PA [Preliminary] 30.3.3 Supply Current of IO Modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register. See "Power Reduction Register" on page 42 for details. Table 30-5. PRR bit PRUSART0 Additional Current Consumption for the Different I/O Modules (Absolute Values) Typical numbers VCC = 2V, F = 1MHz VCC = 3V, F = 4MHz VCC = 5V, F = 8MHz 2.9A 20.7A 97.4A PRTWI 6.0A 44.8A 219.7A PRTIM2 5.0A 34.5A 141.3A PRTIM1 3.6A 24.4A 107.7A PRTIM0 1.4A 9.5A 38.4A PRSPI 5.0A 38.0A 190.4A PRADC 6.1A 47.4A 244.7A Table 30-6. PRR bit Additional Current Consumption (Percentage) in Active and Idle Mode Additional Current consumption compared to Active with external clock (see Figure 30-1 on page 325 and Figure 30-2 on page 325) Additional Current consumption compared to Idle with external clock (see Figure 30-3 on page 326 and Figure 30-4 on page 326) PRUSART0 1.8% 11.4% PRTWI 3.9% 20.6% PRTIM2 2.9% 15.7% PRTIM1 2.1% 11.2% PRTIM0 0.8% 4.2% PRSPI 3.3% 17.6% PRADC 4.2% 22.1% It is possible to calculate the typical current consumption based on the numbers from Table 30-2 on page 327 for other VCC and frequency settings than listed in Table 30-1 on page 327. 30.3.3.1 Example Calculate the expected current consumption in idle mode with TIMER1, ADC, and SPI enabled at VCC = 2.0V and F = 1MHz. From Table 30-2 on page 327, third column, we see that we need to add 11.2% for the TIMER1, 22.1% for the ADC, and 17.6% for the SPI module. Reading from Figure 30-3 on page 326, we find that the idle current consumption is ~0.028mA at VCC = 2.0V and F = 1MHz. The total current consumption in idle mode with TIMER1, ADC, and SPI enabled, gives: I CC total 0.028 mA (1 + 0.112 + 0.221 + 0.176) 0.042 mA 349 9223B-AVR-09/11 30.3.4 Power-down Supply Current Figure 30-61. Power-Down Supply Current versus VCC (Watchdog Timer Disabled) 50.00 45.00 40.00 35.00 ICC [uA] 30.00 25.00 150 20.00 125 15.00 85 10.00 25 5.00 -40 0.00 1.5 2 2.5 3 3.5 4 4.5 5 5.5 V CC [V] Figure 30-62. Power-Down Supply Current versus VCC (Watchdog Timer Enabled) 200 180 160 140 ICC [uA] 120 100 150 80 125 60 85 40 25 20 -40 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 V CC [V] 30.3.5 Pin Pull-Up Figure 30-63. I/O Pin Pull-up Resistor Current versus Input Voltage (VCC = 5.0V) 200 180 160 140 IOP [uA] 120 150 100 125 80 85 60 25 40 -40 20 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VOP [V] 350 Atmel ATmega48PA/88PA/168PA [Preliminary] 9223B-AVR-09/11 Atmel ATmega48PA/88PA/168PA [Preliminary] Figure 30-64. Reset Pull-up Resistor Current versus Reset Pin Voltage (VCC = 5V) 120 100 IRE S E T [uA] 80 60 150 125 40 85 20 25 -40 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 -20 VRE S E T [V] 30.3.6 Pin Driver Strength Figure 30-65. I/O Pin Output Voltage versus Sink Current (VCC = 1.8V) Figure 30-66. I/O Pin Output Voltage versus Sink Current (VCC = 3V) 0.3 0.25 V OL [V] 0.2 0.15 150 125 0.1 85 25 0.05 -40 0 0 1 2 3 4 5 IOL [mA] 351 9223B-AVR-09/11 Figure 30-67. I/O Pin Output Voltage versus Sink Current (VCC = 5V) 0.8 0.7 0.6 VOL [V] 0.5 0.4 150 0.3 125 85 0.2 25 -40 0.1 0 0 2 4 6 8 10 12 14 16 18 20 IOL [mA] Figure 30-68. I/O Pin Output Voltage versus Source Current (Vcc = 1.8V) 2 Current [V] 1.8 1.6 150 1.4 125 85 25 1.2 -40 1 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 IOH [mA] Figure 30-69. I/O Pin Output Voltage versus Source Current (Vcc = 3V) 3.1 3 2.9 V OH [V] 2.8 2.7 150 2.6 125 2.5 85 2.4 25 2.3 -40 2.2 0 1 2 3 4 5 6 7 8 9 10 IOH [mA] 352 Atmel ATmega48PA/88PA/168PA [Preliminary] 9223B-AVR-09/11 Atmel ATmega48PA/88PA/168PA [Preliminary] Figure 30-70. I/O Pin Output Voltage versus Source Current (VCC = 5V) 5.2 5 V OH [V] 4.8 4.6 150 4.4 125 4.2 85 25 4 -40 3.8 0 2 4 6 8 10 12 14 16 18 20 IOH [mA] 30.3.7 Pin Threshold and Hysteresis Figure 30-71. I/O Pin Input Threshold Voltage versus VCC (VIH, I/O Pin read as `1') 3 Threshold [V] 2.5 2 150 1.5 125 85 25 1 -40 0.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 V CC [V ] Figure 30-72. I/O Pin Input Threshold Voltage versus VCC (VIL, I/O Pin read as `0') 2.5 Thr eshold [V] 2 1.5 150 1 125 85 25 0.5 -40 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 V CC [V] 353 9223B-AVR-09/11 Figure 30-73. Reset Input Threshold Voltage versus VCC (VIH, I/O Pin read as `1') 3 2.5 Threshold [V] 2 1.5 150 125 1 85 25 0.5 -40 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V ] Figure 30-74. Reset Input Threshold Voltage versus VCC (VIL, I/O Pin read as `0') 2.5 Thr eshold [V] 2 1.5 150 1 125 85 25 0.5 -40 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] 30.3.8 BOD Threshold Figure 30-75. BOD Thresholds versus Temperature (BODLEVEL is 1.8V) 1.84 1.83 Thr eshold [V] 1.82 1 1.81 0 1.8 1.79 1.78 1.77 - 50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 Temper ature [C] 354 Atmel ATmega48PA/88PA/168PA [Preliminary] 9223B-AVR-09/11 Atmel ATmega48PA/88PA/168PA [Preliminary] Figure 30-76. BOD Thresholds versus Temperature (BODLEVEL is 2.7V) 2.78 2.76 Thr es hold [ V] 2.74 2.72 1 0 2.7 2.68 2.66 2.64 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 Temperature [C] Figure 30-77. BOD Thresholds versus Temperature (BODLEVEL is 4.3V) 4.36 4.34 Thr es hold [ V] 4.32 4.3 1 0 4.28 4.26 4.24 4.22 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 Temperature [C] Figure 30-78. Bandgap Voltage versus VCC 1.11 Bandgap Voltage [V] 1.105 1.1 1.095 150 125 1.09 85 1.085 25 -40 1.08 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Vcc [V] 355 9223B-AVR-09/11 30.3.9 Internal Oscillator Speed Figure 30-79. Watchdog Oscillator Frequency versus Temperature 140 135 FRC [kHz] 6 130 5.5 125 5 4.5 120 4 3.6 115 3.3 110 3 105 2.7 100 -40 - 30 -20 -10 2.4 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 2.2 2 Temperatur e [ ] 1.8 Figure 30-80. Watchdog Oscillator Frequency versus VCC 140 135 130 FRC [kHz] 125 150 120 125 85 115 25 110 -40 105 100 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 30-81. Calibrated 8MHz RC Oscillator Frequency versus VCC 8.4 8.3 FRC [MHz] 8.2 8.1 150 8 125 85 7.9 25 7.8 -40 7.7 7.6 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 V CC [V] 356 Atmel ATmega48PA/88PA/168PA [Preliminary] 9223B-AVR-09/11 Atmel ATmega48PA/88PA/168PA [Preliminary] Figure 30-82. Calibrated 8MHz RC Oscillator Frequency versus Temperature 8.4 8.3 6 5.5 8.2 FRC [MHz] 5 8.1 4.5 4 8 3.6 7.9 3.3 7.8 3 7.7 2.7 2.5 7.6 - 40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 2.2 2 Temperature [ ] 1.8 Figure 30-83. Calibrated 8MHz RC Oscillator Frequency versus OSCCAL Value 16 14 FRC [MHz] 12 10 150 8 125 6 85 25 4 -40 2 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 OSCCA L [X1] 30.3.10 Reset Pulse width Figure 30-84. Minimum Reset Pulse width versus VCC 2000 1800 1600 Pulsewidth [ns ] 1400 1200 1000 150 125 800 600 85 400 25 -40 200 0 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 5.8 V CC [V] 357 9223B-AVR-09/11 31. Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (0xFF) Reserved - - - - - - - - (0xFE) Reserved - - - - - - - - (0xFD) Reserved - - - - - - - - (0xFC) Reserved - - - - - - - - (0xFB) Reserved - - - - - - - - (0xFA) Reserved - - - - - - - - (0xF9) Reserved - - - - - - - - (0xF8) Reserved - - - - - - - - (0xF7) Reserved - - - - - - - - (0xF6) Reserved - - - - - - - - (0xF5) Reserved - - - - - - - - (0xF4) Reserved - - - - - - - - (0xF3) Reserved - - - - - - - - (0xF2) Reserved - - - - - - - - (0xF1) Reserved - - - - - - - - (0xF0) Reserved - - - - - - - - (0xEF) Reserved - - - - - - - - (0xEE) Reserved - - - - - - - - (0xED) Reserved - - - - - - - - (0xEC) Reserved - - - - - - - - (0xEB) Reserved - - - - - - - - (0xEA) Reserved - - - - - - - - (0xE9) Reserved - - - - - - - - (0xE8) Reserved - - - - - - - - (0xE7) Reserved - - - - - - - - (0xE6) Reserved - - - - - - - - (0xE5) Reserved - - - - - - - - (0xE4) Reserved - - - - - - - - (0xE3) Reserved - - - - - - - - (0xE2) Reserved - - - - - - - - (0xE1) Reserved - - - - - - - - (0xE0) Reserved - - - - - - - - (0xDF) Reserved - - - - - - - - (0xDE) Reserved - - - - - - - - (0xDD) Reserved - - - - - - - - (0xDC) Reserved - - - - - - - - (0xDB) Reserved - - - - - - - - (0xDA) Reserved - - - - - - - - (0xD9) Reserved - - - - - - - - (0xD8) Reserved - - - - - - - - (0xD7) Reserved - - - - - - - - (0xD6) Reserved - - - - - - - - (0xD5) Reserved - - - - - - - - (0xD4) Reserved - - - - - - - - (0xD3) Reserved - - - - - - - - Notes: Page 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only. 4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The Atmel ATmega48PA/88PA/168PA is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. 5. Only valid for the Atmel ATmega88A/88PA/168A/168PA/328/328P. 6. BODS and BODSE only available for picoPower devices ATmega48PA/88PA/168PA 358 Atmel ATmega48PA/88PA/168PA [Preliminary] 9223B-AVR-09/11 Atmel ATmega48PA/88PA/168PA [Preliminary] 31. Register Summary (Continued) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (0xD2) Reserved - - - - - - - - (0xD1) Reserved - - - - - - - - (0xD0) Reserved - - - - - - - - (0xCF) Reserved - - - - - - - - (0xCE) Reserved - - - - - - - - (0xCD) Reserved - - - - - - - - (0xCC) Reserved - - - - - - - - (0xCB) Reserved - - - - - - - - (0xCA) Reserved - - - - - - - - (0xC9) Reserved - - - - - - - - (0xC8) Reserved - - - - - - - - (0xC7) Reserved - - - - - - - - (0xC6) UDR0 (0xC5) UBRR0H USART I/O Data Register 196 USART Baud Rate Register High (0xC4) UBRR0L (0xC3) Reserved - - (0xC2) UCSR0C UMSEL01 (0xC1) UCSR0B RXCIE0 (0xC0) UCSR0A Page 201 USART Baud Rate Register Low 201 - - - - - - UMSEL00 UPM01 UPM00 USBS0 UCSZ01 /UDORD0 UCSZ00 / UCPHA0 UCPOL0 TXCIE0 UDRIE0 RXEN0 TXEN0 UCSZ02 RXB80 TXB80 198 RXC0 TXC0 UDRE0 FE0 DOR0 UPE0 U2X0 MPCM0 197 (0xBF) Reserved - - - - - - - - (0xBE) Reserved - - - - - - - - (0xBD) TWAMR TWAM6 TWAM5 TWAM4 TWAM3 TWAM2 TWAM1 TWAM0 - (0xBC) TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN - TWIE (0xBB) TWDR 2-wire Serial Interface Data Register 199/210 243 240 242 (0xBA) TWAR TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE 243 (0xB9) TWSR TWS7 TWS6 TWS5 TWS4 TWS3 - TWPS1 TWPS0 241 (0xB8) TWBR (0xB7) Reserved - (0xB6) ASSR - (0xB5) Reserved - (0xB4) OCR2B Timer/Counter2 Output Compare Register B (0xB3) OCR2A Timer/Counter2 Output Compare Register A 162 (0xB2) TCNT2 Timer/Counter2 (8-bit) 2-wire Serial Interface Bit Rate Register 240 - - - - - - EXCLK AS2 TCN2UB OCR2AUB OCR2BUB TCR2AUB TCR2BUB - - - - - - - 164 162 (0xB1) TCCR2B FOC2A FOC2B - - WGM22 CS22 CS21 CS20 162 161 (0xB0) TCCR2A COM2A1 COM2A0 COM2B1 COM2B0 - - WGM21 WGM20 158 (0xAF) Reserved - - - - - - - - (0xAE) Reserved - - - - - - - - (0xAD) Reserved - - - - - - - - (0xAC) Reserved - - - - - - - - (0xAB) Reserved - - - - - - - - (0xAA) Reserved - - - - - - - - (0xA9) Reserved - - - - - - - - (0xA8) Reserved - - - - - - - - (0xA7) Reserved - - - - - - - - (0xA6) Reserved - - - - - - - - (0xA5) Reserved - - - - - - - - Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only. 4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The Atmel ATmega48PA/88PA/168PA is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. 5. Only valid for the Atmel ATmega88A/88PA/168A/168PA/328/328P. 6. BODS and BODSE only available for picoPower devices ATmega48PA/88PA/168PA 359 9223B-AVR-09/11 31. Register Summary (Continued) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (0xA4) Reserved - - - - - - - - (0xA3) Reserved - - - - - - - - (0xA2) Reserved - - - - - - - - (0xA1) Reserved - - - - - - - - (0xA0) Reserved - - - - - - - - (0x9F) Reserved - - - - - - - - (0x9E) Reserved - - - - - - - - (0x9D) Reserved - - - - - - - - (0x9C) Reserved - - - - - - - - (0x9B) Reserved - - - - - - - - (0x9A) Reserved - - - - - - - - (0x99) Reserved - - - - - - - - (0x98) Reserved - - - - - - - - (0x97) Reserved - - - - - - - - (0x96) Reserved - - - - - - - - (0x95) Reserved - - - - - - - - (0x94) Reserved - - - - - - - - (0x93) Reserved - - - - - - - - (0x92) Reserved - - - - - - - - (0x91) Reserved - - - - - - - - (0x90) Reserved - - - - - - - - (0x8F) Reserved - - - - - - - - (0x8E) Reserved - - - - - - - - (0x8D) Reserved - - - - - - - - (0x8C) Reserved - - - - - - - - (0x8B) OCR1BH Timer/Counter1 - Output Compare Register B High Byte 137 (0x8A) OCR1BL Timer/Counter1 - Output Compare Register B Low Byte 137 (0x89) OCR1AH Timer/Counter1 - Output Compare Register A High Byte 137 (0x88) OCR1AL Timer/Counter1 - Output Compare Register A Low Byte 137 (0x87) ICR1H Timer/Counter1 - Input Capture Register High Byte 138 (0x86) ICR1L Timer/Counter1 - Input Capture Register Low Byte 138 (0x85) TCNT1H Timer/Counter1 - Counter Register High Byte 137 (0x84) TCNT1L Timer/Counter1 - Counter Register Low Byte (0x83) Reserved - - - (0x82) TCCR1C FOC1A FOC1B - - - - - - 136 (0x81) TCCR1B ICNC1 ICES1 - WGM13 WGM12 CS12 CS11 CS10 135 (0x80) TCCR1A COM1A1 COM1A0 COM1B1 COM1B0 - - WGM11 WGM10 133 (0x7F) DIDR1 - - - - - - AIN1D AIN0D 247 (0x7E) DIDR0 - - ADC5D ADC4D ADC3D ADC2D ADC1D ADC0D 266 (0x7D) Reserved - - - - - - - - (0x7C) ADMUX REFS1 REFS0 ADLAR - MUX3 MUX2 MUX1 MUX0 262 (0x7B) ADCSRB - ACME - - - ADTS2 ADTS1 ADTS0 265 (0x7A) ADCSRA ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 (0x79) ADCH (0x78) ADCL (0x77) Reserved Notes: - - 137 - - - ADC Data Register High byte - - - - 263 265 ADC Data Register Low byte - Page 265 - - - 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only. 4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The Atmel ATmega48PA/88PA/168PA is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. 5. Only valid for the Atmel ATmega88A/88PA/168A/168PA/328/328P. 6. BODS and BODSE only available for picoPower devices ATmega48PA/88PA/168PA 360 Atmel ATmega48PA/88PA/168PA [Preliminary] 9223B-AVR-09/11 Atmel ATmega48PA/88PA/168PA [Preliminary] 31. Register Summary (Continued) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (0x76) Reserved - - - - - - - - Page (0x75) Reserved - - - - - - - - (0x74) Reserved - - - - - - - - (0x73) Reserved - - - - - - - - (0x72) Reserved - - - - - - - - (0x71) Reserved - - - - - - - - (0x70) TIMSK2 - - - - - OCIE2B OCIE2A TOIE2 163 (0x6F) TIMSK1 - - ICIE1 - - OCIE1B OCIE1A TOIE1 138 (0x6E) TIMSK0 - - - - - OCIE0B OCIE0A TOIE0 109 (0x6D) PCMSK2 PCINT23 PCINT22 PCINT21 PCINT20 PCINT19 PCINT18 PCINT17 PCINT16 72 (0x6C) PCMSK1 - PCINT14 PCINT13 PCINT12 PCINT11 PCINT10 PCINT9 PCINT8 72 (0x6B) PCMSK0 PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 72 (0x6A) Reserved - - - - - - - - (0x69) EICRA - - - - ISC11 ISC10 ISC01 ISC00 (0x68) PCICR - - - - - PCIE2 PCIE1 PCIE0 - - - - - - - - 69 (0x67) Reserved (0x66) OSCCAL (0x65) Reserved - - - - - - - - (0x64) PRR PRTWI PRTIM2 PRTIM0 - PRTIM1 PRSPI PRUSART0 PRADC (0x63) Reserved - - - - - - - - (0x62) Reserved - - - - - - - - (0x61) CLKPR CLKPCE - - - CLKPS3 CLKPS2 CLKPS1 CLKPS0 37 (0x60) WDTCSR WDIF WDIE WDP3 WDCE WDE WDP2 WDP1 WDP0 56 0x3F (0x5F) SREG I T H S V N Z C 10 0x3E (0x5E) SPH - - - - - (SP10) 5. SP9 SP8 12 0x3D (0x5D) SPL SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 12 0x3C (0x5C) Reserved - - - - - - - - 0x3B (0x5B) Reserved - - - - - - - - 0x3A (0x5A) Reserved - - - - - - - - 0x39 (0x59) Reserved - - - - - - - - 0x38 (0x58) Reserved - - - - - - - - 0x37 (0x57) SPMCSR SPMIE (RWWSB)5. - (RWWSRE)5. BLBSET PGWRT PGERS SELFPRGEN 0x36 (0x56) Reserved - - - - - - - - Oscillator Calibration Register 37 42 292 0x35 (0x55) MCUCR - BODS(6) BODSE(6) PUD - - IVSEL IVCE 45/66/91 0x34 (0x54) MCUSR - - - - WDRF BORF EXTRF PORF 55 0x33 (0x53) SMCR - - - - SM2 SM1 SM0 SE 40 0x32 (0x52) Reserved - - - - - - - - 0x31 (0x51) Reserved - - - - - - - - 0x30 (0x50) ACSR ACD ACBG ACO ACI ACIE ACIC ACIS1 ACIS0 0x2F (0x4F) Reserved - - - - - - - - 0x2E (0x4E) SPDR 0x2D (0x4D) SPSR SPIF WCOL - - - - - SPI2X 174 0x2C (0x4C) SPCR SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 173 0x2B (0x4B) GPIOR2 General Purpose I/O Register 2 0x2A (0x4A) GPIOR1 General Purpose I/O Register 1 0x29 (0x49) Reserved Notes: SPI Data Register - - - - - 245 175 25 25 - - - 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only. 4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The Atmel ATmega48PA/88PA/168PA is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. 5. Only valid for the Atmel ATmega88A/88PA/168A/168PA/328/328P. 6. BODS and BODSE only available for picoPower devices ATmega48PA/88PA/168PA 361 9223B-AVR-09/11 31. Register Summary (Continued) Address Name 0x28 (0x48) OCR0B Bit 7 Bit 6 Bit 5 Timer/Counter0 Output Compare Register B Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 0x27 (0x47) OCR0A Timer/Counter0 Output Compare Register A 0x26 (0x46) TCNT0 0x25 (0x45) TCCR0B FOC0A FOC0B - - WGM02 CS02 CS01 CS00 0x24 (0x44) TCCR0A COM0A1 COM0A0 COM0B1 COM0B0 - - WGM01 WGM00 0x23 (0x43) GTCCR TSM - - - - - PSRASY PSRSYNC 0x22 (0x42) EEARH (EEPROM Address Register High Byte) 5. 21 0x21 (0x41) EEARL EEPROM Address Register Low Byte 21 0x20 (0x40) EEDR EEPROM Data Register 0x1F (0x3F) EECR 0x1E (0x3E) GPIOR0 0x1D (0x3D) EIMSK - - - - - - INT1 INT0 70 0x1C (0x3C) EIFR - - - - - - INTF1 INTF0 70 0x1B (0x3B) PCIFR - - - - - PCIF2 PCIF1 PCIF0 0x1A (0x3A) Reserved - - - - - - - - 0x19 (0x39) Reserved - - - - - - - - 0x18 (0x38) Reserved - - - - - - - - 0x17 (0x37) TIFR2 - - - - - OCF2B OCF2A TOV2 163 0x16 (0x36) TIFR1 - - ICF1 - - OCF1B OCF1A TOV1 139 0x15 (0x35) TIFR0 - - - - - OCF0B OCF0A TOV0 0x14 (0x34) Reserved - - - - - - - - 0x13 (0x33) Reserved - - - - - - - - 0x12 (0x32) Reserved - - - - - - - - 0x11 (0x31) Reserved - - - - - - - - 0x10 (0x30) Reserved - - - - - - - - 0x0F (0x2F) Reserved - - - - - - - - 0x0E (0x2E) Reserved - - - - - - - - 0x0D (0x2D) Reserved - - - - - - - - 0x0C (0x2C) Reserved - - - - - - - - 0x0B (0x2B) PORTD PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 0x0A (0x2A) DDRD DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 92 0x09 (0x29) PIND PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 92 0x08 (0x28) PORTC - PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 91 0x07 (0x27) DDRC - DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 91 Timer/Counter0 (8-bit) - - EEPM1 EEPM0 EERIE 142/165 21 EEMPE EEPE EERE General Purpose I/O Register 0 21 25 92 0x06 (0x26) PINC - PINC6 PINC5 PINC4 PINC3 PINC2 PINC1 PINC0 91 0x05 (0x25) PORTB PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 91 0x04 (0x24) DDRB DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 91 0x03 (0x23) PINB PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 91 0x02 (0x22) Reserved - - - - - - - - 0x01 (0x21) Reserved - - - - - - - - 0x0 (0x20) Reserved - - - - - - - - Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only. 4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The Atmel ATmega48PA/88PA/168PA is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. 5. Only valid for the Atmel ATmega88A/88PA/168A/168PA/328/328P. 6. BODS and BODSE only available for picoPower devices ATmega48PA/88PA/168PA 362 Atmel ATmega48PA/88PA/168PA [Preliminary] 9223B-AVR-09/11 Atmel ATmega48PA/88PA/168PA [Preliminary] 32. Instruction Set Summary Mnemonics Operands Description Operation Flags #Clocks ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers Rd Rd + Rr Z,C,N,V,H ADC Rd, Rr Add with Carry two Registers Rd Rd + Rr + C Z,C,N,V,H 1 ADIW Rdl,K Add Immediate to Word Rdh:Rdl Rdh:Rdl + K Z,C,N,V,S 2 SUB Rd, Rr Subtract two Registers Rd Rd - Rr Z,C,N,V,H 1 SUBI Rd, K Subtract Constant from Register Rd Rd - K Z,C,N,V,H 1 SBC Rd, Rr Subtract with Carry two Registers Rd Rd - Rr - C Z,C,N,V,H 1 SBCI Rd, K Subtract with Carry Constant from Reg. Rd Rd - K - C Z,C,N,V,H 1 2 1 SBIW Rdl,K Subtract Immediate from Word Rdh:Rdl Rdh:Rdl - K Z,C,N,V,S AND Rd, Rr Logical AND Registers Rd Rd * Rr Z,N,V 1 ANDI Rd, K Logical AND Register and Constant Rd Rd * K Z,N,V 1 OR Rd, Rr Logical OR Registers Rd Rd v Rr Z,N,V 1 ORI Rd, K Logical OR Register and Constant Rd Rd v K Z,N,V 1 EOR Rd, Rr Exclusive OR Registers Rd Rd Rr Z,N,V 1 COM Rd One's Complement Rd 0xFF -Rd Z,C,N,V 1 NEG Rd Two's Complement Rd 0x00 -Rd Z,C,N,V,H 1 SBR Rd,K Set Bit(s) in Register Rd Rd v K Z,N,V 1 CBR Rd,K Clear Bit(s) in Register Rd Rd * (0xFF - K) Z,N,V 1 INC Rd Increment Rd Rd + 1 Z,N,V 1 DEC Rd Decrement Rd Rd -1 Z,N,V 1 TST Rd Test for Zero or Minus Rd Rd * Rd Z,N,V 1 CLR Rd Clear Register Rd Rd Rd Z,N,V 1 SER Rd Set Register Rd 0xFF None 1 MUL Rd, Rr Multiply Unsigned R1:R0 Rd x Rr Z,C 2 MULS Rd, Rr Multiply Signed R1:R0 Rd x Rr Z,C 2 MULSU Rd, Rr Multiply Signed with Unsigned R1:R0 Rd x Rr Z,C 2 FMUL Rd, Rr Fractional Multiply Unsigned R1:R0 (Rd x Rr) << Z,C 2 Z,C 2 Z,C 2 FMULS Rd, Rr Fractional Multiply Signed FMULSU Rd, Rr Fractional Multiply Signed with Unsigned 1 R1:R0 (Rd x Rr) << 1 R1:R0 (Rd x Rr) << 1 BRANCH INSTRUCTIONS RJMP k IJMP Relative Jump PC PC + k + 1 None 2 Indirect Jump to (Z) PC Z None 2 JMP(1) k Direct Jump PC k None 3 RCALL k Relative Subroutine Call PC PC + k + 1 None 3 Indirect Call to (Z) PC Z None 3 k Direct Subroutine Call PC k None 4 RET Subroutine Return PC STACK None 4 RETI Interrupt Return PC STACK I Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC PC + 2 or 3 None CP Rd,Rr Compare Rd -Rr Z, N,V,C,H 1 CPC Rd,Rr Compare with Carry Rd -Rr -C Z, N,V,C,H 1 CPI Rd,K Compare Register with Immediate Rd -K Z, N,V,C,H SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b)=0) PC PC + 2 or 3 None ICALL CALL(1) CPSE 4 1/2/3 1 1/2/3 SBRS Rr, b Skip if Bit in Register is Set if (Rr(b)=1) PC PC + 2 or 3 None 1/2/3 SBIC P, b Skip if Bit in I/O Register Cleared if (P(b)=0) PC PC + 2 or 3 None 1/2/3 SBIS P, b Skip if Bit in I/O Register is Set if (P(b)=1) PC PC + 2 or 3 None 1/2/3 BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PCPC+k + 1 None 1/2 BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PCPC+k + 1 None 1/2 BREQ k Branch if Equal if (Z = 1) then PC PC + k + 1 None 1/2 BRNE k Branch if Not Equal if (Z = 0) then PC PC + k + 1 None 1/2 BRCS k Branch if Carry Set if (C = 1) then PC PC + k + 1 None 1/2 BRCC k Branch if Carry Cleared if (C = 0) then PC PC + k + 1 None 1/2 BRSH k Branch if Same or Higher if (C = 0) then PC PC + k + 1 None 1/2 BRLO k Branch if Lower if (C = 1) then PC PC + k + 1 None 1/2 BRMI k Branch if Minus if (N = 1) then PC PC + k + 1 None 1/2 BRPL k Branch if Plus if (N = 0) then PC PC + k + 1 None 1/2 BRGE k Branch if Greater or Equal, Signed if (N V= 0) then PC PC + k + 1 None 1/2 BRLT k Branch if Less Than Zero, Signed if (N V= 1) then PC PC + k + 1 None 1/2 BRHS k Branch if Half Carry Flag Set if (H = 1) then PC PC + k + 1 None 1/2 BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC PC + k + 1 None 1/2 BRTS k Branch if T Flag Set if (T = 1) then PC PC + k + 1 None 1/2 BRTC k Branch if T Flag Cleared if (T = 0) then PC PC + k + 1 None 1/2 Note: 1. These instructions are only available in the Atmel ATmega168PA. 363 9223B-AVR-09/11 32. Instruction Set Summary (Continued) Mnemonics Operands Description Operation Flags #Clocks BRVS k Branch if Overflow Flag is Set if (V = 1) then PC PC + k + 1 None 1/2 BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC PC + k + 1 None 1/2 BRIE k Branch if Interrupt Enabled if ( I = 1) then PC PC + k + 1 None 1/2 BRID k Branch if Interrupt Disabled if ( I = 0) then PC PC + k + 1 None 1/2 BIT AND BIT-TEST INSTRUCTIONS SBI P,b Set Bit in I/O Register I/O(P,b) 1 None 2 CBI P,b Clear Bit in I/O Register I/O(P,b) 0 None 2 LSL Rd Logical Shift Left Rd(n+1) Rd(n), Rd(0) 0 Z,C,N,V 1 LSR Rd Logical Shift Right Rd(n) Rd(n+1), Rd(7) 0 Z,C,N,V 1 ROL Rd Rotate Left Through Carry Rd(0)C,Rd(n+1)Rd(n),CRd(7) Z,C,N,V 1 ROR Rd Rotate Right Through Carry Rd(7)C,Rd(n)Rd(n+1),CRd(0) Z,C,N,V 1 ASR Rd Arithmetic Shift Right Rd(n) Rd(n+1), n=0...6 Z,C,N,V 1 SWAP Rd Swap Nibbles Rd(3...0)Rd(7...4),Rd(7...4)Rd(3...0) None 1 BSET s Flag Set SREG(s) 1 SREG(s) 1 BCLR s Flag Clear SREG(s) 0 SREG(s) 1 BST Rr, b Bit Store from Register to T T Rr(b) T 1 BLD Rd, b Bit load from T to Register Rd(b) T None 1 SEC Set Carry C 1 C 1 CLC Clear Carry C 0 C 1 SEN Set Negative Flag N 1 N 1 CLN Clear Negative Flag N 0 N 1 SEZ Set Zero Flag Z 1 Z 1 CLZ Clear Zero Flag Z 0 Z 1 SEI Global Interrupt Enable I 1 I 1 CLI Global Interrupt Disable I 0 I 1 SES Set Signed Test Flag S 1 S 1 CLS Clear Signed Test Flag S 0 S 1 SEV Set Twos Complement Overflow. V 1 V 1 CLV Clear Twos Complement Overflow V 0 V 1 SET Set T in SREG T 1 T 1 CLT Clear T in SREG T 0 T 1 SEH CLH Set Half Carry Flag in SREG Clear Half Carry Flag in SREG H 1 H 0 H H 1 1 Rd Rr Rd+1:Rd Rr+1:Rr None 1 None 1 DATA TRANSFER INSTRUCTIONS MOV Rd, Rr Move Between Registers MOVW Rd, Rr Copy Register Word LDI Rd, K Load Immediate Rd K None 1 LD Rd, X Load Indirect Rd (X) None 2 LD Rd, X+ Load Indirect and Post-Inc. Rd (X), X X + 1 None 2 LD Rd, - X Load Indirect and Pre-Dec. X X - 1, Rd (X) None 2 LD Rd, Y Load Indirect Rd (Y) None 2 LD Rd, Y+ Load Indirect and Post-Inc. Rd (Y), Y Y + 1 None 2 LD Rd, - Y Load Indirect and Pre-Dec. Y Y - 1, Rd (Y) None 2 LDD Rd,Y+q Load Indirect with Displacement Rd (Y + q) None 2 LD Rd, Z Load Indirect Rd (Z) None 2 LD Rd, Z+ Load Indirect and Post-Inc. Rd (Z), Z Z+1 None 2 LD Rd, -Z Load Indirect and Pre-Dec. Z Z - 1, Rd (Z) None 2 LDD Rd, Z+q Load Indirect with Displacement Rd (Z + q) None 2 LDS Rd, k Load Direct from SRAM Rd (k) None 2 ST X, Rr Store Indirect (X) Rr None 2 ST X+, Rr Store Indirect and Post-Inc. (X) Rr, X X + 1 None 2 ST - X, Rr Store Indirect and Pre-Dec. X X - 1, (X) Rr None 2 ST Y, Rr Store Indirect (Y) Rr None 2 ST Y+, Rr Store Indirect and Post-Inc. (Y) Rr, Y Y + 1 None 2 ST - Y, Rr Store Indirect and Pre-Dec. Y Y - 1, (Y) Rr None 2 STD Y+q,Rr Store Indirect with Displacement (Y + q) Rr None 2 ST Z, Rr Store Indirect (Z) Rr None 2 ST Z+, Rr Store Indirect and Post-Inc. (Z) Rr, Z Z + 1 None 2 ST -Z, Rr Store Indirect and Pre-Dec. Z Z - 1, (Z) Rr None 2 2 STD Z+q,Rr Store Indirect with Displacement (Z + q) Rr None STS k, Rr Store Direct to SRAM (k) Rr None 2 Load Program Memory R0 (Z) None 3 Load Program Memory Rd (Z) None 3 LPM LPM Note: 364 Rd, Z 1. These instructions are only available in the Atmel ATmega168PA. Atmel ATmega48PA/88PA/168PA [Preliminary] 9223B-AVR-09/11 Atmel ATmega48PA/88PA/168PA [Preliminary] 32. Instruction Set Summary (Continued) Mnemonics LPM Operands Rd, Z+ SPM IN Rd, P Description Operation Flags #Clocks Load Program Memory and Post-Inc Rd (Z), Z Z+1 None Store Program Memory (Z) R1:R0 None - In Port Rd P None 1 1 3 OUT P, Rr Out Port P Rr None PUSH Rr Push Register on Stack STACK Rr None 2 POP Rd Pop Register from Stack Rd STACK None 2 MCU CONTROL INSTRUCTIONS NOP No Operation None 1 SLEEP Sleep (see specific descr. for Sleep function) None 1 WDR BREAK Watchdog Reset Break (see specific descr. for WDR/timer) For On-chip Debug Only None None 1 N/A Note: 1. These instructions are only available in the Atmel ATmega168PA. 365 9223B-AVR-09/11 33. Ordering Information 33.1 ATmega48PA/88PA/168PA Speed (MHz) 16(2) Notes: Power Supply (V) 1.8 - 5.5 Ordering Code Package(1) ATmega48PA-15AZ ATmega48PA-15MZ MA PN ATmega88PA-15AZ ATmega88PA-15MZ MA PN ATmega168PA-15AZ ATmega168PA-15MZ MA PN Operational Range Automotive (-40C to 125C) 1. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive).Also Halide free and fully Green. 2. See "Speed Grades" on page 316. Package Type 366 MA MA, 32 - Lead, 7x7 mm Body Size, 1.0 mm Body Thickness 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) PN PN, 32-Lead, 5.0x5.0 mm Body, 0.50 mm, Quad Flat No Lead Package (QFN) Atmel ATmega48PA/88PA/168PA [Preliminary] 9223B-AVR-09/11 Atmel ATmega48PA/88PA/168PA [Preliminary] 34. Packaging Information 34.1 MA 367 9223B-AVR-09/11 34.2 368 PN Atmel ATmega48PA/88PA/168PA [Preliminary] 9223B-AVR-09/11 Atmel ATmega48PA/88PA/168PA [Preliminary] 35. Errata 35.1 Errata ATmega48PA The revision letter in this section refers to the revision of the ATmega48PA/88PA/168PA device. 35.1.1 Rev. D * Analog MUX can be turned off when setting ACME bit 1. Analog MUX can be turned off when setting ACME bit If the ACME (Analog Comparator Multiplexer Enabled) bit in ADCSRB is set while MUX3 in ADMUX is '1' (ADMUX[3:0]=1xxx), all MUX'es are turned off until the ACME bit is cleared. Problem Fix/Workaround Clear the MUX3 bit before setting the ACME bit. 35.2 Errata Atmel ATmega88PA The revision letter in this section refers to the revision of the Atmel ATmega88PA device. 35.2.1 Rev. F * Analog MUX can be turned off when setting ACME bit 1. Analog MUX can be turned off when setting ACME bit If the ACME (Analog Comparator Multiplexer Enabled) bit in ADCSRB is set while MUX3 in ADMUX is '1' (ADMUX[3:0]=1xxx), all MUX'es are turned off until the ACME bit is cleared. Problem Fix/Workaround Clear the MUX3 bit before setting the ACME bit. 35.3 Errata Atmel ATmega168PA The revision letter in this section refers to the revision of the Atmel ATmega168PA device. 35.3.1 Rev E * Analog MUX can be turned off when setting ACME bit 1. Analog MUX can be turned off when setting ACME bit If the ACME (Analog Comparator Multiplexer Enabled) bit in ADCSRB is set while MUX3 in ADMUX is '1' (ADMUX[3:0]=1xxx), all MUX'es are turned off until the ACME bit is cleared. Problem Fix/Workaround Clear the MUX3 bit before setting the ACME bit. 369 9223B-AVR-09/11 36. Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 36.1 Rev. 9223B - 09/11 * ADC characteristics updated * Temperature sensor updated 36.2 Rev. 9223A - 08/11 * Creation of the automotive version starting from industrial version based on the Atmel ATmega48A/48PA/88A/88PA/168A/168PA/328P datasheet 8271C-AVR-08/10. Temperature and voltage ranges reflecting Automotive requirements. 370 Atmel ATmega48PA/88PA/168PA [Preliminary] 9223B-AVR-09/11 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: (+1)(408) 441-0311 Fax: (+1)(408) 487-2600 Atmel Asia Limited Unit 01-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon HONG KONG Tel: (+852) 2245-6100 Fax: (+852) 2722-1369 Atmel Munich GmbH Business Campus Parkring 4 D-85748 Garching b. Munich GERMANY Tel: (+49) 89-31970-0 Fax: (+49) 89-3194621 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 JAPAN Tel: (+81) (3) 3523-3551 Fax: (+81) (3) 3523-7581 (c) 2011 Atmel Corporation. All rights reserved. / Rev.: 9223B-AVR-09/11 Atmel(R), Atmel logo and combinations thereof, AVR (R), AVR (R) logo, AVR Studio (R) and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. 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