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Data Sheet

Revision 3.0, 2010-12-28

TDA 5200

ASK Single Conversion Receiver

Version 3.0

Edition 2010-12-28

Published by

Infineon Technologies AG

81726 Munich, Germany

Legal Disclaimer

The information given in this document shall in no event be regarded as a guarantee of conditions or

characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any

information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties

and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights

of any third party.

Information

For further information on technology, delivery terms and conditions and prices, please contact the nearest

Infineon Technologies Office (www.infineon.com).

Warnings

Due to technical requirements, components may contain dangerous substances. For information on the types in

question, please contact the nearest Infineon Technologies Office.

Infineon Technologies components may be used in life-support devices or systems only with the express written

approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure

of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support

devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain

and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may

be endangered.

TDA 5200

ASK Single Conversion Receiver

Data Sheet 3 Revision 3.0, 2010-12-28

Trademarks of Infineon Technologies AG

AURIX™, BlueMoon™, C166™, CanPAK™, CIPOS™, CIPURSE™, COMNEON™, EconoPACK™, CoolMOS™,

CoolSET™, CORECONTROL™, CROSSAVE™, DAVE™, EasyPIM™, EconoBRIDGE™, EconoDUAL™,

EconoPIM™, EiceDRIVER™, eupec™, FCOS™, HITFET™, HybridPACK™, I²RF™, ISOFACE™, IsoPACK™,

MIPAQ™, ModSTACK™, my-d™, NovalithIC™, OmniTune™, OptiMOS™, ORIGA™, PRIMARION™,

PrimePACK™, PrimeSTACK™, PRO-SIL™, PROFET™, RASIC™, ReverSave™, SatRIC™, SIEGET™,

SINDRION™, SIPMOS™, SMARTi™, SmartLEWIS™, SOLID FLASH™, TEMPFET™, thinQ!™,

TRENCHSTOP™, TriCore™, X-GOLD™, X-PMU™, XMM™, XPOSYS™.

Other Trademarks

Advance Design System™ (ADS) of Agilent Technologies, AMBA™, ARM™, MULTI-ICE™, KEIL™,

PRIMECELL™, REALVIEW™, THUMB™, µVision™ of ARM Limited, UK. AUTOSAR™ is licensed by AUTOSAR

development partnership. Bluetooth™ of Bluetooth SIG Inc. CAT-iq™ of DECT Forum. COLOSSUS™,

FirstGPS™ of Trimble Navigation Ltd. EMV™ of EMVCo, LLC (Visa Holdings Inc.). EPCOS™ of Epcos AG.

FLEXGO™ of Microsoft Corporation. FlexRay™ is licensed by FlexRay Consortium. HYPERTERMINAL™ of

Hilgraeve Incorporated. IEC™ of Commission Electrotechnique Internationale. IrDA™ of Infrared Data

Association Corporation. ISO™ of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB™ of

MathWorks, Inc. MAXIM™ of Maxim Integrated Products, Inc. MICROTEC™, NUCLEUS™ of Mentor Graphics

Corporation. Mifare™ of NXP. MIPI™ of MIPI Alliance, Inc. MIPS™ of MIPS Technologies, Inc., USA. muRata™

of MURATA MANUFACTURING CO., MICROWAVE OFFICE™ (MWO) of Applied Wave Research Inc.,

OmniVision™ of OmniVision Technologies, Inc. Openwave™ Openwave Systems Inc. RED HAT™ Red Hat, Inc.

RFMD™ RF Micro Devices, Inc. SIRIUS™ of Sirius Satellite Radio Inc. SOLARIS™ of Sun Microsystems, Inc.

SPANSION™ of Spansion LLC Ltd. Symbian™ of Symbian Software Limited. TAIYO YUDEN™ of Taiyo Yuden

Co. TEAKLITE™ of CEVA, Inc. TEKTRONIX™ of Tektronix Inc. TOKO™ of TOKO KABUSHIKI KAISHA TA.

UNIX™ of X/Open Company Limited. VERILOG™, PALLADIUM™ of Cadence Design Systems, Inc. VLYNQ™

of Texas Instruments Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of

Diodes Zetex Limited.

Last Trademarks Update 2010-10-26

Revision History

Page or Item Subjects (major changes since previous revision)

Previous Revision: 2.9

Revision 3.0, 2010-12-28

all Converted into structured FrameMaker (EDD 3.4)

4-3 More detailed explanation of AGC

5-6, 5-8 More detailed information of LNA high gain mode and LNA low gain mode

TDA 5200
ASK Single Conversion Receiver
Table of Contents
 Data Sheet 4 Revision 3.0, 2010-12-28
   
  
Table of Contents  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
List of Figures  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  5
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  6
1Product Info . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  7
Product Description  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  8
1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  8
2 Application   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  8
3 Features  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  8
4 Package Outlines  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  9
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  10
1 Pin Configuration   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  10
2 Pin Definition and Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  11
3 Functional Block Diagram  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  18
4 Functional Blocks  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  19
4.1 Low Noise Amplifier (LNA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  19
4.2 Mixer   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  19
4.3 PLL Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  19
4.4 Crystal Oscillator  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  20
4.5 Limiter   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  20
4.6 Data Filter   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  20
4.7 Data Slicer  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  20
4.8 Peak Detector   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  20
4.9 Bandgap Reference Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  20
Applications   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  22
1 Choice of LNA Threshold Voltage and Time Constant  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  22
2 Data Filter Design  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  24
3 Quartz Load Capacitance Calculation   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  25
4 Quartz Frequency Calculation   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  26
5 Data Slicer Threshold Generation   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  27
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  28
1 Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  28
1.1 Absolute Maximum Ratings  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  28
1.2 Operating Range  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  29
1.3 AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  30
2 Test Board   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  34
2.1 Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  34
2.2 Test Board Layouts  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  35
2.3 Bill of Materials   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  37
Table of Contents

TDA 5200
ASK Single Conversion Receiver
List of Figures
 Data Sheet 5 Revision 3.0, 2010-12-28
   
  
Figure 1 PG-TSSOP-28  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  7
Figure 2 PG-TSSOP-28 Package Outlines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  9
Figure 3 IC Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  10
Figure 4 Main Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  18
Figure 5 LNA Automatic Gain Control Circuitry  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  22
Figure 6 Typical Curve of RSSI Level and Permissive AGC Threshold Levels  . . . . . . . . . . . . . . . . . . . . . .  23
Figure 7 Data Filter Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  24
Figure 8 Determination of Series Capacitance Value for the Quartz Oscillator  . . . . . . . . . . . . . . . . . . . . . .  25
Figure 9 Data Slicer Threshold Generation with External R-C Integrator . . . . . . . . . . . . . . . . . . . . . . . . . . .  27
Figure 10 Data Slicer Threshold Generation Utilizing the Peak Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . .  27
Figure 11 Schematic of the Evaluation Board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  34
Figure 12 Top Side of the Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  35
Figure 13 Bottom Side of the Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  35
Figure 14 Component Placement on the Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  36
List of Figures

TDA 5200

ASK Single Conversion Receiver

List of Tables

Data Sheet 6 Revision 3.0, 2010-12-28

Table 1 Pin Definition and Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 2 FSEL Pin Operating States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 3 CSEL Pin Operating States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 4 PDWN Pin Operating States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 5 PLL Division Ratio Dependence on States of CSEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 6 Absolute Maximum Ratings, Ambient Temperature TAMB = - 40 °C ... + 85 °C . . . . . . . . . . . . . . . 28

Table 7 Operating Range, Ambient Temperature TAMB = - 40 °C ... + 85 °C . . . . . . . . . . . . . . . . . . . . . . . 29

Table 8 AC/DC Characteristics with TAMB = 25 °C, VCC = 4.5 ... 5.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 9 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 10 Bill of Materials Addendum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

List of Tables

TDA 5200

ASK Single Conversion Receiver

Product Info

Data Sheet 7 Revision 3.0, 2010-12-28

1 Product Info

General Description

The IC is a very low power consumption single chip ASK Single Conversion Receiver for receive frequencies

bands 868-870 MHz and 433-435 MHz. The IC offers a high level of integration and needs only a few external

components. The device contains a low noise amplifier (LNA), a double balanced mixer, a fully integrated VCO, a

PLL synthesizer, a crystal oscillator, a limiter with RSSI generator, a data filter, a data comparator (slicer) and a

peak detector. Additionally there is a power down feature to save battery life.

Features

• Low supply current (Is = 4.8 mA typ. at 868 MHz, Is = 4.6 mA typ. at 434 MHz)

• Supply voltage range 5 V ±10 %

• Power down mode with very low supply current (50 nA typ)

• Fully integrated VCO and PLL Synthesizer

• RF input sensitivity < – 107 dBm

• Selectable frequency ranges around 868-870 MHz and 433-435 MHz

• Selectable reference frequency

• Limiter with RSSI generation, operating at 10.7 MHz

•2

nd order low pass data filter with external capacitors

• Data slicer with self-adjusting threshold

Application

• Keyless Entry Systems

• Remote Control Systems

• Alarm Systems

• Low Bitrate Communication Systems

Package

Figure 1 PG-TSSOP-28

Ordering Information

Type Ordering Code Package1)

1) Available on tape and reel

TDA5200 SP000016381 PG-TSSOP-28

TDA 5200

ASK Single Conversion Receiver

Product Description

Data Sheet 8 Revision 3.0, 2010-12-28

2 Product Description

2.1 Overview

The IC is a very low power consumption single chip ASK Superheterodyne Receiver (SHR) for the frequency

bands 868-870 MHz and 433-435 MHz. The IC offers a high level of integration and needs only a few external

components. The device contains a low noise amplifier (LNA), a double balanced mixer, a fully integrated VCO, a

PLL synthesizer, a crystal oscillator, a limiter with RSSI generator, a data filter, a data comparator (slicer) and a

peak detector. Additionally there is a power down feature to save battery life.

2.2 Application

• Keyless Entry Systems

• Remote Control Systems

• Alarm Systems

• Low Bitrate Communication Systems

2.3 Features

• Low supply current (Is = 4.8 mA typ. at 868 MHz, Is = 4.6 mA typ. at 434 MHz)

• Supply voltage range 5 V ±10 %

• Power down mode with very low supply current (100 nA typ.)

• Fully integrated VCO and PLL Synthesizer

• RF input sensitivity < – 107 dBm

• Selectable receive frequency bands 868-870 MHz and 433-435 MHz

• Selectable reference frequency

• Limiter with RSSI generation, operating at 10.7 MHz

•2

nd order low pass data filter with external capacitors

• Data slicer with self-adjusting threshold

TDA 5200

ASK Single Conversion Receiver

Product Description

Data Sheet 9 Revision 3.0, 2010-12-28

2.4 Package Outlines

Figure 2 PG-TSSOP-28 Package Outlines

TDA 5200

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Functional Description

Data Sheet 10 Revision 3.0, 2010-12-28

3 Functional Description

3.1 Pin Configuration

Figure 3 IC Pin Configuration

CRST2

PDWN

PDO

DATA

3VOUT

THRES

FFB

OPP

SLN

SLP

LIMX

LIM

CSEL

CRST1

VCC

LNI

TAGC

AGND

LNO

VCC

MIX

AGND

FSEL

IFO

DGND

VDD

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Functional Description

Data Sheet 11 Revision 3.0, 2010-12-28

3.2 Pin Definition and Function

Table 1 Pin Definition and Function

No.

Name Pin

Type

Buffer Type Function

1 CRST1 In/Out External Crystal Connector 1

2VCC In 5 V Supply

3LNI In LNA Input

4.15V

50uA

57uA

500uA

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Functional Description

Data Sheet 12 Revision 3.0, 2010-12-28

4TAGCIn/Out AGC Time Constant Control

5AGNDIn Analogue Ground Return

6LNO Out LNA Output

7VCC In 5 V Supply

8MI In Mixer Input

Table 1 Pin Definition and Function (cont’d)

No.

Name Pin

Type

Buffer Type Function

4.2uA

1.5uA

1.7V

4.3V

1.7V

400uA

2k 2k

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Functional Description

Data Sheet 13 Revision 3.0, 2010-12-28

9 MIX In Complementary Mixer Input

10 AGND In Analogue Ground Return

11 FSEL In Operating Frequency

Selector

869/434 MHz

12 IFO Out IF Mixer Output

10.7 MHz

13 DGND In Digital Ground Return

14 VDD In 5 V Supply

PLL Counter Circuitry

Table 1 Pin Definition and Function (cont’d)

No.

Name Pin

Type

Buffer Type Function

1.7V

400uA

2k 2k

750

1.2V

2.2V

4.5k

300uA

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Functional Description

Data Sheet 14 Revision 3.0, 2010-12-28

15 LF In/Out PLL Filter Access Point

16 CSEL In Quartz Selector

6.xx MHz or 13.xx MHz

17 LIM In Limiter Input

Table 1 Pin Definition and Function (cont’d)

No.

Name Pin

Type

Buffer Type Function

200

30uA

4.6V

2.4V

100

1.2V

80k

330

15k

2.4V

75uA

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Functional Description

Data Sheet 15 Revision 3.0, 2010-12-28

18 LIMX In Complementary Limiter Input

19 SLP In Data Slicer Positive Input

20 SLN In Data Slicer Negative Input

21 OPP In OpAmp Noninverting Input

Table 1 Pin Definition and Function (cont’d)

No.

Name Pin

Type

Buffer Type Function

330

15k

2.4V

75uA

40uA

15uA

100

5uA

10k

200

5uA

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Functional Description

Data Sheet 16 Revision 3.0, 2010-12-28

22 FFB In Data Filter Feedback Pin

23 THRES In AGC Threshold Input

24 3VOUT Out 3 V Reference Output

25 DATA Out Data Output

26 PDO Out Peak Detector Output

Table 1 Pin Definition and Function (cont’d)

No.

Name Pin

Type

Buffer Type Function

100k

5uA

10k

5uA

200

80k

200

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Functional Description

Data Sheet 17 Revision 3.0, 2010-12-28

27 PDWN In Power Down Input

28 CRST2 In/Out External Crystal Connector 2

Table 1 Pin Definition and Function (cont’d)

No.

Name Pin

Type

Buffer Type Function

220k

4.15V

50uA

TDA 5200

ASK Single Conversion Receiver

Functional Description

Data Sheet 18 Revision 3.0, 2010-12-28

3.3 Functional Block Diagram

Figure 4 Main Block Diagram

Filter

VDD

VCC

LNO MI MIX IFO LIM LIMX FFB OPP SLP SLN

DATA

PDO

SLICERRSSI

THRES

LNA

TAGC

DGND

VCC AGND FSEL CSEL PDWN

Crystal

Loop

Filter

Bandgap

Reference

UREF

TDA 5200 AGC

Reference

3VOUT

2/7 5/10 11 15

16 1 28 27

201921

181712

Crystal

OSC

DET

: 128/64VCO: 1/2

TDA 5200

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Functional Description

Data Sheet 19 Revision 3.0, 2010-12-28

3.4 Functional Blocks

3.4.1 Low Noise Amplifier (LNA)

The LNA is an on-chip cascode amplifier with a voltage gain of 15 dB to 20 dB. The gain figure is determined by

the external matching networks situated ahead of LNA and between the LNA output LNO (Pin 6) and the Mixer

Inputs MI and MIX (Pin 8 and Pin 9). The noise figure of the LNA is approximately 3.2 dB, the current consumption

is 500 µA. The gain can be reduced by approximately 18 dB. The switching point of this AGC action can be

determined externally by applying a threshold voltage at the THRES pin (Pin 23). This voltage is compared

internally with the received signal (RSSI) level generated by the limiter circuitry. In case that the RSSI level is

higher than the threshold voltage the LNA gain is reduced and vice versa. The threshold voltage can be generated

by attaching a voltage divider between the 3VOUT pin (Pin 24) which provides a temperature stable 3 V output

generated from the internal bandgap voltage and the THRES pin as described in Chapter 4.1. The time constant

of the AGC action can be determined by connecting a capacitor to the TAGC pin (Pin 4) and should be chosen

along with the appropriate threshold voltage according to the intended operating case and interference scenario

to be expected during operation. The optimum choice of AGC time constant and the threshold voltage is described

in Chapter 4.1.

3.4.2 Mixer

The Double Balanced Mixer down-converts the input frequency (RF) in the range of 433-435 MHz / 868-870 MHz

to the intermediate frequency (IF) at 10.7 MHz with a voltage gain of approximately 21 dB. A low pass filter with a

corner frequency of 20 MHz is built on chip in order to suppress RF signals to appear at the IF output (IFO pin).

The IF output is internally consisting of an emitter follower that has a source impedance of approximately 330 Ω

to facilitate interfacing the pin directly to a standard 10.7 MHz ceramic filter without additional matching circuitry.

3.4.3 PLL Synthesizer

The Phase Locked Loop synthesizer consists of a VCO, an asynchronous divider chain, a phase detector with

charge pump and a loop filter and is fully implemented on-chip. The VCO is including spiral inductors and varactor

diodes. It’s nominal centre frequency is 840 MHz. No additional components are necessary.

Local oscillator high side injection has to be used for receive frequencies below approximately 420 MHz or

840 MHz, low side injection for receive frequencies above approximately 420 MHz or 840 MHz - see also

Chapter 4.4. Therefore low-side injection of the local oscillator has to be used for operation both in the 868 MHz

and the 434 MHz ISM bands.

The oscillator signal is fed both to the synthesizer divider chain and to the down-converting mixer. In case of

operation in the 433-435 MHz range, the signal is divided by two before it is fed to the mixer. This is controlled by

the selection pin FSEL (Pin 11) as described in the following table. The overall division ratio of the divider chain

can be selected to be either 128 or 64, depending on the frequency of the reference oscillator quartz (see below).

The loop filter is also realized fully on-chip.

Table 2 FSEL Pin Operating States

FSEL RF Frequency

Open 433-435 MHz

Shorted to ground 868-870 MHz

TDA 5200

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Functional Description

Data Sheet 20 Revision 3.0, 2010-12-28

3.4.4 Crystal Oscillator

The on-chip crystal oscillator circuitry allows for utilization of quartzes both in the 6 MHz and 13 MHz range as the

overall division ratio of the PLL can be switched between 64 and 128 via the CSEL (Pin 16) pin according to the

following table.

The calculation of the value of the necessary quartz load capacitance is shown in Chapter 4.3, the quartz

frequency calculation is explained in Chapter 4.4.

3.4.5 Limiter

The Limiter is an AC coupled multistage amplifier with a cumulative gain of approximately 80 dB that has a

bandpass-characteristic centered around 10.7 MHz. It has an input impedance of 330 Ω to allow for easy

interfacing to a 10.7 MHz ceramic IF filter. The limiter circuit acts as a Receive Signal Strength Indicator (RSSI)

generator which produces a DC voltage that is directly proportional to the input signal level as can be seen in

Figure 6. This signal is used to demodulate the ASK receive signal in the subsequent baseband circuitry and to

turn down the LNA gain by approximately 17 dB in case the input signal strength is too strong as described in

Chapter 3.4.1 and Chapter 4.1.

3.4.6 Data Filter

The data filter comprises an OP-Amp with a bandwidth of 100 kHz used as a voltage follower and two 100 kΩ on-

chip resistors. Along with two external capacitors a 2nd order Sallen-Key low pass filter is formed. The selection of

the capacitor values is described in Chapter 4.2.

3.4.7 Data Slicer

The data slicer is a fast comparator with a bandwidth of 100 kHz. This allows for a maximum receive data rate of

approximately 120 kBaud. The maximum achievable data rate also depends on the IF Filter bandwidth and the

local oscillator tolerance values. Both inputs are accessible. The output delivers a digital data signal (CMOS-like

levels) for the detector. The self-adjusting threshold on pin 20 is generated by RC-term or peak detector

depending on the baseband coding scheme. The data slicer threshold generation alternatives are described in

more detail in Chapter 4.5.

3.4.8 Peak Detector

The peak detector generates a DC voltage which is proportional to the peak value of the receive data signal. An

external RC network is necessary. The output can be used as an indicator for the signal strength and also as a

reference for the data slicer. The maximum output current is 500 µA.

3.4.9 Bandgap Reference Circuitry

A Bandgap Reference Circuit provides a temperature stable reference voltage for the device. A power down mode

is available to switch off all sub-circuits which is controlled by the PWDN pin (Pin 27) as shown in the following

table. The supply current drawn in this case is typically 50 nA.

Table 3 CSEL Pin Operating States

CSEL Crystal Frequency

Open 6.xx MHz

Shorted to ground 13.xx MHz

TDA 5200

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Functional Description

Data Sheet 21 Revision 3.0, 2010-12-28

Table 4 PDWN Pin Operating States

PDWN Operating State

Open or tied to ground Power Down Mode

Tied to VCC Receiver On

TDA 5200

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Applications

Data Sheet 22 Revision 3.0, 2010-12-28

4 Applications

4.1 Choice of LNA Threshold Voltage and Time Constant

In the following figure the internal circuitry of the LNA automatic gain control is shown.

Figure 5 LNA Automatic Gain Control Circuitry

The LNA automatic gain control circuitry consists of an operational transimpedance amplifier that is used to

compare the received signal strength signal (RSSI) generated by the Limiter with an externally provided threshold

voltage Uthres. As shown in the following figure the threshold voltage can have any value between approximately

typically 0.8 V and 2.8 V to provide a switching point within the receive signal dynamic range.

This voltage Uthres is applied to the THRES pin (Pin 23). The threshold voltage can be generated by attaching a

voltage divider between the 3VOUT pin (Pin 24) which provides a temperature stable 3 V output generated from

the internal bandgap voltage and the THRES pin. If the RSSI level generated by the Limiter is higher than Uthres,

the OTA generates a positive current Iload. This yields a voltage rise on the TAGC pin (Pin 4). Otherwise, the OTA

generates a negative current. These currents do not have the same values in order to achieve a fast-attack and

slow-release action of the AGC and are used to charge an external capacitor which finally generates the LNA gain

control voltage.

Pins: 24 23

LNA

R4 R5

Uthreshold

RSSI (0.8 - 2.8V)

VCC

Gain control

voltage

OTA

+3V

Iload

RSSI > Uthreshold: Iload=4.2µA

RSSI < Uthreshold: Iload= -1.5µA

Uc:< 2.6V : Gain high

Uc:> 2.6V : Gain low

Ucmax= VCC -0.7V

Ucmin = 1.67V

TDA 5200

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Applications

Data Sheet 23 Revision 3.0, 2010-12-28

Figure 6 Typical Curve of RSSI Level and Permissive AGC Threshold Levels

The switching point should be chosen according to the intended operating scenario. The determination of the

optimum point is described in the accompanying Application Note, a threshold voltage level of 1.8 V is apparently

a viable choice. It should be noted that the output of the 3VOUT pin is capable of driving up to 50 µA, but that the

THRES pin input current is only in the region of 40 nA. As the current drawn out of the 3VOUT pin is directly related

to the receiver power consumption, the power divider resistors should have high impedance values. R4 can be

chosen as 120 kΩ, R5 as 180 kΩ to yield an overall 3VOUT output current of 10 µA.

Notes

1. To keep the LNA in high gain mode for the complete RF-input level range a voltage equal or higher than 3.3 V

has to be applied at pin 23. Alternatively, pin 23 has to be connected to pin 24 and pin 4 has to be connected

to GND. In addition this would save an external capacitor.

2. To keep the LNA in low gain mode for the complete RF-input level range a voltage lower than 0.7 V has to be

applied to the THRES pin (e.g. THRES connected to GND). In the above-mentioned mode pin 4 has to be

connected by a capacitor to GND.

3. As stated above, the gain control voltage of the LNA is generated at the capacitor connected to the TAGC pin

by the charging and discharging currents of the OTA. Consequently this capacitor is responsible for the AGC

time constant. As the charging and discharging currents are not equal two different time constants will result.

The time constant corresponding to the charging process of the capacitor shall be chosen according to the

data rate. According to measurements performed at Infineon the capacitor value should be greater than 47 nF.

LNA always

in high gain mode

0.5

1.5

2.5

-120 -110 -100 -90 -80 -70 -60 -50 -40 -30

Input Level at LNA Input [dBm]

UTHRES Voltage Range

RSSI Level Range LNA always

in low gain mode

RSSI Level

TDA 5200

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Applications

Data Sheet 24 Revision 3.0, 2010-12-28

4.2 Data Filter Design

Utilizing the on-board voltage follower and the two 100 kΩ on-chip resistors a 2nd order Sallen-Key low pass data

filter can be constructed by adding 2 external capacitors between pin 19 (SLP) and pin 22 (FFB) and to pin 21

(OPP) as depicted in the following figure and described in the following formulas1).

Figure 7 Data Filter Design

(1)

(2)

with

(3)

1) Taken from Tietze/Schenk: Halbleiterschaltungstechnik, Springer Berlin, 1999

the quality factor of the poles where

in case of a Bessel filter a = 1.3617, b = 0.618

and thus Q = 0.577

and in case of a Butterworth filter a = 1.141, b = 1

and thus Q = 0.71

Example

Butterworth filter with f3dB = 5 kHz and R = 100 kΩ

C1 = 450 pF, C2 = 225 pF

Pins: 22 21 19

100k 100k

C1C2

1Π

fQR

2Π

TDA 5200

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Applications

Data Sheet 25 Revision 3.0, 2010-12-28

4.3 Quartz Load Capacitance Calculation

The value of the capacitor necessary to achieve that the quartz oscillator is operating at the intended frequency is

determined by the reactive part of the negative resistance of the oscillator circuit as shown in Chapter 5.1.3 and

by the quartz specifications given by the quartz manufacturer.

Figure 8 Determination of Series Capacitance Value for the Quartz Oscillator

Crystal specified with load capacitance

(4)

with CL the load capacitance (refer to the quartz crystal specification).

These values may be obtained in high accuracy by putting two capacitors in series to the quartz, such as 20 pF

and 15 pF in the 6.7 MHz case and 15 pF and 8.2 pF in the 13.401 MHz case.

But please note that the calculated value of CS includes the parasitic capacitors also.

Examples

6.7 MHz CL = 12 pF XL = 750 ΩCS = 8.7 pF

13.401 MHz CL = 12 pF XL = 1250 ΩCS = 5.3 pF

Crystal Input

impedance

Z1-28 TDA5200

Pin 28

Pin 1

TDA 5200

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Applications

Data Sheet 26 Revision 3.0, 2010-12-28

4.4 Quartz Frequency Calculation

As described in Chapter 3.4.3, the operating range of the on-chip VCO is 820 MHz to 860 MHz with a nominal

center frequency of approximately 840 MHz. This signal is divided by 2 before applied to the mixer in case of

operation at 434 MHz. This local oscillator signal can be used to down-convert the RF signals both with high- or

low-side injection at the mixer. The resulting receive frequency ranges then extend between 810 MHz and

870 MHz or between 400 MHz and 440 MHz. Low-side injection of the local oscillator has to be used for receive

frequencies between 840 MHz and 870 MHz as well as high-side injection for receive frequencies below 840 MHz.

Corresponding to that in the 400 MHz region low-side injection is applicable for receive frequencies above

420 MHz, high-side injection below this frequency. Therefore for operation both in the 868 MHz and the 434 MHz

ISM bands low-side injection of the local oscillator has to be used. Then the local oscillator frequency is calculated

by subtracting the IF frequency (10.7 MHz) from the RF frequency (434 MHz or 868 MHz). The overall division

ratios in the PLL are 64 or 128 in case of operation at 868 MHz or 32 and 64 in case of operation at 434 MHz,

depending on the crystal frequency used as shown below.

Therefore, the quartz frequency is calculated by using the following formula:

(5)

with

Subtraction of 10.7 occurs in case the receive frequency is higher than the intended local oscillator frequency,

addition in case the receive frequency lies below the local oscillator frequency.

Example

(6)

(7)

(8)

ƒRF Receive frequency

ƒLO Local oscillator (PLL) frequency (ƒRF ± 10.7)

ƒQU Quartz oscillator frequency

rRatio of local oscillator (PLL) frequency and quartz frequency as shown in the subsequent table

Table 5 PLL Division Ratio Dependence on States of CSEL

FSEL CSEL Ratio r = (ƒLO/ƒQU)

Open Open 64

Open GND 32

GND Open 128

GND GND 64

fRF

7.10

()

MHzMHzMHzf 40156.1364/7.104.868

=−=

()

MHzMHzMHzf 7008.6128/7.104.868

=−=

()

MHzMHzMHzf 23437.1332/7.102.434

=−=

TDA 5200

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Data Sheet 27 Revision 3.0, 2010-12-28

4.5 Data Slicer Threshold Generation

The threshold of the data slicer can be generated in two ways, depending on the signal coding scheme used. In

case of a signal coding scheme without DC content such as Manchester coding the threshold can be generated

using an external RC-Integrator as shown in Figure 9. The time constant TA of the RC-Integrator has to be

significantly larger than the longest period of no signal change TL within the data sequence. In order to keep

distortion low, the minimum value for R is 20 kΩ.

Figure 9 Data Slicer Threshold Generation with External R-C Integrator

Another possibility for threshold generation is to use the peak detector in connection with two resistors and one

capacitor as shown in the following figure. The component values are depending on the coding scheme and the

protocol used.

Figure 10 Data Slicer Threshold Generation Utilizing the Peak Detector

Pins: 2019

data out

Uthreshold

data slicer

data

filter

Pins: 20

19 25

data out

Uthreshold

data slicer

data

filter

peak detector

TDA 5200

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Electrical Characteristics

Data Sheet 28 Revision 3.0, 2010-12-28

5Electrical Characteristics

5.1 Electrical Data

5.1.1 Absolute Maximum Ratings

Attention: The maximum ratings may not be exceeded under any circumstances, not even momentarily

and individually, as permanent damage to the IC will result.

Table 6 Absolute Maximum Ratings, Ambient Temperature TAMB = - 40 °C ... + 85 °C

Parameter Symbol Values Unit Note /

Test Condition

Number

Min. Typ. Max.

Supply Voltage VCC -0.3 5.5 V 1.1

Junction Temperature Tj-40 +125 °C 1.2

Storage Temperature Ts-40 +150 °C 1.3

Thermal Resistance RthJA 114 K/W 1.4

ESD HBM integrity, all pins VESD ±1,5 kV AEC Q100-002 /

JESD22-A114B

1.5

ESD SDM integrity, all pins VESD ±750 V AINSI / ESD

SP5.3.2-2008

1.6

TDA 5200

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Electrical Characteristics

Data Sheet 29 Revision 3.0, 2010-12-28

5.1.2 Operating Range

Within the operating range the IC operates as explained in the circuit description. The AC/DC characteristic limits

are not guaranteed.

Supply voltage: VCC = 4.5 V ... 5.5 V

Attention: Test ■ means that the parameter is not subject to production test.

It was verified by design/characterization.

Table 7 Operating Range, Ambient Temperature TAMB = - 40 °C ... + 85 °C

Parameter Symbol Values Unit Note /

Test Condition

Test Number

Min. Typ. Max.

Supply Current IS 868 5.6 mA fRF = 868 MHz 2.1

IS 434 5.4 mA fRF = 434 MHz 2.2

Receiver Input Level RFin -107 -13 dBm @ source impedance

50 Ω, BER 2E-3,

average power level,

Manchester encoded

data rate 4 kBit,

280 kHz IF

Bandwidth

■2.3

LNI Input Frequency fRF 433 435 MHz 2.4

fRF 868 870 MHz 2.5

MI/X Input Frequency fMI 433 435 MHz 2.6

fMI 868 870 MHz 2.7

3 dB IF Frequency

Range

fIF -3 dB 523MHz 2.8

Power Down Mode On PWDNON 0 0.8 V 2.9

Power Down Mode Off PWDNOFF 2VCC V2.10

Gain Control Voltage,

LNA high gain state

VTHRES 2.8 VCC-1 V 2.11

Gain Control Voltage,

LNA low gain state

VTHRES 0 0.7 V 2.12

TDA 5200

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Electrical Characteristics

Data Sheet 30 Revision 3.0, 2010-12-28

5.1.3 AC/DC Characteristics

AC/DC characteristics involve the spread of values guaranteed within the specified voltage and ambient

temperature range. Typical characteristics are the median of the production. The device performance parameters

marked with ■ are not subject to production test. They were verified by design/characterization.

Table 8 AC/DC Characteristics with TAMB = 25 °C, VCC = 4.5 ... 5.5 V

Parameter Symbol Values Unit Note /

Test Condition

Test Number

Min. Typ. Max.

Supply Current

Supply current

standby mode

IS PDWN 50 70 nA Pin 27 (PDWN)

open or tied to 0 V

3.1

Supply current, device

operating at 868 MHz

IS 868 4.8 5.2 mA Pin 11 (FSEL) tied

to GND

3.2

Supply current, device

operating at 434 MHz

IS 434 4.6 5 mA Pin 11 (FSEL)

open

3.3

LNA - Signal Input LNI (PIN 3), VTHRES > 3.3 V, High Gain Mode

Average Power Level

at BER = 2E-3

(Sensitivity)

RFin -110 dBm Manchester

encoded data rate

4kBit, 280kHz IF

Bandwidth

■3.4

Input impedance

fRF = 434 MHz

S11 LNA 0.873 /

-34.7 deg

■3.5

Input impedance

fRF = 868 MHz

S11 LNA 0.738 /

-73.5 deg

■3.6

Input level @ 1 dB

compression

P1dBLNA -10 dBm ■3.7

Input 3rd order intercept

point fRF = 434 MHz

IIP3LNA -10 dBm Matched input ■3.8

Input 3rd order intercept

point fRF = 868 MHz

IIP3LNA -14 dBm Matched input ■3.9

LO signal feedthrough at

antenna port

LOLNI -73 dBm ■3.10

LNA - Signal Output LNO (PIN 6), VTHRES > 3.3 V, High Gain Mode

Gain fRF = 434 MHz S21 LNA 1.509 /

138.2 deg

■3.11

Gain fRF = 868 MHz S21 LNA 1.419 /

101.7 deg

■3.12

Output impedance,

fRF =434MHz

S22 LNA 0.886 /

-12.9 deg

■3.13

Output impedance,

fRF =868MHz

S22 LNA 0.866 /

-24.2 deg

■3.14

LNA - Signal Input LNI, VTHRES = GND, Low Gain Mode

Input impedance

fRF =434MHz

S11 LNA 0.873 /

-34.7 deg

■3.15

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Electrical Characteristics

Data Sheet 31 Revision 3.0, 2010-12-28

Input impedance

fRF =868MHz

S11 LNA 0.738 /

-73.5 deg

■3.16

Input level @ 1 dB C. P.

fRF =434MHz

P1dBLNA -18 dBm Matched input ■3.17

Input level @ 1 dB C. P.

fRF =868MHz

P1dBLNA -6 dBm Matched input ■3.18

Input 3rd order intercept

point fRF =434MHz

IIP3LNA -10 dBm Matched input ■3.19

Input 3rd order intercept

point fRF =868MHz

IIP3LNA -5 dBm Matched input ■3.20

LNA - Signal Output LNO, VTHRES = GND, Low Gain Mode

Gain fRF =434MHz S21 LNA 0.183 /

140.6 deg

■3.21

Gain fRF =868MHz S21 LNA 0.179 /

109.1 deg

■3.22

Output impedance

,fRF =434MHz

S22 LNA 0.897 /

-13.6 deg

■3.23

Output impedance

,fRF =868MHz

S22 LNA 0.868 /

-26.3 deg

■3.24

LNA - Antenna to IFO, VTHRES > 3.3 V, High Gain Mode

Voltage Gain Antenna to

Mixer-Out (IFO)

fRF =434MHz

GAntMixerOut 42 dB 3.25

Voltage Gain Antenna to

Mixer-Out (IFO)

fRF =868MHz

GAntMixerOut 40 dB 3.26

LNA - Antenna to IFO, VTHRES = GND, Low Gain Mode

Voltage Gain Antenna to

Mixer-Out (IFO)

fRF =434MHz

GAntMixerOut 22 dB 3.27

Voltage Gain Antenna to

Mixer-Out (IFO)

fRF =868MHz

GAntMixerOut 19 dB 3.28

AGC - Signal 3VOUT (PIN 24)

Output voltage V3VOUT 3 V At 5 µA 3.29

Current out I3VOUT 50 µA 3.30

AGC - Signal THRES (PIN 23)

Input Voltage range VTHRES 0VCC-1 V See chapter 4.1 3.31

LNA low gain mode VTHRES 0 V 3.32

Table 8 AC/DC Characteristics with TAMB = 25 °C, VCC = 4.5 ... 5.5 V (cont’d)

Parameter Symbol Values Unit Note /

Test Condition

Test Number

Min. Typ. Max.

TDA 5200

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Electrical Characteristics

Data Sheet 32 Revision 3.0, 2010-12-28

LNA high gain mode VTHRES 3.31) VCC-11) V Voltage must not

be higher than

VCC-1 V

3.33

Current in ITHRES_in 5nA ■3.34

AGC - Signal TAGC (PIN 4)

Current out,

LNA low gain state

ITAGC_out 4.2 µA RSSI > VTHRES 3.35

Current in,

LNA high gain state

ITAGC_in 1.5 µA RSSI < VTHRES 3.36

MIXER - Signal Input MI/MIX (PINS 8/9)

Input impedance

fRF =434MHz

S11 MIX 0.942 /

-14.4 deg

■3.37

Input impedance

fRF =868MHz

S11 MIX 0.918 /

-28.1 deg

■3.38

Input 3rd order intercept

point fRF = 434 MHz

IIP3MIX -28 dBm ■3.39

Input 3rd order intercept

point fRF = 868 MHz

IIP3MIX -26 dBm ■3.40

MIXER - Signal Output IFO (PIN 12)

Output impedance ZIFO 330 Ω3.41

Conversion Voltage Gain

fRF =434MHz

GMIX +19 dB 3.42

Conversion Voltage Gain

fRF =868MHz

GMIX +18 dB 3.43

LIMITER - Signal Input LIM/LIMX (PINS 17/18)

Input Impedance ZLIM 264 330 396 Ω■3.44

RSSI dynamic range DRRSSI 60 80 dB 3.45

RSSI linearity LINRSSI ±1 dB ■3.46

Operating frequency

(3 dB points)

fLIM 5 10.7 23 MHz ■3.47

DATA FILTER

Useable bandwidth BWBB FILT 100 kHz ■3.48

RSSI Level at Data Filter

Output SLP

RSSIlow 1.1 V LNA in high gain

RFIN = -103 dBm

868 MHz

3.49

RSSI Level at Data Filter

Output SLP

RSSIhigh 2.65 V LNA in high gain

RFIN =-30dBm

868 MHz

3.50

SLICER - Signal Output DATA (PIN 25)

Useable bandwidth BWBB SLIC 100 kHz ■3.51

Table 8 AC/DC Characteristics with TAMB = 25 °C, VCC = 4.5 ... 5.5 V (cont’d)

Parameter Symbol Values Unit Note /

Test Condition

Test Number

Min. Typ. Max.

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Electrical Characteristics

Data Sheet 33 Revision 3.0, 2010-12-28

Capacitive loading of

output

Cmax SLIC 20 pF 3.52

LOW output voltage VSLIC_L 0 V 3.53

HIGH output voltage VSLIC_H VCC-1.3 VCC-1 VCC-0.7 V Output current

=200µA

3.54

Output current ISLIC_out 200 µA 3.55

PEAK DETECTOR - Signal Output PDO (PIN 26)

LOW output voltage VSLIC_L 0 V 3.56

HIGH output voltage VSLIC_H VCC-1 V 3.57

Load current Iload -500 µA Static load current

must not exceed

-500 µA

3.58

Leakage current Ileakage 700 nA 3.59

CRYSTAL OSCILLATOR - Signals CRST1, CRST2, (PINS 1/28)

Operating frequency fCRSTL 6 14 MHz Fundamental

mode, series

resonance

3.60

Input Impedance

@~6MHz

Z1-28 -900

+j750

Ω■3.61

Input Impedance

@~13MHz

Z1-28 -450

+ j1250

Ω■3.62

Serial Capacity

@~6MHz

CS6 = C1 8.7 pF 3.63

Serial Capacity

@~13MHz

CS13 = C1 5.3 pF 3.64

PLL - Signal LF (PIN 15)

Tuning voltage relative to

VCC

VTUNE 0.4 1.6 2.4 V 3.65

POWER DOWN MODE - Signal PDWN (PIN 27)

Power Mode On VON 2.8 VCC V3.66

Power Mode Off VPWDN 00.8V 3.67

Input bias current PDWN IPDWN 19 µA 3.68

Start-up Time until valid

IF signal is detected

TSU <1 ms Depends on the

used crystal

3.69

PLL DIVIDER - Signal CSEL (PIN 16)

fCRSTL range 6.xx MHz VCSEL 1.4 42) V Or open 3.70

fCRSTL range 13.xx MHz VCSEL 00.2V 3.71

Input bias current CSEL ICSEL 5 µA CSEL tied to GND 3.72

1) See Chapter 4.1 Choice of LNA Threshold Voltage and Time Constant.

2) Maximum voltage in Power-On state is 4 V, but in PDWN-state the maximum voltage is 2.8 V.

Table 8 AC/DC Characteristics with TAMB = 25 °C, VCC = 4.5 ... 5.5 V (cont’d)

Parameter Symbol Values Unit Note /

Test Condition

Test Number

Min. Typ. Max.

TDA 5200

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Electrical Characteristics

Data Sheet 34 Revision 3.0, 2010-12-28

5.2 Test Board

5.2.1 Test Circuit

The device performance parameters marked with ■ in Chapter 5.1.3 are not subject to production test. They were

verified by design/characterization.

Figure 11 Schematic of the Evaluation Board

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Electrical Characteristics

Data Sheet 35 Revision 3.0, 2010-12-28

5.2.2 Test Board Layouts

Figure 12 Top Side of the Evaluation Board

Figure 13 Bottom Side of the Evaluation Board

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Electrical Characteristics

Data Sheet 36 Revision 3.0, 2010-12-28

Figure 14 Component Placement on the Evaluation Board

TDA 5200

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Electrical Characteristics

Data Sheet 37 Revision 3.0, 2010-12-28

5.2.3 Bill of Materials

The following components are necessary for evaluation of the TDA5200 without use of a Microchip HCS515

decoder.

Table 9 Bill of Materials

Ref Value Specification

R1 100 kΩ0805, ± 5 %

R2 100 kΩ0805, ± 5 %

R3 820 kΩ0805, ± 5 %

R4 120 kΩ0805, ± 5 %

R5 180 kΩ0805, ± 5 %

R6 10 kΩ0805, ± 5 %

L1 434 MHz: 15 nH

868 MHz: 3.3 nH

Toko, PTL2012-F15N0G

Toko, PTL2012-F3N3C

L2 434 MHz: 8.2 pF

868 MHz: 3.9 nH

0805, COG, ± 0.1 pF

Toko, PTL2012-F3N9C

C1 1 pF 0805, COG, ± 0.1 pF

C2 434 MHz: 4.7 pF

868 MHz: 3.9 pF

0805, COG, ± 0.1 pF

C3 434 MHz: 6.8 pF

868 MHz: 5.6 pF

0805, COG, ± 0.1 pF

C4 100 pF 0805, COG, ± 5 %

C5 47 nF 1206, X7R, ± 10 %

C6 434 MHz: 10 nH

868 MHz: 3.9 pF

Toko, PTL2012-F10N0G

0805, COG, ± 0.1 pF

C7 100 pF 0805, COG, ± 5 %

C8 434 MHz: 33 pF

868 MHz: 22 pF

0805, COG, ± 5 %

C9 100 pF 0805, COG, ± 5 %

C10 10 nF 0805, X7R, ± 10 %

C11 10 nF 0805, X7R, ± 10 %

C12 220 pF 0805, COG, ± 5 %

C13 47 nF 0805, X7R, ± 10 %

C14 470 pF 0805, COG, ± 5 %

C15 47 nF 0805, X7R, ± 5 %

C16 15 pF 0805, COG, ± 1 %

C17 8.2 pF 0805, COG, ± 1 %

Q2 (fRF – 10.7 MHz)/32 or

(fRF – 10.7 MHz)/64

HC49/U, fundamental mode, CL = 12 pF,

e.g. 434.2 MHz: Jauch Q 13,23437-S11-1323-12-10/20

e.g. 868.4 MHz: Jauch Q 13,40155-S11-1323-12-10/20

F1 SFE10.7MA5-A or

SKM107M1-A20-10

Murata

Toko

X2, X3 142-0701-801 Johnson

TDA 5200

ASK Single Conversion Receiver

Electrical Characteristics

Data Sheet 38 Revision 3.0, 2010-12-28

Please note that in case of operation at 434 MHz a capacitor has to be soldered in place of L2 and an inductor in

place of C6.

The following components are necessary in addition to the above mentioned ones for evaluation of the TDA 5200

in conjunction with a Microchip HCS515 decoder.

X1, X4, S1, S5 2-pole pin connector

S4 3-pole pin connector, or not equipped

IC1 TDA 5200 Infineon

Table 10 Bill of Materials Addendum

Ref Value Specification

R21 22 kΩ0805, ± 5 %

R22 100 kΩ0805, ± 5 %

R23 22 kΩ0805, ± 5 %

R24 820 kΩ0805, ± 5 %

R25 560 kΩ0805, ± 5 %

C21 100 nF 1206, X7R, ± 10 %

C22 100 nF 1206, X7R, ± 10 %

IC2 HCS515 Microchip

T1 BC 847B Infineon

D1 LS T670-JL Infineon

Table 9 Bill of Materials

Ref Value Specification

Published by Infineon Technologies AG