General Purpose Copyright © 2004 by Silicon Laboratories 8.9.2004
P0, P1,
P2, P3
Latches
JTAG
Logic
TCK
TMS
TDI
TDO
UART1
SMBus
SPI Bus
PCA
VDD
Monitor
Timers 0,
1, 2, 4
Timer 3/
RTC
P0
Drv
C
R
O
S
S
B
A
R
Port I/O
Config.
Crossbar
Config.
AV+
VDD
VDD
VDD
DGND
DGND
DGND
AGND
Reset
RST
Digital Power
Analog Power
Debug HW
Boundary Scan
P2.0
P2.7
P1.0/AIN2.0
P1.7/AIN2.7
P0.0
P0.7
P1
Drv
P2
Drv
Data Bus
Address Bus
Bus Control
VREF
ADC
100ksps
(10-Bit)
A
M
U
X
AIN0.0
AIN0.1
AIN0.2
AIN0.3
AIN0.4
AIN0.5
AIN0.6
AIN0.7
CP0+
CP0-
CP1+
CP1-
VREF
TEMP
SENSOR
UART0
P3.0
P3.7
P3
Drv
MONEN WDT
VREF0
Prog
Gain
CP0
CP1
C
T
L
P4 Latch
D
a
t
a
P7 Latch
A
d
d
r
P5 Latch
P6 Latch
P7
DRV
P5
DRV
P6
DRV
P4
DRV
XTAL1
XTAL2
External Oscillator
Circuit
System
Clock
Calibrated Internal
Oscillator
PLL
Circuitry
256 byte
RAM
SFR Bus
8
0
5
1
C
o
r
e
8kbyte
XRAM
External Data
Memory Bus
FLASH
128kbyte
64x4 byte
cache
C8051F131
100 MIPS, 128 kB Flash, 10-Bit ADC, 64-Pin Mixed-Signal MCU
Analog Peripherals
10-Bit ADC
-±1 LSB INL; no missing codes
-Programmable throughput up to 100 ksps
-8 external inputs; programmable as single-ended or differential
-Programmable amplifier gain: 16, 8, 4, 2, 1, 0.5
-Data-dependent windowed interrupt generator
-Built-in temperature sensor (±3 °C)
Two Comparators
Internal Voltage Reference
VDD Monitor/Brown-out Detector
On-Chip JTAG Debug & Boundary Scan
-On-chip debug circuitry facilitates full speed, non-intrusive in-system
debug (no emulator required)
-Provides breakpoints, single stepping, watchpoints, stack monitor
-Inspect/modify memory and registers
-Superior performance to emulation systems using ICE-chips, target
pods, and sockets
-IEEE1149.1 compliant boundary scan
High-Speed 8051 µC Core
-Pipelined instruction architecture; executes 70% of instructions in 1 or 2
system clocks
-Up to 100 MIPS throughput with 100 MHz system clock
-16 x 16 multiply/accumulate engine (2-cycle)
Memory
-8448 bytes data RAM
-128 kB Flash; in-system programmable in 1024-byte sectors (1024 bytes
are reserved)
-External parallel data memory interface
Digital Peripherals
-32 port I/O; all are 5 V tolerant
-Hardware SMBus™ (I2C™ Compatible), SPI™, and two UART serial
ports available concurrently
-Programmable 16-bit counter/timer array with six capture/compare
modules
-5 general-purpose 16-bit counter/timers
-Dedicated watchdog timer; bidirectional reset
-Real-time clock mode using Timer 3 or PCA
Clock Sources
-Internal oscillator: 24.5 MHz, 2% accuracy supports UART operation
-On-chip programmable PLL: up to 100 MHz
-External oscillator: Crystal, RC, C, or Clock
Supply Voltage: 3.0 to 3.6 V
-Typical operating current: 50 mA at 100 MHz
-Typical stop mode current: 0.4 µA
64-Pin TQFP
Temperature Range: –40 to +85 °C
General Purpose Copyright © 2004 by Silicon Laboratories 8.9.2004
Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.
Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders
C8051F131
100 MIPS, 128 kB Flash, 10-Bit ADC, 64-Pin Mixed-Signal MCU
Selected Electrical Specifications
(TA = –40 to +85 C°, VDD = 3.0 V unless otherwise specified)
PARAMETER CONDITIONS MIN TYP MAX UNITS
GLOBAL CHARACTERISTICS
Supply Voltage 3.0 — 3.6 V
Supply Current
(CPU active)
Clock = 100 MHz
Clock = 1 MHz
Clock = 32 kHz
—
—
—
50
0.6
16
—
—
—
mA
mA
µA
Supply Current
(shutdown)
Oscillator off; VDD Monitor Enabled
Oscillator off; VDD Monitor Disabled
—
—
10
0.4
—
—
µA
µA
Clock Frequency Range DC — 100 MHz
INTERNAL CLOCKS
Oscillator Frequency 24.0 24.5 25.0 MHz
PLL Frequency — — 100 MHz
A/D CONVERTER
Resolution 10 bits
Integral Nonlinearity — — ±1 LSB
Differential Nonlinearity Guaranteed Monotonic — — ±1 LSB
Signal-to-Noise Plus
Distortion
59 — — dB
Throughput Rate — — 100 ksps
Package Information
A
A1
A2
b
D
D1
e
E
E1
-
0.05
0.95
0.17
-
-
-
-
-
-
-
-
0.22
12.00
10.00
0.50
12.00
10.00
1.20
0.15
1.05
0.27
-
-
-
-
-
MIN
(mm)
NOM
(mm)
MAX
(mm)
1
64
E
E1
e
A1
b
D
D1
PIN 1
DESIGNATOR
A2
A
C8051F120DK Development Kit
