HARRIS SEMICOND SECTOR Technical Data CD54/74HCT112 CD54/74HCT112 High-Speed CMOS Logic File Number 1843 27E D 4302271 001755) b RMHAS T= &-O7-07- 2 Dual J-K Flip-Flop with Set and Reset. Hysteresis on clock inputs for improved noise immunity and increased rs 4 Ww 1K 7 FF 6 ier i) Negative-Edge Trigger ir 13 zs 19 are 9 Type Features: 23 2a aK Fre 7. input rise and fall times ace 2a = Asynchronous set and reset R14 GND*8 Complementary outputs Veg" 16 s Buffered inputs 9205-4034) a FUNCTIONAL DIAGRAM The RCA-CD54/74HC112 and CD54/74HCT112 utilize siticon-gate CMOS technology to achieve operating speeds equivalent to LSTTL parts. They exhibit the low power consumption of standard CMOS integrated circuits, together with the ability to drive 10 LSTTL loads. These flip-flops have independent J, K, Set, Reset, and Clock inputs and Q and @ outputs. They change state on the negative-going transition of the clock pulse. Set and Reset are accomplished asynchronously by low-level inputs. The 54HCT/74HCT logic family is functionally as well as pin-compatible with the standard 54LS/74LS logic family. The CO54HC112 and CD54HCT112 are supplied in 16-lead hermetic dual-in-line ceramic packages (F suffix). The CO74HC112 and CD74HCT112 are supplied in 16-lead dual-in-line plastic packages (E suffix) and in 16-lead dual- in-line surface-mount plastic packages (M suffix). Both types are also available in chip form (H suffix). TRUTH TABLE (EACH FLIP-FLOP) INPUTS OUTPUTS 5 R cP J K a a L H x x X H L H L xX x xX L H L L xX X xX H* H* H H | NY] L L No Change H H ~_ H L H L H H L H L H H H |-\_T H H Toggle H H H x X No Change 144 Typical fmax = 60 MHz @ Voc 2 5 V, Cv = 15 pF, Ta = 25C Family Features: mu Fanout (Over Temperature Range): 2 Standard Outputs - 10 LSTTL Loads - Bus Driver Outputs - 15 LSTTL Loads Wide Operating Temperature Range: CD74HC/HCT: -40 to +85C . a a Balanced Propagation Delay and Transition Times Significant Power Reduction Compared to LSTTL Logic ICs a Alternate Source is Philips/Signetics @ CD&4HC/CD74HC Types: 2 to 6 V Operation High Noise Immunity: Ni = 30%, Nm = 30% of Vee, @ Vcc = 5V = CDS4HCT/CD74HCT Types: 4.5 to .5 V Operation Direct LSTTL Input Logie Corhpatibitity Vii = 0.8 V Max., Vin = 2 V Min. CMOS Input Compatibility hS1 pA @ Vou, Vou * Output states unpredictable if S and R go: High simultaneously after both being low at the same time. H = High steady state. L = Low steady state. X = Irrelevant. \ = High-to-Low transition.CD54/74HCT112 CD54/74HCT112 T-46-07-07 Technical Data MAXIMUM RATINGS, Absolute-Maximum Values: DC SUPPLY-VOLTAGE, (Vee): (Voltages referenced to Ground) ... 0 eee eee cec cece cee ee cuneveuevscuueseneeeeennans pee eeeteeueeeens bee geeeeeeuee se 05 to #7 V OC INPUT DIODE CURRENT, Ix (FOR Vi < -0.5 V OR Vi > Voc 40.5 V) cece cece ec ee en cceneeneeeterevertay Peeve veraseteresceves 20 MA DC OUTPUT DIODE CURRENT, lox (FOR Vo < -0.5 V OR Vo > Vee +0.5 A) beeeeneeeeteeeereer ess 20 MA DC DRAIN CURRENT, PER OUTPUT (Io) (FOR -0.5 V < Vo < Vec +0.5 NV) ccc cece censor eeeneeeetereereas bee ete veces favasee 25 mA DC Vee OR GROUND CURRENT, (Icc)!.. ees ece eee cece eecneteeeneeseeevurssseepueaeetpeneeatenevneuesenses covevesecerineces LOOMA POWER DISSIPATION PER PACKAGE (Pp): . oo. - x For Ta = -40 to +60C (PACKAGE TYPE E) 10... 0. ccc cece ccc ccucuetecuencerenauneeaecescagenenens ens Soccer eresevae 500 mW For Ta = +60 to +85C (PACKAGE TYPE E) ..0.. 0... cc ccccccccecccecuncetaueveeeves . Derate Linearly at 8 mW/C to 300 mW | - For Ta = -55 to +100C (PACKAGE TYPE F, H) oo. 0... cece ce ceeceenc cess ceesuneeceueeetecnbeyaes Peeeeretrenereerreeeseecs SOO MW For Ta = +100 to +125C (PACKAGE TYPE F.H) .......cccccccccccccecunccecctsceunvnvecveess Derate Linearly at 8 mW/C to 300 mW For Ta = -40 to #70C (PACKAGE TYPE M) .0. 2... ccc ccccceeeeeacesuucecacecuceeucueseuteneeseenens heeaee Viveseuee tenes 400 MW. For Ta = #70 to +125C (PACKAGE TYPE M) 0.20.2... cece cccccuccvsuucaccnceeteeseesevacsegs Derate Linearly at 6. mW/C to 70 mW OPERATING- TEMPERATURE RANGE (Ta): De PACKAGE TYPE F, H leasaneeee eo 0 55 to. +125C e?7E D MM 4302271 0017552 & BHAS PACKAGE TYPE E.M sous. 9-40-to 485C STORAGE TEMPERATURE (Taig) verrereriae G5 to 4+150C LEAD TEMPERATURE (DURING SOLDERING): a . : : At distance 1/16 + 1/32 in. (1.59 + 0.79 mm) from case for 10S MAX. ......... cece csecccceeuuccucecuaneesece printetrecceves t265C Unit inserted into a PC board (min. thickness 1/16 in., 1.59 mm) noe Po with solder contacting lead tips ONly 2.0.2... cece cece cece encneeecsecceceneeenvnnseneraesenses teeeeeae Tesaverecser 4300C - si(9) cL _->0a L - | . a _ Pp 30) cL . a Tha t & : cL + ejay cl 22) 6(7) . oe 21 . n ) +44 > D9. . o : Oo Ko >> oo .- co ae ch : . w i) - Lid 15014) A 2 oO =o. ce 92M-40340 ww =- 4 cL : a Fig. 1 - Flip-tlop logic diagram. " RECOMMENDED OPERATING CONDITIONS: : : ae For maximum reliabillty, nominal operating conditions should be selected so that operation is always within the 4 following ranges: - ; oOo LIMITS : = CHARACTERISTIC q+, UNITS MIN. MAX, . Supply-Voltage Range (For Ta = Full Package-Temperature Range) Vcc:* . oe feee CD54/74HC Types 2 BO pO: CD54/74HCT Types 45 -| 55 Vv DC Input or Output Voltage Vi, Vo 0 oT Veo. Operating Temperature Ty: -: 7: CD74 Types -40 - +85 C CD54 Types -55 $125 2G Input Rise and Fall Times, t,, te , 7 at2V 0 1000 ns at4.5V 0 500. 1] as at6V 0 |. 400 ns * Unless otherwise specified, all voltages are referenced to Ground. * Applicable for all inputs except clock. 145Technical Data __ . T-46-07-07 . 4 CD54/74HCT112 x= 5 CD54/74HCT112 Ee STATIC ELECTRICAL CHARACTERISTICS Sa a - / oe - tt : uy CO74HC112, CO54HC112 CD74HCT112, cps4HcTtiz ~ TEST T4HC/S4HC | 74HC | S4HC TEST T4HCT/S4HCT | 74HCT. | S4HCT a CONDITIONS TYPE TYPE TYPE CONDITIONS TYPE TYPE TYPE oO CHARACTERISTICS UNITS asc -40/ -58/ vase | 80 | 887 a +85C #125C +85C +125C ~ vi lo [Vcc Mi Vee - : . mu : v A v v v - a . nu Min | Typ |Max |Min |Max | Min |Max Min | Typ |Max | Min | Max | Mia-) Max Oo : - o High-Level 2 iis || lis] jis] 48 Input Voltage Vues 45 |3.1s| | j3.15| |[3.15| ~ to {2]/-]}-]2}-]ey-f ov ; a 6 |42| | |4a2| [a2 | 5.5 ~ Low-Levai 2} ] /|05] [05] 405 4.6 a Input Voltage Vin 45 | | 4135} }1.35] 11.35 - to | -} |08] ]08)|08;--Vv 6 | | |18] {18} [18 85 : _. nm High-Level Va. 2 [19{ | [1.9 | [19 | Vin : . nu Output Voltage Von or |-0.02 |45 44] | 144 [ 144} or 45 |[44)} - (44), [441 V CMOS Loads Vin 6 j59| | {59 | [59 | Vos _ Vin Vu. TTL Loads or -4 [45 [3.98] | [3.84] 13.7 | or 45 |3.98} | [3.84] 37 = v . ae Vn | -5.2 | 6 [5.48| | |s.aa] [5.2 | Vin So Low-Level Va 2 | [01] {01} [04 Vu io Output Voltage Va | or | 0.02 [45 | | lor! [or] Jos or 4s |}]torl lork= lor v WW CMOS Loads Vow & | 4,01) |o1/ [0.1 Vim a Va. Vw . za TTL Loads or 4 [45 | | |0.26| jo.33] [04 or 45 | | [0.26] ~ 10.33] =-/04 v S Vin 5.2 6 = | |0.26{ [0.33] | 0.4 Vua Ht Input Leakage Any = Current h Vee Voltage . Li or 6 | | tro1| | +1] [41] Between | 55 | ] Jtos} far} far} wa Gnd Vee and : - . Gnd Ke Quiescent Device Vee m Current lee Veo ~ ac or 0 6/t|4 |] 40] J 60 or 55 J]-|]4 | ~ 140 | | 80 uA =< Gnd Gnd . <= Additional Quiescent Device 45 : | . Current per Veo -2.1 to 1100 }360] | 460 }- 490 HA Input Pin: 5.5 1 Unit Load Alcc *For dual-supply systems theoretical worst case (V, = 2.4 V, Vce = 5.5 Y) specification is 1.8 mA. HCT INPUT LOADING TABLE 1teU h Voc 1K 2] L158 aR INPUT UNIT LOADS * wy {4 5% 4 43 ra 56 ts LK Zcp 18, 28 0.5 19 4 12. ook 1K, 2K 0.6 13 a Jt ay iA, 2A 0.65 23 Ho 2S 1J, 2J, TCP, 2CP 1 sno P28 U Cc isti TOP VIEW 928+40339 * Unit Load is Alce limit specified in Static Characteristic p TERMINAL ASSIGNMENT Chart, e.g.. 360 uA max. @ 25C. 146e?E D MM 4302271 0017554 1 BMHAS HARRIS SEMICOND SECTOR T-46-07-07 | Technical Data SWITCHING CHARACTERISTICS (Vcc = 5 V, Ta = 25C, Input t,, t = 6 ns) , TYPICAL VALUES CHARACTERISTIC Cc .- | UNITS (pF) - Hc - -HCT yoo Propagation Delay / - - CP toa. Q toon, ter 15 414 fs 44 - J ons 5t0Q.Q 13> fs Ad | ons Rtoa,g 18.0. 14. ns GB Frequency frnax 15 60... |. 60 | MHz Power Dissipation Capacitance * Ceo - 12 20. pF * Ceo is used to determine the dynamic power consumption, per flip-flop. Pp = Ceo Vec*f, + E Cx Veo*f. where: f, = input frequency Cx = output load capacitance fo = output frequency Vcc = supply voltage PRE-REQUISITE FOR SWITCHING FUNCTION LIMITS TEST 26C -40C to +85C 55C. to 125C: |. \ . CHARACTERISTIC CONDITION _ | UNITS. HC HoT | 74HC | 7aHCT | 54aHc | saHcT- | Vcc a Vv Min. |Max. |Min. /Max. | Min. |Max.)Min. |Max. | Min. [Max. | Min. |Max: Pulse Width tw 2 so | | | |wo} | | = fraofp f=} cP 4.5 1/]16}|20}]20/+]2atboaal] ns 6 14}-/-|-|iwf-|-{-}2o,-Jf= 2 go | | | Joo} | | = fra [ f=] A, 4.5 16 | | 18 | | 20 | | 23 |. | 2d | = | 27-| =] ns 6 14{-||]-]27}-|-|-]eof-f}- Set-up Time tsu 2 so )|||wof|] frof=f- fap. J, K to CP 4.5 16 | ~ | 16 | | 20} | 20; ; 2a} | 24 pm - ns 6 14{|-}|-|aw]|-}|-]a}t-};-}=]. | Hold Time ta 2 o}/;|~[]|o/-;-}-J.of= f+. [- J. K to GP 4.5 of{3}|o}|3}f|o}=} 3 f= ]ins fo o/]f | |=] = = _ Removal Time trem 2 go; ~ | | | 100} [ | 420 fa me ee Ato OP 4.8 16 | |20]| 20} ]25}~ je] }30}= | ns Sto OF 6 4 }-|-|-J]iw[]-]- fof jf- CP Frequency fmax 2 6ij|-f;-[|s}/-[-{ 4: = ap ce | as 4.5 30 | ~ | 30 | | 26 | ~ | 26 | | 20 | }-20 | | Mrz 6 33 /||]]2/]|]fe2al pape 147Technical Data _ T-46-07-07 Ww = CD54/74HCT112 M SWITCHING CHARACTERISTICS (C, = 50 pF, input t, t= 6 ns) wy .n LIMITS ~ TEST 25C -40C to +85C +55C to +125C - a a CHARACTERISTIC CONDITION Ta UNITS oOo HC HCT 7T4HC 7T4HCT S4HC S4HCT: , Vcc 7 : no v Min, |Max. |Min. Max. |Min. |Max. |Min. Max. |Min. /Max. |Min. |Max. ry Propagation tous 2 1175;/ | | |220' | |] [26s] 7- Delay ten. 4.5 i35 | {35 | |4a4] | 4a] | 53 ) [53 |o- ns > CP toa. 6 }30}/--}-j,[37}/-;-|-|,4]-|]-= a 2 F155] };# | (1951 | |] [235 / - | t0Q,0 4.5 }31 | | 32 | | 39 | | 40 | | 47 | | 48 | ons: aA 6 = [26 | | | | 33 | | | | 40 | | 2 }iso| | | j225) | | fevof = Po fo. t~ RtoQ,.Q 4.5 |36 | |} 37 | } 45 | | 46 | | 54 | |-56-| ns mu . 2 6 {31'#}]]-~|38/-]]|46] fs: Output Transition trun 2 |76 } |} | | 95 | | | [110] -b- Time tra. 4.5 1/15 | |15 | |]19 | 19} | 22 | | 22-)- Os. 6 -~{123]/-};/-]-]1%/|f;-]~w] [= Input : . Cc - 10 | 10 | 10 | i0%; 10 } 10 | - pF Capacitance : HARRIS SEMICOND SECTOR . - 6NO- INPUT 2 v 92$-39233R1 vORK LEVEL GND INPUT LEVEL GNO 92CS-39234 54/74HC 54/74HCT Input Level Vec 3V Switching Voltage, Vs 50% Vee 13V 0 Fig. 2 - Transition times, propagation delay times, and setup and hold times,