6ES5945-7UA11 - Siemens - Product.Network

Pocket Guide CPU 945

Index Page
Explanation of the Operations List 1
Explanation of the Operands 3
Basic Operations
Boolean Logic Operations 8
Set/Reset Operations 8
Load Operations 10
Transfer Operations 16
Timer Operations 22
Counter Operations 22
Comparison Operations 24
Arithmetic Operations 28
Block Call Operations 30
Return Operations 34
”No” Operations 34
Stop Operation 34
Display Generation Operations 34
Supplementary Operations
Boolean Logic Operations 38
Bit Test Operations 40
Bit Set Operations 42
Set/Reset Operations 42
Timer and Counter Operations 44
Load and Transfer Operations 46
Conversion Operations 46
Shift and Rotate Operations 48
Jump Operations 50
Disable and Enable Interrupts 54
Decrement/Increment 54
Other Operations 56
System Operations
Set Operations 58
Load and Transfer Operations 58
Arithmetic Operations 64
Other Operations 66
Machine Code Listing 68
Alphabetical Index of Operations 80
List of Organization Blocks 84
List of Function Blocks 92
Data Block 1 96
Evaluation of CC 1 and CC 0 110

Explanation of the

Operations List

a

* not for LIR, LDI, LIM, MSA, MBA

Abbreviations Explanations

ACCU 1 ACCUulator 1, 32 bits (when ACCU 1 is

loaded, any prior existing contents are

shifted into ACCU 2)*

ACCU 2 ACCUulator 2, 32 bits

ACCU x-H High-word (bits 16 to 31) of ACCU x

ACCU x-L Low-word (bits 0 to 15) of ACCU x

CC0/CC1 Condition code 0/Condition code 1

CSF STEP 5 control system flowchart method of

representation

Formal

operand Expression with a maximum of 4 characters.

The first character must be a letter of the

alphabet.

LAD STEP 5 ladder diagram method of

representation

OS Stored overflow; This condition code is set if

at least one arithmetic operation causes an

overflow (used to detect arithmetic errors).

OV Overflow. This condition code is set, e.g., if

the number range is exceeded during

arithmetic operations.

PII Process image input

PIQ Process image output

RLO Result of logic operation

RLO Y

reloaded

N

The RLO does not change. The RLO cannot

be combined any further. When the next

binary operation takes place (but not

assignment operation), the RLO is reloaded.

Depending on whether the operation

affects the RLO, the RLO is combined further

or left unchanged according to the

operation and the status of the bit that was

scanned.

Explanation of the

Operations List

Abbreviations Explanations

RLO Y

dependent

Y /

N

The statement is executed only if the RLO is

”1”.

The statement is executed only on

positive/negative edge change of the RLO.

The statement is always executed.

RLO Y/N

affected The RLO is affected/not affected by the

operation.

STL STEP 5 statement list method of

representation

Explanation of the

Operands

Abbr Explanation Permissible

Value Range

for Operands

Size

in

Bits

BN Byte constant

(fixed-point number) - 128 to+127 8

C Counter

- for the bit test and set

operations (system

operations)

0 to 127

0.0 to 127.15 -

D Data word 0.0 to 255.15 1

DB Data block 0 to 255 -

DD Data double word 0 to 254 32

DH Constant (hexadecimal

code as double word) 0 to FFFF FFFF 32

DL Data word

(left byte) 0 to 255 8

DR Data word

(right byte) 0 to 255 8

DW Data word 0 to 255 16

DX Data block

(extension) 0 to 255 -

F Flag 0.0 to 255.7 1

FB Function block 0 to 255 -

FD Flag double word 0 to 252 32

FW Flag word 0 to 254 16

FX Function block

(extension) 0 to 255 -

FY Flag byte 0 to 255 8

I Input 0.0 to 127.7 1

a

1 For an overview of the organization blocks and their

functions see page 84

Abbr Explanation Permissible

Value Range

for Operands

Size

in

Bits

IB Input byte 0 to 127 8

ID Input double word 0 to 124 32

IW Input word 0 to 126 16

KB Constant (1 byte) 0 to 255 8

KC Constant

(count) 0 to 999 16

KF Constant

(fixed-point number) - 32768

to+32767 16

KG Constant

(floating-point number) ± 0.1469368

× 10-38 to

± 0.1701412

× 1039 and

0,0 × 100

32

KH Constant

(hexadecimal code) 0 to FFFF 16

KM Constant

(2 byte bit pattern) arbitrary bit

pattern

(16 bit)

16

KS Constant

(2 characters) any two

alphanumeric

characters

16

KT Constant (time) 0.0 to 999.3 16

KY Constant (2 bytes) 0 to 255

(per byte) 16

OB 1Organization block 0 to 255 -

OW Word of the extended I/O

area 0 to 254 16

PB Program block

(with block call and return

operations)

0 to 255 -

a

Abbr Explanation Permissible

Value Range

for Operands

Size

in

Bits

PW Peripheral word

- Digital inputs

- Analog inputs

- Digital outputs

- Analog outputs

0 to 126

128 to 254

0 to 126

128 to 254

16

PY Peripheral byte

- Digital inputs

- Analog inputs

- Digital outputs

- Analog outputs

0 to 127

128 to 255

0 to 127

128 to 255

8

Q Output 0.0 to 127.7 1

QB Output byte 0 to 127 8

QD Output double word 0 to 124 32

QW Output word 0 to 126 16

QY Byte of the extended I/O

area 0 to 255 8

RS System data area

System data word

- for load operations and

transfer operations

- for bit test and setting

operations

0 to 255

0.0 to 255.15

16

1

RT Extended system data area

System data word

- for load operations and

transfer operations

- for bit test and setting

operations

0 to 255

0.0 to 255.15

16

1

S Flag, additional 0.0 to 4095.7 1

SB Sequence block 0 to 255 -

SD Flag double word,

additional 0 to 4092 32

Abbr Explanation Permissible

Value Range

for Operands

Size

in

Bits

SW Flag word, additional 0 to 4094 16

SY Flag byte, additional 0 to 4095 8

T Timer

- for the bit test and set

operations (system

operations)

0 to 127

0.0 to 127.15 -

Basic Operations

for organization blocks (OB)

for program blocks (PB) for function blocks (FB)

for sequence blocks (SB)

Opera-

tion

(STL)

Permissible

Operands

1 RLO depend.

2 RLO affected

3 RLO reloaded

123

Typical

Execution Time

in µs

CPU 945

Function

AI, Q, F, T, C

S, D NYN 0.1

0.35 Scan operand for ”1” and combine with RLO through logic

AND

AN I, Q, F, T, C

S, D NYN 0.1

0.35 Scan operand for ”0” and combine with RLO through logic

AND

OI, Q, F, T, C

S, D NYN 0.1

0.35 Scan operand for ”1” and combine with RLO through logic

OR

ON I, Q, F, T, C

S, D NYN 0.1

0.35 Scan operand for ”0” and combine with RLO through logic

OR

O N Y Y 0.1 Combine AND operations through logic OR

A( N Y Y 0.1 Combine expressions enclosed in parentheses through logic

AND (8 levels)

O( N Y Y 0.1 Combine expressions enclosed in parentheses through logic

OR (8 levels)

) N Y N 0.1 Close parenthesis

(conclusion of a parenthetical expression)

Boolean Logic Operations

SI, Q, F

S, D YNY 0.1

0.45 Set operand to ”1”

RI, Q, F

S, D YNY 0.1

0.45 Reset operand to ”0”

Set/Reset Operations

Basic Operations

for organization blocks (OB)

for program blocks (PB) for function blocks (FB)

for sequence blocks (SB)

Opera-

tion

(STL)

Permissible

Operands

1 RLO depend.

2 RLO affected

3 RLO reloaded

123

Typical

Execution Time

in µs

CPU 945

Function

=I, Q, F

S, D YNY 0.1

0.45 Assign value of RLO to operand.

L IB N N N 0.1 Load an input byte from the PII into ACCU 1.

Byte n bits 0 to 7

L IW N N N 0.1 Load an input word from the PII into ACCU 1.

Byte n bits 8 to 15; byte n+1 bits 0 to 7

L ID N N N 0.2 Load an input double word into ACCU 1:

Byte n bits 24 to 31; byte n+1 bits 16 to 23;

Byte n+2 bits 8 to 15; byte n+3 bits 0 to 7;

L QB N N N 0.1 Load an output byte from the PIQ into ACCU 1.

Byte n bits 0 to 7

L QW N N N 0.1 Load an output byte from the PIQ into ACCU 1:

Byte n bits 8 to 15; byte n+1 bits 0 to 7

L QD N N N 0.2 Load an output double word into ACCU 1:

Byte n bits 24 to 31; byte n+1 bits 16 to 23;

Byte n+2 bits 8 to 15; byte n+3 bits 0 to 7;

L PY N N N 0.2* Load a peripheral word from the digital/analog inputs into

ACCU 1.

Byte n bits 0 to 7

Load Operations

a

*+ ready delay time of the I/O modules addressed

Set/Reset Operations (cont.)

Basic Operations

for organization blocks (OB)

for program blocks (PB) for function blocks (FB)

for sequence blocks (SB)

Opera-

tion

(STL)

Permissible

Operands

1 RLO depend.

2 RLO affected

3 RLO reloaded

123

Typical

Execution Time

in µs

CPU 945

Function

L PW N N N 0.2** Load a peripheral word from the digital/analog inputs into

ACCU 1:

Byte n bits 8 to 15; byte n+1 bits 0 to 7

L OY N N N 0.2* Load a byte of the extended I/O area into ACCU 1:

Byte n bits 0 to 7

L OW N N N 0.2** Load a word of the extended I/O area into ACCU 1:

Byte n bits 8 to 15; byte n+1 bits 0 to 7

L FY N N N 0.1 Load a flag byte into ACCU 1.

Byte n bits 0 to 7

L FW N N N 0.1 Load a flag word into ACCU 1:

Byte n bits 8 to 15; byte n+1 bits 0 to 7

L FD N N N 0.2 Load a flag double word into ACCU 1:

Byte n bits 24 to 31; byte n+1 bits 16 to 23;

Byte n+2 bits 8 to 15; byte n+3 bits 0 to 7

L SY N N N 0.35 Load an extended flag byte into ACCU 1:

Byte n bits 0 to 7

L SW N N N 0.35 Load an extended flag word into ACCU 1:

Byte n bits 8 to 15; byte n+1 bits 0 to 7

L SD N N N 0.45 Load an extended flag double word into ACCU 1:

Byte n bits 24 to 31; byte n+1 bits 16 to 23;

Byte n+2 bits 8 to 15; byte n+3 bits 0 to 7

Load operations (cont.)

a

*+ ready delay time of the I/O modules addressed

a

** +2× ready delay time of the I/O modules addressed

Basic Operations

Opera-

tion

(STL)

Permissible

Operands

1 RLO depend.

2 RLO affected

3 RLO reloaded

123

Typical

Execution Time

in µs

CPU 945

Function

L DL N N N 0.2 Load a data word (left-hand byte) of the current data block

into ACCU 1:

Byte n bits 0 to 7

L DR N N N 0.2 Load a data word (right-hand byte) of the current data

block into ACCU 1:

Byte n bits 0 to 7

L DW N N N 0.2 Load a data word of the current data block into ACCU 1:

Byte n bits 8 to 15; byte n+1 bits 0 to 7

L DD N N N 0.3

Load a data double word of the current data block into

ACCU 1:

Byte n bits 24 to 31; byte n+1 bits 16 to 23;

Byte n+2 bits 8 to 15; byte n+3 bits 0 to 7

L KB N N N 0.1 Load a constant (1-byte number) into ACCU 1

L KC N N N 0.2 Load a constant (2 characters in ASCII format) into ACCU 1

L KF N N N 0.2 Load a constant (fixed-point number) into ACCU 1

L KH N N N 0.2 Load a constant (hexadecimal code) into ACCU 1

L DH N N N 0.3 Load a data double word of the current data block into

ACCU 1

L KG N N N 0.3 Load a constant (floating-point-number) into ACCU 1

L KM N N N 0.2 Load a constant (bit pattern) into ACCU 1

for organization blocks (OB)

for program blocks (PB) for function blocks (FB)

for sequence blocks (SB)

Load operations (cont.)

Basic Operations

for organization blocks (OB)

for program blocks (PB) for function blocks (FB)

for sequence blocks (SB)

Opera-

tion

(STL)

Permissible

Operands

1 RLO depend.

2 RLO affected

3 RLO reloaded

123

Typical

Execution Time

in µs

CPU 945

Function

L KY N N N 0.2 Load a constant (bit pattern) into ACCU 1

L KT N N N 0.2 Load a constant (count in BCD) into ACCU 1

L KC N N N 0.2 Load a constant (count in BCD) into ACCU 1

L T, C N N N 0.1 Load a time or count (in binary code) into ACCU 1

LC T, C N N N 0.15 Load times or counts (in BCD) into ACCU 1

T IB N N N 0.1 Transfer the contents of ACCU 1-L (bits 0 to 7) to an input

byte (into the PII)

T IW N N N 0.1 Transfer the contents of ACCU 1-L to an input word

(into the PIQ): Bits 8 to 15 byte n; bits 0 to 7 byte n+1

T ID N N N 0.2

Transfer the contents of ACCU 1 to an input double word

(into the PII):

Bits 24 to 31 byte n; bits 16 to 23 byte n+1;

Bits 8 to 15 byte n+2; bits 0 to 7 byte n+3

T QB N N N 0.1 Transfer the contents of ACCU 1-L (bits 0 to 7) to an output

word (into the PIQ)

T QW N N N 0.1 Transfer the contents of ACCU 1 to an output word (into the

PIQ): Bits 8 to 15 byte n; bits 0 to 7 Byte n+1

Load Operations (cont.)

Transfer Operations

Basic Operations

for organization blocks (OB)

for program blocks (PB) for function blocks (FB)

for sequence blocks (SB)

a

*+ready delay time of the I/O modules addressed ** +2× ready delay time of the I/O modules addressed

Opera-

tion

(STL)

Permissible

Operands

1 RLO depend.

2 RLO affected

3 RLO reloaded

123

Typical

Execution Time

in µs

CPU 945

Function

T QD N N N 0.2

Transfer the contents of ACCU 1 to an output double word

(into the PIQ):

Bits 24 to 31 byte n; bits 16 to 23 byte n+1;

Bits 8 to 15 byte n+2; bits 0 to 7 byte n+3

T PY N N N 0.2*Transfer the contents of ACCU 1-L (bits 0 to 7) to an I/O byte

of the digital output modules with updating of the PIQ

or analog output modules

T PW N N N 0.2**

Transfer the contents of ACCU 1-L to an I/O byte of the

digital output modules with updating of the PIQ

or analog output modules.

Bits 8 to 15 byte n; bits 0 to 7 byte n+1

T OY N N N 0.2*Transfer the contents of ACCU 1-L (Bits 0 to 7) to a byte of

the extended peripherals of the digital or analog outputs

T OW N N N 0.2** Transfer the contents of ACCU 1-L to a word of the extended

peripherals of the digital or analog outputs:

Bits 8 to 15 byte n; bits 0 to 7 byte n+1

T FY N N N 0.1 Transfer the contents of ACCU 1-L (bits 0 to 7) to a flag byte

T FW N N N 0.1 Transfer the contents of ACCU 1-L to a flag word: Bits 8 to 15

byte n; bits 0 to 7 byte n+1

Transfer Operations (cont.)

Basic Operations

Opera-

tion

(STL)

Permissible

Operands

1 RLO depend.

2 RLO affected

3 RLO reloaded

123

Typical

Execution Time

in µs

CPU 945

Function

T FD N N N 0.2

Transfer the contents of ACCU 1 to a flag double word:

Bits 24 to 31 byte n; bits 16 to 23 byte n+1;

Bits 8 to 15 byte n+2; bits 0 to 7 byte n+3

T SY N N N 0.35 Transfer the contents of ACCU 1-L (bits 0 to 7) to an

extended flag byte

T SW N N N 0.35 Transfer the contents of ACCU 1-L to an extended flag word:

Bits 8 to 15 byte n; bits 0 to 7 byte n+1

T SD N N N 0.45

Transfer the contents of ACCU 1 to an extended flag double

word:

Bits 24 to 31 byte n; bits 16 to 23 byte n+1;

Bits 8 to 15 byte n+2; bits 0 to 7 byte n+3

T DL N N N 0.2 Transfer the contents of ACCU 1-L (bits 0 to 7) to a data word

(left-hand byte) of the current data block (DB/DX)

T DR N N N 0.2 Transfer the contents of ACCU 1-L (bits 0 to 7) to a data word

(right-hand byte) of the current data block(DB/DX)

T DW N N N 0.2 Transfer the contents of ACCU 1-L to a data word of the

current data block (DB/DX)

T DD N N N 0.3

Transfer the contents of ACCU 1 to a data double word of

the current data block (DB/DX):

Bits 24 to 31 byte n; bits 16 to 23 byte n+1;

Bits 8 to 15 byte n+2; bits 0 to 7 byte n+3

for organization blocks (OB)

for program blocks (PB) for function blocks (FB)

for sequence blocks (SB)

Transfer Operations (cont.)

Basic Operations

SP T Y N Y 0.1 Start a timer (stored in ACCU 1-L) as signal-contracting pulse

SE T Y N Y 0.1 Start a timer (stored in ACCU 1-L) as extended pulse

(signal-contracting and stretching)

SD T Y N Y 0.1 Start an on-delay timer (stored in ACCU 1) as extended pulse

SS T Y N Y 0.1 Start a stored on-delay timer (stored in ACCU 1)

SF T Y N Y 0.1 Start an off-delay timer (stored in ACCU 1)

R T Y N Y 0.1 Reset a timer

for organization blocks (OB)

for program blocks (PB) for function blocks (FB)

for sequence blocks (SB)

Opera-

tion

(STL)

Permissible

Operands

1 RLO depend.

2 RLO affected

3 RLO reloaded

123

Typical

Execution Time

in µs

CPU 945

Function

Counter Operations

CU C Y N Y 0.1 Counter counts up 1

CD C Y N Y 0.1 Counter counts down 1

S C Y N Y 0.1 Set counter with the value stored in ACCU 1-L (BCD number

from 0 to 999)

R C Y N Y 0.1 Reset a timer

Timer Operations

Basic Operations

for organization blocks (OB)

for program blocks (PB) for function blocks (FB)

for sequence blocks (SB)

Opera-

tion

(STL)

Permissible

Operands

1 RLO depend.

2 RLO affected

3 RLO reloaded

123

Typical

Execution Time

in µs

CPU 945

Function

!=F N Y N 0.1 Compare two fixed-point numbers for ”equal to”.

If ACCU 2-L=ACCU 1-L, the RLO is ”1”.

CC 1/CC 0 are affected.

><F N Y N 0.1 Compare two fixed-point numbers for ”not equal to”.

If ACCU 2-L ACCU 1-L, the RLO is ”1”.

CC 1/CC 0 are affected.

>F N Y N 0.1 Compare two fixed-point numbers for ”greater than”.

If ACCU 2-L>ACCU 1-L, the RLO is ”1”.

CC 1/CC 0 are affected.

>=F N Y N 0.1 Compare two fixed-point numbers for ”greater than or

equal to”. If ACCU 2-L ACCU 1-L, the RLO is ”1”.

CC 1/CC 0 are affected.

<F N Y N 0.1 Compare two fixed-point numbers for ”less than”.

If ACCU 2-L<ACCU 1-L, the RLO is ”1”.

CC 1/CC 0 are affected.

<=F N Y N 0.1 Compare two fixed-point numbers for ”less than or equal

to”. If ACCU 2-L ACCU 1-L, the RLO is ”1”.

CC 1/CC 0 are affected.

!=D N Y N 0.1 Compare two fixed-point double words for ”equal to”:

if ACCU 2=ACCU 1, the RLO is ”1”.

CC 1/CC 0 are affected.

><D N Y N 0.1 Compare two fixed-point double words for ”not equal to”:

if ACCU 2 ACCU 1, the RLO is ”1”.

CC 1/CC 0 are affected.

Comparison Operations

Basic Operations

for organization blocks (OB)

for program blocks (PB) for function blocks (FB)

for sequence blocks (SB)

Opera-

tion

(STL)

Permissible

Operands

1 RLO depend.

2 RLO affected

3 RLO reloaded

123

Typical

Execution Time

in µs

CPU 945

Function

>D N Y N 0.1 Compare two fixed-point double words for ”greater than”:

if ACCU 2 > ACCU 1, the RLO is ”1”.

CC 1/CC 0 are affected.

>=D N Y N 0.1 Compare two fixed-point double words for ”not equal to”:

if ACCU 2 ACCU 1, the RLO is ”1”

CC 1/CC 0 are affected.

<D N Y N 0.1 Compare two fixed-point double words for ”less than”:

if ACCU 2 < ACCU 1, the RLO is ”1”.

CC 1/CC 0 are affected.

<=D N Y N 0.1 Compare two fixed-point double words for ”less than or

equal to”: if ACCU 2 ACCU 1, the RLO is ”1”

CC 1/CC 0 are affected.

!=G N Y N 0.55 Compare two floating-point numbers for ”equal to”:

if ACCU 2 > ACCU 1, the RLO is ”1”.

CC 1/CC 0 are affected.

><G N Y N 0.55 Compare two floating-point numbers for ”not equal to”:

if ACCU 2 ACCU 1, the RLO is ”1”.

CC 1/CC 0 are affected.

>G N Y N 0.55 Compare two floating-point numbers for ”greater than”:

if ACCU 2 > ACCU 1, the RLO is ”1”.

CC 1/CC 0 are affected.

>=G N Y N 0.55 Compare two floating-point numbers for ”less than or equal

to”: if ACCU 2 ACCU 1, the RLO is ”1”.

CC 1/CC 0 are affected.

Comparison Operations (cont.)

Basic Operations

for organization blocks (OB)

for program blocks (PB) for function blocks (FB)

for sequence blocks (SB)

Opera-

tion

(STL)

Permissible

Operands

1 RLO depend.

2 RLO affected

3 RLO reloaded

123

Typical

Execution Time

in µs

CPU 945

Function

<G N Y N 0.55 Compare two floating-point numbers for ”less than”:

if ACCU 2 < ACCU 1, the RLO is ”1”.

CC 1/CC 0 are affected.

<=G N Y N 0.55 Compare two floating-point numbers for ”less than or equal

to”: if ACCU 2 ACCU 1, the RLO is ”1”.

CC 1/CC 0 are affected.

+F N N N 0.1 Add two fixed-point numbers:

ACCU 1-L=(ACCU 2-L)+(ACCU 1-L).

CC 1/CC 0/OV/OS can be evaluated.

- F N N N 0.1 Subtract one fixed-point number from another:

ACCU 1-L=(ACCU 2-L)-(ACCU 1-L).

CC 1/CC 0/OV/OS can be evaluated.

×F N N N 0.35 Multiply one fixed-point number by another:

ACCU 1=(ACCU 2-L)×(ACCU 1-L).

CC 1/CC 0/OV/OS can be evaluated.

: F N N N 0.4 Divide one fixed-point number by another:

(ACCU 2-L) : (ACCU 1-L). In ACCU 1-L : result; in ACCU 1-H :

remainder. CC 1/CC 0/OV/OS can be evaluated.

+D N N N 0.1 Subtract two fixed-point numbers (32 bits):

ACCU 1=ACCU 2+ACCU 1.

CC 1/CC 0/OV/OS can be evaluated.

Comparison Operations (cont.)

Arithmetic Operations

Basic Operations

for organization blocks (OB)

for program blocks (PB) for function blocks (FB)

for sequence blocks (SB)

a

Opera-

tion

(STL)

Permissible

Operands

1 RLO depend.

2 RLO affected

3 RLO reloaded

123

Typical

Execution Time

in µs

CPU 945

Function

- D N N N 0.1 Subtract two fixed-point numbers (32 bits):

ACCU 1=ACCU 2 - ACCU 1.

CC 1/CC 0/OV/OS can be evaluated.

+G N N N 0.75 Add two floating-point numbers:

ACCU 1=ACCU 2+ACCU 1.

CC 1/CC 0/OV/OS can be evaluated.

- G N N N 0.75 Subtract one floating-point number from another:

ACCU 1=ACCU 2 - ACCU 1.

CC 1/CC 0/OV/OS can be evaluated.

×G N N N 0.75 Multiply one floating-point number by another:

ACCU 1=ACCU 2×ACCU 1.

CC 1/CC 0/OV/OS can be evaluated.

: G N N N 1.35 Divide one floating-point number by another:

ACCU 1=ACCU 2 : ACCU 1.

CC 1/CC 0/OV/OS can be evaluated.

JU OB N N Y 1 Jump unconditionally to an organization block.

JU PB N N Y 1 Jump unconditionally to a program block.

JU FB N N Y 1.5 Jump unconditionally to a function block.

DOU FX N N Y 25.1 Jump unconditionally to a function block (FX).

Block Call Operations

Arithmetic Operations (cont.)

Basic Operations

for organization blocks (OB)

for program blocks (PB) for function blocks (FB)

for sequence blocks (SB)

a

1RLO is set to 1

Opera-

tion

(STL)

Permissible

Operands

1 RLO depend.

2 RLO affected

3 RLO reloaded

123

Typical

Execution Time

in µs

CPU 945

Function

JU SB N N Y 1 Jump unconditionally to a sequence block.

JC OB Y Y1Y1

0.1 Jump conditionallly to an organization block.

Time applies for RLO=1/RLO=0

JC PB Y Y1Y1

0.1 Jump conditionally to a program block.

Time applies for RLO=1/RLO=0

JC FB Y Y1Y1.5

0.35 Jump conditionally to a function block.

Time applies for RLO=1/RLO=0

DOC FX Y Y1Y25.1

0.45 Jump conditionally to a function block (FX).

Time applies for RLO=1/RLO=0

JC SB Y Y1Y1

0.1 Jump conditionally to a sequence block.

Time applies for RLO=1/RLO=0

A DB N N N 0.5 Call a data block.

CX DX N N N 0.6 Call an extended data block.

E DB N N N 45 to 60 Generate a data block.

The number of data words in the block must be stored in

ACCU 1.

GX DX N N N 45 to 60 Generate an extended data block.

The number of its data words must be stored in ACCU 1.

Block Call Operations (cont.)

Basic Operations

a

1 RLO is set to 1

Opera-

tion

(STL)

Permissible

Operands

1 RLO depend.

2 RLO affected

3 RLO reloaded

123

Typical

Execution Time

in µs

CPU 945

Function

BE N N Y 0.8 Block end (termination of a block)

BEC Y Y1Y0.8

0.1 Block end, conditional

Time applies for RLO=1/RLO=0

BEU N N Y 0.8 Block end, unconditional

NOP 0 N N N 0.1 No operation

NOP 1 N N N 0.1 No operation

STP N N N 32 Stop at the end of program execution: current program

processing is brought to an end; the PIQ is output;

afterwards, the PLC enters STOP

BLD

0 to 255 N N N 0.1 Is treated by the CPU like a no-operation.

BLD

130 N N N 0.1 Display generation operation for the programmer:

carriage return generates blank line

Return Operations

for organization blocks (OB)

for program blocks (PB) for function blocks (FB)

for sequence blocks (SB)

Display Generation Operations

”No” Operations

Stop Operation

Basic Operations

Stop-Operation

for organization blocks (OB)

for program blocks (PB) for function blocks (FB)

for sequence blocks (SB)

a

Opera-

tion

(STL)

Permissible

Operands

1 RLO depend.

2 RLO affected

3 RLO reloaded

123

Typical

Execution Time

in µs

CPU 945

Function

BLD

131 N N N 0,1 Display generation operation for the programmer:

switch over to statement list (STL).

BLD

132 N N N 0,1 Display generation operation for the programmer:

switch over to control system flowchart (CSF).

BLD

133 N N N 0,1 Display generation operation for the programmer:

switch over to ladder diagram (LAD).

BLD

255 N N N 0,1 Display generation operation for the programmer:

segment termination.

Display Generation Operations (cont.)

Supplementary Operations

for organization blocks (OB)

for program blocks (PB) for function blocks (FB)

for sequence blocks (SB)

a

* plus execution time of the substituted operation

Oper-

ation

(STL)

Permissible

Operands

1 RLO depend.

2 RLO affected

3 RLO reloaded

123

Typical

Execution Time

in µs

CPU 945

Function

A= Formal oper.

I, Q, F, T, C N Y N 0.5*AND operation: scan formal operand for ”1”.

(Data type: BI)

AN= Formal oper.

I, Q, F, T, C N Y N 0.5*AND operation: scan formal operand for ”0”.

(Data type: BI)

O= Formal oper.

I, Q, F, T, C N Y N 0.5*OR operation: scan formal operand for ”1”.

(Data type: BI)

ON= Formal oper.

I, Q, F, T, C N Y N 0.5*OR operation: scan formal operand for ”0”.

(Data type: BI)

AW N N N 0.1

And ACCU 2-L and ACCU 1-L (word operation);

result in ACCU 1-L.

Result can be evaluated via CC 1/CC 0.

ACCU 1-H remains unchanged.

OW N N N 0.1

Or ACCU 2-L and ACCU 1-L (word operaton);

result in ACCU 1-L.

Result can be evaluated via CC 1/CC 0.

ACCU 1-H remains unchanged.

XOW N N N 0.1

Exclusive-OR ACCU 2-L and ACCU 1-L (word operation);

result in ACCU 1-L.

Result can be evaluated via CC 1/CC 0.

ACCU 1-H remains unchanged.

Boolean Logic Operations

Supplementary Operations

for organization blocks (OB)

for program blocks (PB) for function blocks (FB)

for sequence blocks (SB)

Oper-

ation

(STL)

Permissible

Operands

1 RLO depend.

2 RLO affected

3 RLO reloaded

123

Typical

Execution Time

in µs

CPU 945

Function

TB I, Q, F N Y N 0.2 Test bit of an input, output or flag byte for ”1”

TB T, C N Y N 0.2 Test a timer or counter word bit for ”1”

TB D N Y N 0.35 Test a data word bit (in a DB/DX) for ”1”

TB RS N Y N 0.35 Test a data word bit in the system data range for ”1”

TB RT N Y N 0.35 Test bit of a data word in the extended area of the system

data for ”1”

TBN I, Q, F N Y N 0.2 Test bit of an input, output or flag byte for ”0”

TBN T, C N Y N 0.2 Test a timer or counter word bit for ”0”

TBN D N Y N 0.35 Test a data word bit (in a DB/DX) for ”0”

TBN RS N Y N 0.35 Test a data word bit in the system data range for ”0”

TBN RT N Y N 0.35 Test bit of a data word in the extended area of the system

data for ”0”

Bit Test Operations

Supplementary Operations

a

* plus execution time of the substituted operation

S= Formal oper.

I, Q, F Y N Y 0.5* Set a formal operand, (with RLO =1).

(Data type: BI)

RB= Formal oper.

I, Q, F Y N Y 0.5* Reset a formal operand, (with RLO =1).

(Data type: BI)

== Formal oper.

I, Q, F Y N Y 0.5* The value of the RLO is assigned to the status of the formal

operand. (Data type: BI)

for organization blocks (OB)

for program blocks (PB) for function blocks (FB)

for sequence blocks (SB)

Oper-

ation

(STL)

Permissible

Operands

1 RLO depend.

2 RLO affected

3 RLO reloaded

123

Typical

Execution Time

in µs

CPU 945

Function

SU I, Q, F N N Y 0.2 One input bit (in PII); set an output bit (in PIQ) or a flag bit

unconditionally

SU T, C N N Y 0.2 Set a timer or counter word bit unconditionally

SU D N N Y 0.45 Set a data word bit (in a DB/DX) unconditionally

RU I, Q, F N N Y 0.2 One input bit (in PII); reset an output bit (in PIQ) or a flag bit

unconditionally

RU T, C N N Y 0.2 Reset a timer or counter word bit unconditionally

RU D N N Y 0.45 Reset a data word bit unconditionally

Set/Reset Operations

Bit Set Operations

Supplementary Operations

a

* plus execution time of the substituted operation

Oper-

ation

(STL)

Permissible

Operands

1 RLO depend.

2 RLO affected

3 RLO reloaded

123

Typical

Execution Time

in µs

CPU 945

Function

FR T, C Y N Y 0.1

Enable a timer/counter for cold restart.

If RLO=”1”,

- 'FR T' restarts the timer

- 'FR C' sets, decrements, or increments the counter

FR= Formal oper.

T, C Y N Y 0.5* Enable formal operand (timer/counter) for cold re-start (for

detailed description, see ”FR” operation)

RD= Formal oper.

T, C Y N Y 0.5* Reset a formal operand (digital), (with RLO =1)

SP= Formal oper.

TY N Y 0.5*Start a timer (formal operand) as pulse with the value stored

in ACCU 1

SD= Formal oper.

TY N Y 0.5*Start an on-delay timer (formal operand) with the value

stored in ACCU 1

SEC= Formal oper.

T, C Y N Y 0.5*

Start a timer (formal operand) as extended pulse with the

value stored in ACCU 1, or set a counter (formal operand)

with the next indicated count value

SSU= Formal oper.

T, C Y N Y 0.5*Start a stored on-delay timer (formal operand) with the

value stored in ACCU 1, or increment a counter (formal

operand)

SFD= Formal oper.

T, C Y

Y N Y 0.5*Start an off-delay timer ( ) (formal operand) with the value

stored in ACCU 1, or decrement a counter ( ) (formal

operand)

for organization blocks (OB)

for program blocks (PB) for function blocks (FB)

for sequence blocks (SB)

Timer and Counter Operations

Supplementary Operations

L= Formal oper.

I, Q, F, T, C N N N 0.5*Load the value of the formal operand into ACCU 1 (Data

type: BY, W, D; Actual operands: FD, FY, FW, IB, IW, ID, QB,

QW, QD, PY, PW, DL, DR, DW, DD, RS, RT, C, T)

LC= Formal oper.

T, C N N N 0.5*Load the value of the formal operand in BCD code into

ACCU 1.

LW= Formal oper. N N N 0.45 Load a formal operand bit pattern into ACCU 1 (Parameter

type: D; data type: KF, KH, KM, KY, KS, KT, KC)

LDW= Formal oper. N N N 0.55 Load the bit pattern (32 bits) of a formal operand into

ACCU 1 (parameter type: D; data type: KG)

T= Formal oper.

I, Q, F N N N 0.5*Transfer the contents of ACCU 1 to the formal operand

(Data type: BY, W, D; Actual operands: FD, FY, FW, IB, IW,

ID, QB, QW, QD, PY, PW, DL, DR, DW, DD, RS, RT)

for organization blocks (OB)

for program blocks (PB) for function blocks (FB)

for sequence blocks (SB)

Oper-

ation

(STL)

Permissible

Operands

1 RLO depend.

2 RLO affected

3 RLO reloaded

123

Typical

Execution Time

in µs

CPU 945

Function

Conversion Operations

a

* plus execution time of the substituted operation

CFW N N N 0.1 Form one's complement of ACCU 1-L (Bits 0 to 15).

CSW N N N 0.1 Form two's complement of ACCU 1-L (Bits 0 to 15).

CC 1/CC 0 and OV are affected

CSD N N N 0.1 Form two's complement of ACCU 1 (Bits 0 to 31).

CC1/CC0 and OV are affected.

DEF N N N 0.55 Convert a 16-bit fixed point from BCD into binary.

Load and Transfer Operations

Supplementary Operations

for organization blocks (OB)

for program blocks (PB) for function blocks (FB)

for sequence blocks (SB)

Oper-

ation

(STL)

Permissible

Operands

1 RLO depend.

2 RLO affected

3 RLO reloaded

123

Typical

Execution Time

in µs

CPU 945

Function

DUF N N N 0.65 Convert a 16-bit fixed point from binary into BCD

DED N N N 0.55 Convert a 32-bit fixed point from BCD into binary

DUD N N N 0.80 Convert a 32-bit fixed point from binary into BCD

FDG N N N 0.45 Convert a 32-bit fixed-point number into a floating-point

number

GFD N N N 0.45 Convert a floating-point number into a 32-bit fixed-point

number

SLW Parameter

n=0 to 15 N N N 0.1

Shift the contents of ACCU 1-L (word) to the left by the

value specified in the parameter.

Positions becoming vacant are padded with zeros.

CC 1/CC 0 are affected

SRW Parameter

n=0 to 15 N N N 0.1

Shift the contents of ACCU 1-L (word) to the right by the

value specified in the parameter.

Positions becoming vacant are padded with zeros.

CC 1/CC 0 are affected

SLD Parameter

n=0 to 32 N N N 0.1

Shift the contents of ACCU 1 (double word) to the left by the

value specified in the parameter.

Positions becoming vacant are padded with zeros.

CC 1/CC 0 are affected

Conversion Operations (cont.)

Shift and Rotate Operations

Supplementary Operations

for organization blocks (OB)

for program blocks (PB) for function blocks (FB)

for sequence blocks (SB)

Oper-

ation

(STL)

Permissible

Operands

1 RLO depend.

2 RLO affected

3 RLO reloaded

123

Typical

Execution Time

in µs

CPU 945

Function

SSW Parameter

n=0 to 15 N N N 0.1

Shift the contents of ACCU 1-L (word) to the right by the

value specified in the parameter.

Positions becoming vacant are padded with the sign (bit 15).

CC 1/CC 0 are affected.

SSD Parameter

n=0 to 32 N N N 0.1

Shift the contents of ACCU 1 (double word) to the right by

the value specified in the parameter.

Positions becoming vacant are padded with the sign (bit 31).

CC 1/CC 0 are affected.

RLD Parameter

n=0 to 32 N N N 0.1

Rotate the contents of ACCU 1 (double word) to the left.

Positions becoming vacant are padded with the shifted bits.

CC 1/CC 0 are affected.

RRD Parameter

n=0 to 32 N N N 0.1

Rotate the contents of ACCU 1 (double word) to the right.

Positions becoming vacant are padded with the shifted bits.

CC 1/CC 0 are affected.

Jump Operations

a

1 RLO is set to ”1”.

JU= Symb. address

max. 4 charact. N N N 0.25 Unconditional jump to a symbolic address.

JC= Symb. address

max. 4 charact. YY

1Y0.25

0.1

Conditional jump to a symbolic address, exectued only if

RLO=1

(if RLO=”0”, it is set to ”1”)

Time applies for RLO=1/RLO=0

Shift and Rotate Operations (cont.)

Supplementary Operations

for organization blocks (OB)

for program blocks (PB) for function blocks (FB)

for sequence blocks (SB)

Oper-

ation

(STL)

Permissible

Operands

1 RLO depend.

2 RLO affected

3 RLO reloaded

123

Typical

Execution Time

in µs

CPU 945

Function

JZ= Symb. address

max. 4 charact. NNN 0.25

0.1

Jump if the result is zero. The jump is made only if CC 1=0

and CC 0=0. The RLO is not changed.

Time applies for RLO=1/RLO=0

JN= Symb. address

max. 4 charact. NNN 0.25

0.1

Jump if the result is not zero. The jump is made only if

CC 1 CC 0 . The RLO is not changed.

Time applies for RLO=1/RLO=0

JP= Symb. address

max. 4 charact. NNN 0.25

0.1

Jump if the result>0. The jump is made only if

CC 1=1 und CC 0=0. The RLO is not changed.

Time applies for RLO=1/RLO=0

JM= Symb. address

max. 4 charact. NNN 0.25

0.1

Jump if the result <0. The jump is made only if CC 1=0 and

CC 0=1. The RLO is not changed.

Time applies for RLO=1/RLO=0

JO= Symb. address

max. 4 charact. NNN 0.25

0.1

Jump on overflow: the jump is only made if the OV bit is set

to 1. The RLO is not changed.

Time applies for RLO=1/RLO=0

JOS= Symb. address

max. 4 charact. NNN 0.25

0.1

Jmp on overflow latched: the jump is only made if the OS bit

is set to 1.

The RLO is not changed.

Time applies for RLO=1/RLO=0

JUR N N N 0.25 Linear program execution is interrupted and continued at

the position determined by the jump distance.

(Jump distance in words: -32768 to+32767)

Jump Operations (cont.)

Supplementary Operations

for organization blocks (OB)

for program blocks (PB) for function blocks (FB)

for sequence blocks (SB)

Oper-

ation

(STL)

Permissible

Operands

1 RLO depend.

2 RLO affected

3 RLO reloaded

123

Typical

Execution Time

in µs

CPU 945

Function

IA N N N 28 Disable interrupt: I/O interrupt, time OB execution and time

interrupt OB execution are disabled (does not apply for

OBs 26, 33, 35)

RA N N N 30 to 35 Enable interrupt: Cancels the effect of the IA operation

(does not apply for OBs 26, 33, 35)

SIM N N N 33 to 38 Set interrupt mask (32 bits)

LIM N N N 29 Read interrupt mask (32 bits)

Decrement/Increment

DParameter

n=0 to 255 N N N 0.1 Decrement ACCU 1-LL by the number specified in the

parameter (no carry)

IParameter

n=0 to 255 N N N 0.1 Increment ACCU 1-LL by the number specified in the

parameter (no carry)

Disable and Enable Interrupts

Supplementary Operations

for organization blocks (OB)

for program blocks (PB) for function blocks (FB)

for sequence blocks (SB)

Oper-

ation

(STL)

Permissible

Operands

1 RLO depend.

2 RLO affected

3 RLO reloaded

123

Typical

Execution Time

in µs

CPU 945

Function

DO= Formal oper.

DB, PB, FB, SB,

OB N N N 0.5*Process a block. (Only C DB, JU PB, JU FB,

JU SB and JU OB can be substituted)

DO DW** N N N 0.25 Process data word. The next operation is combined through

logic OR with the parameter specified in the data word and

executed**

DO FW** N N N 0.25 Process flag word. The next operation is combined through

logic OR with the parameter specified in the flag word and

executed**

Other Operations

*plus execution time of the substituted operation

** Permissible operations: L, T3

A, AN, O, ON;1LC

S, R, =;2JU=, JC=, JZ=, JN=, JP=, JM=, JO=, SLW, SRW;

FR T, R T, SF T, SR T, SP T, SS T, SE T; SLD, RLD, SSD, RRD,

FR C, R C, S C, CR C, CU C; D, I; ADD BN;

QDB, TNB, TNW, JU, JC

1only for I, Q, F, T, C

2only for I, Q, F

3only for IB, QB, IW, QW, ID, QD, FY, FW, FD, DL, DR,

DW, DD, RS, RT, PY, PT, OY, OW

System Operations

a

LIR 0 ( ACCU 1-L)

1 ( ACCU 1-H)

2 ( ACCU 2-L)

3 ( ACCU 2-H)

8 ( DBL)

N N N 0.25* Load the 16-bit register specified with the contents of a

memory word (addressed by ACCU 1)

TIR 0 ( ACCU 1-L)

1 ( ACCU 1-H)

2 ( ACCU 2-L)

3 ( ACCU 2-H)

8 ( DBL)

N N N 0.25* The contents of the specified 16-bit register are transferred

to a memory word (addressed by ACCU 1)

LDI A1 ( ACCU 1)

A2 ( ACCU 2)

SA ( SAZ)

BR ( BR

register)

N N N 0.4** Load the specified 32-bit register with the contents of a

memory word n (addressed by ACCU 1) and the following

n+1, n+2 and n+3

for organization blocks (OB)

for program blocks (PB) for function blocks (FB)

for sequence blocks (SB)

Oper-

ation

(STL)

Permissible

Operands

1 RLO depend.

2 RLO affected

3 RLO reloaded

123

Typical

Execution Time

in µs

CPU 945

Function

SU RS N N Y 0.45 Set a bit in the system data area (register) unconditionally

SU RT N N Y 0.45 Set a bit in the extended system data area (register)

unconditionally

RU RS N N Y 0.45 Reset a bit in the system data area (register) unconditionally

RU RT N N Y 0.45 Reset a bit in the extended system data area (register)

unconditionally

Set Operations

Load and Transfer Operations

*When accessing the I/O area, + 2×ready delay time of the

referenced I/O modules ** When accessing the I/O area, + 4×ready delay time of the

referenced I/O modules

System Operations

for organization blocks (OB)

for program blocks (PB) for function blocks (FB)

for sequence blocks (SB)

a

Oper-

ation

(STL)

Permissible

Operands

1 RLO depend.

2 RLO affected

3 RLO reloaded

123

Typical Execution

Time

in µs

CPU 945

Function

TDI A1 ( ACCU 1)

A2 ( ACCU 2)

SA ( SAZ)

BR ( BR

register)

N N N 0.3* Transfer the contents of the specified 32-bit register to a

memory word n (addressed by ACCU 1) and to the following

n+1, n+2 and n+3

TNW Parameter

n=0 to 255 N N N 0.15

+

n × 0.35**

Block transfer word by word

End address of target area: ACCU 1

End address of source area: ACCU 2

Only even addresses may be used. After execution of the

operation, the ACCUs are decremented 2 times the number

of words.

TNB Parameter

n=0 to 255 N N N 0.15

+

n × 0.35**

Block transfer byte by byte

End address of target area: ACCU 1

End address of source area: ACCU 2

After execution of the operation, the ACCUs are

decremented by the number of bytes

L RS N N N 0.2 Load a word from the system data range into ACCU 1

L RT N N N 0.2 Load a word from the extended system data range into

ACCU 1

T RS N N N 0.2 Transfer a word to the system data area

T RT N N N 0.2 Transfer a word to the extended system data area

Load and Transfer Operations (cont.)

** When accessing the I/O area, + 1×ready delay time of the

referenced I/O modules

*When accessing the I/O area, + 4×ready delay time of the

referenced I/O modules

((Seite 61a))

System Operations

for organization blocks (OB)

for program blocks (PB) for function blocks (FB)

for sequence blocks (SB)

Oper-

ation

(STL)

Permissible

Operands

1 RLO depend.

2 RLO affected

3 RLO reloaded

123

Typical

Execution Time

in µs

CPU 945

Function

MBR Parameter

0 to FFFFFHN N N 0.25 Load a 20-bit constant into the BR register

ABR Offset

- 32768 to

+32767

N N N 0.25 The offset is multiplied by 2 (word offset). Add the result to

the contents of the BR register

LRW Offset

- 32768 to

+32767

N N N 0.35 The offset is multiplied by 2 (word offset). Add the result to

the contents of the BR register and load the word with this

address into ACCU 1-L

LRD Offset

- 32768 to

+32767

N N N 0.45 The offset is multiplied by 2 (word offset). Add the result to

the contents of the BR register and load the double word

with this address into ACCU 1-L

TRW Offset

- 32768 to

+32767

N N N 0.35 The offset is multiplied by 2 (word offset). Add the result to

the contents of the BR register and transfer the contents of

ACCU 1-L to the word with this address

TRD Offset

- 32768 to

+32767

N N N 0.45 The offset is multiplied by 2 (word offset).

Add the result to the contents of the BR register and transfer

the contents of ACCU 1 to the double word with this address

MAS N N N 0.25 Transfer the contents of ACCU 1 (bits 31 to 20 remain

unchanged) to the base address register

MAB N N N 0.1 Transfer the contents of ACCU 1 (bits 31 to 20 remain

unchanged) to the base address register

Load and Transfer Operations (cont.)

System Operations

for organization blocks (OB)

for program blocks (PB) for function blocks (FB)

for sequence blocks (SB)

Oper-

ation

(STL)

Permissible

Operands

1 RLO depend.

2 RLO affected

3 RLO reloaded

123

Typical

Execution Time

in µs

CPU 945

Function

MSA N N N 0.1 Transfer the contents of the step address counter to ACCU 1

(bits 31 to 20 are set to zero ) (address of the next command)

MSB N N N 0.1 Transfer the contents of the step address counter to the base

address register (address of the next command)

MBA N N N 0.1 Transfer the contents of the base address register to ACCU 1

(bits 31 to 20 are set to zero)

MBS N N N 0.25 Transfer the contents of the base address register to the step

address counter

Arithmetic Operations

ADD BF

- 128 to+127 N N N 0.1 Add byte constant (fixed point) to ACCU 1-L.

ADD KF

- 32768 to

+32767

N N N 0.25 Add fixed-point constant (word) to ACCU 1-L.

ADD DH

0 to FFFF FFFF N N N 0.35 Add constant (hexadecimal code as double word) to

ACCU 1.

Load and Transfer Operations (cont.)

System Operations

for organization blocks (OB)

for program blocks (PB) for function blocks (FB)

for sequence blocks (SB)

Oper-

ation

(STL)

Permissible

Operands

1 RLO depend.

2 RLO affected

3 RLO reloaded

123

Typical

Execution Time

in µs

CPU 945

Function

STS N N N 44 Stop operation. Program processing is interrupted

immediately after this operation

STP N N N 32 Stop at the end of program execution: current program

execution is brought to an end: the PIQ is output; then the

programmable controller enters the STOP status

TAK N N N 0.1 Swap the contents of ACCU 1 and ACCU 2

Other Operations

Machine Code

Listing

Machine Code

B0

LR

B1

LR

B2

LR

B3

LR

Opera-

tion Ope-

rand

0000 NOP 0

0100 CFW

020

d0

dLT

030

l0

lTNB

040

d0

dFR T

0500 BEC

060

c0

cFR=

070

c0

cA=

0800 IA

0880 RA

0900 CSW

0A0

a0

aLFY

0B0

a0

aTFY

0C0

d0

dLD T

0D0

i0

iJO=

Explanation of indices

a + byte address

b + bit address

c + parameter address

d + timer number

e + constant

f + block number

g + word address

h + number of shifts

i + relative jump address

k + register address

l + block length

m + jump displacement (16 bits)

n + value

o + counter number

Machine Code

B0

LR

B1

LR

B2

LR

B3

LR

Opera-

tion Ope-

rand

0E0

c0

cLD=

0F0

c0

cO=

100

e0

eBLD 0-255

1082 BLD 130

1083 BLD 131

1084 BLD 132

1085 BLD 133

10FF BLD 255

110

n0

nI

120

a0

aLFW

130

a0

aTFW

140

d0

dSF T

150

i0

iJP=

160

c0

cSFD=

170

c0

cS=

190

n0

nD

1A0

a0

aLFD

1B0

a0

aTFD

1C0

d0

dSE T

1D0

f0

fJC FB

1E0

c0

cSEC=

1F0

c0

c==

200

f0

fCDB

2120 >F

2140 <F

Machine Code

B0

LR

B1

LR

B2

LR

B3

LR

Opera-

tion Ope-

rand

2160 ><F

2180 !=F

21A0 >=F

21C0 <=F

220

g0

gLDL

230

g0

gTDL

240

d0

dSD T

250

i0

iJM=

260

c0

cSD=

270

c0

cAN=

280

e0

eLKB

290

h0

hSLD

2A0

g0

gLDR

2B0

g0

gTDR

2C0

d0

dSS T

2D0

i0

iJU=

2E0

c0

cSSU=

2F0

c0

cON=

30010

e0

e

LKC

30020

e0

e

LKT

30040

e0

e

LKF

30100

e0

e

LKS

30200

e0

e

LKY

30400

e0

e

LKH

30800

e0

e

LKM

13 word command with B4 and B5, filled with 0e

Machine Code

B0

LR

B1

LR

B2

LR

B3

LR

Opera-

tion Ope-

rand

3120 >G

3140 <G

3160 ><G

3180 !=G

31A0 >=G

31C0 <=G

320

g0

gLDW

330

g0

gTDW

340

d0

dSP T

350

i0

iJN=

360

c0

cSP=

370

c0

cRB=

38000

e0

e

LKG

1

38400

e0

e

LDH

1

3920 >D

3940 <D

3960 ><D

3980 !=D

39A0 >=D

39C0 <=D

3A0

g0

gLDD

3B0

g0

gTDD

3C0

d0

dRT

3D0

f0

fJU FB

3E0

c0

cRD=

3F0

c0

cLW=

Machine Code

B0

LR

B1

LR

B2

LR

B3

LR

Opera-

tion Ope-

rand

4000

kLIR

4100 AW

420

o0

oLC

430

l0

lTNW

440

o0

oFR C

450

i0

iJZ=

460

c0

cL=

4800

kTIR

4900 OW

4A0

a0

aLIB

4A8

a0

aLQB

4B0

a0

aTIB

4B8

a0

aTQB

4C0

o0

oLD C

4D0

f0

fJC OB

4E0

g0

gDO FW

4F0

g0

gLRT

500

e0

eADD BN

5100 XOW

520

a0

aLIW

528

a0

aLQW

530

a0

aTIW

538

a0

aTQW

540

o0

oCD C

550

f0

fJC PB

Machine Code

B0

LR

B1

LR

B2

LR

B3

LR

Opera-

tion Ope-

rand

560

c0

cLDW=

570

a0

aLOW

58000

e0

e

ADD KF

5900 -F

5A0

a0

aLID

5A8

a0

aLQD

5B0

a0

aTID

5B8

a0

aTQD

5C0

o0

oSC

5D0

f0

fJC SB

5F0

a0

aLOY

6000 :F

6003 :G

6004 xF

60050

e0

e

ADD DH1

6007 xG

6009 -D

600B -G

600C000

i0

iJOS=

600D +D

600F +G

6100

hSLW

620

g0

gLRS

630

g0

gTRS

640

h0

hRLD

a

13 word command with B4 and B5, filled with 0e

Machine Code

B0

LR

B1

LR

B2

LR

B3

LR

Opera-

tion Ope-

rand

6500 BE

6501 BEU

660

c0

cT=

68000

e0

e

LRW

680

h1SSW

6802 GFD

68030

e0

e

TRW

68040

e0

e

LRD

68050

e0

e

TRD

6806 FDG

6807 CSD

6808 DUF

680A DUD

680B LDI A1

680C DEF

680E DED

680F TDI A1

6819 MAS

6829 MAB

682B LDI A2

682F TDI A2

6849 MSA

684B LDI SA

684F TDI SA

6869 MSB

Machine Code

B0

LR

B1

LR

B2

LR

B3

LR

Opera-

tion Ope-

rand

6889 MBA

6899 MBS

68AB LDI BR

68AF TDI BR

6900

hSRW

6C0

o0

oCU C

6D0

f0

fJU OB

6E0

g0

gDO DW

6F0

g0

gTRT

7000 STS

7002 TAK

7003 STP

700B0

m

0

m

0

m

0

m

JUR

700C LIM

700D SIM

700E00

b0

g0

g

RU BT

700E40

b0

g0

g

SU RT

700E80

b0

g0

g

TBN RT

700EC0

b0

g0

g

TB RT

701500

b0

o0

o

RU C

701540

b0

o0

o

SU C

701580

b0

o0

o

TBN C

7015C0

b0

o0

o

TB C

702500

b0

d0

d

RU T

702540

b0

d0

d

SU T

Machine Code

B0

LR

B1

LR

B2

LR

B3

LR

Opera-

tion Ope-

rand

702580

b0

d0

d

TBN T

7025C0

b0

d0

d

TB T

703800

b0

a0

a

RU I

703800

b8

a0

a

RU Q

703840

b0

a0

a

SU I

703840

b8

a0

a

SU Q

703880

b0

a0

a

TBN I

703880

b8

a0

a

TBN Q

7038C0

b0

a0

a

TB I

7038C0

b8

a0

a

TB Q

704600

b0

g0

g

RU D

704640

b0

g0

g

SU D

704680

b0

g0

g

TBN D

7046C0

b0

g0

g

TB D

704900

b0

a0

a

RU F

704940

b0

a0

a

SU F

704980

b0

a0

a

TBN F

7049C0

b0

a0

a

TB F

705700

b0

g0

g

RU RS

705740

b0

g0

g

SU RS

705780

b0

g0

g

TBN RS

7057C0

b0

g0

g

TB RS

710

h0

hSSD

720

a0

aLPY

730

a0

aTPY

Machine Code

B0

LR

B1

LR

B2

LR

B3

LR

Opera-

tion Ope-

rand

740

h0

hRRD

750

f0

fJU PB

760

c0

cDO=

770

a0

aTQW

7801010

f0

fDOU FX

7802090

f0

fDOC FX

7803110

f0

fCX DX

7804000

f0

fGX DX

7805000

f0

fGDB

780

e90

e0

eMBR

780A0

e0

e

ABR

780B0

b0

a0

a

AS

781B0

b0

a0

a

OS

782B0

b0

a0

a

SS

783B0

b0

a0

a

=S

783F00

b0

g0

g

AD

783F10

b0

g0

g

OD

783F20

b0

g0

g

AN D

783F30

b0

g0

g

ON D

783F40

b0

g0

g

SD

783F50

b0

g0

g

RD

783F60

b0

g0

g

=D

784B0

b0

a0

a

AN S

785B0

b0

a0

a

ON S

786B0

b0

a0

a

RS

Machine Code

B0

LR

B1

LR

B2

LR

B3

LR

Opera-

tion Ope-

rand

78AB00

a0

a

LSY

78BB00

a0

a

TSY

78CB00

a0

a

LSW

78DB00

a0

a

TSW

78EB00

a0

a

LSD

78FB00

a0

a

TSD

7900 +F

7A0

a0

aLPW

7B0

a0

aTPW

7C0

o0

oRC

7D0

f0

fJU SB

7F0

a0

aTOY

80

b0

a0

aAF

88

b0

a0

aOF

90

b0

a0

aSF

98

b0

a0

a=F

A0

b0

a0

aAN F

A8

b0

a0

aON F

B0

b0

a0

aRF

B80

o0

oAC

B90

o0

oOC

BA00 A(

BB00 O(

BC0

o0

oAN C

BD0

o0

oON C

Machine Code

B0

LR

B1

LR

B2

LR

B3

LR

Opera-

tion Ope-

rand

BF00 )

C0

b0

a0

aAI

C0

b8

a0

aAQ

C8

b0

a0

aOI

C8

b8

a0

aOQ

D0

b0

a0

aSI

D0

b8

a0

aSQ

D8

b0

a0

a=I

D8

b8

a0

a=Q

E0

b0

a0

aAN I

E0

b8

a0

aAN Q

E8

b0

a0

aON I

E8

b8

a0

aON Q

F0

b0

a0

aRI

F0

b8

a0

aRQ

F80

d0

dAT

F90

d0

dOT

FA0

i0

iJC=

FB00 O

FC0

d0

dAN T

FD0

d0

dON T

FFFF NOP1

Alphabetical Index of

Operations

Operation Page

! = D 24, 71

! G 26, 71

!=F 24, 70

)8,79

+ D 28, 73

+ G 30, 73

+F 28, 78

- D 30, 73

- F 28, 73

- G 30, 73

:F 28, 73

:G 30, 73

< = D 26, 71

< D 26, 71

< =F 24, 70

< F 24, 69

<=G 28, 71

<G 28, 71

=10, 77-79

== 42, 69

> = D 26, 71

> = G 26, 71

> D 26, 71

Operation Page

> G 26, 71

>< D 24, 71

><F 24, 70

><G 26, 71

>=F 24, 70

>F 24, 69

A8, 77-79

A( 8, 78

A= 38, 68

ABR 62, 77

ADD 64, 72, 73

AN 8, 77-79

AN= 38, 70

AW 38, 72

BE 34, 74

BEC 34, 68

BEU 34, 74

BLD

0 to 255 34, 69

BLD 130 34, 69

BLD 131 36, 69

BLD 132 36, 69

BLD 133 36, 69

BLD 255 36, 69

Operation Page

CD 22, 72

CFW 46, 68

CSD 46, 74

CSW 46, 68

CU 22, 75

CX 32, 77

D54, 69

DED 48, 74

DEF 46, 74

DO 56, 72, 75

DO= 56, 77

DOC 32, 77

DOU 30, 77

DUD 48, 74

DUF 48, 74

FDG 48, 74

FR 44, 68, 72

FR= 44, 68

GFD 48, 74

GX 32, 77

I32, 77

I54, 69

IA 54, 68

JC 32, 69, 72, 73

JC= 50, 79

Operation Page

JM= 52, 70

JN= 52, 71

JO= 52, 68

JOS = 52, 73

JP= 52, 69

JU 30, 32,

71, 75-78

JU= 50, 70

JUR 52, 75

JZ= 52, 72

L12-16, 60,

68-78

L= 46, 72

LD 16, 68, 72

LD= 46, 69

LDI 58, 74, 75

LDW = 46, 73

LIM 54, 75

LIR 58, 72

LRD 62, 74

LRW 62, 74

LW= 46, 71

MAB 62, 74

MAS 62, 74

MBA 64, 75

MBR 62, 77

MBS 64, 75

Operation Page

MSA 64, 74

MSB 64, 74

NOP 0 34, 68

NOP 1 34, 79

O8, 77-79

O( 8, 78

O= 38, 69

ON 8, 77-79

ON= 38, 70

OW 38, 72

Q32, 69

R8, 22,

71, 77-79

RA 54, 68

RB= 42, 71

RD= 44, 71

RLD 50, 73

RRD 50, 77

RU 42, 58, 75, 76

S8, 22,

73, 77-79

S= 42, 69

SD 22, 70

SD= 44, 70

SE 22, 69

SEC= 44, 69

Operation Page

SF 22, 69

SFD= 44, 69

SIM 54, 75

SLD 48, 70

SLW 48, 73

SP 22, 71

SP= 44, 71

SRW 48, 75

SS 22, 70

SSD 50, 76

SSU= 44, 70

SSW 50, 74

STP 34, 66, 75

STS 66, 75

SU 42, 58, 75, 76

T16-20,

68-78

T= 46, 74

TAK 66, 75

TB 40, 75, 76

TBN 40, 75, 76

TDI 60, 74, 75

TIR 58, 72

TNB 60, 68

TNW 60, 72

Operation Page

TRD 62, 74

TRW 62, 74

XOW 38, 72

Operation Page

×F 28, 73

×G 30, 73

List of Organization Blocks

You must program the OB.

The operating system calls up the OB.

OB No. Function

OB1 Cyclic program execution

Interrupt-, timed-interrupt- and time-driven program exec.

OB2 Interrupt A: Digital input module -434-7, digital

I/O module 485-7 and IP generate

interrupt

OB3 Interrupt B: IP generates interrupt

OB4 Interrupt C: IP generates interrupt

OB5 Interrupt D: IP generates interrupt

OB10 Time-controlled program execution (variable in

each case: 1 ms to 65535 ms)

OB6 Interrupt generated by internal timers

OB11

OB12

OB13

You must program the OB.

The operating system calls up the OB.

OB No. Function

Controlling restart characteristics

OB24 Time-out during update of process image and

interproc. communication flags

OB21 Manuel switch on

OB22 Automatic switch on when power is restored

Handling programming errors and PLC faults

OB23 Time-out during individual access to the S5 bus

(e.g. L PW, L PY, T PW, T PY, LIR, TIR)

OB19 When a block is called which has not been loaded

Handling of system errors

OB26 Scan time exceeded

OB33 Time interrupt error

OB35 I/O error

OB27 Substitution error

OB32 Transfer error

OB34 Battery failure

The OB is already programmed.

You must call up the OB

OB No. Function Execution time (in µs)

OB31 Scan time triggering 9.1

OB254 Read in process I/O image

OB255 Output process I/O image

65+n×(1.5+Ready delay time of the module)

OB182* Copy data area

OB183* Duplicate DX

OB125* Generate STEP 5 blocks 41

35+n ×2.65 (n: number of data words)

52+n×2.35 (n: number of data words in DX)

OB184* Duplicate DB 52+n×2.35 (n: numbe of data words in DB)

OB190* Transfer flag into DB byte by byte 13+n×1.85 (n: number of bytes)

OB191* Transfer data from DB to flag byte by byte 13+n×1.85 (n: number of bytes)

OB192* Transfer flag into DB word by word 12+n×1.3 (n: number of bytes)

OB193* Transfer data from DB to flag word by word 12+n×1.3 (n: number of bytes)

OB220* Sign expansion 3

OB251* PID control algorithm max. 110

OB160 Programmable time loop 3 to 65535

* From software version Z 02

((Seite 86a)) ((Seite 87a))

The OB is already programmed.

You must call up the OB

OB 250, Operating system services

Service

No. Function Execution time

(typical)

1Activation of OB6

2 to 5 New interval for OB10 to OB13

6Modification of entries in BS128 to 143

7Reduction of PIQ transfer

21 µs

20 µs

33 µs

18 µs

8Generation of list of all I/O bytes addressable 1.7 ms to 86 ms

[t=1700 µs+n×(8 µs+Ready delay time)+

m×(20 µs+Ready delay time)+(512-m-n)×165 µs]

m=existing analog I/O bytes

n=existing digital I/O bytes

10/11 Creation of a DB/DX without TRAF 30 µs to 45 µs

((Seite 88a)) ((Seite 89a))

12 New generation of the block address list 50 µs per existing, valid code block

43 µs per existing, valid DB/DX

26 µs per existing invalid code block

25 µs per existing, invalid DB/DX

13 Read address (byte) from S5 bus 33 µs+Ready delay time (on TO: 193 µs)

14 Write address (byte) on S5 bus 35 µs+Ready delay time (on TO: 195 µs)

15 Read address (word) from S5 bus 34 µs+Ready delay time (on TO: 194 µs)

16 Write address (word) on S5 bus 36 µs+2×Ready delay time (on TO: 196 µs)

17/18 Read byte from page frame/

Write byte from page frame 43 µs+Ready delay time (on TO: 200 µs)

19 Set and reset command output inhibit 24 µs

OB 250, Operating system services (cont.)

Service

No. Function Execution Time

(typical)

((Seite 90a)) ((Seite 91a))

25 µsRead DBA register

20

26 µsWrite DBA register

21

25 µsRead DBL register

22

25 µsWrite DBL register

23

29 µsIndexed accessing of DX

24

30 µsIndexed calling fo FX

25

28 µsRemove block from block address list

26

4.8 ms+n×19 µs (n: number of blocks to be changed)Change block identifier to ”valid in EPROM”

27

6 ms+n×19 µs (n: number of blocks to be changed)Change block identifier to ”valid in RAM”

28

List of Function Blocks

Integral Function Blocks

FB No. Function

FB238 Compress PLC memory

FB239 Delete block

FB244 Send data

Execution

Time

(typical)

20 µs*

19 µs

2.9ms**

FB241 Read analog value from 463

analog input module 60 µs

FB242 Read analog value from 464

analog input module 60 to 115 µs

FB243 Read analog value from 466

analog input module 120 µs

• Idle run VKE=0: t 54µs+4×Ready delay

time

• with data transmission: t 1070µs+30×Ready

delay time+n×(2.5µs+

Ready delay time) with

n=minimum frame length,

block size (in bytes)

Execution Time

(Basis for calculation)

t 45µs+2×Ready delay time

t 50µs+2×Ready delay time

t 45µs+2×Ready delay time

FB245 Receive data

FB246 Fetch data

FB247 Monitor job processing

FB248 Delete job

4.4ms**

0.9ms**

58 µs***

1.2ms

• Idle run VKE=0: t 54µs+4×Ready delay

time

• with data acceptance: t 1280µs+20×Ready

delay

time+n×(5µs+Ready

delay time); with n=mini-

mum frame length, block

size (in bytes)

• Idle run VKE=0: t 54µs+4×Ready delay

time

• with parameter transmission: t 820µs+44×NAK

t 54µs+4×Ready delay time

• Idle run t 30µs+3×NAK

• active: t 1200µs+65×NAK

a

* only triggering of compress function

** for ready delay time=1µs and block size 6 (512 bytes)

*** for ready delay time=1µs

Integral Function Blocks (cont.)

FB No. Function

FB249 Initialize interface

Execution

Time

(typical)

<10s

FB250 Read analog value from 460/465

analog input module 40 to 100 µs

Execution Time

(Basis for calculation)

t 54µs+2×Ready delay time (for cyclic sampling)

t 40 to 100µs (for individual sampling)

FB251 Output analog value 60 µs t 45µs+2×Ready delay time

Data Block 1

Parameter Meaning

Block Identifier: SL1: SINEC L1

p=0, 1 to 30, 255

x=0 to 255

y=0 to 255

a=0 to 255

z=0 to 4095

p=1 to 30

”

SL

ave

N

umber”

”0” = Master function with point-to-point link (at 2nd

interface);

These parameters apply for the 2nd interface if no

computer link or ASCII driver has been activated.

Position of the

S

end

M

ailbox (start of SF)

Position of the

R

eceive

M

ailbox (start of EF)

Position of the

C

oordination

B

yte

R

eceive

Position of the

C

oordination

B

yte

S

end

PG

bus

N

umber

Note: CBS and CBR are in a flag byte or in the high-order

byte of the specified data word (DL)!

Block Identifier: SDP: System-Dependent Parameters

WD

RDLY

RT

RC

RF

PROT

PIO

p=0 to 2550

r=0 to 65535

-

”

W

atch-

D

og” (scan time monitoring)

can be set in milliseconds but only in steps of 10 ms

”

R

un

D

e

L

a

Y

” restart delay after POWER ON in milliseconds

”

R

esident

T

imers”; if ”Y” all timers are retentive, if ”N”

only T 0 to 63*.

”

R

esident

C

ounters”; if ”Y” all counters are retentive, if

”N” only C 0 to 63*.

”

R

esident

F

lags”; if ”Y” all flags, S flags are retentive, if

”N” only the first half are retentive*.

”

PROT

ection” activate software protection?

(input/output of program no longer possible)

”

P

rocess

I

mage

O

utput” disable output of process image?

Argument Permissible

Range

p

DBxDWy or

DXaDWy or

FBy

SYz

p

r

Y/N

a

* Additionally, set switch for Default/Overall Reset on the control panel of the CPU to ”RE”

SLN

SM

RM

CBR

CBS

PGN

Data Block DB1 (cont.)

Parameter Meaning

Block Identifier: SDP: (cont.) System-Dependent Parameters (cont.)

PII

RPIC

PPIT

-

s=0 to 255

-

”

P

rocess

I

mage

I

nput” disable read in of process image?

”

R

educed

P

rocess

I

mage

Output

C

ounter” counter for

cycles with reduced PIQ transfer

”

P

arallel

P

rocess

I

mage

T

ransfer”; if ”N”, the sequential PI

transfer and if ”Y” the parallel PI transfer is set

Argument Permissible

Range

Y/N

s

Y/N

Block Identifier: TFB: Timer-Function Block

Interval during which OB 10 to 13 is called and processed

Time in milliseconds

OB10

OB11

OB12

OB13

p=0 to 65535p

Block Identifier: ASC: ASCII Driver at 2nd Interface

Note: Driver number ”1” for the 2nd interface is set

automatically.

Position of the

S

end

M

ailbox (start of SF)

Position of the

R

eceive

M

ailbox (start of EF)

Position of the

C

oordination

B

yte

R

eceive

Position of the

C

oordination

B

yte

S

end

Position of the

PAR

ameter set

”

MOD

e number” mode number of ASCII driver

”

B

au

D

R

ate” baud rate

SM

RM

CBR

CBS

PAR

MOD

BDR

x=0 to 255

y=0 to 255

a=0 to 255

z=0 to 4095

n=1 to 8

m= 150, 200, 300,

600, 1200, 2400,

4800, 9600,

19200

DBxDWy or

DXaDWy or

FBy or

SYz

n

m

Data Block DB1 (cont.)

Parameter MeaningArgument Permissible

Range

Block Identifier: ASC: (cont.) ASCII Driver at 2nd Interface (cont.)

”

P

a

R

i

TY

” Parity

E

ven

O

dd

M

ark (”1”)

S

pace (”0”)

N

one =No check

”

D

ata

F

ormat”

”

W

ait time after

C

arriage

R

eturn”

Wait time after CR in milliseconds

”

W

ait time after

L

ine

F

eed”

Wait time after LF in milliseconds

”

W

ait time after

F

orm

F

eed”

Wait time after FF in milliseconds

”

D

elay

T

ime” character delay time in milliseconds

”

M

ail

L

ength” frame length in bytes for receive frame; for

mode 1, 8

”

M

ail

E

nd” end identifier; for mode 2, 3, 4, 5, 6

RUB OUT = 7FH= 127D

XON = 11H=17

D

XOFF = 13H=19

D

CR = 0DH=13

D

LF = 0AH=10

D

FF = 0CH=12

D

EOT = 04H=4

D

ETX = 03H=3

D

”

S

kip

LF

”

L

ines

P

er

P

age”

”

L

eft

M

argin”

”

P

age

N

umber”; o=top

u=bottom

PRTY

DF

WCR

WLF

WFF

DT

ML

ME

SLF

LPP

LM

PN

p=

E

O

M

S

N

q=0 to 5, 7, 8

r=0 to 2550

s=10 to 655350

t=0 to 1024

u, v=0 to 255

-

w=1 to 255

w=0 to 255

-

p

q

r

s

t

u v

Y/N

w

o/u

Data Block DB1 (cont.)

Parameter MeaningArgument Permissible

Range

Block Identifier: ASC: (cont.) ASCII Driver at 2nd Interface (cont.)

”

H

ea

D

er 1” 1*

”

H

ea

D

er 2” 2*

”

F

oo

T

er 1” 1*

”

F

oo

T

er 2” 2*

Print control characters are entered as hexadecimal

characters as follows:

Example: ”TEXT $1B$38 FURTHER TEXT”

(1B38=double-width print ON)

HD1

HD2

FT1

FT2

max. 119

alpha-

numeric

characters

”<string>”

a

*- CR (Carriage Return) is automatically generated in the parameter DB at the end of the ASCII string (separation of lines).

If HD 1/2, FT 1/2 is missing, then only CR is stored ( Section 12.5)

- For sending of the $ character $$ must be entered.

- For sending of the ”character $” must be entered.

Block Identifier: RKT: Computer Link at 2nd Interface

Note: Driver number ”2” for the 2nd interface is set

automatically.

Position of the

S

end

M

ailbox (start of SF)

Position of the

R

eceive

M

ailbox (start of EF)

Position of the

C

oordination

B

yte

R

eceive

Position of the

C

oordination

B

yte

S

end

Position of the

PAR

ameter set

”

MOD

e number” mode number

1=No block check character

2=Sending with block check character

”

B

au

D

R

ate” baud rate

SM

RM

CBS

CBR

PAR

MOD

BDR

x=0 to 255

N=0 to 255

a=0 to 255

z=0 to 4095

n=1, 2

m= 150, 200,

300, 600, 1200,

2400, 4800,

9600, 19200

DBxDWy or

DXaDWy or

FBy or

SYz

n

m

Data Block DB1 (cont.)

Parameter MeaningArgument Permissible

Range

Block Identifier: RKT: (cont.) Computer Link at 2nd Interface (cont.)

”

P

a

R

i

TY

”

E

ven

O

dd

M

ark (”1”)

S

pace (”0”)

N

one = No check

”

D

ata

F

ormat”

”

PRI

ority”

l=low

h=high

”

D

elay

T

ime” character delay time in milliseconds

”

TI

me

O

ut” time out delay in milliseconds

”

B

lock

W

ait

T

ime” in milliseconds

”

T

ries

T

o

E

rect”

”

T

ries

T

o

S

end”

PRTY

DF

PRI

DT*

TIO*

BWT*

TTE

TTS

p=

E

O

M

S

N

q=0 to 5, 7, 8

s=10 to 655350

r =1 to 255

p

q

l/h

s

r

Block Identifier: S2T: Deactivate Driver

DEAC Y/N - Deactivation of ASCII driver or computer link. If DEAC=”Y”

driver number ”0” is entered (in BS46) and previously

defined parameters for RKT and ASC are not accepted.

a

* DT<TIO<BWT

Data Block DB1 (cont.)

Parameter MeaningArgument Permissible

Range

Block Identifier: CLP: Clock Parameters

CLK

STW

SET

TIS

OHS

DBxDWy or

DXxDWy or

MWb or

SWz

wd dd.mm.yy

hh:mm:ss

AM/PM1

wd dd.mm.

hh:mm:ss

AM/PM1

hhhhhh:mm:ss2

x=0 to 255

N=0 to 255

b=0 to 254

z=0 to 4094

wd =1 to 7

dd =01 to 31

mm =01 to 12

yy =00 to 99

hh =1 to 12

00 to 23

ss =00 to 59

hhhhhh =000000

to 999999

mm =00 to 59

ss =00 to 59

”

CL

oc

K

Data” start of clock data area

”

ST

atus

W

ord” position of the status word

Set clock time, date

Week day=So to Sa

Day

Month

Year

AM/PM

24-hour mode

Seconds

”

T

imer

I

nterrupt

S

et”

”

O

peration

H

our counter

S

et”

Hours

Minutes

Seconds

a

1If an argument (e.g. week day) is not to be transferred, enter XX! The clock will then continue with the current value. If you

specify AM or PM after the clock time, the clock will operate in the relevant 12-hour mode. If you omit this argument, the

clock will operate in 24-hour mode.

2If an argument (e.g. minute) is not to be transferred, enter XX! The clock will then continue with the current value.

Data Block DB1 (cont.)

Parameter MeaningArgument Permissible

Range

Block Identifier: CLP: (cont.) Clock Parameters (cont.)

OHE

STP

SAV

CF

Y/N

p

-

-400 to+400

”

O

peration

H

our counter

E

nable”

”

ST

o

P

” Update clock in STOP state

”

SAV

e” Save clock time after last

RUN STOP or

Power OFF

”

C

orrection

F

actor” Enter correction factor

Block Identifier: ERT:

ERR DBxDWy or

DXaDWy or

MBz or

SYp

x=0, 2 to 255

N=0 to 255

a=0 to 255

z=0 to 236

p=0 to 4076

”

ERR

ors” Position of the error code

Error Return

Evaluation of

CC 1 and CC 0

CC

1CC

0Arith-

metic

Opera-

tions

Digital

Logic

Opera-

tions

Com-

parison

Operations

Shift

Opera-

tions

Con-

version

Opera-

tions

Jump

Opera-

tions

executed

00

Result

=0 Result

=0 ACCU 2

=

ACCU 1

shifted

Bit

=0 - IZ

01

Result

<0 -

ACCU 2

<

ACCU 1 -

Result

<0 IM

IN

10

Result

>0 Result

0 ACCU 2

>

ACCU 1

shifted

Bit

=0

Result

>0 IP

IN

Suggestions/Corrections:

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Programmable Controller

SIMATIC S5-115U (CPU 945)

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