[ /Title (CD74 HC402 0, CD74 HCT40 20) /Subject (High Speed CMOS CD54/74HC4020, CD54/74HCT4020 Data sheet acquired from Harris Semiconductor SCHS201A High Speed CMOS Logic 14-Stage Binary Counter February 1998 - Revised May 2000 Features Description * Fully Static Operation * Negative Edge Clocking The 'HC4020 and 'HCT4020 are 14-stage ripple-carry binary counters. All counter stages are master-slave flipflops. The state of the stage advances one count on the negative clock transition of each input pulse; a high voltage level on the MR line resets all counters to their zero state. All inputs and outputs are buffered. * Typical fMAX = 60 MHz at VCC = 5V, CL = 15pF, TA = 25oC Ordering Information * Buffered Inputs * Common Reset * Fanout (Over Temperature Range) PART NUMBER - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads TEMP. RANGE (oC) PACKAGE CD54HC4020F -55 to 125 16 Ld CERDIP * Wide Operating Temperature Range . . . -55oC to 125oC CD54HC4020F3A -55 to 125 16 Ld CERDIP * Balanced Propagation Delay and Transition Times CD74HC4020E -55 to 125 16 Ld PDIP * Significant Power Reduction Compared to LSTTL Logic ICs CD74HC4020M -55 to 125 16 Ld SOIC CD54HCT4020F3A -55 to 125 16 Ld CERDIP CD74HCT4020E -55 to 125 16 Ld PDIP * HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V NOTES: 1. When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel. * HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il 1A at VOL, VOH 2. Wafer and die is available which meets all electrical specifications. Please contact your local TI sales office or customer service for ordering information. Pinout CD54HC4020, CD54HCT4020 (CERDIP) CD74HC4020, CD74HCT4020 (PDIP, SOIC) TOP VIEW Q12 1 16 VCC Q13 2 15 Q11 Q14 3 14 Q10 Q6 4 13 Q8 Q5 5 12 Q9 Q7 6 11 MR Q4 7 10 CP GND 8 9 Q1` CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright (c) 2000, Texas Instruments Incorporated 1 CD54/74HC4020, CD54/74HCT4020 Functional Diagram VCC 16 10 9 INPUT PULSES 7 5 4 6 14-STAGE RIPPLE COUNTER 13 12 14 15 1 2 3 11 MASTER RESET Q1' Q4 Q5 Q6 Q7 Q8 BUFFERED OUTPUTS Q9 Q10 Q11 Q12 Q13 Q14 8 GND TRUTH TABLE CP COUNT MR OUTPUT STATE L No Change L Advance to Next State X H All Outputs Are Low NOTE: H = High Voltage Level, L = Low Voltage Level, X = Don't Care, = Transition from Low to High Level, = Transition from High to Low. 2 MR CP 11 10 Q1' R R 9 CP Q 2 CP Q CP Q I Q' CP Q R CP Q 3 CP Q R CP Q 4 CP Q Q4 7 R CP Q 5 CP Q Q5 5 R CP Q 6 CP Q Q6 4 R CP Q 7 CP Q Q7 6 R CP Q 8 CP Q Q8 13 R CP Q 9 CP Q Q9 12 R CP Q 10 CP Q Q10 14 R CP Q 11 CP Q Q11 15 R CP Q 12 CP Q Q12 1 R CP Q 13 CP Q Q13 2 R CP Q 14 CP Q Q14 3 CD54/74HC4020, CD54/74HCT4020 Logic Diagram 3 CD54/74HC4020, CD54/74HCT4020 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .25mA DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .50mA Thermal Resistance (Typical, Note 3) JA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max) CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 3. JA is measured with the component mounted on an evaluation PC board in free air. DC Electrical Specifications TEST CONDITIONS PARAMETER 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL VI (V) IO (mA) VCC (V) VIH - - 2 1.5 - - 1.5 4.5 3.15 - - 3.15 - 3.15 - V 6 4.2 - - 4.2 - 4.2 - V MIN TYP MAX MIN MAX MIN MAX UNITS - 1.5 - V HC TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads VIL VOH - VIH or VIL High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VIH or VIL Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current - 2 - - 0.5 - 0.5 - 0.5 V 4.5 - - 1.35 - 1.35 - 1.35 V 6 - - 1.8 - 1.8 - 1.8 V -0.02 2 1.9 - - 1.9 - 1.9 - V -0.02 4.5 4.4 - - 4.4 - 4.4 - V -0.02 6 5.9 - - 5.9 - 5.9 - V - - - - - - - - - V -4 4.5 3.98 - - 3.84 - 3.7 - V -5.2 6 5.48 - - 5.34 - 5.2 - V 0.02 2 - - 0.1 - 0.1 - 0.1 V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 0.02 6 - - 0.1 - 0.1 - 0.1 V - - - - - - - - - V 4 4.5 - - 0.26 - 0.33 - 0.4 V 5.2 6 - - 0.26 - 0.33 - 0.4 V II VCC or GND - 6 - - 0.1 - 1 - 1 A ICC VCC or GND 0 6 - - 8 - 80 - 160 A 4 CD54/74HC4020, CD54/74HCT4020 DC Electrical Specifications (Continued) TEST CONDITIONS SYMBOL VI (V) IO (mA) High Level Input Voltage VIH - - Low Level Input Voltage VIL - High Level Output Voltage CMOS Loads VOH VIH or VIL PARAMETER 25oC VCC (V) -40oC TO 85oC -55oC TO 125oC MIN TYP MAX MIN MAX MIN MAX UNITS 4.5 to 5.5 2 - - 2 - 2 - V - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 V -0.02 4.5 4.4 - - 4.4 - 4.4 - V -4 4.5 3.98 - - 3.84 - 3.7 - V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 4 4.5 - - 0.26 - 0.33 - 0.4 V HCT TYPES High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VIH or VIL Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load II VCC and GND 0 5.5 - - 0.1 - 1 - 1 A ICC VCC or GND 0 5.5 - - 8 - 80 - 160 A ICC VCC -2.1 - 4.5 to 5.5 - 100 360 - 450 - 490 A NOTE: For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. HCT Input Loading Table INPUT UNIT LOADS MR 0.65 CP 0.5 NOTE: Unit Load is ICC limit specified in DC Electrical Table, e.g., 360A max at 25oC. Prerequisite for Switching Specifications 25oC PARAMETER -40oC TO 85oC -55oC TO 125oC SYMBOL VCC (V) MIN MAX MIN MAX MIN MAX UNITS fMAX 2 6 - 5 - 4 - ns 4.5 30 - 25 - 20 - ns 6 35 - 29 - 24 - ns 2 80 - 100 - 120 - ns 4.5 16 - 20 - 24 - ns 6 14 - 17 - 20 - ns 2 50 - 65 - 75 - ns 4.5 10 - 13 - 15 - ns 6 9 - 11 - 13 - ns HC TYPES Maximum Input Pulse Frequency Input Pulse Width Reset Removal Time tW tREM 5 CD54/74HC4020, CD54/74HCT4020 Prerequisite for Switching Specifications (Continued) 25oC PARAMETER Reset Pulse Width -40oC TO 85oC -55oC TO 125oC SYMBOL VCC (V) MIN MAX MIN MAX MIN MAX UNITS tW 2 80 - 100 - 120 - ns 4.5 16 - 20 - 24 - ns 6 14 - 17 - 20 - ns fMAX 4.5 25 - 20 - 16 - MHz tW 4.5 20 - 25 - 30 - ns tREC 4.5 10 - 13 - 15 - ns tW 4.5 20 - 25 - 30 - ns HCT TYPES Maximum Input Pulse Frequency Input Pulse Width Reset Recovery Time Reset Pulse Width Switching Specifications Input tr, tf = 6ns PARAMETER TEST SYMBOL CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS 2 - - 140 - 175 - 210 ns 4.5 - - 28 - 35 - 42 ns CL =15pF 5 - 11 - - - - - ns CL = 50pF 6 - - 24 - 30 - 36 ns CL = 50pF 2 - - 75 - 95 - 110 ns 4.5 - - 15 - 19 - 22 ns CL =15pF 5 - 6 - - - - - ns CL = 50pF 6 - - 13 - 16 - 19 ns CL = 50pF 2 - - 170 - 215 - 255 ns 4.5 - - 34 - 43 - 51 ns 5 - 14 - - - - - ns 6 - - 29 - 37 - 43 ns 2 - - 75 - 95 - 110 ns 4.5 - - 15 - 19 - 22 ns 6 - - 13 - 16 - 19 ns HC TYPES Propagation Delay Time (Figure 1) tPLH, tPHL CL = 50pF CP to Q1' Output Qn to Qn + 1 MR to Qn Output Transition Time (Figure 1) tPLH, tPHL tPLH, tPHL tTLH, tTHL CL = 50pF Input Capacitance CIN CL = 50pF - - - 10 - 10 - 10 pF Power Dissipation Capacitance (Notes 4, 5) CPD CL =15pF 5 - 30 - - - - - pF tPLH, tPHL CL = 50pF 4.5 - - 40 - 50 - 60 ns CL =15pF 5 - 17 - - - - - ns tPLH, tPHL CL = 50pF 4.5 - - 15 - 19 - 22 ns CL =15pF 5 - 6 - - - - - ns tPLH, tPHL CL = 50pF 4.5 - - 40 - 50 - 60 ns CL =15pF 5 - 17 - - - - - ns HCT TYPES Propagation Delay Time (Figure 2) CP to Q1' Output Qn to Qn + 1 MR to Qn 6 CD54/74HC4020, CD54/74HCT4020 Switching Specifications Input tr, tf = 6ns PARAMETER Output Transition (Continued) 25oC -40oC TO 85oC -55oC TO 125oC TEST SYMBOL CONDITIONS VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS tTLH, tTHL CL = 50pF 4.5 - - 15 - 19 - 22 ns Input Capacitance CIN CL =15pF - - - 10 - 10 - 10 pF Power Dissipation Capacitance (Notes 4, 5) CPD CL =15pF 5 - 30 - - - - - pF NOTES: 4. CPD is used to determine the dynamic power consumption, per package. 5. PD = VCC2 fi (CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage. Test Circuits and Waveforms tfCL trCL CLOCK 90% 10% tWL + tWH = I tWL 50% tfCL = 6ns fCL I fCL 3V VCC 50% 10% tWL + tWH = trCL = 6ns CLOCK 50% 2.7V 0.3V GND 1.3V 0.3V tWL tWH NOTE: Outputs should be switching from 10% VCC to 90% VCC in accordance with device truth table. For fMAX, input duty cycle = 50%. 1.3V 1.3V GND tWH NOTE: Outputs should be switching from 10% VCC to 90% VCC in accordance with device truth table. For fMAX, input duty cycle = 50%. FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND PULSE WIDTH FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND PULSE WIDTH 7 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. 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