STEF033 Electronic fuse for 3.3 V line Datasheet - production data Description DFN10 (3 x 3 mm) Flip Chip 9 Features * Continuous current typ.: 3.6 A (DFN), 2.5 A (Flip Chip) * N-channel on resistance (typ): 40 m (DFN), 25 m (Flip Chip) * Enable/Fault functions * Output clamp voltage (typ): 4.5 V * Undervoltage lockout * Short-circuit limit * Overload current limit * Controlled output voltage ramp * Thermal latch (typ): 160 C * Uses tiny capacitors * Latching and auto-retry versions * Operative junction temp. - 40 C to 125 C * Available in DFN10 3x3 and Flip Chip 9 bumps The STEF033 is an integrated electronic fuse optimized for monitoring output current and the input voltage. Connected in series to the 3.3 V rail, it is able to protect the electronic circuitry on its output from overcurrent and overvoltage. The STEF033 has controlled delay and turn-on time. When an overload condition occurs, the device limits the output current to a predefined safe value. If the anomalous overload condition persists, it goes into an open state, disconnecting the load from the power supply. If a continuous short-circuit is present on the board, when the power is re-applied the E-fuse initially limits the output current to a safe value and then goes again into the open state. The voltage clamping circuit prevents the output voltage from exceeding a fixed value, if the input voltage goes beyond this threshold. The device is equipped with a thermal protection circuit. Intervention of thermal protection is signaled to the board-monitoring circuits through an appropriate signal on the Fault pin. Unlike mechanical fuses, which must be physically replaced after a single event, the Efuse does not degrade in its performances following short-circuit/thermal protection intervention and is reset either by re-cycling the supply voltage or using the appropriate Enable pin. The STEF033 is also available in an autoretry version; in case of thermal fault it automatically attempts to re-apply power to the load when the die temperature returns to a safe value. Applications * Hard disk drives * Solid state drives (SSD) * Hard disk and SSD arrays * Computer * DVD and Blu-Ray disc drivers January 2015 This is information on a product in full production. DocID025099 Rev 2 1/25 www.st.com Contents STEF033 Contents 1 Device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 Typical application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.1 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.1.1 Turn-on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.1.2 Normal operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.1.3 Output voltage clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.1.4 Current limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.1.5 Thermal shutdown and Auto-retry function . . . . . . . . . . . . . . . . . . . . . . 10 5.2 RLimit calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.3 Cdv/dt calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 5.4 Enable-Fault pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 6 Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.1 DFN10 (3 x 3 mm) package information . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.2 QFNxx/DFNxx (3x3 mm) packing information . . . . . . . . . . . . . . . . . . . . . 20 7.3 Flip Chip 9 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2/25 DocID025099 Rev 2 STEF033 1 Device block diagram Device block diagram Figure 1. STEF033 block diagram DocID025099 Rev 2 3/25 25 Pin configuration 2 STEF033 Pin configuration Figure 2. Pin configuration (top view) Table 1. Pin description Pin n Pin n (DFN) (Flip Chip) 1,2,3,4,5 C1,C2,C3 VOUT/Source 6 N.C. I-lim - 7 A1 I-lim + 8 A2 Symbol Note Connected to the source of the internal power MOSFET and to the output terminal of the fuse A resistor between these two pins sets the overload and short-circuit current limit levels. On the Flip Chip the resistor must be connected between the I-Lim+ and Source pins En/Fault The Enable/Fault pin is a tri-state, bi-directional interface. During normal operation the pin must be left floating, or it can be used to disable the output of the device by pulling it to ground using an open drain or open collector device. If a thermal fault occurs, the voltage on this pin goes into an intermediate state to signal a monitor circuit that the device is in thermal shutdown. It can be connected to another device of this family to cause a simultaneous shutdown during thermal events. 9 N.C. dv/dt The internal dv/dt circuit controls the slew rate of the output voltage at turn-on. The internal capacitor allows a ramp-up time of around 1.4 ms. An external capacitor can be added to this pin to increase the ramp time. If an additional capacitor is not required, this pin should be left open. This feature is not available on the Flip Chip version. 10 A3 GND Ground pin Exposed pad B1,B2,B3 VCC Exposed pad. Positive input voltage must be connected to VCC. 4/25 DocID025099 Rev 2 STEF033 3 Maximum ratings Maximum ratings Table 2. Absolute maximum ratings Symbol Parameter VCC VOUT/source Value Unit Positive power supply voltage - 0.3 to 10 V VOUT pin voltage - 0.3 to 7 V VOUT pin voltage (100 ms) - 0.3 to Vcc+0.3 Current limit pin voltage -0.3 to 7 I-Lim+/I-Lim- V Current limit pin voltage (100 ms) En/Fault - 0.3 to VCC+0.3 Enable/Fault pin voltage - 0.3 to 4.6 V dv/dt dv/dt pin voltage - 0.3 to 4.6 V TOP Operating junction temperature range(1) - 40 to 125 C TSTG Storage temperature range - 65 to 150 C TLEAD Lead temperature (soldering) 10 sec 260 C 1. The thermal limit is set above the maximum thermal rating. It is not recommended to operate the device at temperatures greater than the maximum ratings for extended periods of time. Note: Absolute maximum ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Table 3. Recommended operating condition Symbol VCC Parameter Positive power supply voltage Value Unit 3.1 to 8 V Current limitation resistor range, STEF033, STEF033A 10 to 120 Current limitation resistor range, STEF033J, STEF033JA 15 to 120 R-limit Cdv/dt Soft-start capacitor range 0 to 1 nF VEN Enable/Fault pin voltage 0 to 3.6 V Table 4. Thermal data Symbol RthJA RthJC Parameter Value Thermal resistance junction-ambient, DFN10 70 Thermal resistance junction-ambient, Flip Chip 90 Thermal resistance junction-case, DFN10 34 DocID025099 Rev 2 Unit C/W 5/25 25 Maximum ratings STEF033 Table 5. ESD performance Symbol ESD 6/25 Parameter Test conditions Value Unit HBM 4 kV MM 400 V CDM (DFN10) 500 V CDM (Flip Chip) 250 V ESD protection DocID025099 Rev 2 STEF033 Electrical Characteristics 4 Electrical Characteristics VCC = 3.3 V, CI = 10 F, CO =10 F, TJ = 25C (unless otherwise specified) Table 6. Electrical characteristics for STEF033 Symbol Parameter Test conditions Min. Typ. Max. Unit 4 4.5 5 V 2.15 2.35 2.5 V Under/Over Voltage Protection VClamp Output clamping voltage VCC = 8 V VUVLO Under voltage Lockout Turn-on, voltage increasing VHyst UVLO hysteresis 0.1 V Enabling of chip to VOUT=10% of nominal value. 500 s IOUT = 500 mA, TJ = 25C 40 Power MOSFET tdly RDSon Delay time ON resistance (DFN package)(1) IOUT = 500 mA, -40C<TJ<125C ON resistance (Flip Chip package)(1) VOFF ID Off State output voltage 60 m 70 IOUT = 500 mA, TJ = 25C 30 50 m IOUT = 500 mA, -40C<TJ<125C 70 VEN=GND, RL=infinite 100 DFN package 3.6 Flip Chip package 2.5 Continuous current mV A Current limit IShort ILim Short-circuit current limit Overload current limit RLimit = 24 RLimit = 24 1 (2) 1.35 1.75 2.5 A A dv/dt circuit dv/dt Output voltage ramp time VOUT = 10% to 90% of nominal voltage, No Cdv/dt 0.8 1.4 2.5 ms 0.5 V 2 V Enable/Fault VIL VI(INT) VIH Low level input voltage Output disabled, (2) Intermediate level input voltage Thermal fault, output disabled High level input voltage Output enabled VI(MAX) High state maximum voltage IIL Low level input current (sink) VEnable = GND Maximum fan-out for fault signal Total number of chips that can be connected to this pin for simultaneous shutdown (2) (2) 0.8 1.4 2.5 V 3.25 DocID025099 Rev 2 -28 V -50 A 3 Units 7/25 25 Electrical Characteristics STEF033 Table 6. Electrical characteristics for STEF033 (continued) Symbol Parameter Test conditions Min. Typ. Max. Device operational 0.6 2 Thermal shutdown (only on latching versions)(2) 0.5 Device disabled (VEN = GND) 0.35 Shutdown temperature (2) 160 Hysteresis Only on auto-retry versions (2) Unit Total device IBias Bias current mA Thermal latch TSD 1. Pulse test 2. Guaranteed by design, but not tested in production 8/25 DocID025099 Rev 2 C 25 STEF033 5 Typical application Typical application Figure 3. Application circuit, STEF033 and STEF033A (DFN10 package) Figure 4. Application circuit with Kelvin current sensing, STEF033J and STEF033JA (Flip Chip 9 bump package) 5.1 Operating modes 5.1.1 Turn-on When the input voltage is applied, the Enable/Fault pin goes up to the high state, enabling the internal control circuitry. After an initial delay time of typically 500 ms, the output voltage is supplied with a slope defined by the internal dv/dt circuitry. If no additional capacitor is connected to dv/dt pin, the total time from the Enable signal going high and the output voltage reaching the nominal value is around 1.6 ms (refer to Figure 5, and Figure 15). DocID025099 Rev 2 9/25 25 Typical application 5.1.2 STEF033 Normal operating condition The STEF033 E-fuse behaves like a mechanical fuse, buffering the circuitry on its output with the same voltage shown at its input, with a small voltage fall due to the N-channel MOSFET RDSOn. 5.1.3 Output voltage clamp This internal protection circuit clamps the output voltage to a maximum safe value, typically 4.5 V, if the input voltage exceeds this threshold. 5.1.4 Current limiting When an overload event occurs, the current limiting circuit reduces the conductivity of the power MOSFET, in order to clamp the output current at the value selected externally by means of the limiting resistor RLimit (Figure 3). 5.1.5 Thermal shutdown and Auto-retry function If the device temperature exceeds the thermal latch threshold, typically 160 C, the thermal shutdown circuitry turns the power MOSFET off, thus disconnecting the load. The EN/Fault pin of the device is automatically set to an intermediate voltage, in order to signal the overtemperature event. The STEF033 latch version can be reset from this condition either by cycling the supply voltage or by pulling down the EN pin below the Vil threshold and then releasing it. On the STEF033A auto-retry version, the power MOSFET will remain in an OFF state until the die temperature drops below the hysteresis value. Once this happens, the internal autoretry circuit attempts to reset the device, pulling up the EN/Fault pin to the operative value. 5.2 RLimit calculation As shown in Figure 1 the device uses an internal N-channel Sense FET with a fixed ratio, to monitor the output current and limit it at the level set by the user. The RLimit value for achieving the requested current limitation can be estimated by using the "Current limit vs RLimit", graph in Figure 12. The device has two levels of current limitation, depending on the load condition. The short-circuit current limit (IShort) is the current level that is imposed when the output voltage decreases sharply, as in the case of a short-circuit on the output. The overload current limit (ILim), also described as "Current limit trip-point", represents the current level that is recognized by the device as an overload condition. Following this, the current limit trip point is reached the device enters into current limitation, and the current to the load is limited to the IShort value, which is generally lower than the trip-point value. The overload current limit (ILim) is dependent on the device reaction time, so it is influenced by the load current slew-rate. The faster the current increase, the higher the current limit trip point. 10/25 DocID025099 Rev 2 STEF033 5.3 Typical application Cdv/dt calculation The device includes a rise-time control circuit, allowing the soft-start during turn-on and Hotplug of the equipment. The pre-programmed rise time, defined as the time interval during which the output voltage goes from 10% to 90% of the nominal voltage, is typically 1.4 ms. The STEF033 and STEF033A in DFN10 package feature a user-programmable output voltage ramp-up time; by connecting a capacitor between the Cdv/dt pin and GND, modification of the output voltage ramp-up time is possible. The capacitance to be added on the Cdv/dt pin can be selected using the following table. Table 7. Typical rise time values vs. dv/dt capacitor Cdv/dt Rise Time (1) [ms] none 100 pF 470 pF 1 nF 1.4 2.8 8 16 1. VCC = 3.3 V, CIN = 10 F, COUT = 10 F, RLIMIT = 24 , IOUT = 1 A Figure 5. Delay time and VOUT rise time VOUT 90% Enable delay time 10% 5.4 rise time Enable-Fault pin The Enable/Fault pin has the dual function of controlling the output of the device and, at the same time, of providing information about the device status to the application. It can be connected to an external open-drain or open-collector device. In this case, when it is pulled at low logic level, it will turn the output of the E-Fuse off. If this pin is left floating, since it has internal pull-up circuitry, the output of the E-Fuse is kept ON in normal operating conditions. This pin should never be biased to a voltage higher than 3.6 V. In case of thermal fault, the pin is pulled to an intermediate state (Figure 6). This signal can be provided to a monitor circuit, signaling that a thermal shutdown has occurred, or it can be DocID025099 Rev 2 11/25 25 Typical application STEF033 directly connected to the Enable/Fault pins of other STEFxx devices on the same application, in order to achieve a simultaneous enable/disable feature. When a thermal fault occurs, the device can be reset either by cycling the supply voltage or by pulling down the Enable pin below the Vil threshold and then releasing it. Figure 6. Enable/Fault pin status 5 EN/Fault voltage [V] 4 Normal operating condition 3 2 Thermal fault condition 1 Off/Reset 0 time 12/25 DocID025099 Rev 2 AM17209v1 STEF033 Typical performance characteristics 6 Typical performance characteristics The following plots are referred to the typical application circuit and, unless otherwise noted, at TA = 25 C. Figure 7. Clamping voltage vs. temperature Figure 8. Short-circuit current vs. temperature AM17210v1 8 AM17211v1 3 VC C = 6 V V CC = 3.3 V, R- limit = 24 7 2.5 2 5 Ishort [A] Vclamp [V] 6 4 3 1.5 1 2 0.5 1 0 -40 -25 0 25 55 Temperature [C] 85 0 125 -40 Figure 9. Bias current vs. temperature (device operational) 1.6 1.4 1.4 1.2 1.2 0.8 1 0.6 0.4 0.4 0.2 0.2 -40 -25 0 25 55 Temperature [C] AM17213v1 0.8 0.6 0 85 0 125 Figure 11. ON resistance vs. temperature -40 -25 0 25 55 Temperature [C] 85 125 Figure 12. Current limit vs. RLimit (IOUT ramp) AM17214v1 70 125 V cc = 3.3 V, VE N = G ND 1.8 1.6 1 85 2 V cc = 3.3 V, VE N = floating Ibias [A] Ibias [A] 1.8 0 25 55 Temperature [C] Figure 10. Bias current vs. temperature (device disabled) AM17212v1 2 -25 AM17215v1 6 Vcc = 3.3 V, R - limit = 5 5 Limit & Short Current (A) RDS -ON [m] 60 50 40 Iout 500 mA 30 Iout 1 A Iout 2 A 20 Iout 4 A 4 ILIMIT 3 2 1 10 ISHORT 0 0 -40 -20 0 20 40 60 80 Temperature (C) 100 120 140 0 DocID025099 Rev 2 20 40 60 80 100 External Sensing Resistor () 120 140 13/25 25 Typical performance characteristics STEF033 Figure 13. VOUT ramp-up vs. enable VCC = 3,3 V, IOUT = 1 A, CIN = COUT = 10 F, RLimit = 24 , NO Cdv/dt Figure 15. VOUT turn-on vs. enable VCC = 3.3 V, CIN = COUT = 10 F, RLimit = 24 , NO Cdv/dt, IOUT = 1 A, Enable from GND to Floating Figure 17. Startup (slow rising) VCC = 3.3 V, IOUT = 1 A, CIN = COUT = 10 F, RLimit = 24 , Cdv/dt = 470 pF Figure 16. VOUT turn-off vs. enable VCC = 3.3 V, CIN = COUT = 10 F, RLimit = 24 , NO Cdv/dt, IOUT = 1 A, Enable from Floating to GND Figure 18. Startup and voltage clam VCC = from 0 to 3.3 V, CIN = COUT = 10 F, RLimit = 24 , NO Cdv/dt, IOUT = 1 A 14/25 Figure 14. VOUT ramp-up vs. enable VCC = from 0 to 6 V, CIN = COUT = 10 F, RLimit = 24 , NO Cdv/dt, IOUT = 1 A DocID025099 Rev 2 STEF033 Typical performance characteristics Figure 19. Thermal latch from 2 A load to shortcircuit VCC = from 0 to 3.3 V, CIN = COUT = 10 F, RLimit = 24 , NO Cdv/dt, IOUT = 1 A Figure 21. Voltage clamp Figure 20. Startup into output short-circuit VCC = from 0 to 3.3 V, CIN = COUT = 10 F, RLimit = 24 , VOUT short to GND Figure 22. Trip and short current (IOUT ramp) VCC = from 3.3 to 6 V, CIN = COUT =10 F, RLimit = 24 , IOUT = 1 A VCC = from 0 to 3.3 V, CIN = COUT = 10 F, RLimit = 24 DocID025099 Rev 2 15/25 25 Package information 7 STEF033 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. 16/25 DocID025099 Rev 2 STEF033 7.1 Package information DFN10 (3 x 3 mm) package information Figure 23. DFN10 (3 x 3 mm) outline @- DocID025099 Rev 2 17/25 25 Package information STEF033 Table 8. DFN10 (3 x 3 mm) mechanical data mm. Dim. Typ Min. Max. A 0.90 0.80 1.00 A1 0.02 A2 0.70 A3 0.20 b 0.23 0.18 0.30 D 3.00 2.85 3.15 D2 2.38 2.23 2.50 E 3.00 2.85 3.15 E2 1.64 1.49 1.75 E3 0.230 E4 0.365 e 0.50 L 0.40 ddd 18/25 00.5 0.30 0.50 0.08 DocID025099 Rev 2 STEF033 Package information Figure 24. DFN10 (3 x 3 mm) recommended footprint @- DocID025099 Rev 2 19/25 25 Package information 7.2 STEF033 QFNxx/DFNxx (3x3 mm) packing information Figure 25. QFNxx/DFNxx (3x3 mm) tape and reel outline Table 9. QFNxx/DFNxx (3x3 mm) tape and reel mechanical data mm. Dim. Min. Typ. A 330 C 12.8 D 20.2 N 60 13.2 T 20/25 Max. 18.4 Ao 3.3 Bo 3.3 Ko 1.1 Po 4 P 8 DocID025099 Rev 2 STEF033 7.3 Package information Flip Chip 9 package information Figure 26. Flip Chip 9 package outline 7504895_K DocID025099 Rev 2 21/25 25 Package information STEF033 Table 10. Flip Chip 9 mechanical data mm. Dim. Min. Typ. Max. A 0.50 0.55 0.60 A1 0.17 0.20 0.23 A2 0.33 0.35 0.37 b 0.23 0.25 0.29 D 1.16 1.19 1.22 D1 E 0.8 1.16 1.19 E1 0.8 e 0.40 f 0.195 ccc 0.075 1.22 Figure 27. Flip Chip 9 recommended footprint (dimensions in mm.) & % $ *ULGSODFHPHQWHDUHD B. 22/25 DocID025099 Rev 2 STEF033 8 Order codes Order codes Table 11. Order codes Tape and reel Package Version Marking STEF033PUR DFN Latch EF03 Flip Chip 9 Latch 33 STEF033APUR DFN Auto-retry EF03A STEF033AJR (1) Flip Chip 9 Auto-retry 3A STEF033JR (1) 1. Available on request. DocID025099 Rev 2 23/25 25 Revision history 9 STEF033 Revision history Table 12. Document revision history Date Revision 06-Aug-2013 1 Initial release. 2 Updated features in cover page, Figure 2: Pin configuration (top view), Table 1: Pin description, Table 4: Thermal data, Table 5: ESD performance, Table 6: Electrical characteristics for STEF033 and Section 7: Package information. Minor text changes. 28-Jan-2015 24/25 Changes DocID025099 Rev 2 STEF033 IMPORTANT NOTICE - PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST's terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers' products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. (c) 2015 STMicroelectronics - All rights reserved DocID025099 Rev 2 25/25 25