19-5375; Rev 1.2; 4/11 71M6543F/H and 71M6543G/GH Energy Meter ICs LE AVAILAB DATA SHEET April 2011 GENERAL DESCRIPTION FEATURES The 71M6543F, 71M6543H, 71M6543G, and 71M6543GH are Teridian's 4th-generation polyphase metering systems-on-chips (SoCs) with a 5MHz 8051-compatible MPU core, low-power realtime clock (RTC) with digital temperature compensation, flash memory, and LCD driver. Our Single Converter Technology(R) with a 22-bit delta-sigma ADC, seven analog inputs, digital metrology temperature compensation, precision voltage reference, and a 32bit computation engine (CE) supports a wide range of metering applications with very few external components. * 0.1% Accuracy Over 2000:1 Current Range * Exceeds IEC 62053/ANSI C12.20 Standards * Seven Sensor Inputs with Neutral Current Measurement, Differential Mode Selectable for Current Inputs * Selectable Gain of 1 or 8 for One Current Input to Support Shunts * High-Speed Wh/VARh Pulse Outputs with Programmable Width * 64KB Flash, 5KB RAM (71M6543F/H) * 128KB Flash, 5KB RAM (71M6543G/GH) * Up to Four Pulse Outputs with Pulse Count * Four-Quadrant Metering, Phase Sequencing * Digital Temperature Compensation: Metrology Compensation Accurate RTC for TOU Functions with Automatic Temperature Compensation for Crystal in All Power Modes * Independent 32-Bit Compute Engine * 46-64Hz Line Frequency Range with the Same Calibration * Phase Compensation (7) * Three Battery-Backup Modes: Brownout Mode LCD Mode Sleep Mode * Wake-Up on Pin Events and Wake-on-Timer * 1A in Sleep Mode * Flash Security * In-System Program Update * 8-Bit MPU (80515), Up to 5MIPS * Full-Speed MPU Clock in Brownout Mode * LCD Driver: 6 Common Segment Drivers Up to 56 Selectable Pins * Up to 51 Multifunction DIO Pins * Hardware Watchdog Timer (WDT) * I2C/MICROWIRETM EEPROM Interface * SPI Interface with Flash Program Capability * Two UARTs for IR and AMR * IR LED Driver with Modulation * Industrial Temperature Range * 100-Pin Lead-Free LQFP Package The 71M6543F, 71M6543H, 71M6543G and 71M6543GH support optional interfaces to the 71M6xx3 series of isolated sensors that offer BOM cost reduction, immunity to magnetic tamper, and enhanced reliability. The ICs feature ultra-low-power operation in active and battery modes, 5KB shared RAM, and 64KB (71M6543F, 71M6543H) or 128KB (71M6543G, 71M6543GH) of flash memory, which can be programmed with code and/or data during meter operation. High processing and sampling rates combined with differential inputs offer a powerful metering platform for commercial and industrial meters with up to class 0.2 accuracy (71M6543H, 71M6543GH). A complete array of code development tools, demonstration code, and reference designs enable rapid development and certification of meters that meet all ANSI and IEC electricity metering standards worldwide. C Shunt Current Sensors LOAD NEUTRAL B A Functional Diagrams POWER SUPPLY Resistor Dividers 71M6xx3 71M6xx3 71M6xx3 NEUTRAL Pulse Transformers Note: This system is referenced to Neutral 3x TERIDIAN 71M6xx3 MUX and ADC IADC0 IADC1 }IN* VADC10 (VC) IADC6 IADC7 }IC VADC9 (VB) IADC4 IADC5 }IB VADC8 (VA) IADC2 IADC3 }IA VREF SERIAL PORTS AMR IR TX V3P3A V3P3SYS GNDA GNDD TERIDIAN 71M6543F/ 71M6543H/ 71M6543G/ 71M6543GH TEMPERATURE SENSOR RAM COMPUTE ENGINE RX MODUL- RX ATOR TX POWER FAULT COMPARATOR FLASH MEMORY MPU RTC TIMERS PWR MODE CONTROL WAKE-UP REGULATOR BATTERY VBAT VBAT_RTC BATTERY MONITOR COM0...5 SEG SEG/DIO LCD DRIVER DIO, PULSES DIO V3P3D OSCILLATOR/ PLL XIN HOST appearSPI Pin Configurations atINTERFACE end of data sheet. XOUT ICE Functional Diagrams continued at end of data sheet. *IN = Neutral Current UCSP is a trademark of Maxim Integrated Products, Inc. RTC BATTERY LCD DISPLAY 8888.8888 PULSES, DIO I2C or Wire EEPROM 32 kHz 9/17/2010 Single Converter Technology is a registered trademark of Maxim Integrated Products, Inc. MICROWIRE is a trademark of National Semiconductor Corp. For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maximintegrated.com. 71M6543F/H and 71M6543G/GH Data Sheet Table of Contents 1 2 3 Introduction ................................................................................................................................. 10 Hardware Description .................................................................................................................. 11 2.1 Hardware Overview............................................................................................................... 11 2.2 Analog Front-End (AFE) ........................................................................................................ 12 2.2.1 Signal Input Pins ....................................................................................................... 13 2.2.2 Input Multiplexer ........................................................................................................ 14 2.2.3 Delay Compensation ................................................................................................. 19 2.2.4 ADC Pre-Amplifier ..................................................................................................... 20 2.2.5 A/D Converter (ADC) ................................................................................................. 20 2.2.6 FIR Filter ................................................................................................................... 20 2.2.7 Voltage References ................................................................................................... 20 2.2.8 71M6xx3 Isolated Sensor Interface............................................................................ 22 2.3 Digital Computation Engine (CE) ........................................................................................... 25 2.3.1 CE Program Memory ................................................................................................. 25 2.3.2 CE Data Memory ....................................................................................................... 25 2.3.3 CE Communication with the MPU .............................................................................. 25 2.3.4 Meter Equations ........................................................................................................ 26 2.3.5 Real-Time Monitor (RTM) .......................................................................................... 26 2.3.6 Pulse Generators ...................................................................................................... 26 2.3.7 CE Functional Overview ............................................................................................ 28 2.4 80515 MPU Core .................................................................................................................. 30 2.4.1 Memory Organization and Addressing ....................................................................... 30 2.4.2 Special Function Registers (SFRs) ............................................................................ 32 2.4.3 Generic 80515 Special Function Registers ................................................................ 33 2.4.4 Instruction Set ........................................................................................................... 35 2.4.5 80515 Power Reduction Modes ................................................................................. 35 2.4.6 UARTs ...................................................................................................................... 36 2.4.7 Timers and Counters ................................................................................................. 38 2.4.8 WD Timer (Software Watchdog Timer) ...................................................................... 40 2.4.9 Interrupts................................................................................................................... 40 2.5 On-Chip Resources............................................................................................................... 47 2.5.1 Physical Memory ....................................................................................................... 47 2.5.2 Oscillator ................................................................................................................... 49 2.5.3 PLL and Internal Clocks............................................................................................. 50 2.5.4 Real-Time Clock (RTC) ............................................................................................. 51 2.5.5 71M6543 Temperature Sensor .................................................................................. 55 2.5.6 71M6xx3 Temperature Sensor .................................................................................. 56 2.5.7 71M6543 Battery Monitor .......................................................................................... 57 2.5.8 71M6xx3 VCC Monitor .............................................................................................. 57 2.5.9 UART and Optical Interface ....................................................................................... 57 2.5.10 Digital I/O and LCD Segment Drivers......................................................................... 58 2.5.11 EEPROM Interface .................................................................................................... 66 2.5.12 SPI Slave Port ........................................................................................................... 68 2.5.13 Hardware Watchdog Timer ........................................................................................ 72 2.5.14 Test Ports (TMUXOUT and TMUX2OUT Pins)........................................................... 73 Functional Description ................................................................................................................ 75 2 (c) 2008-2011 Teridian Semiconductor Corporation v1.2 71M6543F/H and 71M6543G/GH Data Sheet 3.1 3.2 4 5 v1.2 Theory of Operation .............................................................................................................. 75 Battery Modes....................................................................................................................... 75 3.2.1 BRN Mode ................................................................................................................ 78 3.2.2 LCD Mode ................................................................................................................. 78 3.2.3 SLP Mode ................................................................................................................. 79 3.3 Fault and Reset Behavior ...................................................................................................... 80 3.3.1 Events at Power-Down .............................................................................................. 80 3.3.2 IC Behavior at Low Battery Voltage ........................................................................... 81 3.3.3 Reset Sequence ........................................................................................................ 81 3.3.4 Watchdog Timer (WDT) Reset ................................................................................... 81 3.4 Wake-Up Behavior ................................................................................................................ 82 3.4.1 Wake on Hardware Events ........................................................................................ 82 3.4.2 Wake on Timer .......................................................................................................... 84 3.5 Data Flow and MPU/CE Communication ............................................................................... 84 Application Information ............................................................................................................... 86 4.1 Connecting 5 V Devices ........................................................................................................ 86 4.2 Directly Connected Sensors .................................................................................................. 86 4.3 Systems Using 71M6xx3 Isolated Sensors and Current Shunts ............................................. 87 4.4 System Using Current Transformers ..................................................................................... 88 4.5 Metrology Temperature Compensation.................................................................................. 89 4.5.1 Distinction Between Standard and High-Precision Parts ............................................ 89 4.5.2 Temperature Coefficients for the 71M6543F and 71M6543G ..................................... 90 4.5.3 Temperature Coefficients for the 71M6543H and 71M6543GH .................................. 90 4.5.4 Temperature Coefficients for the 71M6xx3................................................................. 90 4.5.5 Temperature Compensation for VREF and Shunt Sensors ........................................ 90 4.5.6 Temperature Compensation of VREF and Current Transformers ............................... 92 4.6 Connecting I2C EEPROMs .................................................................................................... 94 4.7 Connecting Three-Wire EEPROMs ....................................................................................... 94 4.8 UART0 (TX/RX) .................................................................................................................... 94 4.9 Optical Interface (UART1) ..................................................................................................... 94 4.10 Connecting the Reset Pin...................................................................................................... 95 4.11 Connecting the Emulator Port Pins ........................................................................................ 96 4.12 Flash Programming ............................................................................................................... 96 4.12.1 Flash Programming via the ICE Port .......................................................................... 96 4.12.2 Flash Programming via the SPI Port .......................................................................... 96 4.13 MPU Demonstration Code..................................................................................................... 96 4.14 Crystal Oscillator ................................................................................................................... 97 4.15 Meter Calibration................................................................................................................... 97 Firmware Interface ....................................................................................................................... 98 5.1 I/O RAM Map -Functional Order ........................................................................................... 98 5.2 I/O RAM Map - Alphabetical Order ..................................................................................... 104 5.3 Reading the Info Page (71M6543H and 71M6543GH only).................................................. 118 5.4 CE Interface Description ..................................................................................................... 120 5.4.1 CE Program ............................................................................................................ 120 5.4.2 CE Data Format ...................................................................................................... 120 5.4.3 Constants ................................................................................................................ 120 5.4.4 Environment ............................................................................................................ 121 5.4.5 CE Calculations....................................................................................................... 121 5.4.6 CE Front-End Data (Raw Data) ............................................................................... 122 5.4.7 CE Status and Control ............................................................................................. 123 (c) 2008-2011 Teridian Semiconductor Corporation 3 71M6543F/H and 71M6543G/GH Data Sheet 5.4.8 CE Transfer Variables ............................................................................................. 125 5.4.9 Pulse Generation..................................................................................................... 127 5.4.10 CE Calibration Parameters ...................................................................................... 130 5.4.11 CE Flow Diagrams .................................................................................................. 131 6 71M6543 Specifications............................................................................................................. 133 6.1 Absolute Maximum Ratings ................................................................................................. 133 6.2 Recommended External Components ................................................................................. 134 6.3 Recommended Operating Conditions .................................................................................. 134 6.4 Performance Specifications ................................................................................................. 135 6.4.1 Input Logic Levels ................................................................................................... 135 6.4.2 Output Logic Levels................................................................................................. 135 6.4.3 Battery Monitor ........................................................................................................ 136 6.4.4 Temperature Monitor ............................................................................................... 137 6.4.5 Supply Current ........................................................................................................ 138 6.4.6 V3P3D Switch ......................................................................................................... 139 6.4.7 Internal Power Fault Comparators ........................................................................... 139 6.4.8 2.5 V Voltage Regulator - System Power ................................................................ 139 6.4.9 2.5 V Voltage Regulator - Battery Power ................................................................. 140 6.4.10 Crystal Oscillator ..................................................................................................... 140 6.4.11 Phase-Locked Loop (PLL) ....................................................................................... 140 6.4.12 LCD Drivers ............................................................................................................ 140 6.4.13 VLCD Generator...................................................................................................... 140 6.4.14 71M6543 VREF....................................................................................................... 143 6.4.15 ADC Converter ........................................................................................................ 144 6.4.16 Pre-Amplifier for IADC0-IADC1 ................................................................................ 145 6.5 Timing Specifications .......................................................................................................... 146 6.5.1 Flash Memory ......................................................................................................... 146 6.5.2 SPI Slave ................................................................................................................ 146 6.5.3 EEPROM Interface .................................................................................................. 146 6.5.4 RESET Pin .............................................................................................................. 147 6.5.5 Real-Time Clock (RTC) ........................................................................................... 147 6.6 Typical Performance Data .........................................................Error! Bookmark not defined. 6.7 100-Pin LQFP Package Outline Drawing ............................................................................. 148 6.8 71M6543 Pinout .................................................................................................................. 149 6.9 71M6543 Pin Descriptions................................................................................................... 150 6.9.1 71M6543 Power and Ground Pins ........................................................................... 150 6.9.2 71M6543 Analog Pins ............................................................................................. 151 6.9.3 71M6543 Digital Pins............................................................................................... 152 6.9.4 I/O Equivalent Circuits ............................................................................................. 154 7 Ordering Information ................................................................................................................. 155 7.1 71M6543 Ordering Guide .................................................................................................... 155 8 Related Information ................................................................................................................ 155 9 Contact Information ................................................................................................................ 155 Appendix A: Acronyms ..................................................................................................................... 156 Appendix B: Revision History ........................................................................................................... 157 4 (c) 2008-2011 Teridian Semiconductor Corporation v1.2 71M6543F/H and 71M6543G/GH Data Sheet Figures Figure 1: IC Functional Block Diagram ..................................................................................................... 9 Figure 2: AFE Block Diagram (Shunts: One-Local, Three-Remotes) ...................................................... 12 Figure 3. AFE Block Diagram (Four CTs) ............................................................................................... 13 Figure 4: States in a Multiplexer Frame (MUX_DIV[3:0] = 6) .................................................................. 17 Figure 5: States in a Multiplexer Frame (MUX_DIV[3:0] = 7) .................................................................. 17 Figure 6: General Topology of a Chopped Amplifier ............................................................................... 21 Figure 7: CROSS Signal with CHOP_E = 00........................................................................................... 21 Figure 8: RTM Timing ............................................................................................................................ 26 Figure 9. Pulse Generator FIFO Timing ................................................................................................. 28 Figure 10: Samples from Multiplexer Cycle (Frame) ............................................................................... 29 Figure 11: Accumulation Interval ............................................................................................................ 29 Figure 12: Interrupt Structure ................................................................................................................. 46 Figure 13: Automatic Temperature Compensation ................................................................................. 54 Figure 14: Optical Interface.................................................................................................................... 58 Figure 15: Optical Interface (UART1) ..................................................................................................... 58 Figure 16: Connecting an External Load to DIO Pins ............................................................................. 60 Figure 17: LCD Waveforms ................................................................................................................... 65 Figure 18: 3-wire Interface. Write Command, HiZ=0. ............................................................................. 67 Figure 19: 3-wire Interface. Write Command, HiZ=1 .............................................................................. 68 Figure 20: 3-wire Interface. Read Command. ........................................................................................ 68 Figure 21: 3-Wire Interface. Write Command when CNT=0 ................................................................... 68 Figure 22: 3-wire Interface. Write Command when HiZ=1 and WFR=1. ................................................. 68 Figure 23: SPI Slave Port - Typical Multi-Byte Read and Write operations.............................................. 70 Figure 24: Voltage, Current, Momentary and Accumulated Energy......................................................... 75 Figure 25: Operation Modes State Diagram ........................................................................................... 76 Figure 26: MPU/CE Data Flow ............................................................................................................... 85 Figure 27: Resistive Voltage Divider (Voltage Sensing) .......................................................................... 86 Figure 28. CT with Single-Ended Input Connection (Current Sensing) .................................................... 86 Figure 29: CT with Differential Input Connection (Current Sensing) ........................................................ 86 Figure 30: Differential Resistive Shunt Connections (Current Sensing)................................................... 86 Figure 31: System Using Three-Remotes and One-Local (Neutral) Sensor ............................................ 87 Figure 32. System Using Current Transformers ..................................................................................... 88 2 Figure 33: I C EEPROM Connection...................................................................................................... 94 Figure 34: Connections for UART0 ........................................................................................................ 94 Figure 35: Connection for Optical Components ...................................................................................... 95 Figure 36: External Components for the RESET Pin: Push-Button (Left), Production Circuit (Right) ....... 96 Figure 37: External Components for the Emulator Interface ................................................................... 96 Figure 38. Trim Fuse Bit Mapping ........................................................................................................ 118 Figure 39: CE Data Flow: Multiplexer and ADC .................................................................................... 131 Figure 40: CE Data Flow: Scaling, Gain Control, Intermediate Variables for one Phase........................ 131 Figure 41: CE Data Flow: Squaring and Summation Stages ................................................................. 132 Figure 42: Wh Error from 200 A to 0.1 A at 60 Hz, 240 VAC ......................Error! Bookmark not defined. Figure 43: VARh Error from 200 A to 0.1 A at 60 Hz, 240 VAC...................Error! Bookmark not defined. Figure 44: Wh Error from 200 A to 0.1 A at Various Frequencies (0 Load angle, 240 VAC) ............. Error! Bookmark not defined. Figure 45: 100-pin LQFP Package Outline ........................................................................................... 148 Figure 46: Pinout for the LQFP-100 Package ....................................................................................... 149 Figure 47: I/O Equivalent Circuits......................................................................................................... 154 v1.2 (c) 2008-2011 Teridian Semiconductor Corporation 5 71M6543F/H and 71M6543G/GH Data Sheet Tables Table 1. Required CE Code and Settings for 1-Local / 3-Remotes ......................................................... 15 Table 2. Required CE Code and Settings for CT Sensors ...................................................................... 16 Table 3: Multiplexer and ADC Configuration Bits .................................................................................... 19 Table 4. RCMD[4:0] Bits ........................................................................................................................ 23 Table 5: Remote Interface Read Commands ......................................................................................... 23 Table 6: I/O RAM Control Bits for Isolated Sensor .................................................................................. 24 Table 7: Inputs Selected in Multiplexer Cycles ....................................................................................... 26 Table 8: CKMPU Clock Frequencies ...................................................................................................... 30 Table 9: Memory Map ............................................................................................................................ 31 Table 10: Internal Data Memory Map ..................................................................................................... 32 Table 11: Special Function Register Map ............................................................................................... 32 Table 12: Generic 80515 SFRs - Location and Reset Values ................................................................. 33 Table 13: PSW Bit Functions (SFR 0xD0) ............................................................................................... 34 Table 14: Port Registers (SEGDIO0-15) ................................................................................................ 35 Table 15: Stretch Memory Cycle Width .................................................................................................. 35 Table 16. 80515 PCON SFR Register (SFR 0x87).................................................................................... 36 Table 17: Baud Rate Generation............................................................................................................ 36 Table 18: UART Modes ......................................................................................................................... 37 Table 19: The S0CON (UART0) Register (SFR 0x98) ............................................................................. 37 Table 20: The S1CON (UART1) Register (SFR 0x9B) ............................................................................. 38 Table 21: PCON Register Bit Description (SFR 0x87) .............................................................................. 38 Table 22: Timers/Counters Mode Description ........................................................................................ 39 Table 23: Allowed Timer/Counter Mode Combinations ........................................................................... 39 Table 24: TMOD Register Bit Description (SFR 0x89) ............................................................................ 39 Table 25: The TCON Register Bit Functions (SFR 0x88) ........................................................................ 40 Table 26: The IEN0 Bit Functions (SFR 0xA8)........................................................................................ 41 Table 27: The IEN1 Bit Functions (SFR 0xB8)........................................................................................ 41 Table 28: The IEN2 Bit Functions (SFR 0x9A)........................................................................................ 41 Table 29: TCON Bit Functions (SFR 0x88) ............................................................................................. 41 Table 30: The T2CON Bit Functions (SFR 0xC8) .................................................................................... 42 Table 31: The IRCON Bit Functions (SFR 0xC0) .................................................................................... 42 Table 32: External MPU Interrupts ......................................................................................................... 42 Table 33: Interrupt Enable and Flag Bits ................................................................................................ 43 Table 34: Interrupt Priority Level Groups ................................................................................................ 43 Table 35: Interrupt Priority Levels .......................................................................................................... 44 Table 36: Interrupt Priority Registers (IP0 and IP1) ................................................................................. 44 Table 37: Interrupt Polling Sequence ..................................................................................................... 45 Table 38: Interrupt Vectors .................................................................................................................... 45 Table 39: Flash Memory Access ............................................................................................................ 47 Table 40: Bank Switching with FL_BANK[1:0] (SFR 0xB6[1:0])in the 71M6543G/GH ............................... 48 Table 41: Flash Security ........................................................................................................................ 49 Table 42: Clock System Summary ......................................................................................................... 51 Table 43: RTC Control Registers ........................................................................................................... 52 Table 44: I/O RAM Registers for RTC Temperature Compensation ........................................................ 53 Table 45: NV RAM Table Structure ............................................................Error! Bookmark not defined. Table 46: I/O RAM Registers for RTC Interrupts .................................................................................... 55 Table 47: I/O RAM Registers for Temperature and Battery Measurement .............................................. 56 Table 48: Selectable Resources using the DIO_Rn[2:0] Bits................................................................... 59 6 (c) 2008-2011 Teridian Semiconductor Corporation v1.2 71M6543F/H and 71M6543G/GH Data Sheet Table 49: Data/Direction Registers and Internal Resources for SEGDIO0 to SEGDIO15 ........................ 60 Table 50: Data/Direction Registers for SEGDIO16 to SEGDIO31 ........................................................... 61 Table 51: Data/Direction Registers for SEGDIO32 to SEGDIO45 ........................................................... 61 Table 52: Data/Direction Registers for SEGDIO51 to SEGDIO55 ........................................................... 61 Table 53: LCD_VMODE Configurations .................................................................................................. 63 Table 54: LCD Configurations ................................................................................................................ 64 Table 55: LCD Data Registers for SEGDIO46 to SEGDIO55 .................................................................. 65 Table 56: EECTRL Bits for 2-pin Interface............................................................................................... 66 Table 57: EECTRL Bits for the 3-wire Interface ....................................................................................... 67 Table 58: SPI Transaction Fields ........................................................................................................... 69 Table 59: SPI Command Sequences ..................................................................................................... 70 Table 60: SPI Registers ......................................................................................................................... 70 Table 61: TMUX[4:0] Selections ............................................................................................................ 73 Table 62: TMUX2[4:0] Selections........................................................................................................... 74 Table 63: Available Circuit Functions ..................................................................................................... 77 Table 64: VSTAT[2:0] (SFR 0xF9[2:0]) ................................................................................................... 80 Table 65: Wake Enable and Flag Bits .................................................................................................... 82 Table 66: Wake Bits .............................................................................................................................. 83 Table 67: Clear Events for WAKE flags.................................................................................................. 84 Table 68: GAIN_ADJn Compensation Channels (Figure 2, Figure 31, Table 1) ...................................... 91 Table 69: GAIN_ADJx Compensation Channels (Figure 3, Figure 32, Table 2) ...................................... 93 Table 70: I/O RAM Map - Functional Order, Basic Configuration ........................................................... 98 Table 71: I/O RAM Map - Functional Order ......................................................................................... 100 Table 72: I/O RAM Map - Alphabetical Order ...................................................................................... 104 Table 73: Info Page Trim Fuses ........................................................................................................... 118 Table 74: CE EQU[2:0] Equations and Element Input Mapping ............................................................ 121 Table 75: CE Raw Data Access Locations ........................................................................................... 122 Table 76: CESTATUS Register .............................................................................................................. 123 Table 77: CESTATUS Bit Definitions...................................................................................................... 123 Table 78: CECONFIG Register ............................................................................................................. 123 Table 79: CECONFIG Bit Definitions (CE RAM 0x20) ........................................................................... 124 Table 80: Sag Threshold, Phase Measurement, and Gain Adjust Control ............................................. 125 Table 81: CE Transfer Variables (with Shunts) ..................................................................................... 125 Table 82: CE Transfer Variables (with CTs) ......................................................................................... 126 Table 83: CE Energy Measurement Variables (with Shunts)................................................................. 126 Table 84: CE Energy Measurement Variables (with CTs) ..................................................................... 126 Table 85: Other Transfer Variables ...................................................................................................... 127 Table 86: CE Pulse Generation Parameters......................................................................................... 128 Table 87: CE Parameters for Noise Suppression and Code Version..................................................... 129 Table 88: CE Calibration Parameters ................................................................................................... 130 Table 89: Absolute Maximum Ratings .................................................................................................. 133 Table 90: Recommended External Components .................................................................................. 134 Table 91: Recommended Operating Conditions ................................................................................... 134 Table 92: Input Logic Levels ................................................................................................................ 135 Table 93: Output Logic Levels ............................................................................................................. 135 Table 94: Battery Monitor Performance Specifications (TEMP_BAT = 1) ............................................... 136 Table 95: Temperature Monitor............................................................................................................ 137 Table 96: Supply Current Performance Specifications.......................................................................... 138 Table 98: Internal Power Fault Comparators Performance Specifications ............................................. 139 Table 99: 2.5 V Voltage Regulator Performance Specifications ............................................................ 139 v1.2 (c) 2008-2011 Teridian Semiconductor Corporation 7 71M6543F/H and 71M6543G/GH Data Sheet Table 100: Low-Power Voltage Regulator Performance Specifications ................................................. 140 Table 101: Crystal Oscillator Performance Specifications ..................................................................... 140 Table 102: PLL Performance Specifications ......................................................................................... 140 Table 103: LCD Drivers Performance Specifications ............................................................................ 140 Table 105: 71M6543 VREF Performance Specifications ...................................................................... 143 Table 106: ADC Converter Performance Specifications ....................................................................... 144 Table 107: Pre-Amplifier Performance Specifications ........................................................................... 145 Table 108: Flash Memory Timing Specifications .................................................................................. 146 Table 109. SPI Slave Timing Specifications ......................................................................................... 146 Table 110: EEPROM Interface Timing ................................................................................................. 146 Table 111: RESET Pin Timing ............................................................................................................. 147 Table 112: RTC Range for Date........................................................................................................... 147 Table 113: 71M6543 Power and Ground Pins ...................................................................................... 150 Table 114: 71M6543 Analog Pins ........................................................................................................ 151 Table 115: 71M6543 Digital Pins ......................................................................................................... 152 Table 116. 71M6543 Ordering Guide ................................................................................................... 155 8 (c) 2008-2011 Teridian Semiconductor Corporation v1.2 71M6543F/H and 71M6543G/GH Data Sheet VREF IADC0 IADC1 IADC2 IADC3 IADC4 IADC5 IADC6 IADC7 VADC8 (VA) VADC9 (VB) VADC10 (VC) V3P3A GNDA GNDD VLCD V3P3SYS _ AD CONVERTER VBIAS MUX and PREAMP VBIAS VLCD Voltage Boost FIR V3P3A - V3P3D + VREF VREF VBAT MUX MUX CTRL CROSS Voltage Regulator CK32 XIN XOUT MCK PLL RTCLK (32KHz) Oscillator CK32 32KHz 32 KHz DIV ADC 4.9 MHZ CKADC VDD 4.9 MHz CLOCK GEN CKFIR 22 2.5V to logic CK_4X MUX LCD_GEN CKMPU_2x CE MUX _SYNC WPULSE STRT VARPULSE RTM CKCE < 4.9MHz TEST VLC2 VLC1 VLC0 MEMORY SHARE MPU RAM (5 KB) LCD DRIVER 32-bit Compute Engine TEST MODE CEDATA 32 0x000...0x2FF CE CONTROL COM0..5 6 IP S 0x0000...0x13FF SEG Pins 8 PROG 0x000...0x3FF SEGDIO Pins DIGITAL I/O 16 WPULSE Y S U B R E F X Y S U B _ E C M A R O I/ EEPROM INTERFACE CKMPU < 4.9MHz 2 VARPULSE PB RTC VBAT_RTC RTCLK SDCK RX MPU (80515) UART0 SDOUT Non-Volatile CONFIGURATION RAM SDIN TX OPT_RX/ SEGDIO55 OPT_TX/ SEGDIO51/ WPULSE/ VPULSE OPTICAL INTERFACE CONFIGURATION RAM (I/O RAM) DATA 0x0000...0xFFFF 0x2000...0x20FF 8 PROGRAM 0x0000...0xFFFF VBIAS 8 MEMORY SHARE MPU_RSTZ CKMPU_2x 17 CONFIGURATION PARAMETERS EMULATOR PORT WAKE RTM FAULTZ 3 VSTAT RESET TEMP SENSOR 0x00000 ... FLASH 128KB 0X1FFFF 8 POWER FAULT DETECTION BAT TEST TEST MUX TEST MUX 2 E_RXTX E_TCLK E_RST(Open Drain) E_RXTX/SEG48 E_TCLK/SEG49 E_RST/SEG50 ICE_E 9/20/2010 Figure 1: IC Functional Block Diagram v1.2 (c) 2008-2011 Teridian Semiconductor Corporation 9 71M6543F/H and 71M6543G/GH Data Sheet 1 Introduction This data sheet covers the 71M6543F (64KB, 0.5%), 71M6543H (64KB, 0.1%), 71M6543G (128KB, 0.5%) and 71M6543GH (128KB, 0.1%) 4th-generation Teridian polyphase energy measurement systemon-chips (SoCs). The term "71M6543" is used when discussing a device feature or behavior that is applicable to all four part numbers. The specific part numbers are used when discussing those features that apply only to specific part numbers. This data sheet also covers details about the companion 71M6xx3 isolated current sensor device. This document covers the use of the 71M6543 in conjunction with the 71M6xx3 isolated current sensor. The 71M6543 and 71M6xx3 ICs make it possible to use one non-isolated and three additional isolated shunt current sensors to create polyphase energy meters using inexpensive shunt resistors, while achieving unprecedented performance with this type of sensor technology. The 71M6543 SoCs also support Current Transformers (CT). To facilitate document navigation, hyperlinks are often used to reference figures, tables and section headings that are located in other parts of the document. All hyperlinks in this document are highlighted in blue. Hyperlinks are used extensively to increase the level of detail and clarity provided within each section by referencing other relevant parts of the document. To further facilitate document navigation, this document is published as a PDF document with bookmarks enabled. The reader is also encouraged to obtain and review the documents listed in 8 Related Information on page 155 of this document. 10 (c) 2008-2011 Teridian Semiconductor Corporation v1.2 71M6543F/H and 71M6543G/GH Data Sheet 2 Hardware Description 2.1 Hardware Overview The Teridian 71M6543 single-chip energy meter integrates all primary functional blocks required to implement a solid-state electricity meter. Included on the chip are: * * * * * * * * * * * * * An analog front-end (AFE) featuring a 22-bit second-order sigma-delta ADC An independent 32-bit digital computation engine (CE) to implement DSP functions An 8051-compatible microprocessor (MPU) which executes one instruction per clock cycle (80515) A precision voltage reference (VREF) A temperature sensor for digital temperature compensation of: - Metrology (MPU) - Automatic RTC in all power states - MPU assisted RTC compensation LCD Driver RAM and Flash memory A real time clock (RTC) A variety of I/O pins A power failure interrupt A zero-crossing interrupt Selectable current sensor interfaces for locally-connected sensors as well as isolated sensors (i.e., using the 71M6xx3 companion IC with a shunt resistor sensor) Resistive Shunt and Current Transformers are supported In order to implement a polyphase meter with or without neutral current sensing, one resistive shunt current sensor may be connected directly (non-isolated) to the 71M6543 device, while up to three additional current shunts are isolated using a companion 71M6xx3 isolated sensor IC. An inexpensive, small size pulse transformer is used to electrically isolate the 71M6xx3 remote sensor from the 71M6543. The 71M6543 performs digital communications bi-directionally with the 71M6xx3 and also provides power to the 71M6xx3 through the isolating pulse transformer. Isolated (remote) shunt current sensors are connected to the differential input of the 71M6xx3. The 71M6543 may also be used with Current Transformers; in this case the 71M6xx3 isolated sensors are not required. Included on the 71M6xx3 companion isolator chip are: * * * * * * * Digital isolation communications interface An analog front-end (AFE) featuring a 22-bit second-order sigma-delta ADC A precision voltage reference (VREF) A temperature sensor (for current-sensing digital temperature compensation) A fully differential shunt resistor sensor input A pre-amplifier to optimize shunt current sensor performance Isolated power circuitry obtains dc power from pulses sent by the 71M6543 In a typical application, the 32-bit compute engine (CE) of the 71M6543 sequentially processes the samples from the voltage inputs on analog input pins and performs calculations to measure active energy (Wh) and reactive energy (VARh), as well as A2h, and V2h for four-quadrant metering. These measurements are then accessed by the MPU, processed further and output using the peripheral devices available to the MPU. In addition to advanced measurement functions, the real time clock (RTC) function allows the 71M6543 to record time of use (TOU) metering information for multi-rate applications and to time-stamp tamper or other events. An automatic RTC temperature compensation circuit operates in all power states including when the MPU is halted, and continues to compensate using back-up battery power during power outages. Measurements can be displayed on 3.3 V LCDs commonly used in low-temperature environments. The integrated charge pump and temperature sensor can be used by the MPU to enhance 3.3 V LCD performance at cold temperatures. The on-chip charge pump may also drive 5 V LCDs. Flexible mapping of LCD display segments facilitates the integration of existing custom LCDs. Design trade-off between the v1.2 (c) 2008-2011 Teridian Semiconductor Corporation 11 71M6543F/H and 71M6543G/GH Data Sheet number of LCD segments and DIO pins can be implemented in software to accommodate various requirements. In addition to the temperature-trimmed ultra-precision voltage reference, the on-chip digital temperature compensation mechanism includes a temperature sensor and associated controls for correction of unwanted temperature effects on metrology and RTC accuracy (i.e., to meet the requirements of ANSI and IEC standards). Temperature-dependent external components such as the crystal oscillator, current transformers (CTs), Current Shunts and their corresponding signal conditioning circuits can be characterized and their correction factors can be programmed to produce electricity meters with exceptional accuracy over the industrial temperature range. One of the two internal UARTs is adapted to support an Infrared LED with internal drive and sense configuration and can also function as a standard UART. The optical output can be modulated at 38 kHz. This flexibility makes it possible to implement AMR meters with an IR interface. A block diagram of the IC is shown in Figure 1. 2.2 Analog Front-End (AFE) The AFE functions as a data acquisition system, controlled by the MPU. The 71M6543 AFE may also be augmented by isolated 71M6xx3 sensors in order to support low-cost current shunt sensors. Figure 2, and Figure 3 show the two most common configurations; other configurations are possible. Sensors that are connected directly to the 71M6543 (i.e., IADC0-IADC1, VADC8, VADC9 and VADC10) are multiplexed into the single second-order sigma-delta ADC input for sampling in the 71M6543. The 71M6543 ADC output is decimated by the FIR filter and stored in CE RAM where it can be accessed and processed by the CE. Shunt current sensors that are isolated by using a 71M6xx3 device, are sampled by a second-order sigma delta ADC in the 71M6xx3 and the signal samples are transferred over the digital isolation interface through the low-cost isolation pulse transformer. Figure 2 shows the 71M6543 using shunt current sensors and the 71M6xx3 isolated sensor devices. Figure 2 supports neutral current measurement with a local shunt connected to the IADC0-IADC1 input plus three remote (isolated) shunt sensors. As seen in Figure 2, when a remote isolated shunt sensor is connected via the 71M6xx3, the samples associated with this current channel are not routed to the multiplexer, and are instead transferred digitally to the 71M6543 via the isolation interface and are directly stored in CE RAM. The MUX_SELn[3:0] I/O RAM control fields allow the MPU to configure the AFE for the desired multiplexer sampling sequence. Refer to Table 1 and Table 2 for the appropriate CE code and the corresponding AFE settings. See Figure 31 for the meter wiring configuration corresponding to Figure 2. VREF IN* IADC0 Local Shunt MUX VREF ADC CONVERTER VREF IADC1 FIR VADC VADC8 (VA) 22 VADC9 (VB) VADC10 (VC) IA INP Remote Shunt SP IADC2 SN IADC3 71M6xx3 22 INN CE RAM IB INP Remote Shunt SP IADC4 SN IADC5 SP IADC6 SN IADC7 71M6xx3 Digital Isolation Interface 22 INN IC INP Remote Shunt 71M6xx3 22 INN 71M6543 *IN = Neutral Current 9/17/2010 Figure 2: AFE Block Diagram (Shunts: One-Local, Three-Remotes) 12 (c) 2008-2011 Teridian Semiconductor Corporation v1.2 71M6543F/H and 71M6543G/GH Data Sheet The 71M6543 AFE can also be directly interfaced to Current Transformers (CTs), as seen in Figure 3. In this case, all voltage and current channels are multiplexed into a single second-order sigma-delta ADC in the 71M6543 and the 71M6xx3 remote isolated sensors are not used. The fourth CT and the measurement of Neutral current via the IADC0-IADC1 current channel are optional. See Figure 32 for the meter wiring configuration corresponding to Figure 3. VREF IA IADC2 ADC CONVERTER MUX CT VREF IADC3 VREF FIR VADC CE RAM 22 IB IADC4 CT IADC5 IC IADC6 CT IADC7 IN* IADC0 CT IADC1 VADC8 (VA) VADC9 (VB) VADC10 (VC) 71M6543 *IN = Neutral Current 9/17/2010 Figure 3. AFE Block Diagram (Four CTs) 2.2.1 Signal Input Pins The 71M6543 features eleven ADC input pins. IADC0 through IADC7 are intended for use as current sensor inputs. These eight current sensor inputs can be configured as eight single-ended inputs, or can be paired to form four differential inputs. For best performance, it is recommended to configure the current sensor inputs as differential inputs (i.e., IADC0IADC1, IADC2-IADC3, IADC4-IADC5 and IADC6-IADC7). The first differential input (IADC0-IADC1) features a pre-amplifier with a selectable gain of 1 or 8, and is intended for direct connection to a shunt resistor sensor, and can also be used with a Current Transformer (CT). The three remaining differential pairs (i.e., IADC2-IADC3, IADC4-IADC5 and IADC6-IADC7) may be used with CTs, or may be enabled to interface to a remote 71M6xx3 isolated current sensor providing isolation for a shunt resistor sensor using a low cost pulse transformer. The remaining three inputs VADC8 (VA), VADC9 (VB) and VADC10 (VC) are single-ended, and are intended for sensing each of the phase voltages in a polyphase meter application. These three single-ended inputs are referenced to the V3P3A pin. All ADC input pins measure voltage. In the case of shunt current sensors, currents are sensed as a voltage drop in the shunt resistor sensor. In the case of Current Transformers (CT), the current is measured as a voltage across a burden resistor that is connected to the secondary of the CT. Meanwhile, line voltages are sensed through resistive voltage dividers. The VADC8 (VA), VADC9 (VB) and VADC10 (VC) pins are single-ended and their common return is the V3P3A pin. See Figure 27, Figure 28, Figure 29 and Figure 30 for detailed connections for each type of sensor. Also refer to the 71M6543 Demonstration Board schematic and bill of materials for typical component values used in these and other circuits. v1.2 (c) 2008-2011 Teridian Semiconductor Corporation 13 71M6543F/H and 71M6543G/GH Data Sheet Pins IADC0-IADC1 can be programmed individually to be differential or single-ended as determined by the DIFF0_E (I/O RAM 0x210C[4]) control bit. However, for most applications, IADC0-IADC1 are configured as a differential input to work with a resistive shunt or CT directly interfaced to the IADC0IADC1 differential input with the appropriate external signal conditioning components. The performance of the IADC0-IADC1 pins can be enhanced by enabling a pre-amplifier with a fixed gain of 8, using the I/O RAM control bit PRE_E (I/O RAM 0x2704[5]). When PRE_E = 1, IADC0-IADC1 become the inputs to the 8x pre-amplifier, and the output of this amplifier is supplied to the multiplexer. The 8x amplification is useful when current sensors with low sensitivity, such as shunt resistors, are used. With PRE_E set, the IADC0-IADC1 input signal amplitude is restricted to 31.25 mV peak. When PRE_E = 0 (Gain = 1), the IADC0-IADC1 input signal is restricted to 250 mV peak. For the 71M6543 application utilizing shunt resistor sensors (Figure 2), the IADC0-IADC1 pins are configured for differential mode to interface to a local shunt by setting the DIFF0_E control bit. Meanwhile, the IADC2-IADC3 , IADC4-IADC5 and IADC6-IADC7 pins are re-configured as digital remote sensor interface designed to communicate with a Teridian 71M6xx3 isolated sensor by setting the RMTx_E control bits (I/O RAM 0x2709[5:3]). The 71M6xx3 communicates with the 71M6543 using a bi-directional digital data stream through an isolating pulse transformer. The 71M6543 also supplies power to the 71M6xx3 through the isolating transformer. This type of interface is further described at the end of this chapter. See 2.2.8 71M6xx3 Isolated Sensor Interface. For use with Current Transformers (CTs), as shown in Figure 3, the RMTx_E control bits are reset, so that IADC2-IADC3, IADC4-IADC5 and IADC6-IADC7 are configured as local analog inputs. The IADC0-IADC1 pins cannot be configured as a remote sensor interface. 2.2.2 Input Multiplexer When operating with locally connected sensors, the input multiplexer sequentially applies the input signals from the analog input pins to the input of the ADC (see Figure 3), according to the sampling sequence determined by the eleven MUXn_SEL[3:0] control fields. One complete sampling sequence is called a multiplexer frame. The multiplexer of the 71M6543 can select up to eleven input signals when the current sensor inputs are configured for single-ended mode. When the current sensor inputs are configured in differential mode (recommended for best performance), the number of input signals is seven (i.e., IADC0IADC1, IADC2-IADC3, IADC4-IADC5, IADC6-IADC7, VADC8, VADC9 and VADC10) per multiplexer frame. The number of slots in the multiplexer frame is controlled by the I/O RAM control field MUX_DIV[3:0] (I/O RAM 0x2100[7:4]) (see Figure 4). The multiplexer always starts at state 0 and proceeds until the number of sensor channels determined by the MUX_DIV[3:0] field setting have been converted. The 71M6543 requires a unique CE code that is written for the specific meter configuration. Moreover, each CE code requires specific AFE and MUX settings in order to function properly. Table 1 provides the CE code and settings corresponding to the 1-Local / 3-Remote sensor configuration shown in Figure 2. Table 2 provides the CE code and settings corresponding to the CT configuration shown in Figure 3. 14 (c) 2008-2011 Teridian Semiconductor Corporation v1.2 71M6543F/H and 71M6543G/GH Data Sheet Table 1. Required CE Code and Settings for 1-Local / 3-Remotes I/O RAM I/O RAM I/O RAM Setting Comments Mnemonic Location FIR_LEN[1:0] 210C[2:1] 1 288 cycles ADC_DIV 2200[5] 0 Fast PLL_FAST 2200[4] 1 19.66 MHz MUX_DIV[3:0] 2100[7:4] 6 See note 1 MUX0_SEL[3:0] Slot 0 is IADC0-IADC1 2105[3:0] 0 (IN) MUX1_SEL[3:0] 2105[7:4] 1 Unused (See note 2) MUX2_SEL[3:0] 2104[3:0] 1 Unused (See note 2) MUX3_SEL[3:0] Slot 3 is VADC8 2104[7:4] 8 (VA) MUX4_SEL[3:0] Slot 4 is VADC9 2103[3:0] 9 (VB) MUX5_SEL[3:0] Slot 5 is VADC10 2103[7:4] A (VC) MUX6_SEL[3:0] 2102[3:0] 0 MUX7_SEL[3:0] 2102[7:4] 0 MUX8_SEL[3:0] 2101[3:0] 0 Slots not enabled MUX9_SEL[3:0] 2101[7:4] 0 MUX10_SEL[3:0] 2100[3:0] 0 RMT2_E 2709[3] 1 Enable Remote IADC2-IADC3 (IA) RMT4_E 2709[4] 1 Enable Remote IADC4-IADC5 (IB) RMT6_E 2709[5] 1 Enable Remote IADC6-IADC7 (IC) DIFF0_E 210C[4] 1 Differential IADC0-IADC1 (IN) DIFF2_E 210C[5] 0 See note 3 DIFF4_E 210C[6] 0 See note 3 DIFF6_E 210C[7] 0 See note 3 PRE_E 2704[5] 1 IADC0-IADC1 Gain = 8 EQU[2:0] 2106[7:5] 5 IA*VA + IB*VB + IC*VC ce43b016603 (use with 71M6603) CE Codes ce43b016103 (use with 71M6103) (See note 4) ce43b016113 (use with 71M6113) ce43b016203 (use with 71M6203) Equation(s) 5 Current Sensor Type 1 Local Shunt and 3 Remote Shunts Applicable Figures Figure 2, Figure 4 and Figure 31 Notes: 1. MUX_DIV[3:0] should be set to 0 while writing the other values in this table, and then set to the indicated value before writing the MUXn_SEL[3:0] fields. 2. Each unused slot must be assigned to a valid (0 to A), but unused ADC handle 3. This channel is remote (71M6xx3), hence DIFFx_E is irrelevant 4. Must use the CE code that corresponds to the specific 71M6xx3 device used Teridian updates the CE code periodically. Please contact your local Teridian representative to obtain the latest CE code and the associated settings. v1.2 (c) 2008-2011 Teridian Semiconductor Corporation 15 71M6543F/H and 71M6543G/GH Data Sheet Table 2. Required CE Code and Settings for CT Sensors I/O RAM I/O RAM I/O RAM Setting Comments Mnemonic Location (Hex) FIR_LEN[1:0] 210C[2:1] 1 288 cycles ADC_DIV 2200[5] 0 Fast PLL_FAST 2200[4] 1 19.66 MHz MUX_DIV[3:0] 2100[7:4] 7 See note 1 MUX0_SEL[3:0] Slot 0 is IADC2-IADC3 2105[3:0] 2 (IA) MUX1_SEL[3:0] Slot 1 is VADC8 2105[7:4] 8 (VA) MUX2_SEL[3:0] Slot 2 is IADC4-IADC5 2104[3:0] 4 (IB) MUX3_SEL[3:0] Slot 3 is VADC9 2104[7:4] 9 (VB) MUX4_SEL[3:0] Slot 4 is IADC6-IADC7 2103[3:0] 6 (IC) MUX5_SEL[3:0] Slot 5 is VADC10 2103[7:4] A (VC) MUX6_SEL[3:0] 2102[3:0] 0 Slot 6 is IADC0-IADC1 (IN - See note 2) MUX7_SEL[3:0] 2102[7:4] 0 MUX8_SEL[3:0] 2101[3:0] 0 Slots not enabled MUX9_SEL[3:0] 2101[7:4] 0 MUX10_SEL[3:0] 2100[3:0] 0 RMT2_E 2709[3] 0 Local Sensor IADC2-IADC3 RMT4_E 2709[4] 0 Local Sensor IADC4-IADC5 RMT6_E 2709[5] 0 Local Sensor IADC6-IADC7 DIFF0_E 210C[4] 1 Differential IADC0-IADC1 DIFF2_E 210C[5] 1 Differential IADC2-IADC3 DIFF4_E 210C[6] 1 Differential IADC4-IADC5 DIFF6_E 210C[7] 1 Differential IADC6-IADC7 PRE_E 2704[5] 0 IADC0-IADC1 Gain = 1 EQU[2:0] 2106[7:5] 5 IA*VA + IB*VB + IC*VC CE Code ce43a02 Equation(s) 5 Current Sensor Type 4 Current Transformers (CTs) Applicable Figures Figure 3, Figure 4 and Figure 32 Notes: 1. MUX_DIV[3:0] should be set to 0 while writing the other values in this table, and then set to the indicated value before writing the MUXn_SEL[3:0] fields. 2. IN is the optional Neutral Current Teridian updates the CE code periodically. Please contact your local Teridian representative to obtain the latest CE code and the associated settings. 16 (c) 2008-2011 Teridian Semiconductor Corporation v1.2 71M6543F/H and 71M6543G/GH Data Sheet Using settings for the I/O RAM Mnemonics listed in Table 1 and Table 2 that do not match those required by the corresponding CE code being used may result in undesirable side effects and must not be selected by the MPU. Consult your local Teridian representative to obtain the correct CE code and AFE / MUX settings corresponding to the application. For a polyphase configuration with neutral current sensing using shunt resistor current sensors and the 71M6xx3 isolated sensors, as shown in Figure 2, the IADC0-IADC1 input must be configured as a differential input, to be connected to a local shunt (see Figure 30 for the shunt connection details). The local shunt connected to the IADC0-IADC1 input is used to sense the Neutral current. The voltage sensors (VADC8, VADC9 and VADC10) are also directly connected to the 71M6543 (see Figure 27 for the connection details) and are also routed though the multiplexer, as seen in Figure 2. Meanwhile, the IADC2-IADC3, IADC4-IADC5 and IADC6-IADC7 current inputs are configured as remote sensor digital interfaces and the corresponding samples are not routed through the multiplexer. For this configuration, the multiplexer sequence is as shown in Figure 4. For a polyphase configuration with optional neutral current sensing using Current Transformer (CTs) sensors, as shown in Figure 3, all four current sensor inputs must be configured as a differential inputs, to be connected to their corresponding CTs (see Figure 29 for the differential CT connection details). The IADC0-IADC1 current sensor input is optionally used to sense the Neutral current for anti-tampering purposes. The voltage sensors (VADC8, VADC9 and VADC10) are directly connected to the 71M6543 (see Figure 27 for the voltage sensor connection details). No 71M6xx3 isolated sensors are used in this configuration and all sensors are routed though the multiplexer, as seen in Figure 3. For this configuration, the multiplexer sequence is as shown in Figure 5. The multiplexer sequence shown in Figure 4 corresponds to the configuration shown in Figure 2. The frame duration is 13 CK32 cycles (where CK32 = 32,768 Hz), therefore, the resulting sample rate is 32,768 Hz / 13 = 2,520.6 Hz. Note that Figure 4 only shows the currents that pass through the 71M6543 multiplexer, and does not show the currents that are copied directly into CE RAM from the remote sensors (see Figure 2), which are sampled during the second half of the multiplexer frame. The two unused conversion slots shown are necessary to produce the desired 2,520.6 Hz sample rate. Multiplexer Frame MUX_DIV[3:0] = 6 Conversions Settle CK32 MUX STATE S 0 1 2 3 IN Unused Unused VA 4 5 VB S VC CROSS MUX_SYNC Figure 4: States in a Multiplexer Frame (MUX_DIV[3:0] = 6) The multiplexer sequence shown in Figure 5 corresponds to the CT configuration shown in Figure 3. Since in this case all current sensors are locally connected to the 71M6543, all currents are routed through the multiplexer, as seen in Figure 3. For this multiplexer sequence, the frame duration is 15 CK32 cycles (where CK32 = 32,768 Hz), therefore, the resulting sample rate is 32,768 Hz / 15 = 2,184.5 Hz. Multiplexer Frame Settle MUX_DIV[3:0] = 7 Conversions CK32 MUX STATE S 0 IA 1 VA 2 IB 3 VB 4 IC 5 VC 6 IN S CROSS MUX_SYNC Figure 5: States in a Multiplexer Frame (MUX_DIV[3:0] = 7) v1.2 (c) 2008-2011 Teridian Semiconductor Corporation 17 71M6543F/H and 71M6543G/GH Data Sheet Multiplexer advance, FIR initiation and chopping of the ADC reference voltage (using the internal CROSS signal, see 2.2.7 Voltage References) are controlled by the internal MUX_CTRL circuit. Additionally, MUX_CTRL launches each pass of the CE through its code. MUX_CTRL is clocked by CK32, the 32768 Hz clock from the PLL block. The behavior of the MUX_CTRL circuit is governed by: * * * * CHOP_E[1:0] (I/O RAM 0x2106[3:2]) MUX_DIV[3:0] (I/O RAM 0x2100[7:4]) FIR_LEN[1:0] (I/O RAM 0x210C[2:1]) ADC_DIV (I/O RAM 0x2200[5]) The duration of each multiplexer state depends on the number of ADC samples processed by the FIR as determined by the FIR_LEN[1:0] (I/O RAM 0x210C[2:1] control field. Each multiplexer state starts on the rising edge of CK32, the 32-kHz clock. It is recommended that MUX_DIV[3:0] (I/O RAM 0x2200[2:0]) be set to zero while changing the ADC configuration, to minimize system transients that might be caused by momentary shorts between the ADC inputs, especially when changing the DIFFn_E control bits (I/O RAM 0x210C[5:4]). After the configuration bits are set, MUX_DIV[3:0] should be set to the required value. The duration of each time slot in CK32 cycles depends on FIR_LEN[1:0], ADC_DIV and PLL_FAST: Time_Slot_Duration = (3-2*PLL_FAST)*(FIR_LEN[1:0]+1) * (ADC_DIV+1) The duration of a multiplexer frame in CK32 cycles is: MUX_Frame_Duration = 3-2*PLL_FAST + Time_Slot_Duration * MUX_DIV[3:0] The duration of a multiplexer frame in CK_FIR cycles is: MUX frame duration (CK_FIR cycles) = [3-2*PLL_FAST + Time_Slot_Duration * MUX_DIV] * (48+PLL_FAST*102) The ADC conversion sequence is programmable through the MUXn_SEL control fields (I/O RAM 0x2100 to 0x2105). As stated above, there are up to eleven ADC time slots in the 71M6543, as set by MUX_DIV[3:0] (I/O RAM 0x2100[7:4]). In the expression MUXn_SEL[3:0] = x, `n' refers to the multiplexer frame time slot number and `x' refers to the desired ADC input number or ADC handle (i.e., IADC0 to VADC10, or simply 0 to 10 decimal). Thus, there are a total of 11 valid ADC handles in the 71M6543 devices. For example, if MUX0_SEL[3:0] = 0, then IADC0, corresponding to the sample from the IADC0-IADC1 input (configured as a differential input), is positioned in the multiplexer frame during time slot 0. See Table 1 and Table 2 for the appropriate MUXn_SEL[3:0] settings and other settings applicable to a particular meter configuration and CE code. Note that when the remote sensor interface is enabled, the samples corresponding to the remote sensor currents do not pass through the 71M6543 multiplexer. The sampling of the remote current sensors occurs in the second half of the multiplexer frame. The VA, VB and VC voltages are assigned the last three slots in the frame. With this slot assignment for VA, VB and VC, the sampling of the corresponding remote sensor currents bears a precise timing relationship to their corresponding phase voltages, and delay compensation is accurately performed (see 2.2.3 Delay Compensation on page 19). Also when using remote sensors, it is necessary to introduce unused slots to realize the number of slots specified by the MUX_DIV[3:0] (I/O RAM 0x2100[7:4]) field setting (see Figure 4 and Figure 5). The MUXn_SEL[3:0] control fields for these unused ("dummy") slots must be written with a valid ADC handle (i.e., 0 to 10 decimal) that is not otherwise being used. In this manner, the unused ADC handle, is used as a "dummy" place holder in the multiplexer frame, and the correct duration multiplexer frame sequence is generated and also the desired sample rate. The resulting sample data stored in the CE RAM location corresponding to the "dummy" ADC handle is ignored by the CE code. Meanwhile, the digital isolation interface takes care of automatically storing the samples for the remote current sensors in the appropriate CE RAM locations. 18 (c) 2008-2011 Teridian Semiconductor Corporation v1.2 71M6543F/H and 71M6543G/GH Data Sheet Delay compensation and other functions in the CE code require the settings for MUX_DIV[3:0], MUXn_SEL[3:0], RMT_E, FIR_LEN[1:0], ADC_DIV and PLL_FAST to be fixed for a given CE code. Refer to Table 1 and Table 2 for the settings that are applicable to the 71M6543. Table 3 summarizes the I/O RAM registers used for configuring the multiplexer, signals pins, and ADC. All listed registers are 0 after reset and wake from battery modes, and are readable and writable. Table 3: Multiplexer and ADC Configuration Bits Name Location Description MUX0_SEL[3:0] MUX1_SEL[3:0] MUX2_SEL[3:0] MUX3_SEL[3:0] MUX4_SEL[3:0] MUX5_SEL[3:0] MUX6_SEL[3:0] MUX7_SEL[3:0] MUX8_SEL[3:0] MUX9_SEL[3:0] MUX10_SEL[3:0] ADC_DIV MUX_DIV[3:0] PLL_FAST FIR_LEN[1:0] DIFF0_E DIFF2_E DIFF4_E DIFF6_E 2105[3:0] 2105[7:4] 2104[3:0] 2104[7:4] 2103[3:0] 2103[7:4] 2102[3:0] 2102[7:0] 2101[3:0] 2101[7:0] 2100[3:0] 2200[5] 2100[7:4] 2200[4] 210C[2:1] 210C[4] 210C[5] 210C[6] 210C[7] Selects the ADC input converted during time slot 0. Selects the ADC input converted during time slot 1. Selects the ADC input converted during time slot 2. Selects the ADC input converted during time slot 3. Selects the ADC input converted during time slot 4. Selects the ADC input converted during time slot 5. Selects the ADC input converted during time slot 6. Selects the ADC input converted during time slot 7. Selects the ADC input converted during time slot 8. Selects the ADC input converted during time slot 9. Selects the ADC input converted during time slot 10. Controls the rate of the ADC and FIR clocks. The number of ADC time slots in each multiplexer frame (maximum = 11). Controls the speed of the PLL and MCK. Determines the number of ADC cycles in the ADC decimation FIR filter. Enables the differential configuration for analog input pins IADC0-IADC1 . Enables the differential configuration for analog input pins IADC2-IADC3 . Enables the differential configuration for analog input pins IADC4-IADC5 . Enables the differential configuration for analog input pins IADC6-IADC7 . Enables the remote sensor interface transforming pins IADC2-IADC3 into a digital RMT2_E 2709[3] interface for communications with a 71M6xx3 sensor. Enables the remote sensor interface transforming pins IADC4-IADC5 into a digital RMT4_E 2709[4] interface for communications with a 71M6xx3 sensor. Enables the remote sensor interface transforming pins IADC6-IADC7 into a digital RMT6_E 2709[5] interface for communications with a 71M6xx3 sensor. PRE_E 2704[5] Enables the 8x pre-amplifier. Refer to Table 71 starting on page 104 for more complete details about these I/O RAM locations. 2.2.3 Delay Compensation When measuring the energy of a phase (i.e., Wh and VARh) in a service, the voltage and current for that phase must be sampled at the same instant. Otherwise, the phase difference, , introduces errors. = t delay T 360 o = t delay f 360 o Where f is the frequency of the input signal, T = 1/f and tdelay is the sampling delay between current and voltage. Traditionally, sampling is accomplished by using two A/D converters per phase (one for voltage and the other one for current) controlled to sample simultaneously. Teridian's Single-Converter Technology(R), however, exploits the 32-bit signal processing capability of its CE to implement "constant delay" all-pass filters. The all-pass filter corrects for the conversion time difference between the voltage and the corresponding current samples that are obtained with a single multiplexed A/D converter. o The "constant delay" all-pass filter provides a broad-band delay 360 - , which is precisely matched to the difference in sample time between the voltage and the current of a given phase. This digital filter does not affect the amplitude of the signal, but provides a precisely controlled phase response. v1.2 (c) 2008-2011 Teridian Semiconductor Corporation 19 71M6543F/H and 71M6543G/GH Data Sheet The recommended ADC multiplexer sequence samples the current first, immediately followed by sampling of the corresponding phase voltage, thus the voltage is delayed by a phase angle relative to the current. The delay compensation implemented in the CE aligns the voltage samples with their corresponding current samples by first delaying the current samples by one full sample interval (i.e., o 360 ), then routing the voltage samples through the all-pass filter, thus delaying the voltage samples by 360o - , resulting in the residual phase error between the current and its corresponding voltage of - . The residual phase error is negligible, and is typically less than 1.5 milli-degrees at 100Hz, thus it does not contribute to errors in the energy measurements. When using remote sensors, the CE performs the same delay compensation described above to align each voltage sample with its corresponding current sample. Even though the remote current samples do not pass through the 71M6543 multiplexer, their timing relationship to their corresponding voltages is fixed and precisely known, provided that the MUXn_SEL[3:0] slot assignment fields are programmed as shown in Table 1. Note that these slot assignments result in VA, VB and VC occupying multiplexer slots 3, 4 and 5, respectively (see Figure 4). 2.2.4 ADC Pre-Amplifier The ADC pre-amplifier is a low-noise differential amplifier with a fixed gain of 8 available only on the IADC0-IADC1 sensor input pins. A gain of 8 is enabled by setting PRE_E = 1 (I/O RAM 0x2704[5]). When disabled, the supply current of the pre-amplifier is <10 nA and the gain is unity. With proper settings of the PRE_E and DIFF0_E (I/O RAM 0x210C[4]) bits, the pre-amplifier can be used whether differential mode is selected or not. For best performance, the differential mode is recommended. In order to save power, the bias current of the pre-amplifier and ADC is adjusted according to the ADC_DIV control bit (I/O RAM 0x2200[5]). 2.2.5 A/D Converter (ADC) A single 2nd order sigma-delta A/D converter digitizes the voltage and current inputs to the device. The resolution of the ADC, including the sign bit, is 21 bits (FIR_LEN[1:0] = 01, I/O RAM 0x210C[2:1]), or 22 bits (FIR_LEN[1:0] = 10). The ADC is clocked by CKADC. Initiation of each ADC conversion is controlled by the internal MUX_CTRL circuit as described earlier. At the end of each ADC conversion, the FIR filter output data is stored into the CE RAM location determined by the multiplexer selection. 2.2.6 FIR Filter The finite impulse response filter is an integral part of the ADC and it is optimized for use with the multiplexer. The purpose of the FIR filter is to decimate the ADC output to the desired resolution. At the end of each ADC conversion, the output data is stored into the fixed CE RAM location determined by the multiplexer selection stored in the MUXn_SEL[3:0] fields. FIR data is stored after being shifted left by 9 bits. 2.2.7 Voltage References A bandgap circuit provides the reference voltage to the ADC. The amplifier within the reference is chopper stabilized, i.e., the chopper circuit can be enabled or disabled by the MPU using the I/O RAM control field CHOP_E[1:0] (I/O RAM 0x2106[3:2]). The two bits in the CHOP_E[1:0] field enable the MPU to operate the chopper circuit in regular or inverted operation, or in toggling modes (recommended). When the chopper circuit is toggled in between multiplexer cycles, dc offsets on VREF are automatically be averaged out, therefore the chopper circuit should always be configured for one of the toggling modes. Since the VREF band-gap amplifier is chopper-stabilized, the dc offset voltage, which is the most significant long-term drift mechanism in the voltage references (VREF), is automatically removed by the chopper circuit. Both the 71M6543 and the 71M6xx3 feature chopper circuits for their respective VREF voltage reference. The general topology of a chopped amplifier is shown in Figure 6. The CROSS signal is an internal onchip signal and is not accessible on any pin or register. 20 (c) 2008-2011 Teridian Semiconductor Corporation v1.2 71M6543F/H and 71M6543G/GH Data Sheet A Vinp B A Vinn B A + G - Voutp B A Voutn B CROSS Figure 6: General Topology of a Chopped Amplifier It is assumed that an offset voltage Voff appears at the positive amplifier input. With all switches, as controlled by CROSS (an internal signal), in the A position, the output voltage is: Voutp - Voutn = G (Vinp + Voff - Vinn) = G (Vinp - Vinn) + G Voff With all switches set to the B position by applying the inverted CROSS signal, the output voltage is: Voutn - Voutp = G (Vinn - Vinp + Voff) = G (Vinn - Vinp) + G Voff, or Voutp - Voutn = G (Vinp - Vinn) - G Voff Thus, when CROSS is toggled, e.g., after each multiplexer cycle, the offset alternately appears on the output as positive and negative, which results in the offset effectively being eliminated, regardless of its polarity or magnitude. When CROSS is high, the connection of the amplifier input devices is reversed. This preserves the overall polarity of that amplifier gain; it inverts its input offset. By alternately reversing the connection, the amplifier's offset is averaged to zero. This removes the most significant long-term drift mechanism in the voltage reference. The CHOP_E[1:0] (I/O RAM 0x2106[3:2]) control field controls the behavior of CROSS. On the first CK32 rising edge after the last multiplexer state of its sequence, the multiplexer waits one additional CK32 cycle before beginning a new frame. At the beginning of this cycle, the value of CROSS is updated according to the CHOP_E[1:0] field. The extra CK32 cycle allows time for the chopped VREF to settle. During this cycle, MUXSYNC is held high. The leading edge of MUXSYNC initiates a pass through the CE program sequence. CHOP_E[1:0] has four states: positive, reverse, and two toggle states. In the positive state, CHOP_E[1:0] = 01, CROSS is held low. In the reverse state, CHOP_E[1:0] = 10, CROSS is held high. The two automatic toggling states are selected by setting CHOP_E=11 or CHOP_E=00. Figure 7: CROSS Signal with CHOP_E = 00 Figure 7 shows CROSS over two accumulation intervals when CHOP_E[1:0] = 00: At the end of the first interval, CROSS is high, at the end of the second interval, CROSS is low. Operation with CHOP_E[1:0] = 00 does not require control of the chopping mechanism by the MPU. In the second toggle state, CHOP_E[1:0] = 11, CROSS does not toggle at the end of the last multiplexer cycle in an accumulation interval. v1.2 (c) 2008-2011 Teridian Semiconductor Corporation 21 71M6543F/H Data Sheet 2.2.8 8 71M6xx3 Isolated Sensor Interface 2.2.8.1 General Description Non-isolating sensors, such as shunt resistors, can be connected to the inputs of the 71M6543 via a combination of a pulse transformer and a 71M6xx3 IC (a top-level block diagram of this sensor interface is shown in Figure 31). The 71M6xx3 receives power directly from the 71M6543 via a pulse transformer and does not require a dedicated power supply circuit. The 71M6xx3 establishes 2-way communication with the 71M6543, supplying current samples and auxiliary information such as sensor temperature via a serial data stream. Up to three 71M6xx3 Isolated Sensors can be supported by the 71M6543. When a remote sensor interface is enabled, the two analog current inputs become re-configured as a digital remote sensor interface. For example, when control bit RMT2_E = 1, the IADC2-IADC3 analog pins are re-configured as the digital interface pins to the remote sensor. Each 71M6xx3 Isolated Sensor consists of the following building blocks: * * * * * * Power supply that derives power from pulses received from the 71M6543 Bi-directional digital communications interface Shunt signal pre-amplifier 22-bit 2nd Order Sigma-Delta ADC Converter with precision bandgap reference (chopping amplifier) Temperature sensor (for digitally compensating VREF) Fuse system containing part-specific information During an ordinary multiplexer cycle, the 71M6543 internally determines which other channels are enabled with MUX_DIV[3:0] (I/O RAM 0x2100[7:4]). At the same time, it decimates the modulator output from the 71M6xx3 Isolated Sensors. Each result is written to CE RAM during one of its CE access time slots. 2.2.8.2 Communication between 71M6543 and 71M6xx3 Isolated Sensor The ADC of the 71M6xx3 derives its timing from the power pulses generated by the 71M6543 and as a result, operates its ADC slaved to the frequency of the power pulses. The generation of power pulses, as well as the communication protocol between the 71M6543 and 71M6xx3 Isolated Sensor, is automatic and transparent to the user. Details are not covered in this data sheet. 2.2.8.3 Control of the 71M6xx3 Isolated Sensor The 71M6543 can read or write certain types of information from each 71M6xx3 remote sensor. The data to be read is selected by a combination of the RCMD[4:0] and TMUXRn[2:0]. To perform a read transaction from one of the 71M6xx3 devices, the MPU first writes the TMUXRn[2:0] field (where n = 2, 4, 6, located at I/O RAM 0x270A[2:0], 0x270A[6:4] and 0x2709[2:0], respectively). Next, the MPU writes RCMD[4:0] (SFR 0xFC[4:0]) with the desired command and phase selection. When the RCMD[4:2] bits have cleared to zero, the transaction has been completed and the requested data is available in RMT_RD[15:0] (I/O RAM 0x2602[7:0] is the MSB and 0x2603[7:0] is the LSB). The read parity error bit, PERR_RD (SFR 0xFC[6]) is also updated during the transaction. If the MPU writes to RCMD[4:0] before a previously initiated read transaction is completed, the command is ignored. Therefore, the MPU must wait for RCMD[4:2]=0 before proceeding to issue the next remote sensor read command. If the CE is running (CE_E=1), the MPU must write RCMD[4:0] immediately after a CE_BUSY rising edge. RCMD[4:0] must be written before the next rising edge of MUX_SYNC. Failure to do this can cause incorrect data to be read. The RCMD[4:0] field is divided into two sub-fields, COMMAND=RCMD[4:2] and PHASE=RCMD[1:0], as shown in Table 4. . 22 (c) 2008-2010 MAXIM/TERIDIAN Semiconductor Corporation v1.2 8 71M6543F/H Data Sheet Table 4. RCMD[4:0] Bits Command Phase Selector Associated TMUXRn RCMD[4:2] RCMD[1:0] Control Field --000 Invalid 00 Invalid IADC2-IADC3 001 Command 1 01 TMUXR2[2:0] IADC4-IADC5 010 Command 2 10 TMUXR4[2:0] IADC6-IADC7 011 Reserved 11 TMUXR6[2:0] 100 Reserved 101 Invalid 110 Reserved 111 Reserved Notes: 1. Only two codes of RCMD[4:2] (SFR 0xFC[4:2]) are relevant for normal operation. These are RCMD[4:2] = 001 and 010. Codes 000 and 101 are invalid and will be ignored if used. The remaining codes are reserved and must not be used. 2. For the RCMD[1:0] control field, codes 01, 10 and 11 are valid and 00 is invalid and must not be used. 3. The specific phase (A, B or C) associated with each TMUXRn[2:0] field, is determined by how the IADCn input pins are connected in the meter design. Table 5 shows the allowable combinations of values in RCMD[4:2] and TMUXRn[2:0], and the corresponding data type and format sent back by the 71M6xx3 remote sensor and how the data is stored in RMT_RD[15:8] and RMT_RD[7:0]. The MPU selects which of the three phases is read by asserting the proper code in the RCMD[1:0] field, as shown in Table 4. . Table 5: Remote Interface Read Commands RCMD[4:2] TMUXRn[2:0] 001 00X Read Operation TRIMT[7:0] 001 11X TRIMBGB[7:0] and TRIMBGD[7:0] (trim fuse for all 71M6xx3) RMT_RD [15:8] RMT_RD [7:0] TRIMT[7]=RMT_RD[8] TRIMT[6:0]=RMT_RD[7:1] TRIMBGB[7:0] TRIMBGD[7:0] STEMP[10:8]=RMT_RD[10:8] STEMP[7:0] (additional trim fuses for 71M6113 and 71M6203 only) 010 00X STEMP[10:0] 010 01X VSENSE[7:0] 010 10X VERSION[7:0] (sensed 71M6xx3 temperature) (sensed 71M6xx3 supply voltage) (chip version) (RMT_RD[15:11] are sign extended) All zeros VSENSE[7:0] VERSION[7:0] All zeros Notes: 1. TRIMT[7:0] is the VREF trim value for all 71M6xx3 devices. Note that the TRIMT[7:0] 8-bit value is formed by RMT_RD[8] and RMT_RD[7:1]. See the 71M6xxx Data Sheet for the equations related to TRIMT[7:0] and the corresponding temperature coefficient. 2. TRIMBGB[7:0] and TRIMBGD[7:0] are trim values used for characterizing the 71M6113 (0.5%) and 71M6203 (0.1%) over temperature. See the 71M6xxx Data sheet for the equations related to TRIMBGB[7:0] and TRIMBGD[7:0] and the corresponding temperature coefficients. 3. See 2.5.6 71M6xx3 Temperature Sensor on page 56. 4. See 2.5.8 71M6xx3 VCC Monitor on page 57. With hardware and trim-related information on each connected 71M6xx3 Isolated Sensor available to the 71M6543, the MPU can implement temperature compensation of the energy measurement based on the individual temperature characteristics of the 71M6xx3 Isolated Sensors. See 4.5 Metrology Temperature Compensation for details. Table 6 shows all I/O RAM registers used for control of the external 71M6xx3 Isolated Sensors. See the 71M6xx3 Data Sheet for additional details. v1.2 (c) 2008-2011 Teridian Semiconductor Corporation 23 71M6543F/H Data Sheet 8 Table 6: I/O RAM Control Bits for Isolated Sensor Name Address RST WAKE Default Default R/W Description RCMD[4:0] SFR FC[4:0] 0 0 R/W PERR_RD PERR_WR SFR FC[6] SFR FC[5] 0 0 R/W CHOPR[1:0] 2709[7:6] 00 00 R/W TMUXR2[2:0] TMUXR4[2:0] TMUXR6[2:0] RMT_RD[15:8] RMT_RD[7:0] 270A[2:0] 270A[6:4] 2709[2:0] 2602[7:0] 2603[7:0] 000 000 000 000 000 000 R/W R/W R/W 0 0 R When the MPU writes a non-zero value to RCMD, the 71M6543 issues a command to the corresponding isolated sensor selected with RCMD[1:0]. When the command is complete, the 71M6543 clears RCMD[4:2]. The command code itself is in RCMD[4:2]. The 71M6543 sets these bits to indicate that a parity error on the isolated sensor has been detected. Once set, the bits are remembered until they are cleared by the MPU. The CHOP settings for the isolated sensors. 00 - Auto chop. Change every multiplexer frame. 01 - Positive 10 - Negative 11 - Same as 00 The TMUX bits for control of the isolated sensor. The TMUX bits for control of the isolated sensor. The TMUX bits for control of the isolated sensor. The read buffer for 71M6xx3 read operations. Controls how the 71M6543 drives the 71M6xx3 power pulse. When set, the power pulse is driven RFLY_DIS 210C[3] 0 0 R/W high and low. When cleared, it is driven high followed by an open circuit fly-back interval. Enables the isolated remote sensor interface and RMT2_E 2709[3] 0 0 R/W re-configures pins IADC2-IADC3 as a balanced pair digital remote interface. Enables the isolated remote sensor interface and RMT4_E 2709[4] 0 0 R/W re-configures pins IADC4-IADC5 as a balanced pair digital remote interface. Enables the isolated remote sensor interface and RMT6_E 2709[5] 0 0 R/W re-configures pins IADC6-IADC7 as a balanced pair digital remote interface. Refer to Table 71 starting on page 104 for more complete details about these I/O RAM locations. 24 (c) 2008-2010 MAXIM/TERIDIAN Semiconductor Corporation v1.2 71M6543F/H and 71M6543G/GH Data Sheet 2.3 Digital Computation Engine (CE) The CE, a dedicated 32-bit signal processor, performs the precision computations necessary to accurately measure energy. The CE calculations and processes include: * * * * * * * * Multiplication of each current sample with its associated voltage sample to obtain the energy per sample (when multiplied by the constant sample time). Frequency-insensitive delay cancellation on all channels (to compensate for the delay between samples caused by the multiplexing scheme). 90 phase shifter (for VAR calculations). Pulse generation. Monitoring of the input signal frequency (for frequency and phase information). Monitoring of the input signal amplitude (for sag detection). Scaling of the processed samples based on calibration coefficients. Scaling of samples based on temperature compensation information. 2.3.1 CE Program Memory The CE program resides in flash memory. Common access to flash memory by the CE and MPU is controlled by a memory share circuit. Each CE instruction word is two bytes long. Allocated flash space for the CE program cannot exceed 4096 16-bit words (8 KB). The CE program counter begins a pass through the CE code each time multiplexer state 0 begins. The code pass ends when a HALT instruction is executed. For proper operation, the code pass must be completed before the multiplexer cycle ends. The CE program must begin on a 1 KB boundary of the flash address. The I/O RAM control field CE_LCTN[6/5:0] (I/O RAM 0x2109[6/5:0]) on the 71M6543F/H and CE_LCTN[6:0] (I/O RAM 0x2109[6:0]) on the 71M6543G/GH defines which 1 KB boundary contains the CE code. Thus, the first CE instruction is located at 1024*CE_LCTN[5:0] on the 71M6543F/H and 1024*CE_LCTN[6:0] on the 71M6543G/GH. 2.3.2 CE Data Memory The CE and MPU share data memory (RAM). Common access to XRAM by the CE and MPU is controlled by a memory share circuit. The CE can access up to 3 KB of the 5 KB data RAM (XRAM), i.e. from RAM address 0x0000 to 0x0C00. The XRAM can be accessed by the FIR filter block, the RTM circuit, the CE, and the MPU. Assigned time slots are reserved for FIR and MPU, respectively, to prevent bus contention for XRAM data access by the CE. The MPU reads and writes the XRAM shared between the CE and MPU as the primary means of data communication between the two processors. The CE is aided by support hardware to facilitate implementation of equations, pulse counters, and accumulators. This hardware is controlled through I/O RAM field EQU[2:0] (equation assist, I/O RAM 0x2106[7:5]), bit DIO_PV (I/O RAM 0x2457[6]), bit DIO_PW (pulse count assist, I/O RAM 0x2457[7]), and SUM_SAMPS[12:0] (accumulation assist, I/O RAM 0x2107[4:0] and 0x2108[7:0]). The integration time for each energy output, when using standard CE code, is SUM_SAMPS[12:0] /2184.53 (with MUX_DIV[3:0] = 7, I/O RAM 0x2100[7:4] ). CE hardware issues the XFER_BUSY interrupt when the accumulation is complete. 2.3.3 CE Communication with the MPU The CE outputs six signals to the MPU: CE_BUSY, XFER_BUSY, XPULSE, YPULSE, WPULSE and VPULSE. These are connected to the MPU interrupt service. CE_BUSY indicates that the CE is actively processing data. This signal occurs once every multiplexer frame. XFER_BUSY indicates that the CE is updating to the output region of the CE RAM, which occurs whenever an accumulation cycle has been completed. Both, CE_BUSY and XFER_BUSY are cleared when the CE executes a HALT instruction. XPULSE and YPULSE can be configured to interrupt the MPU and indicate sag failures, zero crossings of the mains voltage, or other significant events. Additionally, these signals can be connected directly to DIO pins to provide direct outputs from the CE. Interrupts associated with these signals always occur on the leading edge. v1.2 (c) 2008-2011 Teridian Semiconductor Corporation 25 71M6543F/H and 71M6543G/GH Data Sheet 2.3.4 Meter Equations The 71M6543 provides hardware assistance to the CE in order to support various meter equations. This assistance is controlled through I/O RAM field EQU[2:0] (equation assist, I/O RAM 0x2106[7:5]). The Compute Engine (CE) firmware configurations can implement the equations listed in Table 7. EQU[2:0] specifies the equation to be used based on the meter configuration and on the number of phases used for metering. Table 7: Inputs Selected in Multiplexer Cycles Wh and VARh formula Element 0 Element 1 Element 2 Recommended Multiplexer Sequence 2-element, 3-W, 3 Delta VA IA VB IB N/A IA VA IB VB 3 2-element, 4-W, 3 Delta VA(IA-IB)/2 VC IC N/A IA VA IB VB IC VC 4 2-element, 4-W, 3 Wye VA(IA-IB)/2 VB(IC-IB)/2 N/A IA VA IB VB IC VC EQU[2:0]* Description 2 5 VA IA VB IB VC IC IA VA IB VB IC VC (ID) 3-element, 4-W, 3 Wye Note: * Only EQU[2:0] = 5 is supported by the currently available CE code versions for the 71M6543. Contact your local Teridian representative for CE codes that support equations 2, 3 and 4. 2.3.5 Real-Time Monitor (RTM) The CE contains a Real-Time Monitor (RTM), which can be programmed to monitor four selectable XRAM locations at full sample rate. The data from the four monitored locations are serially output to the TMUXOUT pin via the digital output multiplexer at the beginning of each CE code pass. The RTM can be enabled and disabled with RTM_E (I/O RAM 0x2106[1]). The RTM output clock is available on the TMUX2OUT pin. Each RTM word is clocked out in 35 cycles and contains a leading flag bit. See Figure 8 for the RTM output format. RTM is low when not in use. CK32 MUX_SYNC MUX_STATE S CKTEST 31 0 FLAG 1 30 31 0 FLAG 1 30 31 SIG N 30 LSB 1 SIG N 0 FLAG LSB 31 SIG N 30 LSB RTM DATA0 (32 bits) RTM DATA1 (32 bits) RTM DATA2 (32 bits) RTM DATA3 (32 bits) 1 LSB 0 FLAG SIG N RTM Figure 8: RTM Timing 2.3.6 Pulse Generators The 71M6543 provides four pulse generators, VPULSE, WPULSE, XPULSE and YPULSE. The XPULSE and YPULSE generators are used by standard CE code to output CE status indicators, for example the status of the sag detection, to DIO pins. All pulses can be configured to generate interrupts to the MPU. The polarity of the pulses may be inverted with PLS_INV (I/O RAM 0x210C[0]). When this bit is set, the pulses are active high, rather than the more usual active low. PLS_INV inverts all the pulse outputs. The function of each pulse generator is determined by the CE code and the MPU code must configure the corresponding pulse outputs in agreement with the CE code. For example, standard CE code produces a mains zero-crossing pulse on XPULSE and a SAG pulse on YPULSE. 26 (c) 2008-2011 Teridian Semiconductor Corporation v1.2 71M6543F/H and 71M6543G/GH Data Sheet A common use of the zero-crossing pulses is to generate interrupts in order to drive real-time clock software in places where the mains frequency is sufficiently accurate to do so and also to adjust for crystal aging. A common use for the SAG pulse is to generate an interrupt that alerts the MPU when mains power is about to fail, so that the MPU code can store accumulated energy and other data to EEPROM before the V3P3SYS supply voltage actually drops. 2.3.6.1 XPULSE and YPULSE Pulses generated by the CE may be exported to the XPULSE and YPULSE pulse output pins. Pins SEGDIO6 and SEGDIO7 are used for these pulses, respectively. Generally, the XPULSE and YPULSE outputs can be updated once on each pass of the CE code. See 5.4 CE Interface Description on page 120 for details. 2.3.6.2 VPULSE and WPULSE Referring to Figure 9, during each CE code pass the hardware stores exported WPULSE and VPULSE sign bits in an 8-bit FIFO and outputs them at a specified interval. This permits the CE code to calculate the VPULSE and WPULSE outputs at the beginning of its code pass and to rely on hardware to spread them over the multiplexer frame. As seen in Figure 9, the FIFO is reset at the beginning of each multiplexer frame. As also seen in Figure 9, the I/O RAM register PLS_INTERVAL[7:0] (I/O RAM 0x210B[7:0]) controls the delay to the first pulse update and the interval between subsequent updates. The LSB of the PLS_INTERVAL[7:0] register is equivalent to 4 CK_FIR cycles (CK_FIR is typically 4.9152MHz if PLL_FAST=1 and ADC_DIV=0, but other CK_FIR frequencies are possible; see the ADC_DIV definition in Table 71.) If PLS_INTERVAL[7:0]=0, the FIFO is deactivated and the pulse outputs are updated immediately. The MUX frame duration in units of CK_FIR clock cycles is given by: If PLL_FAST=1: MUX frame duration in CK_FIR cycles = [1 + (FIR_LEN+1) * (ADC_DIV+1) * (MUX_DIV)] * [150 / (ADC_DIV+1)] If PLL_FAST=0: MUX frame duration in CK_FIR cycles = [3 + 3*(FIR_LEN+1) * (ADC_DIV+1) * (MUX_DIV)] * [48 / (ADC_DIV+1)] PLS_INTERVAL[7:0] in units of CK_FIR clock cycles is calculated by: PLS_INTERVAL[7:0] = floor ( Mux frame duration in CK_FIR cycles / CE pulse updates per Mux frame / 4 ) Since the FIFO resets at the beginning of each multiplexer frame, the user must specify PLS_INTERVAL[7:0] so that all of the possible pulse updates occurring in one CE execution are output before the multiplexer frame completes. For instance, the 71M6543 CE code outputs six updates per multiplexer interval, and if the multiplexer interval is 1950 CK_FIR clock cycles long, the ideal value for the interval is 1950/6/4 = 81.25. However, if PLS_INTERVAL[7:0] = 82, the sixth output occurs too late and would be lost. In this case, the proper value for PLS_INTERVAL[7:0] is 81 (i.e., round down the result). Since one LSB of PLS_INTERVAL[7:0] is equal to 4 CK_FIR clock cycles, the pulse time interval TI in units of CK_FIR clock cycles is: TI = 4*PLS_INTERVAL[7:0] If the FIFO is enabled (i.e., PLS_INTERVAL[7:0] 0), hardware also provides a maximum pulse width feature in control register PLS_MAXWIDTH[7:0] (I/O RAM 0x210A) . By default, WPULSE and VPULSE are negative pulses (i.e., low level pulses, designed to sink current through an LED). PLS_MAXWIDTH[7:0] determines the maximum negative pulse width TMAX in units of CK_FIR clock cycles based on the pulse interval TI according to the formula: TMAX = (2 * PLS_MAXWIDTH[7:0] + 1) * TI If PLS_MAXWIDTH = 255 or PLS_INTERVAL=0, no pulse width checking is performed, and the pulses default to 50% duty cycle. The polarity of the pulses may be inverted with the control bit PLS_INV (I/O RAM 0x210C[0]). When PLS_INV is set, the pulses are active high. The default value for PLS_INV is zero, which selects active low pulses. v1.2 (c) 2008-2011 Teridian Semiconductor Corporation 27 71M6543F/H and 71M6543G/GH Data Sheet The WPULSE and VPULSE pulse generator outputs are available on pins SEGDIO0/WPULSE and SEGDIO1/VPULSE, respectively (pins 45 and 44). The pulses can also be output on OPT_TX pin 53 (see OPT_TXE[1:0], I/O RAM 0x2456[3:2] for details). ADC MUX Frame MUX_DIV Conversions (MUX_DIV=4 is shown) Settle CK32 150 MUX_SYNC CE CODE S0 S1 S2 S3 S4 S5 W_FIFO RST WPULSE S0 S1 S0 4*PLS_INTERVAL 4*PLS_INTERVAL S2 S1 4*PLS_INTERVAL S3 S3 S2 4*PLS_INTERVAL S5 S4 4*PLS_INTERVAL S4 S5 4*PLS_INTERVAL 1. This example shows how the FIFO distributes 6 pulse generator updates over one MUX frame. 2. If WPULSE is low longer than (2*PLS_MAXWIDTH+1) updates, WPULSE will be raised until the next low-going pulse begins. 3. Only the WPULSE circuit is shown. The VARPULSE circuit behaves identically. 4. All dimensions are in CK_FIR cycles (4.92MHz). 5. If PLS_INTERVAL=0, FIFO does not perform delay. Figure 9. Pulse Generator FIFO Timing 2.3.7 CE Functional Overview The ADC processes one sample per channel per multiplexer cycle. Figure 10 shows the timing of the samples taken during one multiplexer cycle with MUX_DIV[3:0] = 7 (I/O RAM 0x2100[7:4]). The number of samples processed during one accumulation cycle is controlled by the I/O RAM register SUM_SAMPS[12:0] (0x2107[4:0] and 0x2108[7:0]). The integration time for each energy output is: SUM_SAMPS[12:0] / 2184.53, where 2184.53 is the sample rate in Hz For example, SUM_SAMPS[12:0] = 2184 establishes 2184 multiplexer cycles per accumulation cycle or 2184/2184.53 = 0.9998 seconds. After an accumulation cycle is completed, the XFER_BUSY interrupt signals to the MPU that accumulated data are available. The slight difference between the nominal length of the accumulation interval (1000 ms) and the actual length of 999.8 ms (0.025%) is accounted for in the CE code and is of no practical consequence. 28 (c) 2008-2011 Teridian Semiconductor Corporation v1.2 71M6543F/H and 71M6543G/GH Data Sheet VB IB IC VA VC ID IA 30.5 s 61.04 s 61.04 s 61.04 s 61.04 s Multiplexer Frame (15 x 30.518 s = 457.8 s) MUX_DIV = 7 Conversions Settle CK32 (32768 Hz) MUX STATE S 0 1 2 3 4 5 6 S Figure 10: Samples from Multiplexer Cycle (Frame) The end of each multiplexer cycle is signaled to the MPU by the CE_BUSY interrupt. At the end of each multiplexer cycle, status information, such as sag data and the digitized input signal, is available to the MPU. 833ms 20ms XFER_BUSY Interrupt to MPU Figure 11: Accumulation Interval Figure 11 shows the accumulation interval resulting from SUM_SAMPS[12:0] = 1819 (I/O RAM 0x2107[4:0] and 0x2108[7:0]), consisting of 1819 samples of 457.8 s each, followed by the XFER_BUSY interrupt. The sampling in this example is applied to a 50 Hz signal. There is no correlation between the line signal frequency and the choice of SUM_SAMPS[12:0]. Furthermore, sampling does not have to start when the line voltage crosses the zero line, and the length of the accumulation interval need not be an integer multiple of the signal cycles. v1.2 (c) 2008-2011 Teridian Semiconductor Corporation 29 71M6543F/H and 71M6543G/GH Data Sheet 2.4 80515 MPU Core The 71M6543 include an 80515 MPU (8-bit, 8051-compatible) that processes most instructions in one clock cycle. Using a 4.9 MHz clock results in a processing throughput of 4.9 MIPS. The 80515 architecture eliminates redundant bus states and implements parallel execution of fetch and execution phases. Normally, a machine cycle is aligned with a memory fetch, therefore, most of the 1-byte instructions are performed in a single machine cycle (MPU clock cycle). This leads to an 8x average performance improvement (in terms of MIPS) over the Intel 8051 device running at the same clock frequency. Table 8 shows the CKMPU frequency as a function of the MCK clock (19.6608 MHz) divided by the MPU clock divider MPU_DIV[2:0] (I/O RAM 0x2200[2:0]). Actual processor clocking speed can be adjusted to the total processing demand of the application (metering calculations, AMR management, memory management, LCD driver management and I/O management) using MPU_DIV[2:0], as shown in Table 8. Table 8: CKMPU Clock Frequencies MPU_DIV [2:0] CKMPU Frequency 000 001 010 011 100 101 110 111 4.9152 MHz 2.4576 MHz 1.2288 MHz 614.4 kHz 307.2 kHz Typical measurement and metering functions based on the results provided by the internal 32-bit compute engine (CE) are available for the MPU as part of the Teridian demonstration code, which is provided to help reduce the product design cycle. 2.4.1 Memory Organization and Addressing The 80515 MPU core incorporates the Harvard architecture with separate code and data spaces. Memory organization in the 80515 is similar to that of the industry standard 8051. There are three memory areas: Program memory (Flash, shared by MPU and CE), external RAM (Data RAM, shared by the CE and MPU, Configuration or I/O RAM), and internal data memory (Internal RAM). Table 9 shows the memory map. Program Memory The 80515 can address up to 64 KB of program memory space (0x0000 to 0xFFFF). Program memory is read when the MPU fetches instructions or performs a MOVC operation. After reset, the MPU starts program execution from program memory location 0x0000. The lower part of the program memory includes reset and interrupt vectors. The interrupt vectors are spaced at 8-byte intervals, starting from 0x0003. MPU External Data Memory (XRAM) Both internal and external memory is physically located on the 71M6543 device. The external memory referred to in this documentation is only external to the 80515 MPU core. 5 KB of RAM starting at address 0x0000 is shared by the CE and MPU. The CE normally uses the first 1 KB, leaving 4 KB for the MPU. Different versions of the CE code use varying amounts. Consult the documentation for the specific code version being used for the exact limit. If the MPU overwrites the CE's working RAM, the CE's output may be corrupted. If the CE is disabled, the first 0x40 bytes of RAM are still unusable while MUX_DIV[3:0] 0 (I/O RAM 0x2100[7:3]), because the 71M6543 ADC writes to these locations. Writing MUX_DIV[3:0] = 0 disables the ADC output, preventing the CE from writing the first 0x40 bytes of RAM. In addition, MUXn_SEL[3:0] values must be written only after writing MUX_DIV[3:0]. 30 (c) 2008-2011 Teridian Semiconductor Corporation v1.2 71M6543F/H and 71M6543G/GH Data Sheet The 80515 writes into external data memory when the MPU executes a MOVX @Ri,A or MOVX @DPTR,A instruction. The MPU reads external data memory by executing a MOVX A,@Ri or MOVX A,@DPTR instruction (PDATA, SFR 0xBF, provides the upper 8 bytes for the MOVX A,@Ri instruction). Internal and External Memory Map Table 9 shows the address, type, use and size of the various memory components. Table 9: Memory Map Address (hex) 0000-FFFF Memory Technology Flash Memory 0000-13FF Static RAM 2000-27FF Static RAM 2800-287F Static RAM 0000-00FF Static RAM Memory Type Name Typical Usage MPU Program and non-volatile data Non-volatile Program memory CE program (on 1 KB boundary) External RAM Shared by CE and Volatile (XRAM) MPU Configuration Volatile Hardware control RAM (I/O RAM) Non-volatile Configuration Battery-buffered (battery) RAM (I/O RAM) memory Volatile Internal RAM Part of 80515 Core Memory Size (bytes) 64 KB 3 KB max. 5 KB 2 KB 128 256 MOVX Addressing There are two types of instructions differing in whether they provide an 8-bit or 16-bit indirect address to the external data RAM. In the first type, MOVX A,@Ri, the contents of R0 or R1 in the current register bank provide the eight lower-ordered bits of address. The eight high-ordered bits of the address are specified with the PDATA SFR. This method allows the user paged access (256 pages of 256 bytes each) to all ranges of the external data RAM. In the second type of MOVX instruction, MOVX A,@DPTR, the data pointer generates a 16-bit address. This form is faster and more efficient when accessing very large data arrays (up to 64 KB), since no additional instructions are needed to set up the eight high ordered bits of the address. It is possible to mix the two MOVX types. This provides the user with four separate data pointers, two with direct access and two with paged access, to the entire 64 KB of external memory range. Dual Data Pointer The Dual Data Pointer accelerates the block moves of data. The standard DPTR is a 16-bit register that is used to address external memory or peripherals. In the 80515 core, the standard data pointer is called DPTR, the second data pointer is called DPTR1. The data pointer select bit, located in the LSB of the DPS register (DPS[0], SFR 0x92), chooses the active pointer. DPTR is selected when DPS[0] = 0 and DPTR1 is selected when DPS[0] = 1. The user switches between pointers by toggling the LSB of the DPS register. The values in the data pointers are not affected by the LSB of the DPS register. All DPTR related instructions use the currently selected DPTR for any activity. The second data pointer may not be supported by certain compilers. DPTR1 is useful for copy routines, where it can make the inner loop of the routine two instructions faster compared to the reloading of DPTR from registers. Any interrupt routine using DPTR1 must save and restore DPS, DPTR and DPTR1, which increases stack usage and slows down interrupt latency. By selecting the Evatronics R80515 core in the Keil compiler project settings and by using the compiler directive "MODC2", dual data pointers are enabled in certain library routines. v1.2 (c) 2008-2011 Teridian Semiconductor Corporation 31 71M6543F/H and 71M6543G/GH Data Sheet An alternative data pointer is available in the form of the PDATA register (SFR 0xBF), sometimes referred to as USR2). It defines the high byte of a 16-bit address when reading or writing XDATA with the instruction MOVX A,@Ri or MOVX @Ri,A. Internal Data Memory Map and Access The Internal data memory provides 256 bytes (0x00 to 0xFF) of data memory. The internal data memory address is always 1 byte wide. Table 10 shows the internal data memory map. The Special Function Registers (SFR) occupy the upper 128 bytes. The SFR area of internal data memory is available only by direct addressing. Indirect addressing of this area accesses the upper 128 bytes of Internal RAM. The lower 128 bytes contain working registers and bit addressable memory. The lower 32 bytes form four banks of eight registers (R0-R7). Two bits on the program memory status word (PSW, SFR 0xD0 ) select which bank is in use. The next 16 bytes form a block of bit addressable memory space at addresses 0x00-0x7F. All of the bytes in the lower 128 bytes are accessible through direct or indirect addressing. Table 10: Internal Data Memory Map Address Range 2.4.2 Direct Addressing Indirect Addressing Special Function Registers (SFRs) RAM 0x80 0xFF 0x30 0x7F Byte addressable area 0x20 0x00 0x2F 0x1F Bit addressable area Register banks R0...R7 Special Function Registers (SFRs) A map of the Special Function Registers is shown in Table 11. Only a few addresses in the SFR memory space are occupied, the others are not implemented. A read access to unimplemented addresses returns undefined data, while a write access has no effect. SFRs specific to the 71M6543 are shown in bold print on a gray field. The registers at 0x80, 0x88, 0x90, etc., are bit addressable, all others are byte addressable. Table 11: Special Function Register Map Bit Hex/ Addressable Bin X000 X001 F8 INTBITS VSTAT F0 B E8 IFLAGS E0 A D8 WDCON D0 PSW C8 T2CON C0 IRCON B8 IEN1 IP1 B0 P3 A8 IEN0 IP0 A0 P2 DIR2 98 S0CON S0BUF 90 P1 DIR1 88 TCON TMOD 80 P0 SP 32 Byte Addressable X010 X011 S0RELH S1RELH FLSHCTL S0RELL DIR0 IEN2 S1CON DPS TL0 TL1 DPL DPH X100 X101 RCMD SPI_CMD S1BUF ERASE TH0 DPL1 X110 X111 FL_BANK PDATA PGADR S1RELL EEDATA EECTRL TH1 DPH1 CKCON (c) 2008-2011 Teridian Semiconductor Corporation PCON Bin/ Hex FF F7 EF E7 DF D7 CF C7 BF B7 AF A7 9F 97 8F 87 v1.2 71M6543F/H and 71M6543G/GH Data Sheet 2.4.3 Generic 80515 Special Function Registers Table 12 shows the location, description and reset or power-up value of the generic 80515 SFRs. Additional descriptions of the registers can be found at the page numbers listed in the table. Table 12: Generic 80515 SFRs - Location and Reset Values Name P0 SP DPL DPH DPL1 DPH1 PCON TCON TMOD TL0 TL1 TH0 TH1 CKCON P1 DPS S0CON S0BUF IEN2 S1CON S1BUF S1RELL P2 IEN0 IP0 S0RELL P3 IEN1 IP1 S0RELH S1RELH PDATA IRCON T2CON PSW WDCON A B v1.2 Address (Hex) 0x80 0x81 0x82 0x83 0x84 0x85 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x90 0x92 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0xA0 0xA8 0xA9 0xAA 0xB0 0xB8 0xB9 0xBA 0xBB 0xBF 0xC0 0xC8 0xD0 0xD8 0xE0 0xF0 Reset value Description (Hex) 0xFF Port 0 0x07 Stack Pointer 0x00 Data Pointer Low 0 0x00 Data Pointer High 0 0x00 Data Pointer Low 1 0x00 Data Pointer High 1 0x00 Power Reduction Modes, UART Speed Control 0x00 Timer/Counter Control 0x00 Timer Mode Control 0x00 Timer 0, low byte 0x00 Timer 1, high byte 0x00 Timer 0, low byte 0x00 Timer 1, high byte 0x01 Clock Control (Stretch=1) 0xFF Port 1 0x00 Data Pointer select Register 0x00 Serial Port 0, Control Register 0x00 Serial Port 0, Data Buffer 0x00 Interrupt Enable Register 2 0x00 Serial Port 1, Control Register 0x00 Serial Port 1, Data Buffer 0x00 Serial Port 1, Reload Register, low byte 0xFF Port 2 0x00 Interrupt Enable Register 0 0x00 Interrupt Priority Register 0 0xD9 Serial Port 0, Reload Register, low byte 0xFF Port 3 0x00 Interrupt Enable Register 1 0x00 Interrupt Priority Register 1 0x03 Serial Port 0, Reload Register, high byte 0x03 Serial Port 1, Reload Register, high byte High address byte for MOVX@Ri - also called USR2 0x00 0x00 Interrupt Request Control Register 0x00 Polarity for INT2 and INT3 0x00 Program Status Word 0x00 Baud Rate Control Register (only WDCON[7] bit used) 0x00 Accumulator 0x00 B Register (c) 2008-2011 Teridian Semiconductor Corporation Page(s) 35 34 34 34 34 34 35, 38 41 39 39 39 39 39 35 35 31 37 36 41 38 36 36 35 41 43 36 35 41 43 36 36 31 42 42 34 36 34 34 33 71M6543F/H and 71M6543G/GH Data Sheet Accumulator (ACC, A, SFR 0x E0): ACC is the accumulator register. Most instructions use the accumulator to hold the operand. The mnemonics for accumulator-specific instructions refer to accumulator as A, not ACC. B Register (SFR 0xF0): The B register is used during multiply and divide instructions. It can also be used as a scratch-pad register to hold temporary data. Program Status Word (PSW, SFR 0xD0): This register contains various flags and control bits for the selection of the register banks (see Table 13). Table 13: PSW Bit Functions (SFR 0xD0) PSW Bit Symbol 7 6 5 CV AC F0 Carry flag. Auxiliary Carry flag for BCD operations. General purpose Flag 0 available for user. F0 is not to be confused with the F0 flag in the CESTATUS register. 4 RS1 Register bank select control bits. The contents of RS1 and RS0 select the working register bank: 3 RS0 2 1 0 OV - P Function Bank selected Location RS1/RS0 00 Bank 0 0x00 - 0x07 01 Bank 1 0x08 - 0x0F 10 Bank 2 0x10 - 0x17 11 Bank 3 0x18 - 0x1F Overflow flag. User defined flag. Parity flag, affected by hardware to indicate odd or even number of one bits in the Accumulator, i.e. even parity. Stack Pointer (SP, SFR 0x81): The stack pointer is a 1-byte register initialized to 0x07 after reset. This register is incremented before PUSH and CALL instructions, causing the stack to begin at location 0x08. Data Pointer: The data pointers (DPTR and DPRT1) are 2 bytes wide. The lower part is DPL (SFR 0x82) and DPL1 (SFR 0x84), respectively. The highest is DPH (SFR 0x83) and DPH1 (SFR 0x85), respectively. The data pointers can be loaded as two registers (e.g. MOV DPL,#data8). They are generally used to access external code or data space (e.g. MOVC A,@A+DPTR or MOVX A,@DPTR respectively). Program Counter: The program counter (PC) is 2 bytes wide and initialized to 0x0000 after reset. This register is incremented when fetching operation code or when operating on data from program memory. Port Registers: SEGDIO0 through SEGDIO15 are controlled by Special Function Registers P0, P1, P2, and P3 as shown in Table 14. Above SEGDIO15, the LCD_SEGDIOn[ ] registers in I/O RAM are used. Since the direction bits are contained in the upper nibble of each SFR Pn register and the DIO bits are contained in the lower nibble, it is possible to configure the direction of a given DIO pin and set its output value with a single write operation, thus facilitating the implementation of bit-banged interfaces. Writing a 1 to a DIO_DIR bit configures the corresponding DIO as an output, while writing a 0 configures it as an input. Writing a 1 to a DIO bit causes the corresponding pin to be at high level (V3P3), while writing a 0 causes the corresponding pin to be held at a low level (GND). See 2.5.10 Digital I/O for additional details. 34 (c) 2008-2011 Teridian Semiconductor Corporation v1.2 71M6543F/H and 71M6543G/GH Data Sheet Table 14: Port Registers (SEGDIO0-15) SFR Name P0 P1 P2 P3 SFR Address D7 D6 D5 D4 D3 DIO_DIR[3:0] DIO_DIR[7:4] DIO_DIR[11:8] DIO_DIR[15:12] 80 90 A0 B0 D2 D1 D0 DIO[3:0] DIO[7:4] DIO[11:8] DIO[15:11] All DIO ports on the chip are bi-directional. Each of them consists of a latch (SFR P0 to P3), an output driver and an input buffer, therefore the MPU can output or read data through any of these ports. Even if a DIO pin is configured as an output, the state of the pin can still be read by the MPU, for example when counting pulses issued via DIO pins that are under CE control. At power-up SEGDIO0-15 are configured as inputs. It is necessary to write PORT_E = 1 (I/O RAM 0x270C[5]) to enable SEGDIO0-DIO15. The default PORT_E = 0 blocks any momentary output transient pulses that would otherwise occur when SEGDIO0-15 are reset on power-up. Clock Stretching (CKCON[2:0], SFR 0x8E) The CKCON[2:0] field defines the stretch memory cycles that are used for MOVX instructions when accessing external peripherals. The practical value of this register for the 71M6543 is to guarantee access to XRAM between CE, MPU, and SPI. The default setting of CKCON[2:0] (001) should be changed to 000 for best performance. Table 15 shows how the signals of the External Memory Interface change when stretch values are set from 0 to 7. The widths of the signals are counted in MPU clock cycles. The post-reset state of the CKCON[2:0] field (001), which is shown in bold in the table, performs the MOVX instructions with a stretch value equal to 1. Table 15: Stretch Memory Cycle Width 2.4.4 Read Signal Width Write Signal Width CKCON[2:0] Stretch Value memaddr memrd memaddr memwr 000 001 010 011 100 101 110 111 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 2 3 4 5 6 7 8 9 1 1 2 3 4 5 6 7 Instruction Set All instructions of the generic 8051 microcontroller are supported. A complete list of the instruction set and of the associated op-codes is contained in the 71M654x Software User's Guide (SUG). 2.4.5 80515 Power Reduction Modes The 80515 core provides two power reduction modes: Idle Mode and Power-Down Mode. These power saving modes are invoked by setting the appropriate control bit in the PCON SFR register (SFR 0x87). Idle Mode halts the MPU while allowing the interrupt, timer, and serial port functions to continue to operate. Once Idle Mode has been entered, an interrupt event automatically ends Idle Mode. After the interrupt has been serviced, program execution continues with the instruction immediately following the instruction that set the Idle Mode bit. To enter Idle Mode, the firmware must set the IDL bit (bit 0) in the PCON SFR register (SFR 0x87). v1.2 (c) 2008-2011 Teridian Semiconductor Corporation 35 71M6543F/H and 71M6543G/GH Data Sheet The MPU core power consumption can be significantly reduced by the proper use of Idle Mode. The amount of power saved depends on the percentage of time spent in Idle Mode. Since some interrupts may occur frequently, thus ending Idle Mode, one method to maximize power savings using Idle Mode, is to employ a software loop in the main background routine at a point where the MPU background processing may be permitted to idle. This loop invokes Idle Mode while testing a bit to exit the loop. Frequently occurring interrupts end Idle Mode, but Idle Mode is immediately re-entered when control is returned to the idle loop. To exit the idle loop, an interrupt must occur, and the associated interrupt service routine must set the bit that terminates the idle loop execution. Power-Down Mode halts the MPU and its peripherals. Power-Down Mode is ended by either a hardware reset or an external interrupt event. To enter Power-Down Mode, the firmware must set the PD bit (bit 1) in the PCON SFR register (SFR 0x87). Bit 7 SMOD Table 16. 80515 PCON SFR Register (SFR 0x87) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 - - - - - PD Bit 0 IDL Notes: The SMOD bit is not related to power management. See 2.4.6 UARTs below for information on the SMOD bit. 2.4.6 UARTs The 71M6543 include a UART (UART0) that can be programmed to communicate with a variety of AMR modules and other external devices. A second UART (UART1) is connected to the optical port, as described in the 2.5.9 UART and Optical Interface on page 57. The UARTs are dedicated 2-wire serial interfaces, which can communicate with an external host processor at up to 38,400 bits/s (with MPU clock = 1.2288 MHz). The operation of the RX and TX UART0 pins is as follows: * * UART0 RX: Serial input data are applied at this pin. Conforming to RS-232 standard, the bytes are input LSB first. UART0 TX: This pin is used to output the serial data. The bytes are output LSB first. The 71M6543 has several UART-related registers for the control and buffering of serial data. A single SFR register serves as both the transmit buffer and receive buffer (S0BUF, SFR 0x99 for UART0 and S1BUF, SFR 0x9C for UART1). When written by the MPU, SxBUF acts as the transmit buffer, and when read by the MPU, it acts as the receive buffer. Writing data to the transmit buffer starts the transmission by the associated UART. Received data are available by reading from the receive buffer. Both UARTs can simultaneously transmit and receive data. WDCON[7] (SFR 0xD8) selects whether timer 1 or the internal baud rate generator is used. All UART transfers are programmable for parity enable, parity, 2 stop bits/1 stop bit and XON/XOFF options for variable communication baud rates from 300 to 38400 bps. Table 17 shows how the baud rates are calculated. Table 18 shows the selectable UART operation modes. Table 17: Baud Rate Generation Using Timer 1 (WDCON[7] = 0) Using Internal Baud Rate Generator (WDCON[7] = 1) UART0 2smod * f CKMPU/ (384 * (256-TH1)) 2smod * f CKMPU/(64 * (210-S0REL)) UART1 N/A fCKMPU/(32 * (210-S1REL)) S0REL and S1REL are 10-bit values derived by combining bits from the respective timer reload registers. (S0RELL, S0RELH, S1RELL, S1RELH are SFR 0xAA, SFR 0xBA, SFR 0x9D and SFR 0xBB, respectively) SMOD is the SMOD bit in the SFR PCON register (SFR 0x87). TH1 (SFR 0x8D) is the high byte of timer 1. 36 (c) 2008-2011 Teridian Semiconductor Corporation v1.2 71M6543F/H and 71M6543G/GH Data Sheet Table 18: UART Modes UART 0 Mode 0 Mode 1 Mode 2 Mode 3 UART 1 Start bit, 8 data bits, parity, stop bit, variable baud rate (internal baud rate generator) N/A Start bit, 8 data bits, stop bit, variable baud rate (internal baud rate generator or timer 1) Start bit, 8 data bits, parity, stop bit, fixed baud rate 1/32 or 1/64 of fCKMPU Start bit, 8 data bits, parity, stop bit, variable baud rate (internal baud rate generator or timer 1) Start bit, 8 data bits, stop bit, variable baud rate (internal baud rate generator) N/A N/A Parity of serial data is available through the P flag of the accumulator. 7-bit serial modes with parity, such as those used by the FLAG protocol, can be simulated by setting and reading bit 7 of 8-bit output data. 7-bit serial modes without parity can be simulated by setting bit 7 to a constant 1. 8-bit serial modes with parity can be simulated by setting and reading the 9th bit, using the control bits TB80 (S0CON[3]) and TB81 (S1CON[3]) in the S0CON (SFR 0x98) and S1CON (SFR 0x9B) registers for transmit and RB81 (S1CON[2]) for receive operations. All supported operation modes use oversampling for the incoming bit stream when receiving data. Each bit is sampled three times at the projected middle of the bit duration. This technique allows for deviations of the received baud rate from nominal of up to 3.5%. The feature of receiving 9 bits (Mode 3 for UART0, Mode A for UART1) can be used as handshake signals for inter-processor communication in multi-processor systems. In this case, the slave processors have bit SM20 (S0CON[5]) for UART0, or SM21 (S1CON[5] for UART1, set to 1. When the master processor outputs the slave's address, it sets the 9th bit to 1, causing a serial port receive interrupt in all the slaves. The slave processors compare the received byte with their address. If there is a match, the addressed slave clears SM20 or SM21 and receive the rest of the message. The rest of the slaves ignore the message. After addressing the slave, the host outputs the rest of the message with the 9th bit set to 0, so no additional serial port receive interrupts is generated. UART Control Registers: The functions of UART0 and UART1 depend on the setting of the Serial Port Control Registers S0CON and S1CON shown in Table 19 and Table 20, respectively, and the PCON register shown in Table 21. Since the TI0, RI0, TI1 and RI1 bits are in an SFR bit addressable byte, common practice would be to clear them with a bit operation, but this must be avoided. The hardware implements bit operations as a byte wide read-modify-write hardware macro. If an interrupt occurs after the read, but before the write, its flag is cleared unintentionally. The proper way to clear these flag bits is to write a byte mask consisting of all ones except for a zero in the location of the bit to be cleared. The flag bits are configured in hardware to ignore ones written to them. Table 19: The S0CON (UART0) Register (SFR 0x98) Bit S0CON[7] Symbol SM0 S0CON[6] SM1 S0CON[5] S0CON[4] SM20 REN0 v1.2 Function The SM0 and SM1 bits set the UART0 mode: Mode 0 1 2 3 Description N/A 8-bit UART 9-bit UART 9-bit UART SM0 0 0 1 1 SM1 0 1 0 1 Enables the inter-processor communication feature. If set, enables serial reception. Cleared by software to disable reception. (c) 2008-2011 Teridian Semiconductor Corporation 37 71M6543F/H and 71M6543G/GH Data Sheet Bit S0CON[3] Symbol TB80 S0CON[2] RB80 S0CON[1] TI0 S0CON[0] RI0 Function The 9th transmitted data bit in Modes 2 and 3. Set or cleared by the MPU, depending on the function it performs (parity check, multiprocessor communication etc.) th In Modes 2 and 3 it is the 9 data bit received. In Mode 1, SM20 is 0, RB80 is the stop bit. In mode 0, this bit is not used. Must be cleared by software. Transmit interrupt flag; set by hardware after completion of a serial transfer. Must be cleared by software (see Caution above). Receive interrupt flag; set by hardware after completion of a serial reception. Must be cleared by software (see Caution above). Table 20: The S1CON (UART1) Register (SFR 0x9B) Bit S1CON[7] Symbol Function Sets the baud rate and mode for UART1. SM SM 0 1 S1CON[5] S1CON[4] S1CON[3] SM21 REN1 TB81 S1CON[2] RB81 S1CON[1] TI1 S1CON[0] RI1 Mode A B Description 9-bit UART 8-bit UART Baud Rate variable variable Enables the inter-processor communication feature. If set, enables serial reception. Cleared by software to disable reception. The 9th transmitted data bit in Mode A. Set or cleared by the MPU, depending on the function it performs (parity check, multiprocessor communication etc.) In Modes A and B, it is the 9th data bit received. In Mode B, if SM21 is 0, RB81 is the stop bit. Must be cleared by software Transmit interrupt flag, set by hardware after completion of a serial transfer. Must be cleared by software (see Caution above). Receive interrupt flag, set by hardware after completion of a serial reception. Must be cleared by software (see Caution above). Table 21: PCON Register Bit Description (SFR 0x87) Bit PCON[7] 2.4.7 Symbol SMOD Function The SMOD bit doubles the baud rate when set Timers and Counters The 80515 has two 16-bit timer/counter registers: Timer 0 and Timer 1. These registers can be configured for counter or timer operations. In timer mode, the register is incremented every machine cycle, i.e. it counts up once for every 12 periods of the MPU clock. In counter mode, the register is incremented when the falling edge is observed at the corresponding input signal T0 or T1 (T0 and T1 are the timer gating inputs derived from certain DIO pins, see 2.5.10 Digital I/O). Since it takes 2 machine cycles to recognize a 1-to-0 event, the maximum input count rate is 1/2 of the clock frequency (CKMPU). There are no restrictions on the duty cycle, however to ensure proper recognition of the 0 or 1 state, an input should be stable for at least 1 machine cycle. Four operating modes can be selected for Timer 0 and Timer 1, as shown in Table 22 and Table 23. The TMOD (SFR 0x89) register, shown in Table 24, is used to select the appropriate mode. The timer/counter operation is controlled by the TCON (SFR 0x88) register, which is shown in Table 25. Bits TR1 (TCON[6]) and TR0 (TCON[4]) in the TCON register start their associated timers when set. 38 (c) 2008-2011 Teridian Semiconductor Corporation v1.2 71M6543F/H and 71M6543G/GH Data Sheet Table 22: Timers/Counters Mode Description M1 M0 Mode 0 0 Mode 0 0 1 1 0 Mode 1 Mode 2 1 1 Mode 3 Function 13-bit Counter/Timer mode with 5 lower bits in the TL0 or TL1 (SFR 0x8A or SFR 0x8B) register and the remaining 8 bits in the TH0 or TH1 (SFR 0x8C or SFR 0x8D) register (for Timer 0 and Timer 1, respectively). The 3 high order bits of TL0 and TL1 are held at zero. 16-bit Counter/Timer mode. 8-bit auto-reload Counter/Timer. The reload value is kept in TH0 or TH1, while TL0 or TL1 is incremented every machine cycle. When TL(x) overflows, a value from TH(x) is copied to TL(x) (where x is 0 for counter/timer 0 or 1 for counter/timer 1. If Timer 1 M1 and M0 bits are set to 1, Timer 1 stops. If Timer 0 M1 and M0 bits are set to 1, Timer 0 acts as two independent 8-bit Timer/Counters. In Mode 3, TL0 is affected by TR0 and gate control bits, and sets the TF0 flag on overflow, while TH0 is affected by the TR1 bit, and the TF1 flag is set on overflow. Table 23 specifies the combinations of operation modes allowed for Timer 0 and Timer 1. Table 23: Allowed Timer/Counter Mode Combinations Timer 1 Timer 0 - mode 0 Timer 0 - mode 1 Timer 0 - mode 2 Mode 0 Mode 1 Mode 2 Yes Yes Not allowed Yes Yes Not allowed Yes Yes Yes Table 24: TMOD Register Bit Description (SFR 0x89) Bit Symbol Timer/Counter 1: TMOD[7] Gate TMOD[6] C/T TMOD[5:4] M1:M0 Timer/Counter 0 TMOD[3] Gate TMOD[2] C/T TMOD[1:0] M1:M0 v1.2 Function If TMOD[7] is set, external input signal control is enabled for Counter 1. The TR0 bit in the TCON register (SFR 0x88) must also be set in order for Counter 0 to increment. With these settings, Counter 0 increments on every falling edge of the logic signal applied to one or more of the SEGDIO2-11 pins, as specified by the contents of the DIO_R2 through DIO_R11 registers. See 2.5.10 Digital I/O and LCD Segment Drivers and Table 47. Selects timer or counter operation. When set to 1, a counter operation is performed. When cleared to 0, the corresponding register functions as a timer. Selects the mode for Timer/Counter 0 as shown in Table 22. If TMOD[3] is set, external input signal control is enabled for Counter 0. The TR1 bit in the TCON register (SFR 0x88) must also be set in order for Counter 1 to increment. With these settings, Counter 1 increments on every falling edge of the logic signal applied to one or more of the SEGDIO2-11 pins, as specified by the contents of the DIO_R2 through DIO_R11 registers. See 2.5.10 Digital I/O and LCD Segment Drivers and Table 47. Selects timer or counter operation. When set to 1, a counter operation is performed. When cleared to 0, the corresponding register functions as a timer. Selects the mode for Timer/Counter 1, as shown in Table 22. (c) 2008-2011 Teridian Semiconductor Corporation 39 71M6543F/H and 71M6543G/GH Data Sheet Table 25: The TCON Register Bit Functions (SFR 0x88) Bit TCON[7] Symbol TF1 TCON[6] TCON[5] TR1 TF0 TCON[4] TCON[3] TR0 IE1 TCON[2] IT1 TCON[1] IE0 TCON[0] IT0 2.4.8 Function The Timer 1 overflow flag is set by hardware when Timer 1 overflows. This flag can be cleared by software and is automatically cleared when an interrupt is processed. Timer 1 run control bit. If cleared, Timer 1 stops. Timer 0 overflow flag set by hardware when Timer 0 overflows. This flag can be cleared by software and is automatically cleared when an interrupt is processed. Timer 0 Run control bit. If cleared, Timer 0 stops. Interrupt 1 edge flag is set by hardware when the falling edge on external pin int1 is observed. Cleared when an interrupt is processed. Interrupt 1 type control bit. Selects either the falling edge or low level on input pin to cause an interrupt. Interrupt 0 edge flag is set by hardware when the falling edge on external pin int0 is observed. Cleared when an interrupt is processed. Interrupt 0 type control bit. Selects either the falling edge or low level on input pin to cause interrupt. WD Timer (Software Watchdog Timer) There is no internal software watchdog timer. Use the standard hardware watchdog timer instead (see 2.5.13 Hardware Watchdog Timer). 2.4.9 Interrupts The 80515 provides 11 interrupt sources with four priority levels. Each source has its own interrupt request flag(s) located in a special function register (TCON, IRCON, and SCON). Each interrupt requested by the corresponding flag can be individually enabled or disabled by the enable bits in IEN0 (SFR 0xA8), IEN1 (SFR 0xB8), and IEN2 (SFR 0x9A). Figure 12 shows the device interrupt structure. Referring to Figure 12, interrupt sources can originate from within the 80515 MPU core (referred to as Internal Sources) or can originate from other parts of the 71M6543 SoC (referred to as External Sources). There are seven external interrupt sources, as seen in the leftmost part of Figure 12, and in Table 26 and Table 27 (i.e., EX0-EX6). Interrupt Overview When an interrupt occurs, the MPU vectors to the predetermined address as shown in Table 38. Once the interrupt service has begun, it can be interrupted only by a higher priority interrupt. The interrupt service is terminated by a return from instruction, RETI. When an RETI is performed, the processor returns to the instruction that would have been next when the interrupt occurred. When the interrupt condition occurs, the processor also indicates this by setting a flag bit. This bit is set regardless of whether the interrupt is enabled or disabled. Each interrupt flag is sampled once per machine cycle, then samples are polled by the hardware. If the sample indicates a pending interrupt when the interrupt is enabled, then the interrupt request flag is set. On the next instruction cycle, the interrupt is acknowledged by hardware forcing an LCALL to the appropriate vector address, if the following conditions are met: * * * No interrupt of equal or higher priority is already in progress. An instruction is currently being executed and is not completed. The instruction in progress is not RETI or any write access to the registers IEN0, IEN1, IEN2, IP0 or IP1. Special Function Registers for Interrupts The following SFR registers control the interrupt functions: * 40 The interrupt enable registers: IEN0, IEN1 and IEN2 (see Table 26, Table 27 and Table 28). (c) 2008-2011 Teridian Semiconductor Corporation v1.2 71M6543F/H and 71M6543G/GH Data Sheet * * * The Timer/Counter control registers, TCON and T2CON (see Table 29 and Table 30). The interrupt request register, IRCON (see Table 31). The interrupt priority registers: IP0 and IP1 (see Table 36). Table 26: The IEN0 Bit Functions (SFR 0xA8) Bit IEN0[7] IEN0[6] IEN0[5] IEN0[4] IEN0[3] IEN0[2] IEN0[1] IEN0[0] Symbol EAL WDT - ES0 ET1 EX1 ET0 EX0 Function EAL = 0 disables all interrupts. Not used for interrupt control. Not Used. ES0 = 0 disables serial channel 0 interrupt. ET1 = 0 disables timer 1 overflow interrupt. EX1 = 0 disables external interrupt 1. ET0 = 0 disables timer 0 overflow interrupt. EX0 = 0 disables external interrupt 0. Table 27: The IEN1 Bit Functions (SFR 0xB8) Bit Symbol IEN1[7] IEN1[6] IEN1[5] IEN1[4] IEN1[3] IEN1[2] IEN1[1] IEN1[0] - - EX6 EX5 EX4 EX3 EX2 - Function Not used. Not used. EX6 = 0 disables external interrupt 6. EX5 = 0 disables external interrupt 5. EX4 = 0 disables external interrupt 4. EX3 = 0 disables external interrupt 3. EX2 = 0 disables external interrupt 2. Not Used. Table 28: The IEN2 Bit Functions (SFR 0x9A) Bit IEN2[0] Symbol ES1 Function ES1 = 0 disables the serial channel 1 interrupt. Table 29: TCON Bit Functions (SFR 0x88) Bit Symbol TCON[7] TCON[6] TCON[5] TCON[4] TCON[3] TCON[2] TF1 TR1 TF0 TR0 IE1 IT1 TCON[1] TCON[0] IE0 IT0 v1.2 Function Timer 1 overflow flag. Not used for interrupt control. Timer 0 overflow flag. Not used for interrupt control. External interrupt 1 flag. External interrupt 1 type control bit: 0 = interrupt on low level. 1 = interrupt on falling edge. External interrupt 0 flag External interrupt 0 type control bit: 0 = interrupt on low level. 1 = interrupt on falling edge. (c) 2008-2011 Teridian Semiconductor Corporation 41 71M6543F/H and 71M6543G/GH Data Sheet Table 30: The T2CON Bit Functions (SFR 0xC8) Bit T2CON[7] T2CON[6] Symbol T2CON[5] I2FR T2CON[4:0] - - I3FR Function Not used. Polarity control for INT3: 0 = falling edge. 1 = rising edge. Polarity control for INT2: 0 = falling edge. 1 = rising edge. Not used. Table 31: The IRCON Bit Functions (SFR 0xC0) Bit IRCON[7] Symbol - Function Not used IRCON[6] - Not used IRCON[5] IRCON[4] IRCON[3] IRCON[2] IRCON[1] IRCON[0] IEX6 IEX5 IEX4 IEX3 IEX2 - 1 = External interrupt 6 occurred and has not been cleared. 1 = External interrupt 5 occurred and has not been cleared. 1 = External interrupt 4 occurred and has not been cleared. 1 = External interrupt 3 occurred and has not been cleared. 1 = External interrupt 2 occurred and has not been cleared. Not used. TF0 and TF1 (Timer 0 and Timer 1 overflow flags) is automatically cleared by hardware when the service routine is called (Signals T0ACK and T1ACK - port ISR - active high when the service routine is called). External MPU Interrupts The seven external interrupts are the interrupts external to the 80515 core, i.e. signals that originate in other parts of the 71M6543, for example the CE, DIO, RTC, or EEPROM interface. The external interrupts are connected as shown in Table 32. The polarity of interrupts 2 and 3 is programmable in the MPU via the I3FR and I2FR bits in T2CON (SFR 0xC8). Interrupts 2 and 3 should be programmed for falling sensitivity (I3FR = I2FR = 0). The generic 8051 MPU literature states that interrupts 4 through 6 are defined as rising-edge sensitive. Thus, the hardware signals attached to interrupts 5 and 6 are inverted to achieve the edge polarity shown in Table 32. Table 32: External MPU Interrupts External Interrupt 0 1 2 3 4 5 6 Connection Digital I/O Digital I/O CE_PULSE CE_BUSY VSTAT (VSTAT[2:0] changed) EEPROM busy (falling), SPI (rising) XFER_BUSY (falling), RTC_1SEC, RTC_1MIN, RTC_T Polarity see 2.5.10 see 2.5.10 rising falling rising falling Flag Reset automatic automatic automatic automatic automatic automatic manual External interrupt 0 and 1 can be mapped to pins on the device using DIO resource maps. See 2.5.10 Digital I/O for more information. 42 (c) 2008-2011 Teridian Semiconductor Corporation v1.2 71M6543F/H and 71M6543G/GH Data Sheet SFR enable bits must be set to permit any of these interrupts to occur. Likewise, each interrupt has its own flag bit, which is set by the interrupt hardware, and reset by the MPU interrupt handler. XFER_BUSY, RTC_1SEC, RTC_1MIN, RTC_T, SPI, PLLRISE and PLLFALL have their own enable and flag bits in addition to the interrupt 6, 4 and enable and flag bits (see Table 33: Interrupt Enable and Flag Bits). IE0 through IEX6 are cleared automatically when the hardware vectors to the interrupt handler. The other flags, IE_XFER through IE_VPULSE, are cleared by writing a zero to them. Since these bits are in an SFR bit addressable byte, common practice would be to clear them with a bit operation, but this must be avoided. The hardware implements bit operations as a byte wide read-modify-write hardware macro. If an interrupt occurs after the read, but before the write, its flag is cleared unintentionally. The proper way to clear the flag bits is to write a byte mask consisting of all ones except for a zero in the location of the bit to be cleared. The flag bits are configured in hardware to ignore ones written to them. Table 33: Interrupt Enable and Flag Bits Interrupt Enable Interrupt Flag Name Location Name Location EX0 EX1 EX2 EX3 EX4 EX5 EX6 EX_XFER EX_RTC1S EX_RTC1M EX_RTCT EX_SPI EX_EEX EX_XPULSE EX_YPULSE EX_WPULSE EX_VPULSE SFR A8[[0] SFR A8[2] SFR B8[1] SFR B8[2] SFR B8[3] SFR B8[4] SFR B8[5] 2700[0] 2700[1] 2700[2] 2700[4] 2701[7] 2700[7] 2700[6] 2700[5] 2701[6] 2701[5] IE0 IE1 IEX2 IEX3 IEX4 IEX5 IEX6 IE_XFER IE_RTC1S IE_RTC1M IE_RTCT IE_SPI IE_EEX IE_XPULSE IE_YPULSE IE_WPULSE IE_VPULSE SFR 88[1] SFR 88[3] SFR C0[1] SFR C0[2] SFR C0[3] SFR C0[4] SFR C0[5] SFR E8[0] SFR E8[1] SFR E8[2] SFR E8[4] SFR F8[7] SFR E8[7] SFR E8[6] SFR E8[5] SFR F8[4] SFR F8[3] Interrupt Description External interrupt 0 External interrupt 1 External interrupt 2 External interrupt 3 External interrupt 4 External interrupt 5 External interrupt 6 XFER_BUSY interrupt (int 6) RTC_1SEC interrupt (int 6) RTC_1MIN interrupt (int 6) RTC_T interrupt (int 6) SPI interrupt EEPROM interrupt CE_Xpulse interrupt (int 2) CE_Ypulse interrupt (int 2) CE_Wpulse interrupt (int 2) CE_Vpulse interrupt (int 2) Interrupt Priority Level Structure All interrupt sources are combined in groups, as shown in Table 34. Table 34: Interrupt Priority Level Groups Group 0 1 2 3 4 5 Group Members External interrupt 0 Timer 0 interrupt External interrupt 1 Timer 1 interrupt Serial channel 0 interrupt - Serial channel 1 interrupt - - - - - - External interrupt 2 External interrupt 3 External interrupt 4 External interrupt 5 External interrupt 6 Each group of interrupt sources can be programmed individually to one of four priority levels (as shown in Table 35) by setting or clearing one bit in the SFR interrupt priority register IP0 (SFR 0xA9) and one in v1.2 (c) 2008-2011 Teridian Semiconductor Corporation 43 71M6543F/H and 71M6543G/GH Data Sheet IP1(SFR 0xB9) (Table 36). If requests of the same priority level are received simultaneously, an internal polling sequence as shown in Table 37 determines which request is serviced first. Changing interrupt priorities while interrupts are enabled can easily cause software defects. It is best to set the interrupt priority registers only once during initialization before interrupts are enabled. Table 35: Interrupt Priority Levels IP1[x] IP0[x] 0 0 1 1 0 1 0 1 Priority Level Level 0 (lowest) Level 1 Level 2 Level 3 (highest) Table 36: Interrupt Priority Registers (IP0 and IP1) Register Address IP0 SFR 0xA9 Bit 7 (MSB) - IP1 SFR 0xB9 - 44 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 - IP0[5] IP0[4] IP0[3] IP0[2] IP0[1] Bit 0 (LSB) IP0[0] - IP1[5] IP1[4] IP1[3] IP1[2] IP1[1] IP1[0] (c) 2008-2011 Teridian Semiconductor Corporation v1.2 71M6543F/H and 71M6543G/GH Data Sheet External interrupt 0 Serial channel 1 interrupt Timer 0 interrupt External interrupt 2 External interrupt 1 External interrupt 3 Timer 1 interrupt External interrupt 4 Serial channel 0 interrupt External interrupt 5 External interrupt 6 Polling sequence Table 37: Interrupt Polling Sequence Interrupt Sources and Vectors Table 38 shows the interrupts with their associated flags and vector addresses. Table 38: Interrupt Vectors Interrupt Request Flag IE0 TF0 IE1 TF1 RI0/TI0 RI1/TI1 IEX2 IEX3 IEX4 IEX5 IEX6 v1.2 Description External interrupt 0 Timer 0 interrupt External interrupt 1 Timer 1 interrupt Serial channel 0 interrupt Serial channel 1 interrupt External interrupt 2 External interrupt 3 External interrupt 4 External interrupt 5 External interrupt 6 Interrupt Vector Address 0x0003 0x000B 0x0013 0x001B 0x0023 0x0083 0x004B 0x0053 0x005B 0x0063 0x006B (c) 2008-2011 Teridian Semiconductor Corporation 45 71M6543F/H and 71M6543G/GH Data Sheet 0 External Source Internal Source Individual Enable Bits Individual Flags DIO DIO status changed DIO_Rn TCON.1 (IE0) byte received UART1 (optical) Logic and Polarity Selection Interrupt Flags Interrupt Enable IEN0.7 (EAL) IEN0.0 (EX0) Priority Assignment IT0 IEN2.0 (ES1) S1CON.0 (RI1) IP1.0/ IP0.0 >=1 byte transmitted S1CON.1 (TI1) IEN0.1 (ET0) Timer 0 XPULSE YPULSE 2 1 3 overflow occurred CE detected zero crossing CE detected sag EX_XPULSE TCON.5 (TF0) EX_YPULSE IE_YPULSE WPULSE Wh pulse EX_WPULSE IE_WPULSE VPULSE VARh pulse EX_VPULSE IE_VPULSE DIO_Rn TCON.3 (IE1) DIO CE_BUSY DIO status changed IEN1.1 (EX2) IE_XPULSE >=1 I3FR overflow occurred VSTAT IEN0.3 (ET1) TCON.7 (TF1) >=1 byte transmitted 5 command received XFER_BUSY accumulation cycle completed RTC_1M RTC_T EX_EEX S0CON.0 (TI0) IEN1.4 (EX5) IE_EEX >=1 SPI RTC_1S 6 BUSY fell IEN0.4 (ES0) S0CON.0 (RI0) UART0 EEPROM every second every minute alarm clock EX_SPI IP1.4/ IP0.4 IRCON.4 (IEX5) IE_SPI EX_XFER IE_XFER EX_RTC1S IE_RTC1S EX_RTC1M IE_RTC1M IEN1.5 (EX6) IP1.5/ IP0.5 IRCON.5 (IEX6) >=1 EX_RTCT IE_RTCT Flag=1 means that an interrupt has occurred and has not been cleared EX0 - EX6 are cleared automaticallywhen the hardware vectors to the interrupt handler (c) 2008-2011 Teridian Semiconductor Corporation Interrupt Vector 3/19/2010 Figure 12: Interrupt Structure 46 IP1.3/ IP0.3 IRCON.3 (IEX4) Supply status changed byte received IP1.2/ IP0.2 IRCON.2 (IEX3) IEN1.3 (EX4) 4 IP1.1/ IP0.1 IEN0.2 (EX1) IEN1.2 (EX3) CE completed code run and has new status information Timer 1 I2FR IRCON.1 (IEX2) Polling Sequence No. v1.2 71M6543F/H and 71M6543G/GH Data Sheet 2.5 On-Chip Resources 2.5.1 Physical Memory 2.5.1.1 Flash Memory The device includes 64 KB (71M6543F/H) or 128 KB (71M6543G/GH) of on-chip flash memory. The flash memory primarily contains MPU and CE program code. It also contains images of the CE RAM and I/O RAM. On power-up, before enabling the CE, the MPU copies these images to their respective locations. Flash space allocated for the CE program is limited to 4096 16-bit words (8 KB). The CE program must begin on a 1-KB boundary of the flash address space. The CE_LCTN[6/5:0] (I/O RAM 0x2109[5:0]) field on the 71M6543F/H and the CE_LCTN[6:0] (I/O RAM 0x2109[6:0]) field on the 71M6543G/GH define which 1-KB boundary contains the CE code. Thus, the first CE instruction is located at 1024*CE_LCTN[6/5:0] on the 71M6543F/H and at 1024*CE_LCTN[6:0] on the 71M6543G/GH. Flash memory can be accessed by the MPU, the CE, and by the SPI interface (R/W). Table 39: Flash Memory Access Access by MPU CE SPI Access Type R/W/E R R/W/E Condition W/E only if CE is disabled. Access only when SFM is invoked (MPU halted). Flash Write Procedures If the FLSH_UNLOCK[3:0] (I/O RAM 0x2702[7:4]) key is correctly programmed, the MPU may write to the flash memory. This is one of the non-volatile storage options available to the user in addition to external EEPROM. The flash program write enable bit, FLSH_PSTWR (SFR 0xB2[0]), differentiates 80515 data store instructions (MOVX@DPTR,A) between Flash and XRAM writes. This bit is automatically cleared by hardware after each byte write operation. Write operations to this bit are inhibited when interrupts are enabled. If the CE is enabled (CE_E = 1, I/O RAM 0x2106[0]), flash write operations must not be attempted unless FLSH_PSTWR is set. This bit enables the "posted flash write" capability. FLSH_PSTWR has no effect when CE_E = 0). When CE_E = 1, however, FLSH_PSTWR delays a flash write until the time interval between the CE code passes. During this delay time, the FLSH_PEND (SFR 0xB2[3]) bit is high, and the MPU continues to execute commands. When the CE code pass ends (CE_BUSY falls), the FLSH_PEND bit falls and the write operation occurs. The MPU can query the FLSH_PEND bit to determine when the write operation has been completed. While FLSH_PEND = 1, further flash write requests are ignored. Updating Individual Bytes in Flash Memory The original state of a flash byte is 0xFF (all bits are 1). Once a value other than 0xFF is written to a flash memory cell, overwriting with a different value usually requires that the cell be erased first. Since cells cannot be erased individually, the page has to be first copied to RAM, followed by a page erase. After this, the page can be updated in RAM and then written back to the flash memory. Flash Erase Procedures Flash erasure is initiated by writing a specific data pattern to specific SFR registers in the proper sequence. These special pattern/sequence requirements prevent inadvertent erasure of the flash memory. The mass erase sequence is: * * Write 1 to the FLSH_MEEN bit (SFR 0xB2[1]). Write the pattern 0xAA to the FLSH_ERASE (SFR 0x94) register. The mass erase cycle can only be initiated when the ICE port is enabled. v1.2 (c) 2008-2011 Teridian Semiconductor Corporation 47 71M6543F/H and 71M6543G/GH Data Sheet The page erase sequence is: * * Write the page address to FLSH_PGADR[5:0] (SFR 0xB7[7:2]). Write the pattern 0x55 to the FLSH_ERASE register (SFR 0x94). Bank-Switching in the 71M6543G/GH The 128 KB program memory in the 71M6543G/GH consists of a fixed lower bank of 32 KB, addressable at 0x0000 to 0x7FFF plus an upper banked area of 32 KB, addressable at 0x8000 to 0xFFFF. The I/O RAM register FL_BANK[1:0] (SFR 0xB6[1:0]) is used to switch four memory banks of 32 KB each into the address range from 0x8000 to 0xFFFF. Note that when FL_BANK[1:0] (SFR 0xB6[1:0]) = 0, the upper bank is the same as the lower bank. Table 40: Bank Switching with FL_BANK[1:0] (SFR 0xB6[1:0])in the 71M6543G/GH 71M6543G/GH Address Range for Lower Address Range for Upper FL_BANK[1:0] Bank (0x0000-0x7FFF) Bank (0x8000-0xFFFF) 00 0x0000-0x7FFF 0x0000-0x7FFF 01 0x0000-0x7FFF 0x8000-0xFFFF 10 0x0000-0x7FFF 0x10000-0x17FFF 11 0x0000-0x7FFF 0x18000-0x1FFFF In the 71M6543G/GH, the address that the FLSH_PGADR[6:0] (SFR 0xB7[7:1]) points to in the program address space can reference different flash memory locations, depending on the setting of the FL_BANK[1:0] (SFR 0xB6[1:0]) bits. The CE_LCTN[6:0] (I/O RAM 0x2109[6:0]) field on the 71M6543G/GH on the other hand, points directly to a location in the flash memory are not affected by the FL_BANK[1:0] (SFR 0xB6[1:0]) bits Program Security When enabled, the security feature limits the ICE to global flash erase operations only. All other ICE operations, such as reading via the SPI or ICE port, are blocked. This guarantees the security of the user's MPU and CE program code. Security is enabled by MPU code that is executed in a 64 CKMPU cycle pre-boot interval before the primary boot sequence begins. Once security is enabled, the only way to disable it is to perform a global erase of the flash, followed by a chip reset. The first 60 cycles of the MPU boot code are called the pre-boot phase because during this phase the ICE is inhibited. A read-only status bit, PREBOOT (SFR 0xB2[7]), identifies these cycles to the MPU. Upon completion of pre-boot, the ICE can be enabled and is permitted to take control of the MPU. The security enable bit, SECURE (SFR 0xB2[6]), is reset whenever the chip is reset. Hardware associated with the bit allows only ones to be written to it. Thus, pre-boot code may set SECURE to enable the security feature but may not reset it. Once SECURE is set, the pre-boot and CE code are protected from erasure, and no external read of program code is possible. Specifically, when the SECURE bit is set, the following applies: * * * The ICE is limited to bulk flash erase only. Page zero of flash memory, the preferred location for the user's pre-boot code, may not be page-erased by either MPU or ICE. Page zero may only be erased with global flash erase. Write operations to page zero, whether by MPU or ICE are inhibited. The 71M6543 also includes hardware to protect against unintentional Flash write and erase. To enable flash write and erase operations, a 4-bit hardware key that must be written to the FLSH_UNLOCK[3:0] field. The key is the binary number `0010'. If FLSH_UNLOCK[3:0] is not `0010', the Flash erase and write operation is inhibited by hardware. Proper operation of this security key requires that there be no firmware function that writes `0010' to FLSH_UNLOCK[3:0]. The key should be written by the external SPI master, in the case of SPI flash programming (SFM mode), or through the ICE interface in the case of ICE flash programming. When a boot loader is used, the key should be sent to the boot load code which then writes it to 48 (c) 2008-2011 Teridian Semiconductor Corporation v1.2 71M6543F/H and 71M6543G/GH Data Sheet FLSH_UNLOCK[3:0]. FLSH_UNLOCK[3:0] is not automatically reset. It should be cleared when the SPI or ICE has finished changing the Flash. Table 41 summarizes the I/O RAM registers used for flash security. Table 41: Flash Security Name Location Rst Wk Dir Description FLSH_UNLOCK[3:0] 2702[7:4] 0 0 R/W SECURE SFR B2[6] 0 0 R/W Must be a 2 to enable any flash modification. See the description of Flash security for more details. Inhibits erasure of page 0 and flash addresses above the beginning of CE code as defined by CE_LCTN[6/5:0](I/O RAM 0x2109[5:0]) on the 71M6543F/H and CE_LCTN[6:0] I/O RAM 0x2109[6:0]) on the 71M6543G/GH. Also inhibits the read of flash via the ICE and SPI ports. SPI Flash Mode In normal operation, the SPI slave interface cannot read or write the flash memory. However, the 71M6543 contains a Special Flash Mode (SFM) that facilitates initial (production) programming of the flash memory. When the 71M6543 is in SFM mode, the SPI interface can erase, read, and write the flash. Other memory elements such as XRAM and I/O RAM are not accessible to the SPI in this mode. In order to protect the flash contents, several operations are required before the SFM mode is successfully invoked. When the 71M6543G/GH is operating SFM, SPI single-byte transactions are used to write to FL_BANK[1:0] (SFR 0xB6[1:0]). During an SPI single-byte transaction, SPI_CMD[1:0] will over-write the contents of FL_BANK[1:0] (SFR 0xB6[1:0]). This will allow for access of the entire 128 KB flash memory while operating in SFM. Details on the SFM can be found in 2.5.12 SPI Slave Port. 2.5.1.2 MPU/CE RAM The 71M6543 includes 5 KB of static RAM memory on-chip (XRAM) plus 256 bytes of internal RAM in the MPU core. The 5KB of static RAM are used for data storage by both MPU and CE and for the communication between MPU and CE. 2.5.1.3 I/O RAM (Configuration RAM) The I/O RAM can be seen as a series of hardware registers that control basic hardware functions. I/O RAM address space starts at 0x2000. The registers of the I/O RAM are listed in Table 69. The 71M6543 includes 128 bytes non-volatile RAM memory on-chip in the I/O RAM address space (addresses 0x2800 to 0x287F). This memory section is supported by the voltage applied at VBAT_RTC, and the data in it are preserved in BRN, LCD, and SLP modes as long as the voltage at VBAT_RTC is within specification. 2.5.2 Oscillator The 71M6543 oscillator drives a standard 32.768 kHz watch crystal. This type of crystal is accurate and does not require a high-current oscillator circuit. The oscillator has been designed specifically to handle watch crystals and is compatible with their high impedance and limited power handling capability. The oscillator power dissipation is very low to maximize the lifetime of any battery attached to VBAT_RTC. Oscillator calibration can improve the accuracy of both the RTC and metering. Refer to 2.5.4, Real-Time Clock (RTC) for more information. The oscillator is powered from the V3P3SYS pin or from the VBAT_RTC pin, depending on the V3OK internal bit (i.e., V3OK = 1 if V3P3SYS 2.8 VDC and V3OK = 0 if V3P3SYS < 2.8 VDC). The oscillator requires approximately 100 nA, which is negligible compared to the internal leakage of a battery. v1.2 (c) 2008-2011 Teridian Semiconductor Corporation 49 71M6543F/H and 71M6543G/GH Data Sheet Although the oscillator may appear to work when VBAT is not connected, this mode of operation is not recommended. If VBAT_RTC is connected to a drained battery or disconnected, a battery test that sets TEMP_BAT may drain the supply connected to VBAT_RTC and cause the oscillator to stop. A stopped oscillator may force the device to reset. Therefore, an unexpected reset during a battery test should be interpreted as a battery failure. 2.5.3 PLL and Internal Clocks Timing for the device is derived from the 32.768 kHz crystal oscillator output that is multiplied by a PLL by 600 to obtain 19.660800 MHz, the master clock (MCK). All on-chip timing, except for the RTC clock, is derived from MCK. Table 42 provides a summary of the clock functions and their controls. The two general-purpose counter/timers contained in the MPU are controlled by CKMPU (see 2.4.7 Timers and Counters). The master clock can be boosted to 19.66 MHz by setting the PLL_FAST bit = 1 (I/O RAM 0x2200[4]) and can be reduced to 6.29 MHz by PLL_FAST = 0. The MPU clock frequency CKMPU is determined by another divider controlled by the I/O RAM control field MPU_DIV[2:0] (I/O RAM 0x2200[2:0]) and can be -(MPU_DIV+2) where MPU_DIV[2:0] may vary from 0 to 4. When the ICE_E pin is high, the set to MCK*2 circuit also generates the 9.83 MHz clock for use by the emulator. The PLL is only turned off in SLP mode or in LCD mode when LCD_BSTE is disabled. The LCD_BSTE value depends on the setting of the LCD_VMODE [1:0] field (see Table 52). When the part is waking up from SLP or LCD modes, the PLL is turned on in 6.29 MHz mode, and the PLL frequency is not be accurate until the PLL_OK (SFR 0xF9[4]) flag rises. Due to potential overshoot, the MPU should not change the value of PLL_FAST until PLL_OK is true. 50 (c) 2008-2011 Teridian Semiconductor Corporation v1.2 71M6543F/H and 71M6543G/GH Data Sheet Table 42: Clock System Summary Clock OSC Crystal MCK Crystal/PLL CKCE MCK CKADC MCK CKMPU MCK CKICE MCK CKOPTMOD MCK CK32 MCK 2.5.4 Fixed Frequency or Range Derived From PLL_FAST=1 PLL_FAST=0 Controlled by Function 32.768 kHz - Crystal clock 19.660800 MHz 6.291456 MHz PLL_FAST Master clock (600*CK32) (192*CK32) 4.9152 MHz 1.5728 MHz - CE clock 1.572864 MHz, 4.9152 MHz, ADC_DIV ADC clock 2.4576 MHz 0.786432 MHz 4.9152 MHz ... 1.572864 MHz... MPU_DIV[2:0] MPU clock 307.2 kHz 98.304 kHz 9.8304 MHz... 3.145728 MHz ... MPU_DIV[2:0] ICE clock 196.608 kHz 614.4 kHz Optical UART 38.40 kHz 38.6 kHz - Modulation 32.768 kHz - 32 kHz clock Real-Time Clock (RTC) 2.5.4.1 RTC General Description The RTC is driven directly by the crystal oscillator and is powered by either the V3P3SYS pin or the VBAT_RTC pin, depending on the V3OK internal bit. The RTC consists of a counter chain and output registers. The counter chain consists of registers for seconds, minutes, hours, day of week, day of month, month, and year. The chain registers are supported by a shadow register that facilitates read and write operations. Table 43 shows the I/O RAM registers for accessing the RTC. 2.5.4.2 Accessing the RTC Two bits, RTC_RD (I/O RAM 0x2890[6]) and RTC_WR (I/O RAM 0x2890[7]), control the behavior of the shadow register. When RTC_RD is low, the shadow register is updated by the RTC after each two milliseconds. When RTC_RD is high, this update is halted and the shadow register contents become stationary and are suitable to be read by the MPU. Thus, when the MPU wishes to read the RTC, it freezes the shadow register by setting the RTC_RD bit, reads the shadow register, and then lowers the RTC_RD bit to let updates to the shadow register resume. Since the RTC clock is only 500 Hz, there may be a delay of approximately 2 ms from when the RTC_RD bit is lowered until the shadow register receives its first update. Reads to RTC_RD continues to return a one until the first shadow update occurs. When RTC_WR is high, the update of the shadow register is also inhibited. During this time, the MPU may overwrite the contents of the shadow register. When RTC_WR is lowered, the shadow register is written into the RTC counter on the next 500Hz RTC clock. A `change' bit is included for each word in the shadow register to ensure that only programmed words are updated when the MPU writes a zero to RTC_WR. Reads of RTC_WR returns one until the counter has actually been updated by the register. The sub-second register of the RTC, RTC_SBSC (I/O RAM 0x2892), can be read by the MPU after the one second interrupt and before reaching the next one second boundary. RTC_SBSC contains the count since the last full second, in 1/128 second nominal clock periods, until the next one-second boundary. When the RST_SUBSEC bit is written, the SUBSEC counter is restarted, counting from 0 to 127. Reading and resetting the sub-second counter can be used as part of an algorithm to accurately set the RTC. The RTC is capable of processing leap years. Each counter has its own output register. The RTC chain registers are not be affected by the reset pin, watchdog timer resets, or by transitions between the battery modes and mission mode. v1.2 (c) 2008-2011 Teridian Semiconductor Corporation 51 71M6543F/H and 71M6543G/GH Data Sheet Table 43: RTC Control Registers Name Location Rst Wk Dir Description RTCA_ADJ[6:0] RTC_P[16:14] RTC_P[13:6] RTC_P[5:0] RTC_Q[1:0] 2504[6:0] 289B[2:0] 289C[7:0] 289D[7:2] 289D[1:0] 40 4 0 0 0 -4 0 0 0 R/W R/W Register for analog RTC frequency adjustment. R/W RTC_RD 2890[6] 0 0 R/W RTC_WR 2890[7] 0 0 R/W RTC_FAIL 2890[4] 0 0 R/W Register for digital RTC adjustment. Freezes the RTC shadow register so it is suitable for MPU reads. When RTC_RD is read, it returns the status of the shadow register: 0 = up to date, 1 = frozen. Writing 0 to RTC_RD bit to enable shadow register update, and writing 1 to RTC_RD to disable update Freezes the RTC shadow register so it is suitable for MPU write operations. When RTC_WR is cleared, the contents of the shadow register are written to the RTC counter on the next RTC clock (~1 kHz). When RTC_WR is read, it returns 1 as long as RTC_WR is set, and continues to return one until the RTC counter is updated. Writing 0 to RTC_WR bit to enable copying the shadow register contents to RTC counter, and writing 1 to RTC_WR to disable copying Indicates that a count error has occurred in the RTC and that the time is not trustworthy. This bit can be cleared by writing a 0. Time remaining since the last 1 second boundary. LSB = 1/128 second. RTC_SBSC[7:0] 2892[7:0] R Registers for digital RTC adjustment. 0x0FFBF RTC_P 0x10040 2.5.4.3 RTC Rate Control The 71M6543 has two rate adjustment mechanisms: * * The first rate adjustment mechanism is an analog rate adjustment, using the I/O RAM register RTCA_ADJ[6:0], that trims the crystal load capacitance. The second rate adjustment mechanism is a digital rate adjust that affects the way the clock frequency is processed in the RTC. Setting RTCA_ADJ[6:0] to 00 minimizes the load capacitance, maximizing the oscillator frequency. Setting RTCA_ADJ[6:0] to 0x7F maximizes the load capacitance, minimizing the oscillator frequency. The adjustable capacitance is approximately: C ADJ = RTCA _ ADJ 16.5 pF 128 The precise amount of adjustment depends on the crystal properties, the PCB layout and the value of the external crystal capacitors (see CXS and CXS in Table 89). The adjustment may occur at any time, and the resulting clock frequency should be measured over a one-second interval. The second rate adjustment is digital, and can be used to adjust the clock rate up to 988ppm, with a resolution of 3.8 ppm. The rate adjustment is implemented starting at the next second-boundary following the adjustment. Since the LSB (define first) results in an adjustment every four seconds, the frequency should be measured over an interval that is a multiple of four seconds. The clock rate is adjusted by writing the appropriate values to RTC_P[16:0] (I/O RAM 0x289B[2:0], 0x289C, 0x289D[7:2]) and RTC_Q[1:0] (I/O RAM 0x289D[1:0]). Updates to RTC rate adjust registers, RTC_P and RTC_Q, are done through the shadow register described above. The new values are loaded into the counters when RTC_WR (I/O RAM 0x2890[7]) is lowered. 52 (c) 2008-2011 Teridian Semiconductor Corporation v1.2 71M6543F/H and 71M6543G/GH Data Sheet The default frequency is 32,768 RTCLK cycles per second. To shift the clock frequency by ppm, RTC_P and RTC_Q are calculated using the following equation: 32768 8 4 RTC_P + RTC_Q = floor + 0.5 -6 1 + 10 Conversely, the amount of ppm shift for a given value of 4RTC_P+RTC_Q is: 32768 8 - 1 106 ( ppm) = 4 RTCP + RTCQ For example, for a shift of -988 ppm, 4 RTC_P + RTC_Q = 262403 = 0x40103. RTC_P[16:0] = 0x10040, (I/O RAM 0x289B[2:0], 0x289C, 0x289D[7:2]) and RTC_Q[1:0] = 0x03 (I/O RAM 0x289D[1:0]. The default values of RTC_P[16:0] and RTC_Q[1:0], corresponding to zero adjustment, are 0x10000 and 0x0, respectively. Two settings for the TMUX2OUT test pin, PULSE_1S and PULSE_4S, are available for measuring and calibrating the RTC clock frequency. These are waveforms of approximately 25% duty cycle with 1s or 4s period. Default values for RTCA_ADJ[6:0], RTC_P[16:0] and RTC_Q[1:0] should be nominal values, at the center of the adjustment range. Un-calibrated extreme values (zero, for example) can cause incorrect operation. If the crystal temperature coefficient is known, the MPU can integrate temperature and correct the RTC time as necessary. Alternatively, the characteristics can be loaded into an NV RAM and the OSC_COMP (I/O RAM 0x28A0[5]) bit may be set. In this case, the oscillator is adjusted automatically, even in SLP mode. See 2.5.4.4 RTC Temperature Compensation for details. 2.5.4.4 RTC Temperature Compensation The 71M6543 can be configured to regularly measure die temperature, including in SLP and LCD modes and while the MPU is halted. If enabled by OSC_COMP, this temperature information is automatically used to correct for the temperature variation of the crystal. A table lookup method is used. Table 44 shows I/O RAM registers involved in automatic RTC temperature compensation. Table 44: I/O RAM Registers for RTC Temperature Compensation Name Location Rst Wk Dir OSC_COMP 28A0[5] 0 0 R/W STEMP[10:3] STEMP[2:0] 2881[7:0] 2882[7:5] - - R LKPADDR[6:0] 2887[6:0] 0 0 R/W 2887[7] 0 0 R/W 2888[7:0] 0 0 R/W 2889[1] 2889[0] 0 0 0 0 R/W R/W LKPAUTOI LKPDAT[7:0] LKP_RD LKP_WR Description Enables the automatic update of RTC_P[16:0] and RTC_Q[1:0] every time the temperature is measured. The result of the temperature measurement (10-bits of magnitude data plus a sign bit). The address for reading and writing the RTC lookup RAM. Auto-increment flag. When set, LKPADDR[6:0] auto increments every time LKP_RD or LKP_WR is pulsed. The incremented address can be read at LKPADDR[6:0]. The data for reading and writing the RTC lookup RAM. Strobe bits for the RTC lookup RAM read and write. When set, the LKPADDR[6:0] and LKPDAT registers are used in a read or write operation. When a strobe is set, it stays set until the operation completes, at which time the strobe is cleared and LKPADDR[6:0] is incremented if LKPAUTOI is set. Referring to Figure 13 the table lookup method uses the 10-bits plus sign-bit value in STEMP[10:0] right-shifted by two bits to obtain an 8-bit plus sign value (i.e., NV RAM Address = STEMP[10:0]/4). A v1.2 (c) 2008-2011 Teridian Semiconductor Corporation 53 71M6543F/H and 71M6543G/GH Data Sheet limiter ensures that the resulting look-up address is in the 6-bit plus sign range of -64 to +63 (decimal). The 8-bit NV RAM content pointed to by the address is added as a 2's complement value to 0x40000, the nominal value of 4*RTC_P[16:0] + RTC_Q[1:0]. Refer to 2.5.4.3 RTC Rate Control for information on the rate adjustments performed by registers RTC_P[16:0] and RTC_Q[1:0]. The 8-bit values loaded in to NV RAM must be scaled correctly to produce rate adjustments that are consistent with the equations given in 2.5.4.3 RTC Rate Control for RTC_P[16:0] and RTC_Q[1:0]. Note that the sum of the looked-up 8-bit 2's complement value and 0x40000 form a 19bit value, which is equal to 4*RTC_P[16:0] + RTC_Q[1:0], as shown in Figure 13. The output of the Temperature Compensation is automatically loaded into the RTC_P[16:0] and RTC_Q[1:0] locations after each look-up and summation operation. LIMIT STEMP 10+S >>2 8+S Look Up RAM 63 ADDR -256 -64 63 255 6+S -64 Q 7+S 19 4*RTC_P+RTC_Q 19 0x40000 Figure 13: Automatic Temperature Compensation The 128 NV RAM locations are organized in 2's complement format. As mentioned above, the STEMP[10:0] digital temperature values are scaled such that the corresponding NV RAM addresses are equal to STEMP[10:0]/4 (limited in the range of -64 to +63). See 2.5.5 71M6543 Temperature Sensor on page 55 for the equations to calculate temperature in degrees C from the STEMP[10:0] reading. For proper operation, the MPU has to load the lookup table with values that reflect the crystal properties with respect to temperature, which is typically done once during initialization. Since the lookup table is not directly addressable, the MPU uses the following procedure to load the NV RAM table: 1. Set the LKPAUTOI bit (I/O RAM 0x2887[7]) to enable address auto-increment. 2. Write zero into the I/O RAM register LKPADDR[6:0] (I/O RAM 0x2887[6:0]). 3. Write the 8-bit datum into I/O RAM register LKPDAT (I/O RAM 0x2888). 4. Set the LKP_WR bit (I/O RAM 0x2889[0]) to write the 8-bit datum into NV_RAM 5. Wait for LKP_WR to clear (LKP_WR auto-clears when the data has been copied to NV RAM). 6. Repeat steps 3 through 5 until all data has been written to NV RAM. The NV RAM table can also be read by writing a 1 into the LKP_RD bit (I/O RAM 0x2889[1]). The process of reading from and writing to the NV RAM is accelerated by setting the LKPAUTOI bit (I/O RAM 0x2887[7]). When LKPAUTOI is set, LKPADDR[6:0] (I/O RAM 0x2887[6:0]) auto-increments every time LKP_RD or LKP_WR is pulsed. It is also possible to perform random access of the NV RAM by writing a 0 to the LKPAUTOI bit and loading the desired address into LKPADDR[6:0]. If the oscillator temperature compensation feature is not being used, it is possible to use the NV RAM storage area as ordinary battery-backed NV storage space using the procedure described above to read and write NV RAM data. In this case, the OSC_COMP bit (I/O RAM 0x28A0[5]) is reset to disable the automatic oscillator temperature compensation feature. 2.5.4.5 RTC Interrupts The RTC generates interrupts each second and each minute. These interrupts are called RTC_1SEC and RTC_1MIN. In addition, the RTC functions as an alarm clock by generating an interrupt when the minutes and hours registers both equal their respective target counts as defined in . The alarm clock interrupt is called RTC_T. All three interrupts appear in the MPU's external interrupt 6. See Table 33 in the interrupt section for the enable bits and flags for these interrupts. The minute and hour target registers are listed in Table 45. 54 (c) 2008-2011 Teridian Semiconductor Corporation v1.2 71M6543F/H and 71M6543G/GH Data Sheet Table 45: I/O RAM Registers for RTC Interrupts Name Location Rst Wk RTC_TMIN[5:0] 289E[5:0] 0 0 289F[4:0] 0 0 RTC_THR[4:0] 2.5.5 Dir Description R/W The target minutes register. See below. The target hours register. The RTC_T interrupt occurs R/W when RTC_MIN[5:0] becomes equal to RTC_TMIN[5:0] and RTC_HR[4:0] becomes equal to RTC_THR[4:0]. 71M6543 Temperature Sensor The 71M6543 includes an on-chip temperature sensor for determining the temperature of its bandgap reference. The primary use of the temperature data is to determine the magnitude of compensation required to offset the thermal drift in the system for the compensation of current, voltage and energy measurement and the RTC. See 4.5 Metrology Temperature Compensation on page 89. Also see 2.5.4.4 RTC Temperature Compensation on page 53. Unlike earlier generation Teridian SoCs, the 71M6543 does not use the ADC to read the temperature sensor. Instead, it uses a technique that is operational in SLP and LCD mode, as well as BRN and MSN modes. This means that the temperature sensor can be used to compensate for the frequency variation of the crystal, even in SLP mode while the MPU is halted. See 2.5.4.4 RTC Temperature Compensation on page 53. In MSN and BRN modes, the temperature sensor is awakened on command from the MPU by setting the TEMP_START (I/O RAM 0x28B4[6]) control bit. In SLP and LCD modes, it is awakened at a regular rate set by TEMP_PER[2:0] (I/O RAM 0x28A0[2:0]). The result of the temperature measurement is read from the two I/O RAM locations STEMP[10:3] (I/O RAM 0x2881) and STEMP[2:0] (I/O RAM 0x2882[7:5]). Note that both of these I/O RAM locations must be read and properly combined to form the STEMP[10:0] 11-bit value (see STEMP in Table 46). The resulting 11-bit value is in 2's complement form and ranges from -1024 to +1023 (decimal). The equations below are used to calculate the sensed temperature. The first equation applies when the 71M6543F and 71M6543G are in MSN mode and TEMP_PWR = 1. The second equation applies when the 71M6543F and 71M6543G are in BRN mode, and in this case, the TEMP_PWR and TEMP_BSEL bits must both be set to the same value, so that the battery that supplies the temperature sensor is also the battery that is measured and reported in BSENSE. Thus, the second equation requires reading STEMP and BSENSE. In the second equation, BSENSE (the sensed battery voltage) is used to obtain a more accurate temperature reading when the IC is in BRN mode. A second set of equations if provided for the 71M6543H and 71M6543GH high precision parts. The coefficients provided in the various STEMP equations below are typical. For the 71M6543F and 71M6543G in MSN Mode (with TEMP_PWR = 1): Temp(C ) = 0.325 STEMP + 22 For the 71M6543F and 71M6543G in BRN Mode, (with TEMP_PWR=TEMP_BSEL): Temp(oC ) = 0.325 STEMP + 0.00218 BSENSE 2 - 0.609 BSENSE + 64.4 For the 71M6543H and 71M6543GH in BRN mode (with TEMP_PWR=TEMP_BSEL): If STEMP 0: () = 0.325 + 0.00218 2 - 0.609 + 64.4 If STEMP > 0: () = v1.2 63 + 0.00218 2 - 0.609 + 64.4 _85 (c) 2008-2011 Teridian Semiconductor Corporation 55 71M6543F/H and 71M6543G/GH Data Sheet Table 46 shows the I/O RAM registers used for temperature and battery measurement. If TEMP_PWR selects VBAT_RTC when the battery is nearly discharged, the temperature measurement may not finish. In this case, firmware may complete the measurement by selecting V3P3D (TEMP_PWR = 1). Table 46: I/O RAM Registers for Temperature and Battery Measurement Name Location Rst Wk Dir 28A0[3] 0 0 R 28A0[2:0] 0 - R/W TEMP_BAT 28A0[4] 0 - R/W TEMP_START 28B4[6] 0 - TEMP_PWR 28A0[6] 0 - TEMP_BSEL 28A0[7] 0 - 0 - TBYTE_BUSY TEMP_PER[2:0] TEMP_TEST[1:0] 2500[1:0] Description Indicates that hardware is still writing the 0x28A0 byte. Additional writes to this byte are locked out while it is one. Write duration could be as long as 6 ms. Sets the period between temperature measurements. Automatic measurements can be enabled in any mode (MSN, BRN, LCD, or SLP). TEMP_PER 0 1-6 7 Causes VBAT to be measured whenever a temperature measurement is performed. TEMP_PER[2:0] must be zero in order for TEMP_START to function. If TEMP_PER[2:0] = 0, then setting TEMP_START starts a temperature measurement. R/W Ignored in SLP and LCD modes. Hardware clears TEMP_START when the temperature measurement is complete. Selects the power source for the temperature sensor: 1 = V3P3D, 0 = VBAT_RTC. This bit is ignored in R/W SLP and LCD modes, where the temperature sensor is always powered by VBAT_RTC. Selects which battery is monitored by the R/W temperature sensor: 1 = VBAT, 0 = VBAT_RTC Test bits for the temperature monitor VCO. TEMP_TEST must be 00 in regular operation. Any other value causes the VCO to run continuously with the control voltage described below. R/W TEMP_TEST Function 00 01 1X STEMP[10:3] STEMP[2:0] 2881[7:0] 2882[7:5] BSENSE[7:0] 2885[7:0] - - 2704[3] 0 0 BCURR 2.5.6 56 Time Manual updates (see TEMP_START) 2 ^ (3+TEMP_PER) (seconds) Continuous Normal operation Reserved for factory test Reserved for factory test R R The result of the temperature measurement. The STEMP[10:0] value may be obtained in C with a single 16-bit read and divide by 32 operation as follows: volatile int16_t xdata STEMP _at_0x2881; fa = (float)(STEMP/32); R The result of the battery measurement. Connects a 100 A load to the battery selected by R/W TEMP_BSEL. 71M6xx3 Temperature Sensor (c) 2008-2011 Teridian Semiconductor Corporation v1.2 71M6543F/H and 71M6543G/GH Data Sheet The 71M6xx3 includes an on-chip temperature sensor for determining the temperature of its bandgap reference. The primary use of the temperature data is to determine the magnitude of compensation required to offset the thermal drift in the system for the compensation of the current measurement performed by the71M6xx3. See the 71M6xxx Data Sheet for the equation to calculate temperature from the 71M6xx3 STEMP[10:0] reading. Also, see 4.5 Metrology Temperature Compensation on page 89. See 2.2.8.3 Control of the 71M6xx3 Isolated Sensor on page 22 for information on how to read the STEMP[10:0] information from the 71M6xx3. 2.5.7 71M6543 Battery Monitor The 71M6543 temperature measurement circuit can also monitor the batteries at the VBAT and VBAT_RTC pins. The battery to be tested (i.e., VBAT or VBAT_RTC pin) is selected by TEMP_BSEL (I/O RAM 0x28A0[7]). When TEMP_BAT (I/O RAM 0x28A0[4]) is set, a battery measurement is performed as part of each temperature measurement. The value of the battery reading is stored in register BSENSE[7:0] (I/O RAM 0x2885). The following equations are used to calculate the voltage measured on the VBAT pin (or VBAT_RTC pin) from the BSENSE[7:0] and STEMP[10:0] values. The result of the equation below is in volts. A slightly different equation is used for MSN mode and BRN mode, as follows. In MSN mode, TEMP_PWR = 1 use: VBAT (orVBAT _ RTC ) = 3.3V + ( BSENSE - 142) 0.0246V + STEMP 0.000297V In BRN mode, TEMP_PWR = TEMP_BSEL use: VBAT (orVBAT _ RTC ) = 3.291V + ( BSENSE - 142) 0.0255V + STEMP 0.000328V In MSN mode, a 100 A de-passivation load can be applied to the selected battery (i.e., selected by the TEMP_BSEL bit) by setting the BCURR (I/O RAM 0x2704[3]) bit. Battery impedance can be measured by taking a battery measurement with and without BCURR. Regardless of the BCURR bit setting, the battery load is never applied in BRN, LCD, and SLP modes. 2.5.8 71M6xx3 VCC Monitor The 71M6xx3 monitors its VCC pin voltage. The voltage of the VCC pin can be obtained by the 71M6543 by issuing a read command to the 71M6xx3. The 71M6543 must request both the VSENSE[7:0] and STEMP[10:0] values from the 71M6xx3. See the 71M6xxx Data Sheet for the equation to calculate the 71M6xx3 VCC pin voltage from the VSENSE[7:0] and STEMP[10:0] values read from the 71M6xx3. See 2.2.8.3 Control of the 71M6xx3 Isolated Sensor on page 22 for information on how to read VSENSE[7:0] and STEMP[10:0] from the 71M6xx3 remote sensors. 2.5.9 UART and Optical Interface The 71M6543 provides two asynchronous interfaces, UART0 and UART1. Both can be used to connect to AMR modules, user interfaces, etc., and also support a mechanism for programming the on-chip flash memory. Referring to Figure 14, UART1 includes an interface to implement an IR/optical port. The pin OPT_TX is designed to directly drive an external LED for transmitting data on an optical link. The pin OPT_RX has the same threshold as the RX pin, but can also be used to sense the input from an external photo detector used as the receiver for the optical link. OPT_TX and OPT_RX are connected to a dedicated UART port (UART1). The OPT_TX and OPT_RX pins can be inverted with configuration bits OPT_TXINV (I/O RAM 0x2456[0]) and OPT_RXINV (I/O RAM 0x2457[1]), respectively. Additionally, the OPT_TX output may be modulated at 38 kHz. Modulation is available in MSN and BRN modes (see Table 62). The OPT_TXMOD bit (I/O RAM 0x2456[1]) enables modulation. The duty cycle is controlled by OPT_FDC[1:0] (I/O RAM 0x2457[5:4]) , which can select 50%, 25%, 12.5%, and 6.25% duty cycle. A 6.25% duty cycle means that OPT_TX is low for 6.25% of the period. When not needed for UART1, OPT_TX can alternatively be configured as SEGDIO51. Configuration is via the OPT_TXE[1:0] (I/O RAM 0x2456[3:2]) field and LCD_MAP[51] (I/O RAM 0x2405[0]). The v1.2 (c) 2008-2011 Teridian Semiconductor Corporation 57 71M6543F/H and 71M6543G/GH Data Sheet OPT_TXE[1:0] field allows the MPU to select VPULSE, WPULSE, SEGDIO51 or the output of the pulse modulator to be sourced onto the OPT_TX pin. Likewise, the OPT_RX pin can alternately be configured as SEGDIO55, and its control is OPT_RXDIS (I/O RAM 0x2457[2]) and LCD_MAP[55] (I/O RAM 0x2405[4]). from OPT_TX UART A VARPULSE WPULSE 3 2 DIO2 B 1 MOD OPT_TXINV EN OPT_TXMOD OPT_FDC V3P3 Internal OPT_TX 0 DUTY OPT_TXE[1:0] 2 OPT_TXMOD = 1, OPT_FDC = 2 (25%) OPT_TXMOD = 0 A A B B 1/38kHz Figure 14: Optical Interface Bit Banged Optical UART (Third UART) As shown in Figure 15, the 71M6543 can also be configured to drive the optical UART with a DIO signal in a bit banged configuration. When control bit OPT_BB (I/O RAM 0x2022[0]) is set, the optical port is driven by DIO5 and the SEGDIO5 pin is driven by UART1_TX. This configuration is typically used when the two dedicated UARTs must be connected to high speed clients and a slower optical UART is permissible. Internal SEG55 DIO55 1 1 OPT_RXDIS UART1_TX 0 DIO5 1 EN 0 SEG51 VARPULSE DIO51 B 0 V3P3 SEGDIO51/ OPT_TX 1 2 DUTY LCD_MAP[55] 3 WPULSE MOD A OPT_TXMOD OPT_FDC OPT_TXINV SEGDIO55/ OPT_RX 0 0 UART1_RX 0 LCD_MAP[51] 1 OPT_TXE[1:0] SEG5 2 1 0 SEGDIO5/TX2 1 LCD_MAP[5] OPT_BB OPT_TXMOD=1, OPT_FDC=2 (25%) OPT_TXMOD=0 A B 1/38kHz Figure 15: Optical Interface (UART1) 2.5.10 Digital I/O and LCD Segment Drivers 2.5.10.1 General Information The 71M6543 combines most DIO pins with LCD segment drivers. Each SEG/DIO pin can be configured as a DIO pin or as a segment driver pin (SEG). On reset or power-up, all DIO pins are DIO inputs (except for SEGDIO0-15, see caution note below) until they are configured as desired under MPU control. The pin function can be configured by the I/O RAM registers LCD_MAPn (0x2405 - 0x240B). Setting the bit corresponding to the pin in LCD_MAPn to 1 configures the pin for LCD, setting LCD_MAPn to 0 configures it for DIO. 58 (c) 2008-2011 Teridian Semiconductor Corporation v1.2 71M6543F/H and 71M6543G/GH Data Sheet After reset or power up, pins SEGDIO0 through SEGDIO15 are initially DIO outputs, but are disabled by PORT_E = 0 (I/O RAM 0x270C[5]) to avoid unwanted pulses during reset. After configuring pins SEGDIO0 through SEGDIO15 the MPU must enable these pins by setting PORT_E. Once a pin is configured as DIO, it can be configured independently as an input or output. For SEGDIO0 to SEGDIO15, this is done with the SFR registers P0 (SFR 0x80), P1 (SFR 0x90), P2 (SFR 0xA0) and P3 (SFR 0xB0), as shown in Table 48. Example: SEGDIO12 (pin 32 in Table 48) is configured as a DIO output pin with a value of 1 (high) by writing 0 to bit 4 of LCD_MAP[15:8], and writing 1 to both P3[4]and P3[0]. The same pin is configured as an LCD driver by writing 1 to bit 4 of LCD_MAP[15:8]. The display information is written to bits 0 to 5 of LCD_SEG12. The PB pin is a dedicated digital input and is not part of the SEGDIO system. The CE features pulse counting registers and each pulse counter interrupt output is internally routed to the pulse interrupt logic. Thus, no routing of pulse signals to external pins is required in order to generate pulse interrupts. See interrupt source No. 2 in Figure 12. A 3-bit configuration word, I/O RAM register DIO_Rn (I/O RAM 0x2009[2:0] through 0x200E[6:4]) can be used for pins SEGDIO2 through SEGDIO11 (when configured as DIO) and PB to individually assign an internal resource such as an interrupt or a timer control (DIO_RPB[2:0], I/O RAM 0x2450[2:0], configures the PB pin). This way, DIO pins can be tracked even if they are configured as outputs. Table 48 lists the internal resources which can be assigned using DIO_R2[2:0] through DIO_R11[2:0] and DIO_RPB[2:0]. If more than one input is connected to the same resource, the resources are combined using a logical OR. Table 47: Selectable Resources using the DIO_Rn[2:0] Bits Resource Selected for SEGDIOn or PB Pin Value in DIO_Rn[2:0] 0 None 1 Reserved 2 T0 (counter0 clock) 3 T1 (counter1 clock) 4 High priority I/O interrupt (INT0) Low priority I/O interrupt (INT1) 5 Note: Resources are selectable only on SEGDIO2 through SEGDIO11 and the PB pin. See Table 49. When driving LEDs, relay coils etc., the DIO pins should sink the current into GNDD (as shown in Figure 16, right), not source it from V3P3D (as shown in Figure 16, left). This is due to the resistance of the internal switch that connects V3P3D to either V3P3SYS or VBAT. See 6.4.6 V3P3D Switch on page 139. Sourcing current in or out of DIO pins other than those dedicated for wake functions, for example with pullup or pulldown resistors, must be avoided. Violating this rule leads to increased quiescent current in sleep and LCD modes. v1.2 (c) 2008-2011 Teridian Semiconductor Corporation 59 71M6543F/H and 71M6543G/GH Data Sheet MISSION LCD/SLEEP BROWNOUT V3P3SYS V3P3SYS MISSION LCD/SLEEP BROWNOUT VBAT VBAT V3P3D HIGH HIGH-Z LOW V3P3D HIGH HIGH-Z LOW DIO DIO GNDD GNDD Not recommended Recommended Figure 16: Connecting an External Load to DIO Pins 2.5.10.2 Combined DIO and SEG Pins A total of 51 combined DIO/LCD pins are available. These pins can be categorized as follows: 39 combined DIO/LCD segment pins: o SEGDIO4...SEGDIO25 (22 pins) o SEGDIO28...SEGDIO35 (8 pins) o SEGDIO40...SEGDIO45 (6 pins) o SEGDIO52...SEGDIO54 (3 pins) 12 combined DIO/LCD segment pins shared with other functions: o SEGDIO0/WPULSE, SEGDIO1/VPULSE (2 pins) o SEGDIO2/SDCK, SEGDIO3/SDATA (2 pins) o SEGDIO26/COM5, SEGDIO27/COM4 (2 pins) o SEGDIO36/SPI_CSZ...SEGDIO39/SPI_CKI (4 pins) o SEGDIO51/OPT_TX, SEGDIO55/OPT_RX (2 pins) Additionally, 5 LCD segment (SEG) pins are available. These pins can be categorized as follows: o 3 SEG pins combined with the ICE interface (SEG48/E_RXTX, SEG49/E_TCLK, SEG50/E_RST) o 2 SEG pins combined with the test multiplexer outputs (SEG46/TMUX2OUT, SEG47/TMUXOUT) Thus, a total of 51 DIO pins are available with minimum LCD configuration, and a total of 56 LCD pins are available with minimum DIO configuration. Table 48: Data/Direction Registers and Internal Resources for SEGDIO0 to SEGDIO15 SEGDIO 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Pin # 45 44 43 42 41 39 38 37 36 35 34 33 32 31 30 29 Configuration: 0 = DIO, 1 = LCD SEG Data Register DIO Data Register Direction Register: 0 = input, 1 = output 60 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 LCD_MAP[7:0] (I/O RAM 0x240B) LCD_MAP[15:8] (I/O RAM 0x240A) 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 LCD_SEG0[5:0] to LCD_SEG15[5:0] (I/O RAM 0x2410[5:0] to 0x241F[5:0] 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 P0 (SFR80) P1 (SFR 0x90) P2 (SFR 0xA0) P3 (SFR 0xB0) 4 5 6 7 4 5 6 7 4 5 6 7 4 5 6 7 P0 (SFR 0x80) P1 (SFR 0x90) P2 (SFR 0xA0) P3 (SFR 0xB0) (c) 2008-2011 Teridian Semiconductor Corporation v1.2 71M6543F/H and 71M6543G/GH Data Sheet SEGDIO 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Pin # 45 44 43 42 41 39 38 37 36 35 34 33 32 31 30 29 Internal Resources Configurable (see Table 47) - - Y Y Y Y Y Y Y Y Y Y - - - - The configuration for pins SEGDIO16 to SEGDIO31 is shown in Table 49, and the configuration for pins SEGDIO32 to SEGDIO45 is shown in Table 50. The configuration for pins SEGDIO51 to SEGDIO55 is shown in Table 51. Table 49: Data/Direction Registers for SEGDIO16 to SEGDIO31 SEGDIO 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Pin # 28 27 25 24 23 22 21 20 19 18 17 16 11 10 9 8 Configuration: 0 = DIO, 1 = LCD 0 16 SEG Data Register 16 DIO Data Register 16 Direction Register: 0 = input, 1 = output 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 LCD_MAP[23:16] (I/O RAM 0x2409) LCD_MAP[31:24] (I/O RAM 0x2408) 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 LCD_SEGDIO16[5:0] to LCD_SEGDIO31[5:0] (I/O RAM 0x2420[5:0] to 0x242F[5:0]) 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 LCD_SEGDIO16[0] to LCD_SEGDIO31[0] (I/O RAM 0x2420[0] to 0x242F[0]) 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 LCD_SEGDIO16[1] to LCD_SEGDIO31[1] (I/O RAM 0x2420[1] to 0x242F[1]) Table 50: Data/Direction Registers for SEGDIO32 to SEGDIO45 SEGDIO 32 33 34 35 36 37 38 39 40 41 42 43 44 45 Pin # 7 6 5 4 3 2 1 100 99 98 97 96 95 94 0 1 5 32 33 32 33 32 33 2 3 4 5 6 7 0 1 2 3 4 LCD_MAP[39:32] LCD_MAP[45:40] (I/O RAM 0x2407) (I/O RAM 0x2406[5:0]) 34 35 36 37 38 39 40 41 42 43 44 LCD_SEGDIO32[5:0] to LCD_SEGDIO45[5:0] (I/O RAM 0x2430[5:0] to 0x243D[5:0]) 34 35 36 37 38 39 40 41 42 43 44 LCD_SEGDIO32[0] to LCD_SEGDIO45[0] (I/O RAM 0x2430[0] to 0x243D[0]) 34 35 36 37 38 39 40 41 42 43 44 LCD_SEGDIO32[1] to LCD_SEGDIO45[1] (I/O RAM 0x2430[1] to 0x243D[1]) Configuration: 0 = DIO, 1 = LCD SEG Data Register DIO Data Register Direction Register: 0 = input, 1 = output 45 45 45 Table 51: Data/Direction Registers for SEGDIO51 to SEGDIO55 SEGDIO Pin # Configuration: 0 = DIO, 1 = LCD SEG Data Register v1.2 51 53 52 52 53 51 3 4 5 51 52 54 47 55 46 - - - 6 7 - LCD_MAP[55:48] (I/O RAM 0x2405) 53 54 55 - - - - - (c) 2008-2011 Teridian Semiconductor Corporation 61 71M6543F/H and 71M6543G/GH Data Sheet DIO Data Register Direction Register: 0 = input, 1 = output LCD_SEGDIO51[5:0] to LCD_SEGDIO55[5:0] (I/O RAM 0x2443[5:0] to 0x2447[5:0]) 51 52 53 54 55 - - - LCD_SEGDIO51[0] to LCD_SEGDIO55[0] (I/O RAM 0x2443[0] to 0x2447[0]) 51 52 53 54 55 - - - LCD_SEGDIO51[1] to LCD_SEGDIO55[1] (I/O RAM 0x2443[1] to 0x2447[1]) 2.5.10.3 LCD Drivers The LCD drivers are grouped into up to six commons (COM0 - COM5) and up to 56 segment drivers. The LCD interface is flexible and can drive 7-segment digits, 14-segment digits or enunciator symbols. A voltage doubler and a contrast DAC generate VLCD from either VBAT or V3P3SYS, depending on the V3P3SYS voltage. The voltage doubler, while capable of driving into a 500 k load, is able to generate a maximum LCD voltage that is within 1 V of twice the supply voltage. The doubler and DAC operate from a trimmed low-power reference. The configuration of the VLCD generation is controlled by the I/O RAM field LCD_VMODE[1:0] (I/O RAM 0x2401[7:6]). It is decoded into LCD_EXT, LDAC_E, and LCD_BSTE. Table 52 details the LCD_VMODE[1:0] configurations. 62 (c) 2008-2011 Teridian Semiconductor Corporation v1.2 71M6543F/H and 71M6543G/GH Data Sheet Table 52: LCD_VMODE Configurations LCD_VMODE[1:0] LCD_EXT LDAC_E LCD_BSTE Description 11 1 0 0 External VLCD connected to the VLCD pin. LCD boost is enabled. Maximum VLCD voltage is 2*V3P3L-1. 10 0 1 1 VLCD = max(2*V3P3L-1, 2.65(1+LCD_DAC[4:0]/31) LCD boost is disabled. The maximum VLCD voltage is V3P3L. 01 0 1 0 VLCD = max(V3P3L, 2.65(1+LCD_DAC[4:0]/31) VLCD=V3P3L, the LCD DAC and LCD boost are disabled. In LCD mode, this setting causes the lowest 00 0 0 0 battery current. Notes: 1. LCD_EXT, LDAC_E and LCD_BSTE are 71M6543 internal signals which are decoded from the LCD_VMODE[1:0] control field setting (I/O RAM 0x2401[7:6]). Each of these decoded signals, when asserted, has the effect indicated in the description column above, and as summarized below. LCD_EXT : When set, the VLCD pin expects an external supply voltage LDAC_E : When set, LCD DAC is enabled LCD_BSTE : When set, the LCD boost circuit is enabled 2. V3P3L is an internal supply rail that is supplied from either the VBAT pin or the V3P3SYS pin, depending on the V3P3SYS pin voltage. When the V3P3SYS pin drops below 3.0 VDC, the 71M6543 switches to BRN mode and V3P3L is sourced from the VBAT pin, otherwise V3P3L is sourced from the V3P3SYS pin while in MSN mode. When using the VLCD boost circuit, use care when setting the LCD_DAC[4:0] (I/O RAM 0x240D[4:0]) value to ensure that the LCD manufacturer's recommended operating voltage specification is not exceeded. The voltage doubler is active in all LCD modes including the LCD mode when LCD_BSTE = 1. Current dissipation in LCD mode can be reduced if the boost circuit is disabled and the LCD system is operated directly from VBAT. The LCD DAC uses a low-power reference and, within the constraints of VBAT and the voltage doubler, generates a VLCD voltage of 2.65 VDC + 2.65 * LCD_DAC[4:0]/31. Two fuse bytes increase the accuracy of the LCD_DAC. LCDADJ12 and LCDADJ0 indicate the actual VLCD output voltage when the DAC is programmed to 12 and 0 respectively. The LCD_BAT (I/O RAM 0x2402[7]) bit causes the LCD system to use the battery voltage in all power modes. This may be useful when an external supply is available for the LCD system. The advantage of connecting the external supply to VBAT, rather than VLCD is that the LCD DAC is still active. If LCD_EXT = 1, the VLCD pin must be driven from an external source. In this case, the LCD DAC has no effect. The LCD system has the ability to drive up to six segments per SEG driver. If the display is configured with six back planes, the 6-way multiplexing reduces the number of SEG pins required to drive a display and therefore enhances the number of DIO pins available to the application. Refer to the LCD_MODE[2:0] field (I/O RAM 0x2400[6:4]) settings (Table 53) for the different LCD multiplexing choices. If 5-state multiplexing is selected, SEGDIO27 is converted to COM4. If 6-state multiplexing is selected, SEGDIO26 is converted to COM5. These conversions override the SEG/DIO mapping of SEGDIO26 and SEGDIO27. Additionally, independent of LCD_MODE[2:0], if LCD_ALLCOM = 1 (I/O RAM 0x2400[3]), then SEGDIO26 and SEGDIO27 become COM4 and COM5 if their LCD_MAP[ ] bits are set. The LCD_ON (I/O RAM 0x240C[0]) and LCD_BLANK (I/O RAM 0x240C[1]) bits are an easy way to either blank the LCD display or turn it fully on. Neither bit affects the contents of the LCD data stored in the LCDSEG_DIO[ ] registers. In comparison, LCD_RST (I/O RAM 0x240C[2]) clears all LCD data to zero. LCD_RST affects only pins that are configured as LCD. v1.2 (c) 2008-2011 Teridian Semiconductor Corporation 63 71M6543F/H and 71M6543G/GH Data Sheet A small amount of power can be saved by programming the LCD frequency to the lowest value that provides satisfactory LCD visibility over the required temperature range. Table 53 shows all I/O RAM registers that control the operation of the LCD interface. Table 53: LCD Configurations Name Location Rst Wk Dir LCD_ALLCOM 2400[3] 0 - R/W LCD_BAT 2402[7] 0 - R/W LCD_E 2400[7] 0 - R/W LCD_ON LCD_BLANK 240C[0] 240C[1] 0 0 - - R/W R/W LCD_RST 240C[2] 0 - R/W LCD_DAC[4:0] 240D[4:0] 0 - R/W LCD_CLK[1:0] 2400[1:0] 0 - R/W Description Configures all 6 SEG/COM pins as COM. Has no effect on pins whose LCD_MAP bit is zero. Connects the LCD power supply to VBAT in all modes. Enables the LCD display. When disabled, VLC2, VLC1, and VLC0 are ground as are the COM and SEG outputs if their LCD_MAP bit is 1. LCD_ON = 1 turns on all LCD segments without affecting the LCD data. Similarly, LCD_BLANK = 1 turns off all LCD segments without affecting the LCD data. If both bits are set, all LCD segments are turned on. Clear all bits of LCD data. These bits affect SEGDIO pins that are configured as LCD drivers. This register controls the LCD contrast DAC which adjusts the VLCD voltage and has an output range of 2.65 VDC to 5.3 VDC. The VLCD voltage is VLCD = 2.65 + 2.65 * LCD_DAC[4:0]/31 Thus, the LSB of the DAC is 85.5 mV. The maximum DAC output voltage is limited by V3P3SYS, VBAT, and whether LCD_BSTE is set. Sets the LCD clock frequency (1/T). See definition of T in Figure 17. Note: fw = 32768 Hz 00-fw/2^9, 01-fw/2^8, 10-fw/2^7, 11-fw/2^6 The LCD bias and multiplex mode. Output LCD_MODE 000 4 states, 1/3 bias 001 3 states, 1/3 bias LCD_MODE[2:0] 2400[6:4] 0 - R/W 010 2 states, 1/2 bias 011 3 states, 1/2 bias 100 Static display 101 5 states, 1/3 bias 110 6 states, 1/3 bias This register specifies how VLCD is generated. LCD_VMODE Description 11 External VLCD LCD boost and LCD DAC LCD_VMODE[1:0] 2401[7:6] 00 00 R/W 10 enabled 01 LCD DAC enabled No boost and no DAC. 00 VLCD = VBAT or V3P3SYS The LCD can be driven in static, 1/2 bias, and 1/3 bias modes. Figure 17 defines the COM waveforms. Note that COM pins that are not required in a specific mode maintain a segment off state rather than GND, VCC, or high impedance. The segment drivers SEGDIO22 and SEGDIO23 can be configured to blink at either 0.5 Hz or 1 Hz. The blink rate is controlled by LCD_Y (I/O RAM 0x2400[2]). There can be up to six pixels/segments connected to each of these driver pins. The I/O RAM fields LCD_BLKMAP22[5:0] (I/O RAM 0x2402[5:0]) and LCD_BLKMAP23[5:0] (I/O RAM 0x2401[5:0]) identify which pixels, if any, are to blink. LCD_BLKMAP22[5:0] and LCD_BLKMAP23[5:0] are non-volatile. 64 (c) 2008-2011 Teridian Semiconductor Corporation v1.2 71M6543F/H and 71M6543G/GH Data Sheet The LCD bias may be compensated for temperature using the LCD_DAC[4:0] field (I/O RAM 0x240D[4:0]). The bias may be adjusted from 1.4 V below the 3.3 V supply (V3P3SYS in MSN mode and VBAT in BRN and LCD modes). When the LCD_DAC[4:0] field is set to 000, the DAC is bypassed and powered down. This setting can be used to reduce current in LCD mode. STATIC (LCD_MODE=100) 1/2 BIAS, 2 STATES (LCD_MODE = 010 ) 0 1 COM0 COM0 1/2 BIAS, 3 STATES (LCD_MODE = 011 ) 0 1 2 COM0 COM1 (1/2) COM1 COM2 (1/2) COM2 (1/2) COM2 COM3 (1/2) COM3 (1/2) COM3 (1/2) COM4 (1/2) COM4 (1/2) COM4 (1/2) COM5 (1/2) COM5 (1/2) COM5 (1/2) SEG_ON SEG_ON SEG_OFF SEG_OFF COM1 SEG_ON SEG_OFF T 1/3 BIAS, 3 STATES (LCD_MODE = 011 ) 0 1 2 COM0 1/3 BIAS, 4 STATES (LCD_MODE = 000 ) 3 0 1 2 COM0 1/3 BIAS, 6 STATES (LCD_MODE = 110 ) 0 1 2 3 4 5 COM0 COM1 COM1 COM2 COM2 COM3 COM3 COM4 COM4 COM4 COM5 COM5 COM5 COM1 COM2 (2/3) (1/3) COM3 SEG_ON SEG_ON SEG_ON SEG_OFF SEG_OFF SEG_OFF Figure 17: LCD Waveforms SEG46 through SEG50 cannot be configured as DIO pins. Display data for these pins are written to I/O RAM registers LCD_SEG46[5:0] through LCD_SEG50[5:0] (see Table 54). Table 54: LCD Data Registers for SEGDIO46 to SEGDIO55 SEGDIO 46 47 48 49 50 51 52 53 54 55 Pin # 93 92 58 57 56 53 52 51 47 46 LCD_SEGDIO55[5:0] (I/O RAM 0x2447[5:0]) LCD_SEGDIO54[5:0] (I/O RAM 0x2446[5:0]) LCD_SEGDIO53[5:0] (I/O RAM 0x2445[5:0]) LCD_SEGDIO52[5:0] (I/O RAM 0x2444[5:0]) LCD_SEGDIO51[5:0] (I/O RAM 0x2443[5:0]) See 2.5.10.2 LCD_SEGDIO50[5:0] (I/O RAM 0x2442[5:0]) LCD_SEGDIO49[5:0] (I/O RAM 0x2441[5:0]) LCD_SEGDIO48[5:0] (I/O RAM 0x2440[5:0] LCD_SEGDIO47[5:0] (I/O RAM 0x243F[5:0]) SEG Data Register Always LCD pins LCD_SEGDIO46[5:0] (I/O RAM 0x243E[5:0] Configuration: The LCD_MAP[47:46] (I/O RAM 0x2406[7:6]) bits are used to determine whether SEG46 and SEG47 are SEG pins or their alternate function (see pins 93 and 92 in Figure 43). If the LCD_MAP[47:46] bits are 1, then the pins are configured as SEG pins. If the LCD_MAP[47:46] bits are 0, then the pins are configured as their alternate functions (TMUX2OUT and TMUXOUT, respectively). v1.2 (c) 2008-2011 Teridian Semiconductor Corporation 65 71M6543F/H and 71M6543G/GH Data Sheet For example, if LCD_MAP[46] = 1, then pin 93 (TMUX2OUT/SEG46) is configured as SEG46, and if LCD_MAP[46]=0, then pin 93 is configured as TMUX2OUT. The SEG pins with alternate ICE interface function (see pins 56-58 in Figure 43) are forced to their alternate ICE interface function (i.e., E_RXTX, E_TCLK and E_RST) if the ICE_E pin (pin 59) is driven high, and in this case, the bits LCD_MAP[50:48] (I/O RAM 0x2405[2:0]) bits are "don't care" bits. If the ICE_E pin is driven low, then LCD_MAP[50:48] bits must written with 1 in order to configure these pins as SEG pins. If the ICE_E pin is low and LCD_MAP[50:48] are written with 0, then these pins are tied to an internal pullup. 2.5.11 EEPROM Interface The 71M6543 provides hardware support for either a two-pin or a three-wire (-wire) type of EEPROM interface. The interfaces use the EECTRL (SFR 0x9F) and EEDATA (SFR 0x9E) registers for communication. 2.5.11.1 Two-pin EEPROM Interface The dedicated 2-pin serial interface communicates with external EEPROM devices. The interface is multiplexed onto the SEGDIO2 (SDCK) and SEGDIO3 (SDATA) pins and is selected by setting DIO_EEX[1:0] = 01 (I/O RAM 0x2456[7:6]). The MPU communicates with the interface through the SFR registers EEDATA and EECTRL. If the MPU wishes to write a byte of data to the EEPROM, it places the data in EEDATA and then writes the Transmit code to EECTRL. This initiates the transmit operation which is finished when the BUSY bit falls. INT5 is also asserted when BUSY falls. The MPU can then check the RX_ACK bit to see if the EEPROM acknowledged the transmission. A byte is read by writing the Receive command to EECTRL and waiting for the BUSY bit to fall. Upon completion, the received data is in EEDATA. The serial transmit and receive clock is 78 kHz during each transmission, and then holds in a high state until the next transmission. The EECTRL bits when the two-pin interface is selected are shown in Table 55. Table 55: EECTRL Bits for 2-pin Interface Status Bit Name Read/ Write Reset State Polarity Description 7 6 5 ERROR BUSY RX_ACK R R R 0 0 1 Positive Positive Positive 4 TX_ACK R 1 Positive 1 when an illegal command is received. 1 when serial data bus is busy. 1 indicates that the EEPROM sent an ACK bit. 1 indicates when an ACK bit has been sent to the EEPROM. CMD[3:0] 0000 0010 3:0 CMD[3:0] W 0000 Positive 0011 0101 0110 1001 Others Operation No-op command. Stops the I2C clock (SDCK). If not issued, SDCK keeps toggling. Receive a byte from the EEPROM and send ACK. Transmit a byte to the EEPROM. Issue a STOP sequence. Receive the last byte from the EEPROM and do not send ACK. Issue a START sequence. No operation, set the ERROR bit. The EEPROM interface can also be operated by controlling the DIO2 and DIO3 pins directly. The direction of the DIO line can be changed from input to output and an output value can be written with a single write operation, thus avoiding collisions (see Table 14 Port Registers (SEGDIO0-15)). Therefore, no resistor is required in series SDATA to protect against collisions. 66 (c) 2008-2011 Teridian Semiconductor Corporation v1.2 71M6543F/H and 71M6543G/GH Data Sheet 2.5.11.2 Three-Wire (-Wire) EEPROM Interface with Single Data Pin A 500 kHz three-wire interface, using SDATA, SDCK, and a DIO pin for CS is available. The interface is selected by setting DIO_EEX[1:0] = 10. The EECTRL bits when the three-wire interface is selected are shown in Table 56. When EECTRL is written, up to 8 bits from EEDATA are either written to the EEPROM or read from the EEPROM, depending on the values of the EECTRL bits. 2.5.11.3 Three-Wire (-Wire/SPI) EEPROM Interface with Separate Di/DO Pins If DIO_EEX[1:0] = 11, the 71M6543 three-wire interface is the same as above, except DI and DO are separate pins. In this case, SEGDIO3 becomes DO and SEGDIO8 becomes DI. The timing diagrams are the same as for DIO_EEX[1:0] = 10 except that all output data appears on DO and all input data is expected on DI. In this mode, DI is ignored while data is being received on DO. This mode is compatible with SPI modes 0,0 and 1,1 where data is shifted out on the falling edge of the clock and is strobed in on the rising edge of the clock. Table 56: EECTRL Bits for the 3-wire Interface Control Bit Name Read/ Write Description Wait for Ready. If this bit is set, the trailing edge of BUSY is delayed until a rising edge is seen on the data line. This bit can be used during the WFR last byte of a Write command to cause the INT5 interrupt to occur when 7 W the EEPROM has finished its internal write sequence. This bit is ignored if HiZ=0. Asserted while the serial data bus is busy. When the BUSY bit falls, an BUSY 6 R INT5 interrupt occurs. Indicates that the SD signal is to be floated to high impedance immediately HiZ 5 W after the last SDCK rising edge. RD Indicates that EEDATA (SFR 0x9E) is to be filled with data from EEPROM. 4 W Specifies the number of clocks to be issued. Allowed values are 0 through 8. If RD = 1, CNT bits of data are read MSB first, and right CNT[3:0] justified into the low order bits of EEDATA. If RD = 0, CNT bits are sent 3:0 W MSB first to the EEPROM, shifted out of the MSB of EEDATA. If CNT[3:0] is zero, SDATA simply obeys the HiZ bit. The timing diagrams in Figure 18 through Figure 22 describe the 3-wire EEPROM interface behavior. All commands begin when the EECTRL register is written. Transactions start by first raising the DIO pin that is connected to CS. Multiple 8-bit or less commands such as those shown in Figure 18 through Figure 22 are then sent via EECTRL and EEDATA. When the transaction is finished, CS must be lowered. At the end of a Read transaction, the EEPROM drives SDATA, but transitions to HiZ (high impedance) when CS falls. The firmware should then immediately issue a write command with CNT=0 and HiZ=0 to take control of SDATA and force it to a low-Z state. EECTRL Byte Written INT5 CNT Cycles (6 shown) Write -- No HiZ SCLK (output) SDATA (output) SDATA output Z D7 D6 D5 D4 D3 D2 (LoZ) BUSY (bit) Figure 18: 3-wire Interface. Write Command, HiZ=0. v1.2 (c) 2008-2011 Teridian Semiconductor Corporation 67 71M6543F/H and 71M6543G/GH Data Sheet EECTRL Byte Written INT5 CNT Cycles (6 shown) Write -- With HiZ SCLK (output) SDATA (output) D7 D6 D5 SDATA output Z D4 D3 D2 (LoZ) (HiZ) BUSY (bit) Figure 19: 3-wire Interface. Write Command, HiZ=1 EECTRL Byte Written INT5 CNT Cycles (8 shown) READ SCLK (output) SDATA (input) D7 D5 D6 SDATA output Z D4 D3 D2 D1 D0 (HiZ) BUSY (bit) Figure 20: 3-wire Interface. Read Command. EECTRL Byte Written INT5 not issued CNT Cycles (0 shown) Write -- No HiZ EECTRL Byte Written Write -- HiZ INT5 not issued CNT Cycles (0 shown) SCLK (output) SCLK (output) SDATA (output) SDATA (output) D7 SDATA output Z SDATA output Z (LoZ) (HiZ) BUSY (bit) BUSY (bit) Figure 21: 3-Wire Interface. Write Command when CNT=0 EECTRL Byte Written INT5 CNT Cycles (6 shown) Write -- With HiZ and WFR SCLK (output) SDATA (out/in) D7 D6 D5 D4 D3 D2 (From 6520) SDATA output Z (LoZ) BUSY READY (From EEPROM) (HiZ) BUSY (bit) Figure 22: 3-wire Interface. Write Command when HiZ=1 and WFR=1. 2.5.12 SPI Slave Port The slave SPI port communicates directly with the MPU data bus and is able to read and write Data RAM and Configuration RAM (I/O RAM) locations. It is also able to send commands to the MPU. The interface to the slave port consists of the SPI_CSZ, SPI_CKI, SPI_DI and SPI_DO pins. These pins are multiplexed with the combined DIO/LCD segment driver pins SEGDIO36 to SEGDIO39 (pins 3, 2, 1 and 100). Additionally, the SPI interface allows flash memory to be read and to be programmed. To facilitate flash programming, cycling power or asserting RESET causes the SPI port pins to default to SPI mode. The SPI port is disabled by clearing the SPI_E bit (I/O RAM 0x270C[4]). Possible applications for the SPI interface are: 68 (c) 2008-2011 Teridian Semiconductor Corporation v1.2 71M6543F/H and 71M6543G/GH Data Sheet 1) An external host reads data from CE locations to obtain metering information. This can be used in applications where the 71M6543 function as a smart front-end with preprocessing capability. Since the addresses are in 16-bit format, any type of XRAM data can be accessed: CE, MPU, I/O RAM, but not SFRs or the 80515-internal register bank. 2) A communication link can be established via the SPI interface: By writing into MPU memory locations, the external host can initiate and control processes in the 71M6543 MPU. Writing to a CE or MPU location normally generates an interrupt, a function that can be used to signal to the MPU that the byte that had just been written by the external host must be read and processed. Data can also be inserted by the external host without generating an interrupt. 3) An external DSP can access front-end data generated by the ADC. This mode of operation uses the 71M6543 as an analog front-end (AFE). 4) Flash programming by the external host (SPI Flash Mode). SPI Transactions A typical SPI transaction is as follows. While SPI_CSZ is high, the port is held in an initialized/reset state. During this state, SPI_DO is held in high impedance state and all transitions on SPI_CLK and SPI_DI are ignored. When SPI_CSZ falls, the port begins the transaction on the first rising edge of SPI_CLK. As shown in Table 57, a transaction consists of an optional 16 bit address, an 8 bit command, an 8 bit status byte, followed by one or more bytes of data. The transaction ends when SPI_CSZ is raised. Some transactions may consist of a command only. When SPI_CSZ rises, SPI command bytes that are not of the form x0000000 cause the SPI_CMD (SFR 0xFD) register to be updated and then cause an interrupt to be issued to the MPU. The exception is if the transaction was a single byte. In this case, the SPI_CMD byte is always updated and the interrupt issued. SPI_CMD is not cleared when SPI_CSZ is high. The SPI port supports data transfers up to 10 Mb/s. A serial read or write operation requires at least 8 clocks per byte, guaranteeing SPI access to the RAM is no faster than 1.25 MHz, thus ensuring that SPI access to DRAM is always possible. Table 57: SPI Transaction Fields Field Name Required Address Yes, except single byte transaction Size Description (bytes) 2 Command Yes 1 Status Yes, if transaction includes DATA 1 Data Yes, if transaction includes DATA 1 or more 16-bit address. The address field is not required if the transaction is a simple SPI command. 8-bit command. This byte can be used as a command to the MPU. In multi-byte transactions, the MSB is the R/W bit. Unless the transaction is multi-byte and SPI_CMD is exactly 0x80 or 0x00, the SPI_CMD register is updated and an SPI interrupt is issued. Otherwise, the SPI_CMD register is unchanged and the interrupt is not issued. 8-bit status field, indicating the status of the previous transaction. This byte is also available in the MPU memory map as SPI_STAT (I/O RAM 0x2708). See Table 59 for the contents. The read or write data. Address is auto incremented for each new byte. The SPI_STAT byte is output on every SPI transaction and indicates the parity of the previous transaction and the error status of the previous transaction. Potential error sources are: * * 71M6543 not ready Transaction not ending on a byte boundary. SPI Safe Mode v1.2 (c) 2008-2011 Teridian Semiconductor Corporation 69 71M6543F/H and 71M6543G/GH Data Sheet Sometimes it is desirable to prevent the SPI interface from writing to arbitrary RAM locations and thus disturbing MPU and CE operation. This is especially true in AFE applications. For this reason, the SPI SAFE mode was created. In SPI SAFE mode, SPI write operations are disabled except for a 16 byte transfer region at address 0x400 to 0x40F. If the SPI host needs to write to other addresses, it must use the SPI_CMD register to request the write operation from the MPU. SPI SAFE mode is enabled by the SPI_SAFE bit (I/O RAM 0x270C[3]). Single-Byte Transaction If a transaction is a single byte, the byte is interpreted as SPI_CMD. Regardless of the byte value, single-byte transactions always update the SPI_CMD register and cause an SPI interrupt to be generated. Multi-Byte Transaction As shown in Figure 23, multi-byte operations consist of a 16 bit address field, an 8 bit CMD, a status byte, and a sequence of data bytes. A multi byte transaction is three or more bytes. SERIAL READ 16 bit Address Status Byte 8 bit CMD DATA[ADDR] DATA[ADDR+1] Extended Read . . . (From Host) SPI_CSZ 0 15 16 A0 C7 23 31 24 32 39 40 D0 D7 47 (From Host) SPI_CK (From Host) SPI_DI A15 A14 A1 C6 C5 C0 HI Z (From 6543) SPI_DO SERIAL WRITE x ST7 16 bit Address ST6 ST5 ST0 D7 D6 DATA[ADDR] Status Byte 8 bit CMD D1 D6 D1 D0 DATA[ADDR+1] Extended Write . . . (From Host) SPI_CSZ 0 15 16 A0 C7 23 31 24 32 39 40 D0 D7 47 (From Host) SPI_CK (From Host) SPI_DI x A15 A14 A1 C6 C5 HI Z (From 6543) SPI_DO C0 D7 ST7 ST6 ST5 D6 D1 D6 D1 D0 x ST0 Figure 23: SPI Slave Port - Typical Multi-Byte Read and Write operations Table 58: SPI Command Sequences Command Sequence ADDR 1xxx xxxx STATUS Byte0 ... ByteN 0xxx xxxx ADDR Byte0 ... ByteN Description Read data starting at ADDR. ADDR is auto-incremented until SPI_CSZ is raised. Upon completion, SPI_CMD (SFR 0xFD) is updated to 1xxx xxxx and an SPI interrupt is generated. The exception is if the command byte is 1000 0000. In this case, no MPU interrupt is generated and SPI_CMD is not updated. Write data starting at ADDR. ADDR is auto-incremented until SPI_CSZ is raised. Upon completion, SPI_CMD is updated to 0xxx xxxx and an SPI interrupt is generated. The exception is if the command byte is 0000 0000. In this case, no MPU interrupt is generated and SPI_CMD is not updated. Table 59: SPI Registers Name EX_SPI SPI_CMD Location Rst Wk Dir Description 2701[7] SFR FD[7:0] 0 - 0 - R/W R SPI_E 270C[4] 1 1 R/W IE_SPI SFR F8[7] 0 0 R/W 270C[3] 0 0 R/W SPI interrupt enable bit. SPI command. The 8-bit command from the bus master. SPI port enable bit. It enables the SPI interface on pins SEGDIO36 - SEGDIO39. SPI interrupt flag. Set by hardware, cleared by writing a 0. Limits SPI writes to SPI_CMD and a 16 byte region in DRAM when set. No other write operations are permitted. SPI_SAFE 70 (c) 2008-2011 Teridian Semiconductor Corporation v1.2 71M6543F/H and 71M6543G/GH Data Sheet Name SPI_STAT Location 2708[7:0] Rst 0 Wk 0 Dir R Description SPI_STAT contains the status results from the previous SPI transaction Bit 7 - 71M6543 ready error: the 71M6543 was not ready to read or write as directed by the previous command. Bit 6 - Read data parity: This bit is the parity of all bytes read from the 71M6543 in the previous command. Does not include the SPI_STAT byte. Bit 5 - Write data parity: This bit is the overall parity of the bytes written to the 71M6543 in the previous command. It includes CMD and ADDR bytes. Bit 4:2 - Bottom 3 bits of the byte count. Does not include ADDR and CMD bytes. One, two, and three byte instructions return 111. Bit 1 - SPI FLASH mode: This bit is zero when the TEST pin is zero. Bit 0 - SPI FLASH mode ready: Used in SPI FLASH mode. Indicates that the flash is ready to receive another write instruction. SPI Flash Mode (SFM) In normal operation, the SPI slave interface cannot read or write the flash memory. However, the 71M6543 supports a special flash mode (SFM) which facilitates initial programming of the flash memory. When the 71M6543 is in this mode, the SPI can erase, read, and write the flash memory. Other memory elements such as XRAM and IO RAM are not accessible in this mode. In order to protect the flash contents, several operations are required before the SFM mode is successfully invoked. In SFM mode, the 71M6543 supports n byte reads and dual-byte writes to flash memory. See the SPI Transaction description on Page 69 for the format of read and write commands. Since the flash write operation is always based on a two-byte word, the initial address must always be even. Data is written to the 16-bit flash memory bus after the odd word is written. When the 71M6543G/GH is operating SFM, SPI single-byte transactions are used to write to FL_BANK[1:0] (SFR 0xB6[1:0]). During an SPI single-byte transaction, SPI_CMD[1:0] will over-write the contents of FL_BANK[1:0] (SFR 0xB6[1:0]). This will allow for access of the entire 128 KB flash memory while operating in SFM. In SFM mode, the MPU is completely halted. For this reason, the interrupt feature described in the SPI Transaction section above is not available in SFM mode. The 71M6543 must be reset by the WD timer or by the RESET pin in order to exit SFM mode. Invoking SFM The following conditions must be met prior to invoking SFM: * * * * * ICE_E = 1. This disables the watchdog and adds another layer of protection against inadvertent Flash corruption. The external power source (V3P3SYS, V3P3A) is at the proper level (> 3.0 VDC). PREBOOT = 0 (SFR 0xB2[7]). This validates the state of the SECURE bit (SFR 0xB2[6]). SECURE = 0. This I/O RAM register indicates that SPI secure mode is not enabled. Operations are limited to SFM Mass Erase mode if the SECURE bit = 1 (Flash read back is not allowed in Secure mode). FLSH_UNLOCK[3:0] = 0010 (I/O RAM 0x2702[7:4]). The I/O RAM registers SFMM (I/O RAM 0x2080) and SFMS (I/O RAM 0x2081) are used to invoke SFM. Only the SPI interface has access to these two registers. This eliminates an indirect path from the MPU for v1.2 (c) 2008-2011 Teridian Semiconductor Corporation 71 71M6543F/H and 71M6543G/GH Data Sheet disabling the watchdog. SFMM and SFMS need to be written to in sequence in order to invoke SFM. This sequential write process prevents inadvertent entering of SFM. The sequence for invoking SFM is: * First, write to SFMM (I/O RAM 0x2080) register. The value written to this register defines the SFM mode. o 0xD1: Mass Erase mode. A Flash Mass erase cycle is invoked upon entering SFM. o 0x2E: Flash Read back mode. SFM is entered for Flash read back purposes. Flash writes will not be blocked and it is up to the user to guarantee that only previously unwritten locations are written. This mode is not accessible when SPI secure mode is set. o SFM is not invoked if any other pattern is written to the SFMM register. * Next, write 0x96 to the SFMS (I/O RAM 0x2081) register. This write invokes SFM provided that the previous write operation to SFMM met the requirements. Writing any other pattern to this register does not invoke SFM. Additionally, any write operations to this register automatically reset the previously written SFMM register values to zero. SFM Details The following occurs upon entering SFM. * * * * * The CE is disabled. The MPU is halted. Once the MPU is halted it can only be restarted with a reset. This reset can be accomplished with the RESET pin, a watchdog reset, or by cycling power (without battery at the VBAT pin). The Flash control logic is reset in case the MPU was in the middle of a Flash write operation or Erase cycle. Mass erase is invoked if specified in the SFMM (I/O RAM 0x2080) register (see Invoking SFM, above). The SECURE bit (SFR 0xB2[6]) is cleared at the end of this and all Mass Erase cycles. All SPI read and write operations now refer to Flash instead of XRAM space. The SPI host can access the current state of the pending multi-cycle Flash access by performing a 4-byte SPI write of any address and checking the status field. All SPI write operations in SFM mode must be 6-byte write transactions that write two bytes to an even address. The write transactions must contain a command byte of 0x00 which is the form that does not create an MPU interrupt. Auto incrementing is disabled for write operations. SPI read transactions can make use of auto increment and may access single bytes. The command byte must always be 0x80 in SFM read transactions. SPI commands in SFM Interrupts are not generated in SFM since the MPU is halted. The format of the commands is shown in the SPI Transactions description on Page 69.SPI Transactions 2.5.13 Hardware Watchdog Timer An independent, robust, fixed-duration, watchdog timer (WDT) is included in the 71M6543. It uses the RTC crystal oscillator as its time base and must be refreshed by the MPU firmware at least every 1.5 seconds. When not refreshed on time, the WDT overflows and the part is reset as if the RESET pin were pulled high, except that the I/O RAM bits are in the same state as after a wake-up from SLP or LCD modes (see the I/O RAM description in 5.2 for a list of I/O RAM bit states after RESET and wake-up). Four thousand, one hundred CK32 cycles (or 125 ms) after the WDT overflow, the MPU is launched from program address 0x0000. The watchdog timer is also reset when the internal signal WAKE=0 (see 3.4 Wake-Up Behavior). The WDT is disabled when the ICE_E pin is pulled high. For details, see 3.3.4 Watchdog Timer (WDT) Reset. 72 (c) 2008-2011 Teridian Semiconductor Corporation v1.2 71M6543F/H and 71M6543G/GH Data Sheet 2.5.14 Test Ports (TMUXOUT and TMUX2OUT Pins) Two independent multiplexers allow the selection of internal analog and digital signals for the TMUXOUT and TMUX2OUT pins. These pins are multiplexed with the SEG47 and SEG46 function. In order to function as test pins, LCD_MAP[46] (I/O RAM 0x2406[6]) and LCD_MAP[47] (I/O RAM 0x2406[7]) must be 0. One of the digital or analog signals listed in Table 61 can be selected to be output on the TMUXOUT pin. The function of the multiplexer is controlled with the I/O RAM register TMUX[4:0] (I/O RAM 0x2502[4:0], as shown in Table 60. One of the digital or analog signals listed in Table 61 can be selected to be output on the TMUX2OUT pin. The function of the multiplexer is controlled with the I/O RAM register TMUX2[4:0] (I/O RAM 0x2503[4:0]), as shown in. The TMUX and TMUX2 I/O RAM locations are non-volatile and their contents are preserved by battery power and across resets. The TMUXOUT and TMUX2OUT pins may be used for diagnosis purposes or in production test. The RTC 1-second output may be used to calibrate the crystal oscillator. The RTC 4-second output provides even higher precision. Table 60: TMUX[4:0] Selections Signal Name Description 1 RTCLK 9 WD_RST A CKMPU D V3AOK bit E V3OK bit 32.768 kHz clock waveform Indicates when the MPU has reset the watchdog timer. Can be monitored to determine spare time in the watchdog timer. MPU clock - see Table 8 Indicates that the V3P3A pin voltage is 3.0 V. The V3P3A and V3P3SYS pins are expected to be tied together at the PCB level. The 71M6543 monitors the V3P3A pin voltage only. Indicates that the V3P3A pin voltage is 2.8 V. The V3P3A and V3P3SYS pins are expected to be tied together at the PCB level. The 71M654 monitors the V3P3A pin voltage only. 1B MUX_SYNC 1C 1D 1F CE_BUSY interrupt CE_XFER interrupt RTM output from CE TMUX[5:0] Internal multiplexer frame SYNC signal. See Figure 4 Figure 5. and See 2.3.3 on page 25 and Figure 12 on page 46 See 2.3.5 on page 26 Note: All TMUX[5:0] values which are not shown are reserved. v1.2 (c) 2008-2011 Teridian Semiconductor Corporation 73 71M6543F/H and 71M6543G/GH Data Sheet Table 61: TMUX2[4:0] Selections Signal Name Description 0 WD_OVF 1 PULSE_1S 2 PULSE_4S 3 RTCLK SPARE[1] bit - I/O RAM 0x2704[1] SPARE[2] bit - I/O RAM 0x2704[2] Indicates when the watchdog timer has expired (overflowed). One second pulse with 25% Duty Cycle. This signal can be used to measure the deviation of the RTC from an ideal 1 second interval. Multiple cycles should be averaged together to filter out jitter. Four second pulse with 25% Duty Cycle. This signal can be used to measure the deviation of the RTC from an ideal 4 second interval. Multiple cycles should be averaged together to filter out jitter. The 4 second pulse provides a more precise measurement than the 1 second pulse. 32.768 kHz clock waveform Copies the value of the bit stored in 0x2704[1]. For general purpose use. Copies the value of the bit stored in 0x2704[2]. For general purpose use. Indicates when a WAKE event has occurred. Internal multiplexer frame SYNC signal. See Figure 4 and Figure 5. See 2.5.3 on page 50. Digital GND. Use this signal to make the TMUX2OUT pin static. TMUX2[4:0] 8 9 A WAKE B MUX_SYNC C E 12 13 14 15 16 17 18 1F MCK GNDD INT0 - DIG I/O INT1 - DIG I/O INT2 - CE_PULSE INT3 - CE_BUSY INT4 - VSTAT INT5 - EEPROM/SPI INT6 - XFER, RTC RTM_CK (flash) Interrupt 0. See 2.4.9 on page 40. Also see Figure 12 on page 46. See 2.3.5 on page 26. Note: All TMUX2[4:0] values which are not shown are reserved. 74 (c) 2008-2011 Teridian Semiconductor Corporation v1.2 71M6543F/H and 71M6543G/GH Data Sheet 3 Functional Description 3.1 Theory of Operation The energy delivered by a power source into a load can be expressed as: t E = V (t ) I (t )dt 0 Assuming phase angles are constant, the following formulae apply: P = Real Energy [Wh] = V * A * cos * t S = Apparent Energy [VAh] = Q = Reactive Energy [VARh] = V * A * sin * t P2 + Q2 For a practical meter, not only voltage and current amplitudes, but also phase angles and harmonic content may change constantly. Thus, simple RMS measurements are inherently inaccurate. A modern solid-state electricity meter IC such as the Teridian 71M6543 functions by emulating the integral operation above, i.e. it processes current and voltage samples through an ADC at a constant frequency. As long as the ADC resolution is high enough and the sample frequency is beyond the harmonic range of interest, the current and voltage samples, multiplied with the time period of sampling yields an accurate quantity for the momentary energy. Summing-up the momentary energy quantities over time results in accumulated energy. 500 400 300 200 100 0 0 5 10 15 20 -100 -200 Current [A] -300 Voltage [V] Energy per Interval [Ws] -400 Accumulated Energy [Ws] -500 Figure 24: Voltage, Current, Momentary and Accumulated Energy Figure 24 shows the shapes of V(t), I(t), the momentary power and the accumulated power, resulting from 50 samples of the voltage and current signals over a period of 20 ms. The application of 240 VAC and 100 A results in an accumulation of 480 Ws (= 0.133 Wh) over the 20 ms period, as indicated by the accumulated power curve. The described sampling method works reliably, even in the presence of dynamic phase shift and harmonic distortion. 3.2 Battery Modes Shortly after system power (V3P3SYS) is applied, the 71M6543 is in mission mode (MSN mode). MSN mode means that the part is operating with system power and that the internal PLL is stable. This mode is the normal operating mode where the part is capable of measuring energy. v1.2 (c) 2008-2011 Teridian Semiconductor Corporation 75 71M6543F/H and 71M6543G/GH Data Sheet When system power is not available, the 71M6543 is in one of three battery modes: * * * BRN mode (brownout mode) LCD mode (LCD-only mode) SLP mode (sleep mode). An internal comparator monitors the voltage at the V3P3SYS pin (note that V3P3SYS and V3P3A are typically connected together at the PCB level). When the V3P3SYS dc voltage drops below 2.8 VDC, the comparator resets an internal power status bit called V3OK . As soon as system power is removed and V3OK = 0, the 71M6543 is forced to BRN mode. The MPU continues to execute code when the system transitions from MSN to BRN mode or from BRN to MSN mode. A soft reset should be executed when returning from BRN to MSN mode in order to re-initialize the I/O RAM. Depending on the MPU code, the MPU can choose to stay in BRN mode, or transition to LCD or to SLP mode (via the I/O RAM bits LCD_ONLY, I/O RAM 0x28B2[6] and SLEEP, I/O RAM 0x28B2[7]). BRN mode is similar to MSN mode except that resources powered by system power, such as the ADC and the CE, are not available (see Table 62), and that the supply current is drawn from the VBAT pin. In BRN mode, the PLL continues to function at the same frequency as in MSN mode. The MPU can configure BRN mode as it desires. For instance, it may choose to minimize battery power by reducing the PLL or MPU clock speed (see 3.2.1 BRN Mode, for the recommended settings to realize minimum power consumption in BRN mode). When system power is restored, the 71M6543 automatically transitions from any of the battery modes (BRN, LCD, SLP) back to MSN mode. Figure 25 shows a state diagram of the various operating modes, with the possible transitions between modes. When the part wakes-up under battery power, the part automatically enters BRN mode (see 3.4 Wake-Up Behavior). From BRN mode, the part may enter either LCD mode or SLP mode, as controlled by the MPU. RESET MSN V3P3SYS falls VSTAT=00X V3P3SYS rises System Power Battery Power VSTAT=001 V3P3SYS rises LCD_ONLY BRN V3P3SYS rises RESET & VBAT sufficient Wake Flags SLEEP or VBAT insufficient Wake event LCD Wake event VBAT insufficient VBAT insufficient RESET & VBAT insufficient SLP Figure 25: Operation Modes State Diagram 76 (c) 2008-2011 Teridian Semiconductor Corporation v1.2 71M6543F/H and 71M6543G/GH Data Sheet Transitions from both LCD and SLP mode to BRN mode can be initiated by the following events: * * * * Wake-up timer timeout. Pushbutton (PB) is activated. A rising edge on SEGDIO4, SEGDIO52 or SEGDIO55. Activity on the RX or OPT_RX pins. The MPU has access to a variety of registers that signal the event that caused the wake up. See 3.4 Wake-Up Behavior for details. Table 62 shows the circuit functions available in each operating mode. Table 62: Available Circuit Functions Circuit Function CE (Computation Engine) FIR ADC, VREF PLL Battery Measurement Temperature sensor Max MPU clock rate System Power MSN (Mission Mode) PLL_FAST=1 PLL_FAST=0 Yes Yes Yes Yes Yes Yes 4.92MHz (from PLL) Yes Yes Yes Yes Yes Yes Yes Yes Yes 38.4kHz Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 1.57MHz (from PLL) Yes Yes Yes Yes Yes Yes Yes Yes Yes 38.9kHz Yes Yes Yes Yes Yes Yes Yes Yes Battery Power BRN (Brownout Mode) LCD PLL_FAST=1 PLL_FAST=0 1 ---Yes Yes Yes 4.92MHz (from PLL) Yes Yes Yes Yes Yes Yes Yes Yes Yes 38.4kHz Yes Yes Yes Yes Yes Yes Yes Yes ---Yes Yes Yes 1.57MHz (from PLL) Yes Yes Yes Yes Yes Yes Yes Yes Yes 38.9kHz Yes Yes Yes Yes Yes Yes Yes Yes SLEEP ---2 Boost -Yes -----Yes -- -- MPU_DIV clk. divider --ICE --DIO Pins --Watchdog Timer --LCD Yes -LCD Boost Yes EEPROM Interface (2-wire) --EEPROM Interface (3-wire) --UART (full speed) --Optical TX modulation --Flash Read --Flash Page Erase --Flash Write --RAM Read and Write --Wakeup Timer Yes Yes OSC and RTC Yes Yes DRAM data preservation --NV RAM data preservation Yes Yes Notes: 1. "--" indicates that the corresponding circuit is not active 2. "Boost" implies that the LCD boost circuit is active (i.e., LCD_VMODE[1:0] = 10 (I/O RAM 0x2401[7:6])). The LCD boost circuit requires a clock from the PLL to function. Thus, the PLL is automatically kept active if LCD boost is active while in LCD mode, otherwise the PLL is de-activated. v1.2 (c) 2008-2011 Teridian Semiconductor Corporation 77 71M6543F/H and 71M6543G/GH Data Sheet 3.2.1 BRN Mode In BRN mode, most non-metering digital functions are active (as shown in Table 62) including ICE, UART, EEPROM, LCD and RTC. In BRN mode, the PLL continues to function at the same frequency as MSN mode. It is up to the MPU to scale down the PLL (using PLL_FAST, I/O RAM 0x2200[4]) or the MPU frequency (using MPU_DIV[2:0], I/O RAM 0x2200[2:0]) in order to save power. From BRN mode, the MPU can choose to enter LCD or SLP modes. When system power is restored while the 71M6543 is in BRN mode, the part automatically transitions to MSN mode. The recommended minimum power configuration for BRN mode is as follows: * * * * * * * * * * * * * * * * * * RCE0 = 0x00 (I/O RAM 0x2709[7:0]) - remote sensors disabled LCD_BAT = 1 (I/O RAM 0x2402[7]) - LCD powered from VBAT LCD_VMODE[1:0] = 0 (I/O RAM 0x2401[7:6]) - 5V LCD boost disabled CE6 = 0x00 (I/O RAM 0x2106) - CE, RTM and CHOP are disabled MUX_DIV[3:0] = 0(I/O RAM 0x2100[7:4]) - the ADC multiplexer is disabled ADC_E = 0 (I/O RAM 0x2704[4]) - ADC disabled VREF_CAL = 0 (I/O RAM 0x2704[7]) - Vref not driven out VREF_DIS = 1 (I/O RAM 0x2704[6]) - Vref disabled PRE_E = 0 (I/O RAM 0x2704[5] - pre-amp disabled BCURR = 0 (I/O RAM 0x2704[3]) - battery 100A current load OFF TMUX[5:0] = 0x0E (I/O RAM 0x2502[5:0]) - TMUXOUT output set to a dc value TMUX2[4:0] = 0x0E (I/O RAM 0x2503[4:0]) - TMUXOUT2 output set to a dc value CKGN = 0x24 (I/O RAM 0x2200) - PLL set slow, and MPU_DIV[2:0] (I/O RAM 0x2200[2:0]) set to maximum TEMP_PER[2:0] = 6 (I/O RAM 0x28A0[2:0]) - temp measurement set to automatic every 512 s TEMP_BSEL = 1 (I/O RAM 0x28A0[7]) - temperature sensor monitors VBAT PCON |= 1 (SFR 0x87) - at the end of the main BRN loop, halt the MPU and wait for an interrupt The baud rate registers are adjusted as needed All unused interrupts are disabled 3.2.2 LCD Mode LCD mode may be commanded by the MPU at any time by setting the LCD_ONLY control bit (I/O RAM 0x28B2[6]). However, it is recommended that the LCD_ONLY control bit be set by the MPU only after the 71M6543 has entered BRN mode. For example, if the 71M6543 is in MSN mode when LCD_ONLY is set, the duration of LCD mode is very brief and the 71M6543 immediately 'wakes'. In LCD mode, V3P3D is disabled, and the VBAT pin supplies the LCD current. Before asserting LCD_ONLY mode, it is recommended that the MPU minimize PLL current by reducing the output frequency of the PLL to 6.29 MHz (i.e., write PLL_FAST = 0, I/O RAM 0x2200[4]). The LCD boost system requires a clock from the PLL for its operation. Thus, if the LCD boost system is enabled (i.e., LCD_VMODE[1:0] = 10, I/O RAM 0x2401[7:6]), then the PLL is automatically kept active during LCD mode, otherwise the PLL is de-activated. In LCD mode, the data contained in the LCD_SEG registers is displayed using the segment driver pins. Up to two LCD segments connected to the pins SEGDIO22 and SEGDIO23 can be made to blink without the involvement of the MPU, which is disabled in LCD mode. To minimize battery power consumption, only segments that are used should be enabled. After the transition from LCD mode to MSN or BRN mode, the PC (Program Counter) is at 0x0000, the XRAM is in an undefined state, and configuration I/O RAM bits are reset (see Table 71 for I/O RAM state upon wake). The data stored in non-volatile I/O RAM locations is preserved in LCD mode (the shaded locations in Table 71 are non-volatile). 78 (c) 2008-2011 Teridian Semiconductor Corporation v1.2 71M6543F/H and 71M6543G/GH Data Sheet 3.2.3 SLP Mode The SLP mode may be commanded by the MPU whenever main system power is absent by asserting the SLEEP bit (I/O RAM 0x28B2[7]). The purpose of the SLP mode is to consume the least power while still maintaining the RTC, temperature compensation of the RTC, and the non-volatile portions of the I/O RAM. In SLP mode, the V3P3D pin is disconnected, removing all sources of leakage from VBAT and V3P3SYS. The non-volatile memory domain and the basic functions, such as temperature sensor, oscillator, and RTC, are powered by the VBAT_RTC input. In this mode, the I/O configuration bits, LCD configuration bits, and NV RAM values are preserved and RTC and oscillator continue to run. This mode can be exited only by system power-up or one of the wake methods described in 3.4 Wake-Up Behavior. If the SLEEP bit is asserted when V3P3SYS pin power is present (i.e., while in MSN mode), the 71M6543 enters SLP mode, resetting the internal WAKE signal, at which point the 71M6543 begins the standard wake from sleep procedures as described in 3.4 Wake-Up Behavior. After the transition from SLP mode to MSN or BRN mode the PC is at 0x0000, the XRAM is in an undefined state, and the I/O RAM is only partially preserved (see the description of I/O RAM states in 5.2). The non-volatile sections of the I/O RAM are preserved unless RESET goes high. v1.2 (c) 2008-2011 Teridian Semiconductor Corporation 79 71M6543F/H and 71M6543G/GH Data Sheet 3.3 Fault and Reset Behavior 3.3.1 Events at Power-Down Power fault detection is performed by internal comparators that monitor the voltage at the V3P3A pin and also monitor the internally generated VDD pin voltage (2.5 VDC). The V3P3SYS and V3P3A pins must be tied together at the PCB level, so that the comparators, which are internally connected only to the V3P3A pin, are able to simultaneously monitor the common V3P3SYS and V3P3A pin voltage. The following discussion assumes that the V3P3A and V3P3SYS pins are tied together at the PCB level. During a power failure, as V3P3A falls, two thresholds are detected: * The first threshold, at 3.0 VDC (VSTAT[2:0] = 001, SFR 0xF9[2:0]), warns the MPU that the analog modules are no longer accurate. Other than warning the MPU, the hardware takes no action when this threshold is crossed. This comparison produces an internal bit named V3OKA. The second threshold, at 2.8 VDC, causes the 71M6543 to switch to battery power. This switching happens while the FLASH and RAM systems are still able to read and write. This comparison produces an internal bit named V3OK. * The power quality is reflected by the VSTAT[2:0] register in I/O RAM space, as shown in Table 63. The VSTAT[2:0] register is located at SFR address F9 and occupies bits 2:0. The VSTAT[2:0] field can only be read. In addition to the state of the main power, the VSTAT[2:0] register provides information about the internal VDD voltage under battery power. Note that if system power (V3P3A) is above 2.8 VDC, the 71M6543 always switches from battery to system power. Table 63: VSTAT[2:0] (SFR 0xF9[2:0]) VSTAT[2:0] 000 001 010 011 101 Description System Power OK. V3P3A > 3.0 VDC. Analog modules are functional and accurate. System Power is low. 2.8 VDC < V3P3A < 3.0 VDC. Analog modules not accurate. Switch over to battery power is imminent. The IC is on battery power and VDD is OK. VDD > 2.25 VDC. The IC has full digital functionality. The IC is on battery power and 2.25 VDC > VDD > 2.0 VDC. Flash write operations are inhibited. The IC is on battery power and VDD < 2.0, which means that the MPU is nearly out of voltage. A reset occurs in 4 cycles of the crystal clock CK32. The response to a system power fault is almost entirely controlled by firmware. During a power failure, system power slowly falls. This fall in power is monitored by internal comparators that cause the hardware to automatically switch over to taking power from the VBAT input. An interrupt notifies the MPU that the part is now battery powered. At this point, it is the MPU's responsibility to reduce power by slowing the clock rate, disabling the PLL, etc. Precision analog components such as the bandgap reference, the bandgap buffer, and the ADC are powered only by the V3P3A pin and become inaccurate and ultimately unavailable as the V3P3A pin voltage continues to drop (i.e., circuits powered by the V3P3A pin are not backed by the VBAT pin). When the V3P3A pin falls below 2.8 VDC, the ADC clocks are halted and the amplifiers are unbiased. Meanwhile, control bits such as ADC_E bit (I/O RAM 0x2704[4]) are not affected, since their I/O RAM storage is powered from the VDD pin (2.5 VDC). The VDD pin is supplied with power through an internal 2.5 VDC regulator that is connected to the V3P3D pin. In turn, the V3P3D pin is switched to receive power from the VBAT pin when the V3P3SYS pin drops below 3.0 VDC. Note that the V3P3SYS and V3P3A pins are typically tied together at the PCB level. 80 (c) 2008-2011 Teridian Semiconductor Corporation v1.2 71M6543F/H and 71M6543G/GH Data Sheet 3.3.2 IC Behavior at Low Battery Voltage When system power is not present, the 71M6543 relies on the VBAT pin for power. If the VBAT voltage is not sufficient to maintain VDD at 2.0 VDC or greater, the MPU cannot operate reliably. Low VBAT voltage can occur while the part is operating in BRN mode, or while it is dormant in SLP or LCD mode. Two cases can be distinguished, depending on MPU code: * * Case 1: System power is not present, and the part is waking from SLP or LCD mode. In this case, the hardware checks the value of VDD to determine if processor operation is possible. If it is not possible, the part configures itself for BRN operation, and holds the processor in reset (WAKE=0). In this mode, VBAT powers the 1.0 VDC reference for the LCD system, the VDD regulator, the PLL, and the fault comparator. The part remains in this waiting mode until VDD becomes high due to system power being applied or the VBAT battery being replaced or recharged. Case 2: The part is operating under VBAT power and VSTAT[2:0] (SFR 0xF9[2:0]) becomes 101, indicating that VDD falls below 2.0 VDC. In this case, the firmware has two choices: 1) One choice is to assert the SLEEP bit (I/O RAM 0x28B2[7]) immediately. This assertion preserves the remaining charge in VBAT. Of course, if the battery voltage is not increased, the 71M6543 enters Case 1 as soon as it tries to wake up. 2) The alternative choice is to enter the waiting mode described in Case 1 immediately. Specifically, if the firmware does not assert the SLEEP bit, the hardware resets the processor four CE32 clock cycles (i.e. 122 s) after VSTAT[2:0] becomes 101 and, as described in Case 1, it begins waiting for VDD to become greater than 2.0 VDC. The MPU wakes up when system power returns, or when VDD becomes greater than 2.0 VDC. In either case, when VDD recovers, and when the MPU wakes up, the WF_BADVDD flag (I/O RAM 0x28B0[2]) can be read to determine that the processor is recovering from a bad VBAT condition. The WF_BADVDD flag remains set until the next time WAKE falls. This flag is independent of the other WF flags. In all cases, low VBAT voltage does not corrupt RTC operation, the state of NV memory, or the state of non-volatile memory. These circuits depend on the VBAT_RTC pin for power. 3.3.3 Reset Sequence When the RESET pin is pulled high, all digital activity in the chip stops, with the exception of the oscillator and RTC. Additionally, all I/O RAM bits are forced to their RST state. A reliable reset does not occur until RESET has been high at least for 2 s. Note that TMUX and the RTC are not reset unless the TEST pin is pulled high while RESET is high. The RESET control bit (I/O RAM 0x 2200[3]) performs an identical reset to the RESET pin except that a significantly shorter reset timer is used. Once initiated, the reset sequence waits until the reset timer times out. The time out occurs in 4100 CE32 cycles (125 ms), at which time the MPU begins executing its pre-boot and boot sequences from address 0x0000. See 2.5.1.1 for a detailed description of the pre-boot and boot sequences. If system power is not present, the reset timer duration is two CE32 cycles, at which time the MPU begins executing in BRN mode, starting at address 0x0000. A softer form of reset is initiated when the E_RST pin of the ICE interface is pulled low. This event causes the MPU and other registers in the MPU core to be reset but does not reset the remainder of the 71M6543. It does not trigger the reset sequence. This type of reset is intended to reset the MPU program, but not to make other changes to the chip's state. 3.3.4 Watchdog Timer (WDT) Reset The watchdog timer (WDT) is described in 2.5.13. A status bit, WF_OVF (I/O RAM 0x28B0[4]), is set when a WDT overflow occurs. Similar to the other wake flags, this bit is powered by the non-volatile supply and can be read by the MPU to determine if the part is initializing after a WD overflow event or after a power-up. The WF_OVF bit is cleared by the RESET pin. There is no internal digital state that could deactivate the WDT. For debug purposes, however, the WDT can be disabled by raising the ICE_E pin to 3.3 VDC. v1.2 (c) 2008-2011 Teridian Semiconductor Corporation 81 71M6543F/H and 71M6543G/GH Data Sheet In normal operation, the WDT is reset by periodically writing a one to the WD_RST control bit I/O RAM 0x28B4[7]). The watchdog timer is also reset when the 71M6543 wakes from LCD or SLP mode, and when ICE_E=1. 3.4 Wake-Up Behavior As described above, the part always wakes up in MSN mode when system power is restored. As stated in 3.2 Battery Modes, transitions from both LCD and SLP mode to BRN mode can be initiated by a wakeup timer timeout, when the pushbutton (PB) input is activated, a rising edge on SEGDIO4, SEGDIO52 or SEGDIO55, or by activity on the RX or OPT_RX pins. 3.4.1 Wake on Hardware Events The following pin signal events wake the 71M6543 from SLP or LCD mode: a high level on the PB pin, either edge on the RX pin, a rising edge on the SEGDIO4 pin, a high level on the SEGDIO52 pin, or a high level on the SEGDIO55 pin or either edge on the OPT_RX pin. See Table 64 for de-bounce details on each pin and for further details on the OPT_RX/SEGDIO55 pin. The SEGDIO4, SEGDIO52, and SEGDIO55 pins must be configured as DIO inputs and their wake enable (EW_x bits) must be set. In SLP and LCD modes, the MPU is held in reset and cannot poll pins or react to interrupts. When one of the hardware wake events occurs, the internal WAKE signal rises and within three CK32 cycles the MPU begins to execute. The MPU can determine which one of the pins awakened it by checking the WF_PB, WF_RX, WF_SEGDIO4, WF_DIO52, or WF_DIO55 flags (see Table 64). If the part is in SLP or LCD mode, it can be awakened by a high level on the PB pin. This pin is normally pulled to GND and can be connected externally so it may be pulled high by a push button depression. Some pins are de-bounced to reject EMI noise. Detection hardware ignores all transitions after the initial transition. Table 64 shows which pins are equipped with de-bounce circuitry. Pins that do not have de-bounce circuits must still be high for at least 2 s to be recognized. The wake enable and flag bits are shown in Table 64. The wake flag bits are set by hardware when the MPU wakes from a wake event. Note that the PB flag is set whenever the PB is pushed, even if the part is already awake. Table 66 lists the events that clear the WF flags. In addition to push buttons and timers, the part can also reboot due to the RESET pin, the RESET bit (I/O RAM 0x2200[3]), the WDT, the cold start detector, and E_RST. As seen in Table 64, each of these mechanisms has a flag bit to alert the MPU to the source of the wakeup. If the wakeup is caused by return of system power, there is no active WF flag and the VSTAT[2:0] field (SFR 0xF9[2:0]) indicates that system power is stable. Table 64: Wake Enable and Flag Bits Wake Enable Wake Flag De-bounce Description Name Location Name Location WAKE_ARM 28B2[5] WF_TMR 28B1[5] No Wake on Timer. EW_PB 28B3[3] WF_PB 28B1[3] Yes Wake on PB.* EW_RX 28B3[4] WF_RX 28B1[4] 2 s Wake on either edge of RX. EW_DIO4 28B3[2] WF_DIO4 28B1[2] 2 s Wake on SEGDIO4. EW_DIO52 28B3[1] WF_DIO52 28B1[1] Yes Wake on SEGDIO52.* WF_DIO55 28B1[0] Yes Always Enabled Always Enabled WF_RST WF_RSTBIT 28B0[6] 28B0[5] 2 s No Always Enabled WF_ERST 28B0[3] 2 s EW_DIO55 82 28B3[0] OPT_RXDIS = 1: Wake on DIO55 with 64 ms de-bounce.* OPT_RXDIS = 0: Wake on either edge of OPT_RX with 2 s de-bounce. OPT_RXDIS: I/O RAM 0x2457[2] Wake after RESET. Wake after RESET bit. Wake after E_RST. (ICE must be enabled) (c) 2008-2011 Teridian Semiconductor Corporation v1.2 71M6543F/H and 71M6543G/GH Data Sheet Wake Enable Name Location Always Enabled Wake Flag Name Location Description Wake after WD reset. Wake after cold start - the first Always Enabled WF_CSTART 28B0[7] No application of power. Wake after insufficient VBAT Always Enabled WF_BADVDD 28B0[2] No voltage. *This pin is sampled every 2 ms and must remain high for 64 ms to be declared a valid high level. This pin is highlevel sensitive. WF_OVF 28B0[4] De-bounce No Table 65: Wake Bits Name Location RST WK Dir EW_DIOR 28B3[2] 0 - R/W EW_DIO52 28B3[1] 0 - R/W EW_DIO55 28B3[0] 0 - R/W WAKE_ARM 28B2[5] 0 - R/W EW_PB 28B3[3] 0 - R/W EW_RX 28B3[4] 0 - R/W WF_DIO4 28B1[2] 0 - R WF_DIO52 28B1[1] 0 - R WF_DIO55 28B1[0] 0 - R WF_TMR WF_PB WF_RX WF_RST WF_RSTBIT WF_ERST WF_CSTART WF_BADVDD 28B1[5] 28B1[3] 28B1[4] 28B0[6] 28B0[5] 28B0[3] 28B0[7] 28B0[2] 0 0 0 * * * * * - - - R R R v1.2 - R Description Connects SEGDIO4 to the WAKE logic and permits SEGDIO4 rising to wake the part. This bit has no effect unless SEGDIO4 is configured as a digital input. Connects DIO52 to the WAKE logic and permits DIO52 high level to wake the part. This bit has no effect unless DIO52 is configured as a digital input. Connects DIO55 to the WAKE logic and permits DIO55 high level to wake the part. This bit has no effect unless DIO55 is configured as a digital input. Arms the WAKE timer and loads it with the value in WAKE_TMR (I/O RAM 0x2880) register. When SLP or LCD mode is asserted by the MPU, the WAKE timer becomes active. Connects the PB pin to the WAKE logic and permits PB high level to wake the part. PB is always configured as an input. Connects the RX pin to the WAKE logic and permits RX rising to wake the part. See 3.4.1 for de-bounce issues. SEGDIO4 flag bit. If SEGDIO4 is configured to wake the part, this bit is set whenever SEGDIO4 rises. It is held in reset if SEGDIO4 is not configured for wakeup. SEGDIO52 flag bit. If SEGDIO52 is configured to wake the part, this bit is set whenever SEGDIO52 is a high level. It is held in reset if SEGDIO52 is not configured for wakeup. SEGDIO55 flag bit. If SEGDIO55 is configured to wake the part, this bit is set whenever SEGDIO55 is a high level. It is held in reset if SEGDIO55 is not configured for wakeup. Indicates that the Wake timer caused the part to wake up. Indicates that the PB pin caused the part to wake. Indicates that RX pin caused the part to wake. Indicates that the RST pin, E_RST pin, RESET bit (I/O RAM 0x2200[3]), the cold start detector, or low voltage on the VBAT pin caused the part to reset. *See Table 66 for details. (c) 2008-2011 Teridian Semiconductor Corporation 83 71M6543F/H and 71M6543G/GH Data Sheet Table 66: Clear Events for WAKE flags Flag Wake on: Clear Events WF_TMR Timer expiration WAKE falls WF_PB PB pin high level WAKE falls WF_RX Either edge RX pin WAKE falls WF_DIO4 SEGDIO4 rising edge WAKE falls WF_DIO52 SEGDIO52 high level If OPT_RXDIS = 1 (I/O RAM 0x2457[2]), wake on SEGDIO55 high If OPT_RXDIS = 0 wake on either edge of OPT_RX WAKE falls RESET pin driven high WAKE falls, WF_CSTART, WF_RSTBIT, WF_OVF, WF_BADVDD RESET bit is set (I/O RAM 0x2200[3]) WAKE falls, WF_CSTART, WF_OVF, WF_BADVDD, WF_RST WF_DIO55 WF_RST WF_RSTBIT WF_ERST WF_OVF WF_CSTART E_RST pin driven high and the ICE interface must be enabled by driving the ICE_E pin high. Watchdog (WD) reset Cold-start (i.e., after the application of first power) WAKE falls WAKE falls, WF_CSTART, WF_RST, WF_OVF, WF_RSTBIT WAKE falls, WF_CSTART, WF_RSTBIT, WF_BADVDD, WF_RST WAKE falls, WF_RSTBIT, WF_OVF, WF_BADVDD, WF_RST Note: "WAKE falls" implies that the internal WAKE signal has been reset, which happens automatically upon entry into LCD mode or SLEEP mode (i.e., when the MPU sets the LCD_ONLY bit (I/O RAM 0x28B2[6]) or the SLEEP (I/O RAM 0x28B2[7]) bit). When the internal WAKE signal resets, all wake flags are reset. Since the various wake flags are automatically reset when WAKE falls, it is not necessary for the MPU to reset these flags before entering LCD mode or SLEEP mode. Also, other wake events can cause the wake flag to reset, as indicated above (e.g., the WF_RST flag can also be reset by any of the following flags setting: WF_CSTART, WS_RSTBIT, WF_OVF, WF_BADVDD) 3.4.2 Wake on Timer If the part is in SLP or LCD mode, it can be awakened by the Wake Timer. Until this timer times out, the MPU is in reset due to the internal WAKE signal being low. When the Wake Timer times out, WAKE rises and within three CK32 cycles, the MPU begins to execute. The MPU can determine that the timer woke it by checking the WF_TMR (I/O RAM 0x28B1[2]) wake flag. The Wake Timer begins timing when the part enters LCD or SLP mode. Its duration is controlled by the WAKE_TMR[7:0] register (I/O RAM 0x2880). The timer duration is WAKE_TMR[7:0] +1 seconds. The Wake Timer is armed by setting WAKE_ARM = 1 (I/O RAM 0x28B2[5]). It must be armed at least three RTC cycles before either SLP or LCD modes are initiated. Setting WAKE_ARM presets the timer with the value in WAKE_TMR and readies the timer to start when the MPU writes to the SLEEP (I/O RAM 0x28B2[7]) or LCD_ONLY (I/O RAM 0x28B2[6]) bits. The timer is neither reset nor disarmed when the MPU wakes-up. Thus, once armed and set, the MPU continues to be awakened WAKE_TMR[7:0] seconds after it requests SLP mode or LCD mode (i.e., once written, the WAKE_TMR[7:0] register holds its value and does not have to be re-written each time the MPU enters SLP or LCD mode. Also, since WAKE_TMR[7:0] is non-volatile, it also holds its value through resets and power failures). 3.5 Data Flow and MPU/CE Communication The data flow between the Compute Engine (CE) and the MPU is shown in Figure 26. In a typical application, the 32-bit CE sequentially processes the samples from the ADC inputs, performing calculations to measure 84 (c) 2008-2011 Teridian Semiconductor Corporation v1.2 71M6543F/H and 71M6543G/GH Data Sheet active power (Wh), reactive power (VARh), A2h, and V2h for four-quadrant metering. These measurements are then accessed by the MPU, processed further and output using the peripheral devices available to the MPU. Both the CE and multiplexer are controlled by the MPU via shared registers in the I/O RAM and in RAM. The CE outputs a total of six discrete signals to the MPU. These consist of four pulses and two interrupts: * * * * CE_BUSY XFER_BUSY WPULSE, VPULSE (pulses for active and reactive energy) XPULSE, YPULSE (auxiliary pulses) These interrupts are connected to the MPU interrupt service inputs as external interrupts. CE_BUSY indicates that the CE is actively processing data. This signal occurs once every multiplexer cycle (typically 396 s), and indicates that the CE has updated status information in its CESTATUS register (CE RAM 0x80). XFER_BUSY indicates that the CE is updating data to the output region of the RAM. This update occurs whenever the CE has finished generating a sum by completing an accumulation interval determined by SUM_SAMPS[12:0], I/O RAM 0x2107[4:0], 2108[7:0], (typically every 1000 ms). Interrupts to the MPU occur on the falling edges of the XFER_BUSY and CE_BUSY signals. WPULSE and VPULSE are typically used to signal energy accumulation of real (Wh) and reactive (VARh) energy. Tying WPULSE and VPULSE into the MPU interrupt system can support pulse counting. XPULSE and YPULSE can be used to signal events such as sags and zero crossings of the mains voltage to the MPU. Tying these outputs into the MPU interrupt system relieves the MPU from having to read the CESTATUS register at every occurrence of the CE_BUSY interrupt in order to detect sag or zero crossing events. Refer to 5.4 CE Interface Description on page 120 for additional information on setting up the device using the MPU firmware. Pulses XPULSE YPULSE Interrupts VPULSE WPULSE CE_BUSY XFER_BUSY CE Samples Processed Metering Data CESTATUS CECONFIG MUX Control MPU Control Control XRAM I/O RAM (Configuration RAM) Figure 26: MPU/CE Data Flow v1.2 (c) 2008-2011 Teridian Semiconductor Corporation 85 71M6543F/H and 71M6543G/GH Data Sheet 4 Application Information 4.1 Connecting 5 V Devices All digital input pins of the 71M6543 are compatible with external 5 V devices. I/O pins configured as inputs do not require current-limiting resistors when they are connected to external 5 V devices. 4.2 Directly Connected Sensors Figure 27 through Figure 30 show voltage-sensing resistive dividers, current-sensing current transformers (CTs) and current-sensing resistive shunts and how they are connected to the voltage and current inputs of the 71M6543. All input signals to the 71M6543 sensor inputs are voltage signals providing a scaled representation of either a sensed voltage or current. The analog input pins of the 71M6543 are designed for sensors with low source impedance. RC filters with resistance values higher than those implemented in the Teridian Demo Boards must not be used. Please refer to the Demo Board schematics for complete sensor input circuits and corresponding component values. VADCn (n = 8, 9 or 10) VIN ROUT V3P3A Figure 27: Resistive Voltage Divider (Voltage Sensing) IIN IOUT IADCn (n = 0,1,...7) CT RBURDEN VOUT V3P3A Noise Filter 1:N Figure 28. CT with Single-Ended Input Connection (Current Sensing) IIN IOUT IADCn (n = 0, 2, 4 or 6) V3P3A CT RBURDEN VOUT IADCn+1 Bias Network and Noise Filter 1:N Figure 29: CT with Differential Input Connection (Current Sensing) IIN IADCn (n = 2, 4 or 6) V3P3A RSHUNT VOUT IADCn+1 Bias Network and Noise Filter Figure 30: Differential Resistive Shunt Connections (Current Sensing) 86 (c) 2008-2011 Teridian Semiconductor Corporation v1.2 71M6543F/H and 71M6543G/GH Data Sheet 4.3 Systems Using 71M6xx3 Isolated Sensors and Current Shunts Figure 31 shows a typical connection for current shunt sensors; using the 71M6xx3 (polyphase) isolated sensors. Note that one shunt current sensor is connected without isolation, which is the neutral current sensor in this example (connected to pins IADC0-IADC1). Each 71M6xx3 device is electrically isolated by a low-cost pulse transformer. The 71M6543 current sensor inputs must be configured for remote sensor communications, as described in 2.2.8 71M6xx3 Isolated Sensor Interface (page 22). Flexible remapping using the I/O RAM registers MUXn_SEL[3:0] allows the sequence of analog input pins to be different from the standard configuration (a corresponding CE code must be used). See Figure 2 for the AFE configuration corresponding to Figure 31. C Shunt Current Sensors LOAD NEUTRAL B A POWER SUPPLY Resistor Dividers 71M6xx3 71M6xx3 71M6xx3 NEUTRAL Pulse Transformers Note: This system is referenced to Neutral 3x TERIDIAN 71M6xx3 MUX and ADC IADC0 IADC1 }IN* VADC10 (VC) IADC6 IADC7 }IC VADC9 (VB) IADC4 IADC5 }IB VADC8 (VA) IADC2 IADC3 }IA V3P3A V3P3SYS GNDA GNDD TERIDIAN 71M6543F/ 71M6543H/ 71M6543G/ 71M6543GH TEMPERATURE SENSOR VREF SERIAL PORTS AMR IR TX RAM COMPUTE ENGINE RX MODUL- RX ATOR TX FLASH MEMORY POWER FAULT COMPARATOR HOST MPU RTC TIMERS PWR MODE CONTROL WAKE-UP REGULATOR VBAT_RTC BATTERY MONITOR COM0...5 SEG SEG/DIO LCD DRIVER DIO, PULSES DIO V3P3D OSCILLATOR/ PLL XIN RTC BATTERY LCD DISPLAY 8888.8888 PULSES, DIO I2C or Wire EEPROM 32 kHz SPI INTERFACE ICE *IN = Neutral Current BATTERY VBAT XOUT 9/17/2010 Figure 31: System Using Three-Remotes and One-Local (Neutral) Sensor v1.2 (c) 2008-2011 Teridian Semiconductor Corporation 87 71M6543F/H and 71M6543G/GH Data Sheet 4.4 System Using Current Transformers Figure 32 shows a polyphase system using four current transformers to support optional Neutral current sensing for anti-tamper purposes. The Neutral current sensing CT can be omitted if Neutral current sensing is not required. The system is referenced to Neutral (i.e., the Neutral rail is tied to V3P3A and V3P3SYS). Current Transformers A LOAD NEUTRAL B C Note: This system is referenced to Neutral POWER SUPPLY NEUTRAL Resistor Dividers MUX and ADC IADC2 }IA IADC3 VADC8 (VA) IADC4 }IB IADC5 VADC9 (VB) IADC6 }IC IADC7 VADC10 (VC) IADC0 }IN* IADC1 VREF SERIAL PORTS AMR IR TX TERIDIAN 71M6543F/ 71M6543H/ 71M6543G/ 71M6543GH TEMPERATURE SENSOR RAM COMPUTE ENGINE RX MODUL- RX ATOR TX POWER FAULT COMPARATOR HOST V3P3A V3P3SYS GNDA GNDD FLASH MEMORY MPU RTC TIMERS PWR MODE CONTROL WAKE-UP REGULATOR BATTERY VBAT VBAT_RTC BATTERY MONITOR COM0...5 SEG SEG/DIO LCD DRIVER DIO, PULSES DIO V3P3D OSCILLATOR/ PLL XIN RTC BATTERY LCD DISPLAY 8888.8888 PULSES, DIO I2C or Wire EEPROM 32 kHz SPI INTERFACE ICE *IN = Optional Neutral Current XOUT 9/17/2010 Figure 32. System Using Current Transformers 88 (c) 2008-2011 Teridian Semiconductor Corporation v1.2 71M6543F/H and 71M6543G/GH Data Sheet 4.5 Metrology Temperature Compensation 4.5.1 Distinction Between Standard and High-Precision Parts Since the VREF band-gap amplifier is chopper-stabilized, as set by the CHOP_E[1:0] (I/O RAM 0x2106[3:2]) control field, the dc offset voltage, which is the most significant long-term drift mechanism in the voltage references (VREF), is automatically removed by the chopper circuit. Both the 71M6543 and the 71M6xx3 feature chopper circuits for their respective VREF voltage reference. Since the variation in the bandgap reference voltage (VREF) is the major contributor to measurement error across temperatures, Teridian implements a two step procedure to trim and characterize the VREF voltage reference during the device manufacturing process. The first step in the process is applied to both all parts (71M6543F, 71M6543H, 71M6543G, 71M6543GH). In this first step, the reference voltage (VREF) is trimmed to a target value of 1.195V. During this trimming process, the TRIMT[7:0] (I/O RAM 0x2309) value is stored in non-volatile fuses. TRIMT[7:0] is trimmed to a value that results in minimum VREF variation with temperature. For the 71M6543F and 71M6543G devices (0.5% energy accuracy), the TRIMT[7:0] value can be read by the MPU during initialization in order to calculate parabolic temperature compensation coefficients suitable for each individual 71M6543F and 71M6543G device. The resulting temperature coefficient for VREF in the 71M6543F and 71M6543G is 40 ppm/C. Considering the factory calibration temperature of VREF to be +22C and the industrial temperature range (-40C to +85C), the VREF error at the temperature extremes for the 71M6543F and 71M6543G devices can be calculated as: (85o C - 22 o C ) 40 ppm / oC = +2520 ppm = +0.252% and (-40 o C - 22 o C ) 40 ppm / oC = -2480 ppm = -0.248% The above calculation implies that both the voltage and the current measurements are individually subject to a theoretical maximum error of approximately 0.25%. When the voltage sample and current sample are multiplied together to obtain the energy per sample, the voltage error and current error combine resulting in approximately 0.5% maximum energy measurement error. However, this theoretical 0.5% error considers only the voltage reference (VREF) as an error source. In practice, other error sources exist in the system. The principal remaining error sources are the current sensors (shunts or CTs) and their corresponding signal conditioning circuits, and the resistor voltage divider used to measure the voltage. The 71M6543F and 71M6543G 0.5% grade devices should be used in Class 1% designs, to allow margin for the other error sources in the system. The 71M6543H and 71M6543GH devices (0.1% energy accuracy) goes through an additional process of characterization during production which makes it suitable to high-accuracy applications. The additional process is the characterization of the voltage reference (VREF) over temperature. The coefficients for the voltage reference are stored in additional non-volatile trim fuses. The MPU can read these trim fuses during initialization and calculate parabolic temperature compensation coefficients suitable for each individual 71M6543H and 71M6543GH device. The resulting temperature coefficient for VREF in the 71M6543H and 71M6543GH is 10 ppm/C. The VREF error at the temperature extremes for the 71M6543H and 71M6543GH devices can be calculated as: (85o C - 22 o C ) 10 ppm / oC = +630 ppm = +0.063% and (-40 o C - 22 o C ) 10 ppm / oC = -620 ppm = -0.062% When the voltage sample and current sample are multiplied together to obtain the energy per sample, the voltage error and current error combine resulting in approximately 0.126% maximum energy v1.2 (c) 2008-2011 Teridian Semiconductor Corporation 89 71M6543F/H and 71M6543G/GH Data Sheet measurement error. The 71M6543H and 71M6543GH 0.1% grade devices should be used in Class 0.2% and Class 0.5% designs, to allow margin for the other error sources in the system. The preceding discussion in this section also applies to the71M6603 (0.5%), 71M6113 (0.5%) and 71M6203 (0.1%) remote sensors. Refer to the 71M6xxx Data Sheet for details. 4.5.2 Temperature Coefficients for the 71M6543F and 71M6543G The equations provided below for calculating TC1 and TC2 apply to the 71M6543F and 71M6543G (0.5% energy accuracy). In order to obtain TC1 and TC2, the MPU reads TRIMT[7:0] (I/O RAM 0x2309) and uses the TC1 and TC2 equations provided. PPMC and PPMC2 are then calculated from TC1 and TC2, as shown. The resulting tracking of the reference voltage (VREF) is within 40 ppm/C, corresponding to a 0.5% energy measurement accuracy. See 4.5.1 Distinction Between Standard and High-Precision Parts. TC1( V / C ) = 275 - 4.95 TRIMT TC 2( V / C 2 ) = -0.557 + 0.00028 TRIMT PPMC = 22.4632 TC1 PPMC 2 = 1150.116 TC 2 See 4.5.5 and 4.5.6 below for further temperature compensation details. 4.5.3 Temperature Coefficients for the 71M6543H and 71M6543GH The 71M6543H and 71M6543GH undergo a two-pass factory trimming process which stores additional trim fuse values. The additional trim fuse values characterize the device's VREF behavior at various temperatures. The values for TC1 and TC2 are calculated from the values read from the TRIMT[7:0] (I/O RAM 0x2309), TRIMBGB[15:0] (Info Page 0x92 and 0x93) and TRIMBGD[7:0] (Info Page 0x94) nonvolatile on-chip fuses using the equations provided. The resulting tracking of the reference voltage is within 10 ppm/C, corresponding to a 0.126% energy measurement accuracy. The equations for deriving PPCM and PPMC2 from TC1 and TC2 are also provided. See 4.5.1 Distinction Between Standard and High-Precision Parts. TC1(V/)=35.091+0.01764TRIMT+1.587( - ) TC 2( V / C 2 ) = -0.557 - 0.00028 TRIMT PPMC = 22.4632 TC1 PPMC 2 = 1150.116 TC 2 TRIMT[7:0] trims the VREF voltage for minimum variation with temperature. The TRIMT[7:0] fuses are read by the MPU directly at I/O RAM address 0x2309[7:0]. During the second pass trim for the 71M6543H and 71M6543GH, VREF is further characterized at 85C and 22C, and the resulting fuse trim values are stored in TRIMBGB[15:0] and TRIMBGD[7:0], respectively. TRIMBGB[15:0] and TRIMBGD[7:0] cannot be read directly by the MPU. See 5.3 Reading the Info Page (71M6543H and 71M6543GH only) on page 118 for information on how to read the Info Page trim fuses. See 4.5.5 and 4.5.6 below for further temperature compensation details. 4.5.4 Temperature Coefficients for the 71M6xx3 Refer to the 71M6xxx Data sheet for the equations that are applicable to each 71M6xx3 part number and the corresponding temperature coefficients. 4.5.5 Temperature Compensation for VREF and Shunt Sensors This section discusses metrology temperature compensation for the meter designs where current shunt sensors are used in conjunction with Teridian's 71M6xx3 remote isolated sensors, as shown in Figure 31. Sensors that are directly connected to the 71M6543 are affected by the voltage variation in the 71M6543 VREF due to temperature. On the other hand, shunt sensors that are connected to 71M6xx3 remote sensor are affected by the VREF in the 71M6xx3. The VREF in both the 71M6543 and 71M6xx3 can be 90 (c) 2008-2011 Teridian Semiconductor Corporation v1.2 71M6543F/H and 71M6543G/GH Data Sheet compensated digitally using a second-order polynomial function of temperature. The 71M6543 and 71M6xx3 feature temperature sensors for the purposes of temperature compensating their corresponding VREF. The compensation computations must be implemented in MPU firmware. Referring to Figure 31, the VADC8 (VA), VADC9 (VB) and VADC10 (VC) voltage sensors are always directly connected to the 71M6543. Thus, the precision of the voltage sensors is primarily affected by VREF in the 71M6543. The temperature coefficient of the resistors used to implement the voltage dividers for the voltage sensors (see Figure 27) determine the behavior of the voltage division ratio with respect to temperature. It is recommended to use resistors with low temperature coefficients, while forming the entire voltage divider using resistors belonging to the same technology family, in order to minimize the temperature dependency of the voltage division ratio. The resistors must also have suitable voltage ratings. The 71M6543 also may have one local current shunt sensor that is connected directly to it via the IADC0IADC1 input pins, and therefore this local current sensor is also affected by the VREF in the 71M6543. The shunt current sensor resistance has a temperature dependency, which also may require compensation, depending on the required accuracy class. The IADC2-IADC3, IADC4-IADC5 and IADC6-IADC7 current sensors are isolated by the 71M6xx3 and depend on the VREF of the 71M6xx3, plus the variation of the corresponding remote shunt current sensor with temperature. The MPU has the responsibility of computing the necessary sample gain compensation values required for each sensor channel based on the sensed temperature. Teridian provides demonstration code that implements the GAIN_ADJx compensation equation shown below. The resulting GAIN_ADJx values are stored by the MPU in five CE RAM locations GAIN_ADJ0-GAIN_ADJ5 (CE RAM 0x40-0x44). The demonstration code thus provides a suitable implementation of temperature compensation, but other methods are possible in MPU firmware by utilizing the on-chip temperature sensors while storing the sample gain adjustment results in the CE RAM GAIN_ADJx storage locations for use by the CE. The demonstration code maintains five separate sets of PPMC and PPMC2 coefficients and computes five separate GAIN_ADJx values based on the sensed temperature using the equation below: GAIN _ ADJx = 16385 + 10 TEMP _ X PPMC 100 TEMP _ X 2 PPMC 2 + 214 2 23 The GAIN_ADJx values stored by the MPU in CE RAM are used by the CE to gain adjust (i.e., multiply) 14 the sample in each corresponding sensor channel. A GAIN_ADJx value of 16,384 (i.e., 2 )corresponds to unity gain, while values less than 16,384 attenuate the samples and values greater than 16,384 amplify the samples. In the above equation, TEMP_X is the deviation from nominal or calibration temperature expressed in multiples of 0.1 C. The 10x and 100x factors seen in the above equation are due to 0.1 oC scaling of TEMP_X. For example, if the calibration (reference) temperature is 22 oC and the measured temperature is 27 oC, then 10*TEMP_X = (27-22) x 10 = 50 (decimal), which represents a +5 oC deviation from 22oC. In the demonstration code, TEMP_X is calculated in the MPU from the STEMP[10:0] temperature sensor reading using the equation provided below and is scaled in 0.1C units. See 2.5.5 71M6543 Temperature Sensor on page 55 for the equation to calculate temperature in degrees C from the STEMP[10:0] value. Table 67 shows the five GAIN_ADJx equation output storage locations and the voltage or current sensor channels for which they compensate for the 1 Local / 3 Remote configuration shown in Figure 31. Table 67: GAIN_ADJn Compensation Channels (Figure 2, Figure 31, Table 1) v1.2 Gain Adjustment Output CE RAM Address GAIN_ADJ0 0x40 GAIN_ADJ1 0x41 GAIN_ADJ2 0x42 GAIN_ADJ3 0x43 Sensor Channel(s) (pin names) VADC8 (VA) VADC9 (VB) VADC10 (VC) IADC0-IADC1 IADC2-IADC3 IADC4-IADC5 Compensation For: VREF in 71M6543 and Voltage Divider Resistors VREF in 71M6543 and Shunt (Neutral Current) VREF in 71M6xx3 and Shunt (Phase A) VREF in 71M6xx3 and Shunt (Phase B) (c) 2008-2011 Teridian Semiconductor Corporation 91 71M6543F/H and 71M6543G/GH Data Sheet GAIN_ADJ4 0x44 IADC6-IADC7 VREF in 71M6xx3 and Shunt (Phase C) In the demonstration code, the shape of the temperature compensation second-order parabolic curve is determined by the values stored in the PPMC (1st order coefficient) and PPMC2 (2nd order coefficient), which are typically setup by the MPU at initialization time from values that are stored in EEPROM. To disable temperature compensation in the demonstration code, PPMC and PPMC2 are both set to zero for each of the five GAIN_ADJx channels. To enable temperature compensation, the PPMC and PPMC2 coefficients are set with values that match the expected temperature variation of the shunt current sensor (if required) and the corresponding VREF voltage reference (summed together). The shunt sensor requires a second order polynomial compensation which is determined by the PPMC and PPMC2 coefficients for the corresponding current measurement channel. The corresponding VREF voltage reference also requires the PPMC and PPMC2 coefficients to match the second order temperature behavior of the voltage reference. The PPMC and PPMC2 values associated with the shunt and with the corresponding VREF are summed together to obtain the compensation coefficients for a st nd given current-sensing channel (i.e., the 1 order PPMC coefficients are summed together, and the 2 order PPMC2 coefficients are summed together). In the 71M6543F and 71M6543G, the required VREF compensation coefficients PPMC and PPMC2 are calculated from readable on-chip non-volatile fuses (see 4.5.2 Temperature Coefficients for the 71M6543F). These coefficients are designed to achieve 40 ppm/C for VREF in the 71M6543F and 71M6543G. PPMC and PPMC2 coefficients are similarly calculated for the 71M6xx3 remote sensor (see 4.5.4 Temperature Coefficients for the 71M6xx3). For the 71M6543H and 71M6543GH (0.1% energy accuracy), coefficients specific to each individual device can be calculated from values read from additional on-chip fuses that characterize the VREF behavior of each individual part across industrial temperatures (see 4.5.3 Temperature Coefficients for the 71M6543H). The resulting tracking of the reference VREF voltage is within 10 ppm/C. For the current channels, to determine the PPMC and PPMC2 coefficients for the shunt current sensors, the designer must either know the average temperature curve of the shunt from its manufacturer's data sheet or obtain these coefficients by laboratory characterization of the shunt used in the design. 4.5.6 Temperature Compensation of VREF and Current Transformers This section discusses metrology temperature compensation for meter designs where Current Transformer (CT) sensors are used, as shown in Figure 32. Sensors that are directly connected to the 71M6543 are affected by the voltage variation in the 71M6543 VREF due to temperature. The VREF in the 71M6543 can be compensated digitally using a secondorder polynomial function of temperature. The 71M6543 features a temperature sensor for the purposes of temperature compensating its VREF. The compensation computations must be implemented in MPU firmware and written to the corresponding GAIN_ADJx CE RAM location. Referring to Figure 32, the VADC8 (VA), VADC9 (VB) and VADC10 (VC) voltage sensors are directly connected to the 71M6543. Thus, the precision of the voltage sensors is primarily affected by VREF in the 71M6543. The temperature coefficient of the resistors used to implement the voltage dividers for the voltage sensors (see Figure 27) determine the behavior of the voltage division ratio with respect to temperature. It is recommended to use resistors with low temperature coefficients, while forming the entire voltage divider using resistors belonging to the same technology family, in order to minimize the temperature dependency of the voltage division ratio. The resistors must also have suitable voltage ratings. The Current Transformers are directly connected to the 71M6543 and are therefore primarily affected by the VREF temperature dependency in the 71M6543. For best performance, it is recommended to use the differential signal conditioning circuit, as shown in Figure 29, to connect the CTs to the 71M6543. Current transformers may also require temperature compensation. The copper wire winding in the CT has dc resistance with a temperature coefficient, which makes the voltage delivered to the burden resistor temperature dependent, and the burden resistor also has a temperature coefficient. Thus, each CT sensor channel needs to compensate for the 71M6543 VREF, and optionally for the temperature dependency of the CT and its burden resistor depending on the required accuracy class. 92 (c) 2008-2011 Teridian Semiconductor Corporation v1.2 71M6543F/H and 71M6543G/GH Data Sheet The MPU has the responsibility of computing the necessary sample gain compensation values required for each sensor channel based on the sensed temperature. Teridian provides demonstration code that implements the GAIN_ADJx compensation equation shown below. The resulting GAIN_ADJx values are stored by the MPU in five CE RAM locations GAIN_ADJ0-GAIN_ADJ5 (CE RAM 0x40-0x44). The demonstration code thus provides a suitable implementation of temperature compensation, but other methods are possible in MPU firmware by utilizing the on-chip temperature sensor while storing the sample gain adjustment results in the CE RAM GAIN_ADJn storage locations. The demonstration code maintains five separate sets of PPMC and PPMC2 coefficients and computes five separate GAIN_ADJn values based on the sensed temperature using the equation below: GAIN _ ADJx = 16385 + 10 TEMP _ X PPMC 100 TEMP _ X 2 PPMC 2 + 214 2 23 The GAIN_ADJn values stored by the MPU in CE RAM are used by the CE to gain adjust (i.e., multiply) the sample in each corresponding sensor channel. A GAIN_ADJx value of 16,384 (i.e., 214)corresponds to unity gain, while values less than 16,384 attenuate the samples and values greater than 16,384 amplify the samples. In the above equation, TEMP_X is the deviation from nominal or calibration temperature expressed in multiples of 0.1 C. The 10x and 100x factors seen in the above equation are due to 0.1 oC scaling of TEMP_X. For example, if the calibration (reference) temperature is 22 C and the measured temperature is 27 C, then 10*TEMP_X = (27-22) x 10 = 50 (decimal), which represents a +5 C deviation from 22 C. In the demonstration code, TEMP_X is calculated in the MPU from the STEMP[10:0] temperature sensor reading using the equation provided below and is scaled in 0.1C units. See 2.5.5 71M6543 Temperature Sensor on page 55 for the equation to calculate temperature in C from the STEMP[10:0] reading. Table 68 shows the five GAIN_ADJx equation output storage locations and the voltage or current measurements for which they compensate. Table 68: GAIN_ADJx Compensation Channels (Figure 3, Figure 32, Table 2) Gain Adjustment Output CE RAM Address GAIN_ADJ0 0x40 GAIN_ADJ1 0x41 GAIN_ADJ2 0x42 GAIN_ADJ3 0x43 GAIN_ADJ4 0x44 Sensor Channel(s) (pin names) VADC8 (VA) VADC9 (VB) VADC10 (VC) IADC0-IADC1 Compensation For: VREF in 71M6543 and Voltage Divider Resistors VREF in 71M6543, CT and Burden Resistor (Neutral Current) IADC2-IADC3 VREF in 71M6543, CT and Burden Resistor (Phase A) IADC4-IADC5 VREF in 71M6543, CT and Burden Resistor (Phase B) IADC6-IADC7 VREF in 71M6543, CT and Burden Resistor (Phase C) In the demonstration code, the shape of the temperature compensation second-order parabolic curve is determined by the values stored in the PPMC (1st order coefficient) and PPMC2 (2nd order coefficient), which are typically setup by the MPU at initialization time from values that are stored in EEPROM. To disable temperature compensation in the demonstration code, PPMC and PPMC2 are both set to zero for each of the five GAIN_ADJx channels. To enable temperature compensation, the PPMC and PPMC2 coefficients are set with values that match the expected VREF temperature variation and optionally the corresponding sensor circuit (i.e., the CT and burden resistor for current channels or the resistor divider network for the voltage channels). In the 71M6543F and 71M6543G (0.5% energy accuracy), the required VREF compensation coefficients PPMC and PPMC2 are calculated from readable on-chip non-volatile fuses (see 4.5.2Temperature Coefficients for the 71M6543F). These coefficients are designed to achieve 40 ppm/C for VREF. For the 71M6543H and 71M6543GH (0.1% energy accuracy), coefficients specific to each individual device can be calculated from values read from additional on-chip fuses that characterize the VREF v1.2 (c) 2008-2011 Teridian Semiconductor Corporation 93 71M6543F/H and 71M6543G/GH Data Sheet behavior of each individual part across industrial temperatures (see 4.5.3 Temperature Coefficients for the 71M6543H). The resulting tracking of the reference VREF voltage is within 10 ppm/C. 4.6 Connecting I2C EEPROMs I2C EEPROMs or other I2C compatible devices should be connected to the DIO pins SEGDIO2 and SEGDIO3, as shown in Figure 33. Pullup resistors of roughly 10 k to V3P3D (to ensure operation in BRN mode) should be used for both SDCK and SDATA signals. The DIO_EEX (I/O RAM 0x2456[7:6]) field must be set to 01 in order to convert the DIO pins SEGDIO2 and SEGDIO3 to I2C pins SCL and SDATA. 10 k V3P3D 10 k EEPROM DIO2 SDCK DIO3 SDATA 71M6543 Figure 33: I2C EEPROM Connection 4.7 Connecting Three-Wire EEPROMs Wire EEPROMs and other compatible devices should be connected to the DIO pins SEGDIO2 and SEGDIO3, as described in 2.5.11 EEPROM Interface on page 66. 4.8 UART0 (TX/RX) The UART0 RX pin should be pulled down by a 10 k resistor and additionally protected by a 100 pF ceramic capacitor, as shown in Figure 34. 71M6543 RX TX 100 pF 10 k RX TX Figure 34: Connections for UART0 4.9 Optical Interface (UART1) The OPT_TX and OPT_RX pins can be used for a regular serial interface (by connecting a RS_232 transceiver for example), or they can be used to directly operate optical components (for example, an infrared diode and phototransistor implementing a FLAG interface). Figure 35 shows the basic connections 94 (c) 2008-2011 Teridian Semiconductor Corporation v1.2 71M6543F/H and 71M6543G/GH Data Sheet for UART1. The OPT_TX pin becomes active when the control field OPT_TXE (I/O RAM 0x2456[3:2]) is set to 00. The polarity of the OPT_TX and OPT_RX pins can be inverted with the configuration bits, OPT_TXINV (I/O RAM 0x2456[0]) and OPT_RXINV (I/O RAM 0x2457[1]), respectively. The OPT_TX output may be modulated at 38 kHz when system power is present. Modulation is not available in BRN mode. The OPT_TXMOD bit (I/O RAM 0x2456[1]) enables modulation. The duty cycle is controlled by OPT_FDC[1:0] (I/O RAM 0x2457[5:4]), which can select 50%, 25%, 12.5%, and 6.25% duty cycle. A 6.25% duty cycle means OPT_TX is low for 6.25% of the period. The OPT_RX pin uses digital signal thresholds. It may need an analog filter when receiving modulated optical signals. With modulation, an optical emitter can be operated at higher current than nominal, enabling it to increase the distance along the optical path. If operation in BRN mode is desired, the external components should be connected to V3P3D. However, it is recommended to limit the current to a few mA. V3P3SYS R1 71M6543 OPT_RX 100 pF 10 k Phototransistor V3P3SYS R2 LED OPT_TX Figure 35: Connection for Optical Components 4.10 Connecting the Reset Pin Even though a functional meter does not necessarily need a reset switch, it is useful to have a reset pushbutton for prototyping as shown in Figure 36, left side. The RESET signal may be sourced from V3P3SYS (functional in MSN mode only), V3P3D (MSN and BRN modes), or VBAT (all modes, if a battery is present), or from a combination of these sources, depending on the application. For a production meter, the RESET pin should be protected by the by the external components shown in Figure 36, right side. R1 should be in the range of 100 and mounted as closely as possible to the IC. Since the 71M6543 generates its own power-on reset, a reset button or circuitry, as shown in Figure 36, is only required for test units and prototypes. v1.2 (c) 2008-2011 Teridian Semiconductor Corporation 95 71M6543F/H and 71M6543G/GH Data Sheet VBAT/ V3P3D 71M6533 71M6543 71M6543 V3P3D R2 1k Reset Switch RESET RESET 100 R1 10k R1 0.1F DGND GNDD Figure 36: External Components for the RESET Pin: Push-Button (Left), Production Circuit (Right) 4.11 Connecting the Emulator Port Pins Even when the emulator is not used, small shunt capacitors to ground (22 pF) should be used for protection from EMI as illustrated in Figure 37. Production boards should have the ICE_E pin connected to ground. LCD Segments (optional) V3P3D 71M6543 ICE_E 62 E_RST 62 E_RXT E_TCLK 62 22 pF 22 pF 22 pF Figure 37: External Components for the Emulator Interface 4.12 Flash Programming 4.12.1 Flash Programming via the ICE Port Operational or test code can be programmed into the flash memory using either an in-circuit emulator or the Flash Programmer Module (TFP-2) available from Teridian. The flash programming procedure uses the E_RST, E_RXTX, and E_TCLK pins. 4.12.2 Flash Programming via the SPI Port It is possible to erase, read and program the flash memory of the 71M6543 via the SPI port. See 2.5.12 for a detailed description. 4.13 MPU Demonstration Code All application-specific MPU functions mentioned in 4 Application Information are featured in the demonstration C source code supplied by Teridian. The code is available as part of the Demonstration Kit for the 71M6543. The Demonstration Kits come with the 71M6543 preprogrammed with demonstration firmware and mounted on a functional sample meter Demo Board. The Demo Boards allow for quick and efficient evaluation of the IC without having to write firmware or having to supply an in-circuit emulator (ICE). 96 (c) 2008-2011 Teridian Semiconductor Corporation v1.2 71M6543F/H and 71M6543G/GH Data Sheet 4.14 Crystal Oscillator The oscillator of the 71M6543 drives a standard 32.768 kHz watch crystal. The oscillator has been designed specifically to handle these crystals and is compatible with their high impedance and limited power handling capability. The oscillator power dissipation is very low to maximize the lifetime of any battery backup device attached to the VBAT_RTC pin. Board layouts with minimum capacitance from XIN to XOUT require less battery current. Good layouts have XIN and XOUT shielded from each other and also keep the XIN and XOUT traces short and away from LCD and digital signals. Since the oscillator is self-biasing, an external resistor must not be connected across the crystal. 4.15 Meter Calibration Once the Teridian 71M6543 energy meter device has been installed in a meter system, it must be calibrated. A complete calibration includes the following: * * * Establishment of the reference temperature for factory calibration (e.g., typically 22 C). Calibration of the metrology section, i.e., calibration for errors of the current sensors, voltage dividers and signal conditioning components as well as of the internal reference voltage (VREF) at the reference temperature (e.g., typically 22 C). Calibration of the oscillator frequency using the RTCA_ADJ register (I/O RAM 0x2504). The metrology section can be calibrated using the gain and phase adjustment factors accessible to the CE. The gain adjustment is used to compensate for tolerances of components used for signal conditioning, especially the resistive components. Phase adjustment is provided to compensate for phase shifts introduced by the current sensors or by the effects of reactive power supplies. Due to the flexibility of the MPU firmware, any calibration method, such as calibration based on energy, or current and voltage can be implemented. It is also possible to implement segment-wise calibration (depending on current range). The 71M6543 supports common industry standard calibration techniques, such as single-point (energy-only), multi-point (energy, Vrms, Irms), and auto-calibration. Teridian provides a calibration spreadsheet file to facilitate the calibration process. Contact your Teridian representative to obtain a copy of the latest calibration spreadsheet file for the 71M6543. v1.2 (c) 2008-2011 Teridian Semiconductor Corporation 97 71M6543F/H and 71M6543G/GH Data Sheet 5 Firmware Interface 5.1 I/O RAM Map -Functional Order In Table 69 and Table 70, unimplemented (U) and reserved (R) bits are shaded in light gray. Unimplemented bits are identified with a `U'. Unimplemented bits have no memory storage, writing them has no effect, and reading them always returns zero. Reserved bits are identified with an `R', and must always be written with a zero. Writing values other than zero to reserved bits may have undesirable side effects and must be avoided. Non-volatile bits are shaded in dark gray. Non-volatile bits are backed-up during power failures if the system includes a battery connected to the VBAT pin. The I/O RAM locations listed in Table 69 have sequential addresses to facilitate reading by the MPU (e.g., in order to verify their contents). These I/O RAM locations are usually modified only at boot-up. The addresses shown in Table 69 are an alternative sequential address to the addresses from Table 70 which are used throughout this document. For instance, EQU[2:0] can be accessed at I/O RAM 0x2000[7:5] or at I/O RAM 0x2106[7:5]. Table 69: I/O RAM Map - Functional Order, Basic Configuration 98 Name Addr CE6 CE5 CE4 2000 2001 2002 CE3 2003 CE2 CE1 CE0 RCE0 RTMUX FOVRD MUX5 MUX4 MUX3 MUX2 MUX1 MUX0 TEMP LCD0 LCD1 2004 2005 2006 2007 2008 2009 200A 200B 200C 200D 200E 200F 2010 2011 2012 Bit 7 U Bit 6 EQU[2:0] U Bit 5 Bit 4 U Bit 3 Bit 2 CHOP_E[1:0] SUM_SAMPS[12:8] SUM_SAMPS[7:0] Bit 1 RTM_E Bit 0 CE_E CE_LCTN[6/5:0] PLS_MAXWIDTH[7:0] PLS_INTERVAL[7:0] DIFF0_E RFLY_DIS RMT4_E RMT2_E U U U DIFF6_E DIFF4_E DIFF2_E CHOPR[1:0] RMT6_E U TMUXR4[2:0] U U R MUX_DIV[3:0] MUX9_SEL MUX7_SEL MUX5_SEL MUX3_SEL MUX1_SEL TEMP_BSEL TEMP_PWR OSC_COMP TEMP_BAT LCD_E LCD_MODE[2:0] LCD_VMODE[1:0] FIR_LEN[1:0] PLS_INV TMUXR6[2:0] TMUXR2[2:0] U U U MUX10_SEL MUX8_SEL MUX6_SEL MUX4_SEL MUX2_SEL MUX0_SEL TBYTE_BUSY TEMP_PER[2:0] LCD_ALLCOM LCD_Y LCD_CLK[1:0] LCD_BLNKMAP23[5:0] (c) 2008-2011 Teridian Semiconductor Corporation v1.2 71M6543F/H and 71M6543G/GH Data Sheet Name Addr Bit 7 LCD_BAT Bit 6 R Bit 5 Bit 4 Bit 3 Bit 2 LCD_BLNKMAP22[5:0] LCD_MAP[55:48] LCD_MAP[47:40] LCD_MAP[39:32] LCD_MAP[31:24] LCD_MAP[23:16] LCD_MAP[15:8] LCD_MAP[7:0] U U U DIO_R11[2:0] U DIO_R9[2:0] U DIO_R7[2:0] U DIO_R5[2:0] U DIO_R3[2:0] U U U OPT_TXE[1:0] OPT_FDC[1:0] U OPT_RXDIS U U U U EX_YPULSE EX_RTCT U EX_RTC1M EX_VPULSE EW_RX EW_PB EW_DIO4 SFMM[7:0]* SFMS[7:0]* LCD2 2013 LCD_MAP6 2014 LCD_MAP5 2015 LCD_MAP4 2016 LCD_MAP3 2017 LCD_MAP2 2018 LCD_MAP1 2019 LCD_MAP0 201A U U DIO_R5 201B U DIO_R4 201C U DIO_R3 201D U DIO_R2 201E U DIO_R1 201F U DIO_R0 2020 DIO_EEX[1:0] DIO0 2021 DIO_PW DIO_PV DIO1 2022 DIO_PX DIO_PY DIO2 2023 EX_EEX EX_XPULSE INT1_E 2024 EX_SPI EX_WPULSE INT2_E 2025 WAKE_E 2026 SFMM 2080 SFMS 2081 Notes: *SFMM and SFMS are accessible only through the SPI slave port. See 2.5.1.1 Flash Memory for details. v1.2 (c) 2008-2011 Teridian Semiconductor Corporation Bit 1 Bit 0 DIO_RPB[2:0] DIO_R10[2:0] DIO_R8[2:0] DIO_R6[2:0] DIO_R4[2:0] DIO_R2[2:0] OPT_TXMOD OPT_RXINV U EX_RTC1S OPT_TXINV OPT_BB U EX_XFER EW_DIO52 EW_DIO55 99 71M6543F/H and 71M6543G/GH Data Sheet Table 70 lists bits and registers that may have to be accessed on a frequent basis. Reserved bits have lighter gray background, and non-volatile bits have a darker gray background. Table 70: I/O RAM Map - Functional Order Name Addr Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CE and ADC MUX_DIV[3:0] MUX10_SEL[3:0] MUX5 2100 MUX9_SEL[3:0] MUX8_SEL[3:0] MUX4 2101 MUX7_SEL[3:0] MUX6_SEL[3:0] MUX3 2102 MUX5_SEL[3:0] MUX4_SEL[3:0] MUX2 2103 MUX3_SEL[3:0] MUX2_SEL[3:0] MUX1 2104 MUX1_SEL[3:0] MUX0_SEL[3:0] MUX0 2105 EQU[2:0] U CHOP_E[1:0] RTM_E CE_E CE6 2106 U SUM_SAMPS[12:8] CE5 2107 SUM_SAMPS[7:0] CE4 2108 U CE_LCTN[6:0] (71M6543G/GH), CE_LCTN[5:0] (71M6543F/H) CE3 2109 PLS_MAXWIDTH[7:0] CE2 210A PLS_INTERVAL[7:0] CE1 210B DIFF6_E DIFF4_E DIFF2_E DIFF0_E RFLY_DIS FIR_LEN[1:0] PLS_INV CE0 210C U U U U U U RTM0[9:8] RTM0 210D RTM0[7:0] RTM0 210E RTM1[7:0] RTM1 210F RTM2[7:0] RTM2 2110 RTM3[7:0] RTM3 2111 CLOCK GENERATION U U ADC_DIV PLL_FAST RESET MPU_DIV[2:0] CKGN 2200 VREF TRIM FUSES TRIMT[7:0] TRIMT 2309 LCD/DIO LCD_E LCD_MODE[2:0] LCD_ALLCOM LCD_Y LCD_CLK[1:0] LCD0 2400 LCD_VMODE[1:0] LCD_BLNKMAP23[5:0] LCD1 2401 LCD_BAT R LCD_BLNKMAP22[5:0] LCD2 2402 LCD_MAP[55:48] LCD_MAP6 2405 LCD_MAP[47:40] LCD_MAP5 2406 LCD_MAP[39:32] LCD_MAP4 2407 LCD_MAP[31:24] LCD_MAP3 2408 100 (c) 2008-2011 Teridian Semiconductor Corporation v1.2 71M6543F/H and 71M6543G/GH Data Sheet Name LCD_MAP2 LCD_MAP1 LCD_MAP0 LCD4 LCD_DAC SEGDIO0 ... SEGDIO15 SEGDIO16 ... SEGDIO45 SEGDIO46 ... SEGDIO50 SEGDIO51 ... SEGDIO55 Addr 2409 240A 240B 240C 240D 2410 ... 241F 2420 ... 243D 243E ... 2442 2443 ... 2447 DIO_R5 2450 DIO_R4 2451 DIO_R3 2452 DIO_R2 2453 DIO_R1 2454 DIO_R0 2455 DIO0 2456 DIO1 2457 DIO2 2458 NV BITS SPARENV 2500 FOVRD 2501 TMUX 2502 TMUX2 2503 RTC1 2504 71M6xx3 Interface v1.2 Bit 7 Bit 6 Bit 5 U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U R U U U U U DIO_EEX[1:0] DIO_PW DIO_PV DIO_PX DIO_PY U U U U U U U U U Bit 4 Bit 3 LCD_MAP[23:16] LCD_MAP[15:8] LCD_MAP[7:0] U U U Bit 1 LCD_RST LCD_BLANK LCD_DAC[4:0] LCD_SEG0[5:0] ... LCD_SEG15[5:0] LCD_SEGDIO16[5:0] ... LCD_SEGDIO45[5:0] LCD_SEG46[5:0] ... LCD_SEG50[5:0] LCD_SEGDIO51[5:0] ... LCD_SEGDIO55[5:0] R R DIO_R11[2:0] DIO_R9[2:0] DIO_R7[2:0] DIO_R5[2:0] DIO_R3[2:0] U U OPT_FDC[1:0] U U U R Bit 2 U U U U U U U U OPT_TXE[1:0] U OPT_RXDIS U U Bit 0 LCD_ON DIO_RPB[2:0] DIO_R10[2:0] DIO_R8[2:0] DIO_R6[2:0] DIO_R4[2:0] DIO_R2[2:0] OPT_TXMOD OPT_RXINV U OPT_TXINV OPT_BB U U U R U U TMUX[5:0] TMUX2[4:0] RTCA_ADJ[6:0] (c) 2008-2011 Teridian Semiconductor Corporation 101 71M6543F/H and 71M6543G/GH Data Sheet Name Addr REMOTE2 2602 REMOTE1 2603 RBITS INT1_E 2700 INT2_E 2701 SECURE 2702 Analog0 2704 VERSION 2706 INTBITS 2707 FLAG0 SFR E8 FLAG1 SFR F8 STAT SFR F9 REMOTE0 SFR FC SPI1 SFR FD SPI0 2708 RCE0 2709 RTMUX 270A INFO_PG 270B DIO3 270C NV RAM and RTC 2800NVRAMxx 287F WAKE 2880 STEMP1 2881 STEMP0 2882 BSENSE 2885 LKPADDR 2887 LKPDATA 2888 LKPCTRL 2889 RTC0 2890 RTC2 2892 RTC3 2893 RTC4 2894 102 Bit 7 EX_EEX EX_SPI VREF_CAL U IE_EEX IE_SPI U U Bit 6 Bit 5 EX_XPULSE EX_YPULSE EX_WPULSE EX_VPULSE FLSH_UNLOCK[3:0] VREF_DIS PRE_E INT6 IE_XPULSE IE_WPULSE U PERR_RD CHOPR[1:0] U U U Bit 4 Bit 3 RMT_RD[15:8] RMT_RD[7:0] INT5 IE_YPULSE IE_VPULSE U PERR_WR RMT6_E TMUXR4[2:0] U PORT_E U U EX_RTCT U U U R ADC_E BCURR VERSION[7:0] INT4 INT3 IE_RTCT U U U PLL_OK U Bit 2 Bit 1 Bit 0 EX_RTC1M U FLSH_RDE EX_RTC1S U FLSH_WRE SPARE[2:0] EX_XFER U R INT2 IE_RTC1M U INT1 IE_RTC1S U VSTAT[2:0] INT0 IE_XFER PB_STATE RCMD[4:0] SPI_CMD[7:0] SPI_STAT[7:0] RMT4_E RMT2_E U U U SPI_E SPI_SAFE U U TMUXR6[2:0] TMUXR2[2:0] U U INFO_PG U U U LKP_RD U LKP_WR U NVRAM[0] - NVRAM[7F] - Direct Access STEMP[2:0] LKPAUTOI U RTC_WR U RTC_RD U U U U U U WAKE_TMR[7:0] STEMP[10:3] U U U BSENSE[7:0] LKPADDR[6:0] LKPDAT[7:0] U U U RTC_FAIL U U RTC_SBSC[7:0] RTC_SEC[5:0] RTC_MIN[5:0] (c) 2008-2011 Teridian Semiconductor Corporation v1.2 71M6543F/H and 71M6543G/GH Data Sheet Name Addr Bit 7 U U U U RTC5 2895 RTC6 2896 RTC7 2897 RTC8 2898 RTC9 2899 U RTC10 289B RTC11 289C RTC12 289D U RTC13 289E U RTC14 289F TEMP 28A0 TEMP_BSEL WF1 28B0 WF_CSTART U WF2 28B1 SLEEP MISC 28B2 U WAKE_E 28B3 WD_RST WDRST 28B4 MPU PORTS PORT3 SFR B0 PORT2 SFR A0 PORT1 SFR 90 PORT0 SFR 80 FLASH ERASE SFR 94 FLSHCTL SFR B2 PREBOOT U FL_BANK SFR B6 PGADR SFR B7 I2C EEDATA SFR 9E EECTRL SFR 9F v1.2 Bit 6 U U U U Bit 5 U U U U Bit 4 Bit 3 U U U U U Bit 2 RTC_HR[4:0] Bit 1 Bit 0 RTC_DAY[2:0] RTC_DATE[4:0] RTC_MO[3:0] U RTC_YR[7:0] U RTC_P[16:14] RTC_P[13:6] RTC_P[5:0] U U TEMP_PWR WF_RST U LCD_ONLY U TEMP_START U OSC_COMP WF_RSTBIT WF_TMR WAKE_ARM U U RTC_Q[1:0] TEMP_BAT WF_OVF WF_RX U EW_RX U RTC_TMIN[5:0] RTC_THR[4:0] TBYTE_BUSY TEMP_PER[2:0] WF_ERST WF_BADVDD U U WF_PB WF_DIO4 WF_DIO52 WF_DIO55 U U U U EW_PB EW_DIO4 EW_DIO52 EW_DIO55 U U U U DIO_DIR[15:12] DIO_DIR[11:8] DIO_DIR[7:4] DIO_DIR[3:0] SECURE U DIO[15:12] DIO[11:8] DIO[7:4] DIO[3:0] FLSH_ERASE[7:0] U U FLSH_PEND U U U FLSH_PGADR[5:0] FLSH_PSTWR U FLSH_MEEN FLSH_PWE FL_BANK[1:0] U U EEDATA[7:0] EECTRL[7:0] (c) 2008-2011 Teridian Semiconductor Corporation 103 71M6543F/H and 71M6543G/GH Data Sheet 5.2 I/O RAM Map - Alphabetical Order Table 71 lists I/O RAM bits and registers in alphabetical order. Bits with a write direction (W in column Dir) are written by the MPU into configuration RAM. Typically, they are initially stored in flash memory and copied to the configuration RAM by the MPU. Some of the more frequently programmed bits are mapped to the MPU SFR memory space. The remaining bits are mapped to the address space 0x2XXX. Bits with R (read) direction can be read by the MPU. Columns labeled Rst and Wk describe the bit values upon reset and wake, respectively. No entry in one of these columns means the bit is either read-only or is powered by the NV supply and is not initialized. Write-only bits return zero when they are read. Locations that are shaded in grey are non-volatile (i.e., battery-backed). Table 71: I/O RAM Map - Alphabetical Order Name ADC_E Location Rst Wk Dir 2704[4] 0 0 R/W ADC_DIV 2200[5] 0 0 R/W BCURR 2704[3] 0 0 R/W 2885[7:0] - - R 2106[0] 0 0 R/W BSENSE[7:0] CE_E CE_LCTN[6:0] 2109[6:0] 31 31 R/W CHIP_ID[15:8] CHIP_ID[7:0] 2300[7:0] 2301[7:0] 0 0 104 0 0 R R Description Enables ADC and VREF. When disabled, reduces bias current. ADC_DIV controls the rate of the ADC and FIR clocks. The ADC_DIV setting determines whether MCK is divided by 4 or 8: 0 = MCK/4 1 = MCK/8 The resulting ADC and FIR clock is as shown below. PLL_FAST = 0 PLL_FAST = 1 MCK 6.291456 MHz 19.660800 MHz ADC_DIV = 0 1.572864 MHz 4.9152 MHz ADC_DIV = 1 0.786432 MHz 2.4576 MHz Connects a 100 A load to the battery selected by TEMP_BSEL. The result of the battery measurement. See 2.5.7 71M6543 Battery Monitor on page 57. CE enable. CE program location. The starting address for the CE program is 1024*CE_LCTN. (CE_LCTN[6:0], 2109[6:0] for 71M6543G, 71M6543GH) (CE_LCTN[5:0], 2109[5:0] for 71M6543F, 71M6543H) These bytes contain the chip identification as shown below. CHIP_ID[15:8] CHIP_ID[7:0] 71M6543F 0x04 0x10 71M6543H 0x04 0x11 71M6543G 0x05 0x10 71M6543GH 0x05 0x11 (c) 2008-2011 Teridian Semiconductor Corporation v1.2 71M6543F/H and 71M6543G/GH Data Sheet Name Location Rst Wk Dir CHOP_E[1:0] 2106[3:2] 0 CHOPR[1:0] 2709[7:6] 00 00 R/W 0 R/W 210C[4] 210C[5] 210C[6] 210C[7] 0 0 0 0 0 0 0 0 R/W R/W R/W R/W 2455[2:0] 2455[6:4] 2454[2:0] 2454[6:4] 2453[2:0] 2453[6:4] 2452[2:0] 2452[6:4] 2451[2:0] 2451[6:4] 2450[2:0] 0 0 0 0 0 0 0 0 0 0 0 - R/W DIO_DIR[15:12] DIO_DIR[11:8] DIO_DIR[7:4] DIO_DIR[3:0] SFR B0[7:4] SFR A0[7:4] F SFR 90[7:4] SFR 80[7:4] F R/W DIO[15:12] DIO[11:8] DIO[7:4] DIO[3:0] SFR B0[3:0] SFR A0[3:0] F SFR 90[3:0] SFR 80[3:0] F R/W DIFF0_E DIFF2_E DIFF4_E DIFF6_E DIO_R2[2:0] DIO_R3[2:0] DIO_R4[2:0] DIO_R5[2:0] DIO_R6[2:0] DIO_R7[2:0] DIO_R8[2:0] DIO_R9[2:0] DIO_R10[2:0] DIO_R11[2:0] DIO_RPB[2:0] v1.2 Description Chop enable for the reference bandgap circuit. The value of CHOP changes on the rising edge of the internal MUXSYNC signal according to the value in CHOP_E[1:0]: 00 = toggle1 01 = positive 10 = reversed 11 = toggle 1 except at the mux sync edge at the end of an accumulation interval. The CHOP settings for the remote sensor. 00 = Auto chop. Change every MUX frame. 01 = Positive 10 = Negative 11 = Auto chop (same as 00) Enables IADC0-IADC1 differential configuration. Enables IADC2-IADC3 differential configuration. Enables IADC4-IADC5 differential configuration. Enables IADC6-IADC7 differential configuration. Connects PB and dedicated I/O pins DIO2 through DIO11 to internal resources. If more than one input is connected to the same resource, the MULTIPLE column below specifies how they are combined. MULTIPLE DIO_Rx Resource 0 NONE - 1 Reserved OR 2 T0 (Timer0 clock or gate) OR 3 T1 (Timer1 clock or gate) OR 4 IO interrupt (int0) OR 5 IO interrupt (int1) OR Programs the direction of the first 16 DIO pins. 1 indicates output. Ignored if the pin is not configured as I/O. See DIO_PV and DIO_PW for special option for DIO0 and DIO1 outputs. See DIO_EEX[1:0] for special option for SEGDIO2 and SEGDIO3. Note that the direction of DIO pins above 15 is set by SEGDIOx[1]. See PORT_E to avoid powerup spikes. The value on the first 16 DIO pins. Pins configured as LCD read zero. When written, changes data on pins configured as outputs. Pins configured as LCD or input ignore writes. Note that the data for DIO pins above 15 is set by SEGDIOx[0]. (c) 2008-2011 Teridian Semiconductor Corporation 105 71M6543F/H and 71M6543G/GH Data Sheet Name Location Rst Wk Dir DIO_EEX[1:0] 2456[7:6] 0 - R/W DIO_PV DIO_PW DIO_PX DIO_PY EEDATA[7:0] 2457[6] 2457[7] 2458[7] 2458[6] SFR 9E 0 0 0 0 0 - - - - 0 R/W R/W R/W R/W R/W EECTRL[7:0] SFR 9F 0 0 R/W Description When set, converts SEGDIO3 and SEGDIO2 to interface with external EEPROM. SEGDIO2 becomes SDCK and SEGDIO3 becomes bi-directional SDATA, but only if LCD_MAP[2] and LCD_MAP[3] are cleared. DIO_EEX[1:0] Function 00 Disable EEPROM interface 01 2-Wire EEPROM interface 10 3-Wire EEPROM interface 3-Wire EEPROM interface with separate DO (SEGDIO3) and DI 11 (SEGDIO8) pins. Causes VPULSE to be output on SEGDIO1, if LCD_MAP[1]=0. Causes WPULSE to be output on SEGDIO0, if LCD_MAP[0]=0. Causes XPULSE to be output on SEGDIO6 , if LCD_MAP[6]=0. Causes YPULSE to be output on SEGDIO7 , if LCD_MAP[7]=0. Serial EEPROM interface data. Serial EEPROM interface control. Status Name Bit ERROR 7 BUSY 6 5 RX_ACK Read/ Write R R R Reset Polarity Description State 0 Positive 1 when an illegal command is received. 0 Positive 1 when serial data bus is busy. 1 indicates that the EEPROM sent an 1 Positive ACK bit. Specifies the power equation. EQU[2:0] 3 EQU[2:0] 2106[7:5] 0 0 R/W 4 5* Description 2 element, 4W, 3 Del a 2 element, 4W, 3 Wye 3 element, 4W, 3 ye Element 0 Element 1 Element 2 VA(I -IB)/ 0 VC IC VA(IA-IB)/2 VB(IC-IB)/2 0 VA IA VB IB VC Recommended MUX Sequence IA VA IB B IA VA IB V C IA C VC I VC A IB VB IC V Note: *The available CE codes implements only equation 5. Contact your local Teridian representative to obtain CE code for equation 3 and 4. 106 (c) 2008-2011 Teridian Semiconductor Corporation v1.2 71M6543F/H and 71M6543G/GH Data Sheet Name EX_XFER EX_RTC1S EX_RTC1M EX_RTCT EX_SPI EX_EEX EX_XPULSE EX_YPULSE EX_WPULSE EX_VPULSE Location Rst Wk Dir 2700[0] 2700[1] 2700[2] 2700[3] 2701[7] 0 0 R/W 2700[7] 2700[6] 2700[5] 2701[6] 2701[5] EW_DIO4 28B3[2] 0 - R/W EW_DIO52 28B3[1] 0 - R/W EW_DIO55 28B3[0] 0 - R/W EW_PB 28B3[3] 0 - R/W EW_RX 28B3[4] 0 - R/W 210C[2:1] 0 0 R/W FIR_LEN[1:0] v1.2 Description Interrupt enable bits. These bits enable the XFER_BUSY, the RTC_1SEC, etc. The bits are set by hardware and cannot be set by writing a 1. The bits are reset by writing 0. Note that if one of these interrupts is to enabled, its corresponding 8051 EX enable bit must also be set. See 2.4.9 Interrupts, for details. Connects SEGDIO4 to the WAKE logic and permits SEGDIO4 rising to wake the part. This bit has no effect unless DIO4 is configured as a digital input. Connects SEGDIO52 to the WAKE logic and permits SEGDIO52 rising to wake the part. This bit has no effect unless SEGDIO52 is configured as a digital input. Connects SEGDIO55 to the WAKE logic and permits the SEGDIO55 rising edge to awaken the part. This bit has no effect unless SEGDIO55 is configured as a digital input. Connects PB to the WAKE logic and permits the PB rising edge to awaken the part. PB is always configured as an input. Connects RX to the WAKE logic and permits the RX rising edge to awaken the part. See the WAKE description in 3.4 Wake on Timer for de-bounce issues. Determines the number of ADC cycles in the ADC decimation FIR filter. PLL_FAST = 1: FIR_LEN[1:0] ADC Cycles 00 141 01 288 10 384 PLL_FAST = 0: FIR_LEN[1:0] ADC Cycles 00 135 01 276 10 Not Allowed The ADC LSB size and full-scale values depend on the FIR_LEN[1:0] setting. Refer to Table 83 on page 126 and Table 105 on page 144 for details. (c) 2008-2011 Teridian Semiconductor Corporation 107 71M6543F/H and 71M6543G/GH Data Sheet Name Location Rst Wk Dir FL_BANK[1:0] SFR B6[1:0] 01 01 R/W FLSH_ERASE[7:0] SFR 94[7:0] 0 0 W FLSH_MEEN SFR B2[1] 0 0 W FLSH_PEND SFR B2[3] 0 0 R SFR B7[7:2] 0 0 W 0 R/W FLSH_PGADR[5:0] FLSH_PSTWR 108 SFR B2[2] 0 Description Flash Bank Selection (71M6543G and 71M6543GH only) The program memory of the 71M6543G/GH consists of a fixed lower bank of 32 KB, addressable at 0x0000 to 0x7FFF plus an upper banked area of 32 KB, addressable at 0x8000 to 0xFFFF. The I/O RAM register FL_BANK is used to switch one of four memory banks of 32 KB each into the address range from 0x8000 to 0xFFFF. Note that when FL_BANK = 0, the upper bank is the same as the lower bank. Address Range for Lower Bank Address Range for Upper Bank FL_BANK[1:0] (0x0000-0x7FFF) (0x8000-0xFFFF) 00 0x0000-0x7FFF 0x0000-0x7FFF 01 0x0000-0x7FFF 0x8000-0xFFFF 10 0x0000-0x7FFF 0x10000-0x17FFF 11 0x0000-0x7FFF 0x18000-0x1FFFF Flash Erase Initiate FLSH_ERASE is used to initiate either the Flash Mass Erase cycle or the Flash Page Erase cycle. Specific patterns are expected for FLSH_ERASE in order to initiate the appropriate Erase cycle. (default = 0x00). 0x55 - Initiate Flash Page Erase cycle. Must be proceeded by a write to FLSH_PGADR[5:0] (SFR 0xB7). 0xAA - Initiate Flash Mass Erase cycle. Must be proceeded by a write to FLSH_MEEN (SFR 0xB2) and the debug (CC) port must be enabled. Any other pattern written to FLSH_ERASE has no effect. Mass Erase Enable 0 = Mass Erase disabled (default). 1 = Mass Erase enabled. Must be re-written for each new Mass Erase cycle. Indicates that a posted flash write is pending. If another flash write is attempted, it is ignored. Flash Page Erase Address Flash Page Address (page 0 thru 63) that is erased during the Page Erase cycle. (default = 0x00). Must be re-written for each new Page Erase cycle. Enables posted flash writes. When 1, and if CE_E = 1, flash write requests are stored in a one element deep FIFO and are executed when CE_BUSY falls. FLSH_PEND can be read to determine the status of the FIFO. If FLSH_PSTWR = 0 or if CE_E = 0, flash writes are immediate. (c) 2008-2011 Teridian Semiconductor Corporation v1.2 71M6543F/H and 71M6543G/GH Data Sheet Name Location Rst Wk Dir FLSH_PWE SFR B2[0] 0 0 R/W FLSH_RDE 2702[2] - - R FLSH_UNLOCK[3:0] 2702[7:4] 0 0 R/W FLSH_WRE IE_XFER IE_RTC1S IE_RTC1M IE_RTCT IE_SPI IE_EEX IE_XPULSE IE_YPULSE IE_WPULSE IE_VPULSE 2702[1] SFR E8[0] SFR E8[1] SFR E8[2] SFR E8[3] SFR F8[7] SFR E8[7] SFR E8[6] SFR E8[5] SFR F8[4] SFR F8[3] - - R 0 0 R/W INTBITS 2707[6:0] - - R LCD_ALLCOM LCD_BAT LCD_BLNKMAP23[5:0] 0 0 - - R/W R/W LCD_BLNKMAP22[5:0] 2400[3] 2402[7] 2401[5:0] 2402[5:0] 0 - R/W LCD_CLK[1:0] 2400[1:0] 0 - R/W v1.2 Description Program Write Enable 0 = MOVX commands refer to External RAM Space, normal operation (default). 1 = MOVX @DPTR,A moves A to External Program Space (Flash) @ DPTR. This bit is automatically reset after each byte written to flash. Writes to this bit are inhibited when interrupts are enabled. Indicates that the flash may be read by ICE or SPI slave. FLSH_RDE = (!SECURE) Must be a 2 to enable any flash modification. See the description of Flash security for more details. Indicates that the flash may be written through ICE or SPI slave ports. Interrupt flags for external interrupts 2 and 6. These flags monitor the source of the int6 and int2 interrupts (external interrupts to the MPU core). These flags are set by hardware and must be cleared by the software interrupt handler. The IEX2 (SFR 0xC0[1]) and IEX6 (SFR 0xC0[5]) interrupt flags are automatically cleared by the MPU core when it vectors to the interrupt handler. IEX2 and IEX6 must be cleared by writing zero to their corresponding bit positions in SFR 0xC0, while writing ones to the other bit positions that are not being cleared. Interrupt inputs. The MPU may read these bits to see the input to external interrupts INT0, INT1, up to INT6. These bits do not have any memory and are primarily intended for debug use. Configures SEG/COM bits as COM. Has no effect on pins whose LCD_MAP bit is zero. Connects the LCD power supply to VBAT in all modes. Identifies which segments connected to SEG23 and SEG22 should blink. 1 means blink. The most significant bit corresponds to COM5, the least significant, to COM0. Sets the LCD clock frequency. Note: f XTAL = 32768 Hz LCD_CLK[1:0] LCD Clock Frequency 9 00 f XTAL/2 01 f XTAL/28 10 f XTAL/27 6 11 f XTAL/2 (c) 2008-2011 Teridian Semiconductor Corporation 109 71M6543F/H and 71M6543G/GH Data Sheet Name Location Rst Wk Dir LCD_DAC[4:0] 240D[4:0] 0 - R/W 2400[7] 0 - R/W 2405[7:0] 2406[7:0] 2407[7:0] 2408[7:0] 2409[7:0] 240A[7:0] 240B[7:0] 0 0 0 0 0 0 0 - - - - - - - R/W R/W R/W R/W R/W R/W R/W Enables LCD segment driver mode of combined SEGDIO pins. Pins that cannot be configured as outputs (SEG48 through SEG50) become inputs with internal pull ups when their LCD_MAP bit is zero. Also, note that SEG48 through SEG50 are multiplexed with the in-circuit emulator signals. When the ICE_E pin is high, the ICE interface is enabled, and SEG48 through SEG50 become E_RXTX, E_TCLK and E_RST, respectively. Selects the LCD bias and multiplex mode. Output LCD_MODE 000 4 states, 1/3 bias 001 3 states, 1/3 bias 010 2 states, 1/2 bias 011 3 states, 1/2 bias 100 Static display 101 5 states, 1/3 bias 110 6 states, 1/3 bias LCD_E LCD_MAP[55:48] LCD_MAP[47:40] LCD_MAP[39:32] LCD_MAP[31:24] LCD_MAP[23:16] LCD_MAP[15:8] LCD_MAP[7:0] Description The LCD contrast DAC. This DAC controls the VLCD voltage and has an output range of 2.65 V to 5.3 V. The VLCD voltage is VLCD = 2.65 + 2.65 * LCD_DAC[4:0]/31 Thus, the LSB of the DAC is 85.5 mV. The maximum DAC output voltage is limited by V3P3SYS, VBAT, and whether LCD_BSTE = 1. Enables the LCD display. When disabled, VLC2, VLC1, and VLC0 are ground as are the COM and SEG outputs if their LCD_MAP bit is 1. 2400[6:4] 0 - R/W LCD_ON LCD_BLANK 240C[0] 240C[1] 0 0 - - R/W R/W LCD_ONLY 28B2[6] 0 0 W LCD_RST 240C[2] 0 - R/W 2410[5:0] to 0 241F[5:0] - R/W SEG Data for SEG0 through SEG15. DIO data for these pins is in SFR space. 2420[5:0] to 0 243D[5:0] - R/W SEG and DIO data for SEGDIO16 through SEGDIO45. If configured as DIO, bit 1 is direction (1 is output, 0 is input), bit 0 is data, and the other bits are ignored. LCD_MODE[2:0] LCD_SEG0[5:0] to LCD_SEG15[5:0] LCD_SEGDIO16[5:0] to LCD_SEGDIO45[5:0] 110 Turns on or off all LCD segments without changing LCD data. If both bits are set, the LCD display is turned on. Puts the 71M6543 to sleep, but with LCD display still active. Ignored if system power is present. It awakens when the Wake Timer times out, when certain DIO pins are raised, or when system power returns (see 3.2 Battery Modes). Clear all bits of LCD data. These bits affect SEGDIO pins that are configured as LCD drivers. This bit does not auto clear. (c) 2008-2011 Teridian Semiconductor Corporation v1.2 71M6543F/H and 71M6543G/GH Data Sheet Name LCD_SEG46[5:0] to LCD_SEG50[5:0] LCD_SEGDIO51[5:0] to LCD_SEGDIO55[5:0] LCD_VMODE[1:0] Location Rst Wk Dir 243E[5:0] 0 to 2442[5:0] - R/W SEG data for SEG46 through SEG50. These pins cannot be configured as DIO. 2443[5:0] to 0 2447[5:0] - R/W SEG and DIO data for SEGDIO51 through SEGDIO55. If configured as DIO, bit 1 is direction (1 is output, 0 is input), bit 0 is data, and the other bits are ignored. 2401[7:6] 00 00 R/W 2400[2] 0 - R/W 2887[6:0] 0 0 R/W 2887[7] 0 0 R/W 2888[7:0] 0 0 R/W 2889[1] 2889[0] 0 0 0 0 R/W R/W MPU_DIV[2:0] 2200[2:0] 0 0 R/W MUX0_SEL[3:0] MUX1_SEL[3:0] MUX2_SEL[3:0] MUX3_SEL[3:0] MUX4_SEL[3:0] MUX5_SEL[3:0] MUX6_SEL[3:0] MUX7_SEL[3:0] 2105[3:0] 2105[7:4] 2104[3:0] 2104[7:4] 2103[3:0] 2103[7:4] 2102[3:0] 2102[7:4] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W LCD_Y LKPADDR[6:0] LKPAUTOI LKPDAT[7:0] LKP_RD LKP_WR v1.2 Description Specifies how VLCD is generated. See 2.5.10.3 for the definition of V3P3L. LCD_VMODE Description 11 External VLCD 10 LCD boost and LCD DAC enabled 01 LCD DAC enabled 00 No boost and no DAC. VLCD=V3P3L. LCD Blink Frequency (ignored if blink is disabled). 1 = 1 Hz, 0 = 0.5 Hz The address for reading and writing the RTC lookup RAM. Auto-increment flag. When set, LKPADDR[6:0] auto increments every time LKP_RD or LKP_WR is pulsed. The incremented address can be read at LKPADDR. The data for reading and writing the RTC lookup RAM. Strobe bits for the RTC lookup RAM read and write. When set, the LKPADDR[6:0] and LKPDAT registers is used in a read or write operation. When a strobe is set, it stays set until the operation completes, at which time the strobe is cleared and LKPADDR[6:0] is incremented if LKPAUTOI is set. MPU clock rate is: MPU Rate = MCK Rate * 2-(2+MPU_DIV[2:0]). The maximum value for MPU_DIV[2:0] is 4. Based on the default values of the PLL_FAST bit and MPU_DIV[2:0], the power-up MPU rate is 6.29 MHz / 4 = 1.5725 MHz. The minimum MPU clock rate is 38.4 kHz when PLL_FAST = 1. Selects which ADC input is to be converted during time slot 0. Selects which ADC input is to be converted during time slot 1. Selects which ADC input is to be converted during time slot 2. Selects which ADC input is to be converted during time slot 3. Selects which ADC input is to be converted during time slot 4. Selects which ADC input is to be converted during time slot 5. Selects which ADC input is to be converted during time slot 6. Selects which ADC input is to be converted during time slot 7. (c) 2008-2011 Teridian Semiconductor Corporation 111 71M6543F/H and 71M6543G/GH Data Sheet Name MUX8_SEL[3:0] MUX9_SEL[3:0] MUX10_SEL[3:0] Location Rst Wk 2101[3:0] 0 0 2101[7:4] 0 0 2100[3:0] 0 0 Dir R/W R/W R/W MUX_DIV[3:0] 2100[7:4] 0 0 R/W 2457[0] 0 - R/W 2457[5:4] 0 - R/W OPT_BB OPT_FDC[1:0] OPT_RXDIS 2457[2] 0 - R/W OPT_RXINV 2457[1] 0 - R/W 00 - R/W OPT_TXE [1,0] 2456[3:2] OPT_TXINV 2456[0] 0 - R/W OPT_TXMOD 2456[1] 0 - R/W OSC_COMP 28A0[5] 0 - R/W SFR F8[0] SFR FC[6] SFR FC[5] 0 0 R 0 0 R/W PB_STATE PERR_RD PERR_WR 112 Description Selects which ADC input is to be converted during time slot 8. Selects which ADC input is to be converted during time slot 9. Selects which ADC input is to be converted during time slot 10. MUX_DIV[3:0] is the number of ADC time slots in each MUX frame. The maximum number of time slots is 11. Configures the input of the optical port to be a DIO pin to allow it to be bit-banged. In this case, DIO5 becomes a third high speed UART. Refer to 2.5.9 UART and Optical Interface =under the "Bit Banged Optical UART (Third UART)" subheading on page 57. Selects OPT_TX modulation duty cycle OPT_FDC Function 00 50% Low 01 25% Low 10 12.5% Low 11 6.25% Low OPT_RX can be configured as an input to the optical UART or as SEGDIO55. OPT_RXDIS = 0 and LCD_MAP[55] = 0: OPT_RX OPT_RXDIS = 1 and LCD_MAP[55] = 0: DIO55 OPT_RXDIS = 0 and LCD_MAP[55] = 1: SEG55 OPT_RXDIS = 1 and LCD_MAP[55] = 1: SEG55 Inverts result from OPT_RX comparator when 1. Affects only the UART input. Has no effect when OPT_RX is used as a DIO input. Configures the OPT_TX output pin. If LCD_MAP[51] = 0: 00 = DIO51, 01 = OPT_TX, 10 = WPULSE, 11 = VPULSE If LCD_MAP[51] = 1: xx = SEG51 Invert OPT_TX when 1. This inversion occurs before modulation. Enables modulation of OPT_TX. When OPT_TXMOD is set, OPT_TX is modulated when it would otherwise have been zero. The modulation is applied after any inversion caused by OPT_TXINV. Enables the automatic update of RTC_P[16:0] and RTC_Q [1:0]every time the temperature is measured. The de-bounced state of the PB pin. The 71M6543 sets these bits to indicate that a parity error on the remote sensor has been detected. Once set, the bits are remembered until they are cleared by the MPU. (c) 2008-2011 Teridian Semiconductor Corporation v1.2 71M6543F/H and 71M6543G/GH Data Sheet Name PLL_OK PLL_FAST Location Rst Wk Dir SFR F9[4] 0 0 R 2200[4] 0 0 R/W PLS_MAXWIDTH[7:0] 210A[7:0] FF FF R/W PLS_INTERVAL[7:0] 210B[7:0] Description Indicates that the clock generation PLL is settled. Controls the speed of the PLL and MCK. 1 = 19.66 MHz (XTAL * 600) 0 = 6.29 MHz (XTAL * 192) PLS_MAXWIDTH[7:0] determines the maximum width of the pulse (low-going pulse if PLS_INV=0 or high-going pulse if PLS_INV=1). The maximum pulse width is (2*PLS_MAXWIDTH[7:0] + 1)*TI. Where TI is PLS_INTERVAL[7:0] in units of CK_FIR clock cycles. If PLS_INTERVAL[7:0] = 0 or PLS_MAXWIDTH[7:0] = 255, no pulse width checking is performed and the output pulses have 50% duty cycle. See 2.3.6.2 VPULSE and WPULSE. PLS_INTERVAL[7:0] determines the interval time between pulses. The time between output pulses is PLS_INTERVAL[7:0]*4 in units of CK_FIR clock cycles. If PLS_INTERVAL[7:0] = 0, the FIFO is not used and pulses are output as soon as the CE issues them. PLS_INTERVAL[7:0] is calculated as follows: PLS_INTERVAL[7:0] = Floor ( Mux frame duration in CK_FIR cycles / CE pulse updates per Mux frame / 4 ) 0 0 R/W PLS_INV 210C[0] 0 0 R/W PORT_E 270C[5] 0 0 R/W 2704[5] SFRB2[7] 0 - 0 - R/W R SFR FC[4:0] 0 0 R/W PRE_E PREBOOT RCMD[4:0] RESET 2200[3] 0 0 W RFLY_DIS 210C[3] 0 0 R/W v1.2 For example, since the 71M6543 CE code is written to generate 6 pulses in one integration interval, when the FIFO is enabled (i.e., PLS_INTERVAL[7:0] 0) and that the frame duration is 1950 CK_FIR clock cycles, PLS_INTERVAL[7:0] should be written with Floor(1950 / 6 / 4) = 81 so that the five pulses are evenly spaced in time over the integration interval and the last pulse is issued just prior to the end of the interval. See 2.3.6.2 VPULSE and WPULSE. Inverts the polarity of WPULSE and VARPULSE. Normally, these pulses are active low. When inverted, they become active high. PLS_INV has no effect on XPULSE or YPULSE. Enables outputs from the SEGDIO0-SEGDIO15 pins. PORT_E = 0 blocks the momentary output pulse that occurs when SEGDIO0-SEGDIO15 are reset on power-up. Enables the 8x pre-amplifier. Indicates that pre-boot sequence is active. When the MPU writes a non-zero value to RCMD, the 71M6543 issues a command to the appropriate remote sensor. When the command is complete, the 71M6543 clears RCMD. When set, writes a one to WF_RSTBIT and then causes a reset. Controls how the 71M6543 drives the power pulse for the 71M6xxx. When set, the power pulse is driven high and low. When cleared, it is driven high followed by an open circuit fly-back interval. (c) 2008-2011 Teridian Semiconductor Corporation 113 71M6543F/H and 71M6543G/GH Data Sheet Name RMT2_E RMT4_E RMT6_E RMT_RD[15:8] RMT_RD[7:0] RTCA_ADJ[6:0] Location Rst Wk Dir 2709[3] 2709[4] 0 0 R/W 2709[5] 2602[7:0] 0 0 R 2603[7:0] 2504[6:0] 40 - R/W 2890[4] 0 0 R/W RTC_P[16:14] RTC_P[13:6] RTC_P[5:0] 289B[2:0] 289C[7:0] 289D[7:2] 4 0 0 4 0 0 R/W RTC_Q[1:0] 289D[1:0] 0 0 R/W 2890[6] 0 0 R/W RTC_SBSC[7:0] RTC_TMIN[5:0] 2892[7:0] 289E[5:0] - 0 - - R R/W RTC_THR[4:0] 289F[4:0] 0 - R/W 2890[7] 0 0 R/W 2893[5:0] 2894[5:0] 2895[4:0] 2896[2:0] 2897[4:0] 2898[3:0] 2899[7:0] - - - - - - - - - - - - - - R/W 2106[1] 0 0 R/W RTC_FAIL RTC_RD RTC_WR RTC_SEC[5:0] RTC_MIN[5:0] RTC_HR[4:0] RTC_DAY[2:0] RTC_DATE[4:0] RTC_MO[3:0] RTC_YR[7:0] RTM_E 114 Description Enables the remote interface. Response from remote read request. Register for analog RTC frequency adjustment. Indicates that a count error has occurred in the RTC and that the time is not trustworthy. This bit can be cleared by writing a 0. RTC adjust. See 2.5.4 Real-Time Clock (RTC). 0x0FFBF RTC_P 0x10040 Note: RTC_P[16:0] and RTC_Q[1:0] form a single 19-bit RTC adjustment value. RTC adjust. See 2.5.4 Real-Time Clock (RTC). Note: RTC_P[16:0] and RTC_Q[1:0] form a single 19-bit RTC adjustment value. Freezes the RTC shadow register so it is suitable for MPU reads. When RTC_RD is read, it returns the status of the shadow register: 0 = up to date, 1 = frozen. Time remaining since the last 1 second boundary. LSB=1/128 second. The target minutes register. See RTC_THR below. The target hours register. The RTC_T interrupt occurs when RTC_MIN [5:0] becomes equal to RTC_TMIN[5:0] and RTC_HR[4:0] becomes equal to RTC_THR[4:0]. Freezes the RTC shadow register so it is suitable for MPU writes. When RTC_WR is cleared, the contents of the shadow register are written to the RTC counter on the next RTC clock (~1 kHz). When RTC_WR is read, it returns 1 as long as RTC_WR is set. It continues to return one until the RTC counter actually updates. The RTC interface. These are the year, month, day, hour, minute and second parameters for the RTC. The RTC is set by writing to these registers. Year 00 and all others divisible by 4 are defined as a leap year. SEC 00 to 59 MIN 00 to 59 HR 00 to 23 (00=Midnight) DAY 01 to 07 (01=Sunday) DATE 01 to 31 MO 01 to 12 YR 00 to 99 Each write operation to one of these registers must be preceded by a write to 0x20A0. Real Time Monitor enable. When 0, the RTM output is low. (c) 2008-2011 Teridian Semiconductor Corporation v1.2 71M6543F/H and 71M6543G/GH Data Sheet Name RTM0[9:8] RTM0[7:0] RTM1[7:0] RTM2[7:0] RTM3[7:0] Location Rst Wk Dir 210D[1:0] 0 0 210E[7:0] 0 0 210F[7:0] 0 0 R/W 2110[7:0] 0 0 2111[7:0] 0 0 SECURE SFR B2[6] 0 0 R/W 28B2[7] 0 0 W SFR FD[7:0] - - R SLEEP SPI_CMD SPI_E 270C[4] 1 1 R/W SPI_SAFE 270C[3] 0 0 R/W SPI_STAT 2708[7:0] 0 0 R Description Four RTM probes. Before each CE code pass, the values of these registers are serially output on the RTM pin. The RTM registers are ignored when RTM_E = 0. Note that RTM0 is 10 bits wide. The others assume the upper two bits are 00. Inhibits erasure of page 0 and flash memory addresses above the beginning of CE code as defined by CE_LCTN[6/5:0]. Also inhibits the reading of flash memory by external devices (SPI or ICE port). Puts the 71M6543 to sleep. Ignored if system power is present. The 71M6543 wakes when the Wake timer times out, when push button is pushed, or when system power returns. SPI command. 8-bit command from the bus master. SPI port enable. Enables the SPI interface on pins SEGDIO36 - SEGDIO39. Requires that LCD_MAP[36-39] = 0. Limits SPI writes to SPI_CMD and a 16 byte region in DRAM. No other writes are permitted. SPI_STAT contains the status results from the previous SPI transaction Bit 7 - 71M6543 ready error: the 71M6543 was not ready to read or write as directed by the previous command. Bit 6 - Read data parity: This bit is the parity of all bytes read from the 71M6543 in the previous command. Does not include the SPI_STAT byte. Bit 5 - Write data parity: This bit is the overall parity of the bytes written to the 71M6543 in the previous command. It includes CMD and ADDR bytes. Bit 4:2 - Bottom 3 bits of the byte count. Does not include ADDR and CMD bytes. One, two, and three byte instructions return 111. Bit 1 - SPI FLASH mode: This bit is zero when the TEST pin is zero. Bit 0 - SPI FLASH mode ready: Used in SPI FLASH mode. Indicates that the flash is ready to receive another write instruction. STEMP[10:3] STEMP[2:0] SUM_SAMPS[12:8] SUM_SAMPS[7:0] TBYTE_BUSY TEMP_22[10:8] TEMP_22[7:0] v1.2 2881[7:0] 2882[7:5] 2107[4:0] 2108[7:0] - - - - R R 0 0 R/W 28A0[3] 0 0 R 230A[2:0] 230B[7:0] 0 - R The result of the temperature measurement. The number of multiplexer cycles (frames) per XFER_BUSY interrupt. Maximum value is 8191 cycles. Indicates that hardware is still writing the 0x28A0 byte. Additional writes to this byte are locked out while it is one. Write duration could be as long as 6 ms. Storage location for STEMP[10:0] at 22C. STEMP[10:0] is an 11 bit word. (c) 2008-2011 Teridian Semiconductor Corporation 115 71M6543F/H and 71M6543G/GH Data Sheet Name TEMP_BAT TEMP_BSEL TEMP_PER[2:0] Location Rst Wk Dir 28A0[4] 0 - R/W 28A0[7] 0 - R/W 28A0[2:0] 0 - R/W Description Causes VBAT to be measured whenever a temperature measurement is performed. Selects which battery is monitored by the temperature sensor: 1 = VBAT, 0 = VBAT_RTC Sets the period between temperature measurements. Automatic measurements can be enabled in any mode (MSN, BRN, LCD, or SLP). TEMP_PER = 0 disables automatic temperature updates, in which case TEMP_START may be used by the MPU to initiate a one-shot temperature measurement. TEMP_PER 0 1-6 7 TEMP_PWR 28A0[6] 0 - R/W TEMP_START 28B4[6] 0 0 R/W TMUX[5:0] TMUX2[4:0] TMUXR2[2:0] TMUXR4[2:0] TMUXR6[2:0] 2502[5:0] - - R/W 2503[4:0] - - R/W 270A[2:0] 270A[6:4] 000 000 R/W 2709[2:0] 2706[7:0] - - R VREF_CAL 2704[7] 0 0 R/W VREF_DIS 2704[6] 0 1 R/W VERSION[7:0] 116 Time (seconds) No temperature updates 2 (3 + TEMP _ PER ) Continuous updates Selects the power source for the temp sensor: 1 = V3P3D, 0 = VBAT_RTC. This bit is ignored in SLP and LCD modes, where the temp sensor is always powered by VBAT_RTC. When TEMP_PER = 0 automatic temperature measurements are disabled, and TEMP_START may be set by the MPU to initiate a one-shot temperature measurement. TEMP_START is ignored in SLP and LCD modes. Hardware clears TEMP_START when the temperature measurement is complete. Selects one of 32 signals for TMUXOUT. See 2.5.14 for details. Selects one of 32 signals for TMUX2OUT. See 2.5.14 for details. The TMUX setting for the remote isolated sensors (71M6xx3). The silicon version index. This word may be read by firmware to determine the silicon version. 71M6543G/GH VERSION[7:0] 71M6543F/H Silicon Version Silicon Version 0001 0001 A01 A01 0001 0011 A03 N/A 0001 0011 B01 N/A 0010 0010 B02 N/A Brings the ADC reference voltage out to the VREF pin. This feature is disabled when VREF_DIS=1. Disables the internal ADC voltage reference. (c) 2008-2011 Teridian Semiconductor Corporation v1.2 71M6543F/H and 71M6543G/GH Data Sheet Name Location Rst Wk Dir Description This word describes the source of power and the status of the VDD. VSTAT[2:0] 000 001 VSTAT[2:0] SFR F9[2:0] - - R 010 011 101 Description System Power OK. V3P3A>3.0v. Analog modules are functional and accurate. [V3AOK,V3OK]=11 System Power Low. 2.8v<V3P3A<3.0v. Analog modules not accurate. Switch over to battery power is imminent. [V3AOK,V3OK]=01 Battery power and VDD OK. VDD>2.25v. Full digital functionality. [V3AOK,V3OK]=00, [VDDOK,VDDgt2]=11 Battery power and VDD>2.0. Flash writes are inhibited. If the TRIMVDD[5] fuse is blown, PLL_FAST is cleared. [V3AOK,V3OK]=00, [VDDOK,VDDgt2]=01 Battery power and VDD<2.0. When VSTAT=101, processor is nearly out of voltage. Processor failure is imminent. [V3AOK,V3OK]=00, [VDDOK,VDDgt2]=00 WAKE_ARM 28B2[5] 0 - R/W Arms the WAKE timer and loads it with WAKE_TMR[7:0]. When SLEEP or LCD mode is asserted by the MPU, the WAKE timer becomes active. WAKE_TMR 2880[7:0] 0 - R/W Timer duration is WAKE_TMR+1 seconds. WD_RST 28B4[7] 0 0 W Reset the WD timer. The WD is reset when a 1 is written to this bit. Writing a one clears and restarts the watch dog timer. WF_DIO4 28B1[2] 0 - R DIO4 wake flag bit. If DIO4 is configured to wake the part, this bit is set whenever the de-bounced version of DIO4 rises. It is held in reset if DI04 is not configured for wakeup. WF_DIO52 28B1[1] 0 - R DIO52 wake flag bit. If DIO52 is configured to wake the part, this bit is set whenever the de-bounced version of DIO52 rises. It is held in reset if DI052 is not configured for wakeup. WF_DIO55 28B1[0] 0 - R DIO55 wake flag bit. If DIO55 is configured to wake the part, this bit is set whenever the de-bounced version of DIO55 rises. It is held in reset if DI055 is not configured for wakeup. WF_TMR 28B1[5] 0 - R Indicates that the wake timer caused the part to wake up. WF_PB 28B1[3] 0 - R Indicates that the PB caused the part to wake. WF_RX WF_CSTART WF_RST WF_RSTBIT WF_OVF WF_ERST WF_BADVDD 28B1[4] 28B0[7] 28B0[6] 28B0[5] 28B0[4] 28B0[3] 28B0[2] 0 0 1 0 0 0 0 - R Indicates that RX caused the part to wake. - R Indicates that the Reset pin, Reset bit, ERST pin, Watchdog timer, the cold start detector, or bad VBAT caused the part to reset. v1.2 (c) 2008-2011 Teridian Semiconductor Corporation 117 71M6543F/H and 71M6543G/GH Data Sheet 5.3 Reading the Info Page (71M6543H and 71M6543GH only) High precision trim fuse values provided in the 71M6543H and 71M6543GH devices cannot be directly accessed through the I/O RAM space. These trim fuses reside in a special area termed the "Info Page". The MPU gains access to the Info Page by setting the INFO_PG (I/O RAM 0x270B[0]) control bit. Once the INFO_PG bit is set, Info Page contents are accessible in program memory space based at the address specified by the contents of CE_LCTN[6/5:0] (I/O RAM 0x2109[5:0]) in the 71M6543H and CE_LCTN[6:0] (I/O RAM 0x2109[6:0]) in the 71M6543GH. CE_LCTN[5:0] in the 71M6543H and CE_LCTN[6:0] in the 71M6543GH specify a base address at a 1KB address boundary. Thus, the base address for the Info Page is at 1024*CE_LCTN[5:0] in the 71M6543H and 1024*CE_LCTN[6:0] in the 71M6543GH. Table 72 provides a list of the available 71M6543H and 71M6543GH trim fuses and their corresponding offsets relative to the Info Page base address. After reading the desired Info Page information, the MPU must reset the INFO_PG bit. Trim Fuse Table 72: Info Page Trim Fuses Object Size Address Offset TEMP_85[10:8] TEMP_85[7:0] (11-bits) 8-bits 8-bits 0x90 0x91 TRIMBGB[15:8] TRIMBGB[7:0] (16-bits) 8-bits 8-bits 0x92 0x93 TRIMBGD[7:0] (8-bits) 8-bits 0x94 LCDADJ12[7:0] (8-bits) 8-bits 0x95 LCDADJ0[7:0] (8-bits) 8-bits 0x96 Comments TEMP_85[10:0] holds the STEMP[10:0] reading at 85C. 2's complement format TRIMBGB[15:0] holds the deviation of VREF from its ideal value (1.195V) at 85C. LSB = 0.1 mV 2's complement format TRIMBGD[7:0] holds the deviation of VREF from its ideal value (1.195V) at 22C. LSB = 0.1 mV 2's complement format LCDADJ12 = [VLCD-3.676v] at 22C when LCD_DAC=0C. LSB=5mV. Two's complement. LCDADJ0 = [VLCD-2.65v] at 22C when LCD_DAC=0. LSB=5mV. Two's complement. Figure 38. Trim Fuse Bit Mapping Offset 0x90 0x91 0x92 0x93 0x94 Name TEMP_85[10:0] TRIMBGB[15:0] TRIMBGD[7:0] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TEMP_85[10:8] TEMP_85[7:0] TRIMBGB[15:8] TRIMBGB[7:0] TRIMBGD[7:0] The code below provides an example for reading Info Page fuse trims. In this code example, the address, "px" is a pointer to the MPU's code space. In assembly language, the Info Page data objects, which are read-only, must be accessed with the MOVC 8051 instruction. In C, Info Page trim fuses must be fetched with a pointer of the correct width, depending whether an 8-bit or a 16-bit data object is to be fetched. The case statements in the code example below perform casts to obtain a pointer of the correct size for each object, as needed. In assembly language, the MPU has to form 11-bit or 16-bit values from two separate 8-bit fetches, depending on the object being fetched. 118 (c) 2008-2011 Teridian Semiconductor Corporation v1.2 71M6543F/H and 71M6543G/GH Data Sheet The byte values containing less than 8 valid bits are LSB justified. For example Info Page offset 0x90 is an 8-bit object, whose three LSBs are bits [10:8] of the complete TEMP_85[10:0] 11-bit object. The Info Page data objects are 2's complement format and should be sign extended when read into a 16-bit data type (see case _TEMP85 in the code example). #if HIGH_PRECISION_METER int16_t read_trim (enum eTRIMSEL select) { uint8r_t *px; int16_t x; px = ((uint16_t)select) + ((uint8r_t *)(CE3 << 10)); switch (select) { default: case _TRIMBGD: INFO_PG = 1; x = *px; INFO_PG = 0; break; case _TRIMBGB: INFO_PG = 1; x = *(uint16r_t*)px; INFO_PG = 0; break; case _TEMP85: INFO_PG = 1; x = *(uint16r_t*)px; INFO_PG = 0; if (x & 0x800) x |= 0xF800; break; } return (x); } #endif //#if HIGH_PRECISION_METER v1.2 (c) 2008-2011 Teridian Semiconductor Corporation 119 71M6543F/H and 71M6543G/GH Data Sheet 5.4 CE Interface Description 5.4.1 CE Program The CE performs the precision computations necessary to accurately measure power. These computations include offset cancellation, phase compensation, product smoothing, product summation, frequency detection, VAR calculation, sag detection and voltage phase measurement. All data computed by the CE is dependent on the selected meter equation as given by EQU[2:0] (I/O RAM 0x2106[7:5]). The standard CE program is supplied by Teridian as a data image that can be merged with the MPU operational code for meter applications. Typically, this CE program covers most applications and does not need to be modified. Other variations of CE code may be available from Teridian. The description in this section applies to CE code revision CE43A01A. 5.4.2 CE Data Format All CE words are 4 bytes. Unless specified otherwise, they are in 32-bit two's complement format (-1 = 0xFFFFFFFF). Calibration parameters are defined in flash memory (or external EEPROM) and must be copied to CE data memory by the MPU before enabling the CE. Internal variables are used in internal CE calculations. Input variables allow the MPU to control the behavior of the CE code. Output variables are outputs of the CE calculations. The corresponding MPU address for the most significant byte is given by 0x0000 + 4 x CE_address and by 0x0003 + 4 x CE_address for the least significant byte. 5.4.3 Constants Constants used in the CE Data Memory tables are: * * * * * * * * * Sampling Frequency: FS = 32768 Hz/15 = 2184.53 Hz. F0 is the fundamental frequency of the mains phases. IMAX is the external rms current corresponding to 250 mV pk at each IADC input. VMAX is the external rms voltage corresponding to 250 mV pk at each VADC input. NACC, the accumulation count for energy measurements is SUM_SAMPS[12:0] (I/O RAM 0x2107[4:0], 0x2108[7:0]). This value also resides in SUM_PRE (CE RAM 0x23) where it is used for phase angle measurement. The duration of the accumulation interval for energy measurements is SUM_SAMPS[12:0] /FS. X is a gain constant of the pulse generators. Its value is determined by PULSE_FAST and PULSE_SLOW (see Table 78). -9 Voltage LSB = VMAX * 7.879810 V. VMAX = 600 V, IMAX = 208 A, and kH = 3.2 Wh/pulse are assumed as default settings. The system constants IMAX and VMAX are used by the MPU to convert internal digital quantities (as used by the CE) to external, i.e. metering quantities. Their values are determined by the scaling of the voltage and current sensors used in an actual meter. The LSB values used in this document relate digital quantities at the CE or MPU interface to external meter input quantities. For example, if a SAG threshold of 80 V peak is desired at the meter input, the digital value that should be programmed into SAG_THR (CE RAM 0x24) would be 80 V/SAG_THRLSB, where SAG_THRLSB is the LSB value in the description of SAG_THR (Table 79). The parameters EQU[2:0], CE_E, and SUM_SAMPS[12:0] , essential to the function of the CE are stored in I/O RAM (see 5.2 for details). 120 (c) 2008-2011 Teridian Semiconductor Corporation v1.2 71M6543F/H and 71M6543G/GH Data Sheet 5.4.4 Environment Before starting the CE using the CE_E bit (I/O RAM 0x2106[0]), the MPU has to establish the proper environment for the CE by implementing the following steps: * * * * * * * Locate the CE code in Flash memory using CE_LCTN[5:0] (I/O RAM 0x2109[5:0]) in the 71M6543F/H and CE_LCTN[6:0] (I/O RAM 0x2109[6:0]) in the 71M6543G/GH Load the CE data into RAM. Establish the equation to be applied in EQU[2:0] (I/O RAM 0x2106[7:5]). Establish the accumulation period and number of samples in SUM_SAMPS[12:0] (I/O RAM 0x2107[4:0], 0x2108[7:0]). Establish the number of cycles per ADC multiplexer frame (MUX_DIV[3:0] (I/O RAM 0x2100[7:4])). Apply proper values to MUXn_SEL, as well as proper selections for DIFFn_E (I/O RAM 0x210C[ ]) and RMTn_E (I/O RAM 0x2709[ ] in order to configure the analog inputs. Initialize any MPU interrupts, such as CE_BUSY, XFER_BUSY, or the power-failure detection interrupt. When different CE codes are used, a different set of environment parameters need to be established. The exact values for these parameters are listed in the Application Notes and other documentation which accompanies the CE code. Operating CE codes with environment parameters deviating from the values specified by Teridian leads to unpredictable results. Typically, there are fifteen 32768 Hz cycles per ADC multiplexer frame (see 2.2.2). This means that the product of the number of cycles per frame and the number of conversions per frame must be 14 (allowing for one settling cycle). The default configuration is FIR_LEN = 01, I/O RAM 0x210C[1] (two cycles per conversion) and MUX_DIV[3:0] = 7 (7 conversions per multiplexer cycle). Sample configurations can be copied from Demo Code provided by Teridian with the Demo Kits. 5.4.5 CE Calculations Referring to Table 73, The MPU selects the desired equation by writing the EQU[2:0] (I/O RAM 0x2106[7:5]). Table 73: CE EQU[2:0] Equations and Element Input Mapping EQU [2:0]* 2 3 4 5 Watt & VAR Formula (WSUM/VARSUM) W0SUM/ VAR0SUM W1SUM/ VAR1SUM VA*IA + VB*IB VA * IA VB * IB (2-element, 3-W, 3 Delta) VA*(IA-IB)/2 + VC*IC VA*(IA-IB)/2 - (2 element, 4W 3 Delta) VA*(IA-IB)/2 + VB*(IC-IB)/2 VA*(IA-IB)/2 VB*(IC-IB)/2 (2 element, 4W 3 Wye) VA*IA + VB*IB + VC*IC VA*IA VB*IB (3 element, 4W 3 Wye) W2SUM/ VAR2SUM I0SQ SUM I1SQ SUM I2SQ SUM N/A IA IB - VC*IC IA-IB IB IC - IA-IB IC-IB IC VC*IC IA IB IC Note: * Only EQU[2:0] = 5 is supported by the currently available CE code versions for the 71M6543. Contact your local Teridian representative for CE codes that support equations 2, 3 and 4. v1.2 (c) 2008-2011 Teridian Semiconductor Corporation 121 71M6543F/H and 71M6543G/GH Data Sheet 5.4.6 CE Front-End Data (Raw Data) Access to the raw data provided by the AFE is possible by reading CE RAM addresses 0 through A, as shown in Table 74. In the expression MUXn_SEL[3:0] = x, `n' refers to the multiplexer frame time slot number and `x' refers to the desired ADC input number or ADC handle (i.e., IADC0 to VADC10, or simply 0 to 10 decimal). The 71M6543 can support up to eleven sensor inputs, when all the current sensors are configured as single-ended inputs. If all the current sensor inputs are configured as differential (recommended for best performance), the number of input sensor channels is reduced to seven (i.e., IADC0-1, IADC2-3, IADC4-5, IADC6-7, VADC8, VADC9 and VADC10). The MUXn_SEL[3:0] column in Table 74 shows the MUXn_SEL handles for the various sensor input pins. For example, if differential mode is enabled via control bit DIFF0_E = 1 (I/O RAM 0x210C[4]), then the IADC0-IADC1 input pins are combined together to form a single differential input and the corresponding MUXn_SEL handle is 0 (i.e., handle 1 is then unused). Similarly, the CE RAM location column provides the CE RAM address where the corresponding sample data is stored. Continuing with the same example, if DIFF0_E = 1, the corresponding CE RAM location where the samples for the IADC0-IADC1 differential input are stored is CE RAM 0. The IADC2-3, IADC4-5 and IADC6-7 inputs can be configured as direct-connected sensors (i.e., directly connected to the 71M6543) or as remote sensors (i.e., using a 71M6xx3 Isolated Sensor). For example, if the IADC2-3 remote sensor is disabled by RMT2_E = 0 (I/O RAM 0x2007[3]) and differential mode is enabled by DIFF2_E = 1 (I/O RAM 0x210C[4]), then IADC2-IADC3 form a differential input with a MUXn_SEL handle of 2 (i.e., handle 3 is then unused), and the corresponding samples are stored in CE RAM location 2. If the remote sensor enable bit RMT2_E = 1, DIFF2_E = x (don't care), then the MUXn_SEL handle is not required (i.e., the sensor is not connected to the 71M6543 multiplexer, so MUXn_SEL does not apply), and the samples corresponding to this remote differential IADC2-IADC3 input are stored in CE RAM location 2 directly by the digital isolation interface (see Figure 2). The voltage sensor inputs (VADC8, VADC9 and VADC10) are always single-ended inputs and cannot be configured as remotes, so they do not have any associated configuration bits. VADC8 (VA) has a MUXn_SEL handle value of 8, and its samples are stored in CE RAM location 8. VADC9 (VB) has a MUXn_SEL handle value of 9 and its samples are stored in CE RAM location 9. VADC10 (VC) has a MUXn_SEL handle value of 10 and its samples are stored in CE RAM location 10. Table 74: CE Raw Data Access Locations Pin MUXn_SEL Handle CE RAM Location IADC4 IADC5 DIFF0_E 0 1 0 0 1 RMT2_E, DIFF2_E 0,0 0,1 1,0 1,1 2 2 3 RMT4_E, DIFF4_E 0,0 0,1 1,0 1,1 4 4 5 DIFF0_E 0 1 0 0 1 RMT2_E, DIFF2_E 0,0 0,1 1,0 1,1 2 2 2* 2* 3 RMT4_E, DIFF4_E 0,0 0,1 1,0 1,1 4 4 4* 4* 5 IADC6 IADC7 0,0 6 7 VADC8 (VA) VADC9 (VB) VADC10 (VC) 8 9 10 IADC0 IADC1 IADC2 IADC3 RMT6_E, DIFF6_E 0,1 1,0 1,1 RMT6_E, DIFF6_E 0,0 0,1 1,0 1,1 6 6 6 6* 6* 7 There are no configuration bits for VADC8, 9, 10 8 9 10 *Remote interface data 122 (c) 2008-2011 Teridian Semiconductor Corporation v1.2 71M6543F/H and 71M6543G/GH Data Sheet 5.4.7 CE Status and Control The CE Status Word is useful for generating early warnings to the MPU (Table 75). It contains sag warnings for phase A, B, and C, as well as F0, the derived clock operating at the fundamental input frequency. The MPU can read the CE status word at every CE_BUSY interrupt. Since the CE_BUSY interrupt occurs at the sample rate (i.e., 2520.6 Hz for MUX_DIV[3:0]=6 or 2184.5 Hz for MUX_DIV[3:0]=7), it is desirable to minimize the computation required in the interrupt handler of the MPU. Table 75: CESTATUS Register CE Address 0x80 Name CESTATUS Description See description of CESTATUS bits in Table 76. CESTATUS provides information about the status of voltage and input AC signal frequency, which are useful for generating an early power fail warning to initiate necessary data storage. CESTATUS represents the status flags for the preceding CE code pass (CE_BUSY interrupt). The significance of the bits in CESTATUS is shown in Table 76. Table 76: CESTATUS Bit Definitions CESTATUS bit Name 31:4 3 Not Used F0 2 SAG_C 1 SAG_B 0 SAG_A Description These unused bits are always zero. F0 is a square wave at the exact fundamental input frequency. Normally zero. Becomes one when VADC10 (VC) remains below SAG_THR (CE RAM 0x24) for SAGCNT samples. Does not return to zero until VADC10 (VC) rises above SAG_THR. Normally zero. Becomes one when VADC9 (VB) remains below SAG_THR for SAG_CNT samples. Does not return to zero until VADC9 (VB) rises above SAG_THR. Normally zero. Becomes one when VADC8 (VA) remains below SAG_THR for SAG_CNT samples. Does not return to zero until VADC8 (VA) rises above SAG_THR. The CE is initialized by the MPU using CECONFIG (Table 77). This register contains in packed form SAG_CNT, FREQSEL0, FREQSEL1, EXT_PULSE, PULSE_SLOW, and PULSE_FAST. The CECONFIG bit definitions are given in Table 78. Table 77: CECONFIG Register CE Address Name Data 0x20 CECONFIG 0x0030DA20 Description See description of the CECONFIG bits in Table 78. The EXT_TEMP bit enables temperature compensation by the MPU, when set to 1. When 0, internal (CE) temperature compensation is enabled. The CE pulse generator can be controlled by either the MPU (external) or CE (internal) variables. Control is by the MPU if EXT_PULSE = 1. In this case, the MPU controls the pulse rate by placing values into APULSEW and APULSER (CE RAM 0x45 and 0x49). By setting EXT_PULSE = 0, the CE controls the pulse rate based on WSUM_X (CE RAM 0x84) and VARSUM_X (CE RAM 0x88). The 71M6543 Demo Code creep function halts both internal and external pulse generation. v1.2 (c) 2008-2011 Teridian Semiconductor Corporation 123 71M6543F/H and 71M6543G/GH Data Sheet Table 78: CECONFIG Bit Definitions (CE RAM 0x20) CECONFIG bit 23 Name Default Reserved 0 22 EXT_TEMP 0 21 EDGE_INT 1 20 SAG_INT 1 19:8 SAG_CNT 218 (0xDA) 7:6 FREQSEL[1:0] 0 5 EXT_PULSE 1 4:2 Reserved 0 1 PULSE_FAST 0 0 PULSE_SLOW 0 Description Reserved. When 1, the MPU controls temperature compensation via the GAIN_ADJn (CE RAM 0x40-0x42), when 0, the CE is in control. When 1, XPULSE produces a pulse for each zero-crossing of the mains phase selected by FREQSEL[1:0] , which can be used to interrupt the MPU. When 1, activates the YPULSE/SEGDIO7 output when a sag is detected (see 2.5.10) on the phase selected with FREQSEL[1:0]. The number of consecutive voltage samples below SAG_THR (CE RAM 0x24) before a sag alarm is declared. The default value is equivalent to 100 ms. FREQSEL[1:0] selects the phase to be used for the frequency monitor, sag detection, the phase-to-phase lag calculation and for the zero crossing counter (MAINEDGE_X, CE RAM 0x83). Phase Phases Selected FREQ SEL[1:0] Selected PH_AtoB_X PH_AtoC_X 0 0 A A-B A-C 0 1 B B-C B-A 1 0 C C-A C-B 1 1 Not allowed When zero, causes the pulse generators to respond to internal data. WPULSE = WSUM_X (CE RAM 0x84), VPULSE = VARSUM_X (CE RAM 0x88.) Otherwise, the generators respond to values the MPU places in APULSEW and APULSER (CE RAM 0x45 and 0x49) Reserved. When PULSE_FAST = 1, the pulse generator input is increased 16x. When PULSE_SLOW = 1, the pulse generator input is reduced by a factor of 64. These two parameters control the pulse gain factor X (see table below). Allowed values are either 1 or 0. Default is 0 for both (X = 6). PULSE_FAST PULSE_SLOW 0 0 0 1 1 0 1 1 X 2 1.5 * 2 = 6 -4 1.5 * 2 = 0.09375 1.5 * 26 = 96 Do not use The FREQSEL[1:0] field in CECONFIG (CE RAM 0x20[7:6]) selects the phase that is utilized to generate a sag interrupt. Thus, a SAG_INT event occurs when the selected phase has satisfied the sag event criteria as set by the SAG_THR (CE RAM 0x24) register and the SAG_CNT field in CECONFIG (CE RAM 0x20[19:8]). When the SAG_INT bit (CE RAM 0x20[20]) is set to 1, a sag event generates a transition on the YPULSE output. After a sag interrupt, the MPU should change the FREQSEL[1:0] setting to select the other phase, if it is powered. Even though a sag interrupt is only generated on the selected phase, all three phases are simultaneously checked for sag. The presence of power on a given phase can be sensed by directly checking the SAG_A, SAG_B and SAG_C bits in CESTATUS (CE RAM 0x80[0:1]). The EXT_TEMP bit enables temperature compensation by the MPU, when set to 1. When 0, internal (CE) temperature compensation is enabled. 124 (c) 2008-2011 Teridian Semiconductor Corporation v1.2 71M6543F/H and 71M6543G/GH Data Sheet The CE pulse generator can be controlled by either the MPU (external) or CE (internal) variables. Control is by the MPU if the EXT_PULSE bit = 1 (CE RAM 0x20[5]). In this case, the MPU controls the pulse rate (external pulse generation) by placing values into APULSEW and APULSER (CE RAM 0x45 and 0x49). By setting EXT_PULSE = 0, the CE controls the pulse rate based on WSUM_X (CE RAM 0x84) and VARSUM_X (CE RAM 0x88). The 71M6543 Demo Code creep function halts both internal and external pulse generation. Table 79: Sag Threshold, Phase Measurement, and Gain Adjust Control CE Address Name Default Description 0x24 SAG_THR 2.39*107 0x40 0x41 0x42 0x43 GAIN_ADJ0 GAIN_ADJ1 GAIN_ADJ2 GAIN_ADJ3 16384 16384 16384 16384 The voltage threshold for sag warnings. The default value is equivalent to 80 V RMS if VMAX = 600 V. The assignments of these gain adjustments depends on the meter design. See 4.5.5 Temperature Compensation for VREF and Shunt Sensors on page 90 or 4.5.6 Temperature Compensation of VREF and Current Transformers on page 92. The default value of 16384 corresponds to unity gain. 0x44 GAIN_ADJ4 16384 5.4.8 CE Transfer Variables When the MPU receives the XFER_BUSY interrupt, it knows that fresh data is available in the transfer variables. CE transfer variables are modified during the CE code pass that ends with an XFER_BUSY interrupt. They remain constant throughout each accumulation interval. In this data sheet, the names of CE transfer variables always end with _X. The transfer variables can be categorized as: * * * Fundamental energy measurement variables Instantaneous (RMS) values Other measurement parameters Fundamental Energy Measurement Variables Table 80 describes each transfer variable for fundamental energy measurement. All variables are signed 32-bit integers. Accumulated variables such as WSUM are internally scaled so they have at least 2x margin before overflow when the integration time is one second. Additionally, the hardware does not permit output values to fold back upon overflow. Table 80: CE Transfer Variables (with Shunts) CE Address Name 0x84 0x85 0x86 0x87 0x88 WSUM_X W0SUM_X W1SUM_X W2SUM_X VARSUM_X The signed sum: W0SUM_X+W1SUM_X+W2SUM_X. 0x89 0x8A 0x8B VAR0SUM_X VAR1SUM_X VAR2SUM_X The sum of VARh samples from each wattmeter element. LSBW = 7.7562*10-13 VMAX * IMAX VARh. v1.2 Description Configuration The sum of Wh samples from each wattmeter element. -13 LSBW = 7.7562*10 VMAX * IMAX Wh. The signed sum: VAR0SUM_X+VAR1SUM_X+VAR2SUM_X. (c) 2008-2011 Teridian Semiconductor Corporation Figure 31 (page 87) 125 71M6543F/H and 71M6543G/GH Data Sheet Table 81: CE Transfer Variables (with CTs) CE Address Name 0x84 0x85 0x86 0x87 0x88 WSUM_X W0SUM_X W1SUM_X W2SUM_X VARSUM_X The signed sum: W0SUM_X+W1SUM_X+W2SUM_X. 0x89 0x8A 0x8B VAR0SUM_X VAR1SUM_X VAR2SUM_X The sum of VARh samples from each wattmeter element. LSBW = 1.0856*10-12 VMAX IMAX VARh. Description Configuration The sum of Wh samples from each wattmeter element. LSBW = 1.0856*10-12 VMAX IMAX Wh. The signed sum: VAR0SUM_X+VAR1SUM_X+VAR2SUM_X. Figure 32 (page 88) WSUM_X and VARSUM_X are the signed sum of Phase-A, Phase-B and Phase-C Wh or VARh values according to the metering equation specified in the control field EQU[2:0] (I/O RAM 0x2106[7:5]). WnSUM_X is the Wh value accumulated for phase n in the last accumulation interval and can be computed based on the specified LSB value. For example, with VMAX = 600 V and IMAX = 208 A, the LSB for WnSUM_X is 0.135 Wh. 5.4.8.1 Instantaneous Energy Measurement Variables InSQSUM_X and VnSQSUM are the squared current and voltage samples acquired during the last accumulation interval. INSQSUM_X can be used for computing the neutral current. Table 82: CE Energy Measurement Variables (with Shunts) CE Address Name Description 0x8C I0SQSUM_X Neutral Current: LSBI = 9.9045*10-13 * IMAX2 A2h (PRE_E=0) -14 2 2 LSBI = 6.1903125*10 * IMAX A h (PRE_E=1) 0x8D I1SQSUM_X 0x8E I2SQSUM_X 0x8F I3SQSUM_X 0x90 V0SQSUM_X 0x91 V1SQSUM_X 0x92 V2SQSUM_X LSBI = 6.3968*10-13 * (IMAX2) A2h Configuration Figure 31 (page 87) LSBV = 9.4045*10-13*VMAX2 V2h Table 83: CE Energy Measurement Variables (with CTs) CE Address Name 0x8C I0SQSUM_X 0x8D I1SQSUM_X 0x8E I2SQSUM_X 0x8F I3SQSUM_X 0x90 V0SQSUM_X 0x91 V1SQSUM_X 0x92 V2SQSUM_X 126 Description Configuration LSBI = 1.0856*10-12 * (IMAX2) A2h Figure 32 (page 88) LSBV = 1.0856*10-12 * VMAX2 V2h (c) 2008-2011 Teridian Semiconductor Corporation v1.2 71M6543F/H and 71M6543G/GH Data Sheet The RMS values can be computed by the MPU from the squared current and voltage samples as follows: Ix RMS = IxSQSUM LSBI 3600 FS N ACC VxRMS = VxSQSUM LSBV 3600 FS N ACC Other transfer variables include those available for frequency and phase measurement, and those reflecting the count of the zero-crossings of the mains voltage and the battery voltage. These transfer variables are listed in Table 84. MAINEDGE_X reflects the number of half-cycles accounted for in the last accumulated interval for the AC signal of the phase specified in the FREQSEL[1 :0] field of the CECONFIG register (CE RAM 0x20[7:6]) . MAINEDGE_X is useful for implementing a real-time clock based on the input AC signal. Table 84: Other Transfer Variables CE Address Name Description 2184 Hz 0.509 10-6 Hz(for CT) 32 2 2520 Hz 0.587 10 -6 Hz(for Shunt) LSB 2 32 Fundamental frequency: LSB 0x82 FREQ_X 0x83 MAINEDGE_X 0x94 PH_AtoB_X 0x95 PH_AtoC_X The number of edge crossings of the selected voltage in the previous accumulation interval. Edge crossings are either direction and are debounced. Voltage phase lag. The selection of the reference phase is based on FREQSEL[1:0] in the CECONFIG register: If FREQSEL[1:0] selects phase A: Phase lag from A to B. If FREQSEL[1:0] selects phase B: Phase lag from B to C. If FREQSEL[1:0] selects phase C: Phase lag from C to A. Angle in degrees is (0 to 360): PH_AtoB_X * 360/NACC + 2.4*15/13 (for CT) Angle in degrees is (0 to 360): PH_AtoB_X * 360/NACC + 2.4 (for Shunt) If FREQSEL[1:0] selects phase A: Phase lag from A to C. If FREQSEL[1:0] selects phase B: Phase lag from B to A. If FREQSEL[1:0] selects phase C: Phase lag from C to B. Angle in degrees is (0 to 360): PH_AtoC_X * 360/NACC + 4.8*15/13 (for CT) Angle in degrees is (0 to 360): PH_AtoC_X * 360/NACC + 4.8*15/13 (for Shunt) Phase angle measurement accuracy can be increased by writing values > 1 into V_ANG_CNT (see Table 79). 5.4.9 Pulse Generation Table 85 describes the CE pulse generation parameters. The combination of the CECONFIG PULSE_SLOW (CE RAM 0x20[0]) and PULSE_FAST (CE RAM 0x20[1]) bits controls the speed of the pulse rate. The default values of 0 and 0 maintain the original pulse rate given by the Kh equation. WRATE (CE RAM 0x21) controls the number of pulses that are generated per measured Wh and VARh quantities. The lower WRATE is the slower the pulse rate for measured energy quantity. The metering constant Kh is derived from WRATE as the amount of energy measured for each pulse. That is, if Kh = 1Wh/pulse, a power applied to the meter of 120 V and 30 A results in one pulse per second. If the load is 240 V at 150 A, ten pulses per second are generated. Control is transferred to the MPU for pulse generation if EXT_PULSE = 1 (CE RAM 0x20[5]). In this case, the pulse rate is determined by APULSEW and APULSER (CE RAM 0x45 and 0x49). The MPU has to load v1.2 (c) 2008-2011 Teridian Semiconductor Corporation 127 71M6543F/H and 71M6543G/GH Data Sheet the source for pulse generation in APULSEW and APULSER to generate pulses. Irrespective of the EXT_PULSE status, the output pulse rate controlled by APULSEW and APULSER is implemented by the CE only. By setting EXT_PULSE = 1, the MPU is providing the source for pulse generation. If EXT_PULSE is 0, W0SUM_X and VAR0SUM_X are the default pulse generation sources. In this case, creep cannot be controlled since it is an MPU function. The maximum pulse rate is 3*FS = 7.5 kHz. See 2.3.6.2 VPULSE and WPULSE (page 27) for details on how to adjust the timing of the output pulses. The maximum time jitter is 1/6 of the multiplexer cycle period (nominally 67 s) and is independent of the number of pulses measured. Thus, if the pulse generator is monitored for one second, the peak jitter is 67 ppm. After 10 seconds, the peak jitter is 6.7 ppm. The average jitter is always zero. If it is attempted to drive either pulse generator faster than its maximum rate, it simply outputs at its maximum rate without exhibiting any rollover characteristics. The actual pulse rate, using WSUM as an example, is: RATE = WRATE WSUM FS X Hz , 2 46 where FS = sampling frequency (2184.53 Hz), X = Pulse speed factor derived from the CE variables PULSE_SLOW (CE RAM 0x20[0]) and PULSE_FAST (CE RAM 0x20[1]). Table 85: CE Pulse Generation Parameters CE Address Name Default 0x21 WRATE 227 0x22 KVAR 6444 0x23 SUM_PRE 2184 0x45 APULSEW 0 0x46 WPULSE_CTR 0 0x47 WPULSE_ FRAC 0 0x48 0x49 0x4A WSUM_ ACCUM APULSER VPULSE_CTR 0 0 0 0x4B VPULSE_ FRAC 0 0x4C VSUM_ACCUM 0 Description Kh = VMAX*IMAX*K / (WRATE*NACC*X) Wh/pulse where: K = 76.3594 when used with local sensors (CT or shunt) K = 54.5793 when used with 71M6xx3 remote sensors Scale factor for VAR measurement. Number of samples per accumulation interval, as specified in SUM_SAMPS[12:0], I/O RAM 0x2107[4:0], 0x2108[7:0] (NACC). Wh pulse (WPULSE) generator input to be updated by the MPU when using external pulse generation. The output pulse rate is: -32 -14 APULSEW * FS * 2 * WRATE * X * 2 . This input is buffered and can be updated by the MPU during a conversion interval. The change takes effect at the beginning of the next interval. Counter for WPULSE output. Unsigned numerator, containing a fraction of a pulse. The value in this register always counts up towards the next pulse. Roll-over accumulator for WPULSE. VARh (VPULSE) pulse generator input. Counter for VPULSE output. Unsigned numerator, containing a fraction of a pulse. The value in this register always counts up towards the next pulse. Roll-over accumulator for VPULSE. Other CE Parameters Table 86 shows the QUANT CE parameters used for suppression of noise due to scaling and truncation effects. The equations for calculating the LSB weight of each QUANT parameter are provided at the bottom of Table 86. 128 (c) 2008-2011 Teridian Semiconductor Corporation v1.2 71M6543F/H and 71M6543G/GH Data Sheet Table 86: CE Parameters for Noise Suppression and Code Version CE Address 0x26 0x27 0x28 0x2A 0x2B 0x2C 0x2E 0x2F 0x30 Name Default QUANT_IA QUANT_WA QUANT_VARA QUANT_IB QUANT_WB QUANT_VARB QUANT_IC QUANT_WC QUANT_VARC 0 0 0 0 0 0 0 0 0 Description Compensation factors for truncation and noise in current, real energy and reactive energy for phase A. Compensation factors for truncation and noise in current, real energy and reactive energy for phase B. Compensation factors for truncation and noise in current, real energy and reactive energy for phase C. Compensation factors for truncation and noise in current for phase D. LSB weights for use with the 71M6xx3 isolated sensors: 0x31 QUANT_ID 0 QUANT _ Ix _ LSB = 5.20864 10 -10 IMAX 2 ( Amps 2 ) QUANT _ Wx _ LSB = 8.59147 10 -10 VMAX IMAX (Watts) QUANT _ VARx _ LSB = 8.59147 10 -10 VMAX IMAX (Vars) LSB weights for use with Current Transformers (CTs): QUANT _ Ix _ LSB = 5.08656 10 -13 IMAX 2 ( Amps 2 ) QUANT _ Wx _ LSB = 1.04173 10 -9 VMAX IMAX (Watts) QUANT _ VARx _ LSB = 1.04173 10 -9 VMAX IMAX (Vars) v1.2 (c) 2008-2011 Teridian Semiconductor Corporation 129 71M6543F/H and 71M6543G/GH Data Sheet 5.4.10 CE Calibration Parameters Table 87 lists the parameters that are typically entered to effect calibration of meter accuracy. Table 87: CE Calibration Parameters CE Address Name Defau lt Description 0x10 0x11 0x13 0x14 0x16 0x17 0x19 CAL_IA CAL_VA CAL_IB CAL_VB CAL_IC CAL_VC CAL_ID 16384 16384 16384 16384 16384 16384 16384 These constants control the gain of their respective channels. The 14 nominal value for each parameter is 2 = 16384. The gain of each channel is directly proportional to its CAL parameter. Thus, if the gain of a channel is 1% low, CAL should be increased by 1%. 0x12 PHADJ_A 0 0x15 PHADJ_B 0 0x18 PHADJ_C 0 0x12 DLYADJ_A 0 These constants control the CT phase compensation. No compensation occurs when PHADJ_X = 0. As PHADJ_X is increased, more compensation (lag) is introduced. The range is 215 - 1. If it is desired to delay the current by the angle , the equations are: 0.029615TAN at 60Hz PHADJ _ X = 2 20 0.1714 - 0.0168 TAN 0.0206 TAN at 50Hz 0.1430 - 0.01226 TAN The shunt delay compensation is obtained using the equation provided below: PHADJ _ X = 2 20 2f 2f + 2ab cos a 2 cos 2 f 2 s fs DLYADJ _ X = deg rees (1 + 0.1 deg rees )214 360 2f c sin fs + b where: a = 2A 0x15 DLYADJ_B 0 b = A2 + 1 2 +2 f is the mains frequency fs is the sampling frequency = 22 + 4 0x18 DLYADJ_C 0 The table below provides the value of A for each channel: Value of A Channel (decimal) D YADJ_A 13840 DLYADJ_B 11693 DLYADJ_C 9359 Note: The current sensor inputs are not assigned to the A, B and C phases in a fixed manner. The assignments of phases A, B and C depends on how the IADC0-1, IADC2-3, IADC4-5, IADC6-7 current sensing inputs are connected in the meter design. The CE code must be aware of these connections. See Figure 31 and Figure 32 for typical meter configurations. VADC8, VADC9 and VADC10 are assigned to voltage phases VA, VB and VC in a fixed manner, respectively. The CE addresses listed in this table are assigned to phases A, B and C as indicated by their names. 130 (c) 2008-2011 Teridian Semiconductor Corporation v1.2 71M6543F/H and 71M6543G/GH Data Sheet 5.4.11 CE Flow Diagrams Figure 39 through Figure 41 show the data flow through the CE in simplified form. Functions not shown include delay compensation, sample interpolation, scaling and the processing of meter equations. multiplexer IA VA IB VB IC VC VREF mod de-multiplexer IA_RAW VA_RAW IB_RAW VB_RAW IC_RAW VC_RAW ID_RAW Decimator ID FS= 2184 Hz FS= 2184 Hz Figure 39: CE Data Flow: Multiplexer and ADC Figure 40: CE Data Flow: Scaling, Gain Control, Intermediate Variables for one Phase v1.2 (c) 2008-2011 Teridian Semiconductor Corporation 131 71M6543F/H and 71M6543G/GH Data Sheet SUM WA WB WC VARA VARB VARC WASUM_X WBSUM_X WCSUM_X VARASUM_X VARBSUM_X VARCSUM_X I2 V2 IASQ IBSQ ICSQ VASQ VBSQ VCSQ IDSQ F0 SUM v SQUARE IA IB IC VA VB VC ID MPU SUM_SAMPS = 2184 IASQSUM_X IBSQSUM_X ICSQSUM_X VASQSUM_X VBSQSUM_X VCSQSUM_X IDSQSUM_X F0 Figure 41: CE Data Flow: Squaring and Summation Stages 132 (c) 2008-2011 Teridian Semiconductor Corporation v1.2 71M6543F/H and 71M6543G/GH Data Sheet 6 71M6543 Specifications This section provides the electrical specifications for the 71M6543. Please refer to the 71M6xxx Data Sheet for the 71M6xx3 electrical specifications, pin-out and package mechanical data. 6.1 Absolute Maximum Ratings Table 88 shows the absolute maximum ratings for the device. Stresses beyond Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation at these or any other conditions beyond those indicated under recommended operating conditions (See 6.3) is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to GNDA. Table 88: Absolute Maximum Ratings Voltage and Current Supplies and Ground Pins V3P3SYS, V3P3A VBAT, VBAT_RTC GNDD Analog Output Pins -0.5 V to +4.6 V -0.5 V to +4.6 V -0.1 V to +0.1 V -10 mA to +10 mA, -0.5 V to V3P3A+0.5 V -10 mA to +10 mA, -0.5 to +3.0 V -10 mA to +10 mA, -0.5 V to 4.6 V -10 mA to +10 mA, -0.5 V to +6 V VREF VDD V3P3D VLCD Analog Input Pins IADC0, IADC1, IADC2, IADC3, IADC4, IADC5, IADC6, IADC7, VADC8, VADC9 and VADC10 -10 mA to +10 mA -0.5 V to V3P3A+0.5 V -10 mA to +10 mA -0.5 V to +3.0 V XIN, XOUT SEG and SEGDIO Pins Configured as SEG or COM drivers Configured as Digital Inputs Configured as Digital Outputs -1 mA to +1 mA, -0.5 V to VLCD+0.5 V -10 mA to +10 mA, -0.5 V to +6 V -10 mA to +10 mA, -0.5 V to V3P3D+0.5 V Digital Pins Inputs (PB, RESET, RX, ICE_E, TEST) Outputs (TX) Temperature Operating junction temperature (peak, 100ms) Operating junction temperature (continuous) Storage temperature Soldering temperature - 10 second duration v1.2 (c) 2008-2011 Teridian Semiconductor Corporation -10 mA to +10 mA, -0.5 to 6 V -10 mA to +10 mA, -0.5 V to V3P3D+0.5 V 140 C 125 C -45 C to +165 C 250 C 133 71M6543F/H and 71M6543G/GH Data Sheet 6.2 Recommended External Components Table 89: Recommended External Components Name From To C1 V3P3A GNDA C2 CSYS V3P3D V3P3SYS GNDD GNDD CVDD VDD CVLCD Value Unit Bypass capacitor for 3.3 V supply Bypass capacitor for 3.3 V output 0.1 20% 0.1 20% F F GNDD Bypass capacitor for V3P3SYS Bypass capacitor for VDD 1.0 30% 0.1 20% F F VLCD GNDD Bypass capacitor for VLCD pin 0.1 20% F XTAL XIN XOUT 32.768 kHz CXS XIN GNDA 15 10% pF CXL XOUT GNDA 10 10% pF 6.3 Function 32.768 kHz crystal - electrically equivalent to ECS .327-12.5-17X or Vishay XT26T, load capacitance 12.5 pF Load capacitor values for crystal depend on crystal specifications and board parasitics. Nominal values are based on 4 pF board capacitance and include an allowance for chip capacitance. Recommended Operating Conditions Unless otherwise specified, all parameters listed under 6.4 Performance Specifications and 6.5 Timing Specifications are valid over the Recommended Operating Conditions provided in Table 90 below. Table 90: Recommended Operating Conditions Parameter Condition V3P3SYS and V3P3A Supply Voltage for precision metering operation (MSN mode). Voltages at VBAT and VBAT_RTC need not be present. VBAT=0 V to 3.8 V VBAT_RTC =0 V to 3.8 V V3P3SYS < 2.8 V and Max(VBAT_RTC, V3P3SYS) > 2.0 V VBAT Voltage (BRN mode). V3P3SYS is below the 2.8 V comparator threshold. Either V3P3SYS or VBAT_RTC must be high enough to power the RTC module. VBAT_RTC Voltage. VBAT_RTC is not needed to support the RTC and non-volatile memory unless V3P3SYS<2.0 V Operating Temperature V3P3SYS<2.0 V Min Typ Max Unit 3.0 3.6 V 2.5 3.8 V 2.0 3.8 V -40 +85 C Notes: 1. GNDA and GNDD must be connected together. 2. V3P3SYS and V3P3A must be connected together. 134 (c) 2008-2011 Teridian Semiconductor Corporation v1.2 71M6543F/H and 71M6543G/GH Data Sheet 6.4 Performance Specifications 6.4.1 Input Logic Levels Table 91: Input Logic Levels Parameter Condition Min 1 Digital high-level input voltage , VIH Digital low-level input voltage1, VIL Input pullup current, IIL E_RXTX, E_RST, E_TCLK OPT_RX, OPT_TX SPI_CSZ (SEGDIO36) Other digital inputs Input pull down current, IIH ICE_E, RESET, TEST Other digital inputs Typ Max Unit 0.8 V V A A A A A A 2 VIN=0 V, ICE_E=3.3 V 10 10 10 -1 0 100 100 100 1 10 -1 0 100 1 VIN=V3P3D Note: 1. In battery powered modes, digital inputs should be below 0.1 V or above VBAT - 0.1 V to minimize battery current. 6.4.2 Output Logic Levels Table 92: Output Logic Levels Parameter Condition Digital high-level output voltage VOH Digital low-level output voltage VOL ILOAD = 1 mA ILOAD = 15 mA (see notes 1, 2) ILOAD = 1 mA ILOAD = 15 mA (see note 1) Min Typ Max V3P3D-0.4 V3P3D-0.6 0 0 Unit V V 0.4 0.8 V V Note: 1. Guaranteed by design; not production tested. 2. Caution: The sum of all pull up currents must be compatible with the on-resistance of the internal V3P3D switch. See 6.4.6 V3P3D Switch on page 139. v1.2 (c) 2008-2011 Teridian Semiconductor Corporation 135 71M6543F/H and 71M6543G/GH Data Sheet 6.4.3 Battery Monitor Table 93: Battery Monitor Performance Specifications (TEMP_BAT = 1) Parameter Condition MSN mode, TEMP_PWR = 1 BV: Battery Voltage (definition) BRN mode, TEMP_PWR=TEMP_BSEL VBAT = 2.0 V 2.5 V 3.0 V 4.0 V Measurement Error BV 100 - 1 VBAT Input impedance in continuous measurement, MSN mode. V(VBAT_RTC)/I(VBAT_RTC) Load applied with BCURR IBAT(BCURR=1) - IBAT(BCURR=0) 136 V3P3 = 3.3 V, TEMP_BSEL = 0, TEMP_PER = 111, VBAT_RTC = 3.6 V, V3P3 = 3.3 V Min Typ Max = 3.3 + ( - 142) 0.0246 + 297 = 3.291 + ( - 142) 0.0255 + 328 7.5 5 3 5 -7.5 -5 -3 -3 1 50 Unit V % % % % M 100 (c) 2008-2011 Teridian Semiconductor Corporation 140 A v1.2 71M6543F/H and 71M6543G/GH Data Sheet 6.4.4 Temperature Monitor Table 94: Temperature Monitor Parameter Condition Temperature Measurement Equation for 71M6543F and 71M6543G (see notes 2 and 4) In MSN, TEMP_PWR=1: Min Temperature Measurement Equation for 71M6543H and 71M6543GH (see notes 3 and 4) In MSN, TEMP_PWR=1: Typ Max Unit = 0.325 + 22 In BRN, TEMP_PWR = TEMP_BSEL: = 0.325 + 0.00218 2 - 0.609 + 64.4 If STEMP 0: If STEMP > 0: = 0.325 + 22 = C 63 + 22 _85 In BRN, TEMP_PWR = TEMP_BSEL: If STEMP 0: = 0.325 + 0.00218 2 - 0.609 + 64.4 If STEMP > 0: Temperature Error (71M6543) (see note 1) VBAT_RTC charge per measurement = 63 + 0.00218 2 - 0.609 + 64.4 _85 TA = 22C -2 TEMP_BSEL = 0, TEMP_PWR=0, SLP Mode, VBAT_RTC = 3.6 V Duration of temperature measurement after setting TEMP_START (see note 1) Notes: 1. Guaranteed by design; not production tested. 2. For the 71M6543F and 71M6543G, TEMP_85 fuses read 0. 3. For the 71M6543H and 71M6543GH, TEMP_85 fuses 0. 4. The coefficients provided in these equations are typical. v1.2 2 16 15 (c) 2008-2011 Teridian Semiconductor Corporation C C 60 ms 137 71M6543F/H and 71M6543G/GH Data Sheet 6.4.5 Supply Current The supply currents provided in Table 95 below include only the current consumed by the 71M6543. Refer to the 71M6xxx Data Sheet for additional current required when using a 71M6x03 remote sensor. Table 95: Supply Current Performance Specifications Parameter Condition I1: V3P3A + V3P3SYS current, Normal Operation Polyphase: 4 Currents, 3 Voltages V3P3A = V3P3SYS = 3.3 V, MPU_DIV [2:0]= 3 (614 kHz MPU clock), No Flash memory write, RTM_E=0, PRE_E=0, CE_E=1, ADC_E=1, ADC_DIV=0, MUX_DIV[3:0]=7, FIR_LEN[1:0]=1, PLL_FAST=1 I1a: V3P3A + V3P3SYS current, ADC Half Rate (ADC_DIV=1) I1b: V3P3A + V3P3SYS current, Normal Operation PLL_FAST=0 Device Same as I1, except ADC_DIV=1, FIR_LEN=0 Same as I1, except PRE_E=1 I1d: V3P3A + V3P3SYS current, Normal Operation PRE_E=1, ADC_DIV=1, FIR_LEN=0. (see note 1) Same as I1, except PRE_E=1, ADC_DIV=1, FIR_LEN=0. I1e: V3P3A + V3P3SYS current, Normal Operation PLL_FAST=0, PRE_E=1. (see note 1) Same as I1, except PRE_E=1, PLL_FAST=0. Same as I1, except with variation of MPU_DIV[2:0]. VBAT current I3: MSN Mode I4: BRN Mode CE_E=0 I5: LCD Mode (ext. VLCD) I6: LCD Mode (boost, DAC) I7: LCD Mode (DAC) I8: LCD Mode (VBAT) I9: SLP Mode LCD_VMODE[1:0]=3, also see note 3 LCD_VMODE[1:0]=2, also see notes 1, 2 LCD_VMODE[1:0]=1, also see notes 1, 2 LCD_VMODE[1:0]=0, also see notes 1, 2 SLP Mode VBAT_RTC current I10: MSN I11: BRN I15: V3P3A + V3P3SYS current, Write Flash with ICE Notes: 1. 2. 3. 138 Max 7.2 8.5 LCD_VMODE[1:0]=2, also see note 3 TA 25 C TA = 85 C Same as I1, except write Flash at maximum rate, CE_E=0, ADC_E=0. Unit mA 71M6543G/GH 7.5 8.8 71M6543F/H 6.4 7.3 71M6543G/GH 6.7 7.7 71M6543F/H 2.9 3.8 71M6543G/GH 3.0 3.9 71M6543F/H 7.3 8.7 71M6543G/GH 7.7 9.1 71M6543F/H 6.5 7.5 71M6543G/GH 6.9 7.9 71M6543F/H 3.0 3.9 71M6543G/GH 3.1 3.9 71M6543F/H 0.4 0.6 mA mA mA mA mA mA/ MHz I MPU_DIV = 0 - I MPU_DIV = 3 4.3 I12: LCD Mode I13: SLP Mode I14: SLP Mode (see note 1) 71M6543F/H Typ Same as I1, except PLL_FAST=0 I1c: V3P3A + V3P3SYS current, Normal Operation PRE_E=1 I2: V3P3A + V3P3SYS dynamic current Min 71M6543G/GH 0.5 0.65 0 2.4 2.6 0.4 24 3.0 1.1 0 300 3.2 3.5 108 36 11 3.4 +300 nA mA mA nA A A A nA 0 240 260 1.8 0.7 1.5 300 410 420 4.1 1.7 3.2 nA nA nA A A A 71M6543F/G 7.1 8.7 71M6543G/GH 7.3 8.7 71M6543 71M6543F/H 71M6543G/GH 71M6543 71M6543 71M6543 71M6543 71M6543 -300 71M6543 71M6543F/G 71M6543G/GH 71M6543 71M6543 71M6543 -300 -300 mA Guaranteed by design; not production tested. LCD_DAC[4:0]=5 (2.9V), LCD_CLK[1:0]=2, LCD_MODE[2:0]=6, all LCD_MAPn bits = 0. LCD_DAC[4:0]=5 (2.9V), LCD_CLK[1:0]=2, LCD_MODE[2:0]=6, LCD_BLANK=0, LCD_ON=1, all LCD_MAPn bits = 1 and VLCD pin = 3.3V. (c) 2008-2011 Teridian Semiconductor Corporation v1.2 71M6543F/H and 71M6543G/GH Data Sheet 6.4.6 V3P3D Switch Table 96: V3P3D Switch Performance Specifications Parameter Condition On resistance - V3P3SYS to V3P3D On resistance - VBAT to V3P3D | IV3P3D | 1 mA | IV3P3D | 1 mA, VBAT>2.5V V3P3SYS = 3V V3P3D = 2.9V VBAT = 2.6V V3P3D = 2.5V V3P3D IOH, MSN V3P3D IOH, BRN 6.4.7 Min Typ Max Unit 10 10 10 mA 10 mA Internal Power Fault Comparators Table 97: Internal Power Fault Comparators Performance Specifications Parameter Condition Overall response time 100mV overdrive, falling 100mV overdrive, rising Falling Threshold 3.0 V Comparator 2.8 V Comparator Difference 3.0V and 2.8V Comparators Falling Threshold 2.25 V Comparator 2.0 V Comparator VDD (@VBAT=3.0V) - 2.25V Comparator Difference 2.25V and 2.0V Comparators Hysteresis, (Rising Threshold - Falling Threshold) 3.0 V Comparator 2.8 V Comparator 2.25 V Comparator 2.0 V Comparator 6.4.8 Min V3P3 falling VDD falling Typ 20 Max Unit 200 200 s s 2.83 2.75 50 2.93 2.81 136 3.03 2.87 220 V V mV 2.2 1.90 0.25 0.15 2.25 2.00 0.35 0.25 2.5 2.20 0.45 0.35 V V V V 22 25 10 10 45 42 33 28 65 60 60 60 mV mV mV mV TA = 22 C 2.5 V Voltage Regulator - System Power Table 98: 2.5 V Voltage Regulator Performance Specifications Parameter Condition V2P5 V2P5 load regulation Voltage overhead V3P3SYS-V2P5 v1.2 V3P3 = 3.0 V - 3.8 V ILOAD = 0 mA V3P3 = 3.3 V ILOAD = 0 mA to 5 mA ILOAD = 5 mA, Reduce V3P3D until V2P5 drops 200 mV Min Typ Max Unit 2.55 2.65 2.75 V 40 mV 440 mV (c) 2008-2011 Teridian Semiconductor Corporation 139 71M6543F/H and 71M6543G/GH Data Sheet 6.4.9 2.5 V Voltage Regulator - Battery Power Table 99: Low-Power Voltage Regulator Performance Specifications Parameter Condition V2P5 V2P5 load regulation Voltage Overhead 2V - VBAT-VDD VBAT = 3.0 V - 3.8 V, V3P3 = 0 V, ILOAD = 0 mA VBAT = 3.3 V, V3P3 = 0 V, ILOAD = 0 mA to 1 mA ILOAD = 0ma, VBAT = 2.0 V, V3P3 = 0 V. Min Typ Max Unit 2.55 2.65 2.75 V 40 mV 200 mV Max 1 Unit W 3 pF 6.4.10 Crystal Oscillator Table 100: Crystal Oscillator Performance Specifications Parameter Maximum Output Power to Crystal XIN to XOUT Capacitance (see note 1) Capacitance change on XOUT Condition Crystal connected, see note 1 Min Typ RTC_ADJ = 7F to 0, Bias voltage = unbiased Vpp = 0.1 V 15 pF Note: 1. Guaranteed by design; not production tested. 6.4.11 Phase-Locked Loop (PLL) Table 101: PLL Performance Specifications PARAMETER PLL Power-up Settling Time PLL_FAST settling time PLL_FAST rise PLL_FAST fall PLL SLP to MSN Settling Time CONDITION PLL_FAST =0, V3P3 = 0 to 3.3 V step Measured from first edge of MCK (TMUX2OUT pin) V3P3=0, VBAT=3.8 to 2.0 V MIN TYP PLL_FAST =0 MAX UNIT 3 ms 3 3 3 ms ms ms 6.4.12 LCD Drivers Table 102: LCD Drivers Performance Specifications PARAMETER VLCD Current CONDITION MIN TYP VLCD=3.3, all LCD map bits=0 VLCD=5.0, all LCD map bits=0 MAX 2 3 UNIT uA uA Note: 1. These specifications apply to all COM and SEG pins. 1. LCD_VMODE=3, LCD_ON=1, LCD_BLANK=0, LCD_MODE=6, LCD_CLK=2. 2. Output load is 74 pF per SEG and COM pin. 6.4.13 VLCD Generator Table 103: VLCD Generator Specifications 140 (c) 2008-2011 Teridian Semiconductor Corporation v1.2 71M6543F/H and 71M6543G/GH Data Sheet Parameter VSYS to VLCD switch impedance VBAT to VLCD switch impedance LCD Boost Frequency VLCD IOH current (VLCD(0)-VLCD(IOH)<0.25) Condition V3P3 = 3.3 V, RVLCD=removed, LCD_BAT=0, LCD_VMODE[1:0]=0, ILCD=10 A V3P3 = 0 V, VBAT = 2.5 V, RVLCD =removed, LCD_BAT =1, LCD_VMODE[1:0]=0, ILCD=10 A LCD_VMODE[1:0] = 2, RVLCD = removed, CVLCD = removed PLL_FAST=1 PLL_FAST=0 LCD_VMODE[1:0] = 2, LCD_CLK[1:0] = 2, RVLCD = removed, V3P3 = 3.3V, LCD_DAC[4:0] = 1F Min Typ Max Unit 750 700 820 786 kHz kHz 10 A From LCDADJ0 and LCDADJ12 fuses: 12 - 0 _ 12 _ + (_) (_) = 2.65 + 2.65 31 The above equations describe the nominal value of VLCD for a specific LCD_DAC value. The specifications below list the maximum deviation between actual VLCD and VLCDnom. Note that when VCC and boost are insufficient, the LCD DAC will not reach its target value and a large negative error will occur. (_) = 5 0 + LCD_DAC Error. VLCD-VLCDnom Full Scale, with Boost V3P3 =3.6 V V3P3 =3.0 V VBAT=4.0 V, V3P3=0, BRN Mode VBAT=2.5 V, V3P3=0, BRN Mode LCD_DAC Error. VLCD-VLCDnom DAC=12, with Boost V3P3 = 3.6 V V3P3 = 3.0 V VBAT = 2.5 V, V3P3 = 0 V, BRN Mode LCD_DAC Error. VLCD-VLCDnom Zero Scale, with Boost V3P3 = 3.6 V V3P3 = 3.0 V VBAT = 4.0 V, V3P3 = 0 V, BRN Mode VBAT = 2.5 V, V3P3 = 0 V, BRN Mode LCD_DAC Error. VLCD-VLCDnom Full Scale, no Boost V3P3 = 3.6 V (see note 1) V3P3 = 3.0 V (see note 1) VBAT = 4.0 V, V3P3 = 0 V, BRN Mode VBAT = 2.5 V, V3P3 = 0 V, BRN Mode LCD_DAC Error. VLCD-VLCDnom DAC=12, no Boost V3P3 = 3.6 V V3P3 = 3.0 V VBAT = 4.0 V, V3P3 = 0 V, BRN Mode VBAT = 2.5 V, V3P3 = 0 V, BRN Mode v1.2 LCD_VMODE = 10, LCD_DAC[4:0] = 1F, LCD_CLK[1:0]=2, LCD_MODE[2:0]=6 LCD_VMODE = 10, LCD_DAC[4:0] = C, LCD_CLK[1:0]=2, LCD_MODE[2:0]=6 LCD_VMODE = 2, LCD_DAC[4:0] =0, LCD_CLK[1:0]=2, LCD_MODE[2:0]=6 LCD_VMODE = 1, LCD_DAC[4:0] = 1F, LCD_CLK[1:0]=2, LCD_MODE[2:0]=6 LCD_VMODE = 1, LCD_DAC[4:0] = C, LCD_CLK[1:0]=2, LCD_MODE[2:0]=6 -0.15 -0.4 -0.15 -1.3 0.15 0.15 0.15 V V V V -0.15 -0.15 -0.15 0.15 0.15 0.15 V V V -0.15 -0.15 -0.15 -0.15 0.15 0.15 0.15 0.15 V V V V -2.1 -2.8 -1.8 -3.2 V V V V -0.5 -1.1 1 -0.15 1 -1.5 V V V V (c) 2008-2011 Teridian Semiconductor Corporation 1 0.15 141 71M6543F/H and 71M6543G/GH Data Sheet Parameter Condition Min Typ Max Unit LCD_DAC Error. VLCD-VLCDnom LCD_VMODE = 01, LCD_DAC[4:0] = 0, Zero Scale, no Boost -0.15 0.15 V LCD_CLK[1:0]=2, V3P3 = 3.6 V -0.15 0.15 LCD_MODE[2:0]=6 V V3P3 = 3.0 V -0.15 0.15 V VBAT = 4.0 V, V3P3 = 0 V, BRN Mode -0.45 0.15 V VBAT = 2.5 V, V3P3 = 0 V, BRN Mode LCD_DAC Error. VLCD-VLCDnom LCD_VMODE = 1, LCD_DAC[4:0] = 1F, Full Scale, with Boost, LCD mode LCD_CLK[1:0]=2, -0.15 0.15 V VBAT = 4.0 V, V3P3 = 0 V LCD_MODE[2:0]=6 -1.3 V VBAT = 2.5 V, V3P3 = 0 V Note: 1. Guaranteed by design; not production tested. 2. The following test conditions also apply to all parameters provided in this table: bypass capacitor CVLCD 0.1 F, test load RVLCD = 500 k, no display, all SEGDIO pins configured as DIO. 142 (c) 2008-2011 Teridian Semiconductor Corporation v1.2 71M6543F/H and 71M6543G/GH Data Sheet 6.4.14 71M6543 VREF Table 104 shows the performance specifications for the 71M6543 ADC reference voltage (VREF). Table 104: 71M6543 VREF Performance Specifications Parameter Condition VREF output voltage, VREF(22) VREF output voltage, VREF(22) TA = 22 C Min Typ Max Unit 1.193 1.195 1.197 V PLL_FAST=0 1.195 V VREF chop step, trimmed VREF(CHOP=01) - VREF(CHOP=10) -10 10 mV VREF power supply sensitivity VREF / V3P3A V3P3A = 3.0 to 3.6 V -1.5 1.5 mV/V VREF_DIS = 1, VREF = 1.3 V to 1.7 V VREF_CAL = 1, ILOAD = 10 A, -10 A VREF input impedance VREF output impedance VNOM definition (see note 2) k 100 k 3.2 VNOM (T ) = VREF (22) + (T - 22)TC1 + (T - 22) 2 TC 2 V If temperature characterization trim information is available (71M6543H and 71M6543GH, 0.1%) VNOM temperature coefficients: 35.091+0.01764TRIMT+1.587(TRIMBGB - TRIMBGD) TC1 = V/C TC2 = VREF(T) deviation from VNOM(T) (see note 1): VREF (T ) - VNOM (T ) 106 VNOM (T ) 62 -0.557 - 2.8 10-4 V/C2 -10 +10 ppm/C If temperature characterization trim information is not available (71M6543F and 71M6543G , 0.5%) VNOM temperature coefficients: TC1 = V/C 275 - 4.95 TRIMT 2 TC2 = V/C -0.557 + 0.00028 TRIMT VREF(T) deviation from VNOM(T) (see note 1): VREF (T ) - VNOM (T ) 106 VNOM (T ) 62 -40 +40 ppm/C 25 VREF aging ppm/ year Notes: 1. Guaranteed by design; not production tested. 2. This relationship describes the nominal behavior of VREF at different temperatures, as st nd governed by a second order polynomial of 1 and 2 order coefficients TC1 and TC2. 3. For the parameters in this table, unless otherwise specified, VREF_DIS = 0, PLL_FAST=1 v1.2 (c) 2008-2011 Teridian Semiconductor Corporation 143 71M6543F/H and 71M6543G/GH Data Sheet 6.4.15 ADC Converter Table 105: ADC Converter Performance Specifications Parameter Condition Recommended Input Range (Vin - V3P3A) Voltage to Current Crosstalk 6 10 *Vcrosstalk cos(Vin - Vcrosstalk ) Vin (see note 1) Input Impedance, no pre-amp ADC Gain Error vs %Power Supply Variation 10 6 Nout PK 357nV / VIN 100 V 3P3 A / 3.3 Input Offset IADC0=IADC1=V3P3A IADC0=V3P3A THD @ 250mVpk Name FIR_LEN A B C D E F G H J ADC_DIV 0 1 0 1 2 0 0 1 2 0 0 0 0 0 1 1 1 1 PLL_FAST 0 0 1 1 1 0 1 1 1 MUX_DIV 3 2 11 6 4 2 6 3 2 FIR_LEN A B C D E F G H J ADC_DIV 0 1 0 1 2 0 0 1 2 0 0 0 0 0 1 1 1 1 PLL_FAST 0 0 1 1 1 0 1 1 1 MUX_DIV 3 2 11 6 4 2 6 3 2 Typ Max Unit -250 250 mV peak -10 10 V/V 40 90 k 50 ppm / % 10 10 mV mV Vin=200 mV pk, 65 Hz V3P3A=3.0 V, 3.6 V DIFF0_E=1, PRE_E=0 DIFF0_E=0, PRE_E=0 THD @ 20mVpk Name Vin = 200 mV peak, 65 Hz, on VADC8 (VA) or VADC9 (VB) or VADC10 (VC). Vcrosstalk = largest measurement on IADC0-1 or IADC2-3 or IADC4-5 or IADC6-7 Vin=65 Hz Min -10 -10 VIN = 65Hz, 250mVpk, 64kpts FFT, Blackman Harris Window. A B C D E F G H J VIN = 65Hz, 20mVpk, 64kpts FFT, Blackman Harris Window. -82 -84 -83 -86 A B C D E F G H J -75 -75 -75 -75 -75 -75 -75 -75 -75 dB A B C D E F G H J -85 -91 -85 -91 -93 -85 -85 -91 -93 dB A B C D E F G H J 3470 406 3040 357 151 3470 3040 357 151 nV LSB Size: Name A B C D E F G H J FIR_LEN ADC_DIV 0 1 0 1 2 0 0 1 2 0 0 0 0 0 1 1 1 1 PLL_FAST 0 0 1 1 1 0 1 1 1 MUX_DIV 3 2 11 6 4 2 6 3 2 Digital Full-Scale: Name A B C D E F G H J 144 FIR_LEN 0 1 0 1 2 0 0 1 2 ADC_DIV 0 0 0 0 0 1 1 1 1 PLL_FAST 0 0 1 1 1 0 1 1 1 MUX_DIV 3 2 11 6 4 2 6 3 2 Vin=65Hz, 20mVpk, 64kpts FFT, BlackmanHarris window A: 91125 B: 778688 C: 103823 D: 884736 E: 2097152 F: 91125 G: 103823 H: 884736 J: 2097152 (c) 2008-2011 Teridian Semiconductor Corporation LSB v1.2 71M6543F/H and 71M6543G/GH Data Sheet Parameter Condition Min Typ Max Unit Note: 1. Guaranteed by design; not production tested. 2. Unless stated otherwise, the following test conditions apply to all the parameters provided in this table: FIR_LEN[1:0]=1, VREF_DIS=0, PLL_FAST=1, ADC_DIV=0, MUX_DIV=6, LSB values do not include the 9-bit left shift at CE input. 6.4.16 Pre-Amplifier for IADC0-IADC1 Table 106: Pre-Amplifier Performance Specifications PARAMETER Differential Gain Vin=30mV differential Vin=15mV differential (see note 1) Gain Variation vs V3P3 Vin=30mV differential (see note 1) Gain Variation vs Temp Vin=30mV differential (see note 1) Phase Shift, Vin=30mV differential (see note 1) Preamp input current IADC0 IADC1 Preamp+ADC THD Vin=30mV differential Vin=15mV differential CONDITION TA= 5C, V3P3=3.3 V, PRE_E=1, FIR_LEN=2, DIFF0_E=1, 2520Hz sample rate V3P3 = 2.97 V, 3.63 V TA = -40C, 85C TA=25C, V3P3=3.3 V PRE_E=1, FIR_LEN=10, DIFF0_E=1 2520Hz sample rate, IADC0=IADC1=V3P3 TA=25C, V3P3=3.3 V, PRE_E=1, FIR_LEN=2, DIFF0_E=1, 2520Hz sample rate. TA=25C, V3P3=3.3 V, PRE_E=1, FIR_LEN=10, DIFF0_E=1, 2520Hz sample rate Preamp Offset IADC0=IADC1=V3P3+30mV IADC0=IADC1= V3P3+15mV IADC0=IADC1= V3P3 IADC0=IADC1= V3P3-15mV IADC0=IADC1= V3P3-30mV Note: 1. Guaranteed by design; not production tested. v1.2 MIN TYP MAX UNIT 7.8 7.8 7.92 7.92 8.0 8.0 V/V V/V 100 ppm/% -80 ppm/C 6 m 16 16 uA uA -100 10 -25 -6 4 4 9 9 -82 -86 dB dB -0.63 -0.57 -0.56 -0.56 -0.55 mV mV mV mV mV (c) 2008-2011 Teridian Semiconductor Corporation 145 71M6543F/H and 71M6543G/GH Data Sheet 6.5 Timing Specifications 6.5.1 Flash Memory Table 107: Flash Memory Timing Specifications Parameter Condition Flash write cycles Flash data retention -40 C to +85 C 25 C 85 C Min Typ Max 20,000 100 10 Cycles Years Flash byte writes between page or mass erase operations Write Time per Byte Page Erase (1024 bytes) Mass Erase 6.5.2 Unit 2 Cycles 21 21 21 s ms ms SPI Slave Table 108. SPI Slave Timing Specifications Parameter SPI Setup Time SPI Hold Time SPI Output Delay SPI Recovery Time SPI Removal Time SPI Clock High SPI Clock Low SPI Clock Freq SPI Transaction Space 6.5.3 Condition SPI_DI to SPI_CK rise SPI_CK rise to SPI_DI SPI_CK fall to SPI_D0 SPI_CSZ fall to SPI_CK SPI_CK to SPI_CSZ rise SPI Freq/MPU Freq SPI_CSZ rise to SPI_CSZ fall Min 10 10 Typ Max 40 10 15 40 40 2.0 4.5 Unit ns ns ns ns ns ns ns MHz/MHz MPU Cycles EEPROM Interface Table 109: EEPROM Interface Timing Parameter Condition 2 Write Clock frequency (I C) Write Clock frequency (3-wire) 146 Min CKMPU = 4.9 MHz, Using interrupts CKMPU = 4.9 MHz, bit-banging DIO2/3 PLL_FAST = 0 CKMPU = 4.9 MHz PLL_FAST = 0 PLL_FAST = 1 (c) 2008-2011 Teridian Semiconductor Corporation Typ Max Unit 310 kHz 100 kHz 160 500 kHz v1.2 71M6543F/H and 71M6543G/GH Data Sheet 6.5.4 RESET Pin Table 110: RESET Pin Timing Parameter Condition Reset pulse width Reset pulse fall time (see note 1) Note: 1. Guaranteed by design; not production tested. 6.5.5 Min Typ Max Unit 1 s s 5 Real-Time Clock (RTC) Table 111: RTC Range for Date Parameter Range for date v1.2 Condition Min Typ Max Unit 2000 - 2255 year (c) 2008-2011 Teridian Semiconductor Corporation 147 71M6543F/H and 71M6543G/GH Data Sheet 6.6 100-Pin LQFP Package Outline Drawing Controlling dimensions are in mm. 15.7(0.618) 16.3(0.641) 1 15.7(0.618) 16.3(0.641) Top View 14.000 +/- 0.200 MAX. 1.600 1.50 +/- 0.10 0.225 +/- 0.045 0.50 TYP. 0.10 +/- 0.10 0.60 TYP> Side View Figure 42: 100-pin LQFP Package Outline 148 (c) 2008-2011 Teridian Semiconductor Corporation v1.2 71M6543F/H and 71M6543G/GH Data Sheet 71M6543 Pinout 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 SPI_CKI/SEGDIO39 SEGDIO40 SEGDIO41 SEGDIO42 SEGDIO43 SEGDIO44 SEGDIO45 TMUX2OUT/SEG46 TMUXOUT/SEG47 RESET PB VLCD VREF IADC0 IADC1 V3P3A VADC8 VADC9 VADC10 TEST GNDA NC NC NC XOUT 6.7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Teridian 71M6543F 71M6543H 71M6543G 71M6543GH 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 XIN NC NC GNDA VBAT_RTC VBAT V3P3SYS IADC2 IADC3 IADC4 IADC5 IADC6 IADC7 GNDD V3P3D VDD ICE_E E_RXTX/SEG48 E_TCLK/SEG49 E_RST/SEG50 RX TX OPT_TX/SEGDIO51 SEGDIO52 SEGDIO53 NC SEGDIO17 SEGDIO16 SEGDIO15 SEGDIO14 SEGDIO13 SEGDIO12 SEGDIO11 SEGDIO10 SEGDIO9 SEGDIO8/DI SEGDIO7/YPULSE SEGDIO6/XPULSE SEGDIO5 NC SEGDIO4 SEGDIO3/SDATA SEGDIO2/SDCK SEGDIO1/VPULSE SEGDIO0/WPULSE OPT_RX/SEGDIO55 SEGDIO54 NC NC NC 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 SPI_DI/SEGDIO38 SPI_DO/SEGDIO37 SPI_CSZ/SEGDIO36 SEGDIO35 SEGDIO34 SEGDIO33 SEGDIO32 SEGDIO31 SEGDIO30 SEGDIO29 SEGDIO28 COM0 COM1 COM2 COM3 SEGDIO27/COM4 SEGDIO26/COM5 SEGDIO25 SEGDIO24 SEGDIO23 SEGDIO22 SEGDIO21 SEGDIO20 SEGDIO19 SEGDIO18 Figure 43: Pinout for the LQFP-100 Package v1.2 (c) 2008-2011 Teridian Semiconductor Corporation 149 71M6543F/H and 71M6543G/GH Data Sheet 6.8 71M6543 Pin Descriptions 6.8.1 71M6543 Power and Ground Pins Pin types: P = Power, O = Output, I = Input, I/O = Input/Output. The circuit number denotes the equivalent circuit, as specified under Section 6.8.4 I/O Equivalent Circuits. Table 112: 71M6543 Power and Ground Pins Pin Name Type Circuit 72, 80 GNDA P -- 62 GNDD P -- 85 V3P3A P -- 69 V3P3SYS P -- 61 V3P3D O 13 60 VDD O -- 89 VLCD O -- 70 VBAT P 12 71 VBAT_RTC P 12 150 Function Analog Ground. This pin should be connected directly to the ground plane. Digital Ground. This pin should be connected directly to the ground plane. Analog Power Supply. A 3.3 V power supply should be connected to this pin. V3P3A must be the same voltage as V3P3SYS. System 3.3 V Supply. This pin should be connected to a 3.3 V power supply. Auxiliary Voltage Output of the Chip. In mission mode, this pin is connected to V3P3SYS by the internal selection switch. In BRN mode, it is internally connected to VBAT. V3P3D is floating in LCD and sleep mode. A bypass capacitor to ground should not exceed 0.1 F. Output of the 2.5 V Regulator. This pin is powered in MSN and BRN modes. A 0.1 F bypass capacitor to ground should be connected to this pin. Output of the LCD DAC. A 0.1 F bypass capacitor to ground should be connected to this pin. Battery Backup Pin to Support the Battery Modes (BRN, LCD). A battery or super capacitor is to be connected between VBAT and GNDD. If no battery is used, connect VBAT to V3P3SYS. RTC and Oscillator Power Supply. A battery or super-capacitor is to be connected between VBAT and GNDD. If no battery is used, connect VBAT_RTC to V3P3SYS. (c) 2008-2011 Teridian Semiconductor Corporation v1.2 71M6543F/H and 71M6543G/GH Data Sheet 6.8.2 71M6543 Analog Pins Pin types: P = Power, O = Output, I = Input, I/O = Input/Output. The circuit number denotes the equivalent circuit, as specified in Section 6.8.4. Table 113: 71M6543 Analog Pins Pin Name 87 86 IADC0 IADC1 68 67 IADC2 IADC3 Type IADC4 IADC5 64 63 IADC6 IADC7 84 VADC8 (VA) 83 VADC9 (VB) 82 VADC10 (VC) 88 VREF 75 76 v1.2 XIN XOUT Function Differential or Single-Ended Analog Line Current Sense Inputs. These pins are voltage inputs to the internal A/D converter. Typically, they are connected to the outputs of current sensors. Unused pins must be connected to V3P3A. I 66 65 Circuit 6 When configured as differential inputs (i.e., by setting the DIFFx_E control bits, where x = 0, 2, 4, 6) pins are paired to form differential inputs pairs: IADC0-IADC1, IADC2-IADC3, IADC4-IADC5, and IADC6-IADC7. IADC2-IADC3, IADC4-IADC5, and IADC6-IADC7 can be configured for communication with the 71M6xx3 remote isolated sensor interface (i.e., by setting the RMTx_E control bits, where x = 2, 4, 6). When configured as remote sensor interfaces, these pins form balanced digital pairs for bidirectional digital communications with a 71M6xx3 remote isolated sensor. I 6 Line Voltage Sense Inputs. These pins are voltage inputs to the internal A/D converter. Typically, they are connected to the outputs of resistor dividers. Unused pins must be connected to V3P3A. O 9 Voltage Reference for the ADC. This pin should be left unconnected (floating). 8 Crystal Inputs. A 32 kHz crystal should be connected across these pins. Typically, a 15 pF capacitor is also connected from XIN to GNDA and a 10 pF capacitor is connected from XOUT to GNDA. It is important to minimize the capacitance between these pins. See the crystal manufacturer data sheet for details. If an external clock is used, a 150 mV (p-p) clock signal should be applied to XIN, and XOUT should be left unconnected. I O (c) 2008-2011 Teridian Semiconductor Corporation 151 71M6543F/H and 71M6543G/GH Data Sheet 6.8.3 71M6543 Digital Pins Pin types: P = Power, O = Output, I = Input, I/O = Input/Output, N/C = no connect. The circuit number denotes the equivalent circuit, as specified in Section 6.8.4. Table 114: 71M6543 Digital Pins Pin Name Type Circuit 12-15 COM0-COM3 O 5 45 SEGDIO0/WPULSE 44 SEGDIO1/VPULSE 43 SEGDIO2/SDCK 42 SEGDIO3/SDATA 41 SEGDIO4 39 SEGDIO5 38 SEGDIO6/XPULSE 37 SEGDIO7/YPULSE 36 SEGDIO8/DI 35-27 SEGDIO[9:17] 25-18 SEGDIO[18:25] 11-4 SEGDIO[28:35] 99-94 SEGDIO[40:45] 52 SEGDIO52 51 SEGDIO53 47 SEGDIO54 17 SEGDIO26/COM5 3, 4, 5 Multiple-Use Pins. Configurable as either LCD segment driver or DIO. Alternative functions with proper selection of associated I/O RAM registers are: SEGDIO0 = WPULSE (45) SEGDIO1 = VPULSE (44) SEGDIO2 = SDCK (43) SEGDIO3 = SDATA (42) SEGDIO6 = XPULSE (38) SEGDIO7 = YPULSE (37) SEGDIO8 = DI (36) Unused pins must be configured as outputs or terminated to V3P3/GNDD. 16 SEGDIO27/COM4 3 SPI_CSZ/SEGDIO36 2 SPI_DO/SEGDIO37 1 SPI_DI/SEGDIO38 100 SPI_CKI/SEGDIO39 53 OPT_TX/SEGDIO51 46 OPT_RX/SEGDIO55 58 56 57 E_RXTX/SEG48 E_RST/SEG50 E_TCLK/SEG49 59 ICE_E 92 TMUXOUT/SEG47 93 TMUX2OUT/SEG46 152 I/O Function LCD Common Outputs. These four pins provide the select signals for the LCD display. I/O 3, 4, 5 Multiple-Use Pins. Configurable as either LCD segment driver or DIO with alternative function (LCD common drivers). I/O 3, 4, 5 Multiple-Use Pins. Configurable as either LCD segment driver or DIO with alternative function (SPI interface). I/O 3, 4, 5 Multiple-Use Pins, configurable as either LCD segment driver or DIO with alternative function (optical port/UART1) I/O 1, 4, 5 O 4, 5 Multiuse Pins. Configurable as either emulator port pins (when ICE_E pulled high) or LCD segment drivers (when ICE_E tied to GND). I 2 ICE Enable. When zero, E_RST, E_TCLK, and E_RXTX become SEG50, SEG49, and SEG48 respectively. For production units, this pin should be pulled to GND to disable the emulator port. O 4, 5 Multiple-Use Pins. Configurable as either multiplexer/clock output or LCD segment driver using the I/O RAM registers. (c) 2008-2011 Teridian Semiconductor Corporation v1.2 71M6543F/H and 71M6543G/GH Data Sheet Pin Name Type Circuit 91 RESET I 2 55 RX I 3 54 TX O 4 81 TEST I 7 90 PB I 3 26, 40, 48, 49, 50, 73, 74, 77, 78, 79 NC N/C -- v1.2 Function Chip Reset. This input pin is used to reset the chip into a known state. For normal operation, this pin is pulled low. To reset the chip, this pin should be pulled high. This pin has an internal 30 A (nominal) current source pulldown. No external reset circuitry is necessary. UART0 Input. If this pin is unused it must be terminated to V3P3D or GNDD. UART0 Output Enables Production Test. This pin must be grounded in normal operation. Pushbutton Input. This pin must be at GNDD when not active or unused. A rising edge sets the WF_PB flag. It also causes the part to wake up if it is in SLP or LCD mode. PB does not have an internal pullup or pulldown resistor. No Connection. Do not connect this pin. (c) 2008-2011 Teridian Semiconductor Corporation 153 71M6543F/H and 71M6543G/GH Data Sheet 6.8.4 I/O Equivalent Circuits V3P3D V3P3A V3P3D 110K Digital Input Pin from internal reference LCD SEG Output Pin LCD Driver CMOS Input VREF Pin GNDA GNDD GNDD LCD Output Equivalent Circuit Type 5: LCD SEG or pin configured as LCD SEG Digital Input Equivalent Circuit Type 1: Standard Digital Input or pin configured as DIO Input with Internal Pull-Up VREF Equivalent Circuit Type 9: VREF V3P3A V3P3D V3P3D Digital Input Pin CMOS Input Analog Input Pin GNDD GNDD V2P5 Equivalent Circuit Type 10: V2P5 Analog Input Equivalent Circuit Type 6: ADC Input Digital Input Type 2: Pin configured as DIO Input with Internal Pull-Down V3P3A V3P3D Comparator Input Pin To Comparator VLCD Pin LCD Drivers GNDA Digital Input Pin V2P5 Pin GNDA 110K GNDD from internal reference To MUX CMOS Input GNDD Comparator Input Equivalent Circuit Type 7: Comparator Input VLCD Equivalent Circuit Type 11: VLCD Power GNDD Oscillator Pin Digital Input Type 3: Standard Digital Input or pin configured as DIO Input To Oscillator Power Down Circuits VBAT Pin GNDD GNDD V3P3D Oscillator Equivalent Circuit Type 8: Oscillator I/O V3P3D 10 Digital Output Pin CMOS Output VBAT Equivalent Circuit Type 12: VBAT Power from V3P3SYS V3P3D Pin GNDD 40 from VBAT GNDD Digital Output Equivalent Circuit Type 4: Standard Digital Output or pin configured as DIO Output V3P3D Equivalent Circuit Type 13: V3P3D Figure 44: I/O Equivalent Circuits 154 (c) 2008-2011 Teridian Semiconductor Corporation v1.2 71M6543F/H and 71M6543G/GH Data Sheet 7 Ordering Information 7.1 71M6543 Ordering Guide Refer to the 71M6xxx data sheet for the 71M6xx3 ordering guide information. Table 115. 71M6543 Ordering Guide Part Part Description (Package, Accuracy) Flash Size (KB) Packaging Order Number 100-pin LQFP 64 bulk 71M6543F-IGT/F Lead(Pb)-Free, 0.5% 100-pin LQFP 71M6543F tape and reel 71M6543F-IGTR/F 64 Lead(Pb)-Free, 0.5% 100-pin LQFP 71M6543H* 64 bulk 71M6543H-IGT/F Lead(Pb)-Free, 0.1% 100-pin LQFP 71M6543H* tape and reel 71M6543H-IGTR/F 64 Lead(Pb)-Free, 0.1% 100-pin LQFP 71M6543G 128 bulk 71M6543G-IGT/F Lead(Pb)-Free, 0.5% 100-pin LQFP 71M6543G 128 tape and reel 71M6543G-IGTR/F Lead(Pb)-Free, 0.5% 100-pin LQFP 71M6543GH* 128 bulk 71M6543GH-IGT/F Lead(Pb)-Free, 0.1% 100-pin LQFP 71M6543GH* 128 tape and reel 71M6543GH-IGTR/F Lead(Pb)-Free, 0.1% See 4.5.1 Distinction Between Standard and High-Precision Parts (page 89). *Future product--contact factory for availability. 71M6543F 8 Package Marking 71M6543F-IGT 71M6543F-IGT 71M6543H-IGT 71M6543H-IGT 71M6543G-IGT 71M6543G-IGT 71M6543GH-IGT 71M6543GH-IGT Related Information The following documents related to the 71M6543 and 71M6xx3 are available from Teridian Semiconductor Corporation: * * * * 71M6543F/H and 71M6543G/GH Data Sheet (this document) 71M6xxx Data Sheet 71M654x Software User's Guide (SUG) 71M6543 Demo Board User's Manual (DBUM) 9 Contact Information For technical support or more information about Maxim products, contact technical support at www.maxim-ic.com/support. v1.2 (c) 2008-2011 Teridian Semiconductor Corporation 155 71M6543F/H and 71M6543G/GH Data Sheet Appendix A: Acronyms AFE AMR ANSI CE DIO DSP FIR I2C ICE IEC MPU PLL RMS SFR SoC SPI TOU UART 156 Analog Front-End Automatic Meter Reading American National Standards Institute Compute Engine Digital I /O Digital Signal Processor Finite Impulse Response Inter-IC Bus In-Circuit Emulator International Electrotechnical Commission Microprocessor Unit (CPU) Phase-Locked Loop Root Mean Square Special Function Register System-on-Chip Serial Peripheral Interface Time of Use Universal Asynchronous Receiver/Transmitter (c) 2008-2011 Teridian Semiconductor Corporation v1.2 71M6543F/H and 71M6543G/GH Data Sheet Appendix B: Revision History REVISION NUMBER 1.0 1.1 REVISION DATE 1/11 3/11 1.2 4/11 DESCRIPTION Initial release Added the 71M6543G, 71M6543GH Removed the 17mW typ consumption at 3.3V for sleep mode from the Features section PAGES CHANGED -- All 1 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 (c) Maxim Integrated 157 The Maxim logo and Maxim Integrated are trademarks of Maxim Integrated Products, Inc.