AVAILABLE
Functional Diagrams
Pin Configurations appear at end of data sheet.
Functional Diagrams continued at end of data sheet.
UCSP is a trademark of Maxim Integrated Products, Inc.
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.
71M6543F/H and 71M6543G/GH
Energy Meter ICs
DATA SHEET
April 2011
GENERAL DESCRIPTION
The 71M6543F, 71M6543H, 71M6543G, and 71M6543GH are
Teridian’s 4th-generation polyphase metering systems-on-chips
(SoCs) with a 5MHz 8051-compatible MPU core, low-power real-
time clock (RTC) with digital temperature compensation, flash
memory, and LCD driver. Our Single Converter Tec hnology® with
a 22-bit delta-sigma ADC, seven analog inputs, digital metrology
temperature compensation, precision voltage reference, and a 32-
bit computation engine (CE) supports a wide range of metering
applications with very few external components.
The 71M6543F, 71M6543H, 71M6543G and 71M6543GH support
optional interfaces to the 71M6xx3 series of isolated sensors that
offer BOM cost reduction, immunity to magnetic tamper, and
enhanced reliability. The ICs feature ultra-low-power operation in
active and battery modes, 5KB shared RAM, and 64KB
(71M6543F, 71M6543H) or 128KB (71M6543G, 71M6543GH) of
flash memory, which can be programmed with code and/or data
during meter operation. High processing and sampling rates
combined with differential inputs offer a powerful metering platform
for commercial and industrial meters with up to class 0.2 accuracy
(71M6543H, 71M6543GH).
A complete array of code development tools, demonstration code,
and reference designs enable rapid development and certification of
meters that meet all ANSI and IEC electricity metering standards
worldwide.
MPU
RTC
TIMERS
IADC0
VADC8 (VA)
IADC2
VADC9 (VB)
XIN
XOUT
RX
TX
TX
RX
COM0...5
V3P3A V3P3SYS
VBAT
VBAT_RTC
IADC4
VADC10 (VC)
SEG
GNDA GNDD
SEG/DIO
DIO
ICE
C
B
A
NEUTRAL
LOAD
8888.8888
PULSES,
DIO
IR
AMR
POWER FAULT
COMPARATOR
MODUL-
ATOR
SERIAL PORTS
OSCILLATOR/
PLL
MUX and ADC
LCD DRIVER
DIO, PULSES
COMPUTE
ENGINE
FLASH
MEMORY
RAM
32 kHz
REGULATOR
Shunt Current Sensors
POWER SUPPLY
TERIDIAN
71M6543F/
71M6543H/
71M6543G/
71M6543GH
TEMPERATURE
SENSOR
VREF
IADC6
BATTERY
PWR MODE
CONTROL
WAKE-UP
NEUTRAL
I
2
C or µWire
EEPROM
9/17/2010
IADC1
IADC3
IADC5
IADC7
RTC
BATTERY
V3P3D
BATTERY
MONITOR
SPI INTERFACE
HOST
LCD DISPLAY
Resistor Dividers
Pulse Transformers
3x TERIDIAN
71M6xx3
Note: This system is referenced to Neutral
71M6xx3
71M6xx3
71M6xx3
}
IN*
}
IA
}
IB
}
IC
*IN = Neutral Current
FEATURES
• 0.1% Accuracy Over 2000:1 Current Range
• Exceeds IEC 62053/ANSI C12.20 Standards
• Seven S ens or Inputs with Neutral Current
Measurement, Differential Mode Selectable
for C ur r e nt I nputs
• Selectable Gain of 1 or 8 for One Current
Input to Support Shunts
• High-Speed Wh /VARh Pulse Outputs with
Programmable Width
• 64KB Flash, 5KB RAM (71M6543F/H)
• 128KB Flash, 5KB RAM (71M6543G/GH)
• Up to Four Pulse Outputs with Pulse Count
• Four-Quadrant Metering, Phase Sequencing
• Digital Temperature Compensation:
Metrology Compensation
Accurate RTC for TOU Functions with
Automatic Temperature Compensation
for Cryst a l i n All Power Modes
• Independent 32-Bit Compute Engine
• 46-64Hz Line Frequency Range with the Same
Calibration
• Phase Compensation (±7°)
• Three Battery-Backup Modes:
Brownout Mode
LCD Mode
Sleep Mode
• Wake-Up on Pin Events and Wake-on-Timer
• 1µA in Sl eep Mode
• Flash Security
• In-System Program Update
• 8-Bit MPU (80515), Up to 5MIPS
• Full-Speed MPU Clock in Brownout Mode
• LCD Driver:
6 Common Segment Drivers
Up to 56 Selectable Pins
• Up to 51 Multifunction DIO Pins
• Hardware Watchdog Timer (WDT)
• I2C/MICROWIRE™ EEPROM In terface
• SPI Interface with Flash Program Capability
• Two UARTs for IR and AMR
• IR LED Driver with Modulation
• Industrial Temperature Range
• 100-Pin Lead-Free LQFP Package
19-5375; Rev 1.2; 4/11
Single C onverter Tec hnology is a regi stered trade ma rk of Maxim Inte grated
Products , Inc .
MICROWIRE is a t rademark of N ational Semiconductor C orp.
71M6543F/H and 71M6543G /GH Data Sheet
2 © 2008–2011 Teridian Sem iconduc tor Corpor ation v1.2
Table of Contents
1 Introduction ................................................................................................................................. 10
2 Hardware Descript io n .................................................................................................................. 11
2.1 Hardwar e Overview............................................................................................................... 11
2.2 Analog F r ont-End (AFE) ........................................................................................................ 12
2.2.1 Signal Input Pins ....................................................................................................... 13
2.2.2 Input M ultiplex er ........................................................................................................ 14
2.2.3 Delay Com pensation ................................................................................................. 19
2.2.4 ADC Pre-Amplifier ..................................................................................................... 20
2.2.5 A/D Converter (ADC) ................................................................................................. 20
2.2.6 FIR Filter ................................................................................................................... 20
2.2.7 Vol tage Referenc es ................................................................................................... 20
2.2.8 71M6xx3 Isolated S ensor I nterf ac e ............................................................................ 22
2.3 Digital Com putation Engine (CE) ........................................................................................... 25
2.3.1 CE Progra m Me mory ................................................................................................. 25
2.3.2 CE Data M em ory ....................................................................................................... 25
2.3.3 CE Communicati on with t he MPU .............................................................................. 25
2.3.4 Meter E quations ........................................................................................................ 26
2.3.5 Real-Time Monitor (RTM) .......................................................................................... 26
2.3.6 Pul se Gener ators ...................................................................................................... 26
2.3.7 CE Func tional Overview ............................................................................................ 28
2.4 80515 MPU Cor e .................................................................................................................. 30
2.4.1 Memory Or ganizati on and A ddr essing ....................................................................... 30
2.4.2 Special Function Registers (SF Rs) ............................................................................ 32
2.4.3 Generic 80515 Speci al Functi on Register s ................................................................ 33
2.4.4 Instruc tion S et ........................................................................................................... 35
2.4.5 80515 Power Reduction M odes ................................................................................. 35
2.4.6 UARTs ...................................................................................................................... 36
2.4.7 Timers and Counters ................................................................................................. 38
2.4.8 WD Timer (Software Watchdog Timer) ...................................................................... 40
2.4.9 Interrupts ................................................................................................................... 40
2.5 On-Chip Resources ............................................................................................................... 47
2.5.1 Phys ical Me mory ....................................................................................................... 47
2.5.2 Oscillator ................................................................................................................... 49
2.5.3 PLL and Internal Cl ocks............................................................................................. 50
2.5.4 Real-Time Clock (RTC) ............................................................................................. 51
2.5.5 71M6543 Temperature Sensor .................................................................................. 55
2.5.6 71M6xx3 Temperature Sensor .................................................................................. 56
2.5.7 71M6543 Bat tery Monitor .......................................................................................... 57
2.5.8 71M6xx3 VCC Monitor .............................................................................................. 57
2.5.9 UART and Opti c al Interface ....................................................................................... 57
2.5.10 Digital I/O and LCD Segment Drivers ......................................................................... 58
2.5.11 EEPROM Interface .................................................................................................... 66
2.5.12 SPI S la ve Port ........................................................................................................... 68
2.5.13 Hardware Watchdog Timer ........................................................................................ 72
2.5.14 Test Por ts (TMUXOUT and TMUX2OUT Pi ns)........................................................... 73
3 Functio nal Descrip tion ................................................................................................................ 75
71M6543F/H and 71M6543G /GH Data Sheet
v1.2 © 2008–2011 Teridian Sem iconduc tor Corpor ation 3
3.1 Theory of Operation .............................................................................................................. 75
3.2 Battery Modes ....................................................................................................................... 75
3.2.1 BRN Mode ................................................................................................................ 78
3.2.2 LCD Mode ................................................................................................................. 78
3.2.3 SLP Mode ................................................................................................................. 79
3.3 F ault and Reset Behavior ...................................................................................................... 80
3.3.1 Events at Power-Down .............................................................................................. 80
3.3.2 IC Behav ior at Low Batter y Volt age ........................................................................... 81
3.3.3 Reset Sequence ........................................................................................................ 81
3.3.4 Watchdog Timer (WDT ) Reset ................................................................................... 81
3.4 Wake-Up Behavior ................................................................................................................ 82
3.4.1 Wake on Hardware Event s ........................................................................................ 82
3.4.2 Wake on Timer .......................................................................................................... 84
3.5 Dat a Flow and MPU/CE Communication ............................................................................... 84
4 Application Information ............................................................................................................... 86
4.1 Connecti ng 5 V Devices ........................................................................................................ 86
4.2 Directly Connected Sensors .................................................................................................. 86
4.3 Sy stems Using 71M6xx3 Isolated Sensors and Current S hunts ............................................. 87
4.4 Sy stem Usi ng Cur r ent Transf ormers ..................................................................................... 88
4.5 Metrology Temperat ur e Com pensation .................................................................................. 89
4.5.1 Distincti on B etween Standard and High-Precision Parts ............................................ 89
4.5.2 Temper ature Coefficient s for the 71M 6543F and 71M6543G ..................................... 90
4.5.3 Temper ature Coefficient s for the 71M 6543H and 71M 6543GH .................................. 90
4.5.4 Temper ature Coefficient s for the 71M 6xx3................................................................. 90
4.5.5 Temper ature Compensation for VREF and Shunt Sensors ........................................ 90
4.5.6 Temper ature Compensation of VREF and Current Transf ormers ............................... 92
4.6 Connecti ng I2C EEPROMs .................................................................................................... 94
4.7 Connecti ng Three-Wire EEPROMs ....................................................................................... 94
4.8 UART0 (TX/RX) .................................................................................................................... 94
4.9 O ptical I nterface (UART1) ..................................................................................................... 94
4.10 Connecti ng the Reset Pin ...................................................................................................... 95
4.11 Connecti ng the Emulator Por t Pins ........................................................................................ 96
4.12 F lash Programming ............................................................................................................... 96
4.12.1 Flash Programming v ia the I CE Port .......................................................................... 96
4.12.2 Flash Programming v ia the SP I Por t .......................................................................... 96
4.13 MPU Demonstr ati on Code..................................................................................................... 96
4.14 Cry stal O scillator ................................................................................................................... 97
4.15 Meter Calibration ................................................................................................................... 97
5 Firmware Interface ....................................................................................................................... 98
5.1 I /O RAM Map –Functiona l Order ........................................................................................... 98
5.2 I /O RAM Map – Alphabetic al Order ..................................................................................... 104
5.3 Reading the Info Page (71M6543H and 71M6543GH only).................................................. 118
5.4 CE Interface Descripti on ..................................................................................................... 120
5.4.1 CE Program ............................................................................................................ 120
5.4.2 CE Data Format ...................................................................................................... 120
5.4.3 Constants ................................................................................................................ 120
5.4.4 Environment ............................................................................................................ 121
5.4.5 CE Cal c ulations ....................................................................................................... 121
5.4.6 CE Fr ont-End Data (Raw Data) ............................................................................... 122
5.4.7 CE St atus and Control ............................................................................................. 123
71M6543F/H and 71M6543G /GH Data Sheet
4 © 2008–2011 Teridian Sem iconduc tor Corpor ation v1.2
5.4.8 CE Transfer Variabl es ............................................................................................. 125
5.4.9 Pul se Gener ation..................................................................................................... 127
5.4.10 CE Cali br ation Parameters ...................................................................................... 130
5.4.11 CE Flow Diagr am s .................................................................................................. 131
6 71M6543 Specifi cat io ns ............................................................................................................. 133
6.1 Absol ute Maximum Ratings ................................................................................................. 133
6.2 Recom mended Ext er nal Com ponents ................................................................................. 134
6.3 Recommended Operating Conditions .................................................................................. 134
6.4 Perform anc e S pecificati ons ................................................................................................. 135
6.4.1 Input Logic Levels ................................................................................................... 135
6.4.2 Out put Logic Levels ................................................................................................. 135
6.4.3 Battery Monitor ........................................................................................................ 136
6.4.4 Temperature Monit or ............................................................................................... 137
6.4.5 Suppl y Cur r ent ........................................................................................................ 138
6.4.6 V3P3D Swi t ch ......................................................................................................... 139
6.4.7 Int er nal Power F ault Comparat or s ........................................................................... 139
6.4.8 2.5 V V oltage Regulator – System Power ................................................................ 139
6.4.9 2.5 V V oltage Regulator – Battery Power ................................................................. 140
6.4.10 Crystal Oscill ator ..................................................................................................... 140
6.4.11 Phase-Locked Loo p ( P LL) ....................................................................................... 140
6.4.12 LCD Drivers ............................................................................................................ 140
6.4.13 VLCD Gener ator...................................................................................................... 140
6.4.14 71M6543 VREF ....................................................................................................... 143
6.4.15 ADC Converter ........................................................................................................ 144
6.4.16 Pre-A mplifier for IADC0-IADC1 ................................................................................ 145
6.5 Timing Specifications .......................................................................................................... 146
6.5.1 Flash Memory ......................................................................................................... 146
6.5.2 SPI Slave ................................................................................................................ 146
6.5.3 EEPROM Interface .................................................................................................. 146
6.5.4 RESET Pin .............................................................................................................. 147
6.5.5 Real-Time Clock (RTC) ........................................................................................... 147
6.6 Typical Performance Data ......................................................... Erro r! Boo kmark not defined .
6.7 100-Pin LQFP Package Outline Drawing ............................................................................. 148
6.8 71M6543 P inout .................................................................................................................. 149
6.9 71M6543 P in Descriptions................................................................................................... 150
6.9.1 71M6543 Power and Ground Pins ........................................................................... 150
6.9.2 71M6543 Analog Pi ns ............................................................................................. 151
6.9.3 71M6543 Digital Pins............................................................................................... 152
6.9.4 I/ O Equivalent Circuits ............................................................................................. 154
7 Orderin g I nformation ................................................................................................................. 155
7.1 71M6543 Ordering Guide .................................................................................................... 155
8 Rel ated Information ................................................................................................................ 155
9 Con ta ct I n fo rmati on ................................................................................................................ 155
Appendix A: Acronyms ..................................................................................................................... 156
Appendix B: Revisio n Hi story ........................................................................................................... 157
71M6543F/H and 71M6543G /GH Data Sheet
v1.2 © 2008–2011 Teridian Sem iconduc tor Corpor ation 5
Figures
Figure 1: IC Functional Block Di agr am ..................................................................................................... 9
Figure 2: AFE Block Diagram ( S hunts: One-Local , T hr ee-Remotes) ...................................................... 12
Figure 3. AFE Block Diagram (Four CTs) ............................................................................................... 13
Figure 4: States i n a Multiplexer Fr am e (MUX_DIV[3:0] = 6) .................................................................. 17
Figure 5: States i n a Multiplexer Fr am e (MUX_DIV[3:0] = 7) .................................................................. 17
Figure 6: General Topology of a Chopped Amplifier ............................................................................... 21
Figure 7: CROSS Signal with CHOP_E = 00 ........................................................................................... 21
Figure 8: RTM Timing ............................................................................................................................ 26
Figure 9. Pulse Generator FIFO Timing ................................................................................................. 28
Figure 10: Samples fr om Multiplexer Cycle (Frame) ............................................................................... 29
Figure 11: Acc um ulation Interv al ............................................................................................................ 29
Figure 12: Interr upt Structure ................................................................................................................. 46
Figure 13: Aut om atic Temper ature Compensation ................................................................................. 54
Figure 14: Optical Interfac e .................................................................................................................... 58
Figure 15: Optical Interfac e ( UA RT1) ..................................................................................................... 58
Figure 16: Connect ing an Exter nal Load to DIO Pi ns ............................................................................. 60
Figure 17: LCD Waveform s ................................................................................................................... 65
Figure 18: 3-wire I nterface. Wri te Command, HiZ=0. ............................................................................. 67
Figure 19: 3-wire I nterface. Wri te Command, HiZ=1 .............................................................................. 68
Figure 20: 3-wire I nterface. Read Command. ........................................................................................ 68
Figure 21: 3-Wir e Int erfac e. Write Command when CNT=0 ................................................................... 68
Figure 22: 3-wire I nterface. Wri te Command when Hi Z=1 and WFR=1. ................................................. 68
Figure 23: SPI Slav e Port - Typica l Multi-Byt e Read and Write operations .............................................. 70
Figure 24: Volt age, Current, Moment ar y and Accum ulated Ener gy ......................................................... 75
Figure 25: Oper ation Modes St ate Diagram ........................................................................................... 76
Figure 26: MPU/CE Data Fl ow ............................................................................................................... 85
Figure 27: Resistive Voltage Divider (Voltage S ensi ng) .......................................................................... 86
Figure 28. CT wi th Single-Ended Input Connection (Current S ensi ng) .................................................... 86
Figure 29: CT wi th Differenti al Input Connec tion (Current Sensi ng) ........................................................ 86
Figure 30: Differenti al Resi stive Shunt Connections (Current S ensi ng) ................................................... 86
Figure 31: System Usi ng Three-Rem otes and One-Local (Neutral) Sensor ............................................ 87
Figure 32. System Usi ng Cur r ent T r ansformers ..................................................................................... 88
Figure 33: I2C EEPROM Connec tion ...................................................................................................... 94
Figure 34: Connect ions for UART0 ........................................................................................................ 94
Figure 35: Connect ion for Optic al Com ponents ...................................................................................... 95
Figure 36: External Components for t he RE SET Pin: Push-Butt on ( Left), Pr oduc tion Circuit (Right) ....... 96
Figure 37: External Components for t he Emulator Int erface ................................................................... 96
Figure 38. Trim Fuse Bit Mapping ........................................................................................................ 118
Figure 39: CE Data Flow: Multipl ex er and ADC .................................................................................... 131
Figure 40: CE Data Flow: Sc aling, Gain Control, Intermediate Variables for one Phase........................ 131
Figure 41: CE Data Flow: Squar ing and Summati on Stages ................................................................. 132
Figure 42: Wh Error from 200 A to 0.1 A at 60 Hz, 240 VAC ...................... Error! Boo kmark not defined .
Figure 43: VARh Error from 200 A to 0.1 A at 60 Hz, 240 VAC ................... Error! Bookmark not defined.
Figure 44: Wh Error from 200 A to 0.1 A at Various Frequenc ies (0° Load angle, 240 V A C) ............. Error!
Bookmark not defined.
Figure 45: 100-pi n LQF P Pack age Outli ne ........................................................................................... 148
Figure 46: Pinout for the LQFP-100 Package ....................................................................................... 149
Figure 47: I/O Equivalent Ci rcuit s ......................................................................................................... 154
71M6543F/H and 71M6543G /GH Data Sheet
6 © 2008–2011 Teridian Sem iconduc tor Corpor ation v1.2
Tables
Table 1. Requir ed CE Code and Set tings for 1-Local / 3-Remotes ......................................................... 15
Table 2. Requir ed CE Code and Set tings for CT Sensors ...................................................................... 16
Table 3: Multiplex er and A DC Configurati on Bi ts .................................................................................... 19
Table 4. RCMD[4:0] Bits ........................................................................................................................ 23
Table 5: Remote Int erface Read Commands ......................................................................................... 23
Table 6: I/O RAM Control Bits for Isolat ed S ensor .................................................................................. 24
Table 7: Input s Selected in Multi plex er Cy cl es ....................................................................................... 26
Table 8: CKMPU Clock Frequencies ...................................................................................................... 30
Table 9: Memory Map ............................................................................................................................ 31
Table 10: Int er nal Data Mem or y Map ..................................................................................................... 32
Table 11: Special F unc tion Regi ster Map ............................................................................................... 32
Table 12: Generic 80515 SFRs - Locati on and Reset V alues ................................................................. 33
Table 13: PSW Bit Functions (SFR 0xD0) ............................................................................................... 34
Table 14: Port Regi ster s (SE GDIO0-15) ................................................................................................ 35
Table 15: Str etch M em ory Cycl e Widt h .................................................................................................. 35
Table 16. 80515 PCON SFR Register ( S FR 0x87).................................................................................... 36
Table 17: Baud Rate Generati on............................................................................................................ 36
Table 18: UART Modes ......................................................................................................................... 37
Table 19: The S0CON (UART 0) Regi ster ( SFR 0x 98) ............................................................................. 37
Table 20: The S1CON (UART 1) Regi ster ( SFR 0x 9B ) ............................................................................. 38
Table 21: PCON Register Bi t Description (SFR 0x8 7) .............................................................................. 38
Table 22: Timer s/Counters Mode Descri ption ........................................................................................ 39
Table 23: All owed Timer /Counter Mode Combinations ........................................................................... 39
Table 24: TMOD Register Bit Description (SF R 0x 89) ............................................................................ 39
Table 25: The TCON Register Bit Functions (SFR 0x 88) ........................................................................ 40
Table 26: The IEN0 Bit Functi ons (SFR 0xA 8) ........................................................................................ 41
Table 27: The IEN1 Bit Functi ons (SFR 0xB 8) ........................................................................................ 41
Table 28: The IEN2 Bit Functions (SFR 0x9A) ........................................................................................ 41
Table 29: TCON Bit Functions (SFR 0x88) ............................................................................................. 41
Table 30: The T2CON Bit F unctions (SFR 0xC8) .................................................................................... 42
Table 31: The IRCON Bit F unc tions (SFR 0xC0) .................................................................................... 42
Table 32: External MPU Interrupts ......................................................................................................... 42
Table 33: Int er r upt Enable and Flag Bit s ................................................................................................ 43
Table 34: Int er r upt Pri ori ty Level Groups ................................................................................................ 43
Table 35: Int er r upt Pri ori ty Levels .......................................................................................................... 44
Table 36: Int er r upt Pri ori ty Registers (IP0 and IP1) ................................................................................. 44
Table 37: Int er r upt Polling Sequence ..................................................................................................... 45
Table 38: Int er r upt Vector s .................................................................................................................... 45
Table 39: Flash Memory Access ............................................................................................................ 47
Table 40: Bank Switching wit h FL _BA NK[1:0] ( SF R 0x B6 [1:0 ]) in the 71M6543G/GH ............................... 48
Table 41: Flash Security ........................................................................................................................ 49
Table 42: Clock Sy stem Summ ar y ......................................................................................................... 51
Table 43: RTC Control Registers ........................................................................................................... 52
Table 44: I/O RAM Registers for RTC Temperature Compensation ........................................................ 53
Table 45: NV RAM Table Structur e ............................................................ Error! Boo kmark not defined .
Table 46: I/O RAM Register s for RTC Interr upts .................................................................................... 55
Table 47: I/O RAM Registers for Temper ature and Battery Measurement .............................................. 56
Table 48: Select able Resources using the DIO_Rn[2:0] Bits................................................................... 59
71M6543F/H and 71M6543G /GH Data Sheet
v1.2 © 2008–2011 Teridian Sem iconduc tor Corpor ation 7
Table 49: Data/ Dir ec tion Registers and Int er nal Resources f or SEG DIO 0 to SEGDIO 15 ........................ 60
Table 50: Data/Direction Registers f or SEG DIO 16 to SEGDIO 31 ........................................................... 61
Table 51: Data/ Dir ec tion Registers for SEGDIO32 to SEGDIO 45 ........................................................... 61
Table 52: Data/ Dir ec tion Registers for SEGDIO51 to SEGDIO 55 ........................................................... 61
Table 53: LCD_VMODE Configurations .................................................................................................. 63
Table 54: LCD Configurations ................................................................................................................ 64
Table 55: LCD Data Registers for SEGDIO 46 to SEGDIO55 .................................................................. 65
Table 56: EECTRL Bits for 2-pin Interface ............................................................................................... 66
Table 57: EECTRL Bits for the 3-wi r e Interfac e ....................................................................................... 67
Table 58: SPI Transaction Fields ........................................................................................................... 69
Table 59: SPI Command S equenc es ..................................................................................................... 70
Table 60: SPI Regi ster s ......................................................................................................................... 70
Table 61: TMUX[4:0] Selections ............................................................................................................ 73
Table 62: TMUX2[4:0] Selections ........................................................................................................... 74
Table 63: Available Circuit F unc tions ..................................................................................................... 77
Table 64: VSTAT[2:0] (SFR 0xF9[2:0]) ................................................................................................... 80
Table 65: Wake Enabl e and Flag Bits .................................................................................................... 82
Table 66: Wake Bits .............................................................................................................................. 83
Table 67: Clear Events for WAKE flags .................................................................................................. 84
Table 68: GAIN_ADJ n Com pensation Channels (Figure 2, Figur e 31, T able 1) ...................................... 91
Table 69: GAIN_ADJx Compensation Channels (Fi gur e 3, Fi gur e 32, Tabl e 2) ...................................... 93
Table 70: I/O RAM Map – Func tional Order , Basi c Configuration ........................................................... 98
Table 71: I/O RAM Map – Functional Order ......................................................................................... 100
Table 72: I/O RAM Map – Alphabetic al Order ...................................................................................... 104
Table 73: Inf o Page Trim F uses ........................................................................................................... 118
Table 74: CE EQU[2:0] E quations and Element I nput Mapping ............................................................ 121
Table 75: CE Raw Data Access Locations ........................................................................................... 122
Table 76: CESTATUS Register .............................................................................................................. 123
Table 77: CESTATUS Bit Def initions...................................................................................................... 123
Table 78: CECONFIG Register ............................................................................................................. 123
Table 79: CECONFIG Bi t Defi nitions (CE RAM 0x20) ........................................................................... 124
Table 80: Sag Threshold, P hase Measurement, and Gai n A djust Control ............................................. 125
Table 81: CE Transf er Variables (with S hunts) ..................................................................................... 125
Table 82: CE Transf er Variables (with CTs) ......................................................................................... 126
Table 83: CE Energy Measurement Variables (wi th Shunts)................................................................. 126
Table 84: CE Energy Measurement Variables (wi th CTs) ..................................................................... 126
Table 85: Other Transfer Vari ables ...................................................................................................... 127
Table 86: CE Pulse Generation Param eters......................................................................................... 128
Table 87: CE Param eters for Noise Suppres si on and Code V er si on..................................................... 129
Table 88: CE Calibrat ion Paramet er s ................................................................................................... 130
Table 89: Absolut e M aximum Ratings .................................................................................................. 133
Table 90: Recommended Exter nal Com ponents .................................................................................. 134
Table 91: Recommended Operati ng Conditions ................................................................................... 134
Table 92: Input Logic Lev els ................................................................................................................ 135
Table 93: Output Logic Level s ............................................................................................................. 135
Table 94: Battery M onitor Performance Specifications (TEMP_BAT = 1) ............................................... 136
Table 95: Temper ature Monitor ............................................................................................................ 137
Table 96: Suppl y Current Perform anc e S pecifications .......................................................................... 138
Table 98: Int er nal P ower Fault Comparators Performance S pec ificati ons ............................................. 139
Table 99: 2.5 V Voltage Regulat or Performance Specificat ions ............................................................ 139
71M6543F/H and 71M6543G /GH Data Sheet
8 © 2008–2011 Teridian Sem iconduc tor Corpor ation v1.2
Table 100: Low-Power Voltage Regulator Performance Specifications ................................................. 140
Table 101: Crystal Oscillat or P erformance Specificati ons ..................................................................... 140
Table 102: PLL Performance Specifications ......................................................................................... 140
Table 103: LCD Drivers Performanc e S pecificati ons ............................................................................ 140
Table 105: 71M6543 VREF Perform anc e Specif ic ations ...................................................................... 143
Table 106: ADC Converter Performance Specifications ....................................................................... 144
Table 107: Pre-Am plifier Performance Specificati ons ........................................................................... 145
Table 108: Flash Memory Timing Specific ations .................................................................................. 146
Table 109. SPI Slave Timing Specific ations ......................................................................................... 146
Table 110: EEPROM Int erface Timing ................................................................................................. 146
Table 111: RESET Pin Timing ............................................................................................................. 147
Table 112: RTC Range f or Date........................................................................................................... 147
Table 113: 71M6543 Power and Ground P ins ...................................................................................... 150
Table 114: 71M6543 Analog Pins ........................................................................................................ 151
Table 115: 71M6543 Di gital Pins ......................................................................................................... 152
Table 116. 71M6543 Or deri ng Guide ................................................................................................... 155
71M6543F/H and 71M6543G /GH Data Sheet
v1.2 © 2008–2011 Teridian Sem iconduc tor Corpor ation 9
Figure 1: IC Functional Block Di agr am
IADC
MUX
and
PREAMP
XIN
XOUT
VREF
CKADC
CE
32
-
bit Compute
Engine
MPU
(
80515
)
CE CONTROL
OPT
_
RX
/
SEGDIO
55
OPT
_
TX
/
SEGDIO
51
/
WPULSE
/
VPULSE
RESET
VBIAS
EMULATOR
PORT
3
C
E
_
B
U
S
Y
OPTICAL
INTERFACE
UART
0
TX
RX
X
F
E
R
B
U
S
Y
6
COM
0
..
5
VLC
2
LCD DRIVER
CEDATA
0
x
000
...
0
x
2
FF
PROG
0
x
000
...
0
x
3
FF
DATA
0
x
0000
...
0
xFFFF
PROGRAM
0
x
0000
...
0
xFFFF
0
x
00000
…
0
X1FFFF
DIGITAL I
/
O
CONFIGURATION
RAM
(
I
/
O RAM
)
0
x
2000
...
0
x
20
FF
I
/
O
R
A
M
MEMORY SHARE
0
x
0000
...
0
x
13
FF
16
8
RTCLK
RTCLK
(
32
KHz
)
MUX
_
SYNC
CKCE
CKMPU
CK
32
32
8
8
8
P OWER FAULT
DETECTION
4
.
9
MHZ
<
4
.
9
MHz
4
.
9
MHz
GNDD
V
3
P
3
A
V
3
P
3
D
VBAT
Voltage
Regulator
2
.
5
V to logic
VDD
32
KHz
MPU
_
RSTZ
FAULTZ
WAKE
CON
-
FIGURATION
PARAMETERS
GNDA
VBIAS
9
/
20
/
2010
CROSS
CLOCK GEN
Oscillator
32
KHz
CK
32
MCK
PLL
VREF
DIV
ADC
MUX CT RL
STRT
MUX
MUX
CKFIR
RTM
SEGDIO Pi ns
WPULSE
VARPULSE
WPULSE
VARPULSE
TEST
TEST
MODE
VLC
1
VLC
0
<
4
.
9
MHz
CKMPU
_
2
x
CKMPU
_
2
x
SDCK
SDOUT
SDIN
E
_
RXTX
/
SEG
48
E
_
TCLK
/
SEG
49
E
_
RST
/
SEG
50
FLASH
128
KB
V
3
P
3
A
FIR
EEPROM
INTERFACE
CK
_
4
X
LCD
_
GEN
PB
RTC
VBIAS
MEMORY
SHARE
17
E
_
RXTX
E
_
TCLK
E
_
RST
(
Open Drain
)
ICE
E
∆Σ_
AD CONVERTER
+
-
VREF
V
3
P
3
SYS
TEST MUX
VLCD
VLCD
Voltage
Boost
MPU R AM
(
5
KB
)
22
S
P
I
VSTAT
VBAT
_
RTC
IADC
IADC
IADC
3
IADC
4
IADC
IADC
IADC
7
VADC
8
(
VA
)
VADC
9
(
VB
)
VADC
10
(
VC
)
SEG Pins
2
TEST MUX
2
Non
-
Volatile
CONFIGURATION
RAM
BAT
TEST
TEMP
SENSOR
RTM
71M6543F/H and 71M6543G /GH Data Sheet
10 © 2008–2011 Teridian Sem iconduc tor Corpor ation v1.2
1 Introduction
This data sheet cover s the 71M 6543F (64KB, 0.5%), 71M6543H (64KB, 0.1%), 71M6543G (128K B,
0.5%) and 71M 6543GH (128KB , 0. 1%) 4th-generation Teridian polyphase energy measurement system-
on-chi ps (SoCs). The term “71M 6543” is used when disc us si ng a dev ice featur e or behavior that is
applicable to all four part numbers. The specif ic part number s are used whe n discussing those f eatures
that apply only to specif ic par t number s. T his data sheet also covers detail s about the companion
71M6xx3 isolated curr ent sensor device.
This document covers the use of the 71M6543 i n conj unction with the 71M6xx3 isolat ed c urrent sensor.
The 71M6543 and 71M 6x x3 ICs make it possi ble t o use one non-i sol ated and thr ee additional isolated
shunt current sensor s to c r eate polyphase energy meters using inexpensive shunt resistors, while
achi ev ing unprec edented perf ormance with this type of sen sor t ec hnology. The 71M 6543 S oCs al so
support Cur r ent Transf ormers (CT).
To f acil itate doc um ent navigati on, hyper links are often used t o r efer enc e figures, t ables and section
headings that are locat ed in other par ts of the doc um ent. All hy perli nk s i n this document are highlighted in
blue. Hyperlinks are used extensively to inc r ease the level of det ail and cl ar ity provided within each
secti on by r eferencing other relev ant parts of the document. To further facili tate document nav igation, this
document is publi shed as a PDF document with bookmark s enabl ed.
The reader is al so encouraged to obtain and rev iew the document s listed i n 8 Relat e d I nf o rm at i o n on
page 155 of this docu ment.
71M6543F/H and 71M6543G /GH Data Sheet
v1.2 © 2008–2011 Teridian Sem iconduc tor Corpor ation 11
2 Hardware Description
2.1 Hardware Overview
The Teridian 71M6543 single-chip energy met er i ntegrates all primary functional blocks requi r ed to
im plem ent a solid-state electricity meter. Incl uded on the chip are:
• An analog front-end (AFE) featuring a 22-bit second-order sigma-delta ADC
• An independent 32-bit digital comput ation engi ne ( CE) to implement DSP functions
• An 8051-compati ble mi c r opr oc essor (MPU) whic h ex ecutes one i nstruction per clock cyc le (80515)
• A precision voltage referenc e (VREF)
• A tem per ature sensor for digital temperature com pensation of:
- Metr ology (MPU)
- Autom atic RTC in all power states
- MPU assisted RTC c om pensation
• LCD Driv er
• RAM and Flash memory
• A real time clock (RT C)
• A variety of I/O pi ns
• A power failure interr upt
• A zero-cr ossing interr upt
• Selectable c ur r ent sensor interfaces for locally-c onnec ted sensors as well as isolated sensors (i.e.,
using the 71M6xx3 companion IC with a shunt r esistor se nsor )
• Resistive Shunt and Current Transf ormers are supported
In order to implement a polyphase meter with or without neutral curr ent sensing, one r esi stive shunt
current sensor may be c onnec ted directly (non-isolated) to the 71M6543 device, while up to three
additi onal c ur r ent shunts are i sol ated using a com panion 71M6xx 3 isol at ed sensor IC. A n inex pensive,
small size pulse tr ansform er is used to electrically isolate t he 71M 6xx3 remote sensor fr om the 71M6543.
The 71M6543 perform s di gital comm unic ations bi-directi onally wi th the 71M6xx3 and also provides power
to t he 71M 6xx3 through the isol ating pul se tr ansformer. Isolated (rem ote) shunt c ur rent sensors are
connect ed to the diff er ential i nput of the 71M6xx3. The 71M6543 may also be used with Current
Transform er s; in this case the 71M6xx3 isol ated sensors are not required. Included on the 71M6xx 3
companion i sol ator chip are:
• Digit al isolation communic ations interf ac e
• An analog front-end (AFE) featuring a 22-bit second-order sigma-delta ADC
• A precision voltage reference ( V REF)
• A temper ature sensor (for current-sensing digital temperature c om pensation)
• A fully differ ential shunt resistor sensor input
• A pre-amplifier to optimize shunt current sensor perfor manc e
• Isolat ed power circuitry obtains dc power from pul ses sent by the 71M6543
In a typical applicati on, t he 32-bit com pute engine (CE) of the 71M6543 sequentially processes the
samples from the voltage inputs on analog input pi ns and perf orms cal c ulations to measure active energy
(Wh) and reactive energy (VARh), as w e ll as A2h, and V2h for four-quadrant metering. These measurements
are then ac c essed by the MP U, processed f ur ther and output usi ng the peripheral devices available to t he
MPU.
In add ition to ad vanc ed meas ure me nt fu nc tions , the rea l t ime clock (RTC) function allows the 71M6543 to
record time of use (TOU) metering informa tion for mu lti-rate appl ications and t o time-stamp tamper or other
events. An automatic RTC temperature compensation circuit operates in all power states including when the
MPU is halted, and continues to compensate using back-up battery power during po wer ou tages.
Measurements can be displayed on 3.3 V LCDs co mmo n ly used in low-temper ature environments. The
integrated charge pump and temperature sensor can be used by the MPU to enhance 3.3 V LCD
performance at cold temperatures. The on-chip charge pump may also drive 5 V LCDs. Flexible mapping o f
LCD display segments facilitates the integration of existing custom LCDs. Desi gn trade-off bet ween the
71M6543F/H and 71M6543G /GH Data Sheet
12 © 2008–2011 Teridian Sem iconduc tor Corpor ation v1.2
num ber of LCD segm ents and DIO pi ns can be implemented in software to ac c ommodate vari ous
requirements.
In addition to the temperature-t rimmed ultra-preci si on vol tage ref er enc e, t he on-c hip digital temper ature
compensation mechanism includes a temperature sensor and associated controls for correction of unwanted
temper ature effects on metrology and RTC accuracy (i.e., to meet the r equir em ents of ANSI and IEC
standards). Temperature-dependent external component s such as the crystal oscillator, curr ent
transformers (CTs), Current Shun ts and their corresponding signa l con d it ioning cir cu its can be chara c ter-
ized an d th eir correct ion factors c an be p r ogrammed to prod uce ele c tric it y m eters with exc ept ional accuracy
over the industrial temperature range.
On e of t he two internal UARTs is ad apted to s up port an Infrared LED with inte r nal driv e and sense
configuration and can also f unction as a standard UART . The optical output can be m odulated at 38 kHz.
This flexibility makes it possible to implem ent AM R meters wit h an IR interfac e. A block di agr am of the I C
is shown in Figure 1.
2.2 Analog Front-End (AFE)
The AFE functi ons as a data acquisiti on system, control led by the MPU. The 71M6543 AFE may also be
augmented by i sol ated 71M6xx 3 sensors in order to support low-cost curr ent shunt sensors. Figure 2,
and Figure 3 show t he two most common configurations; other configur ations are possible. S ensors that
are connected di r ectly to the 71M6543 (i.e., IADC0-IADC1, VADC8, V ADC9 and VADC10) are
multiplexed into t he si ngle second-order si gma-delta ADC input for sampling i n the 71M6543. The
71M6543 ADC out put is decim ated by the FIR filter and stored i n CE RAM where it c an be accessed and
processed by t he CE .
Shunt c ur r ent sensors that ar e isol ated by using a 71M6xx3 device, are sam pled by a second-order
sigma delta ADC in the 71M6xx3 and the signal sam ples are transferred over the digital isolation interface
through the low-cost isolati on pulse transformer.
Figure 2 shows the 71M6543 u sing shunt current sensors and the 71M 6x x3 isol ated sensor devi c es.
Figure 2 supports neutral curr ent measurem ent with a local shunt c onnec ted to the IADC0-IADC1 input
plus thr ee r em ote (isolated) shunt sensors. As seen in Figure 2, when a remote isolated shunt sensor is
connected via the 71M6 xx3, the sam ples associ ated with this current c hannel ar e not rout ed to the
m ultiplexer, and are instead t r ansferred digitally to the 71M6543 via the isolati on interf ac e and are di r ectly
stored i n CE RAM. The MUX_SELn[3:0] I/O RAM control fields allow t he MPU t o configur e the AFE for t he
desired multi plexer sampling sequence. Refer to Table 1 and Table 2 for the appropr iate CE code and the
correspondi ng A FE sett ings.
See Figure 31 for the meter wiring configurat ion corresponding to Figure 2.
∆Σ ADC
CONVERTER
VREF
MUX
VREF
VREF
VADC
22
FIR
IADC2
VADC9 (VB)
IADC0
VADC8 (VA)
IADC1
IADC3
71M6543
CE RAM
71M6xx3
SP
SN
INP
INN
Remote
Shunt
IB
Digital
Isolation
Interface
Local
Shunt
IN*
22
IADC4
IADC5
71M6xx3
SP
SN
INP
INN
Remote
Shunt
IC
VADC10 (VC)
22
IADC6
IADC7
71M6xx3
SP
SN
INP
INN
Remote
Shunt
IA
22
*IN = Neutral Current 9/17/2010
Figure 2: AFE Blo ck Diagram (Shunts: One-Local, Three-Remotes)
71M6543F/H and 71M6543G /GH Data Sheet
v1.2 © 2008–2011 Teridian Sem iconduc tor Corpor ation 13
The 71M6543 A FE can al so be di r ec tly interf ac ed to Cur r ent Transformers (CTs), as seen in Figure 3. In
this case, all v oltage and curr ent channels are multiplexed into a single second-order sigma-delta ADC in
the 71M6543 and the 71M6xx 3 r em ote isolat ed sensors are not used. The four th CT and the
measurement of Neutral c ur r ent via the IADC0-IADC1 curr ent channel are optional.
See Figure 32 for t he m eter wiri ng c onfiguration corresponding to Figure 3.
∆Σ ADC
CONVERTER
VREF
MUX
VREF
VREF
VADC
22
FIR
IADC4
VADC9 (VB)
IADC2
VADC8 (VA)
IADC3
IADC5
71M6543
CE RAM
IB
CT
IA
CT
IADC6
IADC7
IC
CT
IADC0
IADC1
IN*
CT
VADC10 (VC)
9/17/2010
*IN = Neutral Current
Figure 3. AF E Blo ck Diag ram ( Fo ur CTs)
2.2.1 Signal Input Pins
The 71M6543 features eleven ADC input pins.
IADC0 through IADC7 are intended for use as current sensor inputs. These eight current sensor inputs can
be configur ed as e ight s ingle-ende d inpu ts, or can be pa ired to form four dif feren t ial inputs . For bes t
perfor manc e , it is recom men ded to con figure the cu rrent sens or inpu ts as dif feren t ia l inputs (i.e., IADC 0-
IADC1, IADC2 -IADC3, IADC4-IADC5 and IADC6-IADC7). The firs t differential input (IADC0-IADC1)
fe atures a pr e-ampli fier with a selectable gain of 1 or 8, and is intended for direc t connection to a shun t
res istor sensor , and can a lso be used with a Cur re nt T ra nsformer (C T). The three re ma ining dif feren t ial
pairs (i.e., IADC2 -IADC3, IADC4-IADC5 and IADC6-IADC7) may be used with CTs, or may be en abled to
inter face to a remo te 7 1M6xx3 isolated current sensor providing isolation for a shunt resistor sensor usi ng a
low cost pulse transformer.
The remaining three inputs VADC8 (V A), VAD C9 (VB) and VADC10 (VC) are single-ended, and are
intended for sensing each of the phas e voltages in a polyphase meter app lica t ion . These three single-ended
inputs are referenced to the V3P3A pin.
All ADC input pins measure v oltage. In the case of shunt current sensors, currents are sensed as a voltage
drop in the shun t res is tor sensor. In th e case of Cur ren t Transfor me rs (C T ), the cu rr en t is measu red as a
vo ltage across a burd en resis to r tha t is conn ec ted to th e s econda r y o f the C T. Meanwhile, line voltages are
sens ed throug h resist i ve voltage di viders. The VADC8 (VA), VADC9 (VB) and VADC10 (VC) pins are
single-ended and their common return is the V3P3A pin. See Figure 27, Figure 28, Figure 29 and Figure
30 for detail ed connect ions for each type of sensor. Al so ref er to the 71M6543 Demonstration Board
schemati c and bill of materials for typic al c om ponent values used in these and other c irc uits.
71M6543F/H and 71M6543G /GH Data Sheet
14 © 2008–2011 Teridian Sem iconduc tor Corpor ation v1.2
Pins IADC0-IADC1 can be progr ammed individually to be differ ential or si ngle-ended as determined by
the DIFF0_E (I/O RAM 0x210C[4]) control bit. However, for most appli c ations, IADC0-IADC1 are
configured as a differenti al input to work with a resistive shunt or CT directly interf ac ed to t he IADC0-
IADC1 differ ential input with t he appr opr iate exter nal signal c onditi oning components.
The performanc e of t he IADC0-IADC1 pins can be enhanced by enabli ng a pr e-am plifier with a f ixed gain
of 8, usi ng the I/O RAM contr ol bit PRE_E (I/O RA M 0x2 704[5 ]). When PRE_E = 1, IADC0-IADC1 become
the inputs to the 8x pr e-am plifier, and the output of this amplif ier i s supplied to the mu ltiplexer. The 8x
am plificati on is usef ul when current sensors with low se nsi tiv ity, such as shunt resi stors, ar e used. With
PRE_E s et, the IADC0-IADC1 i nput signal amplitude is restrict ed to 31. 25 m V peak. When PRE_E = 0
(Gain = 1), the IADC0-IADC1 input signal is restricted to 250 mV peak.
For the 71M 6543 application utilizing shunt resistor sensors (Figure 2), the IADC0-IADC1 pi ns are
configured for differential mode to interface to a local shunt by setting the DIFF0_E control bit. Meanwhile,
the IADC2-IADC3 , IADC4-IADC5 and IADC6-IADC7 pins are re-config ured a s digital remote sen s or
inter face de signed to c ommunicate wi th a Teridian 71M6xx3 isolated sensor by setting the RMTx_E control
bits (I/O RAM 0x270 9[ 5:3]). The 71M6xx3 communicates w ith th e 71 M654 3 using a bi-directional digital data
stream through an isolating pulse transformer. T he 71M65 43 also supplies power to the 71M6xx3 through
the isolat ing transfor me r. This type of interface is further described at the end of th is cha pter . See 2.2.8
71M6xx3 Isolated Sensor Interface.
For use with Cur r ent Transf ormers (CTs), as sho wn in Figure 3, the RMTx_E control bits are reset, so that
IADC2-IADC3, IADC4-IADC5 and IADC6-IADC7 are configured as local analog inputs. The IADC0-IADC1
pins cannot be c onfi gur ed as a remote sensor int erface.
2.2.2 Inp ut Mu lt iple x e r
When operating with locally connected sensors, the input multiple xer sequentially applies the input signals
from the analog input pins to the input of the ADC (see Figure 3), according to the sampling sequence
determined by the eleven MUXn_SEL[3:0] control fie lds. One complete sampling sequence is called a
multiplexer frame. The multiplexer of the 71M6543 can select up to eleven i nput si gnals when the current
se ns or inputs are configured for single-ended mode. When the current sensor inputs are configured in
differential mode (recommended for best performance), the number of input signals is se ven (i.e., IADC0-
IADC1, IADC2-IADC3, IADC4-IADC5, IADC6-IADC7, VADC8, VADC9 and VADC10) per multiplexer frame.
The number of slots in the multiplexer frame is controlled by the I/O RAM control field MUX_DIV[3:0] (I/ O
RAM 0x2100[7:4]) (see Figure 4). The mul t i pl ex er alwa ys sta rt s at stat e 0 and proceeds until t he num ber
of sensor channels determined by the MUX_DIV[3:0] fiel d sett i ng have be en conver ted.
The 71M6543 req uires a unique CE co de that is wr itte n for th e specific met er c onfigur ati on. Mor eover,
eac h CE code req uires specifi c A FE and MU X sett ings i n ord er to fu nc tion pro perly. Table 1 provides
the CE code and settings correspo nding to the 1-Local / 3-Remote sen sor co nf i gur ati on sh own in
Figure 2. Table 2 provides the CE c ode and settings corresponding to the CT conf iguration shown in
Figure 3.
71M6543F/H and 71M6543G /GH Data Sheet
v1.2 © 2008–2011 Teridian Sem iconduc tor Corpor ation 15
Table 1. Required CE Cod e and Settin gs for 1-Local / 3-Remotes
I/O RAM
Mnemonic
I/O RAM
Location
I/O RAM Setting Comments
FIR_LEN[1:0]
210C[2:1]
1
288 cycles
ADC_DIV
2200[5]
0
Fast
PLL_FAST
2200[4]
1
19.66 MHz
MUX_DIV[3:0]
2100[7:4]
6
See note 1
MUX0_SEL[3:0]
2105[3:0]
0
Slot 0 is IADC0-IADC1
(IN)
MUX1_SEL[3:0]
2105[7:4]
1
Unused (See note 2)
MUX2_SEL[3:0]
2104[3:0]
1
Unused (See note 2)
MUX3_SEL[3:0]
2104[7:4]
8
Slot 3 is VADC8
(VA)
MUX4_SEL[3:0]
2103[3:0]
9
Slot 4 is VADC9
(VB)
MUX5_SEL[3:0]
2103[7:4]
A
Slot 5 is VADC10
(VC)
MUX6_SEL[3:0]
2102[3:0]
0
Sl ots not enabl ed
MUX7_SEL[3:0]
2102[7:4]
0
MUX8_SEL[3:0]
2101[3:0]
0
MUX9_SEL[3:0]
2101[7:4]
0
MUX10_SEL[3:0]
2100[3:0]
0
RMT2_E
2709[3]
1
Enable Remote IADC2-IADC3
(IA)
RMT4_E
2709[4]
1
Enable Remote IADC4-IADC5
(IB)
RMT6_E
2709[5]
1
Enable Remote IADC6-IADC7
(IC)
DIFF0_E
210C[4]
1
Differential IADC0-IADC1
(IN)
DIFF2_E
210C[5]
0
See note 3
DIFF4_E
210C[6]
0
See note 3
DIFF6_E
210C[7]
0
See note 3
PRE_E
2704[5]
1
IADC0-IADC1 Ga in = 8
EQU[2:0]
2106[7:5]
5
IA*VA + IB*VB + IC*VC
CE Codes
(See not e 4)
ce43b01660 3 ( use with 71M6603)
ce43b01610 3 ( use with 71M6103)
ce43b01611 3 ( use with 71M6113)
ce43b01620 3 ( use with 71M6203)
Equation(s)
5
Current S ensor T y pe
1 Local S hunt and 3 Remote Shunts
Applicable Figures
Figure 2, Figure 4 and Figure 31
Notes:
1. MUX_DIV[3:0] should be set t o 0 while wri ting the other val ues i n this table, and then set
to t he indicated v alue bef or e wri ting the MUXn_SEL[3:0] fields.
2. Eac h unused sl ot must be assigned to a valid (0 t o A), but unused ADC handle
3. T his channel is remote (71M6xx3), hence DIFFx_E is irrel ev ant
4. Must u se the CE c ode that correspond s to the specific 71M6xx3 device used
Teridian updat es the CE c ode peri odically . Please cont ac t your local Teridian representative
to obt ain the latest CE code and t he associated settings.
71M6543F/H and 71M6543G /GH Data Sheet
16 © 2008–2011 Teridian Sem iconduc tor Corpor ation v1.2
Table 2. Required CE Cod e and Settin gs for CT S ensors
I/O RAM
Mnemonic
I/O RAM
Location
I/O RAM Setting
(Hex)
Comments
FIR_LEN[1:0]
210C[2:1]
1
288 cycles
ADC_DIV
2200[5]
0
Fast
PLL_FAST
2200[4]
1
19.66 MHz
MUX_DIV[3:0]
2100[7:4]
7
See note 1
MUX0_SEL[3:0]
2105[3:0]
2
Slot 0 is IADC2-IADC3
(IA)
MUX1_SEL[3:0]
2105[7:4]
8
Slot 1 is VADC8
(VA)
MUX2_SEL[3:0]
2104[3:0]
4
Slot 2 is IADC4-IADC5
(IB)
MUX3_SEL[3:0]
2104[7:4]
9
Slot 3 is VADC9
(VB)
MUX4_SEL[3:0]
2103[3:0]
6
Slot 4 is IADC6-IADC7
(IC)
MUX5_SEL[3:0]
2103[7:4]
A
Slot 5 is VADC10
(VC)
MUX6_SEL[3:0]
2102[3:0]
0
Slot 6 is IADC0-IADC1
(IN – S ee note 2)
MUX7_SEL[3:0]
2102[7:4]
0
Sl ots not enabl ed
MUX8_SEL[3:0]
2101[3:0]
0
MUX9_SEL[3:0]
2101[7:4]
0
MUX10_SEL[3:0]
2100[3:0]
0
RMT2_E
2709[3]
0
Local S ensor IADC2-IADC3
RMT4_E
2709[4]
0
Local S ensor IADC4-IADC5
RMT6_E
2709[5]
0
Local S ensor IADC6-IADC7
DIFF0_E
210C[4]
1
Differential IADC0-IADC1
DIFF2_E
210C[5]
1
Differential IADC2-IADC3
DIFF4_E
210C[6]
1
Differential IADC4-IADC5
DIFF6_E
210C[7]
1
Differential IADC6-IADC7
PRE_E
2704[5]
0
IADC0-IADC1 Ga in = 1
EQU[2:0]
2106[7:5]
5
IA*VA + IB*VB + IC*VC
CE Code
ce43a02
Equation(s)
5
Current S ensor T y pe
4 Current Transform er s (CT s)
Applicable Figures
Figure 3, Figure 4 and Figure 32
Notes:
1. MUX_DIV[3:0] should be set t o 0 while wri ting the other val ues i n this table, and then set to
the indicated value bef or e writing the MUXn_SEL[3:0] fields.
2. I N is the opti onal Neutral Current
Teridian updat es the CE c ode peri odically . Please cont ac t your local Teridian representative to
obtain the latest CE code and the associat ed settings.
71M6543F/H and 71M6543G /GH Data Sheet
v1.2 © 2008–2011 Teridian Sem iconduc tor Corpor ation 17
Usi ng settings for the I/O RA M Mnemonics l ist ed in Table 1 and Table 2 that do not mat c h
those req uired by the c orrespon ding CE c ode being u sed may re sul t i n unde si ra bl e sid e
effects and must not b e selected by the M PU. Con sul t your local Teridian r epre se ntati ve to
obtai n the corr ec t CE code and AFE / MUX settin gs c or responding to the application.
For a polyphase confi gur ati on wi th neutr al cur r ent sensi ng usi ng shunt r esi stor c ur r ent sensors and the
71M6xx3 isolated sensors, as shown in Figure 2, the IADC0-IADC1 input must be confi gur ed as a
differential input, to be connected to a local shunt (see Figure 30 for the shunt connect ion det ails). The
loc al shunt c onnec ted to the I ADC0-IADC1 input is used to sense the Neutral current. The voltage
sensors (V ADC8, VADC9 and VADC10) are also directly connected to the 71M6543 (see Figure 27 for
the connec ti on details) and are also routed though t he multiplex er , as seen i n Figure 2. Meanwhil e, t he
IADC2-IADC3, IADC4-IADC5 and IADC6-IADC7 curren t inputs are configur ed as remote sensor digi tal
interf ac es and the c or r espondi ng samples are not routed t hr ough the multiplex er . For this confi gur ation,
the multipl ex er sequence is as shown in Figure 4.
For a polyphase confi gur ati on wi th optional neut r al current sensing usi ng Cur r ent Tr ansformer (CTs)
sensors, as shown in Figure 3, all f our curr ent sensor inputs must be configured as a diff er ential input s, to
be connect ed to their c orresponding CTs (see Figure 29 for the differential CT connec tion details). The
IADC0-IADC1 current sensor input is optionally used to sense the Neut r al current for anti-tampering
purposes. T he voltage sensors (VADC8, VADC9 and VADC10) are directly c onnec ted t o the 71M6543
(see Figure 27 for the volt age sensor connect ion det ails). No 71M 6x x3 isolated sensors are u sed i n thi s
configuration and all sensors are routed though the multi plex er , as seen in Figure 3. Fo r th is
configuration, the multiplex er sequence is as shown in Figure 5.
The multipl ex er sequence sho wn in Figure 4 corr esponds to the c onfiguration shown i n Figure 2. T he
fram e dur ation is 13 CK32 cycles (where CK32 = 32,768 Hz ) , therefor e, t he r esul ting sample rate is
32,768 Hz / 13 = 2,520.6 Hz. Note that Figure 4 onl y shows the current s that pass thr ough the 71M6543
m ultiplexer, and does not show the cur r ents that ar e c opied directly into CE RAM fr om the remot e
sensors (see Figure 2), which are sampl ed duri ng the second half of the multiplexer frame. T he two
unused conversi on sl ots shown are nec es sary to produce the desi r ed 2,520.6 Hz sample r ate.
CK32
MUX STATE 0 1 2 3 4 5
MUX_DIV[3:0] = 6 Conversions
Settle
Multiplexer Frame
S
CROSS
MUX_SYNC
S
IN Unused Unused VA VB VC
Figure 4: States in a Multip lexer Frame (MUX_DIV[3:0] = 6)
The multipl ex er sequence sho wn in Figure 5 corr esponds to the CT configuration shown i n Figure 3.
Si nc e in this case all curr ent sensors are l oc ally connected to the 71M6543, all c ur r ents are routed
through the multi plexer, as seen in Figure 3. For this m ultiplexer sequence, t he frame dur ation is 15 CK32
cycles (where CK32 = 32, 768 Hz ), therefore, the resul ting sam ple rate is 32,768 Hz / 15 = 2,184.5 Hz.
CK32
MUX STATE 0 1 2 3 4 5
MUX_DIV[3:0] = 7 Conversions Settle
Multiplexer Frame
S
CROSS
MUX_SYNC
S6
IA VA IB VB IC VC IN
Figure 5: States in a Multip lexer Frame (MUX_DIV[3:0] = 7)
71M6543F/H and 71M6543G /GH Data Sheet
18 © 2008–2011 Teridian Sem iconduc tor Corpor ation v1.2
Multiplexer advance, FI R initiation and chopping of the ADC re ference voltage (using the internal CR OSS
signal , see 2.2.7 V oltage Refer enc es) are controlled by the int ernal M UX_CTRL circuit. Additionally,
MUX_CTRL l aunc hes each pass of th e CE throu gh its c ode. MUX_CTRL is clocked by CK32, the 32768 Hz
clock fr om the PLL bloc k . T he behav ior of the MUX_CTRL circuit is governed by:
• CHOP_E[1:0] (I /O RA M 0x2106 [3 :2])
• MUX_DIV[3:0] (I/O RA M 0x21 00[ 7:4])
• FIR_LEN[1:0] (I/O RAM 0x210C[2:1])
• ADC_DIV (I/O RAM 0x220 0[ 5])
The durati on of each multiplexer state depends on the num ber of ADC samples processe d by the FIR as
determined by the FIR_LEN[1:0] (I/O RAM 0x210C[2:1] control fie ld. Each multiplexer stat e star ts on the
ri si ng edge of CK32, the 32-kHz clock.
It is r ecommended that MUX_DIV[3: 0] (I/O RAM 0x2200[2:0]) be set to zero while changing the A DC
configuration, to minimize sys te m transien ts tha t migh t be caused by momen tary sho r ts between th e ADC
inputs, especially when changing t he DIFFn_E control bits (I/O RAM 0x210C[5:4]). After the configurati on
bits are set, MUX_DIV[3:0] shoul d be set to the r equired value.
The durati on of each time sl ot in CK32 cycles depends on FIR_LEN[1:0], ADC_DIV and PLL_FAST:
Time_Slot_Duration = (3-2*PLL_FAST)*(FIR_LEN[1:0]+1) * (ADC_DIV+1)
The duration of a multiplexer frame in C K32 cycle s is:
MUX_Frame_Duration = 3-2*PLL_FAST + Time_Sl ot_Durati on * MUX_DIV[3:0]
The durati on of a multiplexer frame in CK _FIR cycle s is:
MUX f r am e duration ( CK _FI R c ycles) =
[3-2*PLL_FAST + Time_Slot _Dur ation * MUX_DIV] * (48+PLL_FAST*102)
The ADC co nversion seq uence is p r ogrammable through t he MUXn_SEL control fi elds ( I/ O RAM 0x 2100
to 0x2105). As stat ed above, there are up to ele ven ADC tim e sl ots in the 71M6543, as set by
MUX_DIV[3:0] (I/O RAM 0x 210 0[7:4]). In the expression MUXn_SEL[3:0] = x, ‘n’ refers to the multiplexer
frame time slot number and ‘x’ refers to the desired ADC input number or ADC handle (i.e., IADC0 to VADC10,
or simply 0 to 10 decimal). Thus, there are a total of 11 valid ADC handles in the 71M6543 devices. For
examp le, if MUX0_SEL[3:0] = 0, then IADC0, corresponding to the sample from the IADC0-IADC1 input
(configured as a differential input), is positio ne d in the multiplexer frame during time slot 0. See Table 1 and
Table 2 f or the appropriate MUXn_SEL[3:0] setting s and othe r settings appl icable to a part icular meter
conf i gu rati o n an d CE co de.
Note that when the r emot e sen s or interface is ena bled, the samples corresp ondi ng t o the remote
sensor curr ents do not pass through the 71M6543 multiplexer. The sampling of the remote current
sen s ors occ urs in the second half of the multi plexer frame. The VA, VB an d VC vol tages are assigned
the la s t three sl ots in th e fr ame. With this sl ot assignment for VA, VB an d V C, the sam pl i ng of the
corresponding remote sensor currents bears a precise timing relatio nship to their correspon din g phase
v olt age s, and delay com pe n sati on i s acc ur atel y pe rf or m ed (se e 2.2.3 Delay Com pensation on page 19).
Al so whe n usi ng r em ote sensors, i t is necessary to introduce u nused slots to real ize the numb er of
sl ot s speci f i ed by the MUX_DIV[3:0] (I/O RAM 0x2100[7:4]) fiel d setting (see Figure 4 and Figure 5). T he
MUXn_SEL[3:0] c ontrol fields for th ese unused (“dummy”) slots mu st be wr itten wit h a valid ADC handle
(i .e., 0 to 1 0 decimal) that is not otherwise being used. In this m anner, th e un used ADC handle, i s used
as a “dummy” place holder in t he mul ti plexer frame, and the cor re ct duration multipl exer fram e
sequence is gene rat ed and also the desired s ample rate. The res ult ing s ample data stored in the CE
RAM locatio n cor responding to the “dummy” A DC h andle is ignore d by the CE code. Mean while, the
digit al isolation inter face tak es c are of automatically storin g th e samples for the remot e current sensors
in the appropr iate CE RAM locations.
71M6543F/H and 71M6543G /GH Data Sheet
v1.2 © 2008–2011 Teridian Sem iconduc tor Corpor ation 19
Delay c om pensation and ot her functions in t he CE code requir e the sett ings for MUX_DIV[3:0],
MUXn_SEL[3:0], R MT_E, FIR_LEN [1:0], ADC_DIV and PLL_FAST to be fixed for a giv en CE code.
Refer to Table 1 and Table 2 for the settings that ar e applicable to the 71M6543.
Table 3 summariz es the I/ O RAM registers used for c onfiguring t he m ultiplexer, signal s pins, and ADC. All
list ed registers are 0 aft er reset a nd wake from bat tery mo des, and are rea dable and writa ble.
Table 3: Mul tipl exer and ADC Configuration Bits
Name Location Description
MUX0_SEL[3:0]
2105[3:0] Selects the AD C inpu t c onv erted durin g t ime slot 0.
MUX1_SEL[3:0]
2105[7:4]
Selects the AD C input co nverted d uring time slot 1.
MUX2_SEL[3:0] 2104[3:0] Selec ts the ADC i nput co nverted d uring time slot 2.
MUX3_SEL[3:0] 2104[7:4] Selec ts the ADC i nput co nverted d uring time slot 3.
MUX4_SEL[3:0] 2103[3:0] Selec ts the ADC i nput co nverted d uring time slot 4.
MUX5_SEL[3:0]
2103[7:4] Selects the AD C inpu t c onv erted durin g t ime slot 5.
MUX6_SEL[3:0] 2102[3:0] Selec ts the ADC i nput co nverted d uring time slot 6.
MUX7_SEL[3:0]
2102[7:0] Selects the AD C inpu t c onv erted durin g t ime slot 7.
MUX8_SEL[3:0] 2101[3:0] Selec ts the ADC i nput co nverted d uring time slot 8.
MUX9_SEL[3:0] 2101[7:0] Selec ts the ADC i nput co nverted d uring t i me sl ot 9.
MUX10_SEL[3:0] 2100[3:0] Selects the AD C inpu t c onv erted durin g t ime slot 10.
ADC_DIV 2200[5]
Controls the rate of the ADC and FIR clocks.
MUX_DIV[3:0] 2100[7:4] The number of ADC time s lots in each multiple xe r frame (maximum = 11).
PLL_FAST 2200[4] Control s the speed of the PLL and MCK.
FIR_LEN[1:0] 210C[2:1]
Determines the n umber of A D C cy c les i n the A D C d eci mat ion F IR filter .
DIFF0_E
210C[4] Enables the differential configuration for anal og input pins IADC0-IADC1 .
DIFF2_E 210C[5] Enables the differential configuration for anal og input pins IADC2-IADC3 .
DIFF4_E 210C[6] Enables the differential configuration for anal og input pins IADC4-IADC5 .
DIFF6_E 210C[7] Enables the differential configuration for anal og input pins IADC6-IADC7 .
RMT2_E 2709[3] E nables the re mote sensor inte rface transforming pins IADC2-IADC3 into a digital
interface for communications with a 71M6xx3 sensor.
RMT4_E 2709[4] E nables the re mote sensor inte rface transforming pins IADC4-IADC5 into a digital
int erface for communicati ons with a 71M6xx3 sensor.
RMT6_E 2709[5] E nables the re mote sensor inte rface transforming pins IADC6-IADC7 into a digital
int erface for communicati ons with a 71M6xx3 sensor.
PRE_E 2704[5] Enables t he 8x pre-amplifier.
Refer to Table 71 start ing on page 104 for m ore complete deta ils abo ut t hes e I/O R AM l ocation s.
2.2.3 Delay Compensation
When measuring the energy of a phase (i .e., Wh and VARh) i n a serv ice, t he v oltage and current f or that
phase must be sampled at t he same instant . Otherwise, the phase difference, Ф, introduces errors.
o
delay
o
delay ft
T
t360360 ⋅⋅=⋅=
φ
Where f is the frequency of t he input signal, T = 1 /f and tdelay is the sam pling delay between current and
voltage.
Traditionally, sa mpling is accomplished by using two A/D c onverters per phase (one for v oltage and the
other one for cur r ent) c ontrolled t o sample sim ultaneously. Teridian’s Si ngle-Converter Technology®,
howev er , exploit s the 32-bit signal processing capability of it s CE to implement “constant del ay ” all -pass
filters. The a ll-pass filt er corr ec ts for the conversi on time diff erenc e between the vol tage and the
correspondi ng c ur r ent samples that ar e obtained with a single m ultiplexed A/D conver ter.
The “c onstant del ay ” all -pass fi lter provides a broad-band delay 360o - θ, which is precisely m atched to
the dif ference in sample time between the voltage and the current of a given phase. This digital f ilter does
not affect t he ampli tude of the si gnal, but pr ov ides a precisely c ontrolled phase response.
71M6543F/H and 71M6543G /GH Data Sheet
20 © 2008–2011 Teridian Sem iconduc tor Corpor ation v1.2
The rec ommended ADC multiplexer sequence sam ples the curr ent fi r st, immediately fol lowed by
sampling of the cor r espondi ng phase voltage, thus the voltage is delayed by a phase angle Ф relative to
the cur r ent. The delay c om pensation implem ent ed in the CE aligns the volt age samples with their
correspondi ng c ur r ent samples by first delay ing the current samples by one full sample interval (i.e.,
360o), then routi ng the voltage samples through t he all-pass filter, thus delaying the vo ltage samples by
360o - θ, resulting in the residual phase error bet ween the cur r ent and its correspondi ng voltage of θ – Ф.
The resi dual phase error is negligible, and is typi c ally less than ±1. 5 mil li-degrees at 100Hz, thus it does
not contribut e to errors in the energy measurements.
When using r em ote sensors, the CE perform s the same delay c om pensation descri bed above to align
each voltage sample wit h its correspondi ng current sample. Even though the rem ote current samples do
not pass through the 71M 6543 multi plexer, their timing relationship to their corresponding vo ltages is
fixed and preci sel y known, provided that t he MUXn_SEL[3:0] slot assignment fields are programm ed as
shown in Table 1. Note that these slot assignments result in VA, VB and VC occupyi ng m ultipl ex er slot s
3, 4 and 5, respectively ( see Figure 4).
2.2.4 ADC P re-Amplifier
The ADC pr e-amplifier is a low-noi se different ial amplifier wit h a fixed gain of 8 available only on the
IADC0-IADC1 sensor input pins. A gain of 8 is enabled by setting PRE_E = 1 (I/O RAM 0x2704[ 5]). When
disabl ed, the suppl y c ur r ent of the pr e-amp lifier is <10 nA and t he gain is unity. With pro per sett ing s of the
PRE_E and DIFF0_E (I/O RAM 0x210C[4]) bit s, the pre -am pl i f i er can b e use d whet h er di ff erentia l mode
is selected or not . F or best perf ormance, the differential mode is recommended. In order to save power,
the bias current of the pre-amplifier and ADC is adjusted ac cording to the ADC_DIV control bit (I /O RAM
0x2200[5]).
2.2.5 A/ D Co nve rter (ADC)
A single 2nd order sigma-delta A/D converter digiti z es the voltage and current inputs to the device. The
resolution of the ADC, including the sign bit, is 21 bits (FIR_LEN[1:0] = 01, I/O RAM 0x210 C[ 2:1]), or 22
bits (FIR_LEN[1:0] = 10). The ADC is clocked by CKADC.
Initiation of each ADC conversion is controlled by the internal MUX_CTRL circuit as described earlier. At
the end of eac h ADC conversion, the FIR filter output data is stored into the CE RAM location determined by
the multiplexer selection.
2.2.6 FIR Fi lte r
The finite impulse response filter is an integral part of the ADC and it is optimized for use with the multiplexer.
The purpose of the FIR fil ter is to dec imate the ADC output to t he desi r ed r esol ution. At t he end of eac h
ADC conversi on, t he output data is stored i nto t he fixed CE RAM location determi ned by the multipl exer
selection stor ed in the MUXn_SEL[3:0] fields. FIR dat a is stored after being shifted left by 9 bit s .
2.2.7 Voltage References
A bandgap c ircu it provides the re ferenc e voltage to the ADC . The amplifier w ithin the reference is chopper
stabilized, i.e., the chopper ci r c uit can be enabled or disabled by the M P U usi ng the I/O RAM control field
CHOP_E[1:0] (I/O RAM 0x2106[3 :2]). The tw o bits in the CHOP_E[1:0] field ena ble the MPU t o operate t he
chopper c ircuit in regular or i nvert ed oper ati on, or in toggl in g modes (recommended). When the chopper
ci r c uit is toggled in b etween multiplexer cycles, dc offset s on VREF are automatically be aver aged out,
therefore the chopper circ uit should always be confi gur ed for one of the t oggling modes.
Since the VREF band-gap amplifier is cho ppe r-stabilized, the dc offset voltage, which is the most
significant long-term drift mechanism in the voltage re fe rences (VREF ) , is automatic ally r em ov ed by the
chopper circ uit. B oth the 71M6543 and the 71M 6xx3 f eature c hopper c ircuits for their r espect ive VREF
v oltage ref er enc e.
The general topol ogy of a chopped am plifi er i s shown in Figure 6. The CROSS si gnal is an i nternal on-
chip signal and is not accessible on any pin or register .
71M6543F/H and 71M6543G /GH Data Sheet
v1.2 © 2008–2011 Teridian Sem iconduc tor Corpor ation 21
Figure 6: General Topology of a Chopped Amplifier
It is as s umed that an offset voltage V off appears at the positive am plif ier inp ut. With all switches, as
controlled by CROSS ( an internal signal), in the A position, the out put voltage is:
Voutp – Voutn = G (Vinp + Voff – Vinn) = G (Vinp – Vinn) + G Voff
With al l switc hes set to the B position by applying the inverted CROS S signal, the output v oltage is:
Voutn – Voutp = G (Vinn – Vinp + Voff) = G (Vinn – Vinp) + G Voff, or
Voutp – Voutn = G (Vinp – Vinn) - G Voff
Thus, when CROSS is toggled, e.g., aft er eac h m ultiplexer cycle, the offset alternat ely appears on the
output as posit ive and negative, whic h r esults i n the offset effectively bei ng elimi nated, regardless of its
polarity or magnitude.
When CROSS is high, the connection of the amplifier input devices is reversed. This pre s erves th e overall
polarity of that amplifier gain; it inverts its input offset. By a lternately reversing the connection, the amplifier’s
offset is averaged to zero. Thi s remov es the m ost si gnificant long-term drift mechanism in the voltage
reference. The CHOP_E[1:0] (I/ O RAM 0x2106[3:2]) control field controls the be havi or of CROSS. On th e
first CK32 rising edge after the last multiplexer state of its sequence, the multiplexer waits one additi onal
CK32 cyc le before beginning a new frame. At the beginning of thi s cycl e, t he val ue of CROSS is updated
according to the CHOP_E[1:0] field. The extr a CK32 cycl e allows time for the chopped VREF to settle.
During this cycle, MUXSYNC is held high. T he leading ed ge of MUXSYNC initiates a pass through the CE
program sequence.
CHOP_E[1:0] has four states: posit ive, rever se, and two toggle states. In the positive state, CHOP_E[1:0]
= 01, CRO S S is held low . In the re verse state, CHOP_E[1:0] = 10, CROS S is held high. The two
automati c toggling stat es are selec ted by setting CHOP_E= 11 or CHOP_E=00.
Figure 7: CROSS Signal with CHOP_E = 00
Figure 7 shows CROSS over two accum ulati on intervals when CHOP_E[1:0] = 00: At the end of the
first interval, CROSS i s hi gh, at the end of the second interval, CROSS is l ow. Oper ation with
CHOP_E[1:0] = 00 does not require control of t he chopping mechanism by the MPU.
In t he second t oggle state, CHOP_E[1:0] = 11, CROS S does not toggle at the end of the last multiple xer
cycle in an accumulation i nterval.
G
-
+V
inp
V
outp
V
outn
V
inn
CROSS
A
B
A
B
A
B
A
B
71M6543F/H Data S heet 8
22 © 2008-2010 MAXIM/TERIDIAN Semiconductor Corporation v1.2
2.2.8 71M6xx3 Isolated Sensor Interface
2.2.8.1 General Description
Non-isol ati ng sensors, such as shunt r esi stors, c an be c onnec ted to t he inputs of the 71M6543 via a
combination of a pulse transf ormer and a 71M6xx3 IC (a top-level block diagram of this sensor i nterfac e
is shown in Figure 31). The 71M 6xx3 receives power directly from the 71M6543 via a pulse transformer
and does not require a dedicated power supply circuit. The 71M6xx3 establ ishes 2-way communicati on
with t he 71M 6543, supplying current samples and auxiliary information such as sensor t emperature v ia a
serial data str eam .
Up to three 71M6xx3 Isolat ed Sen s ors can be s upp orted by t he 71M 6 54 3. When a remote sensor
interface is e nabled, the two analog current inputs become re-c onfi gur ed as a digital r em ote sensor
interf ac e. For exam ple, when control bit RMT2_E = 1, the IADC2-IADC3 analog pins are re-c onfigured as
the digital interface pins to the r em ote sensor.
Each 71M6xx3 I sol ated Sensor consi sts of the f ollowing building blocks:
• Power supply that derives power from pulses received from the 71M 6543
• Bi-direc tional di gital communi c ations interfac e
• Shunt signal pre-amplifier
• 22-bit 2nd Order Si gm a-Delta ADC Converter with precision bandgap r efer enc e (chopping amplif ier)
• Temperature sensor (for digitally compensating VREF)
• Fuse system contai ning par t-specifi c i nform ation
Duri ng an or dinary multiplexer cycle, t he 71M6543 internally determines which ot her c hannels are
enabled with MUX_DIV[3:0] (I/O RAM 0x2100[7:4]). At the same time, it decim ates the modulator output
from the 71M6xx3 Isolat ed Sensors. Each result is written to CE RAM during one of its CE access time
slots.
2.2.8.2 Communi cat io n b etween 71M6543 and 71M6xx3 Isolated Sensor
The ADC of the 71M6xx3 derives its timing from the power pulses generated by the 71M6543 and as a
result, operates its ADC slaved to the frequency of the power pulses. The generation of power pulses, as well
as the communication protocol between the 71M6543 and 71M6xx3 Isolated Sensor, is automatic and
transparent to the user. Details are not covered in this data sheet.
2.2.8.3 Control of the 71M6xx3 Isolated Sensor
The 71M6543 can read or write certain types of information from each 71M6xx3 remote sensor.
The data to be read is selected by a combination of the RCMD[4:0] and TMUXRn[2:0]. To perform a read
transaction from one of the 71M6xx3 de vices, the MPU first w rites the TMUXRn[2:0] field (where n = 2, 4, 6,
loc ated at I/O RAM 0x270A[2:0], 0x270A[6:4] and 0x2709[2:0], respectively). Next, the MPU writes
RCMD[4:0] (SFR 0xFC[4:0]) with the desired c ommand and phase select ion. When the RCMD[4:2] bits
have c leare d to zer o, the transac tion has bee n completed and th e reque s ted dat a is availabl e in
RMT_RD[15:0] (I/O RAM 0x2602[7:0 ] is the MSB and 0x2603[7:0] is the LSB). The read parity error bit,
PERR_RD (SFR 0xFC[6]) is also updated during the transaction. If the MP U writes to RCMD[4:0] before a
previously initi ated read transaction is completed, the command is ignored. Ther efore, the MPU must wait
for RCMD[4:2]=0 before proc eeding to issue the next remote sens or read command.
If the CE is running (CE_E=1), the MPU must w rite RCMD[4:0] immediately after a CE_BUSY rising
edge. RCMD[4:0] m ust be wri tten before t he next ri si ng edge of MUX_SYNC. Failure to do this can cause
inc or r ec t dat a to be read.
The RCMD[4:0] field is divided into two sub-fields, COMMAND=RCMD[4:2] and PHASE=RCMD[1:0], as
shown in Table 4.
.
8 71M6543F/H Data Sheet
v1.2 © 2008–2011 Teridian Sem iconduc tor Corpor ation 23
Table 4. RCMD[4:0] Bits
Command
RCMD[4:2]
Phase S electo r
RCMD[1:0]
Associated TMUXRn
Contr ol Field
000
Invalid
00
Invalid
---
001
Command 1
01
IADC
2
-IADC3
TMUXR2[2:0]
010
Command 2
10
IADC
4
-IADC5
TMUXR4[2:0]
011
Reserved
11
IADC
6
-IADC7
TMUXR6[2:0]
100
Reserved
101
Invalid
110
Reserved
111
Reserved
Notes:
1. Only two codes of RCMD[4:2] (SFR 0xFC[4:2]) are relevant f or normal
operation. These are RCMD[4:2] = 001 and 010. Codes 000 and 101
are i nv alid and will be ignored if used. The r em aining codes are
reserved and must not be used.
2. F or the RCMD[1:0] contr ol field, codes 01, 10 and 11 are valid and 00
is i nv alid and m ust not be used.
3. T he specif ic phase (A, B or C) associat ed with each TMUXRn[2:0]
field, is de termined by how the I A DCn input pins are connect ed in the
m eter desi gn.
Table 5 shows the allowable combinations of val ues i n RCMD[4:2] and TMUXRn[2:0], and the
corresponding data type and format sent back by the 71M6xx3 remote sensor and ho w the dat a is stored
in RMT_RD[15:8] and RMT_RD[7:0]. The MP U select s which of the three phases is read by asserting the
proper code in the RCMD[1:0] field, as shown i n Table 4.
.
Table 5: Remo t e Interface Read Commands
RCMD[4:2] TMUXRn[2:0] Read Op era tion RMT_RD [15:8] RMT_RD [7:0]
001 00X TRIMT[7:0]
(trim fuse for all 71M6xx3)
TRIMT[7]=RMT_RD[8] TRIMT[6:0]=RMT_RD[7:1]
001 11X TRIMBGB[7:0] and
TRIMBGD[7:0]
(additional trim fuses for
71M6113 and 71M6203 only)
TRIMBGB[7:0] TRIMBGD[7:0]
010 00X
STEMP[10:0]
(sensed 71M6xx3 temperature)
STEMP[10:8]=RMT_RD[10:8]
(RMT_RD[15:11] are si gn extended ) STEMP[7:0]
010 01X VSENSE[7:0]
(sensed 71M6xx3 supply v oltage)
All zeros VSENSE[7:0]
010 10X VERSION[7:0]
(chip version) VERSION[7:0] All zeros
Notes:
1. TRIMT[7:0] is the V REF t rim value for all 71M6xx3 devices. Note th at the TRIMT[7:0] 8-bit value is for med
by RMT_RD[8] and RMT_RD[7:1]. See the 71M6xxx Data Sheet for the equations related to TRIMT[7:0]
and the correspond ing tempe rature coefficient .
2. TRIMBGB[7:0] and TRIMBGD[7:0] are trim values used for characteriz ing the 71M6113 (0.5%) and 71M6203
(0.1%) over temperature. See the 71M6xxx Data sheet for the equations re lated to TRIMBGB[7:0] and
TRIMBGD[7:0] and the corresponding temperature coefficients.
3. See 2.5.6 71M 6xx3 Temperat ur e Sensor on page 56.
4. See 2.5.8 71M 6xx3 VCC Moni tor on page 57.
With hardware and trim-related information on eac h c onnected 71M6xx3 Isol ated Sensor a vailable to the
71M6543, the MPU can implement temperature compensation of the energy measurement ba sed on the
individual temperature characteri stics of the 71M6xx3 Isolat ed S ensors. See 4.5 Metrology Temperature
Compensation for detail s.
Table 6 shows al l I /O RAM registers used for cont r ol of the ext er nal 71M 6xx3 Isolat ed S ensors. See t he
71M6xx3 Data Sheet for additional details.
71M6543F/H Data S heet 8
24 © 2008-2010 MAXIM/TERIDIAN Semiconductor Corporation v1.2
Table 6: I/O RAM Control Bits for Isolated Sensor
Name Address
RST
Default
WAKE
Default R/W Description
RCMD[4:0] SFR
FC[4:0] 0 0 R/W
When the MPU writes a non-zero value to RCMD,
the 71M6543 issues a command to the cor-
respondi ng isol ated sensor selected wit h
RCMD[1:0]. When the co mmand is co mplete , the
71M6543 clears RCMD[4:2]. The command code
itself is in RCMD[4:2].
PERR_RD
PERR_WR SFR FC[6]
SFR FC[5] 0 0 R/W The 71M6543 sets t hes e bit s to ind icate that a
pari ty error on the i sol ated sensor has been de-
tected. On ce s et, t he bi t s are remember ed until
they ar e cl ear ed by the MP U.
CHOPR[1:0] 2709[7:6] 00 00 R/W
The CHOP settings for the isolated sensors.
00 – Auto chop. Change every multiplexer frame.
01 – Positive
10 – Negative
11 – Same as 00
TMUXR2[2:0] 270A[2:0] 000 000 R/W The TMUX bits for control of the is olated sensor.
TMUXR4[2:0]
270A[6:4]
000
000
R/W
The T M UX bits for control of the is olated sensor.
TMUXR6[2:0]
2709[2:0] 000 000 R/W The T M UX bits for control of the isolated sensor.
RMT_RD[15:8]
RMT_RD[7:0]
2602[7:0]
2603[7:0] 0 0 R The read buffer for 71M6xx3 read operations.
RFLY_DIS 210C[3] 0 0 R/W
Controls how the 71M6543 drives the 71M6xx3
power pul se. When set, the power pulse i s driven
high and low. When cleared, it is driven high
followed by an open cir c uit fly-back interva l.
RMT2_E 2709[3] 0 0 R/W
Enabl es the isolated remote sensor interface and
re-configures pins IADC2-IADC3 as a balanced
pair digital remote interfac e.
RMT4_E 2709[4] 0 0 R/W Enabl es the isolat ed r em ote sensor interface and
re-configures pins IADC4-IADC5 as a balanced
pair digital remote interfac e.
RMT6_E 2709[5] 0 0 R/W Enabl es the isolat ed r em ote sensor interface and
re-configures pins IADC6-IADC7 as a balanced
pair digital remote interfac e.
Refer to Table 71 start ing on page 104 for more complete details about t hese I/O RA M locati ons.
71M6543F/H and 71M6543G /GH Data Sheet
v1.2 © 2008–2011 Teridian Sem iconduc tor Corpor ation 25
2.3 Digital Computation Engine (CE)
Th e CE , a de dicate d 32-bit signal proce s s or, performs the precision computat ions nece s s ary to ac curately
m easure energy . The CE calculations and processes inc lude:
• Multiplicati on of each current sample with its assoc iated voltage sample to obtain the energy per
sample (when multipli ed by the constant sam ple time).
• Frequency-insensit ive delay c anc ellati on on all c hannels (t o c om pensate for the delay between
samples caused by the mult iplexing scheme).
• 90° phase shifter (for VAR calc ulations).
• Pulse generat ion.
• Monitoring of the input signal f r equenc y (for frequenc y and phase i nformati on) .
• Monitoring of the input signal amplitude (for sag detec tion).
• Scali ng of the processed samples based on cali br ation coeffic ients.
• Scali ng of sam ples based on tem per ature compensati on informati on.
2.3.1 CE Pr og ram Memo ry
The CE program resides in f lash memory. C ommon ac cess to f lash memory by the CE an d MPU is
controlled by a mem or y share ci rcuit. Each CE instruction word is two bytes long. Allocated flash space
for the CE program cannot exc eed 4096 16-bi t words (8 KB). The CE program counter begins a pass
through the CE code eac h time m ultiplexer state 0 begins. The code pass ends when a HA LT instruction
is executed. For pr oper oper ation, the code pass must be completed before the multiplexer c ycle ends.
The CE pr ogr am must begi n on a 1 KB boundary of the fl ash addre ss. The I/O RAM co ntrol field
CE_LCTN[6/5:0] (I/O RAM 0x2109[6/5:0]) on the 71M6543F/H and CE_LCTN[6:0] (I/O RAM 0x2109[6:0]) on
the 71M6543G/GH defines whi c h 1 K B boundar y c ontains the CE code. Thus, the fir st CE i nstr uc tion is
loc ated at 1024*CE_LCTN[5:0] on the 71M6543F/H and 1024*CE_LCTN[6:0] on the 71M6543G/GH.
2.3.2 CE Da ta Memory
The CE and MPU share data memory (RAM). Common access to XRAM by the CE and MPU is controlled
by a memor y share ci r c uit. The CE can access up to 3 KB of the 5 KB data RAM (XRAM), i.e. from RAM
address 0x 0000 to 0x0C00.
The XRAM can be ac c essed by the F IR fil ter block, the RTM circuit, the CE, and the MPU. Assigned time
slots are reserved for FIR and MPU, respectively, to prevent bus contention for XRAM data access by the CE.
The MPU reads and writes the XRAM shared bet ween the CE and MP U as the primary m eans of data
communication between the t wo processors.
T h e CE i s ai de d by s up p or t h ar d war e t o faci l i t at e im pl ement at i on of equ ation s, p ul s e c ounte r s, an d
accumulators. This hardware is contr oll ed through I/O RAM field EQU[2:0] (equation assi st, I/O RAM
0x2106[7:5]), bit DIO_PV (I/O RAM 0x2457[6]), bit DIO_PW (pulse count assi st, I/ O RAM 0x2457[7]), and
SUM_SAMPS[12:0] (accumulation assi st, I/O RAM 0x21 07[4:0] and 0x2108[7:0]).
The integration time for each energy output, when usi ng standard CE code, is SUM_SAMPS[12:0] /2184.53
(with MUX_DIV[3:0] = 7, I/O RAM 0x210 0[7:4] ). CE hardware i s sue s the XFE R_B US Y interrupt when the
accumulation is co mplete .
2.3.3 CE Communication with the MPU
The CE outputs six signals to the MPU: CE_BUSY, XFER_BUSY, XPULSE, YPULSE, WPULSE and
VPULSE. T hese are connec ted to the MPU interr upt servi c e. CE_BUS Y indi c ates that the CE i s act ively
processi ng data. This si gnal occurs once every multiplexer frame. XFER_BUS Y i ndic ates that the CE is
updating to the output region of the CE RAM, which occurs whenever an accumulation cycle has been
completed. B oth, CE_BUSY an d X FER_ B USY are clea r ed when t he CE executes a HALT instruction.
XPULSE and YPULS E c an be c onfigured to inter r upt the MPU and indicate sag failures, z er o c r ossings of
the mains voltage, or other si gnificant ev ents. Additionally, these signals can be connected directly to DIO
pins to provide direct output s from the CE. Int er r upts associated with these si gnals always occur on t he
leading edge.
71M6543F/H and 71M6543G /GH Data Sheet
26 © 2008–2011 Teridian Sem iconduc tor Corpor ation v1.2
2.3.4 Meter Equations
The 71M6543 provides hardware assistance to the CE in or der to support various met er equations. This
assistance is contr olled t hr ough I/ O RAM field EQU[2:0] (equati on assist, I/O RAM 0x2106[7:5]). The
Compute Engine (CE) firmware configurations can implement the equations l isted in Table 7. EQU[2:0]
spec ifies the equa t ion to be us ed bas ed on th e meter configuration and on the number of p has es used for
metering.
Table 7: Inpu t s Selected in Multiplexer Cycl es
EQU[2:0]* Description Wh and VARh formula Recommended
Multiplexer Sequence
Element 0
Element 1
Element 2
2 2-elemen t, 3-W, 3φ Delta VA ∙ IA VB ∙ IB N/A IA VA IB VB
3 2-elemen t, 4-W, 3φ Delta VA(IA-IB)/2 VC ∙IC N/A IA VA IB VB IC VC
4 2-element, 4-W, 3 φ Wye VA(IA-IB)/2 VB(IC-IB)/2 N/A IA VA IB VB IC VC
5 3-element, 4-W, 3 φ Wye VA ∙ IA VB ∙ IB VC ∙ IC IA VA IB VB IC VC (ID)
Note:
* Only EQU[2:0] = 5 is support ed by the currently available CE c ode v er si ons for the 71M6543. Contact
your local Teridian representativ e for CE codes that support equati ons 2, 3 and 4.
2.3.5 Real-Time Monit or (RTM)
The CE con ta ins a Rea l-T ime Moni tor ( RTM), which can b e programmed to monitor f our s elec table XRAM
locations at full sample rate. The data from the four monitored locations are serially output to the TMUXOUT
pin via the digital output multiplexer at the beginnin g of each CE c ode pass . The RT M c an be e nabled and
disabled with RTM_E (I/O RAM 0x21 06[ 1]). The RTM output clock is avai lable on the TM UX2OUT pin. Each
RTM word is clocked out in 35 cycles and c ontains a leading flag bit. See Figure 8 for the RTM output
format. R TM is low when not in use.
Figure 8: R TM Tim ing
2.3.6 Pulse Generators
The 71M6543 provides four pulse generat or s, VPULSE, WPULSE, XPULSE and YPULSE. The XPULSE
and YPULSE generators are used by standard CE code to output CE status i ndic ators, fo r example the
status of the sag detec tion, to DIO pins. All pulses can be c onfigur ed to generate i nterr upts to the MPU.
The polarit y of the pulses may be inverted with PLS_INV (I/O RAM 0x 210C[0]). When t his bit is set, the
pulses are active high, rat her than t he m ore usual active low. PLS_INV i nverts all the pulse outputs.
The f unc tion of each pul se generat or is determi ned by the CE code and t he MPU code m ust c onfigure the
correspondi ng pulse output s i n agr eement with the CE code. For example, standard CE c ode pr oduc es a
m ains zero-c r ossing pulse on XPULSE and a S A G pulse on YPULSE.
CKTEST
RTM
FLAG
RTM DATA0 (32 bits)
LSB
SIGN
LSB
SIGN
RTM DATA1 (32 bits)
LSB
LSB
SIGN
SIGN
RTM DATA2 (32 bits)
RTM DATA3 (32 bits)
0 1 30 31 0 1 30 31 0 1 30 31 0 1 30 31
FLAG FLAG FLAG
MUX_STATE S
MUX_SYNC
CK32
71M6543F/H and 71M6543G /GH Data Sheet
v1.2 © 2008–2011 Teridian Sem iconduc tor Corpor ation 27
A comm on use of the zer o-c r ossing pulses i s to gener ate interrupts in order to driv e real-time clock
software in places where the mai ns frequenc y is sufficiently accurat e to do so and also to adjust for
crystal aging. A common use for the SAG pulse is to generate an interrupt that alerts the MPU when mains
power i s about to fail, so that the MPU code can stor e accumulated ener gy and other data to EEPROM
before the V3P3S YS supply v oltage act ually dr ops.
2.3.6.1 XPULSE and YPULSE
Pul ses generated by the CE may be ex ported to the XPULSE and YPULS E pul se output pins. Pins
SEG DIO 6 and SEG DIO 7 ar e used for these pulses, respec tively. Generally, the XPULSE and YPULS E
out puts c an be updated once o n each pa s s of the CE code.
See 5.4 CE Interface Description on page 120 for det ails.
2.3.6.2 VPULSE and WPU LSE
Referring to Figure 9, during each CE code pass the hardware stores exported WPULSE and VPULSE sign
bits in an 8-bit FIFO and outputs them at a specified interval. This permits the CE code to calculate the
VPULSE and WPULSE outputs at the beginning of its code pass and to rely on hardwar e to spread th em
over the multiplexer frame. As seen in Figure 9, the FIFO is reset at the beginni ng of each multiplexer
frame. As also seen in Figure 9, the I/ O RAM register PLS_INTERVAL[7:0] (I/O RA M 0x210 B[7:0]) controls
the delay to th e first pulse up date and the interval between s ubseq uent up dates. The LSB of the
PLS_INTERVAL[7:0] register is equivalent to 4 CK_FIR cy c le s (CK_FIR is typically 4.9152MHz if PLL_FAST=1
and ADC_DIV=0, but other CK_FIR frequencies are possible; see the ADC_DIV definition in Table 71.) If
PLS_INTERVAL[7:0]=0, the FIFO is deactivated and the pulse outputs are updated immediately.
The MUX fr am e dur ation in units of CK_FIR cloc k cycles i s given by:
If PLL_FAST=1:
MU X frame d uration i n CK_F IR cyc les = [ 1 + (FIR_LEN+1) * (ADC_DIV+1) * (MUX_DIV)] * [1 5 0 / (ADC_DIV+1)]
If PLL_FAST=0:
MU X frame d uration i n CK_F IR cyc les = [ 3 + 3* (FIR_LEN+1) * ( ADC_DIV+1 ) * (MUX_DIV) ] * [48 / (ADC_DIV+1)]
PLS_INTERVAL[7:0] in units of C K_ FIR clo ck cycles is c alculat ed b y:
PLS_INTERVAL[7:0] = floor ( Mux fram e duration in CK_F IR cycle s / C E p ulse up dates per Mux frame / 4 )
Si nc e the FIFO r esets at the beginni ng of each multiplexer frame, t he user must specify
PLS_INTERVAL[7:0] so that all of the possible pulse updates occurring in one CE ex ec ution are out put
before the multiplexer fr ame completes. For instance, the 71M6543 CE code out puts si x updates per
multiplexer interval, and if the multiplexer int erval is 1950 CK_FIR cl ock cycles long, the ideal value for
the interval is 1950/6/4 = 81.25. Howe ver, if PLS_INTERVAL[7:0] = 82, the sixth out put occ urs too late and
would be lost. In this case, the proper v alue for PLS_INTERVAL[7:0] i s 81 (i. e., r ound down the resul t).
Since one LSB of PLS_INTERVAL[7:0] i s equal t o 4 CK_FIR cloc k cycles, the p ulse t ime interv al T I in u nits of
CK_F IR clo ck cyc le s is:
TI = 4*PLS_INTERVAL[7:0]
If the FIFO is e nab led ( i.e., PLS_INTERVAL[7:0] ≠ 0), hardware also provides a maximu m pulse width feature
in control register PLS_MAXWIDTH[7:0] (I/O RAM 0x210A) . By default, WPULSE and VPULSE are negative
puls es ( i. e . , low leve l p ulses , designed t o s ink c ur r ent throug h an LE D) . PLS_MAXWIDTH[7:0] determines the
maximu m negative p ul se wi d th TMAX in uni t s of CK_F IR cl oc k cy c le s ba se d o n th e p ul se i nt e rv al TI
acc ordi ng to the formula:
TMAX = (2 * PLS_MAXWIDTH[7:0] + 1) * TI
If PLS_MAXWIDTH = 255 or PLS_INTERVAL=0, no pulse widt h c hec k ing is perform ed, and t he pulses
default to 50% dut y cycl e.
The polarit y of the pulses may be inverted with t he c ontrol bit PLS_INV (I/O RAM 0x210C[0]). When
PLS_INV is set, t he pulses are active high. T he default value for PLS_INV i s zero, which sel ec ts active low
pulses.
71M6543F/H and 71M6543G /GH Data Sheet
28 © 2008–2011 Teridian Sem iconduc tor Corpor ation v1.2
The WPULSE and VPULSE pulse generator outputs are available on pins SEG DIO 0/W P ULSE and
SEGDIO1/VPULSE, respectively ( pins 45 and 44). The pulses can also be output on OPT_TX pin 53
(see OPT_TXE[1:0], I/O RAM 0x245 6[ 3:2] f or details).
Figure 9. Puls e Ge ne r a t or FI FO Timing
2.3.7 CE Functional Overview
The ADC pr oc esses one sample per channel per multiplex er c y cl e. Figure 10 shows the t im ing of the
samples taken during one multiplexer cycle with MUX_DIV[3:0] = 7 ( I/O RAM 0x2100[7:4]).
The nu mbe r o f samp les pro cess ed dur ing one ac cu mu lation c yc le is con trolled by the I/O RAM register
SUM_SAMPS[12:0] (0x2107[4:0] and 0x2108[7:0]). The inte gra tion time for each ener gy out pu t is:
SUM_SAMPS[12:0] / 2184.53, where 2184.53 is the sample r ate in Hz
Fo r example, SUM_SAMPS[12:0] = 2184 establi shes 2184 multiplexer cycles per acc um ulation cycle or
2184/2184. 53 = 0.9998 seconds. After an accum ulation cycle is complet ed, t he XFE R_B USY int er r upt
signal s to the MPU that accum ulated data ar e av ailable. The slight dif ference between t he nom inal length
of t he ac c um ulation interval (1000 ms) and the act ual length of 999.8 ms (0.025%) is account ed for in the
CE code and is of no pr actical consequence.
CK32
MUX_DIV Conversions (MUX_DIV=4 is s hown) Settle
ADC MUX Frame
MUX_SYNC 150
WPULSE
S
0
S
1
S
2
S
3
S
4
S
5
CE CODE
RST
W_FIFO
S
0
S
1
S
2
S
3
S
4
S
5
S
0
S
1
S
2
S
3
S
4
S
5
4*PLS_INTERVAL
2. If WPULSE is low longer than (2*PLS_MAXWIDTH+1) updates, WPULSE will be raised until the next
low-going pulse begins.
3. Only the WPULSE circuit is shown. The VARPULSE circuit behaves identically.
4. All dimensions are in CK_FIR cycles (4.92MHz).
5. If PLS_INTERVAL=0, FIFO does not perform delay.
4*PLS_INTERVAL 4*PLS_INTERVAL 4*PLS_INTERVAL 4*PLS_INTERVAL 4*PLS_INTERVAL
1. This example shows how the FIFO distributes 6 pulse generator updates over one MUX frame.
71M6543F/H and 71M6543G /GH Data Sheet
v1.2 © 2008–2011 Teridian Sem iconduc tor Corpor ation 29
Figure 10: Samples from Multiplexer Cycle (Frame)
The end of each multiplexer cycle is signaled to the MPU by the CE_BUSY interrupt. At the end of each
multiplexer cycle, status information, such as sag data and the digitized input signal, is available to the MPU.
Figure 11: Accumulation Interval
Figure 11 shows the accum ulati on interval resul ting from SUM_SAMPS[12:0] = 1819 (I/O RAM 0x2107[4:0]
and 0x2108[7:0]), consisting of 1819 sample s of 45 7.8 µs each, foll owed by the XFE R_B US Y interrupt.
The sam pling in thi s example is appl ied to a 50 Hz si gnal. There i s no corr elati on between the l ine signal
frequenc y and the choice of SUM_SAMPS[12:0]. Furthermore, sampling does not have to start when the
line voltage cro s s es the z ero li ne, and the lengt h of t he accumulatio n interval need not be an inte ger
multiple of the signal cycles.
MUX
STATE
CK32
(32768 Hz)
0 31 2
MUX_DIV = 7 Conversions Settle
Multiplexer Frame (15 x 30.518 µs = 457.8 µs)
SS
IA
VA
IB
30.5 µs
61.04 µs
VB
61.04 µs
IC
VC
4 5 6
61.04 µs 61.04 µs
ID
XFER_BUSY
Interrupt to MPU
20ms
833ms
71M6543F/H and 71M6543G /GH Data Sheet
30 © 2008–2011 Teridian Sem iconduc tor Corpor ation v1.2
2.4 80515 MPU Core
The 71M6543 include an 80515 MPU (8-bit, 8051-compatible) that processes mos t instructions in one clock
cycle. Using a 4.9 MHz clock results in a processing throughput of 4.9 MIPS. The 80515 architecture
eliminates redundant bus states and implements parallel execution of fetch and execution phases. Normally, a
machine cycle is aligned w ith a memory fetch, therefore, most of the 1-byte instructions are performed in a
single machine cycle (MPU clock cyc le). This leads to an 8x average performance improvement (in terms of
MIPS) over the Intel 8051 device running at the same clock frequency.
Table 8 shows the CK M P U frequenc y as a func tion of the MCK clock (19.6608 M Hz ) div ided by the MPU
cl oc k divider MPU_DIV[2:0] ( I/O RAM 0x2200[2:0]). Actual proc essor cl oc k ing speed can be adjusted to the
tot al pr oc essing demand of the applicati on (met er ing calc ulati ons, AMR managem ent, memory
m anagem ent, LCD driver m anagem ent and I/O management) usi ng MPU_DIV[2:0], as shown in Table 8.
Table 8: CKMP U Clock Frequ enci es
MPU_DIV [2:0] CKMPU F requ ency
000
4.9152 MHz
001
2.4576 MHz
010
1.2288 MHz
011 614.4 kHz
100
307.2 kHz
101
110
111
Typica l meas ur e men t and me ter ing fu nc tions b as ed on t he results provided by the inte rna l 32-bit compute
engine ( CE ) ar e av ailable for the MPU as part of the Teridian demonstration code, whic h is provided to
help r educ e the product design c y cl e.
2.4.1 Memor y Organization and Addressing
The 8051 5 M PU core incorporates the Harvard ar c hitecture with separate code and data spaces. Memory
organi z ati on in the 80515 is similar t o that of the industry standard 8051. There ar e three m emory ar eas:
Program memory (Flash, shared by MPU and CE), external RAM (Data RAM, shared by the CE and MPU,
Configuration or I/O RAM), and internal data memory (Internal RAM). Table 9 shows the memory map.
Program Memory
The 80515 can addr es s up to 64 K B of progr am memory space (0x0000 to 0xFFFF). Program memory is
read when the M P U fetches instruc tions or perform s a MOVC operation.
After reset, t he MPU starts program exec ution f r om pr ogram mem or y loc ation 0x0000. The lower part of
the program memory includes reset and interrupt vectors. T h e i nt er ru pt vec to r s ar e s pac e d at 8 -byte
intervals, starting from 0x0003.
MPU External Data Memory (XRAM)
Both inte rna l and exter nal memory is physically loca ted on th e 71M6543 device. The external memory
referred to in this documentation i s onl y exter nal to the 80515 MPU c or e.
5 KB of RAM starting at address 0x0000 is shared by the CE and MP U. The CE normally uses the first
1 KB, l eav ing 4 KB for the MPU. Different ver si ons of the CE code use varying am ounts. Consult the
documentation for the specif ic c ode v er si on being used f or the ex ac t limit.
If the MPU overwrites the CE’s working RA M , the CE’s output may be corrupted. If the CE is dis-
abled, the first 0x40 bytes of RAM are still unusable while MUX_DIV[3:0] ≠ 0 (I/O RAM 0x2100[7:3]),
because t he 71M6543 ADC writ es to these locations. Writing MUX_DIV[3:0] = 0 disables the A DC
output , preventing the CE from writing t he first 0x40 bytes of RAM.
In addition, MUXn_SEL[3:0] val ues must be writt en only after writing MUX_DIV[3:0].
71M6543F/H and 71M6543G /GH Data Sheet
v1.2 © 2008–2011 Teridian Sem iconduc tor Corpor ation 31
The 80515 writes int o exter nal dat a memory when the MPU exec utes a MOV X @Ri,A or MOV X
@DPTR,A instruction. The MPU reads external dat a memory by exec uting a MOVX A,@Ri or MOV X
A,@DPTR instruction (PDATA, SFR 0xBF, prov ides the upper 8 byt es for the MOVX A,@Ri instr uc tion).
Internal and External Memory Map
Table 9 shows the addr es s, type, use and size of the various mem ory com ponents.
Table 9: Memory Map
Address
(hex) Memory
Technology Memory
Type Name Typical Usage Memory Size
(bytes)
0000-FFFF F lash Memory Non-volatile Pro gra m memory
MPU Pr ogr am and
non-v olatil e data
64 KB
CE program
(on 1 KB boundary)
3 KB ma x.
0000-13FF Static RAM Volatile
Ext er nal RA M
(XRAM)
Shared by CE and
MPU
5 KB
2000-27FF Static RAM Volatile
Configuration
RAM (I/O RAM)
Hardware control 2 KB
2800-287F Stati c RAM
Non-volatile
(battery)
Configuration
RAM (I/O RAM)
Battery-buffered
memory
128
0000-00FF
Static RAM
Volatile
Int er nal RAM
Part of 80515 Core
256
MOV X Addressi ng
There ar e two types of instructi ons differing in whether they provide an 8-bit or 16-bit indirect address to
the external dat a RA M.
In t he first type, MOVX A,@Ri, the contents of R0 or R1 in the current register bank pr ov ide the eight
lower-ordered bit s of addr es s. The ei ght high-ordered bit s of the address are specified with the PDATA
SFR. T his met hod allows the user paged acces s (256 pages of 256 bytes each) to all ranges of t he
external data RAM.
In t he second t y pe of MOVX i nstr uc tion, MOV X A,@DPTR, the data pointer generates a 16-bit address.
This form i s faster and m or e eff icient when accessing v er y large dat a arrays (up t o 64 KB), si nc e no
additi onal instr uc tions are needed to set up t he eight high ordered bits of the addres s.
It is possible to mix the t wo MOVX types. This provides the user with four separate dat a pointers, t wo wi th
dir ec t acc ess and two with paged ac c es s, to the entire 64 KB of exter nal m em or y range.
Dual Dat a Poin t er
The Dual Data Pointer ac c eler ates the block m oves of data. The standard DPTR is a 16-bit register that is
used to addre ss external memory or peri pher als. In the 80515 core, the standard dat a pointer is call ed
DPTR, the second data pointer i s called DPTR1. The data pointer select bit, located in the LSB of the DPS
regi ster ( DPS[0], SFR 0x92), chooses the active pointer. DPTR is select ed when DPS[0] = 0 and DPTR1 is
select ed when DPS[0] = 1.
The user switches between pointers by toggling the LSB of the DPS register. The values in the data pointers
are not affected by the LSB of the DPS register. All DPTR related instruc ti ons use the curr ently selected
DPTR f or any activ ity.
The second data point er may not be supported by c er tain compilers.
DPTR1 is useful for copy routines, where it can make the inner loop of the routine two instructions faster
compared to the reloading of DPTR from registers. Any interrupt routine using DPTR1 must save and
restore DPS, DPTR and DPTR1, which increases stack usage and slows down interrupt latency.
By selecting the Evatronics R80515 core in the Keil compiler project settings and by using the compiler
directive “MODC2”, dual data pointers are enabled in certain library routines.
71M6543F/H and 71M6543G /GH Data Sheet
32 © 2008–2011 Teridian Sem iconduc tor Corpor ation v1.2
An al ternative data pointer is available in the form of the PDATA register (S FR 0 x BF), sometimes referred
to as USR2). It d efines the high byte of a 16-bit address when reading or writing XDATA with the instruction
MOVX A,@Ri or MOVX @ Ri,A.
In t ernal Data Memory Map and Access
The I nternal dat a memory pr ov ides 256 byt es (0x00 to 0xFF) of dat a memory. The i nternal data memor y
address is al way s 1 byt e wide. Table 10 shows the i nternal dat a m emory map.
The Spec ial F unc tion Registers ( S FR) oc cup y the upper 128 bytes. The SFR area of internal data memory
is availabl e only by di r ect addr essing. Indirect addr essing of this area accesses the upper 128 byt es of
Int er nal RAM. The lower 128 bytes cont ain working r egisters and bit addr es sabl e mem or y. The low er 32
bytes form four banks of eight regi ster s (R0-R7). Two bits on the program memory status word (PSW, SFR
0xD0 ) select which bank i s in use. T h e nex t 16 bytes f orm a bl o ck of bi t addressable mem ory sp ac e at
addresses 0x00-0x7F. All of the bytes i n the lower 128 bytes are acc es si ble thr ough dir ec t or indirect
addressing.
Table 10: In t ernal Data Memory Map
Address Range Direct Add ressing I nd irect Addressi ng
0x80 0xFF Speci al Functi on Register s (SFRs) RAM
0x30 0x7F Byt e addr essable area
0x20 0x2F Bi t addressable area
0x00 0x1F Register bank s R0…R7
2.4.2 Special Function Registers (SFRs)
A map of the S peci al Function Regi ster s i s shown in Table 11.
Only a few addresses in the SFR memory s pace ar e occupied, the other s are not implemented. A read
access to unimplem ented addresses returns undefined data, while a wr it e access has no effect. SFRs
specific to the 71M6543 ar e sho wn in bold print on a gray fiel d. The registers at 0x80, 0x 88, 0x90, etc.,
are bi t addressabl e, all others are byte addressable.
Table 11: Special Function Register Map
Hex/
Bin
Bit
Addressable
Byte Addressab le Bin/
Hex
X000
X001
X010
X011
X100
X101
X110
X111
F8
INTBITS
VSTAT
RCMD
SPI_CMD
FF
F0
B
F7
E8
IFLAGS
EF
E0 A E7
D8
WDCON
DF
D0
PSW
D7
C8 T2CON CF
C0 IRCON C7
B8 IEN1 IP1 S0RELH S1RELH PDATA BF
B0
P3 FLSHCTL FL_BANK PGADR
B7
A8
IEN0 IP0 S0RELL
AF
A0 P2 DIR2 DIR0 A7
98
S0CON
S0BUF
IEN2
S1CON
S1BUF
S1RELL
EEDATA EECTRL
9F
90
P1 DIR1 DPS ERASE
97
88 TCON TMOD TL0 TL1 TH0 TH1 CKCON 8F
80 P0 SP DPL DPH DPL1 DPH1 PCON 87
71M6543F/H and 71M6543G /GH Data Sheet
v1.2 © 2008–2011 Teridian Sem iconduc tor Corpor ation 33
2.4.3 Generic 80515 Special Function Registers
Table 12 shows the location, description and reset or power-up value of the generic 80515 SFRs. Additional
descripti ons of the registers can be found at the page numbers listed in the table.
Table 12: G eneri c 80515 S FRs - Location and Reset Valu es
Name Address
(Hex) Reset value
(Hex) Description Page(s)
P0 0x80 0xFF Port 0 35
SP
0x81 0x07 Stack Pointer 34
DPL
0x82 0x00 Dat a P ointer Low 0 34
DPH 0x83 0x00 Dat a P ointer High 0 34
DPL1 0x84 0x00 Data P ointer Low 1 34
DPH1 0x85 0x00 Dat a P ointer High 1 34
PCON 0x87 0x00 Power Reduct ion Modes, UART Speed Control 35, 38
TCON
0x88
0x00
Timer /Counter Contr ol
41
TMOD 0x89 0x00 Timer Mode Control 39
TL0
0x8A 0x00 Timer 0, low byte 39
TL1
0x8B 0x00 Timer 1, high byt e 39
TH0 0x8C 0x00 Timer 0, low byte 39
TH1 0x8D 0x00 Timer 1, high byt e 39
CKCON 0x8E 0x01 Cloc k Contr ol ( Str etch=1) 35
P1 0x90 0xFF Port 1 35
DPS
0x92
0x00
Data Pointer selec t Register
31
S0CON 0x98 0x00 Serial Port 0, Contr ol Register 37
S0BUF
0x99 0x00 Serial Port 0, Data Buffer 36
IEN2
0x9A 0x00 Interr upt Enable Register 2 41
S1CON 0x9B 0x00 Ser ial Port 1, Cont r ol Register 38
S1BUF 0x9C 0x00 Serial Port 1, Data Buffer 36
S1RELL 0x9D 0x00 Seria l Port 1, Reload Register, low byte 36
P2 0xA0 0xFF Port 2 35
IEN0
0xA8
0x00
Int er r upt Enable Register 0
41
IP0 0xA9 0x00 I nterrupt Pri or ity Register 0 43
S0RELL
0xAA 0xD9 Serial Port 0, Reload Register, low byte 36
P3
0xB0 0xFF Port 3 35
IEN1 0xB8 0x00 Interrupt Enable Register 1 41
IP1 0xB9 0x00 I nterrupt Pri or ity Register 1 43
S0RELH 0xBA 0x03 Seri al Port 0, Reload Register, high by te 36
S1RELH 0xBB 0x03 Seri al Port 1, Reload Register, high by te 36
PDATA
0xBF
0x00
High addr ess byte for MOVX@Ri - also called USR2
31
IRCON 0xC0 0x00 Int er r upt Request Cont r ol Regi ster 42
T2CON
0xC8 0x00 Polarity f or INT2 and I NT3 42
PSW
0xD0 0x00 Program Status Word 34
WDCON 0xD8 0x00 Baud Rate Control Register (onl y WDCON[7] bit used) 36
A 0xE0 0x00 Accumulator 34
B 0xF0 0x00 B Register 34
71M6543F/H and 71M6543G /GH Data Sheet
34 © 2008–2011 Teridian Sem iconduc tor Corpor ation v1.2
Accumulat or (ACC, A, S FR 0 x E0):
ACC is the accumulator register. Mos t instructions use the accumulator to hold the operand. The mnemonics
for accumulat or -specif ic instruc tions refer to accumulator as A, not ACC.
B Register (SFR 0xF0):
The B register is used during multiply and divide instructions. It c an also be used as a s c r atch-pad register to
hold temporar y data.
Program Status Wo rd (PSW, SFR 0xD0):
This register c ontains vari ous flags and cont r ol bits for the select ion of the r egister bank s (see Table 13).
Table 13: PSW Bit F unc tions (SFR 0xD0)
PSW Bit Symbol Function
7
CV
Carry flag.
6
AC
Auxili ary Carr y flag for BCD operations.
5
F0
General purpose Flag 0 av ailable f or user.
F0 is not to be con fused with the F0 flag in the CESTATUS register.
4
RS1
Register bank sel ec t cont r ol bits. The c ontents of RS1 and RS0 select t he
working register bank :
RS1/RS0 Bank selected Location
00 Bank 0 0x00 – 0x07
01 Bank 1 0x08 – 0x0F
10 Bank 2 0x10 – 0x17
11 Bank 3 0x18 – 0x1F
3
RS0
2
OV
Overflow fl ag.
1
–
User defined flag.
0
P
Parity flag, affected by hardware to indic ate odd or ev en num ber of one bits in
the Ac c um ulator, i.e. even par ity.
Stack Po in t er (SP, SFR 0x81):
The stack point er is a 1-byte register initi aliz ed to 0x07 after r eset. This register is incr em ented before
PUSH and CALL instr uc ti ons, c ausi ng the stack to begin at loc ation 0x08.
Data Po in t er:
The dat a pointers (DPTR and DPRT1) are 2 bytes wide. The lower part is DPL (SFR 0x82) and DPL1 (S FR
0x84), respectively. The highest is DPH (SFR 0x83) and DPH1 (SFR 0x85), respectively. The data point er s
can be l oaded as two regi ster s (e. g. MOV DPL,#data8). They are generally used to ac c ess external code
or data space (e.g. MOV C A,@A+DP TR or MOV X A,@DPTR r espect ively).
Program Counter:
The program counter (PC) is 2 by tes wid e and initialized to 0x0000 after reset. This register is incremented
when fetchi ng oper ation code or when operat ing on data from pr ogr am memor y.
Port Regi st ers:
SEGDIO0 through SEGDIO15 ar e contr olled by Special Function Registers P0, P1, P2, and P3 as shown
in Table 14. Above SEGDIO15, the LCD_SEGDIOn[ ] registers in I/O RAM are used. Since t he dir ec tion
bits are contained in the upper nibble of eac h SFR Pn register and the DIO bits are contained i n the lower
nibble, it is possi ble t o c onfigure t he dir ection of a given DIO pin and set its output value with a si ngle
write operation, thu s facilitating the implementat ion of bit-banged interfaces. W r it i ng a 1 t o a DIO_DIR
bit conf igures the corr espondi ng DIO as an output, whi le wri ting a 0 configur es i t as an input. Writi ng a 1
to a DIO bit causes the corr esponding pin to be at high le vel (V3P 3) , while writing a 0 causes the
c orrespo nding pin t o be held at a low level (G ND) . See 2.5.10 Digital I/ O for additional details.
71M6543F/H and 71M6543G /GH Data Sheet
v1.2 © 2008–2011 Teridian Sem iconduc tor Corpor ation 35
Table 14: Port Regi st ers (SEGDIO0-15)
SFR
Name SFR
Address D7 D6 D5 D4 D3 D2 D1 D0
P0 80 DIO_DIR[3:0] DIO[3:0]
P1 90 DIO_DIR[7:4] DIO[7:4]
P2 A0 DIO_DIR[11:8] DIO[11:8]
P3 B0 DIO_DIR[15:12] DIO[15:11]
All DIO ports on the c hip ar e bi-directional. Each of them consists of a latch (SFR P0 to P3), an output
driver and an input buff er , t her efore the MPU can output or read data through any of these port s. E ven if
a DIO pi n is confi gur ed as an output, the stat e of t he pin can stil l be r ead by the MP U, f or example when
counting pulses i ssued via DIO pins that are under CE control .
At power-up SEGDIO0-15 are c onfigured as inputs. It is necessary to writ e PORT_E = 1 (I/O
R AM 0x27 0C[5]) to enable SEGDIO0-DIO15. The def ault PORT_E = 0 blocks any momentary
output transient pulses that would other wis e oc c ur when SEGDIO0-15 are reset on power-up.
Clo ck S t ret chi ng (CKCON[2:0], SFR 0x8E)
The CKCON[2:0] field defines th e stretch memory cycles th at are used for MOVX instr uctions when
accessing external peripherals. The practical value of this register for the 71M6543 is to guarantee access
to XRAM bet ween CE, M P U, and SPI. T he default set ting of CKCON[2:0] (001) should be c hanged to 000
for best perform anc e.
Table 15 shows how the signal s of the External Mem ory I nterf ace change when str etch values are set
from 0 to 7. The widths of the signal s are counted in MPU clock cycles. The post-reset state of the
CKCON[2:0] field (001), whic h is shown in bold in the table, perf orms the MOVX instr uc tions with a
stretc h value equal to 1.
Table 15: S t ret ch Memory Cycle Width
CKCON[2:0] Stretch
Value Read Signal Width Write Signal Width
memaddr memrd memaddr memwr
000
0
1
1
2
1
001 1 2 2 3 1
010 2 3 3 4 2
011 3 4 4 5 3
100 4 5 5 6 4
101 5 6 6 7 5
110 6 7 7 8 6
111 7 8 8 9 7
2.4.4 Instruction Set
All instr uc tions of the gener ic 8051 microc ontroll er are supported. A complete list of the instructi on set
and of t he associated op-codes is cont ained in t he 71M654x Softw ar e Us er ’s Guide (S UG).
2.4.5 80515 Power Reduction Modes
The 80515 cor e provides two power reduction modes: Idle Mode and Power-Down Mode. These power
saving modes are i nv ok ed by setting the appropriate control bit in the PCON SF R regi ster (SFR 0x87).
Idle Mode halts the MPU while allowing the interrupt, timer, and serial por t f unc tions to continue to
operate. Once Idl e Mode has been entered, an interrupt event autom atically ends Idle M ode. After the
interrupt has been serviced, program executi on c ontinues wit h the instructi on immediately following the
instr uc ti on that set the I dle M ode bit. To ent er Idle Mode, the firmware m ust set the IDL bi t (bit 0) in the
PCON SFR regi ster ( SFR 0x8 7).
71M6543F/H and 71M6543G /GH Data Sheet
36 © 2008–2011 Teridian Sem iconduc tor Corpor ation v1.2
The MP U core power consumpti on c an be significantly reduced by the pr oper use of Idle Mode. The
am ount of power saved depends on the percentage of time spent in Idle Mode. Since some interrupts
may occur frequently, thus endi ng Idle Mode, one m ethod t o m aximize power savings usi ng Idl e Mode, is
to employ a software loop in the main background routine at a point where t he M P U bac k gr ound
processi ng may be permitted to idle. This loop invokes Idle Mode whi le t esting a bit to exit the loop.
Frequentl y occur ri ng interrupts end Idle Mode, but I dle Mode i s immediatel y re-ent er ed when contr ol is
returned t o the idle loop. To exit the idle loop, an inter r upt must oc c ur , and t he associated i nterrupt
service routine must se t the bit that terminates the idle loop execution.
Power-Down Mode halts the MPU and its peripherals. Power-Down Mode is ended by either a hardware
reset or an external interrupt ev ent. To enter Power-Down Mode, the firmw are must set the PD bit (bit 1)
in the PCON SFR register (SFR 0x87).
Table 16. 80515 PCON SFR Regist er ( SFR 0x87)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SMOD
-
-
-
-
-
PD
IDL
Notes:
The SMO D bit is not r elated t o power management.
See 2.4.6 UARTs below for inform ation on the SMOD bit.
2.4.6 UARTs
The 71M6543 include a UART (UART0) that c an be programmed to comm unic ate with a v ari ety of AM R
modules and other ext er nal dev ices. A second UART (UART 1) is connected to the opti c al por t, as
described in the 2.5.9 UART and Opti c al Interface on page 57.
Th e UA RTs ar e dedic at ed 2-wir e s erial interfa ces, wh ich can communic ate with an external host processor
at up t o 38,400 bits/s (wit h MPU cloc k = 1.2288 MHz). The oper ati on of t he RX and TX UART0 pins is as
follows:
• UART0 RX: Serial input data are applied at this pi n. Co nforming to RS-232 standard, the bytes are
input LSB first.
• UART0 TX: Thi s pi n is used to output the seri al data. The bytes are output LS B first.
The 71M6543 has sever al UA RT-related regi ster s for the control and buffering of serial data.
A single SFR register serves as both the t r ansmit buffer and rec eive buffer (S0BUF, SFR 0x 99 for UART0
and S1BUF, SFR 0x 9 C for UART1). When w ritten by the MPU, SxBUF ac ts as the transmit buffer, and
when read by t he M P U, it act s as the receive buffer. Writing data to the transmit buffer start s the
transmi ssion by the associat ed UA RT. Received dat a are availabl e by reading f r om the rec eiv e buffer.
Both UA RTs can simult aneousl y transmit and r ec eiv e data.
WDCON[7] (S FR 0x D8) selec ts whether timer 1 or the internal baud rate generator i s used. All UART
transfers are program mable for p ar ity enabl e, parity, 2 stop bit s/1 stop bi t and XON/XOFF opti ons for
v ar ia ble com m unic ation baud rat es fr om 300 to 38400 bps. Table 17 shows how the baud rates are
calculated. Table 18 shows the selectabl e UA RT operation modes.
Table 17: Baud Rat e Gen erat io n
Using Timer 1
(WDCON[7] = 0) Usin g Int ernal Baud Rate Generat or
(WDCON[7] = 1)
UART0 2
smod
* fCKMPU/ (384 * (256-TH1)) 2
smod
* fCKMPU/(64 * (2
10
-S0REL))
UART1 N/A fCKMPU/(32 * (210-S1REL))
S0REL and S1REL are 10-bit val ues derived by combining bits from the r espect ive timer reload registers.
(S0RELL, S 0RE LH, S1RELL, S1RELH are SFR 0x AA, S FR 0x BA, S FR 0 x9 D and SFR 0 xBB, respectively) SMOD
is the SMOD bit in the SFR PCON register (SF R 0x87 ). TH1 (SFR 0x8D) is the high byte of tim er 1.
71M6543F/H and 71M6543G /GH Data Sheet
v1.2 © 2008–2011 Teridian Sem iconduc tor Corpor ation 37
Table 18: UART Mod es
UART 0 UART 1
Mode 0 N/A Star t bit, 8 data bits, par ity, stop bit, variable
baud rate ( internal baud rat e generator )
Mode 1 Star t bit, 8 data bits, stop bit, variable
baud rate ( internal baud rat e generator
or tim er 1) St ar t bit, 8 data bits, stop bit, variable baud
rate (i nternal baud rate generat or )
Mode 2 Star t bit, 8 data bits, par ity, stop bit,
fixed baud rate 1/ 32 or 1/64 of f
CKMPU
N/A
Mode 3 S ta rt bit , 8 dat a bi t s , p ari t y, stop bit,
variable baud rat e (inter nal baud r ate
generator or timer 1)
N/A
Parity of serial data i s avail able through the P flag of the accumul ator. 7-bit serial modes with
pari ty, such as those used by the F LAG pr otocol, can be si mulated by setting and readi ng bit 7 of
8-bit output data. 7-bit serial m odes without parity can be simulated by setting bit 7 to a c onstant 1.
8-bit serial modes wi th parit y can be sim ulated by setti ng and readi ng the 9th bit , using the contr ol
bits TB80 (S0CON[3]) an d TB81 (S1CON[3]) in the S0CON (SFR 0x98) and S1CON (SFR 0x9B ) regist ers
for transmit and RB81 (S1CON[2]) f or receiv e oper ations.
All support ed oper ati on m odes use over sampli ng for the incoming bit str eam when receiving dat a. Each
bit is sampled thr ee times at the projected middle of the bit durati on. This technique allows for deviations
of t he r ec eiv ed baud r ate from nom inal of up to 3.5%.
The feature of receiving 9 bits (Mode 3 for UART0, Mode A for UART1) can be used as handshake signals
for inter-processor communicati on in m ulti-proce ssor syst ems. I n this case, the slav e processors have bit
SM20 (S0CON[5]) for UART0, or SM21 (S1CON[5] for UART1, set to 1. When the master processor outputs
the slave’s address, it sets the 9th bit to 1, causing a serial port receive interrupt in all the slaves. The sl ave
processors compare the received byte with their address. If there is a match, the addressed slave clears
SM20 or SM21 and receive the rest of the message. The rest of the slaves ignore the message. After
addressing the slave, the host outputs the rest of t he message with t he 9th bit set to 0, so no additional
serial port receive interr upts is generated.
UART Cont rol Regi st ers:
The functions of UART0 and UART1 depend on the sett ing of the Serial Port Control Registers S0CON
and S1CON shown in Table 19 and Table 20, respectively, and t he PCON r egister shown i n Table 21.
Since the TI0, RI0, TI1 and RI1 bits are i n an SFR bit addres sabl e by te, c ommon practice
would be to clear them with a bit operation, but this must be avoided. The hardware implements
bit operati ons as a byte wide read-modify-write hardw are macro. If an interrupt oc c ur s after
the read, but before the write, its fl ag is cleared unintentionally.
The proper way to cl ear these fl ag bits is to wri te a byte mask consisting of all ones except
for a zero in the l oc ation of the bit to be clear ed. The flag bits are confi gur ed in har dware to
ignor e ones writ ten to them.
Table 19: The S0CON (UART0) Regi st er (SFR 0x98)
Bit Symbol Function
S0CON[7]
SM0
The SM0 and SM1 bit s set the UART0 mod e:
Mode
Description
SM0
SM1
0 N/A 0 0
1
8-bit UART
0
1
2 9-bit UART 1 0
3
9-bit UART
1
1
S0CON[6]
SM1
S0CON[5]
SM20
Enables the inter-pro cess or communicat ion fea tur e.
S0CON[4]
REN0
If set, ena bles serial reception. Clea red b y softwa re t o disable recep tion.
71M6543F/H and 71M6543G /GH Data Sheet
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Bit Symbol Function
S0CON[3]
TB80
The 9th transmitted data bit in Modes 2 and 3. Set or cleared by t he MPU ,
dependi ng on the function it performs (parit y check, multiprocessor
c ommunication etc.)
S0CON[2]
RB80
In Modes 2 and 3 it is the 9th data bit received. In Mode 1, SM20 is 0 , RB80 i s the
s top bit . In mode 0, this bit is not used. Must be cleared by s oft w are.
S0CON[1]
TI0
Transmit interrupt flag; set by hardware after completion of a serial transfer. Must
be cleared by software (see Caution above).
S0CON[0]
RI0
Receive interrupt flag; se t by hardware afte r completion of a se rial re ception. Must
be cl eared by soft ware (see Caution above) .
Table 20: The S1CON (UART1) Regi st er (SF R 0x9B)
Bit Symbol Function
S1CON[7]
SM
Sets t he baud rate and mode f or UART1.
SM Mode Description Baud Ra te
0 A 9-bit UART variable
1 B 8-bit UART variable
S1CON[5]
SM21
Enables the inter-pro cess or communicat ion fea tur e.
S1CON[4]
REN1
If set, ena bles serial reception. Clea red b y softwa re t o disable recep tion.
S1CON[3]
TB81
The 9 th t ransm i t ted data bit in Mode A. S et or c leared by the M PU, d epending
on the function it per forms ( parity check, multipr ocessor communication et c.)
S1CON[2]
RB81
In Modes A and B, it is the 9th data bit received. In Mode B, if SM21 is 0, RB81 is
th e stop bit. M ust be cleared by s oft w are
S1CON[1]
TI1
Transmit interrupt flag, set by hardware after completion of a serial transfer. Must
be cl eared by soft ware (see Caution above).
S1CON[0]
RI1
Receive interrupt flag, se t by hardware afte r completion of a se rial re ception. Must
be cl eared by soft ware (see Caution above).
Table 21: PCON Register Bit Description (SFR 0x87)
Bit Symbol Function
PCON[7] SMOD The SMOD bit doubles the baud r ate when set
2.4.7 Timers and Counters
The 8051 5 has two 16-bit timer/coun ter reg isters: Timer 0 and T imer 1. Th es e reg is ters can be con figur ed
for counter or tim er operat ions.
In timer mode, the register is incremented every machine cycle, i.e. it counts up once for every 12 periods of
the MPU clock . In count er mode, the register is i nc r emented when the falling edge is observed at the
corresponding input signal T0 or T1 (T0 and T1 are the timer gating inputs derived from certain DIO pins, see
2.5.10 Digital I/O). Since it takes 2 machine cycles to recognize a 1-to-0 event, the maximum input count rate
is 1/2 of the clock frequency (CKMPU). The re a re no restric t io ns on t he duty cyc le , how ever to ensure proper
recognition of the 0 or 1 state, an input should be stable for at least 1 machine cycle.
Four oper ati ng modes can be select ed for Timer 0 and Timer 1, as shown in Table 22 and Table 23. The
TMOD (SFR 0x89) register , shown in
Table 24, is used to selec t the appropriate mode. The tim er/c ounter operation is controlled by the TCON
(SFR 0x88) register , which is shown in Table 25. Bits TR1 (TCON[6]) and TR0 (TCON[4]) i n the TCON
register start their associat ed timers when set.
71M6543F/H and 71M6543G /GH Data Sheet
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Table 22: Timers/Counters Mode Description
M1 M0 Mode Function
0 0 Mode 0
13-bit Counter /Timer mode with 5 lower bits in the TL0 or TL1 (SFR
0x8A or SFR 0x8B) register and t he remaining 8 bits in the TH0 or TH1
(SFR 0x8C or SFR 0x8D) register (f or Timer 0 and Timer 1, r espect ively ) .
The 3 high order bits of TL0 and TL1 are held at zero.
0 1 Mode 1 16-bit Counter/Tim er mode.
1 0 Mode 2 8-bit aut o-rel oad Counter/Tim er . T he r eload v alue is kept in
TH0
or
TH1, while TL0 or TL1 i s i nc r em ented every machine cycle. When
TL(x) overflow s , a value from TH(x) is copied to TL(x) (where x is 0 for
counter /tim er 0 or 1 for count er /timer 1.
1 1 Mode 3 If Time r 1
M1
and
M0
bits are set to 1, Timer 1 stops.
If Timer 0 M1 and M0 bits are set to 1, Timer 0 acts as two independent
8-bit Timer/Counters.
In Mode 3, TL0 i s affect ed by TR0 and gate control bit s, and sets the TF0 f lag on overflow, whi le TH0
is affect ed by the TR1 bit, and the TF1 fl ag is set on overflow.
Table 23 specifies the com binations of operation m odes al lowed f or Tim er 0 and Tim er 1.
Table 23: Allowe d Tim e r /Counter Mode Combinations
Ti mer 1
Mode 0 Mode 1 Mode 2
Ti mer 0 - mode 0 Yes Yes Yes
Ti mer 0 - mode 1 Yes Yes Yes
Ti mer 0 - mode 2 Not all owed Not all owed Yes
Table 24: TMOD Reg ister Bit Description (SFR 0x89)
Bit Symbol Function
Timer/Counter 1:
TMOD[7]
Gate
If TMOD[7] is set, external input si gnal c ontrol is enable d for Counter 1. The
TR0 bit in the TCON register (SFR 0x88) must also be set in order for Counter 0
to increment. W ith these settings, Counter 0 increments on every falling
edge of the l ogic signal applied to one or more of the SEGDIO 2-11 pins, as
specif ied by the contents of the DIO_R2 through DIO_R11 registers. See
2.5.10 Digital I/O and LCD Segment Driv er s and Table 47.
TMOD[6]
C/T
Selects timer or counter operation. When set to 1, a counter operation is
performed. When cleared to 0, the corresponding register functions as a timer.
TMOD[5:4]
M1:M0
Sel ec ts the mode for Timer/Counter 0 as sho wn in Table 22.
Timer/Counter 0
TMOD[3]
Gate
If TMOD[3] i s set, ex ternal input si gnal c ontrol is enabled for Count er 0. The
TR1 bit in the TCON register (SFR 0x88) must also be set in order for Counter 1
to increment. W ith these settings, Counter 1 inc r em ents on every falling
edge of the l ogic signal applied to one or more of the SEGDIO 2-11 pins, as
specif ied by the contents of the DIO_R2 through DIO_R11 registers. See
2.5.10 Digital I/O and LCD Segment Driv er s and Table 47.
TMOD[2] C/T Sel ec ts timer or count er operat ion. When set to 1, a counter operation is
performed. When clear ed to 0, the c or r esponding register functions as a
timer.
TMOD[1:0]
M1:M0
Sel ec ts the mode for Timer/Counter 1, as shown in Table 22.
71M6543F/H and 71M6543G /GH Data Sheet
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Table 25: The TCON Register Bit Functions (SFR 0x88)
Bit Symbol Function
TCON[7]
TF1
The Timer 1 overflow flag is set by har dware when Tim er 1 overflows.
This flag can be clear ed by sof tware and is automatically clear ed when an
interrupt is processed.
TCON[6]
TR1
Timer 1 run control bit . If cl ear ed, Timer 1 stops.
TCON[5]
TF0
Timer 0 overfl ow f lag set by hardware when Timer 0 overflows. This flag
can be cleared by software and is automatically clear ed when an interr upt
is proces sed.
TCON[4]
TR0
Timer 0 Run control bit. If cl ear ed, T imer 0 stops.
TCON[3]
IE1
Int er r upt 1 edge flag is set by hardware wh en the falling edge on external
pin int1 is obs erved. Cleared when an int er r upt is processed.
TCON[2]
IT1
Int er r upt 1 type control bit . Selects eit her the f alling edge or low level on
input pin to cause an int er rupt.
TCON[1]
IE0
Int er r upt 0 edge flag is set by hardware wh en the falling edge on external
pin int0 is obs erved. Cleared when an int er r upt is processed.
TCON[0]
IT0
Int er r upt 0 type control bit . Selects eit her the f alling edge or low level on
input pin to cause int er r upt.
2.4.8 WD Timer (Software Watchdog Timer)
There is no i nternal soft ware watchdo g tim er. Use the standard hardware watchdog timer instead (see
2.5.13 Hardware Watchdog Timer).
2.4.9 Interrupts
The 80515 provides 11 interrupt sources with four priority levels. Each s ourc e has i ts o wn interrupt request
flag(s) l oc ated in a speci al functi on r egister (TCON, IRCON, and SCON). Each inter r upt requested by the
corresponding flag can be individually enabled or disabled by the enable bits i n IEN0 (SFR 0x A8 ), IEN1
(SFR 0x B8), and IEN2 (SFR 0x9A). Figure 12 shows the device int er r upt struc ture.
Referring to Figure 12, interrupt source s can or iginate from withi n the 80 515 MPU core (refer r ed to as
Internal S our c es) or c an ori ginat e from other par ts of the 71M6543 SoC (referred t o as External S our c es).
There ar e seven ext er nal interrupt sources, as seen i n the lef tmost part of Figure 12, and in Table 26 and
Table 27 (i.e., EX0-EX6).
Interrupt Overview
When an interrupt oc c ur s, the MP U vect ors to the predeterm ined address as shown i n Table 38. Once
the interrupt service has begun, it can be interrupted only by a higher priority interrupt. The interrupt service
is terminated by a retur n from instr uc tion, RETI. When an RETI i s perf ormed, the processor returns to t he
instr uc ti on that would hav e been nex t when the i nterrupt occ ur r ed.
When the i nterrupt conditi on occurs, the processor also indicates this by setting a flag bit. This bit is se t
regardless of whether t he int er r upt is enabled or disabled. Each interrup t flag is sampled once per
m achine c y c le, t hen sampl es are polled by t he har dware. If the sample indicates a pending interrupt when
the inter rup t is enabled, then th e in te rrupt req ues t fla g is s et . On th e ne xt ins t ruct ion cycle, the interrupt is
acknow ledged by hardware forcing an LCALL to the appropriate vector address, if the following conditions
are met:
• No int er r upt of equal or higher pri or ity is alr eady in pr ogress.
• An instr uc tion is current ly being ex ec uted and is not completed.
• T he inst ruct io n in progr ess is not RETI o r any write ac cess to th e r egisters IEN0, IEN1, IEN2, IP0 or IP1.
Special Function Regi st ers f or Int errupt s
The foll owing SFR r egister s cont r ol the interr upt functions:
• The i nterr upt enabl e regi ster s: IEN0, IE N1 and IEN2 (see T able 26, Table 27 and Table 28).
71M6543F/H and 71M6543G /GH Data Sheet
v1.2 © 2008–2011 Teridian Sem iconduc tor Corpor ation 41
• The Tim er/Counter control register s, TCON and T2CON (see Table 29 and Table 30).
• The interrupt r equest register, IRCON (see Table 31).
• The i nterr upt priority registers: IP0 and IP1 (see Table 36).
Table 26: The IEN0 Bit Functions (SFR 0xA8)
Bit Symbol Function
IEN0[7] EAL EAL = 0 disables all interrupts.
IEN0[6]
WDT
Not used for int errupt c ontrol.
IEN0[5] – Not Used.
IEN0[4] ES0 ES0 = 0 disables seri al channel 0 interrupt.
IEN0[3]
ET1
ET1
= 0 disables tim er 1 overflow interrupt .
IEN0[2] EX1 EX1 = 0 disables externa l interrupt 1.
IEN0[1] ET0 ET0 = 0 disables timer 0 overfl ow interrupt.
IEN0[0]
EX0
EX0
= 0 disables external interrupt 0.
Table 27: The IEN1 Bit Functions (SFR 0xB8)
Bit Symbol Function
IEN1[7] – Not used.
IEN1[6] – Not used.
IEN1[5] EX6 EX6 = 0 disables external interrupt 6.
IEN1[4]
EX5
EX5
= 0 disables external interrupt 5.
IEN1[3] EX4 EX4 = 0 disables external interrupt 4.
IEN1[2] EX3 EX3 = 0 disables external interrupt 3.
IEN1[1]
EX2
EX2
= 0 disables external interrupt 2.
IEN1[0] – Not Used.
Table 28: The IEN2 Bit Functions (SFR 0x9A)
Bit Symbol Function
IEN2[0] ES1 ES1 = 0 disables the serial c hannel 1 interrupt .
Table 29: TCON Bit Functions (SFR 0x88)
Bit Symbol Function
TCON[7] TF1 T imer 1 overflow f lag.
TCON[6]
TR1
Not used for int errupt c ontrol.
TCON[5] TF0 T imer 0 overflow f lag.
TCON[4] TR0 Not used f or interrupt control.
TCON[3]
IE1
Ext er nal interrupt 1 flag.
TCON[2] IT1 External interrupt 1 type c ontrol bit :
0 = interrupt on low level.
1 = interrupt on falling edge.
TCON[1] IE0 Ext er nal interrupt 0 flag
TCON[0] IT0 External int er r upt 0 t y pe c ontrol bit :
0 = interrupt on low level.
1 = interrupt on falling edge.
71M6543F/H and 71M6543G /GH Data Sheet
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Table 30: The T2CON Bit Fu nc tions (SF R 0xC8)
Bit Symbol Function
T2CON[7] – Not used.
T2CON[6] I3FR Pol ar ity control for INT3:
0 = falling edge.
1 = ri si ng edge.
T2CON[5] I2FR Pol ar ity control for INT2:
0 = falling edge.
1 = ri si ng edge.
T2CON[4:0] – Not used.
Table 31: The IRCON Bit Functions (SFR 0xC0)
Bit Symbol Function
IRCON[7]
–
Not used
IRCON[6]
–
Not used
IRCON[5] IEX6 1 = Ext er nal interrupt 6 occur r ed and has not been c leared.
IRCON[4] IEX5 1 = Exter nal interrupt 5 occur r ed and has not been c leared.
IRCON[3] IEX4 1 = Ext er nal interrupt 4 occur r ed and has not been c leared.
IRCON[2]
IEX3
1 = Ext er nal interrupt 3 occur r ed and has not been c leared.
IRCON[1] IEX2 1 = Ext er nal interrupt 2 occur r ed and has not been c leared.
IRCON[0] – Not used.
TF0 and TF1 ( Timer 0 and Timer 1 ov erflow flags) is automatically cl ear ed by har dware when the
service routine is call ed (Signals T0ACK and T1ACK – port ISR – ac tive high when the servic e
routine is called).
External MPU Interrupts
The sev en ex ternal int er r upts are the interrupt s ext er nal to the 80515 c or e, i. e. signals that originate in
other par ts of the 71M6543, for exa mple the CE, DIO, RTC, or EEPROM interface .
The external interr upts are connected as shown in Table 32. T he polarity of interrupts 2 and 3 is
pro grammable i n the M PU vi a the I3FR and I2FR bits in T2CON (SFR 0xC8). Int err upts 2 an d 3 shoul d
be programmed for falli ng s en si tivit y ( I3FR = I2FR = 0). The generi c 8051 MPU l iteratur e states t hat
interrupts 4 through 6 are defined as rising-edge sensitive. Thus, the hardware signals attached to
interrupts 5 and 6 are inverted to achieve the edge polarity shown in Table 32.
Table 32: E xt ernal MPU In t errupts
External
Interrupt Connection Polarity Flag Reset
0 Digital I/O see 2.5.10 automatic
1 Digital I/O see 2.5.10 automatic
2 CE_PULSE rising automatic
3 CE_BUSY falling automatic
4 VSTAT (VSTAT[2 :0] changed) rising automatic
5 EE P ROM busy (falling) , SP I (ri si ng) automatic
6 XFER_B US Y (falli ng), RTC_1SEC, RTC_1MI N, RT C_T falling manual
Ext er nal interrupt 0 and 1 can be m apped to pins on the device using DIO resource maps. See 2.5.10
Digital I/O for mo re information.
71M6543F/H and 71M6543G /GH Data Sheet
v1.2 © 2008–2011 Teridian Sem iconduc tor Corpor ation 43
SFR enable bits m ust be set to permit any of these interrupts to occur. Li k ewis e, each interrupt has its own
flag bit, which is set by the interrupt hardware, and rese t by the MPU interrup t handler. XFER_BUSY,
RTC_1SEC, RTC_1MIN, RTC_T, SPI, PLLRISE and PLL FALL have their own enable and f lag bits in
addition to the interru pt 6, 4 and e nable and f lag bits (see Table 33: Interrupt Enable and Flag Bits).
IE0 through IEX6 are cleared automatically when the hardware vectors to the interrupt handler.
The ot her flags, IE_XFER t hr ough IE_VPULSE, are cleared by writing a zero t o them.
Si nc e these bits are in an SFR bit addressable byte, c ommon practice would be t o cl ear them
with a bit oper ation, but t his must be avoided. The hardware i mplem ents bit operat ions as a
byte wide r ead-modify-wr it e har dware macro. If an interrupt occ ur s after the read, but bef or e
the write, its flag is clear ed unintentionally.
The proper way to cl ear the flag bits is to wri te a byte m ask consi sting of all ones ex c ept f or a
zero in the l oc ation of the bit to be clear ed. The flag bits are conf igured in hardware to ignore
ones w ritten to them.
Table 33: Interrupt Enable and Flag Bits
Interrupt Enable Inte r r u pt Flag Int errup t Description
Name Location Name Location
EX0
SFR A8[[0]
IE0
SFR 88[1]
Ext er nal interrupt 0
EX1
SFR A 8[2]
IE1
SFR 88[3]
Ext er nal interrupt 1
EX2
SFR B 8[1]
IEX2
SFR C0[1]
Ext er nal interrupt 2
EX3
SFR B 8[2]
IEX3
SFR C0[2]
Ext er nal interrupt 3
EX4
SFR B 8[3]
IEX4
SFR C0[3]
Ext er nal interrupt 4
EX5
SFR B 8[4]
IEX5
SFR C0[4]
Ext er nal interrupt 5
EX6
SFR B 8[5]
IEX6
SFR C0[5]
Ext er nal interrupt 6
EX_XFER
EX_RTC1S
EX_RTC1M
EX_RTCT
EX_SPI
EX_EEX
EX_XPULSE
EX_YPULSE
EX_WPULSE
EX_VPULSE
2700[0]
2700[1]
2700[2]
2700[4]
2701[7]
2700[7]
2700[6]
2700[5]
2701[6]
2701[5]
IE_XFER
IE_RTC1S
IE_RTC1M
IE_RTCT
IE_SPI
IE_EEX
IE_XPULSE
IE_YPULSE
IE_WPULSE
IE_VPULSE
SFR E 8[0]
SFR E 8[1]
SFR E 8[2]
SFR E 8[4]
SFR F8[7]
SFR E 8[7]
SFR E 8[6]
SFR E 8[5]
SFR F8[4]
SFR F8[3]
XFER_BUSY interrupt (int 6)
RTC_1SEC interrupt (in t 6)
RTC_1MIN interrupt (int 6)
RTC_T i nterrupt (int 6)
SPI interrupt
EEPROM interrupt
CE_Xpulse interrupt (int 2)
CE_Ypulse int er r upt (int 2)
CE_Wpulse interrupt (int 2)
CE_Vpulse int er r upt (int 2)
In t errup t P rio rity Level Stru cture
All interrupt sources are combined in groups, as shown in Table 34.
Table 34: Interrupt Priority Level Groups
Group Grou p M e m bers
0 Ext er nal interrupt 0 Ser ial channel 1 interrupt –
1 Timer 0 interrupt – Ext er nal interrupt 2
2 Ext er nal interrupt 1 – Ext er nal interrupt 3
3 Timer 1 interrupt – Ext er nal interrupt 4
4 Serial channel 0 interrupt – External interrupt 5
5 – – Ext er nal interrupt 6
Each group of inter r upt sources can be program med individually t o one of four prior ity levels (as shown in
Table 35) by setti ng or clearing one bit in the SFR int errupt pr iority register IP0 (SFR 0xA9 ) and one in
71M6543F/H and 71M6543G /GH Data Sheet
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IP1(SFR 0xB9) (Table 36). If requests of the sam e pri orit y lev el ar e r ec eiv ed simultaneously , an inter nal
polling sequence as shown in Table 37 determines which r equest is serviced first.
Changing interrupt priorities while interrupts are enabled can easily cause sof tware defects. It is best
to set the interrupt priority registers only once during initialization before interrupts are enabled.
Table 35: In t errupt Priori t y Level s
IP1[x] IP0[x] Priority Level
0
0
Level 0 (lowest)
0 1 Level 1
1
0
Level 2
1
1
Level 3 (highest)
Table 36: In t errupt Priority Regist ers ( IP0 and IP1)
Register Address Bit 7
(MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
(LSB)
IP0 SFR 0x A9
–
–
IP0[5] IP0[4] IP0[3] IP0[2] IP0[1] IP0[0]
IP1 SFR 0x B9
–
–
IP1[5] IP1[4] IP1[3] IP1[2] IP1[1] IP1[0]
71M6543F/H and 71M6543G /GH Data Sheet
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Table 37: Interrupt Polling Sequence
Ext er nal interrupt 0
Polling sequence
Serial channel 1 interrupt
Timer 0 interrupt
Ext er nal interrupt 2
Ext er nal interrupt 1
Ext er nal interrupt 3
Timer 1 interrupt
Ext er nal interrupt 4
Serial channel 0 interrupt
Ext er nal interrupt 5
Ext er nal interrupt 6
In t errup t Sources and Vectors
Table 38 shows the interrupts wit h their associated flags and v ec tor addresses.
Table 38: In t errupt Vectors
Interrupt
Request Flag Description In t errup t V ector
Address
IE0 Ex ternal i nterr upt 0 0x0003
TF0 Timer 0 interrupt 0x000B
IE1 Ex ternal i nterr upt 1 0x0013
TF1 Timer 1 interrupt 0x001B
RI0/TI0 Serial c hannel 0 interrupt 0x0023
RI1/TI1 Serial c hannel 1 interrupt 0x0083
IEX2 Ext er nal interrupt 2 0x004B
IEX3 External i nterr upt 3 0x0053
IEX4 Ext er nal interrupt 4 0x005B
IEX5 Ext er nal interrupt 5 0x0063
IEX6 Ext er nal interrupt 6 0x006B
71M6543F/H and 71M6543G /GH Data Sheet
46 © 2008–2011 Teridian Semiconduct or Cor por ation v1.2
Figure 12: Interrupt Structure
TCON.1 (IE0 )
Individual
Enable Bits
S1CON.0 (RI1 )
S1CON.1 (TI1 )
Individual Flags
Internal
Source
>=1
TCON.5 (TF0 )
TCON.3 (IE1 )
TCON.7 (TF1 )
S0CON.0 (RI0 )
S0CON.0 (TI0 ) >=1
IRCON.1
(IEX2)
I2FR
IRCON.2
(IEX3)
I3FR
IRCON.3
(IEX4)
IRCON.4
(IEX5)
IRCON.5
(IEX6)
IEN0.7
(EAL)
IP1.0/
IP0.0
IP1.1/
IP0.1
IP1.2/
IP0.2
IP1.3/
IP0.3
IP1.4/
IP0.4
IP1.5/
IP0.5
Interrupt
Flags Priority
Assignment
Interrupt
Vector
Polling Sequence
Interrupt Enable
Logic and Polarity
Selection
DIO
Timer 0
DIO
Timer 1
CE_BUSY
UART0
EEPROM
XFER_BUSY
RTC_1S EX_RTC1S
VSTAT
RTC_T EX_RTCT
XPULSE
External
Source
DIO_Rn
DIO_Rn
SPI
>=1
EX_VPULSE
VPULSE
>=1
IEN2.0
(ES1)
IEN0.1
(ET0)
IEN0.0
(EX0)
IEN1.1
(EX2)
IEN0.2
(EX1)
IEN1.2
(EX3)
IEN0.3
(ET1)
IEN1.3
(EX4)
IEN0.4
(ES0)
IEN1.4
(EX5)
IEN1.5
(EX6)
IE_XFER
IE_RTC1S
IE_RTCT
EX_XFER
>=1
EX_EEX
EX_SPI
IE_EEX
IE_SPI
IT0
IE_XPULSE
IE_VPULSE
EX_XPULSE
RTC_1M EX_RTC1M IE_RTC1M
UART1
(optical)
0
2
1
3
4
5
6
No.
Flag=1
means that
an interrupt
has occurred
and has not
been cleared
EX0 – EX6 are cleared
automaticallywhen the
hardware vectors to the
interrupt handler
byte received
byte transmitted
overflow occurred
overflow occurred
byte received
byte transmitted
accumulation
cycle completed
alarm clock
Supply status changed
CE completed code run and
has new status information
DIO status
changed
DIO status
changed
CE detected sag
every second
every minute
BUSY fell
command
received
WPULSE
YPULSE
EX_WPULSE
EX_YPULSE IE_YPULSE
IE_WPULSE
CE detected zero
crossing
Wh pulse
VARh pulse
3/19/2010
71M6543F/H and 71M6543G /GH Data Sheet
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2.5 On-Chip Resources
2.5.1 Physical Memory
2.5.1.1 Flash Memory
The device includes 64 KB (71M6543F/ H) or 128 KB (71M6543G/GH) of on-chip flash me mory. The
flash m em or y primarily contains MPU and CE program code. It also cont ains images of the CE RAM and
I/ O RAM. On power-up, bef or e enabling t he CE, the MPU copies these images to t heir r espect ive
locations.
Flash space allocated for the CE program i s limit ed to 4096 16-bit words (8 KB). The CE program m ust
begin on a 1-K B boundary of the flash address space. The CE_LCTN[6/5:0] (I/O RAM 0x 2109[5:0]) f ield
on the 71M6543F/H and the CE_LCTN[6:0] (I/O RA M 0x 2109[ 6:0]) field on the 71M6543G/G H define
which 1-KB boundar y c ontai ns the CE code. Thus, t he first CE instr uc tion is located at
1024*CE_LCTN[6/5:0] on the 71M6543F /H and at 1024*CE_LCTN[6:0] on the 71M6543G/GH.
Flash m em or y can be acc essed by the MP U, t he CE, and by the S PI interface (R/W ).
Table 39: Fl ash Memory Access
Access by Access
Type Condition
MPU R/W/E W/E only if CE is di sabl ed.
CE R
SPI R/W/E Ac c ess only when SFM is i nvoked (MPU halted).
Flash Write Procedures
If the FLSH_UNLOCK[3:0] (I/O RAM 0x2702[7:4] ) key i s correctl y pr ogr ammed, the MP U may write t o the
flash m em or y . Thi s is one of the non-v olatile storage options avail able to the user in addi tion to exter nal
EEPROM.
The flash program w rite enable bit, FLSH_PSTWR (SF R 0xB2[0 ]), differentiates 80515 data store instructions
(MO V X@ DPTR,A) between Flash and XRAM writ es. This bit i s autom atically clear ed by har dware after
each byt e wri te operati on. Write oper ations to this bi t are inhibited when interrupts are enabled.
If the CE is enabl ed ( CE_E = 1, I/O RAM 0x2106[0]), flash writ e oper ations must not be att em pted unless
FLSH_PSTWR is set. Thi s bi t enables the “posted f lash writ e” c apability . FLSH_PSTWR has no effect when
CE_E = 0 ). When CE_E = 1, however, FLSH_PSTWR delays a fl ash writ e until the time interval between
the CE c ode passes. During thi s del ay tim e, t he FLSH_PEND (SFR 0xB2[3]) bit is high, and the MPU
continues to exec ute commands. When the CE code pass ends (CE_BUS Y fall s), the FLSH_PEND bit
falls and th e write op erati on occur s. T he MPU can query the FLSH_PEND bit to determine when the
wri te operatio n has be en completed. While FLSH_PEND = 1, furt her flash write requests are ignored.
Updating Indiv idual Bytes i n Flash Memory
The original stat e of a fl ash byt e is 0xF F (all bits are 1). Once a value other than 0xFF is written to a flash
memo r y cell, ove r wri ti ng with a dif ferent value usually requi r es that the c ell be er ased fir st. Since cells
cannot be er ased i ndividually, t he page has to be first copi ed to RAM, foll owed by a page erase. After
this, the page can be updated in RAM and then written back to t he flash memory.
Flash Erase Procedures
Flash eras ur e is in it iated by wr it ing a spe c ific da ta patte r n to spe c ific S FR reg is ters in the pro per seq uence .
Th ese s pecial pattern/sequence requirements prevent inadvertent erasure of the flash memory.
The mass erase sequence is:
• Write 1 to the FLSH_MEEN bit (SF R 0xB2[1]).
• Write the pattern 0 xAA to the FLSH_ERASE (SFR 0x 94) register.
The mass erase cyc le can only be i nitiated when the I CE port is enabl ed.
71M6543F/H and 71M6543G /GH Data Sheet
48 © 2008–2011 Teridian Semiconduct or Cor por ation v1.2
The page erase sequence is:
• W rite the page addres s to FLSH_PGADR[5:0] (S FR 0x B7 [7 :2]).
• Write the pattern 0x55 to the FLSH_ERASE register (SFR 0x94).
Bank-Switching in the 71M6543G/GH
The 128 K B program memory in the 71M6543G /G H consists of a f ixed lower bank of 32 K B, addr essable
at 0x0000 to 0x7FFF plus an upper banked area of 32 KB, addressable at 0x8000 to 0xFFFF . T he I/O
RAM register FL_BANK[1: 0] (SFR 0xB6[1:0]) is used to switc h four memory banks of 32 KB each into the
address range from 0x 8000 to 0xFFFF . Not e that when F L _BANK [1:0] (SFR 0xB6[1: 0]) = 0, the upper
bank i s the same as the lower bank.
Table 40: B a nk Switch in g with FL_BANK[1:0] (SFR 0xB6[1:0])in the 71M6543G/GH
71M6543G/GH
FL_BANK[1:0]
Add ress Range f or Lowe r
Bank (0x0000-0x7FFF)
Add ress Range f or Upper
Bank (0x8000-0xFFFF)
00
0x0000-0x7FFF
0x0000-0x7FFF
01
0x0000-0x7FFF
0x8000-0xFFFF
10
0x0000-0x7FFF
0x10000-0x17FFF
11
0x0000-0x7FFF
0x18000-0x1FFFF
In t he 71M 6543G/GH, the address that the FLSH_PGADR[6:0] (SFR 0xB7[7:1]) points to in the program
address space can r eference different flash memor y locations, dependi ng on the setting of t he
FL_BANK[1:0] (SFR 0xB6[1:0]) bits. T he CE_LCTN[6:0] (I/O RAM 0x2109[6 :0]) field on the 71M6543G/GH
on the ot her hand, points dir ectly to a locati on in the flash memor y ar e not affec ted by the FL_BANK[1:0]
(SFR 0xB6[1:0]) bits
Program Securit y
When e nabl ed, the sec urity featu r e lim it s the ICE to global flash erase oper ations onl y . All oth er ICE
operations , su ch as reading via the S PI or ICE port, are bloc ked . Th is guaran tees th e se cu r ity of the use r’s
MPU and CE pr ogr am code. Security is enabled by MPU code that i s executed in a 64 CKMPU cycle
pre-boot int erval befor e the prim ar y boot sequence beg ins. Once security is enabled, the only way to
disabl e it is to perf orm a global erase of the flash, followed by a c hip reset.
The first 60 c ycles of the M P U boot code ar e called the pre-boot phase because during this phase t he
ICE is i nhibit ed. A read-onl y status bi t, PREBOOT (SFR 0xB2[7]), i dentif ies these cycles to the MPU.
Upon completion of pre-boot, the I CE can be enabled and is permitt ed to t ak e contr ol of t he MPU.
The security enable bit , SECURE (S FR 0xB2[ 6]), is reset whenever the chip is reset. Hardware associated
with the bit allows on ly ones to be wr it ten to it. Thus , pre-boot code ma y set SECURE to enable the security
feature but m ay not reset i t. Once SECURE i s set, the pre-boot and CE c ode ar e pr otected fr om erasure,
and no ex ternal read of progr am c ode is possi ble.
Specif ically , when the SECURE bit is set, the following a pplies:
• The ICE i s limit ed to bulk flash erase only.
• Page zero of flash m em or y, the preferred location for the user’s pre-boot c ode, may not be
page-era sed by either MPU or ICE. Page z er o may only be erased with gl obal fl ash erase.
• Write operations t o page z er o, whet her by M P U or ICE are inhibited.
The 71M6543 also includes hardware to protect against unintentional Flash write and erase. To enable flash
wri te and era se op erat ions, a 4-bit hardware key that must be written to the FLSH_UNLOCK[3:0] field. The
key is the binary number ‘0010’. If FLSH_UNLOCK[3:0] i s not ‘0010’, the Fla sh erase an d wr it e operation is
inhibited by hardware. Proper operation of this security key requires that there be no firmware function that
writes ‘0010’ to FLSH_UNLOCK[3:0]. The key should be written by the external SPI master, in the case of
SPI flas h programming (SFM mode), or through the ICE interface in the case of ICE flash programming.
When a boot loader is used, the key should be sent to the boot load code which then writes it to
71M6543F/H and 71M6543G /GH Data Sheet
v1.2 © 2008–2011 Teridian Sem iconduc tor Corpor ation 49
FLSH_UNLOCK[3:0]. FLSH_UNLOCK[3:0] is not automatically reset. It should be cleared when the SPI or
ICE has finished changing the Flash. Table 41 summarizes the I/O RAM registers used for flash security.
Table 41: Fl ash Security
Name Location Rst Wk Dir Description
FLSH_UNLOCK[3:0] 2702[7:4] 0 0 R/W Must be a 2 to enable any flash modification.
See the descripti on of Fl ash securi ty for
m or e details.
SECURE SFR B 2[6] 0 0 R/W Inhibits erasure of page 0 and flash addresses
abov e the beginni ng of CE code as defi ned
by CE_LCTN[6/5:0](I/O RAM 0x2109[5:0]) on
the 71M6543F/H and CE_LCTN[6:0] I/O
RAM 0x2109[6:0]) on the 71M6543G/GH.
Al so i nhibits the read of flash via the ICE
and SPI por ts.
SPI Flash Mode
In norm al oper ati on, the SPI slave interface cannot r ead or writ e the fl ash memory. However, the
71M6543 cont ains a Special Flash Mode (SFM) that facilitates initial (production) progr amming of the
flash m em or y . When the 71M6543 is in SFM mode, the SPI interface can erase, read, and write the
flash. Other memory elem ents such as XRAM and I/O RAM ar e not acc essible to the SPI in this mode.
In order to protec t the flash con ten ts , sev eral operations are required before the SFM mode is successfully
invoked.
When the 71M6543G/G H is operat ing SFM, SPI singl e-byte t r ansact ions are used to write to
FL_BANK[1:0] (SFR 0xB6[1:0]). Duri ng an S PI si ngle-by te tr ansact ion, SPI_CMD[1:0] will ov er-write the
contents of FL_BA NK[1:0] (SFR 0xB6[1:0] ). This will all ow for ac c ess of the entire 128 KB f lash memory
while oper ati ng in SFM.
Detail s on the SFM can be found in 2.5.12 SPI Sla ve Port.
2.5.1.2 MPU/CE RAM
The 71M6543 includes 5 KB of stat ic RAM m em or y on-chip (XRAM) plus 256 byt es of internal RAM in the
M P U core. The 5 K B of static RAM are used for data stor age by bot h MP U an d CE and for the
communication bet ween MPU and CE.
2.5.1.3 I/O RAM (Configuration RAM)
The I/O RAM can be seen as a seri es of hardware registers that cont r ol basic hardware f unc tions. I/O
RAM address space star ts at 0x2000. The registers of the I /O RAM are listed in Table 69.
The 71M6543 includes 128 byt es non-vol atile RAM memory on-chi p in the I/O RAM address space
(addresse s 0x2800 to 0x 287F). This memor y section is supported by the volt age applied at VBAT_RTC,
and the dat a in it are preserved in BRN, LCD, and SLP modes as l ong as the voltage at VBAT_RTC i s
within specificati on.
2.5.2 Oscillator
The 71M6543 oscillator drives a standard 32.768 kHz wat ch c rystal . This type of crystal is ac curate and
does not requi r e a high-cur r ent osci llat or circ uit . The oscill ator has been designed specific ally to handle
watch cr y stals and is compatible with their hi gh im pedance and limited power handl ing capability. The
oscillator power dissipation is very low to maximize the lifetime of any battery attached to VBAT_RTC.
Osci llat or calibrati on can improve the accuracy of bot h the RTC and met eri ng. Ref er to 2.5.4, Real-Time
Clock (RTC) for more information.
The o scillat or is powered fr om the V 3P3SYS pin or from the VBAT_ RTC pin, de pending o n th e V3OK
internal bit (i.e., V3OK = 1 if V3P 3SYS ≥ 2.8 V DC and V3OK = 0 if V 3P 3S Y S < 2.8 VDC). The oscillator
requi r es approximately 100 nA, which is negligible compared t o the inter nal leak age of a battery.
71M6543F/H and 71M6543G /GH Data Sheet
50 © 2008–2011 Teridian Semiconduct or Cor por ation v1.2
Al though the oscillator may appear to work when VBA T is not connect ed, t his mode of oper ation is not re-
commended.
If VBAT_RTC i s connected to a drai ned batt er y or disconnected, a battery test that sets
TEMP_BAT may drain the supply c onnec ted to VBAT_RTC and cause the osci llator to stop. A
stopped oscill ator may forc e the devic e to reset. Therefor e, an unexpec ted reset during a battery
test should be int er pr eted as a battery f ailur e.
2.5.3 PLL and Internal Clocks
Timing for the device is derived f r om the 32.768 kHz crystal oscill ator output that is multipli ed by a PLL by
600 to obtain 19.660800 MHz, the master clock (MCK). All on-chip timi ng, except for the RTC cloc k, is
derived from MCK. Table 42 prov ides a summary of the cl oc k functions and thei r cont r ols.
The t wo general -pur pose count er /timers cont ained in the MPU are controlled by CKMPU (see 2.4.7
Timers and Counters).
The master cl oc k c an be boosted to 19. 66 M Hz by setting the PLL_FAST bit = 1 (I/O RAM 0x22 00[4]) and
can be reduced to 6.29 MHz by PLL_FAST = 0. The MPU clock frequency CK M P U is determined by
another divider contr olled by the I/O RAM control field MPU_DIV[2:0] (I/O RAM 0x220 0[2:0]) and can be
set to M CK*2-(MPU_DIV+2) where MPU_DIV[2:0] m ay var y fr om 0 to 4. When the ICE_E pin is high, the
circuit also generat es the 9.83 MHz clock for use by the emulator.
The PLL is onl y turned off in SLP mode or in LCD mode when LCD_BSTE is disabled. The LCD_BSTE
v alue depends on the setti ng of the LCD_VMODE [1:0 ] field (see Table 52).
When the part is waking up f r om SLP or LCD modes, the PLL is turned on in 6.29 MHz mode, and the
PLL frequency is not be accurat e unti l the PLL_OK (SFR 0xF9[4]) flag rises. Due to potential overshoot, the
MPU should not change t he v alue of PLL_FAST until PLL_OK is true.
71M6543F/H and 71M6543G /GH Data Sheet
v1.2 © 2008–2011 Teridian Sem iconduc tor Corpor ation 51
Table 42: Clo ck S yst em Summary
Clock Derived
From Fixed Frequency or Range Function
PLL_FAST=1 PLL_FAST=0 Contr olled by
OSC Crystal 32.768 kHz – Cry stal cloc k
MCK Crystal/PLL 19.660800 MHz
(600*CK32) 6. 291456 M Hz
(192*CK32) PLL_FAST Master clock
CKCE MCK 4.9152 MHz 1.5728 MHz – CE clock
CKADC MCK 4.9152 MHz ,
2.4576 MHz 1.572864 MHz,
0.786432 MHz ADC_DIV ADC clock
CKMPU MCK 4. 9152 M Hz …
307.2 kHz 1.572864 MHz…
98.304 kHz MPU_DIV[2:0] MPU cl ock
CKICE MCK 9.8304 MHz…
614.4 kHz
3.145728 MHz …
196.608 kHz MPU_DIV[2:0] ICE cl oc k
CKOPTMOD MCK 38.40 k Hz 38.6 kHz – Optical
UART
Modulation
CK32 MCK 32.768 kHz – 32 kHz cl oc k
2.5.4 Real-Time Clock (RTC)
2.5.4.1 RTC G eneral Description
The RT C is driven directly by the c rystal oscillator and is po wered by either the V3P3SYS pin or the
VBAT _ RTC pi n, depending on the V3OK i nternal bit. The RTC consists of a counter chain and output
registers. The cou n ter cha in co ns is ts of regis ters for se c onds , minu tes , hours, day of week, day of month,
month, and year . The cha in reg is ters are supp or ted by a shad ow reg ister that facilitates read and writ e
operations.
Table 43 shows the I/O RA M registers for accessing the RT C.
2.5.4.2 Accessing the RTC
Two bits, RTC_RD (I/O RAM 0x 2890[ 6]) and R T C_WR (I/ O RAM 0x 2890[ 7]), c ontrol the behavior of the
shado w regi ster .
When RTC_RD i s l ow, t he shadow register is updated by the RT C aft er eac h two milliseconds. When
RTC_RD is high, this update is halted and the shadow register contents become stationary and are suitable
to be read by the MP U. Thus, when the MPU wishes to r ead the RTC, it freezes the shado w regi ster by
setting the RTC_RD bit, reads the shadow register , and then lowers the RTC_RD bit to let updates to t he
shado w regi ster r esume. Since t he RTC cloc k i s only 500 Hz, t her e may be a delay of approx im ately
2 ms from when the RTC_RD bit is lowered unti l the shadow regi ster r ec eives i ts fi r st update. Reads t o
RTC_RD continues to retur n a one until the first shado w update occurs.
When RTC_WR is hi gh, the update of the shadow regi ster is also i nhibited. During this time, the MPU may
overwrite the contents of the shadow register. When RTC_WR is low ered , the sha dow reg is ter is written into
the RTC coun te r on the next 500Hz RTC clock . A ‘change’ bit is inc luded for each word in th e sh adow
regi ster to ensure that only pr ogr ammed words are updated when the MP U wri tes a zero to RTC_WR.
Reads of RTC_WR returns one until the counter has actual ly been updated by t he r egister .
The sub-second register of the RTC, RTC_SBSC (I/O RAM 0x2892), c an be read by t he MPU after the one
second int er r upt and befor e r eac hing the next one second boundary. RTC_SBSC contains the count since
the last full se cond, in 1/128 second nom inal clock periods, until the nex t one-second boundary. When the
RST_SUBSEC bit is written, the SUBSEC coun te r is res tart ed, counting from 0 to 127. Reading and resetting
the sub-second counter can be used a s part of an algorithm to accurately set t he RTC.
The RT C is capable of processing l eap y ear s. E ac h counter has i ts own output r egister. T he RTC chain
registers are not be affected by the reset pin, watchdog timer resets, or by transi tions between the batt er y
modes and mis s ion mode.
71M6543F/H and 71M6543G /GH Data Sheet
52 © 2008–2011 Teridian Semiconduct or Cor por ation v1.2
Table 43: RTC Cont rol Regi st ers
Name Location Rst Wk Dir Description
RTCA_ADJ[6:0] 2504[6:0] 40 -- R/W Register for analog RTC frequency adjustment.
RTC_P[16:14]
RTC_P[13:6]
RTC_P[5:0]
289B[2:0]
289C[7:0]
289D[7:2]
4
0
0
4
0
0
R/W Register s for digital RTC adjustment.
0x0FFBF ≤ RTC_P ≤ 0x10040
RTC_Q[1:0] 289D[1:0] 0 0 R/W Register for digital RTC adjustment.
RTC_RD 2890[6] 0 0 R/W
Freez es the RTC shadow regi ster so i t i s suit able for
MPU reads. When RTC_RD is read , it returns the
status of the shadow register: 0 = up to date, 1 =
frozen.
Writing 0 to RTC_RD bit to enable shadow register
update, and writing 1 to RTC_RD to dis able update
RTC_WR 2890[7] 0 0 R/W
Freez es the RTC shadow regi ster so i t i s suit able for
MPU write operations. When RTC_WR is cleared, the
contents of the shadow register are written to the RTC
counter on the next RTC cl ock (~1 kHz). When
RTC_WR is read, it returns 1 as long as RTC_WR is
set, and continues t o r eturn one until the RT C counter
is updated.
Writing 0 to RTC_ WR bit to enable copying the shadow
register contents to RTC counter, and w riting 1 to
RTC_WR to dis able copying
RTC_FAIL 2890[4] 0 0 R/W Indicates that a count err or has occurred in the RTC
and that the time is not tr ustworthy . Thi s bi t can be
cl ear ed by wri ting a 0.
RTC_SBSC[7:0] 2892[7:0] R Time remaini ng since the last 1 second boundary.
LSB = 1/128 second.
2.5.4.3 RT C Rate Control
The 71M6543 has two rat e adjustment mechanisms:
• The first rate adjustment me chanism i s an anal og rate adjustment, usi ng the I/O RAM register
RTCA_ADJ[6:0], that trims the cr y stal load capacitance.
• The second rate adjustment mechanism is a digital rate adjust that affects the way the clock frequency
is proces sed i n the RTC.
Setting RTCA_ADJ[6:0] to 00 min imizes th e load cap ac it ance , ma xim iz ing the oscillator freq uency. Setting
RTCA_ADJ[6:0] to 0x7F maximizes the load capacitance, minimizing the oscillator frequency. The adjusta b le
capacitance is approximately:
pF
ADJRTCA
C
ADJ
5.16
128
_⋅=
The precise amount of adju stment depends on the crystal proper ties, the PCB lay out and the value of the
externa l cr ysta l cap ac itors (see CXS and CX S in Table 89). Th e adjus tmen t may occur at any ti me, and t he
resulting clock frequ enc y should be measured over a one-second interval .
The second rat e adjustment is digit al, and can be used to adjust the clock rat e up to ±988ppm, wit h a
resolut ion of 3.8 ppm. T he rate adjustment is impleme nted starting at the n ext secon d-boundary
following the adjustment. S ince the LSB (de fine first) results i n an adjustment every four seconds, t he
frequenc y shoul d be m easured over an interval that is a mult iple of four seconds.
The cloc k r ate is adjusted by wri ti ng the appropr iat e values to RTC_P[16:0] (I/O RAM 0x289B[2:0], 0x 289C,
0x289D[7:2]) and RTC_Q[1:0] ( I/O RAM 0x289D[1:0 ]). Updates to RTC rate adjust regi ster s, RTC_P and
RTC_Q, are done thr ough the shadow regi ster described above. The new values are loaded into the
counter s when RTC_WR (I/O RAM 0x2890[7]) is lowered.
71M6543F/H and 71M6543G /GH Data Sheet
v1.2 © 2008–2011 Teridian Sem iconduc tor Corpor ation 53
The def ault frequency is 32,768 RT CLK cycl es per second. T o shift t he cl oc k fr equenc y by ∆ ppm,
RTC_P and RTC_Q are calculated using t he following equation:
+
⋅∆+
⋅
=+⋅ −5.0
101 832768
RTC_QRTC_P4 6
floor
Conv er sel y , the amount of ppm shift f or a giv en val ue of 4RTC_P+RTC_Q is:
6
101
4832768
)( ⋅
−
+⋅
⋅
=∆
QP RTCRTC
ppm
For ex am ple, for a shift of -988 ppm, 4 ⋅ RTC_P + RTC_Q = 262403 = 0x40103. RTC_P[16:0] = 0x 10040,
(I/O RAM 0x289B[2:0] , 0x289C, 0x289D[7:2]) and RTC_Q[1:0] = 0x03 (I/O RAM 0x289D[1:0]. The default
values of RTC_P[16:0] and RTC_Q[1:0], corresponding to zero adjustment, are 0x10000 and 0x0, respectively.
Two settings f or the TMUX2OUT test pin, PULSE_1S and PULSE_4S , are available for measuri ng and
cal ibrating the RTC cl oc k frequenc y . These are waveform s of approximately 25% duty cycl e with 1s or 4s
period.
Defaul t values for RTCA_ADJ[6:0], RTC_P[16:0] and RTC_Q[1:0] should be nomi nal values, at
the center of t he ad justm ent range. Un-calibrated extreme val ues (zer o, for ex am ple) c an cause
inc or r ec t operati on.
If the cr y stal temperature coeffi ci ent is known, the MPU can integrate tem per ature and c or r ec t t he RTC
time as necessary. Alt er natively, t he c har ac teristics can be l oaded into an NV RAM and the OSC_COMP
(I/O RAM 0x28A0[5]) bit m ay be set. In thi s case, the oscillator is adjusted aut om atically, even in SLP
m ode. See 2.5.4.4 RTC Temper ature Com pensation for det ails.
2.5.4.4 RTC Temperature Compensatio n
The 71M6543 can be c onfigured t o r egular ly measure die temperature, including in SLP and LCD modes
and while th e M PU is halte d. If enabl ed by OSC_COMP, this temperature i nform ati on is automatically
used to cor re c t for the temp era tu re varia tion of the crystal. A table lookup method is used.
Table 44 sho ws I/ O RAM registers i nvolved in autom atic RTC temperat ur e compensation.
Table 44: I/ O RAM Regi st ers f or RT C Temp erature Comp ensation
Name Location Rst Wk Dir Description
OSC_COMP 28A0[5] 0 0 R/W Enables the autom atic updat e of RTC_P[16:0] and
RTC_Q[1:0] every tim e the t em per ature is measured.
STEMP[10:3]
STEMP[2:0] 2881[7:0]
2882[7:5] – – R The result of the temperature measurement (10-bits
of magnitude data plus a sign bit).
LKPADDR[6:0] 2887[6:0] 0 0 R/W The address for reading and w riting the RTC lookup
RAM.
LKPAUTOI 2887[7] 0 0 R/W
Auto-incr em ent fl ag. When set, LKPADDR[6:0] auto
increments every time LKP_RD or LKP_WR is pul sed.
The incremented addr ess can be read at
LKPADDR[6:0].
LKPDAT[7:0] 2888[7:0] 0 0 R/W T he data for reading and writing the RT C look up
RAM.
LKP_RD
LKP_WR 2889[1]
2889[0] 0
0 0
0 R/W
R/W
Str obe bits for the RTC look up RA M read and write.
When set, the LKPADDR[6:0] and LKPDAT registers
are used in a read or write operation. When a strobe is
set, it stays set until the oper ation complet es, at which
time the strobe is cleared and LKPADDR[6:0] is
incremented if LKPAUTOI is se t.
Referring to Figure 13 the tabl e lo okup method uses the 10-bi ts plu s sign -bit value i n STEMP[10:0]
right-shi f t ed by t wo bit s to obtain an 8-bit plu s sign val ue ( i.e. , NV RA M Address = STEMP[10:0]/4). A
71M6543F/H and 71M6543G /GH Data Sheet
54 © 2008–2011 Teridian Semiconduct or Cor por ation v1.2
limit er ensures that the r esulting look-up ad dr e ss i s in the 6-bi t pl us si gn ra ng e of -64 to +63 ( decimal ) .
The 8-bit NV RAM c ontent pointe d to by the addres s is add ed as a 2’ s com plement val ue to 0x400 00,
the nomi nal value of 4*RTC_P[16:0] + RTC_Q[1:0].
Refer to 2.5.4.3 RTC Rate Control for in formation on t he rate adjustments performed by registers
RTC_P[16:0] and RTC_Q[1:0]. The 8 -bit values loaded in t o NV RAM must be scaled c orrectly to produce
rate adjustments that ar e consistent with the equati ons given in 2.5.4.3 RTC Rate Control for RTC_P[16:0]
and RTC_Q[1:0]. Note t hat t he sum of the look ed-up 8-bit 2’s complement value and 0x 40000 form a 19-
bit value, which i s equal to 4*RTC_P[16:0] + RTC_Q[1:0], as sho wn in Figure 13. The output of the
Temper ature Compensation is automatic ally loaded into the RTC_P[16:0] and RTC_Q[1:0] l oc ations af ter
each l ook -up and summati on oper ation.
Σ
0x40000
19
10+S
STEMP >>2
63
-64
-64 63 255-256
LIMIT Look Up
RAM
ADDR
6+S
8+S Q7+S 4*RTC_P+RTC_Q
19
Figure 13: Automatic Temperature Compensati on
The 128 NV RAM locations are organi z ed in 2’s complement f ormat. As mentioned above, the
STEMP[10:0] digit al temperature val ues are sc aled s uch t hat the correspon ding NV RA M addresses are
equal to STEMP[10:0]/4 (limited in the range of -64 t o + 63) . See 2.5.5 71M6543 Tem per ature Sensor on
page 55 for the equations to calculate temperature in degrees °C from the STEMP[10:0] reading.
For pr oper oper ation, the MPU has to l oad the lookup table with v alues that reflec t t he crystal proper ties
with respect to tem per ature, which is typic ally done once duri ng initi aliz ation. S ince the lookup table is
not directly addr essable, the MP U uses the following procedure to l oad the NV RAM tabl e:
1. Set the LKPAUTOI bit (I/ O RAM 0x2887[7]) to enable address auto-increment.
2. Write z er o into t he I/O RAM register LKPADDR[6:0] (I/ O RAM 0x2887[6:0]).
3. Write the 8-bit datum into I/O RAM regi ster LKPDAT (I /O RAM 0x2888).
4. Set the LKP_WR bit (I /O RAM 0x2889[0]) to write the 8-bi t dat um into NV_RAM
5. Wait for LKP_WR to cl ear (LKP_WR auto-clears when the data has been copied to NV RAM).
6. Repeat steps 3 thr ough 5 unti l all dat a has been wr itten to NV RAM.
The NV RAM table can also be read by writi ng a 1 into the LKP_RD bit (I/O RAM 0x2889[1]). The pr oc ess
of reading from and writing to the NV RAM is accelerated by setting the LKPAUTOI bit (I/O RAM 0x2887[7]).
When LKPAUTOI is set, LKPADDR[6:0] (I/ O RAM 0x2887[6:0] ) auto-increments every time LKP_RD or
LKP_WR is pulsed. It is al so possi ble t o perform random ac c ess of the NV RAM by wr iting a 0 to the
LKPAUTOI bit and loading the desi r ed addr ess int o LKPADDR[6:0].
If the oscillator temperature compensation feature is not being used, it is possible to use the NV
RAM storage ar ea as ordinary battery-backed NV storage space using the procedur e described
abov e to read and wri te NV RAM data. In t his case, the OSC_COMP bit (I/ O RAM 0x28A0[5]) is
reset to disable the autom atic oscillator temperature compensation feature.
2.5.4.5 RT C Interru pts
The RT C gener ates interrupts each second and each mi nute. These i nterrupt s are called RTC_1SEC
and RTC_1MIN. In addition, the RTC functions as an al arm clock by generati ng an interrupt when the
minutes and hours registers both equal their res pec tive targe t coun ts as defined in . The alarm clock
interrupt is called RTC_T. All three inter rup ts appe ar in t he M PU’s extern a l inte rrupt 6. See Table 33 in the
interrupt section f or the enable bits and flags for these interrupts.
The minut e and hour target registers are listed in Table 45.
71M6543F/H and 71M6543G /GH Data Sheet
v1.2 © 2008–2011 Teridian Sem iconduc tor Corpor ation 55
Table 45: I/ O RAM Regi st ers f or RT C Interru pts
Name Location Rst Wk Dir Description
RTC_TMIN[5:0] 289E[5:0] 0 0 R/W The target minut es register. See bel ow.
RTC_THR[4:0] 289F[4:0] 0 0 R/W The targe t hours reg ister . The RTC_T interr upt occurs
when RTC_MIN[5:0] becomes equal to RTC_TMIN[5:0]
and RTC_HR[4:0] becomes equal to RTC_THR[4:0].
2.5.5 71M6543 Temperature Sensor
The 71M6543 includes an on-chip tempe r ature s ensor for d eter mining the temp erature of its bandgap
reference. Th e pr im ar y us e of the t em pe r at ur e d at a is t o det e rm i ne t h e m a gni t ud e of com p en sa tion
req ui red to offset the thermal drift in the s ystem for the compensation of current, voltage and energy
measurement and the RTC. See 4.5 Metrology Tempe r ature Compensation on page 89. Also see 2.5.4.4
RTC T em per ature Com pensation on page 53.
Unlike ea r lier generation Teridi an SoC s, the 71M6543 doe s not use t he ADC to rea d th e tem perature
sensor. Inst ead, it uses a technique t hat is operational in SLP and LCD mode, as well as BRN and MSN
modes. This means that the temperature sensor c an be used to c ompensate f or the f r equenc y v ari ation
of the c rystal, even in SLP mode whil e the MP U is halted. See 2.5.4.4 RTC Temperature Com pensation
on page 53.
In MS N and BRN modes, t he temperature sensor is awakened on com mand from the MP U by setti ng the
TEMP_START (I/O R AM 0x28B4[6]) c ontrol bit . In SLP and LCD m odes, it is awakened at a r egular r ate
set by TEMP_PER[2:0] (I/O RAM 0x28 A0 [2:0 ]).
The resul t of the temperature measurement is read from the two I/O RAM locations STEMP[10:3] (I/O
RAM 0x2881) and STEMP[2:0] (I/O RAM 0x2882[7:5]). Note that both of these I/O RAM l oc ations must be
read and properly c om bined to form the STEMP[10:0] 11-bit value (see STEMP in Table 46). The resulting
11-bit value is in 2’s complement f orm and ranges from -1024 to +1023 (decimal).
The equat ions below are used to calculate the sensed tem per ature. The first equat ion applies when t he
71M6543F and 71M 6543G are in MSN mode and TEMP_PWR = 1. The second equation appli es when the
71M6543F and 71M 6543G are in BRN mode, and i n this case, t he TEMP_PWR and TEMP_BSEL bits m ust
both be set to the same value, so that the battery that supplies the tem per ature sensor is al so the batter y
that is measured and reported i n BSENSE. Thus, the second equat ion requires readi ng STEMP and
BSENSE. In the second equati on, BSENSE (the sensed bat tery v oltage) is used to obtai n a more acc ur ate
temper ature reading when the IC is i n BRN mode. A second set of equat ions if provided for the
71M6543H and 71M6543G H high prec ision par ts. T he coeffici ents provided i n the vari ous STEMP
equations below are typical.
For the 71M6543F and 71M6543G i n M S N Mode (with TEMP_PWR = 1):
22325.0)( +⋅=° STEMPCTemp
For the 71M6543F and 71M6543G in BRN Mode, (with TEMP_PWR=TEMP_BSEL):
4.64609.000218.0325.0)( 2+⋅−⋅+⋅= BSENSEBSENSESTEMPCTemp o
For the 71M6543H and 71M6543GH in BRN m ode (with TEMP_PWR=TEMP_BSEL):
If STEMP ≤ 0:
()= 0.325 + 0.00218 0.609 +64.4
If STEMP > 0:
()=63 
_85 + 0.00218 0.609  +64.4
71M6543F/H and 71M6543G /GH Data Sheet
56 © 2008–2011 Teridian Semiconduct or Cor por ation v1.2
Table 46 shows the I/O RA M registers used for temperature and battery measurement.
If TEMP_PWR selects VBAT_RTC when the battery is nearly discharged, the temperature
measurement may not finish. In this case, firmware may complete the measurement by selecting
V3P3D (TEMP_PWR = 1).
Table 46: I/ O RAM Regi st ers f or T emperature and Battery Measurement
Name Location Rst Wk Dir Description
TBYTE_BUSY 28A0[3] 0 0 R
Indicat es that hardware i s sti ll writing the 0x28A0
byte. Additi onal wri tes to this byt e are locked out
while it is one. Write duration could be as long as 6 ms.
TEMP_PER[2:0] 28A0[2:0] 0 – R/W
Sets the period between temperature measurements.
Automatic m easurement s can be enabled in any
m ode (MSN, BRN, LCD, or SLP).
TEMP_PER
Time
0
Manual updates (see TEMP_START)
1-6 2 ^ (3+TEMP_PER) (seconds)
7
Continuous
TEMP_BAT 28A0[4] 0 – R/W
Causes VBAT to be measured whenever a
temper ature measurement i s perf ormed.
TEMP_START 28B4[6] 0 – R/W
TEMP_PER[2:0] must be zero in order for TEMP_START
to fu ncti on. I f TEMP_PER[2:0] = 0, then setti ng
TEMP_START starts a temperature m easurement .
Ignored in SLP and LCD modes. Hardware clears
TEMP_START when the t em per ature measurement i s
complete.
TEMP_PWR 28A0[6] 0 – R/W
Sel ec ts the power source for the temperature sensor:
1 = V3P3D, 0 = VBAT_RTC. Thi s bi t is ignor ed in
SLP and LCD modes, where the temperature sensor is
always powered by V B A T_RTC.
TEMP_BSEL 28A0[7] 0 – R/W
Sel ec ts whic h batter y is monitored by the
temperature sensor: 1 = VBA T, 0 = VBAT_RTC
TEMP_TEST[1:0] 2500[1:0] 0 – R/W
Test bits for the temperature monitor VCO.
TEMP_TEST must be 00 in regul ar oper ation. Any
other value causes the V CO to run conti nuousl y with
the control voltage descri bed below.
TEMP_TEST Function
00 Normal operati on
01 Reserved for factory test
1X Reserved for factory test
STEMP[10:3]
STEMP[2:0]
2881[7:0]
2882[7:5]
R
R
The resul t of the temperature measurement.
The STEMP[10:0] value may be obt ained in C with a
singl e 16-bit read and divide by 32 operation as
follows:
vo latile int16_t xdata STEMP _at_0x2881;
fa = (float)(ST EMP/32);
BSENSE[7:0]
2885[7:0]
–
–
R
The resul t of the batter y measurem ent.
BCURR 2704[3] 0 0 R/W
Connects a 100 µA load to the battery sel ec ted by
TEMP_BSEL.
2.5.6 71M 6xx3 Tem per at ure Sen s o r
71M6543F/H and 71M6543G /GH Data Sheet
v1.2 © 2008–2011 Teridian Sem iconduc tor Corpor ation 57
The 71M6xx3 includes an on-chip tem perature s en s or for d eterm ining the temp erature of its bandgap
reference. Th e pr im ar y us e of the t em pe r at ur e d at a is t o det e rm i ne t h e m a gni t ud e of com p en sa tion
req ui red to offset the thermal drift in the s ystem fo r the compensation of the current measurement
performed by the71M6xx3. See the 71M6xxx Data Sheet for the equation to calculate temperature from the
71M6xx3 STEMP[10:0] reading. Also, see 4.5 Met rology Temperatur e Compensation on page 89.
See 2.2.8.3 Control of the 71M6xx 3 Isolated Sensor on page 22 for inf ormation on how to read the
STEMP[10:0] information from the 71M6xx3 .
2.5.7 71M6543 Battery Monitor
The 71M6543 temperature measurement circ uit can also monitor the batt er ies at the VBAT and
VBAT_RTC pins. The batt ery t o be tested (i.e., VBAT or VBAT_RTC pin) is selected by TEMP_BSEL (I/O
R AM 0x28A 0[7] ).
When TEMP_BAT (I/O RAM 0x28A0[4]) is set, a bat ter y measurement is perfor med as part of each
temperature measurement. The value of the battery reading is stored in register BSENSE[7:0] (I/O RAM
0x2885). The following equa t ions are used to calculate the voltage measured on the VBAT pin (or
VBAT_RTC pin) from the BSENSE[7:0] and STEMP[10:0] va lues. The resu lt of t he equation below is in volts .
A slightly d ifferent equat ion is us ed for MS N mo de and B RN mode , as follow s .
In MSN mode, TEMP_PWR = 1 use:
VSTEMPVBSENSEVRTCorVBATVBAT 000297.00246.0)142(3.3)_( ⋅+⋅−+=
In BRN mode, TEMP_PWR = TEMP_BSEL use:
VSTEMPVBSENSEVRTCorVBATVBAT 000328.00255.0)142(291.3)_( ⋅+⋅−+=
In MSN mode, a 100 µA de-passivation load can be applied to the selected battery (i.e., selected by the
TEMP_BSEL bit) by setting the BCURR (I/O RAM 0x2704[3]) bit. Battery impedance can be measured by
taking a bat te r y m easurement wi th and with out BCURR. Regardless of the BCURR bit setting, the battery
load is never applied in BRN, LCD, and SLP modes.
2.5.8 71M 6xx3 VCC M o nitor
The 71M6xx3 monitors its VCC p in voltage. The voltage of the VCC pin can be obtained by the 71M 6543
by issuing a read command to the 71M6xx3. The 71M6 543 must request both the VSENSE[7:0] and
STEMP[10:0] values from the 71M6xx3. See the 71M6xxx Data Sheet for the equation to calculate the
71M6xx3 VCC pin voltage from the VSENSE[7:0] and STEMP[10:0] values read from the 71M6xx3.
See 2.2.8.3 Control of the 71M6xx 3 Isolated Sensor on page 22 for informati on on how to read
VSENSE[7:0] and STEMP[10:0] from the 71M6xx3 remote sensors.
2.5.9 UART and Optical Interface
The 71M6543 pr ov ides two asynchr onous interfaces, UART0 and UA RT1. Bot h c an be used to conn ec t
to AMR mo du les , user int er faces , et c ., and also sup por t a me chan is m for prog ra m ming the on-chip flash
memory .
Referring to Figure 14, UART1 includes an interf ace to im plem ent an IR/optic al por t. The pin OPT _TX is
designed to direc tly driv e an exter nal LE D for transmitting data on an optical link. The pi n OPT_RX has
the sam e threshold as the RX pin, but can also be used t o s en s e th e inp ut from an external photo detec tor
used as the rec e iver for the optical link. OPT_TX and OPT_RX are connect ed to a dedicated UART port
(UART1).
The O PT_TX and OPT_RX pins can be inverted with configur ation bits OPT_TXINV (I/O RAM 0x2456[0] )
and OPT_RXINV (I/O RAM 0x2457[1] ), r espect ively. Additionally, t he OPT_T X output may be modulated at
38 kHz. Modul ation is available in MSN and BRN modes (see Table 62). The OPT_TXMOD bit (I/O RAM
0x2456[1]) enables modulati on. The duty cycle is cont rol led by OPT_FDC[1:0] (I/O RAM 0x2457[5:4] ) ,
which can selec t 50%, 25%, 12. 5%, and 6.25% duty cycle. A 6.25% dut y cycl e m eans that OPT_TX is
low for 6.25% of the period.
When not needed for UART1, OPT_TX can alt er natively be configur ed as SEGDIO51. Configuration is
via the OPT_TXE[1:0] (I/O RAM 0x 2456[3:2]) field and LCD_MAP[51] (I/O RA M 0x24 05[0]). The
71M6543F/H and 71M6543G /GH Data Sheet
58 © 2008–2011 Teridian Semiconduct or Cor por ation v1.2
OPT_TXE[1:0] field allows the MPU to selec t VPULSE, WPULSE, SEGDIO 51 or the out put of the pulse
m odulator to be sourced onto the OPT_TX pin. Likewise, the OPT_RX pin can alternately be c onfigured
as SEGDIO55, and its control is OPT_RXDIS (I/O RAM 0x2457[2] ) and LCD_MAP[55] (I/O RAM 0x2405[4]).
B
A
OPT_TXMOD = 0 OPT_TXMOD = 1,
OPT_FDC = 2 (25%)
B
A
1/38kHz
OPT_TXINV
from
OPT_TX UART MOD
EN DUTY
OPT_TX
OPT_TXMOD
OPT_FDC
OPT_TXE[1:0]
1
2
V3P3
Internal
AB0
2
3
DIO2
WPULSE
VARPULSE
Figure 14: Optical Interface
Bit Bang ed Opt ical UART (T hird UART)
As shown in Figure 15, t he 71M6543 c an also be conf igur ed to drive the optical UA RT wit h a DIO signal
in a bit banged confi gur ation. When control bit OPT_BB (I/O RAM 0x2022[0]) i s set, the optic al port is
driven by DIO5 and the SEGDIO 5 pin is driven by UART1_TX. Thi s confi gur ation is typically used when
the t wo dedic ated UART s must be connec ted to hi gh speed cli ents and a sl ower optical UART is
permiss ible.
OPT_TXINV
UART1_TX MOD
EN DUTY
SEGDIO51/
OPT_TX
OPT_TXMOD
OPT_FDC
OPT_TXE[1:0]
0
2
V3P3
Internal
A B
OPT_TXMOD=0 OPT_TXMOD=1,
OPT_FDC=2 (25%)
B
A
1/38kHz
1
2
3
DIO51
WPULSE
VARPULSE SEG51
LCD_MAP[51]
1
0
SEGDIO55/
OPT_RX
SEG55
LCD_MAP[55]
1
0
DIO55
1
0
OPT_RXDIS
UART1_RX
DIO5
SEGDIO5/TX2
SEG5
1
0
LCD_MAP[5]
OPT_BB
0
0
1
1
Figure 15: Opti cal Int erf ace ( UART1)
2.5.10 Digital I/O and LCD Segment Driver s
2.5.10.1 General Information
The 71M 6543 c om bines most DIO pins wi th LCD segment driver s. Each SEG/DIO pin c an be c onfigured
as a DIO pin or as a segment driver pi n (SEG).
On reset or power-up, all DIO pins are DI O input s (except for SEGDIO0-15, see caution not e below) until
they ar e c onfigured as desired under M P U c ontrol. The pin function can be confi gur ed by the I/O RAM
registers LCD_MAPn (0x2405 – 0x240B). Setti ng the bit corr espondi ng to the pin in LCD_MAPn to 1
configures the pin for LCD, setting LCD_MAPn t o 0 configures it for DIO.
71M6543F/H and 71M6543G /GH Data Sheet
v1.2 © 2008–2011 Teridian Sem iconduc tor Corpor ation 59
After reset or power up, pi ns SEGDIO0 through SE GDIO15 are initially DIO outputs, but ar e
disabl ed by PORT_E = 0 ( I/O RAM 0x270C[5 ]) to avoi d unwa nted pulse s during reset. After
configuring pins SEGDIO0 t hr ough S EGDIO 15 the MPU must enable these pins by sett ing
PORT_E.
Once a pin is conf igured as DIO, it can be c onfigured independentl y as an i nput or output. For SEGDIO0
to SEGDIO15, thi s i s done with the SFR registers P0 (SFR 0x80), P1 (SFR 0x90), P2 (SFR 0xA0) and P3
(SFR 0x B0), as shown in Table 48.
Example: SEGDIO12 ( pin 32 in Table 48) is configur ed as a DIO output pin with a v alue of 1 (high) by
wri ti ng 0 to bit 4 of LCD_MAP[15:8], and writin g 1 to bot h P3[4]and P3[0]. The same pi n is configured
as an LCD driver by writi ng 1 to bit 4 of LCD_MAP[15:8]. The di spl ay information is writt en to bits 0 to 5
of LCD_SEG12.
The PB pin is a dedi c ated digital input and is not part of the SEGDIO system.
The CE features pulse counting registers and each pulse counter int er r upt output is int er nally
routed to the pulse i nterrupt logic. T hus, no r outing of pulse signal s to ex ternal pins is requir ed in
order t o gener ate pul se i nterr upts. See int er r upt source No. 2 in Figure 12.
A 3-bit confi gur ation word, I/O RAM register DIO_Rn (I/O RA M 0x2009[2:0] through 0x200E[6:4]) can be
used for pins SEGDIO2 through SEGDIO11 (when configured as DIO) and PB to indiv idually assign an
internal resource such as an interrupt or a timer control (DIO_RPB[2:0], I/O RAM 0x2450[2:0] , configures
the PB pin) . Thi s way, DIO pins can be trac ked even if they ar e configured as outputs. Table 48 lists the
internal resources which can be assigned using DIO_R2[2:0] through DIO_R11[2:0] and DIO_RPB[2:0]. If
more than one input is conne c ted to the sa me res our ce , the resources are co mb ined us ing a logica l O R .
Table 47: S electable Resources using the DIO_Rn[2:0] Bits
Value in DIO_Rn[2:0]
Resou rce S elected fo r SEGDIOn or PB Pin
0
None
1
Reserved
2
T0 ( c ounter0 cloc k )
3
T1 (c ounter1 cloc k )
4
High priority I/O interrupt (IN T0)
5
Low priority I/O interrupt (IN T1)
Note:
Resources are selec tabl e only on SEGDIO 2 through SEG DIO 11 and the
PB pin. See Table 49.
When driving LE Ds, r elay coil s etc ., the DIO pins should sink the current into GNDD (as
shown in Figure 16, right), not source it from V3P3D (as shown in Figure 16, left). This is due
to t he r esi stanc e of the i nternal swi tch t hat connects V3P3D t o either V3P3SYS or VBAT. See
6.4.6 V3P3D Switch on page 139.
S ourcing curren t in or out of DIO pins othe r than tho s e dedicate d for wa ke functions , for
examp le with pullup or pulldown resi stors, must be av oided. Violating this rul e leads to
inc r eased qui escent c ur r ent i n sleep and LCD modes.
71M6543F/H and 71M6543G /GH Data Sheet
60 © 2008–2011 Teridian Semiconduct or Cor por ation v1.2
Figure 16: Connecting an External Load to DIO Pins
2.5.10.2 Combined DIO and SEG Pins
A total of 51 combined DIO/LCD pins are avail able. These pins can be categorized as follows:
39 combined DIO/ LCD segment pi ns:
o SEG DIO 4… SEG DIO 25 ( 22 pins)
o SEG DIO 28… S EGDIO 35 ( 8 pins)
o SEG DIO 40… S EGDIO 45 ( 6 pins)
o SEG DIO 52… S EGDIO 54 ( 3 pins)
12 combined DIO/ LCD segment pi ns shared with other functions:
o SEG DIO 0/W P ULS E, SEG DIO 1/VP ULS E ( 2 pins)
o SEGDIO2/SDCK, SEGDIO3/SDATA (2 pins)
o SEG DIO 26/COM5, SEGDIO 27/CO M 4 (2 pins)
o SEGDIO36/SPI_CSZ…SEGDIO39/SPI_CKI (4 pins)
o SEG DIO 51/O P T_TX, SEGDIO55/OPT_RX (2 pi ns)
Additionally, 5 LCD segment (SEG) pins are availabl e. These pins can be categorized as foll ows:
o 3 SEG pins combined with the ICE int erfac e ( SEG 48/E_RXTX, S E G49/E _TCLK,
SEG50/E_RST)
o 2 SEG pins combined with the test multi plexer outputs (SEG46/TMUX2OUT ,
SEG47/TMUXOUT)
Thus, a t otal of 51 DIO pins are avail able with minimum LCD confi gur ation, and a t otal of 56 LCD pins are
av ailable wit h mi nim um DIO configurati on.
Table 48: Dat a/Directio n Regist ers and Intern al Reso urces for SEGDIO0 to SEGDIO 15
SEGDIO 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Pin # 45 44 43 42 41 39 38 37 36 35 34 33 32 31 30 29
Configuration:
0 = DIO, 1 = LCD 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
LCD_MAP[7:0] (I/O RAM 0x240B) LCD_MAP[15:8] (I /O RAM 0x 240 A)
SEG Data Regi ster 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
LCD_SEG0[5:0] to LCD_SEG15[5:0] (I/O RA M 0x2410[5:0] to 0x241F[5:0]
DIO Data Register
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
P0 (SFR80) P1 (SFR 0x90) P2 (SFR 0xA0) P3 (SFR 0xB0)
Dir ec tion Register:
0 = input, 1 = output 4 5 6 7 4 5 6 7 4 5 6 7 4 5 6 7
P0 (SFR 0x80) P1 (SFR 0x90) P2 (SFR 0xA0) P3 (SFR 0xB0)
V3P3SYS
VBAT
V3P3D
DIO
GNDD
MISSION
BROWNOUT
LCD/SLEEP
LOW
HIGH
HIGH-Z
V3P3SYS
VBAT
V3P3D
DIO
GNDD
MISSION
BROWNOUT
LCD/SLEEP
LOW
HIGH
HIGH-Z
Not recommended Recommended
71M6543F/H and 71M6543G /GH Data Sheet
v1.2 © 2008–2011 Teridian Sem iconduc tor Corpor ation 61
SEGDIO 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Pin # 45 44 43 42 41 39 38 37 36 35 34 33 32 31 30 29
Int er nal Resources
Configurable
(see Table 47) – – Y Y Y Y Y Y Y Y Y Y – – – –
The configurat ion for pins SEGDIO16 to SEGDIO31 is sh own in Table 49, and the confi gur ation for pi ns
SEGDIO32 to SEGDIO45 is shown in Table 50. The configur ation for pi ns SEGDIO51 to SEGDIO55 is
shown in Table 51.
Table 49: Dat a/Directio n Regist ers f or SEGDIO16 to SEGDIO31
SEGDIO 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Pin # 28 27 25 24 23 22 21 20 19 18 17 16 11 10 9 8
Configuration:
0 = DIO, 1 = LC D 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
LCD_MAP[23:16] (I/O RAM 0x2409) LCD_MAP[31:24] (I/O RA M 0x2408)
SEG Data Reg is ter 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
LCD_SEGDIO16[5:0] to LCD_SEGDIO31[5:0]
(I/O RA M 0x 2420[ 5 :0 ] to 0x242F[5:0])
DIO Data R egister 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
LCD_SEGDIO16[0] to LCD_SEGDIO31[0]
(I/O RA M 0x 2420[ 0 ] to 0x242F[0])
Direct ion R egister:
0 = input, 1 = output
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
LCD_SEGDIO16[1] to LCD_SEGDIO31[1]
(I/O RA M 0x 2420[ 1 ] to 0x242F[1])
Table 50: Dat a/Directio n Regist ers f or SEGDIO32 to SEG DIO 45
SEGDIO 32 33 34 35 36 37 38 39 40 41 42 43 44 45
Pin # 7 6 5 4 3 2 1 100 99 98 97 96 95 94
Configuration:
0 = DIO, 1 = LC D
0 1 2 3 4 5 6 7 0 1 2 3 4 5
LCD_MAP[39:32]
(I/O RA M 0x 2407) LCD_MAP[45:40]
(I/O RA M 0x 2406[ 5 :0 ])
SEG Data Reg is ter 32 33 34 35 36 37 38 39 40 41 42 43 44 45
LCD_SEGDIO32[5:0]
to
LCD_SEGDIO45[5:0]
(I/O RAM 0x2430[5:0] to 0x243D[5:0])
DIO Data R egister 32 33 34 35 36 37 38 39 40 41 42 43 44 45
LCD_SEGDIO32[0] to LCD_SEGDIO45[0]
(I/O RA M 0x 2430[ 0 ] to 0x24 3D[ 0 ])
Direct ion R egister:
0 = input, 1 = output
32 33 34 35 36 37 38 39 40 41 42 43 44 45
LCD_SEGDIO32[1] to LCD_SEGDIO45[1]
(I/O RA M 0x 2430[ 1 ] to 0x24 3D[ 1 ])
Table 51: Dat a/Directio n Regist ers f or SEGDIO51 to SEG DIO 55
SEGDIO 51 52 53 54 55
Pin # 53 52 51 47 46 – – –
Configuration:
0 = DIO, 1 = LC D
3 4 5 6 7 – – –
LCD_MAP[55:48]
(I/O RA M 0x 2405)
SEG Data Reg is ter 51 52 53 54 55 – – –
71M6543F/H and 71M6543G /GH Data Sheet
62 © 2008–2011 Teridian Semiconduct or Cor por ation v1.2
LCD_SEGDIO51[5:0] to LCD_SEGDIO55[5:0]
(I/O RA M 0x 2443[ 5 :0 ] to 0x 2447[5:0])
DIO Data R egister 51 52 53 54 55 – – –
LCD_SEGDIO51[0] to LCD_SEGDIO55[0]
(I/O RAM 0x 2443[ 0 ] to 0x24 47[0])
Direct ion R egister:
0 = input, 1 = output
51 52 53 54 55 – – –
LCD_SEGDIO51[1]
to
LCD_SEGDIO55[1]
(I/O RA M 0x 2443[ 1 ] to 0x24 47[ 1 ])
2.5.10.3 L CD Drivers
The LCD drivers are grouped i nto up to six commons (COM0 – COM5) and up to 56 segment drivers.
The LCD interfac e is flexi ble and can driv e 7-segment digits, 14-segment digit s or enunciat or symbols.
A volt age doubler and a contr ast DA C gener ate VLCD from either V BAT or V3P 3S YS, depending on the
V3P3SYS voltage. The voltage doubler, while capable of driving into a 500 kΩ load, is able to generat e a
m aximum LCD v oltage that is wi thin 1 V of twice the supply voltage. The doubler and DAC operate fro m
a trimmed low-power referenc e.
The configur ati on of the VLCD generati on is contr olled by the I/O RAM field LCD_VMODE[1:0] (I/ O RAM
0x2401[7:6]). It is decoded into LCD_E XT, LDAC_E, and LCD_BSTE. Table 52 details the
LCD_VMODE[1:0] configurations.
71M6543F/H and 71M6543G /GH Data Sheet
v1.2 © 2008–2011 Teridian Sem iconduc tor Corpor ation 63
Table 52: LCD_VMODE Configurations
LCD_VMODE[1:0]
LCD_EXT
LDAC_E
LCD_BSTE
Description
11 1 0 0 Ext er nal V LCD c onnec ted to the VLCD pin.
10 0 1 1
LCD boost is enabl ed. Maxim um VLCD voltage is
2*V3P3L-1.
VLCD = max(2*V3P3L-1, 2.65(1+LCD_DAC[4:0]/31)
01 0 1 0 LCD boost is dis abled. The maxi mum V LC D
voltage is V3P3L.
VLCD = max(V3P3L, 2.65(1+LCD_DAC[4:0]/31)
00 0 0 0
VLCD=V3P3L, the LCD DAC and LCD boost are dis-
abled. In LCD mode, this setting causes the lowest
batt er y c ur r ent.
Notes:
1. LC D _E XT, L DA C_E an d LC D_B S TE a r e 71 M6 5 43 i nt er n al si gn als wh ic h ar e d ec o d ed f rom
the LCD_VMODE[1:0] c ontrol fiel d setting (I/O RAM 0x2401[7:6]). Each of these decoded signals,
when asserted, has the effect indicat ed in the descri ption column abov e, and as summarized
below. L C D_E X T : Whe n set , t h e VL CD pi n ex p e ct s a n external su ppl y volt a g e
LDAC_E : When set , LC D DA C i s ena bled
LCD_BSTE : When set, the LCD boost circuit is enabled
2. V3P3L is an inte rnal supply rail that is supplied from either the VBAT pin or the V3P3SYS pin,
de p e ndi n g on t h e V3 P 3SY S pin volta ge . When t h e V3 P 3S YS pin dr o p s belo w 3. 0 V DC, th e
71M6543 swi tches to BRN mode a nd V3 P 3L is sourced fr om the VBAT pin, oth erwise V 3P3L
is source d from th e V3P 3SY S pin whi le in MSN mo de.
When using the VLCD boost circuit, use care when setting the LCD_DAC[4:0] (I/O RAM 0x240D[4:0 ])
v alue to ensure that the LCD m anufacturer’s recom mended operating voltage specific ation i s not
exceeded.
The voltage doubl er is active in all LCD modes incl uding the LCD mode when LCD_BSTE = 1. Current
dissipat ion in LCD mode can be r educ ed if t he boost ci rcuit is disabled and the LCD system is operated
directly from VBAT.
The LCD DAC uses a low-power refer enc e and, within the constraints of VBAT and the voltage doubler,
generates a VLCD voltage of 2.65 VDC + 2.65 * LCD_DAC[4:0]/31. Two fuse bytes inc r ease the ac c ur ac y
of t he LCD_DA C. LCDADJ 12 and LCDA DJ 0 indic ate the act ual VLCD output v oltage when the DAC is
programmed to 12 and 0 respect ively.
The LCD_BAT (I/O RAM 0x240 2[ 7]) bit causes the LCD system to use the bat tery voltage in all power
modes. This may be usef ul when an ext ernal s up ply is availa ble for the LCD sys tem. T he advanta ge of
c onne c ting t he external supply to VBA T, rather t han VLCD i s that t he LCD DA C is still active.
If LCD_EXT = 1, the VLCD pin m ust be driven fr om an ext er nal source. In thi s case, t he LCD DA C has
no eff ec t.
The LCD s ystem has the ab ilit y to drive up to six segments per SEG driver. If the display is configured with
six back pla nes, t he 6-way multiplexing reduces the number of SEG pins required to drive a display and
therefor e enha nces the number of DIO pins available to the application. Refer to the LCD_MODE[2:0] field
(I/O RAM 0x2400[ 6:4]) settin gs (Table 53) f or th e differ ent LCD multiplexing choices. If 5-state multiple xing
is selected, S EGDIO 27 is converted to COM4. If 6-state multiplexing is sel ec ted, SEGDIO26 is converted
to COM5. These conversions override the SEG/ DIO m apping of SEGDIO26 and SEG DIO27. Additi onally,
independent of LCD_MODE[2:0], if LCD_ALLCOM = 1 (I/O RAM 0x2400[3]) , t hen S E GDI O26 and
SEG DIO 27 bec om e COM4 and COM5 if t heir LCD_MAP[ ] bits are set.
The LCD_ON (I/O RAM 0x240C[0]) and LCD_BLANK (I/O RAM 0x240C[1]) bit s are an easy way to either
blank the LCD display or tur n it f ully on. Neit her bit affects the cont ents of the LCD data stored in the
LCDSEG_DIO[ ] registers. In compar ison, LCD_RST (I/O RAM 0x240C[2]) clears all LCD data t o zero.
LCD_RST affec ts only pins that are c onfigured as LCD.
71M6543F/H and 71M6543G /GH Data Sheet
64 © 2008–2011 Teridian Semiconduct or Cor por ation v1.2
A small am ount of power can be saved by progr amming the LCD frequenc y to t he lowest value that
provides satisfact or y LCD visibility over the required temperat ur e range.
Table 53 shows all I/O RAM register s that cont r ol the operation of t he LCD interf ace.
Table 53: LCD Configurations
Name Location Rst Wk Dir Description
LCD_ALLCOM 2400[3] 0 – R/W
Configures all 6 SEG/COM pins as COM. Has no effect
on pins whose LCD_MAP bit is zero.
LCD_BAT
2402[7]
0
–
R/W
Connects the LCD power suppl y to VBAT in all m odes.
LCD_E 2400[7] 0 – R/W
Enabl es the LCD display . When di sabl ed, VLC2,
VLC1, and V LC0 ar e gr ound as are t he COM and S EG
outputs if their LCD_MAP bit is 1.
LCD_ON
LCD_BLANK 240C[0]
240C[1] 0
0 –
– R/W
R/W
LCD_ON = 1 turns on al l LCD segments without
aff ec ting the LCD data. Similarly, LCD_BLANK = 1
turns off all LCD segments without affecting t he LCD
data. If both bits are set, all LCD segm ents are tur ned
on.
LCD_RST 240C[2] 0 – R/W
Clear all bits of LCD data. These bit s aff ect S EGDIO
pins that are configured as LCD drivers.
LCD_DAC[4:0] 240D[4:0] 0 – R/W
This register c ontrols the LCD contrast DA C which
adjusts the V LCD voltage and has an output r ange of
2.65 VDC t o 5.3 VDC. The VLCD voltage is
VLCD = 2. 65 + 2.65 * LCD_DAC[4:0]/31
Thus, t he LS B of the DAC is 85.5 mV . The maximum
DAC output volt age is limited by V3P3SYS, VBAT , and
whether
LCD_BSTE
is set.
LCD_CLK[1:0] 2400[1:0] 0 – R/W
Sets the LCD cl oc k frequenc y ( 1/T ) . See definition of T
in Figure 17. Note: fw = 32768 Hz
00-fw/2^9, 01-fw/2^8, 10-fw/2^7, 11-fw/2^6
LCD_MODE[2:0] 2400[6:4] 0 – R/W
The LCD bias and m ultipl ex mode.
LCD_MODE
Output
000
4 states, 1/ 3 bias
001
3 states, 1/ 3 bias
010
2 states, ½ bias
011
3 states, ½ bias
100
Static display
101
5 states, 1/ 3 bias
110
6 states, 1/ 3 bias
LCD_VMODE[1:0] 2401[7:6] 00 00 R/W
This register specif ies how VLCD is generated.
LCD_VMODE
Description
11
Ext er nal V LCD
10
LCD boost and LCD DAC
enabled
01
LCD DAC enabl ed
00
No boost and no DAC.
VLCD = VBAT or V3P3SYS
The LCD can be driven in static, ½ bias, and 1/ 3 bias modes. Figure 17 defines the COM waveforms .
Note t hat COM pins that are not r equir ed in a specific mode maint ain a segment off state rather t han
GND, V CC, or high im pedanc e.
T h e se gm ent d river s SEGDIO22 and SE GDIO23 c a n be co nf i gu r ed t o bli n k at either 0.5 Hz or 1 Hz .
Th e bl ink rate is contr olled by LCD_Y (I/O RAM 0x240 0[ 2]) . T her e c an be up to six pixels/segments
connect ed to each of these driver pins. The I/O RAM fields LCD_BLKMAP22[5:0] (I/O RAM 0x2402[5:0])
and LCD_BLKMAP23[5:0] (I/O RAM 0x2401[5:0 ]) identify which pixels, if any, ar e to blink.
LCD_BLKMA P22[5:0] and LCD_B LKMAP23[5:0] are non-volatile.
71M6543F/H and 71M6543G /GH Data Sheet
v1.2 © 2008–2011 Teridian Sem iconduc tor Corpor ation 65
The LCD bias m ay be compensated for tem per ature using the LCD_DAC[4:0] field (I /O R AM 0x240D[4:0]).
The bias m ay be adjusted from 1.4 V below the 3. 3 V supply ( V 3P 3S YS in MSN mode and VBAT in BRN
and LCD mode s) . When the LCD_DAC[4:0] f ield i s s et to 000, the DAC is bypas s ed and powere d
down. T his setting c an be used to r educ e c ur r ent in LC D mode.
Figure 17: LCD Waveforms
SEG 46 through S E G50 cannot be confi gur ed as DIO pins. Display data f or these pins are written t o I/O
RAM registers LCD_SEG46[5:0] through LCD_SEG50[5:0] (see Table 54).
Table 54: LCD Data Registers for SEG DIO 46 to SEGDIO55
SEGDIO 46 47 48 49 50 51 52 53 54 55
Pin # 93 92 58 57 56 53 52 51 47 46
Configuration: Always LCD pi ns S ee 2.5.10.2
SEG Data
Register
LCD_SEGDIO46[5:0]
(I/O RAM 0x243E[5:0]
LCD_SEGDIO47[5:0]
(I/O RAM 0x243F[5:0])
LCD_SEGDIO48[5:0]
(I/O R AM 0 x2440[ 5: 0]
LCD_SEGDIO49[5:0]
(I/O R AM 0 x2441[ 5: 0])
LCD_SEGDIO50[5:0]
(I/O R AM 0 x2442[ 5: 0])
LCD_SEGDIO51[5:0]
(I/O R AM 0 x2443[ 5: 0])
LCD_SEGDIO52[5:0]
(I/O R AM 0 x2444[ 5: 0])
LCD_SEGDIO53[5:0]
(I/O R AM 0 x2445[ 5: 0])
LCD_SEGDIO54[5:0]
(I/O R AM 0 x2446[ 5: 0])
LCD_SEGDIO55[5:0]
(I/O R AM 0 x2447[ 5: 0])
The LCD_MAP[47:46] (I/O RAM 0x2406[7:6]) bits ar e used to det ermine whether SEG 46 and SEG47 are
SEG pins or t heir alternat e function (see pins 93 and 92 i n Figure 43). If the LCD_MAP[47:46] bits are 1,
then t he pins are confi gur ed as SEG pins. If the LCD_MAP[47:46] bits are 0, t hen the pins are configured
as their alternate functions (TM UX2OUT and T MUXOUT, respectively).
STATIC (LCD_MODE=100)
COM0
COM1
COM2
COM3
COM4
COM5
SEG_ON
SEG_OFF
(1/2)
(1/2)
(1/2)
(1/2)
(1/2)
1/2 BIAS, 2 STATES (LCD_MODE = 010 )
COM0
COM1
COM2
COM3
COM4
COM5
SEG_ON
SEG_OFF
(1/2)
(1/2)
(1/2)
(1/2)
0 1 1/2 BIAS, 3 STATES (LCD_MODE = 011 )
COM0
COM1
COM2
COM3
COM4
COM5
SEG_ON
SEG_OFF
(1/2)
(1/2)
(1/2)
012
1/3 BIAS, 3 STATES (LCD_MODE = 011 )
COM0
COM1
COM2
COM3
COM4
COM5
SEG_ON
SEG_OFF
(2/3)
012
(1/3)
1/3 BIAS, 4 STATES (LCD_MODE = 000 )
COM0
COM1
COM2
COM3
COM4
COM5
SEG_ON
SEG_OFF
0 1 2 1/3 BIAS, 6 STATES (LCD_MODE = 110 )
COM0
COM1
COM2
COM3
COM4
COM5
SEG_ON
SEG_OFF
0 1 23 3 4 5
T
71M6543F/H and 71M6543G /GH Data Sheet
66 © 2008–2011 Teridian Semiconduct or Cor por ation v1.2
For example, if LCD_MAP[46] = 1, then pin 93 (TMUX2OUT/SEG46) is configur ed as SEG46, and if
LCD_MAP[46]=0, then pin 93 is confi gur ed as TM UX2OUT.
The SEG pins with alt er nate ICE interfac e function (see pins 56-58 i n Figure 43) are forced to their
alternate ICE interface function (i.e., E_RXTX, E_T CLK and E_RST) if the ICE_E pi n (pi n 59) i s driven
high, and in this case, the bits LCD_MAP[50:48] (I /O RA M 0x2405 [2:0 ]) bits are “don’t care” bits. If the
ICE_E pin is driven low, t hen LCD_MAP[50:48] bits must writt en with 1 in order to configure these pins as
SEG pins. If the ICE _E pi n is low and LCD_MAP[50:48] are wri tten with 0, then these pins are tied t o an
internal pullup.
2.5.11 EEPROM Interface
The 71M6543 provides hardware support for either a two-pin or a three-wire (µ-wire) typ e o f EEPROM
interfac e. The interfaces use the EECTRL (SFR 0x9F) and EEDATA (SFR 0x9E ) registers for communication.
2.5.11.1 Two-pin EEPROM Interface
The de di cat ed 2-pin s er ial inter face communicat es with ext ernal EEPROM devices. The int er face is
multipl ex ed onto the SEGDIO2 (SDCK) and SEGDIO3 (SDATA) pins and is selected by setting
DIO_EEX[1:0] = 01 (I/O RAM 0x2456[7:6]). The MPU commun icates with the interface through the SFR
registers EEDATA and EECTRL. If the M P U wi she s to wri te a byt e of dat a to the EEP ROM, it pl ac es the
data in EEDATA and then writes the Transmit code t o EECTRL. This initiates the transmit oper ation which
is finished when the BUSY bit fa lls. INT5 is also assert ed when BUSY falls. The MPU can then chec k the
RX_ACK bit to see if t he EEPROM ac k nowledged the transmission.
A byt e is read by wri ting the Receive comm and to EECTRL and w aiting for the BUSY bit to fall. Upon
completion, the received data is in EEDATA. T he serial transmit and rec eive clock is 78 kHz duri ng eac h
transm ission, and then holds in a high state until the next transmission. The EECTRL bits when the two-pin
interf ac e is selected are shown i n Table 55.
Table 55: EECTRL Bits for 2-pin Interf ace
Status
Bit Name Read/
Write Reset
State Polarity Description
7 ERROR R 0 Positive 1 when an il legal command is received.
6 BUSY R 0 Positive 1 when serial data bus is busy.
5 RX_ACK R 1 Positive 1 indic ates that the EEP ROM sent an ACK bit.
4 TX_ACK R 1 Positive 1 indicates w hen an ACK bit has been sent to the
EEPROM.
3:0 CMD[3:0] W 0000 Positive
CMD[3:0]
Operation
0000 No-op c om mand. Stops the I
2
C clock
(SDCK). If not issued, SDCK keeps
toggling.
0010 Rec eive a byte from the EEPROM and
send ACK.
0011
Transmit a byte to the EEPROM.
0101 Issu e a S TOP sequence.
0110 Rec eive the last byte from the
EEPROM and do not send ACK.
1001 Issu e a S TART sequence.
Others No operation, set the ERROR bit.
The EE P ROM i nterf ac e c an also be operat ed by c ontrolling the DIO2 and DIO3 pins di r ec tly. The
dir ec tion of the DIO line c an be changed fr om input to output and an output value can be wr it ten
with a single write operati on, t hus avoiding colli si ons (see Table 14 Port Registers (SEG DIO0-15)).
Therefore, no r esi stor is required in seri es SDATA to protect against c ollisions.
71M6543F/H and 71M6543G /GH Data Sheet
v1.2 © 2008–2011 Teridian Sem iconduc tor Corpor ation 67
2.5.11.2 Three-Wire (µ-Wire) EEPR OM Interfac e with Single Data Pin
A 500 kHz three-wire int erfac e, using S DA TA, SDCK, and a DIO pin for CS i s availabl e. The interface is
selected by sett ing DIO_EEX[1:0] = 10. The EECTRL bits when the thr ee-wire interface is selected are
shown in Table 56. When EECTRL is written, up to 8 bits fr om EEDATA are either writt en to t he E E P ROM
or read f r om the E EPRO M, depending on the values of t he EECTRL bits.
2.5.11.3 Three-Wire (µ-Wire/SPI) EEPROM Interface w ith Separate Di /DO Pins
If DIO_EEX[1:0] = 11, the 71M6543 three-wire interface is the same as above, except DI and DO are
separate pi ns. In this case, SE GDIO3 becom es DO and SEG DIO8 becom es DI. The timi ng diagr am s
are the same as for DIO_EEX[1:0] = 10 ex c ept that all output data appears on DO and all input dat a is
expected on DI. I n this mode, DI is ignored while data is being received on DO. This mode is com patible
with SP I modes 0,0 and 1,1 where data i s shif ted out on the falli ng edge of t he cl oc k and i s strobed i n on
the rising edge of t he cl oc k.
Table 56: EECTRL Bits for the 3-wire In t erf ace
Control
Bit Name Read/
Write Description
7 WFR W
Wait fo r Ready . If this bit is set, the trailing edge of BUSY is delayed until
a ri si ng edge is seen on the data line. This bit can be used during t he
last by te of a Wri te com mand to cause the INT5 interr upt to occur when
the EE P ROM has finished its internal write sequence. This bit is
ignor ed if HiZ=0.
6 BUSY R Asserted while the seri al data bus is busy. When the BUSY bit falls, an
INT5 interrupt occurs.
5 HiZ W Indicates that the SD signal is to be floated to high impedance immediately
aft er the last SDCK rising edge.
4
RD
W Indicates that
EEDATA
(
SFR 0x9E
) is to be filled with data from EEPROM.
3:0 CNT[3:0] W
Specif ies the number of cloc k s to be issued. Allowed val ues are 0
through 8. If RD = 1, CNT bi ts of dat a are read MSB first, and r ight
justified into the low order bits of EEDATA. If RD = 0, CNT bits are sent
MSB first to the EEPROM, shift ed out of the MS B of EEDATA. If
CNT[3:0] is zero, S DATA simply obey s the HiZ bit.
The timing diagrams i n Figure 18 through Figure 22 describe the 3-wire EE P ROM interface behavior. All
commands begin when the EECTRL register is written. Transactions star t by fi r st r aisi ng the DIO pin that
is connected to CS. M ultipl e 8-bit or less comm ands such as those sho wn in Figure 18 through Figure 22
are then sent v ia EECTRL and EEDATA.
When the transaction is finished, CS must be lowered. At the end of a Read transact ion, the EE P ROM
drives SDATA, but t r ansi tions to HiZ (high impedance) when CS falls. The firmware should then
immediately issue a wri te command wi th CNT=0 and HiZ=0 to take control of SDATA and forc e it t o a
low-Z state.
Figure 18: 3-wire Interface. Wri t e Command, HiZ=0.
SCLK (output )
BUSY (bit)
CNT Cycles (6 s hown)
SDATA (output)
Wr ite -- No HiZ
D2D3D4D5D6D7
EECTRL Byt e Wri t ten INT5
SDATA output Z
(LoZ)
71M6543F/H and 71M6543G /GH Data Sheet
68 © 2008–2011 Teridian Semiconduct or Cor por ation v1.2
Figure 19: 3-wire Interface. Wri t e Command, HiZ=1
Figure 20: 3-wire Interface. Read Co mmand .
Figure 21: 3-Wire Interface. Write Command when CNT=0
Figure 22: 3-wire Interface. Writ e C om m a n d when HiZ =1 and WFR=1.
2.5.12 SPI Slave Port
The slave SPI port comm unic ates directly with t he M PU data bus and i s abl e to read and wri te Data RAM
and Configurat ion RAM (I/O RAM) locations. I t is also abl e to send commands to the MPU. The interface
to the slave p or t c onsists of the SPI_CSZ, SPI_CKI, SPI_DI and SPI_DO pins. Th es e p ins are mu ltiplexed
with the combined DIO / LCD segment driver pins SEGDIO36 to S EGDIO39 ( pins 3, 2, 1 and 100).
Addi tionall y , t he SPI i nterface allows flash mem or y to be read and to be programmed. To fac ilitate flash
programming, cycling power or asserting RE S E T causes the SPI port pins to def ault to SPI mode. The
SPI port is disabl ed by cl ear ing the SPI_E bit (I/O RAM 0x270C[4] ).
Possible applications for the SPI interface are:
CNT Cycles (6 s hown)
Wr ite -- With HiZ
INT5
EECTRL Byt e Wri t ten
SCLK (output )
BUSY (bit)
SDATA (output) D2D3D4D5D6D7
(HiZ)(LoZ)
SDATA output Z
CNT Cycles (8 s hown)
READ
D0D1D2D3D4D5
INT5
D6D7
EECTRL Byt e Wri t ten
SCLK (output )
BUSY (bit)
SDATA (i nput)
SDATA output Z
(HiZ)
CNT Cycles (0 s hown)
Wr ite -- No HiZ
D7
INT5 not issued CNT Cycles (0 s hown)
Wr ite -- HiZ
INT5 not issued
EECTRL Byt e Wri t ten EECTRL Byt e Wri t ten
SCLK (output )
BUSY (bit)
SDATA (output)
SCLK (output )
BUSY (bit)
SDATA (output)
(HiZ)
SDATA output ZSDATA output Z
(LoZ)
CNT Cycles (6 s hown)
Write -- Wi th HiZ and WFR
EECTRL Byt e Wri t ten
SCLK (output )
BUSY (bit)
SDATA (out/in)
D2D3D4D5D6D7 BUSY READY
(From EEPROM)
INT5
(From 6520)
SDATA output Z
(HiZ)(LoZ)
71M6543F/H and 71M6543G /GH Data Sheet
v1.2 © 2008–2011 Teridian Sem iconduc tor Corpor ation 69
1) An external host reads data from CE locat ions to obtain metering information. This c an be us ed in
applications where the 71M6543 function as a smart front-end with preprocessing capability. Since t he
addresses ar e in 16-bit format, any type of XRAM data can be access ed: CE, MPU, I/O RAM, but not
SFRs or the 80515-internal regis ter bank.
2) A communication link can be established via the SPI interface: By writing into MPU memory locations,
the external host can initiate and c ontrol proces s es in the 71M6543 MPU. Writing to a CE or MPU
location nor m ally gener ates an int er r upt, a function that can be used t o signal to the MPU that the
byte that had just been wr itt en by the external host must be r ead and pr oc es s ed. Dat a c an als o be
insert ed by the external host without generating an interrupt .
3) An external DSP can access f r ont -end data generat ed by the A DC. Thi s mode of operat ion uses the
71M6543 as an analog fr ont -end (AF E ).
4) Flash programm ing by the external host (S P I Fl ash Mode).
SPI Transactions
A typical SPI tr ansact ion is as follows. While SPI_CSZ is high, the port is held in an initi aliz ed/reset state.
Duri ng this state, S PI_DO is held in high impedanc e state and all transi ti ons on SPI_CLK and S PI_DI are
ignor ed. When SPI_CSZ falls, the port begins the tr ansacti on on the fir st ri si ng edge of SP I_CLK. As
shown in Table 57, a transaction consists of an optional 16 bit addres s, an 8 bit command, an 8 bit stat us
byte, f ollowed by one or mor e by tes of data. T he transact ion ends when SPI _CS Z is raised. S om e
transact ions m ay consist of a command only.
When SPI_CSZ rises , SPI comm and bytes that are not of the form x 0000000 cause the SPI_CMD (SFR
0xFD) register to be updated and then cause an interrupt to be issued to the MPU. The exception is if the
transaction was a si ngle byte. In this case, the SPI_CMD byte is always updated and the interrupt issued.
SPI_CMD is not cl ear ed when SPI _CS Z is high.
The SP I port supports data transfers up to 10 Mb/ s. A serial r ead or write operation requires at least 8
clocks per byt e, guaranteeing SPI access to the RAM is no faster than 1.25 MHz, thus ensuring t hat SPI
access to DRA M is al ways possibl e.
Table 57: SPI Transac t io n Fields
Field
Name Required Size
(bytes) Description
Address Yes, exc ept
singl e by te
transaction 2 16-
bit ad dress . T he address field is not requ ir ed if th e transactio n
is a simple SPI command.
Command Yes 1
8-bit command. This byte c an be used as a command to the
MPU. In multi-byte transactions, the MSB is the R/W bit. Unless
the transaction is multi-byt e and SPI_CMD is exactly 0x80 or
0x 00, t he SPI_CMD register is updated and an SP I int errupt is
issued. Otherwise, t he SPI_CMD register is unchanged and the
interrupt is not issued.
Status Yes , if transaction
inc ludes DATA 1 8-bit status field, indica t ing the status of the previous transaction.
This byte is also availabl e in the MPU memory map as
SPI_STAT ( I/O RA M 0x270 8). See Table 59 for the contents.
Data Yes, if transaction
inc ludes DATA 1 or
more The read or write data. Address is auto i nc r em ented for each
new byte.
The SPI_STAT byte is output on ever y SPI transaction and indi c ates the parity of the prev ious tr ansact ion
and the err or status of the pr ev ious tr ansact ion. Potential error sources are:
• 71M6543 not ready
• Transaction not ending on a by te boundary.
SPI Safe Mode
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Sometim es it is desirable to prevent t he S PI interface from writing to ar bitrary RAM l oc ations and thus
distur bing MP U and CE operati on. Thi s i s especially true in AFE applic ations. For this reason, the SPI
SAFE mode was creat ed. In SPI SAFE mode, SPI write operations are disabled exc ept for a 16 byte
transfer r egion at address 0x400 to 0x40F. If the SPI host needs to wri te to other addr esses, i t must use
the SPI_CMD register to request the write operati on f r om the MPU. SPI SAF E mode is enabled by t he
SPI_SAFE bit (I/O RAM 0x270C[3]).
Single-Byte Transaction
If a tr a n sa cti o n i s a si ngle byt e, th e b yt e i s i nt e rp r et ed a s SP I_ C MD. Reg ar dl e ss of the by t e val ue ,
single-byt e transact ions always update the SPI_CMD regi ster and c ause an SPI interr upt t o be gener ated.
Multi-Byte Transaction
As shown in Figure 23, multi-byte operations consist of a 16 bit address field, an 8 bit CMD, a stat us byt e,
and a sequence of data byt es. A multi byt e transact ion is three or more bytes.
A15 A14 A1 A0 C0
0 31
x
D6 D1 D0 D7 D6 D1 D0
C5C6C7
(From Host) SPI_CSZ
(From Host) SPI_CK
(From Host) SPI_DI
(From 6543) SPI_DO
8 bit CMD
16 bit Address DATA[ADDR] DATA[ADDR+1]
15 16 23 24 32 39 Extended Read . . .
SERIAL READ
A15 A14 A1 A0 C0
C5C6C7x
8 bit CMD16 bit Address DATA[ADDR] DATA[ADDR+1]
Extended Write . . .
SERIAL WRITE
D6 D1 D0 D7 D6 D1 D0 x
HI Z
HI Z
Status Byte
ST7 ST6 ST5 ST0 D7
40 47
0 31
15 16 23 24 32 39 40 47
Status Byte
D7
ST7 ST6 ST5 ST0
(From Host) SPI_CSZ
(From Host) SPI_CK
(From Host) SPI_DI
(From 6543) SPI_DO
Figure 23: SPI Sl ave Port - Typical Multi-Byt e Read and Write operations
Table 58: SPI Command Sequences
Command Sequ ence Description
ADDR 1xxx xxxx ST ATUS
Byte0 ... ByteN
Read data starti ng at ADDR. ADDR is auto-incremented until SPI_CSZ
is raised. Upon completion, SPI_CMD (SFR 0x FD ) is updat ed to 1xxx xxxx
and an SPI interrupt is ge nerate d. The exce ption is if th e command
byte is 1000 0000. In t his case, no MP U interrupt is generated and
SPI_CMD is not updated.
0xxx xxxx ADDR Byte0 ...
ByteN
Write data starting at ADDR. ADDR is auto-incremented until SPI_CSZ is
rai sed. Upon c om pletion, SPI_CMD is updat ed to 0xxx xxxx and an SPI
interrupt is generated. The exc eption is if the command byte is 0000
0000. I n this case, no MPU interrupt is generated and SPI_CMD is not
updated.
Table 59: SPI Regi st ers
Name Location Rst Wk Dir Description
EX_SPI 2701[7] 0 0 R/W SPI inter r upt enable bit.
SPI_CMD
SFR FD [7 :0] – – R SP I command. The 8-bit command from the bus master.
SPI_E 270C[4] 1 1 R/W SPI port enable bit. It enabl es the S PI interfac e on pins
SEGDIO36 – SEGDIO39.
IE_SPI
SFR F8[7]
0
0
R/W
SPI interrupt flag. Set by ha r dware, cl eared by writi ng a 0.
SPI_SAFE 270C[3] 0 0 R/W Limits SPI writes to SPI_CMD and a 16 byte region in
DRAM when set . No other wr it e operations are permit ted.
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Name Location Rst Wk Dir Description
SPI_STAT 2708[7:0] 0 0 R
SPI_STAT contains the status result s from the pr ev ious
SPI transaction
Bit 7 - 71M6543 r eady er r or : the 71M6543 was not
ready t o r ead or write as di r ec ted by the previous
command.
Bit 6 - Read data par ity: T his bit is the parit y of all bytes
read from the 71M6543 i n the prev ious command. Does
not include t he SPI _STAT by te.
Bit 5 - Write data parity: This bit is t he overall pari ty of
the bytes wri tten to t he 71M6543 i n the previous
command. It includes CMD and ADDR bytes.
Bit 4:2 - Bott om 3 bi t s of t h e b y t e c o unt . Do es no t
include A DDR and CM D bytes. One, two, and thr ee
byte instruc tions return 111.
Bit 1 - SPI FLASH mode: This bit is zero when the
TEST pin is zero.
Bit 0 - SPI FLASH mode ready : Used in SPI FLASH
m ode. I ndic ates that the fl ash i s ready to rec eiv e
another wri te i nstr uc tion.
SPI Flash Mode (SFM)
In norm al oper ati on, the SPI slave interface cannot r ead or writ e the fl ash memory. However, the
71M6543 suppor ts a special flash mode (S FM) wh ich facilitates initial progr a mmin g of the flash me mory.
When the 71M6543 is in this mode, the SPI can erase, read, and write the flash memory. Other memory
elem ents such as XRAM and IO RAM are not acc essible in this mode. In order to pr otect t he flash
contents, sever al operations are requir ed before the SFM m ode is successfull y inv ok ed.
In SFM m ode, t he 71M6543 supports n byte reads and dual-by te writ es to flash memory. See the SPI
Transaction de sc ri ption on Page 69 for the format of read and write commands. S ince the flash wr it e
operation is alway s based o n a two -by te word, the initial addr ess m ust always be even. Data is written to
th e 16-bit flash memory bus aft er the odd wor d is writt en.
When the 71M6543G/G H is operat ing SFM, SPI singl e-byte t r ansact ions are used to write to
FL_BANK[1:0] (SFR 0xB6[1:0] ). Duri ng an S PI si ngle-by te transact ion, SPI_CMD[1:0] will over-write the
contents of FL_BANK[1:0] (SFR 0xB6[ 1:0] ). This will all ow for ac c ess of the entire 128 KB f lash memory
while oper ati ng in SFM.
In SFM m ode, t he MPU is completely halted. For thi s reason, the interrupt feat ur e described in t he SPI
Transaction secti on above is not available in SFM mode. The 71M6543 m ust be reset by the WD timer or
by the RE S ET pin in or der to exit SFM m ode.
Invoking SFM
The f ollowing conditions must be met prior to invoking SFM:
• ICE_E = 1. Thi s disables the watchdog and adds another layer of protection against inadver tent
Flash corrupti on.
• The ext er nal power source (V3P3SYS, V3P3A) is at the proper lev el (> 3.0 VDC) .
• PREBOOT = 0 (S F R 0xB2[7]). T his validates the state of the SECURE bit (SF R 0xB2[6]).
• SECURE = 0. This I/O RAM register indicat es that SPI secure m ode is not enabled. Operations are
limited to SFM Mass Erase mode if the SECURE bit = 1 (Flash read back is not allowed in Secure mode).
• FLSH_UNLOCK[3:0] = 0010 (I/O RAM 0x27 02[7:4]) .
The I /O RAM registers SFMM (I/O RAM 0x2080) and SFMS (I/O RAM 0x2081) are used to invoke SFM. Only
the SP I int erface has access to these two regi sters. T his eliminates an i ndir ec t path from the MPU for
71M6543F/H and 71M6543G /GH Data Sheet
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disabl ing t he watchdog. SFMM and SFMS need to be written to in sequence in order to invoke SFM. This
se que ntial write proc ess prevents i nadv er tent entering of SFM. The sequence for inv oki ng SFM is:
• First, write to SFMM (I/O RAM 0x2080) regis ter . The value written to this register defines the SFM mode.
o 0x D1: Mass Erase mode. A Flash Mass erase cycle is i nv ok ed upon entering SFM.
o 0x 2E : Flash Read back mode. SFM is ent er ed for Flash read back pur pos es. Fl ash writ es
will not be blocked and it is up to the user to guarant ee that only pr ev iously unwritten
loc ations are written. This mode i s not accessibl e when S P I secure mode is set .
o SFM is not invoked if any other patter n is writ ten to the SFMM register.
• Next , write 0x96 to the SFMS (I/O RAM 0x2081) register. This write invokes S FM provided that the
previous write operation to SFMM met th e req uireme nts. Wr iting any oth er pa ttern to this registe r
does not invoke SFM. Ad dit ionally, any writ e oper ations to t his regi ster automaticall y reset t he
previously wri tt en SFMM register values to zero.
SFM Details
The following occurs upon entering SFM.
• The CE is disabled.
• The MPU is halted. Once the MP U i s hal ted it can onl y be restarted with a r eset. T his reset can be
accomplished wi th the RE S ET pin, a watchdog reset, or by c y cli ng power (wit hout batt er y at the
VBAT pin).
• The Flash cont r ol logic is r eset in case t he M P U was in the middl e of a Fl ash writ e operation or Erase
cycle.
• Mass erase is in voked if specified in the SFMM (I/O RA M 0x2080) register (see Invoking SFM, above).
The SECURE bit (SFR 0xB2[6]) is c leared at t he end of thi s and al l M ass Erase cycles.
• All SPI read and writ e operations now refer to Fl ash i nstead of XRAM space.
The SP I host can ac c ess the curr ent state of t he pending multi-cycle Flash access by performi ng a 4-byte
SPI wri te of any address and check ing t he status fiel d.
All SPI write operati ons i n SFM mode must be 6-byte wri te transactions that write t wo bytes to an ev en
address. T he wri te transactions must c ontain a command byte of 0x00 which i s the form that does not
creat e an M P U interr upt. Auto incrementing i s disabled f or wri te operations.
SPI r ead transact ions can make use of auto increm ent and may access single byt es. The command byte
m ust always be 0x80 in SFM read tr ansact ions.
SPI commands in SFM
Interrupts are not generated in SFM since the MPU is halted. The format of the commands is shown in the
SPI Transactions descri ption on P age 69.SPI Transactions
2.5.13 Hardw are Wat chd o g Ti mer
An independent, r obust, fix ed-dur ation, watchdog timer (WDT) is incl uded in the 71M6543. It uses the
RTC crystal oscillator as its time base and must be r efreshed by the MPU firmware at least every
1.5 second s. When not refreshed on tim e, the WDT overflows and t he par t i s reset as if t he RESET pin
were pull ed high, except that the I/O RAM bi ts are i n the sam e state as after a wake-up fr om SLP or LCD
m odes (see the I/O RAM descri ption in 5.2 for a list of I/O RAM bit states after RESET and wake-up).
Four thousand, one hund red CK32 cycles (or 125 ms) after the WDT overflow, the MPU is launched from
program address 0x0000.
The watchdog timer is also reset when the internal signal WAKE=0 (see 3.4 Wake-Up Beha vior). The
WDT i s di sabl ed when the I CE _E pi n is pull ed high.
For detail s, see 3.3.4 Watchdog Timer (WDT) Reset.
71M6543F/H and 71M6543G /GH Data Sheet
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2.5.14 Test P o r ts (TMUXOUT and TMUX2OUT Pins)
Two independent multipl ex er s all ow the selec tion of internal anal og and digital signals for the TMUXOUT
and TMUX2OUT pins. These pins are multiplexed with the SEG47 and SEG46 function. In order to function
as test pins, LCD_MAP[46] (I /O RA M 0x240 6[6 ]) and LCD_MAP[47] (I/O RAM 0x2406[7]) must be 0.
One of the digital or anal og si gnals l isted in Table 61 can be select ed to be output on t he TMUXOUT pin.
The f unc tion of the multiplexer is cont r olled with the I/O RAM register TMUX[4:0] (I/O RAM 0x250 2[4 :0], as
shown in Table 60.
One of the digital or anal og si gnals l isted in Table 61 can be selected to be output on t he TMUX2OUT pin.
The function of the multiplexer is controlled with the I/O RAM register TMUX2[4:0] (I/O RAM 0x2503[4:0]), as
show n in .
The T M UX and TMUX2 I/O RAM locati ons are non-volatile and t heir c ontent s are preserved by
batt er y power and acros s resets.
The TMUXOUT and TMUX2OUT pins may be used for diagnosi s purposes or in pr oduc tion test. The
RTC 1-second output may be used to c alibr ate the crystal oscillator. The RTC 4-second out put provides
ev en higher pr ec ision.
Table 60: TMUX[4:0] Selections
TMUX[5:0] Signal Nam e Description
1 RTCLK 32. 76 8 kHz cl oc k wav eform
9 WD_RST Indicat es when th e MPU h as r es et th e watc h d og t i m er. Can be
monitored to determine spare time in the watchdog timer.
A CKMPU MPU clock – see Table 8
D V3AOK bit Indicates that the V3P3A pin voltage is ≥ 3.0 V. The V3P3A and
V3P 3SYS pi ns are exp ec ted to be tied tog eth er at th e PCB l evel .
The 71M6543 monitors the V3P3A pin voltage only.
E V 3O K bit Indicate s that the V3P3A pin voltage is ≥ 2.8 V. The V3P3A and
V3P 3SYS pi ns are exp ec ted to be tied tog eth er at th e PCB l evel .
T he 71 M6 54 m on itors th e V3P3A pi n vol t age onl y.
1B MUX_SYNC Internal multiplexer frame SYNC signal. See Figure 4 and
Figure 5.
1C CE_BUSY interrupt See 2.3.3 on pag e 25 and Figure 12 on pag e 46
1D CE_XFER interrupt
1F RTM output from CE See 2.3.5 on pag e 26
Note:
All TMUX[5:0] valu es whic h are n ot sh own are r es erved .
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Table 61: TMUX2[4:0] Selections
TMUX2[4:0] Sign al Nam e Description
0 WD_OVF Ind icat es when the w atc h dog ti m er h as e xp ired (ov er f l ow ed).
1 PULSE_1S
One second pulse with 25% Duty Cycle. This signal can be used
to measure the deviation o f the RTC from an ideal 1 se cond
interval. Multiple cycles should be averaged togethe r to filter out
jitter.
2 PULSE_4S
Four second pulse with 25% Duty Cy cle. This signal can be used
to measure the deviation o f the RTC fro m an ideal 4 se cond
int er val . Mu lti ple cycles should be averaged togethe r to filter out
jitter. The 4 second pulse provides a more precise measurement
than the 1 seco nd pulse.
3 RTCLK 32.76 8 kHz cl oc k wav eform
8 SPARE[ 1] bit – I/O RA M
0x2704[1] Copies the value of the bit sto red i n 0x2704[1]. For general
purpose use.
9 SPARE[ 2] bit – I/O RA M
0x2704[2] Copie s the value of the bit sto red in 0x2704[2]. For general
purpose use.
A WAKE Indicates when a WAKE event has occurred.
B MUX_SYNC Internal multiplexer fra me SYNC signal. See Figure 4 and Figure
5.
C MCK See 2.5.3 on p ag e 50.
E GNDD Digital GND. Use this signal to make the TMUX2OUT pin static.
12 INT0 – DIG I/O
Int err u pt 0. S ee 2.4.9 on page 40. Also see Figure 12 on page 46.
13 INT1 – DIG I/O
14 INT2 – CE_PULSE
15 INT3 – CE_BUSY
16 INT4 - VSTAT
17 INT5 – EEPROM/SPI
18 INT6 – XFER, RTC
1F RTM_CK (flash) See 2.3.5 on p ag e 26.
Note:
All TMUX2[4:0] valu es w hic h are not s h ow n are res er v ed.
71M6543F/H and 71M6543G /GH Data Sheet
v1.2 © 2008–2011 Teridian Sem iconduc tor Corpor ation 75
3 Functional Description
3.1 Theory of Operation
The energy deliver ed by a power source into a load can be ex pr essed as:
∫
=
t
dttItVE
0
)()(
Assum ing phase angl es are constant , the f ollowing formulae apply:
P = Real Energy [W h] = V * A * cos φ* t
Q = Reactive Energy [VARh] = V * A * sin φ * t
S = Apparent Energy [VAh] =
22
QP +
For a practical meter , not o nly vol tage and current ampli tudes, b ut also ph ase angles and har moni c
content may change c onstantly. Thus, simple RM S measurement s are inherently i nac c ur ate. A modern
solid-state ele c trici ty met er IC suc h a s the Teridian 71M6543 functions by emulating the integral
operation above, i.e. it proc esses current and voltage sam ples thr ough an A DC at a constant fr equenc y.
As long as the ADC r esol ution i s high enough and the sample frequency is beyond the harm onic r ange of
interest, the current and voltage sam ples, multiplied with the time period of sampling yields an accurat e
quantity for the mo mentary energy. Summing-up the momentary energy quant iti es over time r esul t s in
accumulat ed ener gy .
Figure 24: Voltage, Current, Moment ary and Accumul at ed Energ y
Figure 24 shows the shapes of V(t), I(t) , t he m omentar y power and the accumulated power, resulting from
50 samples of the voltage and c ur r ent signals over a period of 20 ms. The applicati on of 240 VA C and
100 A results in an ac cumulation of 480 Ws (= 0.1 33 Wh) over the 20 ms period, as i ndicated by the
accumulated power curve. The described sampling method works reliably, ev en i n the presence of dynamic
phase shif t and harmonic distor ti on.
3.2 Battery Modes
Short ly aft er system power (V3P 3S Y S ) i s appli ed, t he 71M6543 i s i n mi ssion mode ( M S N mode). MSN
m ode m eans that t he par t is operating wit h system power and that the int er nal P LL is stabl e. T his mode
is the normal operati ng m ode where the par t is capable of measuring ener gy .
-500
-400
-300
-200
-100
0
100
200
300
400
500
0 5 10 15 20
Current [A ]
V oltage [V]
Energy per I nterval [Ws]
A ccumulated Energy [Ws]
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When system power is not available, the 71M6543 is in one of three battery modes:
• BRN mode (br ownout mode)
• LCD mode ( LCD-only mode)
• SLP mode (sleep mode).
An internal comparator monitors the voltage at the V3P3SYS pin (note that V3P3SYS and V3P3A are
typica lly co nne cted toge ther at the PC B level). Wh en the V3P 3S YS dc voltage dro ps be low 2.8 VDC, the
c omparator resets an internal power status bit called V3OK . As s oon as system power is rem oved and
V3OK = 0, the 71M6543 is forced to BRN mode. The MPU continues to ex ec ute code when the system
transi ti ons fr om MSN to BRN mode or from BRN to MSN m ode. A soft reset should be executed when
returning from BRN to MSN mode in order to re-initi alize the I/O RAM. Depending on the MPU code, the
MPU can c hoose to stay in B RN m ode, or transi tion to LCD or to S LP mode (vi a the I/ O RAM bits
LCD_ONLY, I/O RAM 0x28B2[6] and SLEEP, I/O RAM 0x28B2[7]). BRN mode is similar to MS N mode except
that r esources po wered by sy stem power, such as the ADC and the CE, are not available (see Table 62),
and that the supply current is drawn from the V BAT pi n. In BRN mode, t he PLL conti nues to f unc tion at
the sam e frequenc y as i n M S N mode. The MPU can configure B RN m ode as it desires. F or instanc e, it
m ay choose to minim ize batt er y power by reducing the PLL or MP U cl ock spee d (see 3.2.1 BRN Mode,
for the recom mend ed sett ings to rea liz e min imu m p ower cons ump t ion in BRN mode).
When system power is restored, the 71M6543 auto matically transitions from any of the batt er y m odes
(BRN, LCD, SLP ) bac k to MSN mode.
Figure 25 shows a state diagram of the various operating modes , w ith the possible transitions between modes.
When the part wakes-up under batter y power, the part automati c ally enters BRN mode ( see 3.4 Wake-Up
Behavior). From BRN mode, the part may enter either LCD mode or SLP mode, as controlled by the MPU.
Figure 25: Op erat ion Modes State Diagram
V3P3SYS
rises
V3P3SYS
falls
MSN
BRN
LCD
SLEEP or
VBAT
insufficient
System Power
Battery Power
LCD_ONLY
RESET &
VBAT
sufficient
RESET
Wake Flags
Wake
event
RESET &
VBAT
insufficient
V3P3SYS
rises
V3P3SYS
rises
SLP
Wake
event
VBAT
insufficient
VBAT
insufficient
VSTAT=001VSTAT=00X
71M6543F/H and 71M6543G /GH Data Sheet
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Transi ti ons fr om both LCD and SLP mode to BRN mode can be initiat ed by the follow ing e vents:
• Wake-up timer timeout.
• Pushbutton (PB) is activated.
• A rising edge on SEGDIO4, SEGDIO52 or SEGDIO55.
• Activ ity on the RX or OPT_RX pi ns.
The MP U has access to a variety of registers that si gnal the event that c aused the wake up. See 3.4
Wake-Up Behav ior for details.
Table 62 shows the ci r c uit f unc tions availabl e in eac h operating mode.
Table 62: Available Circuit Functions
Cir c uit Funct io n
System Pow er
Battery Power
MSN (M is s ion Mode )
BRN (Br ownout Mode)
LCD SLEEP
PLL_FAST=1
PLL_FAST=0
PLL_FAST=1
PLL_FAST=0
CE (Computation Engine) Yes Yes --
1
-- -- --
FIR
Yes
Yes
--
--
--
--
ADC, VREF Yes Yes -- -- -- --
PLL Yes Yes Yes Yes Boost
2
--
B attery M eas urem en t Yes Yes Yes Yes -- --
Temperature senso r
Yes
Yes
Yes
Yes
Yes
Yes
Max MP U clock ra te 4.92MHz
(from PLL)
1.57MHz
(from PLL)
4.92MHz
(from PLL)
1.57MHz
(from PLL)
-- --
MPU_DIV clk. divider
Yes
Yes
Yes
Yes
--
--
ICE Yes Yes Yes Yes -- --
DIO Pins
Yes
Yes
Yes
Yes
--
--
Watchdog Timer
Yes
Yes
Yes
Yes
--
--
LCD
Yes
Yes
Yes
Yes
Yes
--
LCD Boost
Yes
Yes
Yes
Yes
Yes
EEPROM Interface (2-wire)
Yes
Yes
Yes
Yes
--
--
EEPROM Interface (3-wire)
Yes
Yes
Yes
Yes
--
--
UART (full speed)
Yes
Yes
Yes
Yes
--
--
Optical TX modulation
38.4kHz
38.9kHz
38.4kHz
38.9kHz
--
--
Flash Read
Yes
Yes
Yes
Yes
--
--
Flash Page Erase
Yes
Yes
Yes
Yes
--
--
Flash Wri te
Yes
Yes
Yes
Yes
--
--
RAM Read and Write
Yes
Yes
Yes
Yes
--
--
Wakeup Timer
Yes
Yes
Yes
Yes
Yes
Yes
OSC and RTC
Yes
Yes
Yes
Yes
Yes
Yes
DRAM data preservation
Yes
Yes
Yes
Yes
--
--
NV RAM data pre servation
Yes
Yes
Yes
Yes
Yes
Yes
Notes:
1. “--“ indicates that the c orres ponding circuit is not active
2. “Boost” implies that the LCD boos t circuit is active (i.e., LCD_VMODE[1:0] = 10 (I/O RAM 0x2401[7:6])). The LCD b oos t
circuit requires a clock from the PLL to function. Thus, the PLL is automatically kept active if LCD boost is active while in
LCD m od e, otherwise the PLL is de-activated.
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3.2.1 BRN Mode
In BRN mode, most non-metering dig ita l functions are act ive (as sho wn in Table 62) includi ng ICE, UART,
EEPROM, LCD and RTC. In BRN m ode, t he P LL continues to functi on at t he same frequency as MSN
m od e. I t i s up to t h e MP U to s c al e do wn t h e PL L ( usi ng PLL_ FA ST, I/ O R AM 0x2 200[ 4] ) or the MPU
frequency (using MPU_DIV[2:0], I/ O RAM 0x 2200[2:0]) in order to save power .
From BRN mode, the MPU can choose to ent er LCD or SLP m odes. When system power is restored
while the 71M6543 is in B RN mode, the part automatically tr ansi tions to MSN mode.
The rec ommended minimum power conf iguration for BRN mode is as follows:
• RCE0 = 0x 00 ( I/O RAM 0x270 9[ 7:0]) - remote sensors disabl ed
• LCD_BAT = 1 (I/O RAM 0x2402[7]) - LCD powered from VBAT
• LCD_VMODE[1:0] = 0 ( I/O RAM 0x24 01[7:6]) - 5V LCD boost disabled
• CE6 = 0x0 0 (I/O RAM 0x2106) - CE, RTM and CHOP are di sabl ed
• MUX_DIV[3:0] = 0( I/O RAM 0x2100 [7 :4]) - the ADC multiplexer is disabled
• ADC_E = 0 ( I/O RAM 0x27 04[ 4]) - ADC disabled
• VREF_CAL = 0 (I/O RAM 0x2704[7] ) – Vr ef not driven out
• VREF_DIS = 1 (I/O RAM 0x2704[6] ) - Vref disabled
• PRE_E = 0 (I/O RAM 0x27 04[5] - pre-amp disabled
• BCURR = 0 (I/ O RAM 0x2704[3] ) - battery 100µA curr ent load OFF
• TMUX[5:0] = 0x0E (I/O RAM 0x2502[ 5:0]) – TMUXOUT output set to a dc value
• TMUX2[4:0] = 0x0 E (I/O RAM 0x2503[4:0]) – TMUXOUT2 output set to a dc val ue
• CKGN = 0 x24 (I/O RAM 0x2200) - PLL set slow, and MPU_DIV[2:0] (I/O RAM 0x2200[2:0]) s et to maximu m
• TEMP_PER[2:0] = 6 (I/O RAM 0x28A0[2:0]) - t em p measurement set to autom atic ev er y 512 s
• TEMP_BSEL = 1 (I/O R AM 0x28 A0 [7 ]) - temperature sensor monitor s VBA T
• PCON |= 1 (SFR 0x87) - at the end of the main B RN loop, halt the MPU and wai t f or an interrupt
• The baud rat e r egister s are adjusted as needed
• All unused i nterrupts are disabl ed
3.2.2 LCD Mode
LCD m ode m ay be commanded by t he MPU at any time by setting the LCD_ONLY control bit ( I/O RAM
0x28B2[6]). However, it is recommended that t he LCD_ONLY contr ol bit be set by t he MPU only aft er the
71M6543 has entered BRN mode. For example, if the 71M6543 is in MSN mode when LCD_ONLY is set,
the durati on of LCD mode is ver y bri ef and t he 71M6543 immediately 'wak es'.
In LCD mode, V3P3D is disabled, and the VBAT pin supplies the LCD curr ent. Before asserting
LCD_ONLY mode, i t is recommended t hat t he MPU minimi z e P LL current by reduci ng the out put
frequency of the PLL to 6.29 MHz (i .e., write PLL_FAST = 0 , I/ O RAM 0x2200[4]) . T he LCD boost system
requi r es a clock from the PLL for its operation. Thus, if the LCD boost system is enabled (i .e.,
LCD_VMODE[1:0] = 10, I/O RAM 0x2401[7:6]), then the PLL is automati c ally kept ac tive during LCD
m ode, ot her wise the P LL is de-activated.
In LCD mode, the data contained in the LCD_SEG registers is di spl ay ed usi ng the segment driver pins.
Up to t wo LCD segment s connected to the pins SEGDIO22 and SEGDIO23 c an be m ade to blink wit hout
the involvem ent of the MP U, which is disabl ed in LCD m ode. T o mi nimi z e batt er y power consumption,
only segments that are used should be enabled.
After the transition from LCD mode to MSN or BRN mode, the PC (Program Counter) is at 0x 0000, t he
XRAM is i n an undefined state, and configuration I/O RAM bits are reset (see Table 71 for I/O RAM state
upon wake). The data stored in non-volatile I/O RAM lo cations is preserved in LCD mode (the shaded
loc ations in Table 71 are non-volatile).
71M6543F/H and 71M6543G /GH Data Sheet
v1.2 © 2008–2011 Teridian Sem iconduc tor Corpor ation 79
3.2.3 SLP Mode
The SLP m ode may be commanded by the MPU whenever main system power is absent by assert ing the
SLEEP bit (I/O RAM 0x28B2[7]). The pur pose of the SLP mode is to consume the least power while stil l
maintaining the RTC, temperature compensation of the RTC, and the non-volatile por t ions of the I/ O RAM .
In SLP mode, the V3P3D pin is disconnected, rem ov ing all sources of leakage fr om VBAT and V3P3SY S.
The non-volatile me mory domain and t he basi c functions, such a s temperature sensor, oscillator , and
RTC, are powered by the VBAT _RTC input. In this mode, the I/O configuration bits, LCD confi gur ation
bits, and NV RAM values are preserved and RTC and oscillator continue t o run. This mode can be exited
only by system power-up or one of the wake m ethods described in 3.4 Wake-Up Behavi or.
If the SLEEP bit is assert ed when V3P3SYS pin power is present (i.e., while in M S N mode), the 71M 6543
enters SLP m ode, resetti ng the inter nal WAK E signal, at whic h point the 71M6543 begins the standard
wake fr om sl eep pr oc edur es as described i n 3.4 Wake-Up Behavior.
After the transition from SLP mode to MSN or BRN mode the PC is at 0x0000, the XRAM is in an
undefi ned state, and the I/O RAM is only partially preserved (see the description of I/O RAM states in
5.2). The non-volatil e secti ons of the I /O RAM are pr eserved unless RES E T goes high.
71M6543F/H and 71M6543G /GH Data Sheet
80 © 2008–2011 Teridian Semiconduct or Cor por ation v1.2
3.3 Fault and Reset Behavior
3.3.1 Events at Power-Down
Power f ault detection is performed by internal comparators that monit or the volt age at the V3P3A pin and
also monitor the internally generated VDD pin voltage (2.5 VDC). T he V 3P 3SYS and V 3P 3A pins must be
tied together at the PCB level, so that the com par ators, which ar e internall y c onnec ted only to the V3P3A
pin, are ab le to simu ltaneously monitor the common V3P3SYS and V3P3A pin voltage. The follow ing
discussi on as sumes that the V3P3A and V3P3S Y S pi ns are ti ed together at the PCB lev el.
Duri ng a power failure, as V3P3A falls , two thresholds are detected:
• The fir st threshold, at 3.0 VDC (VSTAT[2:0] = 001, SFR 0xF 9[2: 0]), warns the MPU that the analog
m odules are no longer acc ur ate. Other than warning t he MPU, the har dware tak es no act ion when
this threshold is crossed. T his comparison produces an internal bit named V3OKA.
• The second threshol d, at 2.8 VDC, causes the 71M6543 to switc h to battery power. This switching
happens whi le t he FLAS H and RAM systems are sti ll able to read and writ e. This comparison
produces an internal bit nam ed V3OK.
The power qualit y i s refl ec ted by the VSTAT[2:0] regi ster i n I/O RAM space, as shown in Table 63. The
VSTAT[2:0] register is located at SFR address F9 and oc c upies bits 2:0. The VSTAT[2:0] field can only be
read.
In addition to t he state of the m ain power, the VSTAT[2:0] register provides information about the internal
VDD voltage under bat tery pow er . Note tha t if system power (V3P3A) is above 2.8 VDC, the 71M6543
always swi tches fr om battery to system power.
Table 63: VSTAT[2:0] (SF R 0xF9[2: 0] )
VSTAT[2:0] Description
000 System Power OK. V3P3A > 3.0 VDC. Analog modules are func tional and accur ate.
001 System Power i s low. 2.8 VDC < V3P3A < 3.0 VDC. Analog m odules not accur ate.
Switc h ov er to bat tery power is immi nent.
010 The IC is on battery power and VDD is OK. VDD > 2.25 VDC. The IC has full digital
functionality.
011 The IC is on battery power and 2. 25 V DC > VDD > 2.0 VDC. Flash write operations are
inhibited.
101 The IC is on battery power and VDD < 2.0, which m eans that the MPU is nearly out of
voltage. A reset occurs i n 4 cycles of the cr ystal cl oc k CK32.
The respon se to a system power fault is almost entir ely cont r olled by firm ware. Duri ng a power failure,
system power slowly f alls. Th is fall in power is monitored by internal comparators that cause the
hardware to autom atically switc h over to taking power from the VBA T input . An interrupt notifies the MPU
that the part is now batt er y powered. A t this poi nt, it is the MP U’s responsi bility to reduce power by
slowing the c lock rat e, disabling t he P LL, et c.
Precision anal og compon ents s uc h a s the bandg ap reference, the band gap buff er , an d the ADC are
powered only by the V3P3A pin and becom e inac c ur ate and ultim ately unavailabl e as the V 3P 3A pin
voltage continues to drop (i.e. , cir cuits po were d by the V3P3A pi n ar e n ot b ack e d by the VBA T pin).
When the V3P3A pin falls below 2.8 VDC, the AD C c lo cks are halte d a nd the amplifiers are unbiased.
Meanwhil e, cont r ol bits such as ADC_E bit (I/O RAM 0x2 704[4 ]) are not af fect ed, since thei r I/O RAM
storage i s po wered from the V DD pin ( 2.5 VDC). The VDD pin is supplied with power through an int er nal
2.5 VDC r egulator t hat is connect ed to the V3P3D pin. In turn, the V3P 3D pin is switched t o r ec eive
power fr om the VBAT pi n when the V3P 3S Y S pi n dr ops below 3.0 VDC. Note that the V3P3SYS and
V3P3A pins are typi c ally tied together at t he P CB level.
71M6543F/H and 71M6543G /GH Data Sheet
v1.2 © 2008–2011 Teridian Sem iconduc tor Corpor ation 81
3.3.2 IC Behavior at Low Battery Voltage
When syste m pow er is not pres en t , the 71M 6543 re lies on th e VBAT pin for power. If the VB A T voltage is
not sufficient to maintain VDD at 2.0 VDC or greater, the MPU cannot operate reliably. Low VBAT voltage
can occur while the part is operating in BRN mode, or while it is dorman t in SL P or LCD mode . Two cas es
can be di stinguished, dependi ng on M P U code:
• Case 1: System power is not pr esent, and the part is waking f r om SLP or LCD mode. In this case,
the hardware check s the value of VDD to determine if processor operation is possible. If it is not
possible, the part confi gur es itself for BRN operation, and holds the pr oc essor in reset (WAK E= 0) . In
this m ode, VBAT powers the 1. 0 VDC reference for the LCD system, the VDD regulator, the PLL, and
the fault comparator. The part remains i n this wait ing mod e unt il V DD become s high d ue to s ystem
power bei ng applied or the VBAT battery being r eplaced or recharged.
• Case 2: The part is operat ing under VBAT power an d VSTAT[2:0] (S FR 0xF9[2:0]) becomes 101,
indicating that VDD f alls bel ow 2.0 VDC. In this case, the firm ware has two choices:
1) One c hoice is to assert the SLEEP bit (I/ O RA M 0x28B 2[ 7]) immediate ly. This assertion preserves
the rem aining char ge in V BAT. Of course, if the batt ery voltage is not increased, t he 71M6543
enters Case 1 as soon as it tries to wake up.
2) The alternat ive choice is to enter the waiting mode described in Case 1 immediately. Specifically,
if the fir mware does not assert the SLEEP bit, the hardware resets the proces sor four CE32 clock
cycles (i.e. 122 µs) after VSTAT[2:0] bec om es 101 and, as descri bed in Case 1, it begins waiting
for VDD to become greater than 2.0 VDC. The MPU wakes up wh en sy st em po wer returns, or
when VDD becomes greater than 2. 0 VDC.
In either case, when VDD recovers, and when the MPU wakes up, the WF_BADVDD flag (I/O RAM 0x28B0[2])
can be read t o determine that the proc essor is recover ing from a bad VBAT conditi on. The WF_BADVDD
fla g remain s set until the next tim e WAKE f alls. This fl ag is i ndependent of the other WF flags.
In all cases, l ow VBAT volt age does not c or r upt RTC operat ion, the stat e of NV memory, o r the s tate of
non-volatile me mory. These circ uits depend on the VBAT_RTC pin f or power.
3.3.3 Reset Sequence
When the RESET pin is pulled high, all di gital activity i n the chip stops, with the ex c eption of the oscillator
and RTC. Additiona lly, a ll I/O RA M bits are f or c ed to t heir RST state. A reliable reset does not occ ur until
RESET has been high at least for 2 µs. Note that TMUX and the RTC are not reset unless the TEST pin
is pul led high while RESET i s hi gh.
The RESET control bit (I/ O RAM 0x 2200[3]) performs an identical r eset to the RESET pin except that a
significantly shorter r eset timer is used.
Once initiated, the reset sequence w aits until t he r eset timer times out. The time out occurs in 4100
CE32 cycles (125 ms), at wh ich time the MPU b egins execut ing its pre-boot and boot sequenc es from
address 0x0000. See 2.5.1.1 for a detailed description of the pre-boot and boot sequences.
If system power i s not pr esent, the r eset timer duration is t wo CE32 cycles, at which time the MPU begins
ex ec uting in BRN m ode, starti ng at addres s 0x0000.
A softer form of reset is initiated whe n th e E_RST pin of the ICE interface is pulled low. This event causes
the MPU an d other registers in t he MPU core to be re s et but doe s not res et the remainder of t he
71M6543. It does not trigger the reset sequence. This type of reset i s intended to reset the MPU
program, but not t o make ot her changes to the c hip’s state.
3.3.4 Watchdog Tim er (WDT) Reset
The watchdog ti mer (WDT) is described in 2.5.13.
A status bit, WF_OVF (I/O RAM 0x28B0[4]) , i s s et when a WDT overflo w oc curs. Similar to the other wak e
flags, this b it is pow ered by the non-volatile supp ly and c an be read by the MPU to det er min e if th e pa rt is
initializing afte r a WD overflow eve nt or afte r a power-up. The WF_OVF bit is cleared by the RES ET pin.
There is no i nternal digital state t hat could deactiv ate the WDT. For debug purposes, however, the WDT
can be di sabl ed by r aisi ng the ICE_E pin to 3.3 V DC.
71M6543F/H and 71M6543G /GH Data Sheet
82 © 2008–2011 Teridian Semiconduct or Cor por ation v1.2
In norm al oper ati on, t he WDT is reset by periodicall y writi ng a one to t he WD_RST control bit I/O RAM
0x28B4[7]). The watchdog timer is also reset when the 71M6543 wakes from LCD or SLP m ode, and
when ICE_E =1.
3.4 Wake-Up Behavior
As described above, the part always wakes up in MSN mode when system power i s restored. As stated
in 3.2 Batter y M odes, transitions from both LCD and SLP mode to BRN mode can be initiated by a wake-
up timer timeout, when the pushbutton (P B ) input is activated, a risi ng edge on S EGDIO 4, SEGDIO52 or
SEG DIO 55, or by activity on the RX or OPT_RX pi ns.
3.4.1 Wake on H ard ware Even t s
Th e fo llowing pin signal events wake the 71M6543 from SLP or LCD mode: a high level on the PB pin, either
edge on the RX pin, a rising edge on the SEGDIO4 pin, a high level on the SEGDIO52 pin, or a high level on
the SEGDIO55 pin or either edge on the OPT_RX pin. See Table 64 for de-bounc e details on each pin and
for further details on the OPT_RX/SEGDIO55 pin. The SEGDIO4, SEGDIO52, and SEGDIO55 pins must
be conf igured as DIO inputs and their wake enabl e (EW_x bi ts) must be set. In SLP and LCD modes, the
MPU is held in res et and can not poll pins o r reac t to i nter rupts. When on e of th e hard ware wake events
occurs, the inter nal WAKE si gnal ris es and within t hree CK 32 cy c le s th e M PU begins to execut e. The
MPU can determine which one of the pins awakened it by checking the WF_PB, WF_RX, WF_SEGDIO4,
WF_DIO52, or WF_DIO55 flags (see Table 64).
If the part is in SLP or LCD mode, it can be awakened by a high level on the PB pin. This pin is normally
pulled to GND and can be connected externally so i t may be pull ed high by a push but ton depression.
Some pins are de-bounced to r ejec t EMI noise. Detection hardware ignores all transitions after the initial
transition. Table 64 shows whic h pins are equi pped with de-bounce c irc uitry.
Pi ns that do not have de-bounce cir c uits m ust still be high f or at least 2 µs to be recognized.
The wake enable and fl ag bits are shown in Table 64. The wake flag bit s are set by har dware when the
MPU wakes from a wake event. Note that the PB f lag is set whenever the PB i s pushed, even if the part
is al r eady awake. Table 66 lists the event s that clear the WF fl ags.
In addition to push butt ons and timer s, the part can also reboot due t o the RES ET pin, the RESET bit (I/O
RAM 0x220 0[ 3]), th e WDT , t he c ol d start d et e ct or , a n d E_R ST . As seen in Table 64, eac h of these
m ec hanisms has a flag bit to aler t the MPU t o the sou r c e of t he wakeu p. If the wakeup is c aused b y
return of system power, there is no active WF flag and the VSTAT[2:0] field (SFR 0xF9[2:0]) indicates that
system power i s stabl e.
Table 64: Wake Enable and Flag Bits
Wake Enable Wake Flag De-bounce Description
Name Location Name Location
WAKE_ARM
28B2[5]
WF_TMR
28B1[5]
No
Wake o n Ti mer.
EW_PB 28B3[3] WF_PB 28B1[3] Yes Wake on P B .*
EW_RX 28B3[4] WF_RX 28B1[4] 2 µs Wake on eith er edge of RX.
EW_DIO4 28B3[2] WF_DIO4 28B1[2] 2 µs Wake o n SE GDIO4.
EW_DIO52 28B3[1] WF_DIO52 28B1[1] Yes Wake on S EGDIO52.*
EW_DIO55 28B3[0] WF_DIO55 28B1[0] Yes
OPT_RXDIS = 1: W ake on DIO55 with
64 ms de-bounce.*
OPT_RXDIS = 0: Wake o n either edg e
of OPT_R X with 2 µ s de-bounce.
OPT_RXDIS: I/O RAM 0x2457[2]
Always Enabl ed
WF_RST
28B0[6]
2 µs
Wake a fter RESET.
Always Enabl ed
WF_RSTBIT
28B0[5]
No
Wake a fter RESET bit.
Always Enabl ed WF_ERST 28B0[3] 2 µs
Wake a fter E_R ST.
(ICE must be enabled)
71M6543F/H and 71M6543G /GH Data Sheet
v1.2 © 2008–2011 Teridian Sem iconduc tor Corpor ation 83
Wake Enable Wake Flag De-bounce Description
Name Location Name Location
Always Enabl ed
WF_OVF
28B0[4]
No
Wake after WD reset.
Always Enabl ed WF_CSTART 28B0[7] No
Wake a fter co ld start - the fi rst
application of power .
Always Enabl ed WF_BADVDD 28B0[2] No
Wake a fter insuffi cient VB A T
voltage.
*This pin is sampled every 2 ms and must remain high for 64 ms to be declared a valid high level. This pin is high-
level sensitive.
Table 65: Wake Bi t s
Name Location RST WK Dir Description
EW_DIOR 28B3[2] 0 – R/W
Connects SEGDIO4 to the WAKE l ogic and permits
SEGDIO4 rising to wake the part. T his bi t has no eff ec t
unless SEGDIO4 i s confi gur ed as a di gital input.
EW_DIO52 28B3[1] 0 – R/W Connect s DIO52 to the WAKE logic and permits DIO52
high level to wake the part. This bit has no effec t unless
DIO 52 is conf igured as a di gital input.
EW_DIO55 28B3[0] 0 – R/W Connect s DIO55 to the WAKE logic and permits DIO55
high level to wake the par t. This bit has no effec t unless
DIO 55 is conf igured as a di gital input.
WAKE_ARM 28B2[5] 0 – R/W
Arms the WAKE timer and loads it wit h the value in
WAKE_TMR (I/O RAM 0x288 0) register. When SLP or
LCD mode is asserted by the MPU, the WAK E tim er
becomes active.
EW_PB 28B3[3] 0 – R/W
Connects the PB pin to the W AKE logic and permits PB
high level to wake the par t. PB is al ways configur ed as
an input.
EW_RX 28B3[4] 0 – R/W Connects the RX pin t o the W AKE logic and permits
RX rising to wake the p ar t. See 3.4.1 for de-bounce
issues.
WF_DIO4 28B1[2] 0 – R
SEGDIO4 flag b it . If SEGDIO4 is configured to wake
the part, this bit is set whenever SEGDIO4 rises. It is
held in reset if SEGDIO 4 is not c onfigured for wakeup.
WF_DIO52 28B1[1] 0 – R
SEGDIO52 flag bit. If SEGDIO 52 is confi gur ed to wake
the part, this bit is set whenever SEGDIO52 is a high
level. It is held in reset if SEGDIO52 is not confi gur ed
for wakeup.
WF_DIO55 28B1[0] 0 – R
SEGDIO55 flag bit. If SEGDIO 55 is confi gur ed to wake
the part, this bit is set whenever SEGDIO55 is a high
level. It is held in reset if SEGDIO55 is not confi gur ed
for wakeup.
WF_TMR
28B1[5] 0 – R Indicates that the Wake timer caused the part to wake up.
WF_PB
28B1[3]
0
–
R
Indicat es that t he PB pin caused the par t to wake.
WF_RX
28B1[4] 0 – R Indicat es that RX pin caused the part to wake.
WF_RST
WF_RSTBIT
WF_ERST
WF_CSTART
WF_BADVDD
28B0[6]
28B0[5]
28B0[3]
28B0[7]
28B0[2]
*
*
*
*
*
– R Indicat es that t he RST pin, E_RST pi n, RESET bit (I/O
R AM 0x22 00[3]), the cold start detec tor, or low voltage
on the VBAT pin caused the part to reset.
*See Table 66 for details.
71M6543F/H and 71M6543G /GH Data Sheet
84 © 2008–2011 Teridian Semiconduct or Cor por ation v1.2
Table 66: Cl ear E vents fo r WAKE flags
Flag Wake on: Clear Events
WF_TMR Ti mer expiration WAKE falls
WF_PB P B pin high level WAKE falls
WF_RX E it her edge RX pin WAKE falls
WF_DIO4 SEGDIO 4 ri si ng edge WAKE falls
WF_DIO52 SEG DIO 52 high level WAKE falls
WF_DIO55
If OPT_RXDIS = 1 (I/O RAM 0x245 7[2 ]),
wake on SEGDI O55 high
If OPT_RXDIS = 0
wake on either edge of OPT_RX
WAKE falls
WF_RST RES E T pin driven high WAKE falls, WF_CSTART, WF_RSTBIT,
WF_ OVF, WF_ BADVDD
WF_RSTBIT RESET bit is set (I/O RAM 0x2200[3]) WAKE falls, WF_CSTART, WF_OVF,
WF_BADVDD, WF_RST
WF_ERST
E_RST pin driven high and the ICE
interface m ust be enabled by driving the
ICE_E pin high.
WAKE falls, WF_CSTART, WF_RST,
WF_ OVF , WF_R S TBIT
WF_OVF Watchdog (WD) reset WAKE falls, WF_CSTART, WF_RSTBIT,
WF_BADVDD, WF_RST
WF_CSTART Cold-start (i. e., aft er the applicati on of
first power) WA K E fa lls , WF_ R STBIT, WF_ OVF,
WF_BADVDD, WF_RST
Note:
“WA K E falls” implies that the internal WAKE signal has been reset, whic h happens automatic ally upon
entry into LCD mode or SLEE P mode (i.e., when the MPU sets the LCD_ONLY b it ( I/O RAM 0x28B2[6]) or
the SLEEP (I/O RAM 0x28B2[7]) bit). When the internal WAKE signal r esets, all wake fl ags are reset. Since
the var ious wake f lags are autom atically reset when WAKE fall s, it is not necessary for the MPU to reset
these flags bef or e entering LCD mode or SLEE P mode. Also, ot her wake events can cause the wake flag
to reset, as indicated above (e.g. , t he WF_RST fl ag c an also be reset by any of the following flags setting:
WF_CSTART, WS_RSTBIT, WF_OVF, WF_BADVDD)
3.4.2 Wake on Timer
If the part is in S LP or LCD mode, it c an be awakened by t he Wake Timer. Until t his timer times out, the
MPU is in r eset due to the internal WAKE signal bei ng low. W hen the Wake Timer times out, WA K E rises
and within thr ee CK32 cycl es, the MPU begins to execute. The MPU can determi ne that the timer wok e it
by checking the WF_TMR (I/O RAM 0x28B1[2]) w ake flag.
The Wake Timer begins timing when the part enters LCD or SLP mode. Its durati on is cont r olled by the
WAKE_TMR[7:0] register (I/O RAM 0x2880). The timer duration is WAKE_TMR[7:0] +1 seconds.
The Wake T imer i s armed by setting WAKE_ARM = 1 (I/O RAM 0x28B2 [5 ]). It must be armed at l east
three RTC cycles bef or e either SLP or LCD mode s are i nit iated. S ettin g WAKE_ARM preset s th e timer
with the value in WAKE_TMR and r eadies the t imer to start when the MPU writ es to the SLEEP (I/O RAM
0x28B2[7]) or LCD_ONLY (I/O RAM 0x28B2[6]) bits. T he timer is nei ther reset nor di sarmed when the
MPU wakes-up. Thus, once ar med and set, t he MPU continues to be awakened WAKE_TMR[7:0]
seconds after it requests SLP mode or LCD mode (i.e., once written, the WAKE_TMR[7:0] register holds
its v alue and does not have to be re-wri tt en eac h time the MPU enters SLP or LCD mode. Al so, si nc e
WAKE_TMR[7:0] i s non-volatile, it also holds its value through resets and power fail ur es).
3.5 Data Flow and MPU/CE Communication
The data flow between the Compute Engine (CE) and the MPU is shown in Figure 26. In a typical application,
the 32-bit CE sequentially processes the samples from the ADC inputs, performing calculations to measure
71M6543F/H and 71M6543G /GH Data Sheet
v1.2 © 2008–2011 Teridian Sem iconduc tor Corpor ation 85
active power (Wh), reactive pow er (VARh), A2h, and V2h for four-quadrant metering. These measurements
are then ac c essed by the MP U, processed f ur ther and output usi ng the peri pher al dev ic es availabl e to t he
MPU.
Both the CE and m ultipl ex er are controlled by the MP U vi a shared register s i n the I/O RAM and in RAM.
The CE outputs a total of six discrete signals to the MPU. These consist of four pulses and two interrupts:
• CE_BUSY
• XFER_BUSY
• W PULSE, VP ULSE (pulses for active and reactive energy)
• XPULSE, YP ULS E (auxiliary pulses)
These interrupts are conn ec ted to th e M PU interrupt ser vi c e inputs as ext er nal int errupts. CE_BU S Y
indicates that the CE is actively processing d ata. This sign al occurs once every multiplexer cyc le (ty pically
396 µs), and indicates that the CE has updated status information in its CESTATUS register (CE RAM 0x80).
XFER_BUSY indicates that the CE is updating data to the output region of the RAM. This update occurs
whenever the CE has finished generating a sum by completing an accum ulation interval determi ned by
SUM_SAMP S[12:0], I/O RAM 0x2107[4:0], 2108[7:0], (typically every 1000 ms). Interrupts to the MPU occur
on the f alling edges of t he XFE R_B USY and CE_B USY signals.
WPULSE and VPULSE are typic ally used to signal energy acc um ulation of real (Wh) and r eactive (VARh)
energy. Tying WPULSE and VPULS E into the MP U interr upt system c an support pulse counting.
XPULSE and YP ULSE can be used to si gnal e ven ts suc h as sags and zero cr os s ings of the ma ins voltage
to t he MPU. Tying these output s i nto the MPU int er r upt system relieves the MPU from hav ing to read the
CESTATUS regi ster at ever y occurr enc e of the CE_BUSY interr upt in order to det ect sag or zero cr ossing
events.
Refer to 5.4 CE Interface Description on page 120 for additional inf ormation on setting up t he dev ic e
using the M P U firmware.
Figure 26: MPU/ CE Data Flow
MPU
CE
I/O RAM (Configuration RAM)
Pulses
Samples
WPULSE
VPULSE
XPULSE
YPULSE
Control
Processed
Metering
Data
MUX
Control
Control
Interrupts
CECONFIG
CESTATUS
XRAM
CE_BUSY
XFER_BUSY
71M6543F/H and 71M6543G /GH Data Sheet
86 © 2008–2011 Teridian Semiconduct or Cor por ation v1.2
4 Application Information
4.1 Connecting 5 V Devices
All digital i nput pins of the 71M6543 are com patible with external 5 V devices. I/O pins configured as
inputs do not require current-limi ting resistor s when they ar e c onnec ted to external 5 V devices.
4.2 Directly Connected Sensors
Figure 27 through Figure 30 show voltage-sensing resi stive div iders, current-sensing current transformers
(CTs) and current-sensing resistive shunts and how they are connec ted to the voltage and curr ent input s
of t he 71M6543. All input signals to the 71M 6543 sensor input s are voltage signal s providing a scal ed
representat ion of either a sensed voltage or current.
The analog input pins of the 71M6543 are designed f or sensors wit h low source impedanc e.
RC filt er s with r esi stanc e values hi gher than those implemented in the T eri dian Dem o B oar ds
must not be used. P lease refer to t he Dem o Board schematics for complet e sensor input
ci r c uits and corresponding c omponent values.
V
IN
R
OUT
V3P3A
VADCn
(n = 8, 9 or 10)
Figure 27: Resistive Volt age Di vid er (Voltage Sensing)
I
IN
IADCn
V3P3A
V
OUT
I
OUT
R
BURDEN
CT
1:N Noise Filter
(n = 0,1,...7)
Figure 28. CT wit h Sin gle-Ended Input Connect io n (Curren t S ensi ng )
IIN
IADCn
IADCn+1
V3P3A
VOUT
IOUT
RBURDEN
CT
1:N Bias Network and Noise Filter
(n = 0, 2, 4 or 6)
Figure 29: CT with D iff e r e ntial Input Connection (Current Sensing)
I
IN
R
SHUNT
IADCn
IADCn+1
V3P3A
V
OUT
Bias Network and Noise Filter
(n = 2, 4 or 6)
Figure 30: Differential Resistive Shunt Connections (Current Sen sin g)
71M6543F/H and 71M6543G /GH Data Sheet
v1.2 © 2008–2011 Teridian Sem iconduc tor Corpor ation 87
4.3 Systems Using 71M6xx3 Isolated Sensors and Current Sh unts
Figure 31 shows a typical connection for cur r ent shunt sensors; usi ng the 71M6xx3 (polyphase) isolated
sensors. Note t hat one shunt cur r ent sensor is connect ed without isolati on, which is the neutr al current
sensor in thi s example (connected to pins IADC0-IADC1). Each 71M6xx3 device is electrically isolated
by a l ow-cost pul se tr ansformer. The 71M6543 current sen sor inputs m ust be c onfigured f or remote
sensor communications, as described in 2.2.8 71M6xx3 Isolat ed S ensor I nterf ac e (page 22). Flexible
remappi ng using the I/ O RAM registers MUXn_SEL[3:0] allows the sequence of analog input pi ns to be
differ ent f r om the standard conf igurati on (a corresponding CE c ode m ust be used). See Figure 2 for the
AFE configuration corresponding t o Figure 31.
MPU
RTC
TIMERS
IADC0
VADC8 (VA)
IADC2
VADC9 (VB)
XIN
XOUT
RX
TX
TX
RX
COM0...5
V3P3A V3P3SYS
VBAT
VBAT_RTC
IADC4
VADC10 (VC)
SEG
GNDA GNDD
SEG/DIO
DIO
ICE
C
B
A
NEUTRAL
LOAD
8888.8888
PULSES,
DIO
IR
AMR
POWER FAULT
COMPARATOR
MODUL-
ATOR
SERIAL PORTS
OSCILLATOR/
PLL
MUX and ADC
LCD DRIVER
DIO, PULSES
COMPUTE
ENGINE
FLASH
MEMORY
RAM
32 kHz
REGULATOR
Shunt Current Sensors
POWER SUPPLY
TERIDIAN
71M6543F/
71M6543H/
71M6543G/
71M6543GH
TEMPERATURE
SENSOR
VREF
IADC6
BATTERY
PWR MODE
CONTROL
WAKE-UP
NEUTRAL
I
2
C or µWire
EEPROM
9/17/2010
IADC1
IADC3
IADC5
IADC7
RTC
BATTERY
V3P3D
BATTERY
MONITOR
SPI INTERFACE
HOST
LCD DISPLAY
Resistor Dividers
Pulse Transformers
3x TERIDIAN
71M6xx3
Note: This system is referenced to Neutral
71M6xx3
71M6xx3
71M6xx3
}
IN*
}
IA
}
IB
}
IC
*IN = Neutral Current
Figure 31: System Usi ng Three-Remotes and One-Local (Neutral) S enso r
71M6543F/H and 71M6543G /GH Data Sheet
88 © 2008–2011 Teridian Semiconduct or Cor por ation v1.2
4.4 Syst em Using Current Transformers
Figure 32 shows a polyphase system usi ng f our current t r ansform er s to support optional Neutr al c ur r ent
sensing for anti-tamper pur poses. The Neutral curr ent sensing CT c an be omi tt ed if Neutr al current
sensing is not requi r ed. T he system is ref er enc ed to Neutral (i.e., the Neutr al rail is tied to V3P3A and
V3P3SYS).
MPU
RTC
TIMERS
IADC2
VADC8 (VA)
IADC4
VADC9 (VB)
XIN
XOUT
RX
TX
TX
RX
COM0...5
V3P3A V3P3SYS
VBAT
VBAT_RTC
IADC6
VADC10 (VC)
SEG
GNDA GNDD
SEG/DIO
DIO
ICE
A
B
C
NEUTRAL
LOAD
8888.8888
PULSES,
DIO
IR
AMR
POWER FAULT
COMPARATOR
MODUL-
ATOR
SERIAL PORTS
OSCILLATOR/
PLL
MUX and ADC
LCD DRIVER
DIO, PULSES
COMPUTE
ENGINE
FLASH
MEMORY
RAM
32 kHz
REGULATOR
Current Transformers
POWER SUPPLY
TERIDIAN
71M6543F/
71M6543H/
71M6543G/
71M6543GH
TEMPERATURE
SENSOR
VREF
IADC0
BATTERY
PWR MODE
CONTROL
WAKE-UP
NEUTRAL
I
2
C or µWire
EEPROM
9/17/2010
IADC3
IADC5
IADC7
IADC1
RTC
BATTERY
V3P3D
BATTERY
MONITOR
SPI INTERFACE
HOST
LCD DISPLAY
Resistor Dividers
Note: This system is referenced to Neutral
}
IA
}
IB
}
IC
}
IN*
*IN = Optional Neutral Current
Figure 32. System Usin g Cu rrent Transformers
71M6543F/H and 71M6543G /GH Data Sheet
v1.2 © 2008–2011 Teridian Sem iconduc tor Corpor ation 89
4.5 Metrology Temperature Compensation
4.5.1 Distinc tion Between Standard and High-Precision Parts
Since the VREF band-gap a mp lifier is cho ppe r-sta bili zed, as s et by t he CHOP_E[ 1:0] (I/ O RAM 0x2 106[3:2])
control field, the dc offset voltage, which is the most significant long-term drift mechanis m in the voltage
references (VREF), is autom atically rem ov ed by the chopper cir c uit. B oth the 71M6543 and the 71M 6xx3
feature chopper ci r c uits for their respective V REF voltage r efer enc e.
Since the vari ation in the bandgap reference v oltage (VREF) is the major contributor to measurement
error across temper atures , Teridian implements a two step procedure to tr im and ch ar act erize the
VREF voltage reference d ur ing the devi c e manufac turing pro c ess.
The fi r st step in the process is applied to both all par ts (71M6543F, 71M6543H, 71M 6543G,
71M6543GH). In this first s te p , th e re ference voltage (VREF) is trimmed to a target val ue of 1. 195V .
Duri ng this trimmi ng pr oc ess, the TRIMT[7:0] (I/O RAM 0x2309) value is stored in non-volatile fuses.
TRIMT[7:0] is trimmed to a value that results in minimum VREF variation w ith temperature.
For th e 71M65 43F a nd 71M 6 54 3G devices (±0.5% energy a ccuracy) , the TRIMT[7:0] val ue c an be r ead
by the MPU during initial ization in order to c alcul ate parabolic temper ature c ompen s ati on coeffici ents
suitabl e for each i ndiv idual 71M6543F and 71M65 43G device. T he resulting temperature coefficient for
VREF in the 71M6543F a nd 7 1M6 543G is ±40 ppm / °C.
Considerin g the factory cali bration temperature of V REF to be +22°C and the i nd ustrial temperatu r e
ran ge (-40°C to +85 °C), the VRE F er ror at the temperatur e ext r emes for th e 71M65 43F an d 71M 65 4 3G
devices can be cal c ulated a s:
%252.02520/40)2285(+=+=⋅− ppmCppmCC ooo
and
%248.02480/40)2240(−=−=⋅−− ppmCppmCC
ooo
The ab ove calcul ati on im plies that both the voltage a nd the current mea su r ements are indivi dually
subjec t to a the oreti c al maxi mum er r or of approx imately ± 0.25%. When the volt age sample and current
sampl e are multipl ied togethe r to obtain the en ergy pe r sam ple, the voltage erro r and current error
combi ne resultin g in appr oximately ±0.5% maximum energy me asurement err or. However , this
theoretical ± 0.5 % error conside rs only the vol tage r eference (VRE F) as an e r r or source. In p r ac tice,
oth er err or sou rc e s ex ist in the system. The principal r em aini ng er ror sour c es ar e the c urr ent s en sor s
( sh unts or CTs) an d their corresponding signal condi ti oning ci r cuits, and th e resistor vol tage divi der
use d to measure t he voltage. The 71M65 43F a nd 71 M65 43G 0.5% grade devices s houl d be u sed in
Class 1% de signs, to allow margi n for the other er ror source s i n the system.
The 71M6543H and 71M 6543GH devices (±0.1% energy accurac y ) goes thr ough an additional pr oc ess of
characterizati on duri ng pr oduc tion which makes it sui table to high-acc ur ac y appli c ations. The additional
process is the char ac ter iza tion of the voltage reference (VREF) over temperature. The coeff icient s for the
voltage reference are stored in additional non-volatile trim fuses. The MP U c an read these t r im fuses
during initi ali z ati on and cal culate p ar abolic temper ature c ompen s ati on coefficients s uit abl e for each
individual 71M65 43H and 71M 6543GH device. The resul ti ng temperature c oefficient for V RE F i n the
71M6543H an d 71M65 43GH is ±10 ppm/ °C.
The V RE F e r ror at th e temper ature extreme s for the 7 1M 6543H a nd 71 M6 54 3GH devices ca n be
cal c ulated a s :
%063.0630/10)2285(+=+=⋅− ppmCppmCC
ooo
and
%062.0620/10)2240(−=−=⋅−− ppmCppmCC
ooo
When the voltage s ample a nd current sample ar e multipl ied together to obtain the energy per sampl e,
the v ol tage er r or a nd c urr ent error combine re s ulting in approxi mately ± 0.126% maxi mum energy
71M6543F/H and 71M6543G /GH Data Sheet
90 © 2008–2011 Teridian Semiconduct or Cor por ation v1.2
m easur em ent er r or. T he 7 1M6 543H a nd 71M 654 3G H 0.1% gra de devic es s hould be use d in Class
0.2% and Class 0.5% design s , to allow margin for the other error sources in the syst em.
The preceding discussion in this s ec ti on also ap pli es to the7 1M 6603 (0.5%), 71M6113 ( 0. 5%) a nd
71M 6203 ( 0.1 %) r em ot e sen so r s. Refer to the 7 1M 6xxx Dat a Sheet for detail s.
4.5.2 Temperature Coefficients for the 71M6543F and 71M6543G
Th e equations provided below for calculating TC1 and TC2 apply to the 71M6543F and 71 M 65 43G (0.5%
energy accuracy). In order to obtain TC1 and TC2, the MPU reads TRIMT[7:0] (I/O RAM 0x2309) and uses
the TC1 and TC2 equations provided. PPMC and PPMC2 are then calculated from TC1 and TC2, as shown.
The resulting tr ack ing of the reference voltage (VREF) is within ±40 ppm/°C, corresponding to a ±0.5%
energy measure men t accura cy . See 4.5.1 Distinction Between Standard and Hi gh-P r ec ision P arts.
TRIMTCVTC ⋅−=° 95.4275)/(1
µ
TRIMTCVTC ⋅+−=° 00028.0557.0)/(2 2
µ
14632.22 TCPPMC ⋅=
2116.11502TCPPMC ⋅=
See 4.5.5 and 4.5.6 below for fu rther temperature compensation details.
4.5.3 Temperature Coefficients for the 71M6543H and 71M6543GH
The 71M6543H and 71M6543G H under go a two-pass fact or y trimming process which stores addi ti onal
trim fuse values. The additional trim fuse values characterize the device’s VREF behavior at various
temperatures. The values for TC1 and T C2 are calculated from the values read from the TRIMT[7:0] (I/O
RAM 0x2309), TRIMBGB[15:0] (Info P age 0x92 and 0x93) and TRIMBGD[7:0] (Info Page 0x94) non-
volatile on-chip fuses using t he equati ons provided. The resulting tracking of the reference voltage is
within ±10 ppm/°C, corresponding to a ±0.126% energy measurement accuracy. Th e equa t ions for deriving
P P CM and PP MC2 from TC1 and TC2 are also provided. See 4.5.1 Distinction Between Standard and
High-Pr eci si on P ar ts.
TC1(V/)
=35.091+0.01764TRIMT+1.587
(
 
)
TRIMTCVTC ⋅−−=° 00028.0557.0)/(2 2
µ
14632.22 TCPPMC ⋅=
2116.11502TCPPMC ⋅=
TRIMT[7:0] trims the VREF voltage for minimum varia tion with temperature. The TRIMT[7:0] fuses are
read by t he M P U directl y at I/O RAM address 0x2309[7:0].
Duri ng the second pass trim for the 71M6543H and 71M6543GH, VREF i s fur ther charact eri z ed at 85°C
and 22°C, and t he r esul ting fuse trim values are stored in TRIMBGB[15:0] and TRIMBGD[7:0],
respectively. TRIMBGB[15:0] and TRIMBGD[7:0] cannot be r ead dir ec tly by the MPU. See 5.3 Reading
the I nfo Page (71M6543H and 71M6543G H only) on page 118 for inf ormati on on how to read the Info
Page trim fuses.
See 4.5.5 and 4.5.6 below for fu rther temperature compensation details.
4.5.4 Temperature Coefficients for the 71M6xx3
Refer to the 71M6xxx Data sheet f or the equations that are appli c able to each 71M6xx 3 part num ber and
the cor r espondi ng temperature coeff icient s.
4.5.5 Temperature Compensation for VREF and Shunt Sensors
This sect ion discusses metr ology temper ature compensation f or the met er designs where curr ent shunt
sensors are used in conjuncti on with T eri dian’s 71M6xx 3 r em ote isolat ed sensors, as sho wn in Figure 31.
Sensors that ar e directly c onnec ted to the 71M6543 are affected by the voltage vari ation in t he 71M 6543
VREF due to t em per ature. On the other hand, shunt sensor s that are connected to 71M6xx3 remote
sensor are affected by the VREF in the 71M6xx3. The VREF in both the 71M6543 and 71M6xx3 can be
71M6543F/H and 71M6543G /GH Data Sheet
v1.2 © 2008–2011 Teridian Sem iconduc tor Corpor ation 91
compensated di gitall y using a second-order polynomial functi on of t em per ature. The 71M6543 and
71M6xx3 feat ur e temper ature sensors f or the purpose s of temperat ur e c om pensating their correspondi ng
VREF. The compensation com putations must be implemented in MPU firmware.
Referring to Figure 31, the VADC8 (VA), VADC9 (VB) and VADC10 (VC) volt age sensors are always
dir ec tly connected to the 71M6543. Thus, t he pr eci si on of t he voltage sensors is primarily affected by
VREF in the 71M6543. The temperature coefficient of the resistors used to implement the voltage dividers
for the voltage sensors (see Figure 27) determine the behavior of the voltage division ratio with respect to
temperature. It is recommended to use resistors with low temperature coefficients, while forming the entire
voltage divider using resistors belonging to the same technology family, in order to minimize the temperature
dependency of the voltage division ratio. The resistors must also have suitable voltage ratings.
The 71M6543 also may have one local c ur r ent sh unt s ens or tha t is c onnec ted di r ec tly t o it via the IADC0-
IADC1 input pins, and therefor e this local c ur r ent sensor i s al so aff ected by the VREF in the 71M6543.
The shunt cur r ent sensor resistance has a t emperature dependency, whi c h also may require
compensation, depending on the r equired accuracy class.
The IADC2-IADC3, IADC4-IADC5 and IADC6-IADC7 current sensors are is olated by the 71M6xx3 and
depend on the VREF of the 71M6xx3, plus the variation of the corresponding remote shunt current s ensor
with temperature.
The MPU has the responsib ilit y of co mpu t ing the nec es s ary sample gain co mpensation values req uired for
each sensor channel based on the sensed temper ature. T eri dian provides demonstrat ion code that
implements the GAIN_ADJx c om pensation equati on shown belo w. T he r esul ting GAIN_ADJx values are
stored by t he MPU in five C E RA M locat ions GAIN_ADJ0-GAIN_ADJ5 (CE RAM 0x40-0x44). The
demonstration code thus provides a suita ble implementat ion of t em per ature compensati on, but other
m ethods are possible in MPU firmw ar e by ut iliz ing the on-chip temperature sensors while storing the
sample gain adj ustment resul ts in the CE RAM GAIN_ADJx storage locations for us e by the CE . The
demonstration code maintains five separate sets of PPMC and PPMC2 coefficient s and computes five
separate GAIN_ADJx values based on the sensed temperature using t he equati on below:
23
2
14 22_100
2
_10
16385_ PPMCXTEMPPPMCXTEMP
ADJxGAIN ⋅⋅
+
⋅⋅
+=
The GAIN_ADJx values stored by t he MPU in CE RAM are used by the CE t o gain adjust ( i.e., multi ply )
the sam ple in each correspondi ng sen sor channel. A GAIN_ADJx value of 16,384 (i.e., 214)c or r esponds to
unity gain, whil e v alues l ess than 16,384 attenuate the sampl es and values greater than 16,384 amplify
the sam ples.
In t he above equ ati on, TEMP_X is the devi ati on from nominal or cali br ation temperat ure expr ess ed in
multiples of 0.1 °C. The 10x and 100x f actor s seen in the above equation are due to 0.1 oC scali ng of
TEMP_X. For example, if the calibrati on (refer enc e) temperature is 22 oC and the measured temperature
is 27 oC, then 10*TEMP_X = (27-22) x 10 = 50 (decimal), which r epr esents a +5 oC dev iation from 22oC.
In t he dem onstr ation code, TEMP_X is calculated in the MPU from the STEMP[10:0] temper ature sensor
readi ng usi ng the equation prov ided below and is scaled in 0.1°C units. See 2.5.5 71M6543 Temper ature
Sensor on page 55 for the equation to ca lculate temperature in degrees °C from the STEMP[10:0] value.
Table 67 shows the five GAIN_ADJx equation output storage locati ons and the volt age or curr ent sensor
channel s for whic h they c om pensate for the 1 Local / 3 Remot e configur ation shown in Figure 31.
Table 67: GAIN_ADJn Compensation Channels (Figure 2, Figure 31, Table 1)
Gain Adju st me nt Out put CE RAM Address Sensor Channel(s)
(pin name s) Compensation For:
GAIN_ADJ0 0x40 VADC8 (VA)
VADC9 (VB)
VADC10 (VC)
VRE F in 71 M 6543 and Voltage Divide r
Resistors
GAIN_ADJ1 0x41 IADC0-IADC1
VREF in 71M 65 43 and S h un t
(Neutral Current)
GAIN_ADJ2 0x42 IADC2-IADC3
VREF in 71M6xx3 and Shunt
(Phase A)
GAIN_ADJ3 0x43 IADC4-IADC5
VREF in 71M6xx3 and Shunt
(Phase B)
71M6543F/H and 71M6543G /GH Data Sheet
92 © 2008–2011 Teridian Semiconduct or Cor por ation v1.2
GAIN_ADJ4 0x44 IADC6-IADC7
VREF in 71M6xx3 and Shunt
(Phase C)
In t he dem onstr ation code, the shape of the t em per ature compensati on second-order par aboli c c urve is
determ ined by the values stored in the PPMC (1st or der coefficient ) and PPMC2 (2nd order coeff icient),
which are typically setup by the MP U at initi alizati on time from val ues that are stor ed in EEPROM.
To disable temperature com pensation in the demonstrat ion code, PPMC and PPMC2 are both set to zero
for each of the five GAIN_ADJx channels. To enable temperature compensation, the PPMC and PPMC2
coefficients are set wit h val ues that match the expect ed temper ature vari ation of the shunt curr ent sensor
(if required) and the corr espondi ng V RE F voltage reference (summed t ogether).
The shunt sensor requires a second or der polynomial com pensation which is deter m ined by the PPMC
and PPMC2 coefficients for the c or r espondi ng c ur r ent measurem ent channel. The corresponding VREF
v oltage ref er enc e also requires the PPMC and PPMC2 coef fici ents to mat c h the second order
temper ature behavior of the volt age r eference. The P PMC and PP M C2 v alues associ ated with the shunt
and with t he c or r espondi ng V RE F are summed together to obtain the com pensation coefficients for a
giv en c ur r ent-sensi ng c hannel (i.e., the 1st order PPMC coeff icient s are summed together, and the 2nd
order PPMC2 coeff ic ient s are summed t ogether).
In the 71M 6543 F and 7 1M654 3G, the required VREF compensation coefficients PPMC and PPMC2 are
calculated from readable on-c hip non-volatile fuses (see 4.5.2 T emper ature Coefficient s for the
71M6543F). T hes e co ef fi ci ent s are de si gne d to ac hi ev e ±4 0 ppm/° C for VR E F i n the 71M65 43F and
71M6543G. P P M C and P P M C2 coefficients are simi larly calculated for t he 71M6xx3 rem ot e sen sor
(see 4.5.4 Temperature Coefficients for the 71M6xx3).
For the 71M6543H and 71M6543GH (±0.1% ener gy accurac y ), coefficients speci fi c to eac h indiv idual
device can be calcu lated from values read from additional on-chip fuses that c har ac terize t he VREF
behav ior of each indiv idual part acr oss industrial temper atures (see 4.5.3 Te mperature Coefficients for
the 71M6543H). The resulting t rac k ing of the reference VREF voltage is within ±10 ppm/°C.
For th e current c hannels, to determine the PPMC and PPMC2 coefficients for t he shu nt cu r rent
sensors, the de signer mu st either kno w th e average temperature curve of t he shunt from its
m anuf act ur er ’s d ata sh eet or obt ai n these coeffi c ient s by la borator y charact erizat ion of the shunt used
in the de si gn.
4.5.6 Temperature Compensation of VREF and Current Transformers
This sect ion discusses metr ology temper ature compensation for meter desi gns where Current
Transform er (CT ) sensors are used, as shown in Figure 32.
Sensors that ar e directly c onnec ted to the 71M6543 are aff ec ted by the voltage variation in the 71M6543
VREF due to t em per ature. The VREF in the 71M6543 can be compensated di git ally usi ng a second-
order polynomial functi on of t em per ature. T he 71M 6543 features a tem per ature sensor for the purposes
of t em per ature compensati ng its VREF. The compensa tion c om putati ons must be implemented in MPU
firmware and wri tten to t he correspondi ng GAIN_ADJx CE RAM location.
Referring to Figure 32, t he VADC8 (VA), VADC9 (VB) and VADC10 (VC) v oltage sensors are dir ec tly
connect ed to the 71M 6543. Thus, the pr ec ision of t he voltage sensors is primarily affected by VREF in the
71M6543. The temperature coefficient of the resistors used to implement the voltage dividers for the voltage
sen s ors (see Figure 27) determine the behavior of the voltage division ratio with respect to temperature. It is
recommended to use resistors with low temperature coefficients, while forming the entire voltage divider
using resistors belonging to the same technology family, in order to minimize the temperature dependency of
the voltage division ratio. The resistors must also have suitable voltage ratings.
The Current Transformers are directly connected to the 71M6543 and are therefore primarily affected by the
VREF tem perature dependenc y in the 71M 6543. For best performance, it is recommended to use the
dif fer entia l s ignal condition ing circ u it , as s hown in Figure 29, to connect the CTs to the 71M6543. Current
transformers may also require temperature compensation. The copper w ire winding in the CT has dc
resistance with a temperature coefficient, which makes the voltage delivered to the burden resistor
temperature dependent, and the burden resistor also has a temperature coefficient. Thus, each CT sensor
channel needs to compensate for the 71M6543 VREF, and optionally for the temperature dependency of the
CT and its burden resistor dep en ding on the re qu ir ed accur ac y c las s.
71M6543F/H and 71M6543G /GH Data Sheet
v1.2 © 2008–2011 Teridian Sem iconduc tor Corpor ation 93
The MPU has the responsib ilit y of co mpu t ing the nec es s ary sample gain co mpensation values req uired for
each sensor channel based on the sensed temper ature. T eri dian provides demonstrat ion code that
im plem ents the GAIN_ADJx com pensation equat ion shown bel ow. The resul ting GAIN_ADJx values are
stored by t he MPU in five C E RA M locat ions GAIN_ADJ0-GAIN_ADJ5 (CE RA M 0x40-0x44). The
demonstration code thus provides a suita ble implementat ion of t em per ature compensati on, but other
m ethods are possible in MPU firmw ar e by ut iliz ing th e on-chip temperature sensor while storin g th e s ample
gain adjus t men t res u lts in the CE RA M GAIN_ADJn sto ra ge loc ations. The de monstration code main tains
five separat e sets of PPMC and PPMC2 coeffi ci ents and computes five separat e GAIN_ADJn values
based on the sensed t emper ature using the equat ion below:
23
2
14 22_100
2
_10
16385_ PPMCXTEMPPPMCXTEMP
ADJxGAIN ⋅⋅
+
⋅⋅
+=
The GAIN_ADJn values stor ed by the MPU in CE RAM are used by the CE to gain adjust (i. e., multiply)
the sam ple in each correspondi ng sen sor channel. A GAIN_ADJx value of 16,384 (i.e., 214) c or r espond s to
unity gain, whil e v alues l ess than 16,384 attenuate the sampl es and values greater than 16,384 amplify
the sam ples.
In t he above equ ati on, TEMP_X i s the devi ati on fr om nominal or cali br ation temperat ure expr ess ed in
multipl es of 0.1 °C. The 10x and 100x factor s seen in the above equation are due to 0.1 oC scaling of
TEMP_X. For example, if the calibrat ion (refer enc e) temperat ur e is 22 °C and the measured temper ature
is 27 °C, then 10*TEMP_X = ( 27-22) x 10 = 50 (decimal) , which r epr esents a +5 °C dev iation fr om 22 °C.
In t he dem onstr ation code, TEMP_X is calculated in the MPU from the STEMP[10:0] t em per ature sensor
readi ng usi ng the equation prov ided below and is scaled in 0.1°C unit s. See 2.5.5 71M6543 Temperature
Sensor on page 55 for the equation to ca lculate temperature in °C from the STEMP[10:0] reading.
Table 68 shows the five GAIN_ADJx equation output storage locations and the v oltage or current
m easurement s for which t hey c om pensate.
Table 68: GAI N_ADJx Compensation Ch ann els (Figure 3, Figure 32, Table 2)
Gain Adju st me nt Out put CE RAM Address Sensor Channel(s)
(pin name s) Compensation For:
GAIN_ADJ0 0x40 VADC8 (VA)
VADC9 (VB)
VADC10 (VC)
VREF in 71M6543 and Voltage Divider
Resistors
GAIN_ADJ1 0x41 IADC0-IADC1
VRE F in 71 M 6543 , CT and Burden
Res i st or (Neutral Current)
GAIN_ADJ2 0x42 IADC2-IADC3
VRE F in 71 M 6543, CT and Burden
Res i st or (Phase A)
GAIN_ADJ3 0x43 IADC4-IADC5
VRE F in 71 M 6543, CT and Burden
Res i st or (Phase B)
GAIN_ADJ4 0x44 IADC6-IADC7
VRE F in 71 M 6543, CT and Burden
Res i st or (Phase C)
In t he dem onstr ation code, the shape of the temper ature compensation second-order par abolic curv e is
determ ined by the values stored in the PPMC (1st or der coefficient ) and PPMC2 (2nd order coefficient),
which are t y pically setup by the MP U at initi alization time f r om values that are stor ed in EEPROM.
To disable temperature com pensation in the demonstrat ion code, PPMC and PPMC2 are both set to zero
for each of the five GAIN_ADJx channels. To enable temperature compensation, the PPMC and PPMC2
coefficients are set wit h val ues that match the expect ed VREF temperature variation and optionally the
correspondi ng s ensor circuit (i.e., the CT and burden resistor for curr ent channels or the r esi stor div ider
network for the voltage channels).
In the 71M 6543 F and 7 1M654 3G (±0.5% energy accuracy), the req uire d VREF co mpe ns at ion coefficients
PPMC and PPMC2 are cal culated fr om r eadable on-chip non-vo latile fus es (see 4.5.2Temperature
Coeff icients for the 71M6543F). T hese coeff icients ar e desi gned to achieve ±40 ppm/°C for VREF.
For the 71M6543H and 71M6543GH (±0.1% energ y accur ac y), coeffi ci ents specif ic to each individual
device can be calcu lated from values read from additional on-chip fuses that c har ac terize the VRE F
71M6543F/H and 71M6543G /GH Data Sheet
94 © 2008–2011 Teridian Semiconduct or Cor por ation v1.2
behav ior of each indiv idual part acr oss industrial temper atures (see 4.5.3 Te mperature Coefficients for
the 71M6543H). The resulting t r acking of the reference VREF voltage is within ±10 ppm/°C.
4.6 Connecting I2C EEPROMs
I2C EEPRO Ms or other I2C c om patible devices should be connec ted to t he DIO pi ns SEGDIO2 and
SEGDIO3, as shown in Figure 33.
Pullup resistors of roughly 10 kΩ to V3P3D (t o ensure operation in BRN mode) should be used f or both
SDCK and SDATA signals. The DIO_EEX (I/O RAM 0x2456[7:6]) fie ld must be se t to 01 in ord er to convert
the DI O pins SEGDIO2 and SEGDIO3 to I 2C pins SCL and SDATA.
Figure 33: I2C E EPRO M Conn ection
4.7 Connecting Three-Wire EEPROMs
µWir e E E P ROMs and other c om patible devices should be connec ted to t he DIO pi ns SEGDIO2 and
SEGDIO3, as descri bed in 2.5.11 EEPROM Inter face on page 66.
4.8 UART0 (TX/RX)
The UART0 RX pi n sh ould b e pul led do wn by a 10 kΩ resistor an d addi ti on ally protec ted by a 100 pF
ceram ic capacit or , as shown in Figure 34.
Figure 34: Connec t i ons f or UART0
4.9 Optical Interface (UART1)
The O P T_TX and OP T_RX pins ca n be u sed for a re g ular serial int erf ac e (by con ne ct ing a RS _2 32
transceiver fo r example), or they can be used to di r ectly oper ate optical c om ponents (for example, an
infr ared di od e and ph ototra nsist or implementing a FLA G i nter face). Figure 35 shows the basi c connections
TX
RX
71M6543
10 k
Ω
100 pF
RX
TX
DIO2
DIO3
EEPROM
SDCK
SDATA
V3P3D
10 k
Ω
10 k
Ω
71M6543
71M6543F/H and 71M6543G /GH Data Sheet
v1.2 © 2008–2011 Teridian Sem iconduc tor Corpor ation 95
for UART1. T he OPT_T X pi n bec om es active when the control field OPT_TXE (I/O RAM 0x2456[3:2] ) is
set to 00.
The polarit y of the OPT _TX and OPT_RX pins can be inverted wit h the configur ation bits, OPT_TXINV
(I/O RAM 0x2456[0] ) and OPT_RXINV (I/O RAM 0x2457[1] ), respectively.
The O PT_TX output may be modulated at 38 kHz when system power is present. Modulation is not
ava ilab le in BRN mode. The OPT_TXMOD bit (I/O RAM 0 x245 6[1]) enables modulation . The duty cycle is
contr olled by OPT_FDC[1:0] (I/O RAM 0x2457[5:4]), whic h c an sel ec t 50%, 25%, 12. 5%, and 6. 25% duty
cycle. A 6.25% duty cycl e means OPT _TX is l ow for 6.25% of the peri od. The OPT_RX pi n uses digital
signal thresholds. It may need an anal og filt er when receivi ng modul ated optic al si gnals.
With modulation, an optic al emitter can be operated at higher c ur r ent than nomi nal, enabling it to
inc r ease the distance along the optic al path.
If operation in BRN mode is desired, the external components shoul d be c onnec ted to V3P3D. However,
it is recommended to limit the current t o a few mA.
Figure 35: Connection for Optical Components
4.10 Connecting the Reset Pin
Even though a functional meter does not nec es saril y need a reset swit c h, it is usef ul to have a r eset
pushbutton for prototyping as shown in Figure 36, left side. The RESET signal may be sourced from
V3P3SYS (functional in MSN mode only), V 3P 3D (MSN and BRN modes), or VBAT (all modes, if a battery is
present), or fr om a combinati on of these sources, depe nding on t he applicati on.
For a pr oduc tion meter, the RES ET pin shoul d be pr otected by the by t he exter nal c om ponents
shown in Figure 36, right side. R1 should be in the range of 100Ω and m ounted as closely as possible
to t he IC.
Since the 71M6543 generates its own power-on reset, a reset button or circuitry, as shown in Figure 36, is
only r equired for test units and prot otypes.
OPT_TX
R
2
R
1
OPT_RX
71M6543
V3P3SYS
Phototransistor
LED
10 kΩ
100 pF
V3P3SYS
71M6543F/H and 71M6543G /GH Data Sheet
96 © 2008–2011 Teridian Semiconduct or Cor por ation v1.2
R1
RESET
71M6533
DGND
100Ω
R1
RESET
71M6533
DGND
100Ω
Figure 36: Extern al Components for the RESET Pin: Push-Button (Left), Production Circuit (Right)
4.11 Conne cting the Emulator Port Pins
Even when the emulator is not used, small sh unt c apaci to rs to gro und (22 pF) s hould be u s ed f or protection
from EMI as illustrated in Figure 37. Production boards should have the ICE_E pi n connect ed to ground.
Figure 37: External C omponents for the E mul ator Interface
4.12 Flash Pro gra mming
4.12.1 Flash Programming via the ICE Por t
Operati onal or test code c an be pr ogr ammed into the flash mem or y usi ng either an in-circuit em ul ator or
the Fl ash Progr am mer Module (TF P -2) available fro m Teridian. The flash programming procedur e uses
the E_RS T, E _RXTX, and E _TCLK pins.
4.12.2 Flash Programming via the SPI Port
It is possible to e r ase, r ead and program the flash mem or y of the 71M654 3 via the SP I p or t. See
2.5.12 for a detailed description.
4.13 MPU Demonstration Code
All application-specific MPU f unc tions menti oned in 4 Applic ation Inf ormation are featured in the
dem onstr ati on C source code supplied by Teridian. T he code i s availabl e as part of the Demonstration Kit
for the 71M6543. The Demonstration Kits come w ith the 71M6543 preprogrammed wit h demo nstration
firmware and moun ted on a f unctional s ample meter Dem o Board. The Demo Boards allow for quick and
efficient evaluation of the IC wit hout having to write firmware or hav ing to supply an in-circuit emulat or
(ICE).
E_RST
71M6543
E_TCLK
62
Ω
62 Ω
62 Ω
22 pF
22 pF
22 pF
LCD
Segments
ICE_E
V3P3D
E_RXT
(optional)
R
1
RESET
71M6543
GNDD
V3P3D
R
2
VBAT/
V3P3D
Reset
Switch
1k
Ω
0.1µF
10k
Ω
71M6543
71M6543F/H and 71M6543G /GH Data Sheet
v1.2 © 2008–2011 Teridian Sem iconduc tor Corpor ation 97
4.14 Crystal Oscillator
The osci llat or of the 71M6543 dr ives a standard 32. 768 k Hz watch c r y stal. T he oscillator has been
designed specif i cally to handl e these crystals and is compatible with their hi gh im pedanc e and lim ited
power han dling c apability. The oscillator pow er diss ipation is very low to maximize the lifetime of any
batt er y bac k up dev ic e att ac hed to the VBAT_RT C pin.
Board layout s w ith minimu m capacitance fro m XIN to XOUT require less battery current. Good layouts
hav e XIN and XOUT shielded f r om each ot her and al so keep t he XIN and XOUT t r ac es short and away
from LCD and digital signals.
Since the oscillator is self-bias ing, an e xterna l resistor must not be connected across the crystal.
4.15 Meter Calibration
Once the Teridian 71M6543 energy meter dev ic e has been i nstalled in a met er system , it m ust be
calibrated. A com plete calibration includes the following:
• Establishment of the reference temperature for factory calibration (e.g., typically 22 °C).
• Calibratio n of the metrolo gy secti on, i. e., c alibr ati on for errors of the current sensors, vol tage
div iders and signal conditioning com ponents as well as of the i nternal reference vo ltage (VREF) a t
the reference temper ature (e.g., typically 22 °C).
• Calibrati on of t he oscillator fr equenc y usi ng the RTCA_ADJ register (I/O RAM 0x250 4).
The metrology section can be calibr ated using the gai n and phase adjustment factors accessible to the
CE. The gain adjustment is used to comp ens at e for to leran ces of compo nen ts us ed fo r s ignal co nd it ioning ,
especially the resistive components. Phase adjustment is pro vided to compensate for phase shifts introduced
by the c ur r ent sensors or by t he effects of r eac tive power supplies.
Due to t he flexibilit y of t he MPU firmware, any c alibration met hod, such as calibration based on energy, or
current and voltage can be implemented. It i s al s o poss i ble to im plem e nt s egm e nt-wise c al ib ra t io n
(depending on current range) .
The 71M6543 supports common industry standard cali bration techniques, such as si ngle-point
(energy-only), mu lti-poi nt (ener gy , Vrm s, Irm s), and auto-calibration.
Teridian prov ides a calibrati on spreadsheet file to facilitat e the calibrat ion process. Contact y our Teridian
representative to obtain a copy of the latest calibration spreadsheet file for the 71M6543.
71M6543F/H and 71M6543G /GH Data Sheet
98 © 2008–2011 Teridian Sem iconduc tor Corpor ation v1.2
5 Firmware Interface
5.1 I/O RAM Map –Func tional O r der
In Table 69 and Table 70, unim plem ented (U) and reserved (R) bit s are shaded in light gray. Unimplemented bits are i dentified wit h a ‘U’.
Unim plemented bit s have no mem or y stor age, writi ng them has no effect, and reading them always returns zero. Reserved bits are identif ied wit h
an ‘R’, and must always be writ ten with a zero. Writing values other than zero to reserved bits may have undesirable side effects and must be
av oided. Non-volatile bit s are shaded in dar k gr ay. Non-vol atile bits are backed-up dur ing power failures if the syst em includes a batt er y connect ed
to t he VBAT pin.
The I /O RAM loc ations listed in Table 69 have sequenti al addresses to facilitate reading by the MP U (e.g., in order t o v erify their c ontent s). These
I/ O RAM l oc ations are usually m odified only at boot-up. The addresses shown in Table 69 are an alt er native sequential addr ess to the addr esses
from Table 70 whic h ar e used throughout this document. For instance, EQU[2:0] can be accessed at I/O RAM 0x2000[7:5] or at I/O RAM
0x2106[7:5].
Table 69: I/O RAM M a p – Functional Order, Basic Configuration
Name Addr Bi t 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
CE6 2000 EQU[2:0] U CHOP_E[1:0] RTM_E CE_E
CE5 2001 U SUM_SAMPS[12:8]
CE4 2002 SUM_SAMPS[7:0]
CE3 2003 U
CE_LCTN[6/5:0]
CE2 2004 PLS_MAXWIDTH[7:0]
CE1 2005 PLS_INTERVAL[7:0]
CE0 2006 DIFF6_E DIFF4_E DIFF2_E DIFF0_E RFLY_DIS FIR_LEN[1:0] PLS_INV
RCE0 2007 CHOPR[1:0] RMT6_E RMT4_E RMT2_E TMUXR6[2:0]
RTMUX 2008 U TMUXR4[2:0] U TMUXR2[2:0]
FOVRD 2009 U U R U U U U U
MUX5 200A MUX_DIV[3:0] MUX10_SEL
MUX4 200B MUX9_SEL MUX8_SEL
MUX3 200C MUX7_SEL MUX6_SEL
MUX2 200D MUX5_SEL MUX4_SEL
MUX1 200E MUX3_SEL MUX2_SEL
MUX0 200F MUX1_SEL MUX0_SEL
TEMP 2010 TEMP_BSEL TEMP_PWR OSC_COMP TEMP_BAT TBYTE_BUSY TEMP_PER[2:0]
LCD0 2011 LCD_E LCD_MODE[2:0] LCD_ALLCOM LCD_Y LCD_CLK[1:0]
LCD1 2012 LCD_VMODE[1:0] LCD_BLNKMAP23[5:0]
71M6543F/H and 71M6543G /GH Data Sheet
v1.2 © 2008–2011 Teridian Sem iconduc tor Corpor ation 99
Name Addr Bi t 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
LCD2 2013 LCD_BAT R LCD_BLNKMAP22[5:0]
LCD_MAP6 2014 LCD_MAP[55:48]
LCD_MAP5 2015 LCD_MAP[47:40]
LCD_MAP4 2016 LCD_MAP[39:32]
LCD_MAP3 2017 LCD_MAP[31:24]
LCD_MAP2 2018 LCD_MAP[23:16]
LCD_MAP1 2019 LCD_MAP[15:8]
LCD_MAP0 201A LCD_MAP[7:0]
DIO_R5 201B U U U U U DIO_RPB[2:0]
DIO_R4 201C U DIO_R11[2:0] U DIO_R10[2:0]
DIO_R3 201D U DIO_R9[2:0] U DIO_R8[2:0]
DIO_R2 201E U DIO_R7[2:0] U DIO_R6[2:0]
DIO_R1 201F U DIO_R5[2:0] U DIO_R4[2:0]
DIO_R0 2020 U DIO_R3[2:0] U DIO_R2[2:0]
DIO0 2021 DIO_EEX[1:0] U U OPT_TXE[1:0] OPT_TXMOD OPT_TXINV
DIO1 2022 DIO_PW DIO_PV OPT_FDC[1:0] U OPT_RXDIS OPT_RXINV OPT_BB
DIO2 2023 DIO_PX DIO_PY U U U U U U
INT1_E 2024 EX_EEX EX_XPULSE EX_YPULSE EX_RTCT U EX_RTC1M EX_RTC1S EX_XFER
INT2_E 2025 EX_SPI EX_WPULSE EX_VPULSE
WAKE_E 2026 EW_RX EW_PB EW_DIO4 EW_DIO52 EW_DIO55
SFMM 2080 SFMM[7:0]*
SFMS 2081 SFMS[7:0]*
Notes:
*SFMM and SFMS are acc essible only through the S PI slave port. See 2.5.1.1 Flash Mem ory for details.
71M6543F/H and 71M6543G /GH Data Sheet
100 © 2008–2011 Teridian Semiconductor Corpor ation v1.2
Table 70 lists bi ts and registers that may have to be accessed on a fr equent basis. Reserved bits have lighter gray backgr ound, and non-volatile
bits have a darker gr ay backgr ound.
Table 70: I/O RAM Map – F unc tiona l Or de r
Name Addr Bi t 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
CE and ADC
MUX5 2100
MUX_DIV[3:0]
MUX10_SEL[3:0]
MUX4 2101 MUX9_SEL[3:0] MUX8_SEL[3:0]
MUX3 2102 MUX7_SEL[3:0] MUX6_SEL[3:0]
MUX2 2103 MUX5_SEL[3:0] MUX4_SEL[3:0]
MUX1 2104
MUX3_SEL[3:0]
MUX2_SEL[3:0]
MUX0 2105 MUX1_SEL[3:0] MUX0_SEL[3:0]
CE6 2106 EQU[2:0] U CHOP_E[1:0] RTM_E CE_E
CE5 2107
U
SUM_SAMPS[12:8]
CE4 2108 SUM_SAMPS[7:0]
CE3 2109 U CE_LCTN[6:0] (71M6543G/GH), CE_LCTN[5:0] (71M6543F/H)
CE2 210A
PLS_MAXWIDTH[7:0]
CE1
210B
PLS_INTERVAL[7:0]
CE0
210C
DIFF6_E DIFF4_E DIFF2_E DIFF0_E RFLY_DIS FIR_LEN[1:0] PLS_INV
RTM0 210D
U
U
U
U
U
U
RTM0[9:8]
RTM0
210E
RTM0[7:0]
RTM1
210F
RTM1[7:0]
RTM2 2110 RTM2[7:0]
RTM3 2111
RTM3[7:0]
CLOCK GENERA TION
CKGN
2200
U U ADC_DIV PLL_FAST RESET MPU_DIV[2:0]
VREF TRIM FUSES
TRIMT
2309
TRIMT[7:0]
LCD/DIO
LCD0 2400
LCD_E
LCD_MODE[2:0]
LCD_ALLCOM
LCD_Y
LCD_CLK[1:0]
LCD1 2401
LCD_VMODE[1:0]
LCD_BLNKMAP23[5:0]
LCD2
2402
LCD_BAT R LCD_BLNKMAP22[5:0]
LCD_MAP6 2405
LCD_MAP[55:48]
LCD_MAP5 2406
LCD_MAP[47:40]
LCD_MAP4
2407
LCD_MAP[39:32]
LCD_MAP3
2408
LCD_MAP[31:24]
71M6543F/H and 71M6543G /GH Data Sheet
v1.2 © 2008–2011 Teridian Sem iconduc tor Corpor ation 101
Name Addr Bi t 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
LCD_MAP2 2409 LCD_MAP[23:16]
LCD_MAP1 240A LCD_MAP[15:8]
LCD_MAP0 240B
LCD_MAP[7:0]
LCD4 240C U U U U U LCD_RST LCD_BLANK LCD_ON
LCD_DAC 240D U U U LCD_DAC[4:0]
SEGDIO0 2410
U
U
LCD_SEG0[5:0]
…
…
U
U
…
SEGDIO15
241F
U U LCD_SEG15[5:0]
SEGDIO16 2420
U
U
LCD_SEGDIO 16[5:0]
…
…
U
U
…
SEGDIO45
243D
U U LCD_SEGDIO45[5:0]
SEGDIO46 243E U U LCD_SEG46[5:0]
… …
U
U
…
SEGDIO50
2442
U
U
LCD_SEG50[5:0]
SEGDIO51
2443
U U LCD_SEGDIO51[5:0]
… …
U
U
…
SEGDIO55
2447
U
U
LCD_SEGDIO55[5:0]
DIO_R5 2450
U
R
R
R
U
DIO_RPB[2:0]
DIO_R4 2451
U
DIO_R11[2:0]
U
DIO_R10[2:0]
DIO_R3
2452
U DIO_R9[2:0] U DIO_R8[2:0]
DIO_R2 2453
U
DIO_R7[2:0]
U
DIO_R6[2:0]
DIO_R1 2454
U
DIO_R5[2:0]
U
DIO_R4[2:0]
DIO_R0
2455
U
DIO_R3[2:0]
U
DIO_R2[2:0]
DIO0
2456
DIO_EEX[1:0] U U OPT_TXE[1:0] OPT_TXMOD OPT_TXINV
DIO1 2457
DIO_PW
DIO_PV
OPT_FDC[1:0]
U
OPT_RXDIS
OPT_RXINV
OPT_BB
DIO2 2458
DIO_PX
DIO_PY
U
U
U
U
U
U
NV BITS
SPARENV 2500
U
U
U
U
R
FOVRD 2501
U
U
R
U
U
U
U
U
TMUX
2502
U U TMUX[5:0]
TMUX2 2503 U U U TMUX2[4:0]
RTC1 2504
U
RTCA_ADJ[6:0]
71M6xx3 Interface
71M6543F/H and 71M6543G /GH Data Sheet
102 © 2008–2011 Teridian Semiconductor Corpor ation v1.2
Name Addr Bi t 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
REMOTE2 2602 RMT_RD[15:8]
REMOTE1 2603 RMT_RD[7:0]
RBITS
INT1_E 2700
EX_EEX
EX_XPULSE
EX_YPULSE
EX_RTCT
U
EX_RTC1M
EX_RTC1S
EX_XFER
INT2_E 2701 EX_SPI EX_WPULSE EX_VPULSE U U U U U
SECURE 2702 FLSH_UNLOCK[3:0] R FLSH_RDE FLSH_WRE R
Analog0 2704
VREF_CAL
VREF_DIS
PRE_E
ADC_E
BCURR
SPARE[2:0]
VERSION 2706 VERSION[7:0]
INTBITS 2707 U INT6 INT5 INT4 INT3 INT2 INT1 INT0
FLAG0 SFR E8
IE_EEX
IE_XPULSE
IE_YPULSE
IE_RTCT
U
IE_RTC1M
IE_RTC1S
IE_XFER
FLAG1 SFR F8
IE_SPI
IE_WPULSE
IE_VPULSE
U
U
U
U
PB_STATE
STAT SFR F9
U U U PLL_OK U VSTAT[2:0]
REMOTE0 S FR FC
U
PERR_RD
PERR_WR
RCMD[4:0]
SPI1 SFR FD
SPI_CMD[7:0]
SPI0 2708 SPI_STAT[7:0]
RCE0 2709
CHOPR[1:0]
RMT6_E
RMT4_E
RMT2_E
TMUXR6[2:0]
RTMUX 270A
U
TMUXR4[2:0]
U
TMUXR2[2:0]
INFO_PG 270B U U U U U U U INFO_PG
DIO3 270C
U
U
PORT_E
SPI_E
SPI_SAFE
U
U
U
NV RAM and RTC
NVRAMxx 2800-
287F NVRAM[0] – NVRAM[7F] – Direct Access
WAKE 2880 WAKE_TMR[7:0]
STEMP1 2881 STEMP[10:3]
STEMP0 2882 STEMP[2:0] U U U U U
BSENSE 2885 BSENSE[7:0]
LKPADDR 2887 LKPAUTOI LKPADDR[6:0]
LKPDATA 2888 LKPDAT[7:0]
LKPCTRL 2889 U U U U U U LKP_RD LKP_WR
RTC0 2890 RTC_WR RTC_RD U RTC_FAIL U U U U
RTC2 2892 RTC_SBSC[7:0]
RTC3 2893 U U RTC_SEC[5:0]
RTC4 2894 U U RTC_MIN[5:0]
71M6543F/H and 71M6543G /GH Data Sheet
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Name Addr Bi t 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
RTC5 2895 U U U RTC_HR[4:0]
RTC6 2896 U U U U U RTC_DAY[2:0]
RTC7 2897 U U U RTC_DATE[4:0]
RTC8 2898 U U U U RTC_MO[3:0]
RTC9 2899 RTC_YR[7:0]
RTC10 289B U U U U U RTC_P[16:14]
RTC11 289C RTC_P[13:6]
RTC12 289D RTC_P[5:0] RTC_Q[1:0]
RTC13 289E U U RTC_TMIN[5:0]
RTC14 289F U U U RTC_THR[4:0]
TEMP 28A0 TEMP_BSEL TEMP_PWR OSC_COMP TEMP_BAT TBYTE_BUSY TEMP_PER[2:0]
WF1 28B0 WF_CSTART WF_RST WF_RSTBIT WF_OVF WF_ERST WF_BADVDD U U
WF2 28B1 U U WF_TMR WF_RX WF_PB WF_DIO4 WF_DIO52 WF_DIO55
MISC 28B2 SLEEP LCD_ONLY WAKE_ARM U U U U U
WAKE_E 28B3 U U U EW_RX EW_PB EW_DIO4 EW_DIO52 EW_DIO55
WDRST 28B4 WD_RST TEMP_START U U U U U U
MPU PORTS
PORT3 SFR B0
DIO_DIR[15:12] DIO[15:12]
PORT2 SFR A0
DIO_DIR[11:8] DIO[11:8]
PORT1 SFR 90
DIO_DIR[7:4] DIO[7:4]
PORT0 SFR 80
DIO_DIR[3:0] DIO[3:0]
FLASH
ERASE SF R 94
FLSH_ERASE[7:0]
FLSHCTL SFR B2
PREBOOT SECURE U U FLSH_PEND FLSH_PSTWR FLSH_MEEN FLSH_PWE
FL_BANK SFR B6
U U U U U U FL_BANK[1:0]
PGADR SFR B7
FLSH_PGADR[5:0] U U
I
2
C
EEDATA SFR 9E
EEDATA[7:0]
EECTRL SF R 9F
EECTRL[7:0]
71M6543F/H and 71M6543G /GH Data Sheet
104 © 2008–2011 Teridian Semiconductor Corpor ation v1.2
5.2 I/O RAM Map – Alphabetical Order
Table 71 lists I/O RAM bits and registers i n alphabeti c al order.
B its wit h a write direction (W i n column Dir ) ar e wri tt en by the M P U into configurati on RA M. Typic ally , they are initi ally st or ed in flash memor y and
copi ed to the configur ation RAM by the MPU. Some of the more frequently programmed bits are mapped to the MPU SFR m em ory space. The
remai ning bits ar e mappe d to the addre s s space 0x2 X X X. Bit s wit h R (read) dir ection can be read by the MP U. C olumn s l abeled R st and Wk
describe the bit v alues upon reset and wake, respectiv ely. No ent ry in one of these columns means the bit is either read-only or is power ed by the
NV supply and is not initi alized. Write-only bits return zero when they ar e r ead.
Locations that ar e shaded i n gr ey ar e non-volatile ( i.e., batte ry -backed).
Table 71: I/O RAM Map – Alphabetical Order
Name Location Rst
Wk
Dir Description
ADC_E
2704[4]
0
0
R/W
Enabl es ADC and VRE F. When disabled, reduces bi as curr ent .
ADC_DIV 2200[5] 0 0 R/W
ADC_DIV controls the rate of the ADC and FIR clocks.
The ADC_DIV setting det ermines whether MCK is divided by 4 or 8:
0 = MCK/4
1 = MCK/8
The resul ting ADC and FIR cl oc k is as shown below.
PLL_FA S T = 0 PLL_FAS T = 1
MCK 6. 291456 M Hz 19.660800 MHz
ADC_DIV = 0 1.572864 MHz 4. 9152 M Hz
ADC_DIV = 1 0.786432 MHz 2. 4576 M Hz
BCURR
2704[3]
0
0
R/W
Connects a 100 µA load to the battery sel ec ted by TEMP_BSEL.
BSENSE[7:0] 2885[7:0] – – R
The resul t of the batter y measurem ent.
See 2.5.7 71M6543 Battery Monitor on page 57.
CE_E
2106[0]
0
0
R/W
CE enabl e.
CE_LCTN[6:0] 2109[6:0] 31 31 R/W
CE program loc ation. The starting address for the CE program is 1024*CE_LCTN.
(CE_LCTN[6:0], 2109[ 6:0] for 71M6543G, 71M6543GH)
(CE_LCTN[5:0], 2109[ 5:0] for 71M6543F, 71M6543H)
CHIP_ID[15:8]
CHIP_ID[7:0] 2300[7:0]
2301[7:0] 0
0 0
0 R
R
These bytes cont ain t he chip identification as shown below.
CHIP_ID[15:8]
CHIP_ID[7:0]
71M6543F
0x04
0x10
71M6543H
0x04
0x11
71M6543G
0x05
0x10
71M6543GH
0x05
0x11
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CHOP_E[1:0] 2106[3:2] 0 0 R/W
Chop enable for t he refer enc e bandgap c ircuit. The value of CHO P changes on the
ri si ng edge of the internal MUXSYNC signal according to the va lue in CHOP_E[1:0]:
00 = toggle1 01 = positive 10 = rev er sed 11 = toggle
1
ex c ept at the mux sync edge at the end of an accu mulation interval.
CHOPR[1:0] 2709[7:6] 00 00 R/W
The CHO P settings for the rem ote sensor.
00 = A uto chop. Change every MUX frame.
01 = Positive
10 = Negative
11 = A uto chop ( sam e as 00)
DIFF0_E
210C[4]
0
0
R/W
Enables IADC0-IADC1 dif ferential c onfigurat ion.
DIFF2_E
210C[5]
0
0
R/W
Enables IADC2-IADC3 dif ferential c onfigurat ion.
DIFF4_E
210C[6]
0
0
R/W
Enables IADC4-IADC5 dif ferential c onfigurat ion.
DIFF6_E
210C[7]
0
0
R/W
Enables IADC6-IADC7 dif ferential c onfigurat ion.
DIO_R2[2:0]
DIO_R3[2:0]
DIO_R4[2:0]
DIO_R5[2:0]
DIO_R6[2:0]
DIO_R7[2:0]
DIO_R8[2:0]
DIO_R9[2:0]
DIO_R10[2:0]
DIO_R11[2:0]
DIO_RPB[2:0]
2455[2:0]
2455[6:4]
2454[2:0]
2454[6:4]
2453[2:0]
2453[6:4]
2452[2:0]
2452[6:4]
2451[2:0]
2451[6:4]
2450[2:0]
0
0
0
0
0
0
0
0
0
0
0
– R/W
Connects PB and dedicated I/O pi ns DIO2 t hr ough DIO11 to internal resources. If more
than one input is connected to the same resource, the MULTIPLE column below specif ies
how they are combined.
DIO_Rx
Resource
MULTIPLE
0 NONE –
1 Reserved OR
2
T0 (Timer0 clock or gate)
OR
3 T 1 ( Timer1 clock or gate) OR
4 IO interrupt (int0) OR
5
IO interrupt (int1)
OR
DIO_DIR[15:12]
DIO_DIR[11:8]
DIO_DIR[7:4]
DIO_DIR[3:0]
SFR B 0[7: 4]
SFR A 0[7: 4]
SFR 90[7:4]
SFR 80[7:4]
F F R/W
Programs the dir ec tion of the first 16 DIO pins. 1 indic ates output . I gnor ed if the pin is
not configured as I/ O. See DIO_PV and DIO_PW for special option for DIO0 and DIO1
output s. S ee DIO_EEX[1:0] for special opti on f or SEGDIO2 and SEGDIO3. Note that
the direction of DIO pins above 15 is set by SEGDIOx[1]. See PORT_E t o avoid power-
up spikes.
DIO[15:12]
DIO[11:8]
DIO[7:4]
DIO[3:0]
SFR B 0[3: 0]
SFR A 0[3: 0]
SFR 90[3:0]
SFR 80[3:0]
F F R/W
The value on the fir st 16 DIO pi ns. Pins configured as LCD read zero. When written,
changes data on pi ns configured as outputs. Pins confi gured as LCD or input ignore
wr ites. N ote t hat the data f or DIO pin s ab ove 1 5 is s et by SEGDIOx[0].
71M6543F/H and 71M6543G /GH Data Sheet
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Dir Description
DIO_EEX[1:0] 2456[7:6] 0 – R/W
When set, c onv er ts SEGDIO3 and SEGDIO2 to interface with e xternal EEPROM.
SEG DIO 2 bec om es SDCK and SEG DIO 3 bec om es bi-di r ec tional SDATA, but only if
LCD_MAP[2] and LCD_MAP[3] are cleared.
DIO_EEX[1:0] Function
00 Disable EEPROM interface
01 2-Wire EEPROM interface
10 3-Wire EEPROM interface
11 3-Wire E E P ROM interface with separate DO ( SEGDIO3) and DI
(SEGDIO8) pins.
DIO_PV
2457[6]
0
–
R/W
Causes VPULSE to be output on SEGDIO1, if LCD_MAP[1]=0.
DIO_PW
2457[7]
0
–
R/W
Causes WPULSE to be output on SEGDIO0, if LCD_MAP[0]=0.
DIO_PX
2458[7]
0
–
R/W
Causes XPULSE to be output on SEGDIO6 , if LCD_MAP[6]=0.
DIO_PY
2458[6]
0
–
R/W
Causes YPULSE to be output on SEGDIO7 , if LCD_MAP[7]=0.
EEDATA[7:0]
SFR 9E
0
0
R/W
Serial EEPROM interface data.
EECTRL[7:0] SFR 9F 0 0 R/W
Serial EEPROM interface control.
Status
Bit Name Read/
Write Reset
State Polarity Description
7 ERROR R 0 Positive 1 when an illegal command is received.
6 BUSY R 0 Positive 1 when serial data bus is busy.
5 RX_ACK R 1 Positive 1 indicat es that t he E E P ROM sent an
ACK bit .
EQU[2:0] 2106[7:5] 0 0 R/W
Specif ies the power equation.
EQU[2:0] Description
Element
0
Element
1
Element
2
Recommended
MUX Sequ ence
3
2 elem ent, 4W,
3
φ
Dela
VA(I-IB)/ 0 VC IC IA VA IB B C VC
4
2 elem ent, 4W,
3
φ
Wye
VA(IA-IB)/2 VB(IC-IB)/2 0 IA VA IB V I VC
5*
3 elem ent, 4W,
3
φ
ye
VA IA VB IB VC C IA A IBVB ICV
Note:
*T he avai lab l e CE c od es im plem en t s onl y equation 5. Contact your local Teridian representative to obtain
CE code f or equati on 3 an d 4.
71M6543F/H and 71M6543G /GH Data Sheet
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EX_XFER
EX_RTC1S
EX_RTC1M
EX_RTCT
EX_SPI
EX_EEX
EX_XPULSE
EX_YPULSE
EX_WPULSE
EX_VPULSE
2700[0]
2700[1]
2700[2]
2700[3]
2701[7]
2700[7]
2700[6]
2700[5]
2701[6]
2701[5]
0 0 R/W
Int er r upt enabl e bits. These bit s enabl e the XFER_BUSY, the RT C_1S E C, et c. The
bits are set by hardware and cannot be set by wri ti ng a 1. The bit s are reset by wri ting
0. Not e that if one of these i nterrupts is to enabled, its corr espondi ng 805 1 EX enable
bit must also be s et. See 2.4.9 Interrupts, for details.
EW_DIO4 28B3[2] 0 – R/W
Connects SEGDIO4 to the WA K E l ogic and permits SEGDIO4 rising to wake the part.
This bit has no effect unless DIO4 is configur ed as a digi tal input.
EW_DIO52 28B3[1] 0 – R/W
Connects SEGDIO52 to the WAKE logic and permits SEGDIO52 ri si ng to wake the part.
This bit has no effect unless SEGDIO52 is conf igured as a digi tal input.
EW_DIO55 28B3[0] 0 – R/W
Connects SEGDIO55 to the WAKE logic and permits the SEGDIO55 rising edge to
awaken the par t. This bit has no effect unless SEGDIO55 i s conf igured as a digital
input.
EW_PB 28B3[3] 0 – R/W
Connects PB to the WAKE logic and permits the PB rising edge to awaken the par t. PB
is al ways confi gur ed as an input.
EW_RX 28B3[4] 0 – R/W
Connects RX to the WAKE logi c and permits the RX rising edge to awaken the part .
See the WAKE description in 3.4 Wake on Time r for de-bounce i ssues.
FIR_LEN[1:0] 210C[2:1] 0 0 R/W
Determ ines the num ber of ADC cycles i n the ADC decima tion FIR filter.
PLL_FAST = 1:
FIR_LEN[1:0]
ADC Cycles
00
141
01
288
10
384
PLL_FAST = 0:
FIR_LEN[1:0]
ADC Cycles
00
135
01
276
10
Not Allowed
The ADC LS B size and full-scale v alues depend on the FIR_LEN[1:0] setting. Refer to
Table 83 on page 126 and Table 105 on page 144 for details.
71M6543F/H and 71M6543G /GH Data Sheet
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Name Location Rst
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Dir Description
FL_BANK[1:0] SFR B6[1:0]
01 01 R/W
Flash Bank Selection (71M6543G and 71M 6543GH only)
The progr am m em or y of the 71M6543G/GH consists of a fix ed lower bank of 32 K B,
addressable at 0x 0000 to 0x7F FF plus an upper banked ar ea of 32 KB, addressable at
0x 8000 to 0xFFFF. The I/O RAM register FL_BANK i s used to swit c h one of four
m em ory banks of 32 K B each int o the addres s range from 0x8000 to 0xFFFF. Note t hat
when FL_BANK = 0, the upper bank is the same as the lower bank.
FL_BANK[1:0]
Address Range for Lower Bank
(0x0000-0x7FFF)
Address Range for Upper B ank
(0x8000-0xFFFF)
00
0x0000-0x7FFF
0x0000-0x7FFF
01
0x0000-0x7FFF
0x8000-0xFFFF
10
0x0000-0x7FFF
0x10000-0x17FFF
11
0x0000-0x7FFF
0x18000-0x1FFFF
FLSH_ERASE[7:0] SFR 94[7:0]
0 0 W
Flash Erase Initiate
FLSH_ERASE i s used to i nitiate either the Fl ash Mass Erase cyc le or the Fl ash Page
Erase cycle. Specific patter ns are expec ted for FLSH_ERASE in or der to initiate the
appropriate E r ase cycl e. (de fault = 0x00).
0x55 – Initiat e Flash Page Erase cyc le. Must be proceeded by a writ e to
FLSH_PGADR[5:0] (SFR 0xB7 ).
0xAA – Init iate Flash Mass Erase cyc le. Must be proc eeded by a writ e to
FLSH_MEEN (SFR 0 xB2 ) and the debug ( CC) por t must be enabled.
Any ot her patt er n wri tten to
FLSH_ERASE
has no effect.
FLSH_MEEN SFR B2[1] 0 0 W
Mass Erase Enabl e
0 = Mass Eras e disabled ( default).
1 = Mass Eras e enabled.
Must be re-writt en for each new Mass Erase cycl e.
FLSH_PEND SFR B 2[3] 0 0 R
Indicat es that a posted f lash write is pendi ng. If another flash writ e is att em pted, it is
ignored.
FLSH_PGADR[5:0] SFR B7[7: 2]
0 0 W
Flash Page Erase Address
Flash Page Address (page 0 thru 63) that is erased during the Page Erase cycle.
(default = 0x00).
Must be re-writt en for each new Page E rase cycle.
FLSH_PSTWR SFR B 2[2] 0 0 R/W
Enabl es posted flash wri tes. When 1, and if CE_E = 1, fl ash writ e r equests are stored in
a one elem ent deep FIFO and are executed when CE_BUSY f alls. FLSH_PEND can be
read to determine the status of the FIFO. If FLSH_PSTWR = 0 or if CE_E = 0, flash writes
are immediat e.
71M6543F/H and 71M6543G /GH Data Sheet
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FLSH_PWE SFR B2[0] 0 0 R/W
Program Write Enable
0 = MOVX commands refer to External RAM Space, normal operation (default).
1 = MOVX @DPTR,A moves A to External Program Space (Fl ash) @ DPTR.
This bit is automati c ally reset after each byte writt en to fl ash. Writes to this bit ar e
inhibit ed when interrupts are enabled.
FLSH_RDE
2702[2]
–
–
R
Indicates that the flash may be read by ICE or SPI slave. FLSH_RDE = (!SECURE)
FLSH_UNLOCK[3:0] 2702[7:4] 0 0 R/W
Mu st be a 2 to e nabl e any flash modi fication. See th e de s c r ipt io n of F lash security for
m or e details.
FLSH_WRE
2702[1]
–
–
R
Indicat es that t he flash m ay be written through ICE or SPI slav e por ts.
IE_XFER
IE_RTC1S
IE_RTC1M
IE_RTCT
IE_SPI
IE_EEX
IE_XPULSE
IE_YPULSE
IE_WPULSE
IE_VPULSE
SFR E 8[0]
SFR E 8[1]
SFR E 8[2]
SFR E 8[3]
SFR F8[7]
SFR E 8[7]
SFR E 8[6]
SFR E 8[5]
SFR F8[4]
SFR F8[3]
0 0 R/W
Interrupt flags for ex ternal interrupts 2 and 6. These flags monitor the source of the int 6
and int2 interrupts (ext er nal interrupts to the MPU c or e). These flags are set by
hardware and must be clear ed by the software i nterr upt handler. The IEX2 (SFR
0xC0[1]) and IEX6 (SFR 0xC0[5]) interrupt flags are automatic ally cl ear ed by the MP U
core when it v ec tors to the interr upt handler. IEX2 and IEX6 must be cl ear ed by wri ting
zero t o their corresponding bit posi tions in SFR 0xC0, while writing ones to the other bit
positions that ar e not being cleared.
INTBITS 2707[6:0] – – R
Int err upt in puts . The MP U may read these bits to se e t he in put to extern al interrupts
INT 0, I NT1, up to INT6. These bits do not have any memory and are primari ly i ntended
for debug use.
LCD_ALLCOM
2400[3]
0
–
R/W
Configures SEG /COM bits as COM. Has no eff ec t on pins who se LCD_MAP bit is zero.
LCD_BAT
2402[7]
0
–
R/W
Connects the LCD power suppl y to VBAT in all m odes.
LCD_BLNKMAP23[5:0]
LCD_BLNKMAP22[5:0]
2401[5:0]
2402[5:0]
0 – R/W
Ident ifi es which segm ents connected to SEG23 and SEG 22 shoul d blink. 1 means
blink. The mos t significant bit corresponds to COM5, the least significant, to COM0.
LCD_CLK[1:0] 2400[1:0] 0 – R/W
Sets the LCD cl oc k frequenc y . Note: f
XTAL
= 32768 Hz
LCD_CLK[1:0]
LCD Clock Frequency
00
f
XTAL
/29
01
f
XTAL
/28
10
f
XTAL
/27
11
f
XTAL
/26
71M6543F/H and 71M6543G /GH Data Sheet
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Dir Description
LCD_DAC[4:0] 240D[4:0] 0 – R/W
The LCD contrast DAC. This DAC controls the VLCD voltage and has an output r ange of
2.65 V to 5.3 V. The VLCD voltage is
VLCD = 2.65 + 2.65 * LCD_DAC[4:0]/31
Thus, t he LS B of the DAC is 85.5 mV . The maximum DAC output vo ltage is limited by
V3P3SY S , VB AT, and whether LCD_BSTE = 1.
LCD_E 2400[7] 0 – R/W
Enabl es the LCD display . When di sabl ed, VLC2, VLC1, and VLC0 are gr ound as are
the CO M and SEG outputs if thei r LCD_MAP bit is 1.
LCD_MAP[55:48]
LCD_MAP[47:40]
LCD_MAP[39:32]
LCD_MAP[31:24]
LCD_MAP[23:16]
LCD_MAP[15:8]
LCD_MAP[7:0]
2405[7:0]
2406[7:0]
2407[7:0]
2408[7:0]
2409[7:0]
240A[7:0]
240B[7:0]
0
0
0
0
0
0
0
–
–
–
–
–
–
–
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Enabl es LCD segment driver mode of combined SEGDIO pins. Pi ns that cannot be
configured as outputs (SEG 48 through S E G50) become inputs with int er nal pull ups
when their LCD_MAP bit i s zero. Also, note that SEG48 through SEG50 ar e m ultipl ex ed
with the in-cir c uit emulator signals. When the ICE _E pin i s hi gh, t he ICE interf ace is
enabled, and SEG48 t hr ough S EG50 bec om e E _RXTX, E _TCLK and E_RST,
respectively.
LCD_MODE[2:0] 2400[6:4] 0 – R/W
Sel ec ts the LCD bias and m ulti plex m ode.
LCD_MODE
Output
000 4 states, 1/3 bias
001 3 states, 1/3 bias
010
2 states, 1/2 bias
011 3 states, 1/2 bias
100
Static display
101
5 states, 1/ 3 bias
110 6 states, 1/3 bias
LCD_ON
LCD_BLANK
240C[0]
240C[1]
0
0
–
–
R/W
R/W
Turns on or off all LCD segm ents wi thout c hanging LCD data. If both bits are set , t he
LCD displ ay is turned on.
LCD_ONLY 28B2[6] 0 0 W
Puts the 71M6543 to sleep, but w ith LCD display still active. Ignored if system power is
present. It awakens when the Wak e T imer times out, when certain DIO pins are raised,
or when system power ret ur ns (see 3.2 Battery Modes).
LCD_RST 240C[2] 0 – R/W
Clear all bits of LCD data. These bit s affect SEGDIO pins that are c onfigured as LCD
drivers. Thi s bit does not auto clear.
LCD_SEG0[5:0]
to
LCD_SEG15[5:0]
2410[5: 0] to
241F[5:0] 0 – R/W SEG Data f or SEG0 t hr ough SEG 15. DIO data for these pi ns i s i n SFR space.
LCD_SEGDIO16[5:0]
to
LCD_SEGDIO45[5:0]
2420[5:0] to
243D[5:0] 0 – R/W SEG and DIO data for SEGDIO16 through SEGDIO45. If configur ed as DIO, bit 1 i s
dir ec tion (1 is output, 0 is input), bit 0 is data, an d th e other bi ts are i gnored.
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LCD_SEG46[5:0]
to
LCD_SEG50[5:0]
243E[5:0]
to 2442[ 5:0]
0 – R/W S E G data for SEG46 thr ough S EG50. T hese pi ns cannot be c onfigured as DIO.
LCD_SEGDIO51[5:0]
to
LCD_SEGDIO55[5:0]
2443[5:0] to
2447[5:0] 0 – R/W SEG and DIO data for SEGDIO51 through SEGDIO55. If configur ed as DIO, bit 1 is
dir ec tion (1 is output, 0 is input), bit 0 is data, an d the ot her bi ts are i gnored.
LCD_VMODE[1:0] 2401[7:6] 00 00 R/W
Specif ies how VLCD is generated. S ee 2.5.10.3 for the definiti on of V3P 3L.
LCD_VMODE Description
11 Ext er nal V LCD
10 LCD boost and LCD DAC enabl ed
01 LCD DAC enabl ed
00 No boost and no DAC. VLCD=V3P3L.
LCD_Y 2400[2] 0 – R/W
LCD Blink Frequency (i gnor ed if bli nk i s disabled).
1 = 1 Hz, 0 = 0.5 Hz
LKPADDR[6:0]
2887[6:0]
0
0
R/W
The addres s for readi ng and wri ting the RTC lookup RAM.
LKPAUTOI 2887[7] 0 0 R/W
Auto-incr em ent fl ag. When set, LKPADDR[6:0] auto in cremen ts ever y tim e LKP_RD or
LKP_WR is pulsed. The increm ented addres s can be read at LKPADDR.
LKPDAT[7:0]
2888[7:0]
0
0
R/W
The dat a for reading and wri ting the RTC lookup RAM.
LKP_RD
LKP_WR 2889[1]
2889[0] 0
0 0
0 R/W
R/W
Str obe bits for the RTC look up RA M read and write. W hen set, the LKPADDR[6:0] and
LKPDAT registers is used in a read or wri te operati on. W hen a strobe i s set, it stays set
until the operation com pletes, at whi c h time the strobe is cleared and LKPADDR[6:0] is
incremented if LKPAUTOI is se t.
MPU_DIV[2:0] 2200[2:0] 0 0 R/W
MPU clock rate is:
MPU Rat e = MCK Rat e * 2-(2+MPU_DIV[2:0]).
The maximum value for MPU_DIV[2:0] is 4. Based on the default values of the PLL_FAST
bit and MPU_DIV[2:0], the power-up MPU rate is 6.29 MHz / 4 = 1.5725 MHz. The
mi nim um MPU cloc k rat e is 38.4 k Hz when PLL_FAST = 1.
MUX0_SEL[3:0]
2105[3:0]
0
0
R/W
Sel ec ts whic h A DC input is to be converted dur ing time sl ot 0.
MUX1_SEL[3:0]
2105[7:4]
0
0
R/W
Selects w hich ADC input is t o be converted during time slot 1.
MUX2_SEL[3:0]
2104[3:0]
0
0
R/W
Sel ec ts whic h A DC input is to be converted dur ing time sl ot 2.
MUX3_SEL[3:0]
2104[7:4]
0
0
R/W
Sel ec ts whic h A DC input is to be converted dur ing time sl ot 3.
MUX4_SEL[3:0]
2103[3:0]
0
0
R/W
Sel ec ts whic h A DC input is to be converted dur ing time sl ot 4.
MUX5_SEL[3:0]
2103[7:4]
0
0
R/W
Sel ec ts whic h A DC input is to be converted dur ing time sl ot 5.
MUX6_SEL[3:0]
2102[3:0]
0
0
R/W
Sel ec ts whic h A DC input is to be converted dur ing time sl ot 6.
MUX7_SEL[3:0]
2102[7:4]
0
0
R/W
Sel ec ts whic h A DC input is to be converted dur ing time sl ot 7.
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MUX8_SEL[3:0]
2101[3:0]
0
0
R/W
Sel ec ts whic h A DC input is to be converted dur ing time sl ot 8.
MUX9_SEL[3:0]
2101[7:4]
0
0
R/W
Selects w hich ADC input is t o be converted during time slot 9.
MUX10_SEL[3:0]
2100[3:0]
0
0
R/W
Sel ec ts whic h A DC input is to be converted dur ing time sl ot 10.
MUX_DIV[3:0] 2100[7:4] 0 0 R/W
MUX_DIV[3:0] is the number of ADC time sl ots in each MUX frame. The maximum
num ber of time slots is 11.
OPT_BB 2457[0] 0 – R/W
Configures the input of the opt ical port to be a DIO pi n to allow it to b e
bit-banged. In t his case, DI O5 becom es a third high speed UART. Refe r to 2.5.9 UART
and Opti c al Interfac e =under the “Bit Banged Optical UART (Third UART)” sub-
heading on page 57.
OPT_FDC[1:0] 2457[5:4] 0 – R/W
Sel ec ts OPT_TX modulati on duty cycle
OPT_FDC Function
00 50% Low
01 25% Low
10 12.5% Low
11 6.25% Low
OPT_RXDIS 2457[2] 0 – R/W
OPT_RX can be configur ed as an i nput t o the opti c al UART or as SEGDIO55.
OPT_RXDIS = 0 and LCD_MAP[55] = 0: OPT_RX
OPT_RXDIS = 1 and LCD_MAP[55] = 0: DIO55
OPT_RXDIS = 0 and LCD_MAP[55] = 1: SEG55
OPT_RXDIS = 1 and LCD_MAP[55] = 1: SEG55
OPT_RXINV 2457[1] 0 – R/W
Inverts result from OPT_RX comparat or when 1. Affects only the UART input. Has no
eff ec t when OPT _RX i s used as a DIO i nput.
OPT_TXE [1,0 ] 2456[3:2] 00 – R/W
Configures the O PT_TX output pin.
If LCD_MAP[51] = 0:
00 = DIO51, 01 = OPT_TX, 10 = WPULSE, 11 = VPULSE
If LCD_MAP[51] = 1:
xx = SEG51
OPT_TXINV
2456[0]
0
–
R/W
Invert OPT_TX when 1. This inv er si on oc c ur s befor e m odulation.
OPT_TXMOD 2456[1] 0 – R/W
Enables modul ation of OPT_TX. When OPT_TXMOD is set, OPT_TX is modulated
when it wou ld otherwise have been zero. The modulation is applied after any invers ion
caused by OPT_TXINV.
OSC_COMP 28A0[5] 0 – R/W
Enables the auto ma tic upda te o f RTC_P[16:0] and RTC_Q [1:0]every time the temperature
is measured.
PB_STATE
SFR F8[0]
0
0
R
The de-bounced state of the PB pin.
PERR_RD
PERR_WR
SFR FC[6]
SFR FC[5]
0 0 R/W
The 71M6543 sets these bi ts to indic ate t hat a parity error on the remote sensor has
been detected. Once set, the bits are remembered until they are clear ed by the MP U.
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PLL_OK
SFR F9[4]
0
0
R
Indicat es that t he cl oc k generat ion PLL is settled.
PLL_FAST 2200[4] 0 0 R/W Cont r ols the speed of the PLL and M CK.
1 = 19.66 MHz (XTAL * 600)
0 = 6.29 MHz (XTAL * 192)
PLS_MAXWIDTH[7:0] 210A[7:0] FF FF
R/W
PLS_MAXWIDTH[7:0] determi nes the m aximum widt h of t he pulse (low-goi ng pulse if
PLS_INV=0 or high-going pul se if PLS_INV=1). The maxim um pul se width is
(2*PLS_MAXWIDTH[7:0] + 1)*TI. Where TI is PLS_INTERVAL[7:0] i n u nits of CK _F I R
cl ock cy cl es. If PLS_INTERVAL[7:0] = 0 or PLS_MAXWIDTH[7:0] = 255, no pulse
width checking is performed and the out put pulses have 50% dut y c y cl e. See 2.3.6.2
VPULSE and WPULSE.
PLS_INTERVAL[7:0] 210B[7:0] 0 0 R/W
PLS_INTERVAL[7:0] determines the interva l time between pulses. The time between
output pulses is PLS_INTERVAL[7:0]*4 in units of CK_FIR clock cycles. If
PLS_INTERVAL[7:0] = 0, the FIFO is not used and pulses are output as soon as the CE
issues them. PLS_INTERVAL[7:0] is calculated as follows:
PLS_INTERVAL[7:0] = Fl oor ( Mu x frame duration in CK_FIR cy cl es / CE pulse updat es per Mux
frame / 4 )
For example, since the 71M6543 CE code is written to generate 6 pulses in one integration
interval, when the FIFO is enabled (i.e., PLS_INTERVAL[7:0] ≠ 0) and that the frame
duration is 1950 CK_FIR clock cycles, PLS_INTERVAL[7:0] should be written with
Floor(1950 / 6 / 4) = 81 so that the five pulses are evenly spaced in time over the
integration interval and the last pulse is i ssued just prior to the end of the interval. See
2.3.6.2 VPULSE and WPULSE.
PLS_INV 210C[0] 0 0 R/W
Inverts the polarity of WPULSE and VARPULSE . Norm ally , t hese pul ses are active low.
When inverted, they bec om e active high. PLS_INV has no effect on XPULSE or
YPULSE.
PORT_E 270C[5] 0 0 R/W
Enables outputs from the SEGDIO0-SEGDIO15 pins . PORT_E = 0 blocks the momentary
output pulse that occurs when SEGDIO0-SEGDIO15 are reset on power-up.
PRE_E
2704[5]
0
0
R/W
Enabl es the 8x pr e-amplifier.
PREBOOT
SFRB2[7]
–
–
R
Indicat es that pre-boot sequence is active.
RCMD[4:0]
SFR FC [4 :0]
0 0 R/W
When the MPU wri tes a non-zero va lue to RCMD, the 71M6543 issues a command to
the appropr iat e r em ote sensor. When the command is com plete, the 71M6543 clears
RCMD.
RESET
2200[3]
0
0
W
When set, wri tes a one to WF_RSTBIT and then causes a reset.
RFLY_DIS 210C[3] 0 0 R/W
Controls how the 71M6543 drives the power pul se for the 71M6x x x . When set, the
power pul se i s driven high and low. When clear ed, it i s driven high f ollowed by an open
circuit fly-back interval.
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RMT2_E
RMT4_E
RMT6_E
2709[3]
2709[4]
2709[5]
0 0 R/W E nables the rem ote interface.
RMT_RD[15:8]
RMT_RD[7:0]
2602[7:0]
2603[7:0]
0 0 R Response fr om remote read request.
RTCA_ADJ[6:0]
2504[6:0]
40
–
R/W
Register for analog RTC frequency adjustment.
RTC_FAIL 2890[4] 0 0 R/W
Indicat es that a count error has occurred in the RTC and that the time is not trustworthy.
T his b it can be cleared by writi ng a 0.
RTC_P[16:14]
RTC_P[13:6]
RTC_P[5:0]
289B[2:0]
289C[7:0]
289D[7:2]
4
0
0
4
0
0
R/W
RTC adjust. See 2.5.4 Real-Time Clock (RTC).
0x0FFBF ≤ RTC_P ≤ 0x10040
Note: RTC_P[16:0] and RTC_Q[1:0] form a single 19-bit RT C adjustment value.
RTC_Q[1:0] 289D[1:0] 0 0 R/W
RTC adjust. See 2.5.4 Real-Time Clock (RTC).
Note:
RTC_P[16:0]
and
RTC_Q[1:0]
form a single 19-bit RT C adjustment value.
RTC_RD 2890[6] 0 0 R/W
Freez es the RTC shadow regi ster so i t i s suit able for MPU reads. When RTC_RD is
read, it ret ur ns the status of the shadow register:
0 = up to date, 1 = frozen.
RTC_SBSC[7:0]
2892[7:0]
–
–
R
Time remaini ng since the last 1 second boundary. LSB=1/ 128 second.
RTC_TMIN[5:0]
289E[5:0]
0
–
R/W
The t ar get minutes register . See RTC_THR below.
RTC_THR[4:0] 289F[4:0] 0 – R/W
The target hours register. The RTC_T interrupt occurs when RTC_MIN [5:0] becomes
equal to RTC_TMIN[5:0] and RTC_HR[4:0] becomes equal to RTC_THR[4:0].
RTC_WR 2890[7] 0 0 R/W
Freez es the RTC shadow regi ster so i t i s suit able for MPU writes. When RTC_WR is
cl ear ed, the contents of the shadow register are wri tten to the RTC counter on the next
RTC cloc k (~ 1 kHz). When RTC_WR i s read, it returns 1 as long as RTC_WR is set. It
continues to ret ur n one until the RTC counter actually updates.
RTC_SEC[5:0]
RTC_MIN[5:0]
RTC_HR[4:0]
RTC_DAY[2:0]
RTC_DATE[4:0]
RTC_MO[3:0]
RTC_YR[7:0]
2893[5:0]
2894[5:0]
2895[4:0]
2896[2:0]
2897[4:0]
2898[3:0]
2899[7:0]
–
–
–
–
–
–
–
–
–
–
–
–
–
–
R/W
The RTC interface. These are the year, month, day, hour, minute and second parameters
for the RTC. The RTC is set by writing to these registers. Year 00 and all others divisible
by 4 are defi ned as a l eap y ear .
SEC 00 to 59
MIN 00 t o 59
HR 00 to 23 (00=Midnight)
DAY 01 t o 07 (01=Sunday)
DATE 01 to 31
MO 01 to 12
YR 00 to 99
Each wri t e operation to one of t hese registers m ust be preceded by a wri te to 0x20A0.
RTM_E
2106[1]
0
0
R/W
Real Time Monitor enable. When 0, t he RTM output i s l ow.
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RTM0[9:8]
RTM0[7:0]
RTM1[7:0]
RTM2[7:0]
RTM3[7:0]
210D[1:0]
210E[7:0]
210F[7:0]
2110[7:0]
2111[7:0]
0
0
0
0
0
0
0
0
0
0
R/W Four RTM pr obes. B efore each CE code pass, the values of these registers are serially
output on the RTM pin. The RTM registers are ignored when RTM_E = 0. Note that
RTM0 is 10 bi ts wide. The other s assum e the upper t wo bits are 00.
SECURE SFR B 2[6] 0 0 R/W
Inhib its erasure of page 0 and flash me mo ry address es above the beginn ing of CE cod e
as defined by CE_LCTN[6/5:0]. Also inhibits the reading of flash memory by external
devices (SPI or ICE port).
SLEEP 28B2[7] 0 0 W
Puts the 71M6543 to sleep. Ignored if system power is present. The 71M6543 wakes
when the Wake timer times out, when push button is pushed, or when system power
returns.
SPI_CMD
SFR FD [7 :0]
–
–
R
SPI command. 8-bit c ommand fr om the bus master.
SPI_E 270C[4] 1 1 R/W
SPI por t enable. Enables the SPI i nterface on pins SEGDIO36 – SEGDIO39. Requires
that LCD_MAP[36-39] = 0.
SPI_SAFE 270C[3] 0 0 R/W
Lim its SPI write s t o SPI_CMD and a 16 byt e re gio n in DRAM . No ot her wri te s are
permitted.
SPI_STAT 2708[7:0] 0 0 R
SPI_STAT contains the status result s from the pr ev ious SPI transaction
Bit 7 - 71M6543 ready er r or : the 71M6543 was not ready to read or write as di r ected by
the prev ious command.
Bit 6 - Read data par ity: This bit is the pari ty of all bytes read from the 71M6543 i n the
previous command. Does not i nc lude the SPI_STAT byte.
Bit 5 - Write data parity: This bi t is the overall pari ty of the bytes writ ten to the 71M6543
in the prev ious command. It includes CMD and ADDR bytes.
B it 4: 2 - B ot t om 3 bi ts of th e b y t e c o unt . Do e s no t inc lude ADDR and CM D bytes.
One, two, and thr ee by te instructions return 111.
Bit 1 - SPI FLASH mode: This bit is zero when the TEST pin is zero.
Bi t 0 - SPI FLASH mode ready: Used in SPI FLASH mode . Indica te s that the flash is ready to
receive another wr it e instruction.
STEMP[10:3]
STEMP[2:0]
2881[7:0]
2882[7:5]
–
–
–
–
R
R
The resul t of the temperature measurement.
SUM_SAMPS[12:8]
SUM_SAMPS[7:0]
2107[4:0]
2108[7:0]
0 0 R/W
The nu mbe r o f multiplexer c ycles (fra mes ) per X FER_B US Y in terru pt. Ma ximum value is
8191 cycles.
TBYTE_BUSY 28A0[3] 0 0 R
Indicat es that hardware i s sti ll writing the 0x28A0 byte. Additional wri tes to this byte are
loc k ed out while it is one. Write duration could be as long as 6 ms.
TEMP_22[10:8]
TEMP_22[7:0]
230A[2:0]
230B[7:0]
0 – R Storage location for STEMP[10:0] at 22C. STEMP[10:0] is an 11 bit word.
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TEMP_BAT
28A0[4]
0
–
R/W
Causes VBAT to be measure d whe never a temperat ure meas urement is performed.
TEMP_BSEL 28A0[7] 0 – R/W
Sel ec ts whic h batter y is monitored by the temperature sensor:
1 = VBA T, 0 = VBAT_RTC
TEMP_PER[2:0] 28A0[2:0] 0 – R/W
Sets the period between temperature measurements. Automatic measurements can be
enabled in any mode (M S N, BRN, LCD, or SLP). TEMP_PER = 0 disables automatic
temper ature updat es, in which c ase TEMP_START may be used by t he M P U to initiate a
one-shot te mperature measurement.
TEMP_PER Time (second s)
0 No t em per ature updat es
1-6
)PER_TEMP3(
2
+
7 Cont inuous updates
TEMP_PWR 28A0[6] 0 – R/W
Sel ec ts the power source for the temp sensor :
1 = V3P3D, 0 = VB AT_RTC.
This bit is ignored in S LP and LCD modes, where the t emp sensor is al ways powered
by VBAT_RTC.
TEMP_START 28B4[6] 0 0 R/W
When TEMP_PER = 0 aut om at i c tem p e ra tu r e me a su rem e nt s ar e disabl e d, an d
TEMP_START may be s et by the MPU to init iate a o ne-shot temperature
measurement. TEMP_START is ignored in SLP and LCD modes. Hardware clears
TEMP_START when the temperature measurement is complete.
TMUX[5:0]
2502[5:0]
–
–
R/W
Sel ec ts one of 32 signals for TMUXOUT. See 2.5.14 for details.
TMUX2[4:0]
2503[4:0]
–
–
R/W
Sel ec ts one of 32 signals for TMUX2OUT. See 2.5.14 for details.
TMUXR2[2:0]
TMUXR4[2:0]
TMUXR6[2:0]
270A[2:0]
270A[6:4]
2709[2:0]
000
000
R/W The T M UX setting for the remote isolated sensors (71M6x x3).
VERSION[7:0] 2706[7:0] – – R
The silicon version index. This word may be read by firmware to det ermine t he si licon
version.
VERSION[7:0] 71M6543F/H
Silicon Version 71M6543G/GH
Silicon Version
0001 0001 A01 A01
0001 0011 A03 N/A
0001 0011 B01 N/A
0010 0010 B02 N/A
VREF_CAL 2704[7] 0 0 R/W
Brings the ADC reference voltage out to the VREF pin. This feature is disabled when
VREF_DIS=1.
VREF_DIS
2704[6]
0
1
R/W
Disabl es the int er nal ADC voltage reference.
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VSTAT[2:0] SFR F9[2: 0] – – R
This word descri bes the s our c e of power and the status of the VDD.
VSTAT[2:0] Description
000
System P ower OK . V3P 3A> 3.0v. Analog modules are func tional and
accurate. [V3AOK,V3OK]=11
001
System P ower Lo w. 2. 8v <V3P 3A< 3.0v. Analog modules not acc ur ate.
Switc h ov er to bat tery power is immi nent. [V3AOK ,V3OK]=01
010
Battery power and VDD OK. VDD>2.25v. Full digital functionality.
[V3AOK,V3OK]=00, [VDDOK,VDDgt2]=11
011
Battery power and VDD> 2.0. Flash writ es are inhibited. If t he
TRI M V DD[5] fuse is bl own, PLL_FAST is cleared.
[V3AOK,V3OK]=00, [VDDOK,VDDgt2]=01
101
Battery power and VDD< 2.0. When V STAT=101, processor is nearl y
out of v oltage. Processor failure is imminent.
[V3AOK,V3OK]=00, [VDDOK,VDDgt2]=00
WAKE_ARM 28B2[5] 0 – R/W A rms the WAKE timer and loads i t wit h WAK E _TMR[7:0]. When SLEEP or LCD mode
is asserted by the MPU, the WAKE timer bec om es active.
WAKE_TMR 2880[7:0] 0 – R/W Time r duration is WAKE_TMR+1 seconds.
WD_RST 28B4[7] 0 0 W Reset the WD timer. The WD is reset when a 1 is written t o this bit. Writing a one
cl ear s and restarts the watch dog timer.
WF_DIO4 28B1[2] 0 – R DI O4 wake flag bit. If DIO 4 is confi gur ed to wake the part, this bit is set whenever the
de-bounced versi on of DI O4 rises. It is hel d in r eset if DI04 is not confi gur ed for
wakeup.
WF_DIO52 28B1[1] 0 – R DIO52 wake flag bit. If DIO52 is configured to wake the part , t his bit is set whenever the
de-bounced version of DIO52 rises. It is held in reset if DI052 is not configured for wakeup.
WF_DIO55 28B1[0] 0 – R DIO55 wake flag bit. If DIO55 is configured to wake the part , t his bit is set whenever the
de-bounced version of DIO55 rises. It is held in reset if DI055 is not configured for wakeup.
WF_TMR 28B1[5] 0 – R Indicat es that t he wake tim er c aused the par t to wake up.
WF_PB 28B1[3] 0 – R I ndicates that the PB caused the part to wake.
WF_RX 28B1[4] 0 – R Indic ates that RX caused the par t to wake.
WF_CSTART
WF_RST
WF_RSTBIT
WF_OVF
WF_ERST
WF_BADVDD
28B0[7]
28B0[6]
28B0[5]
28B0[4]
28B0[3]
28B0[2]
0
1
0
0
0
0
– R Indi cates that the Reset pin, Reset bit , ERST pin, Watchdog ti mer , the cold s ta r t d etec tor,
or bad VBA T caused the par t to reset.
71M6543F/H and 71M6543G /GH Data Sheet
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5.3 Reading the Inf o Page (71M6543H and 71M6543GH only)
High precision trim fuse values provided in the 71M6543H and 71M6543G H devices cannot be dir ec tly
accessed thr ough the I/O RA M space. T hese tr im fuses reside in a special ar ea term ed the “Info Page”.
The MP U gains access to the Info P age by setting the INFO_PG (I /O R AM 0x2 70B[0]) contr ol bit. Once the
INFO_PG bit is set, Info Page cont ents are accessible in program m em or y space based at the address
specif ied by the contents of CE_LCTN[6/5:0] (I/O R AM 0x2109[5:0]) in the 71M 6543 H and CE_LCTN[6:0]
(I/O RA M 0x2109[ 6:0]) in the 71M6543GH. CE_LCTN[5:0] in the 71M6543H and CE_LCTN[6:0] in the
71M6543GH specify a base address at a 1KB address boundary . Thus, the bas e address for the Info Page
is at 1024*CE_LCTN[5:0] in the 71M6 543 H and 1024*CE_LCTN[6:0] in the 71M 6543 G H. Table 72 provides
a list of the avail able 71M 6543H and 71M 6543GH trim fuses and thei r c or r espondi ng offsets relative to
the I nfo Page base address. After readi ng the desir ed Info Page i nform ation, the MPU must reset the
INFO_PG bit.
Table 72: Inf o Page T rim Fuses
Trim Fus e
Object Size
Address Offset
Comments
TEMP_85[10:8]
TEMP_85[7:0]
(11-bits)
8-bits
8-bits
0x90
0x91 TEMP_85[10:0] holds the
STEMP[10:0] readi ng at 85° C.
2’s complement for mat
TRIMBGB[15:8]
TRIMBGB[7:0]
(16-bits)
8-bits
8-bits
0x92
0x93
TRIMBGB[15:0] holds the
deviation of VREF from its ideal
v alue ( 1.195V) at 85° C.
LSB = 0. 1 mV
2’s complement forma t
TRIMBGD[7:0]
(8-bits)
8-bits
0x94
TRIMBGD[7:0] holds the
deviation of VREF from its ideal
v alue ( 1.195V) at 22° C.
LSB = 0. 1 mV
2’s complement forma t
LCDADJ12[7:0]
(8-bits) 8-bits 0x95
LCDADJ12 = [VLCD-3. 676v ] at
22C when LCD_DAC= 0C.
LSB=5mV. Two’s c omplement.
LCDADJ0[7:0]
(8-bits) 8-bits 0x96
LCDADJ0 = [VLCD-2.65v] at
22C when LCD_DAC= 0.
LSB=5mV. Two’s c omplement.
Figure 38. T rim Fuse Bit Mapping
Offset
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x90
TEMP_85[10:0]
TEMP_85[10:8]
0x91
TEMP_85[7:0]
0x92
TRIMBGB[15:0]
TRIMBGB[15:8]
0x93
TRIMBGB[7:0]
0x94
TRIMBGD[7:0]
TRIMBGD[7:0]
The code below provi des an example for reading Info Page fuse trim s. In this code exam ple, the addr ess,
"px" is a pointer to the MPU’s code space. In assembl y language, the I nfo Page data object s, whic h ar e
read-only, m ust be accessed with the MOVC 8051 instruction.
In C, Inf o Page trim f uses must be fetc hed with a pointer of the cor r ec t widt h, depending whether an 8-bit
or a 16-bi t dat a objec t is to be fetched. The case statements in the code example below perf orm casts to
obtain a pointer of t he correc t siz e for each object, as needed.
In assembly language, the MPU has to form 11-bit or 16-bit values from two separate 8-bit fetches,
depending on the obj ec t being fetched.
71M6543F/H and 71M6543G /GH Data Sheet
v1.2 © 2008–2011 Teridian Sem iconduc tor Corpor ation 119
The byte values containing less than 8 val id bits are LSB j ustified. For ex am ple Inf o P age offset 0x 90 is
an 8-bit object, whose three LSBs are bits [10:8] of the complete TEMP_85[10:0] 11-bit object. The Info
Page data objects are 2’s com plement format and should be sign extended when read into a 16-bit dat a
type ( see case _TEM P 85 in the code exam ple) .
#if HIGH_PRECISION_METER
int16_t read_trim (enum eTRIMSEL select) {
uint8r_t *px;
int16_t x;
px = ((uint16_t)select) + ((uint8r_t *)(CE3 << 10));
switch (select)
{
default:
case _TRIMBGD:
INFO_PG = 1;
x = *px;
INFO_PG = 0;
break;
case _TRIMBGB:
INFO_PG = 1;
x = *(uint16r_t*)px;
INFO_PG = 0;
break;
case _TEMP85:
INFO_PG = 1;
x = *(uint16r_t*)px;
INFO_PG = 0;
if (x & 0x800)
x |= 0xF800;
break;
}
return (x);
}
#endif //#if HIGH_PRECISION_METER
71M6543F/H and 71M6543G /GH Data Sheet
120 © 2008–2011 Teridian Semi c onduc tor Corpor ation v1.2
5.4 CE Interface Description
5.4.1 CE Program
The CE performs the precision computations necessary to accurately measure power. These computations
inc lud e of f set ca nc el lat i on, ph a se com pe n sati on, prod uct smoothing, pro duct summ ati on, frequency
detecti on, VAR calculation, sag detection and v oltage phase measurement . All dat a c om puted by the CE
is dependent on the selected met er equation as given by EQU[2:0] (I/O R AM 0x2106[7:5]).
The standard CE pr og ram is s uppl ied by Teridian as a data im age that c an be m erged with th e M P U
operational code for meter app lications . Typically , this CE pr ogr am c ov er s most applications and does
not need t o be m odified. Ot her v ari ations of CE code may be av ailable f r om Teridian. The description in
this sect ion applies to CE code revision CE43A01A.
5.4.2 CE Da ta For mat
All CE words ar e 4 bytes . Unles s s pec ified otherw is e, they are in 32-bit two’s c om plem ent format
(-1 = 0xFFFFFFFF ). Calibration parameters are defined in flash m emory (or external EEPROM) and
m ust be c opied to CE data mem or y by the MPU bef or e enabling the CE. Internal vari ables are used in
internal CE calculations. Input variabl es all ow the MP U to control the behavior of the CE code. Output
v ari ables are outputs of the CE calculations. The corresponding M P U addr ess f or the most si gnificant
byte is given by 0x0000 + 4 x CE_address and by 0x0003 + 4 x CE_address for the least signif ic ant byte.
5.4.3 Constants
Constants used i n the CE Dat a Memory tables are:
• Sam pling Frequency : FS = 32768 Hz/15 = 2184.53 Hz.
• F0 is the fundamental frequency of t he mai ns phases.
• IMAX is the external rm s curr ent corresponding t o 250 m V pk at each IADC input.
• VMAX is th e external rm s volt age c or r espondi ng to 250 mV pk at each VADC input.
• NACC, the accumulation count for energy measurements is SUM_SAMPS[12:0] ( I/O RA M 0x21 07[4:0],
0x2108[7:0]). This value also resides in SUM_PRE (CE RAM 0x23) where it is used f or phase angl e
measurement.
• The durat ion of the accumulation interval for energy measurements is SUM_SAMPS[12:0] /FS.
• X is a gain constant of the pulse generators. Its value is determined by PULSE_FAST and PULSE_SLOW
(see Table 78).
• Voltage LSB = VMAX * 7.879810-9 V.
• VMAX = 600 V, IMA X = 208 A, and kH = 3.2 Wh/ pulse are assumed as def ault settings.
The system constant s IMAX and VMAX are used by the MPU to conver t internal digital quantiti es (as
used by the CE) to external, i.e. meteri ng quantities. Their values are det ermi ned by the scaling of the
v oltage and curr ent sensors used i n an ac tual met er. The LSB values use d in this document relat e digital
quantities at the CE or MPU interf ac e to external m eter input quantities. F or example, if a SAG threshol d
of 80 V peak is desired at the meter i nput, the digital val ue that should be programmed into SAG_THR (CE
RAM 0x24) would be 80 V/SAG_THRLSB, wher e SAG_THRLSB is the LSB v alue in the description of
SAG_THR (Table 79).
The param eters EQU[2:0], CE_ E, and SUM_SAMPS[12:0] , essential to the func tion of the CE are stored i n
I/ O RAM (see 5.2 for detail s).
71M6543F/H and 71M6543G /GH Data Sheet
v1.2 © 2008–2011 Teridian Sem iconduc tor Corpor ation 121
5.4.4 Environment
Before st arti ng the CE usi ng the CE_E bit (I/O RA M 0x210 6[ 0]), th e MP U h as to establish the pr oper
environment for the CE by implementing the fo llowing steps:
• Locate t he CE code i n Flash m em ory usi ng CE_LCTN[5:0] (I/ O RAM 0x2109[5:0]) in the 71M6543F/H
and CE_LCTN[6:0] (I/O RAM 0x2109[6:0]) i n the 71M6543G/ GH
• Load the CE data into RAM.
• Establish the equat ion to be appli ed in EQU[2:0] ( I/O RAM 0x2106 [7:5 ]).
• Establish the acc um ulation period and number of samples i n SUM_SA MP S[1 2:0] (I/O RAM
0x2107[4:0] , 0x2108[7:0] ).
• Establish the number of cy cl es per ADC m ultiplexer frame (MUX_DIV[3:0] (I/O R A M 0x2100[7:4])).
• Apply pr oper v alues to MUXn_SEL, as well as proper sel ec tions for DIFFn_E (I/O RAM 0x210C[ ]) and
RMTn_E (I /O RA M 0x270 9[ ] in order to configure the analog input s.
• I nit ialize any MPU interrupts, such a s CE_BUSY, XFER_BUSY, or the power -failure dete ction inte r rup t.
When different CE codes are used, a differ ent set of environm ent parameters need to be establi shed.
The exac t values for these param eters are li sted in the Applicati on Notes and other docum entation which
accompanies the CE c ode.
Operating CE codes w ith environment parameters deviating from the values specified by Teridian
leads to unpr edictable results.
Typically , t her e ar e fifteen 32768 Hz cycles per ADC mul tipl ex er fr am e (see 2.2.2). This means that the
product of the number of cycl es per f r am e and the number of conversions per f rame must be 14 (allowing
for one settling cycle). The default configuration is FIR_LEN = 01, I/O RAM 0x210C[1] (two cycl es per
conversion) and MUX_DIV[3:0] = 7 ( 7 conversi ons per multiplexer cycle).
Sample confi gur ations can be copi ed from Dem o Code provided by Teridian with th e Demo Kits.
5.4.5 CE Calculations
Referring to Table 73, The MPU selects the desired equati on by writing the EQU[2:0] (I/O RAM
0x2106[7:5]).
Table 73: CE EQU[2:0] Equations and Element Input Mapping
EQU
[2:0]* Watt & VAR Fo rmul a
(WSUM/VARSUM) W0SUM/
VAR0SUM W1SUM/
VAR1SUM W2SUM/
VAR2SUM I0SQ
SUM I1SQ
SUM I2SQ
SUM
2
VA*IA + VB*I B
(2-element, 3-W, 3φ
Delta)
VA * I A VB * IB N/A IA IB –
3
VA*(IA-IB)/2 + VC*IC
(2 element, 4W 3
φ
Delta)
VA*(IA-IB)/2 – VC*IC IA-IB IB IC
4
VA*(IA-I B) /2 + VB*(I C-IB)/2
(2 element, 4W 3
φ
Wye)
VA*(IA-IB)/2 VB*(IC-IB)/2 – IA-IB IC-IB IC
5
VA*IA + VB*I B + VC*IC
(3 element, 4W 3
φ
Wye)
VA*IA VB*IB VC*IC IA IB IC
Note:
* Only EQU[2:0] = 5 is support ed by the currently available CE c ode v er si ons for the 71M6543. Contact
your local Teridian representativ e for CE codes that support equati ons 2, 3 and 4.
71M6543F/H and 71M6543G /GH Data Sheet
122 © 2008–2011 Teridian Semi c onduc tor Corpor ation v1.2
5.4.6 CE Front-End Data (Raw Data)
Access to the raw data provided by the AFE is possible by re ading CE RAM add r es s es 0 thr ough A, as
shown in Table 74. In the expression MUXn_SEL[3:0] = x, ‘n’ refers to the multiplexer frame time slot number
and ‘x’ refers to the desired ADC input number or ADC handle (i.e., IADC0 to VADC10, or simply 0 to 10
decimal).
The 71M6543 can s upport up to eleven sensor inputs, wh en all the c urrent sensors are co nfigured as
single-e nded inputs. I f all the current sensor inputs are c onfigur ed as di fferent ial ( r ecommended for
best p erform anc e), t he num b er of input sens or c ha nnels i s r edu c ed t o seven (i .e., IADC0-1, IADC2-3,
IADC4-5, IADC6-7, VADC8, VADC9 an d V ADC10). The MUXn_SEL[3:0] column in Table 74 shows the
MUXn_SEL handles for the variou s s ensor input pins. For example, if differential mode is enabled via
control bit DIFF0_E = 1 (I/O RAM 0x210C [4 ]), then the IADC0-IADC1 input pins are combined together to
form a single differential input and the corresponding MUXn_SEL handle is 0 (i.e., handle 1 is then unused).
Similarly, the CE RAM location column provides the CE RAM address where the corresponding sampl e data
is s t or ed . Co ntinuing with the same example, if DIFF0_E = 1, the corresponding CE RAM location where the
samples for the IADC0-IADC1 differential input are stored is CE RAM 0.
The IADC2-3, IADC4-5 and IADC6-7 inputs can be c onfigured as direc t-co nnected s ensors (i.e., directly
connected to the 71M6543) or as remote sensors (i.e., using a 71M6xx3 Isolated Sensor). For example, if the
IADC2-3 remote sensor is disabled by RMT2_E = 0 (I/O RAM 0x2007[3 ]) and differential mode is enabled by
DIFF2_E = 1 (I/O RA M 0x210 C[ 4]), then IADC2-IADC3 form a differential input w ith a MUXn_SEL handle of 2
(i.e., handle 3 is then unused), and the corresponding samples are stored in CE RAM location 2. If the
remote s ensor enabl e bit RMT2_E = 1 , DIFF2_E = x (don’t care), then the MUXn_SEL handle is not required
(i.e., th e sensor is not connected to the 71M6543 multiplexer, so MUXn_SEL does not apply), and the
samples corresponding to this remote differential IADC2-IADC3 input are stored in CE RAM location 2
directly by the digital isolation interface (see Figure 2).
The voltage sensor inputs (VADC8, VADC9 and V ADC10) are always single-ended inputs and cannot be
configured as remotes, so they do not hav e any associated c onfigur ation bits. VADC8 (VA) has a
MUXn_SEL handle value of 8, and its samples are stored i n CE RAM loc ation 8. VADC9 (VB) has a
MUXn_SEL handle value of 9 and its samples are stored in CE RAM location 9. VADC10 (VC) has a
MUXn_SEL handle value of 10 and its samples are stored in CE RAM location 10.
Table 74: CE Raw Data Access Lo cat io ns
Pin MUXn_SEL Handle CE RAM Location
DIFF0_E
DIFF0_E
0 1 0 1
IADC0 0 0 0 0
IADC1 1 1
RMT2_E, DIFF2_E RMT2_E, DIFF2_E
0,0 0,1 1,0 1,1 0,0 0,1 1,0 1,1
IADC2 2 2 - - 2 2 2* 2*
IADC3 3 3
RMT4_E, DIFF4_E
RMT4_E, DIFF4_E
0,0 0,1 1,0 1,1 0,0 0,1 1,0 1,1
IADC4 4 4 - - 4 4 4* 4*
IADC5
5 5
RMT6_E, DIFF6_E
RMT6_E, DIFF6_E
0,0 0,1 1,0 1,1 0,0 0,1 1,0 1,1
IADC6 6 6 - - 6 6 6* 6*
IADC7 7 7
There are no confi guration bits for VADC8, 9, 10
VADC8 (VA) 8 8
VADC9 (VB) 9 9
VADC10 (VC) 10 10
*Remote interface data
71M6543F/H and 71M6543G /GH Data Sheet
v1.2 © 2008–2011 Teridian Sem iconduc tor Corpor ation 123
5.4.7 CE S tatus and Control
The CE Status Word is useful for generating early warnings to the MPU (Table 75). It contains sag warnings
for phase A, B , and C, as well as F0, the derived clock operating at the funda mental input frequenc y . The
MPU can r ead the CE status word at ever y CE_BUS Y interrupt . Sinc e the CE_BUSY int errupt occ ur s at
the sam ple rate (i.e., 2520.6 Hz for MUX_DIV[3:0]=6 or 2184.5 Hz f or MUX_DIV[3:0]=7), it is desirable to
mi nimi z e the com putation r equir ed in the inter r upt handler of the MPU.
Table 75: CESTATUS Register
CE Address Name Description
0x80
CESTATUS
See descri pti on of
CESTATUS
bits in Table 76.
CESTATUS provide s information about th e status of v olt age and input AC signal freq ue nc y, which are useful
for generating an early power fail warni ng to initiate necessary data storage. CESTATUS represents the
status fl ags for the pr ec eding CE code pass (CE_B US Y interrupt). The significance of the bits in
CESTATUS is shown in Table 76. Table 76: CESTATUS Bit Definitions
CESTATUS
bit Name Description
31:4 Not Used These unused bit s are always zer o.
3 F0 F0 is a square wave at the exact funda menta l input frequency.
2 SAG_C Normally zero. Becomes one when VADC10 (VC) remains below
SAG_THR
(CE RAM 0x24) for SAGCNT s amples. Does not return to zero until VADC10
(VC) rises above SAG_THR.
1 SAG_B Normally zero. Becomes one when VADC9 (VB) remains below SAG_THR
for SAG_CNT samples. Does not return to zero until VADC9 (VB) rises above
SAG_THR.
0 SAG_A Normally zero. Becomes one when VADC8 (VA) remains below SAG_THR
for SAG_CNT samples. Does not return to zero until VADC8 (VA) rises above
SAG_THR.
The CE is i nitialized by the MPU using CECONFIG (Table 77). This register c ontains in packed form
SAG_CNT, FREQSE L0, FREQSEL1, EXT_ PULSE, PULSE_SLOW, and PULSE_FAST. The CECONFIG bit
definitions are given in Table 78.
Table 77: CECONFIG Register
CE Address Name Data Description
0x20 CECONFIG 0x0030DA20 See descript ion of the CECONFIG bits in Table 78.
The EXT_TEMP bit enables temperature compensation by the MP U, when set to 1. When 0, inter nal ( CE )
temper ature com pensation is enabled.
The CE pulse generator can be controlled by either the MPU (external) or CE (internal) variables. Control is by
the MPU if EXT_PULSE = 1. In this case, the MPU controls the pulse rate by placing values into APULSEW and
APULSER (C E RAM 0x45 and 0x49). By setting EXT_PULSE = 0, the CE controls the pulse rate based on
WSUM_X (CE RAM 0x84) and VARS U M _X (CE RA M 0 x88).
The 71M6543 Dem o Code creep f unc tion halts both internal and ext er nal pulse generation.
71M6543F/H and 71M6543G /GH Data Sheet
124 © 2008–2011 Teridian Semi c onduc tor Corpor ation v1.2
Table 78: CECONFIG Bit Definitions (CE RAM 0x20)
CECONFIG
bit Name Default Description
23
Reserved
0 Reserved.
22 EXT_TEMP 0 When 1, the MP U contr ols tem per ature compensation via the
GAIN_ADJn (CE RAM 0x40-0x42), when 0, the CE is i n contr ol.
21 EDGE_INT 1 When 1, XPULSE produc es a pul se for eac h z er o-crossing of
the mains phase selec ted by FREQSEL[1:0] , whi c h c an be used
to interrupt the MP U.
20 SAG_INT 1 When 1, activ ates the Y P ULS E/S EGDIO 7 output when a sag i s
detected (see 2.5.10) on the phase selec t e d with FREQ-
SEL[1:0].
19:8 SAG_CNT 218
(0xDA)
The number of consecut ive voltage samples below SAG_THR
(CE RAM 0x24) before a sag al arm is dec lar ed. The d efault value
is equival ent t o 100 ms.
7:6 FREQSEL[1:0] 0
FREQSEL[1:0]
selects the phase to be used f or the frequency
m onitor, sag detect ion, the phase-to-phase lag c alculation and
for the zero crossing count er (MAINEDGE_X, CE RAM 0x83).
FREQ SEL[1:0] Phase
Selected
Phases S elected
PH_AtoB_X PH_AtoC_X
0 0 A A-B A-C
0 1 B B-C B-A
1 0 C C-A C-B
1 1 Not allowed
5 EXT_PULSE 1
When zero, causes the pul se generators to r espond to int er nal
data. WPULSE = WSUM_X (CE RAM 0x84), VPULSE = VARSUM_X
(CE RAM 0x88.) Other wise, the generat or s respond to values the
MPU places in APULSEW and APULSER (CE RAM 0 x4 5 and 0x49)
4:2 Reserved 0 Reserved.
1 PULSE_FAST 0
When PULSE_FAST = 1, the pul se generat or input i s increased
16x. When PULSE_SLOW = 1, t he pulse generator input is
reduced by a factor of 64. These two paramet er s cont rol the
pulse gai n fact or X (see table below). Allowed values are either
1 or 0. Default is 0 f or both (X = 6).
PULSE_FAST PULSE_SLOW X
0 0 1. 5 * 2
2
= 6
0 1 1.5 * 2
-4
= 0.09375
1 0 1.5 * 2
6
= 96
1 1 Do not use
0 PULSE_SLOW 0
The FREQSEL[1:0] field in CECONFIG (CE RAM 0x20[7:6]) selects the phase that is utilized to generate a sag
interrupt. Thus, a SAG_INT event occur s when the selected phase has sati sfi ed the sag ev ent cri teria as
set by the SAG_THR (CE RAM 0x24) register and the SAG_CNT field in CECONFIG (CE RAM 0x20[19:8]).
When the SAG_INT bit ( CE RAM 0x20[20]) is set to 1, a sag event generates a tr ansi ti on on the YPULSE
output . Aft er a sag i nterrupt, the MP U should change the FREQSEL[1:0] setting to selec t t he other phase,
if it is powered. Even though a sag int er r upt is only generat ed on the selected phase, all three phase s
are simult aneousl y c hec k ed for sag. The presence of power on a given phase can be sensed by directly
checking t he SAG_A, SAG_B and SAG_C bits in CESTATUS (CE RAM 0x80 [0:1 ]).
The EXT_TEMP bit enables temperature compensation by the MP U, when set to 1. When 0, inter nal ( CE )
temper ature com pensation is enabled.
71M6543F/H and 71M6543G /GH Data Sheet
v1.2 © 2008–2011 Teridian Sem iconduc tor Corpor ation 125
The CE pulse generator can be controlled by either the MPU (external) or CE (internal) variables. Control is by
the MPU if the EXT_PULSE bit = 1 (CE RAM 0x20[5]). In this case, the MPU controls the pulse rate (external
pulse generat ion) by placing v alues i nto APULSEW and APULSER (CE RAM 0 x45 and 0x49). By set t ing
EXT_PULSE = 0, the CE controls the pulse rat e based on WSUM_X (CE RAM 0x84) and VARS UM_X (C E
RAM 0x88).
The 71M6543 Dem o Code creep f unc tion halts both internal and ext er nal pulse generation.
Table 79: Sag Threshold, Phase Measurement, and Gain Adjust Control
CE
Address
Name Default Description
0x24 SAG_THR 2.39*107 T he v oltage threshol d for sag warnings. The de fault value is
equivalent to 80 V RMS if VMAX = 600 V.
0x40 GAIN_ADJ0 16384 The assignm ents of these gai n adjustments depends on the
m eter desi gn. See 4.5.5 Temper ature Compensation for VREF
and Shunt S ensors on page 90 or 4.5.6 Temperature
Com pensation of VREF and Current Transformers on page 92.
The def ault value of 16384 c or r esponds to uni ty gain.
0x41 GAIN_ADJ1 16384
0x42 GAIN_ADJ2 16384
0x43 GAIN_ADJ3 16384
0x44 GAIN_ADJ4 16384
5.4.8 CE Tran s f er Variables
When the MPU receives the XFER_B US Y int errupt , it knows that fresh data is available in the t r ansfer
variables. CE transfer v ari ables are modified duri ng the CE code pass that ends with an XFER_BUS Y
interrupt. They remain constant throughout eac h ac c um ulation interval. In thi s data sheet, the names of
CE tr ansfer variables always end with _X. The tr ansfer variables can be categor ized as:
• Fundamental energy measurement variables
• Instantaneous (RMS) values
• Other measurement parameters
Fundamental Energy Measurement V ariab les
Table 80 describes each transfer variable for fundamen tal energy measurement. All vari ables are signed
32-bit integers. Accumulated v ari ables such as WSUM are internally scal ed so they hav e at least 2x
margin before overflow when the integration time is one second. Additionally, the hardware does n o t permit
output values to fold back upon ov erflow.
Table 80: CE Transfer Variables (with Shunts)
CE
Address Name Description Configuration
0x84
WSUM_X
The signed sum: W0SUM_X+W1SUM_X+W2SUM_X.
Figure 31 (page 87)
0x85
W0SUM_X
The sum of Wh samples fr om eac h wattmeter
element.
LSBW = 7.7562*10-13 VMAX * IMAX Wh.
0x86 W1SUM_X
0x87 W2SUM_X
0x88
VARSUM_X
The signed sum:
VAR0SUM_X+VAR1SUM_X+VAR2SUM_X.
0x89 VAR0SUM_X The sum of VARh samples f r om each wattm eter
element.
LSBW = 7.7562*10-13 VMAX * IMAX VARh.
0x8A
VAR1SUM_X
0x8B VAR2SUM_X
71M6543F/H and 71M6543G /GH Data Sheet
126 © 2008–2011 Teridian Semi c onduc tor Corpor ation v1.2
Table 81: CE Tran sf er V ariables (with CTs)
CE
Address Name Description Configuration
0x84
WSUM_X
The signed sum:
W0SUM_X+W1SUM_X+W2SUM_X
.
Figure 32 (page 88)
0x85
W0SUM_X T he sum of Wh sam ples fr om eac h wattmet er
element.
LSBW = 1.0856*10-12 VMAX IMAX Wh.
0x86 W1SUM_X
0x87 W2SUM_X
0x88
VARSUM_X
The signed sum:
VAR0SUM_X+VAR1SUM_X+VAR2SUM_X.
0x89 VAR0SUM_X The sum of VARh samples f r om each wattm eter
element.
LSBW = 1.0856*10-12 VMAX IMAX VARh.
0x8A
VAR1SUM_X
0x8B
VAR2SUM_X
WSUM_X and VARSUM_X ar e the sign ed sum of Phase-A, Phase -B and Phase-C Wh or VARh val ues
according t o the metering equation specified in t he control fie ld EQU[2:0] (I/O RAM 0x2106[7:5]).
WnSUM_X is the Wh value accumulated for phase n in the las t accumulation interval and can be computed
based on the specified LSB value.
Fo r example, with VMAX = 600 V and IMAX = 208 A, the LSB for WnSUM_X is 0 .135 µWh.
5.4.8.1 Inst antaneous Energy Measurement Variables
InSQSUM_X and VnSQSUM are the squared current and voltage samples acquired during the last accumulation
interval. INSQSUM_X can be used for com puting t he neutral current.
Table 82: CE Energy Measurement Variables (with Shunts)
CE
Address Name Description Configuration
0x8C I0SQSUM_X Neutral Current:
LSBI = 9.9045*10-13 * IMAX2 A2h (PRE_E=0)
LSB
I
= 6.1903125*10-14 * IMAX2 A2h (PRE_E=1)
Figure 31 (page 87)
0x8D I1SQSUM_X
LSBI = 6.3968*10-13 * (IMAX2) A2h
0x8E I2SQSUM_X
0x8F I3SQSUM_X
0x90 V0SQSUM_X
LSBV = 9.4045*10-13*VMAX2 V2h
0x91 V1SQSUM_X
0x92 V2SQSUM_X
Table 83: CE Energy Measurement Variables (with CTs)
CE
Address Name Description Configuration
0x8C I0SQSUM_X
LSBI = 1.0856*10-12 * (IMAX2) A2h
Figure 32 (page 88)
0x8D I1SQSUM_X
0x8E I2SQSUM_X
0x8F
I3SQSUM_X
0x90 V0SQSUM_X
LSBV = 1.0856*10-12 * VMAX2 V2h
0x91 V1SQSUM_X
0x92 V2SQSUM_X
71M6543F/H and 71M6543G /GH Data Sheet
v1.2 © 2008–2011 Teridian Sem iconduc tor Corpor ation 127
The RMS v alues can be com puted by the MPU fr om the squared current and voltage samples as foll ows:
Other transfer variables include those available for frequency and phase m easurement, and those reflecting
the count of the zer o-crossings of the mains voltage an d the battery vo ltage. These tr ansfer variables are
listed in Table 84.
MAINEDGE_X reflects the number of half-cycles accounted for in the last accumulated interval for the AC
signal of the phase specified in the FREQSEL[1 :0] field of the CECONFIG register (CE RAM 0x20[7:6]) .
MAINEDGE_X is useful for implementing a real-time clock based on the input AC signal.
Table 84: Other Transfer Variables
CE
Address Name Description
0x82 FREQ_X Fundamental frequency: LSB
6
32
10509.0
2
2184
−
⋅≈≡ Hz
Hz(for CT)
LSB
6
32 10587.0
2
2520 −
⋅≈≡ Hz
Hz(for S hunt)
0x83 MAINEDGE_X The numbe r of edg e c rossings of t he selected volt age in the previous
accumul ation interval. Edge crossing s are ei ther direction and are
debounced.
0x94 PH_AtoB_X
Vol tage phase lag. The selection of the re ference phase is based on
FREQSEL[1:0] in the CECONFIG register:
If FREQSEL[1:0] selects phase A: Phase l ag from A to B.
If FREQSEL[1:0] selects phase B: Phase l ag from B to C.
If FREQSEL[1:0] selects phase C: Phase lag from C to A.
Angle in degrees is (0 to 360): PH_AtoB_X * 360/NACC + 2.4*15/13 (for CT)
Angle in degrees is (0 to 360): PH_AtoB_X * 360/NACC + 2.4 (for Shunt)
0x95 PH_AtoC_X
If FREQSEL[1:0] selects phase A: Phase l ag from A to C.
If FREQSEL[1:0] selects phase B: Phase l ag from B to A.
If FREQSEL[1:0] selects phase C: Phase lag from C to B.
Angle in degrees is (0 to 360): PH_AtoC_X * 360/NACC + 4.8*15/13 (for CT)
Angle in degrees is (0 to 360): PH_AtoC_X * 360/NACC + 4.8*15/13 (for Shunt)
Phase angle measurement accurac y c an be inc r eased by writing val ues > 1 into V_ANG_CNT (see
Table 79).
5.4.9 Pulse Generation
Table 85 describes the CE pulse generation parameters.
The com bination of the CECONFIG PULSE_SLOW (CE RAM 0x20[0]) and PULSE_FAST (CE R AM 0x20 [1])
bits controls the speed of the pulse rat e. The default values of 0 and 0 maintain the ori ginal pulse rate
giv en by the Kh equation.
WRATE (CE RAM 0x21) contr ols the number of pulses that are generat ed per m easured W h and V A Rh
quantities. The lower WRATE is the slower the pulse rate f or measured energy quant it y . The met eri ng
constant Kh is derived from WRATE as the am ount of energy measured for eac h pulse. That is, if Kh =
1Wh/pulse, a power applied to the met er of 120 V and 30 A results i n one pulse per second. If the load is
240 V at 150 A, ten pulses per second are generated.
Control is transferr ed to the MPU for pulse generat ion if EXT_PULSE = 1 (CE R AM 0x20[5]). In this case,
the pulse rate is determi ned by APULSEW and APULSER (CE RAM 0x45 and 0x4 9). The MPU has to load
ACC
SI
RMS NFLSBIxSQSUM
Ix ⋅⋅⋅
=3600
ACC
SV
RMS NFLSBVxSQSUM
Vx ⋅⋅⋅
=3600
71M6543F/H and 71M6543G /GH Data Sheet
128 © 2008–2011 Teridian Semi c onduc tor Corpor ation v1.2
the source for pulse generation in APULSEW and APULSER t o gener ate pulses. Irrespect ive of the
EXT_PULSE status, t he output pulse rat e c ontrolled by APULSEW and APULSER is implemented by the CE
only. By setting EXT_PULSE = 1, the MPU is providing the source for pulse generat ion. If EXT_PULSE is 0,
W0SUM_X and VAR0SUM_X are the def aul t pul se gen e rati o n sour ce s. In this case, c r eep ca nnot be
contr olled since it is an MPU f unc tion.
The maximu m pulse rate is 3*FS = 7.5 kHz.
See 2.3.6.2 VPULSE and WPULSE (page 27) for det ails on how to adjust the timi ng of t he output pulses.
The maximu m time jitter is 1/6 of the multiplexer cycle period (nominally 67 µs) and is independent of the
num ber of pulses measured. T hus, if t he pulse generat or is monitor ed for one sec ond, the peak jitter is
67 ppm . Aft er 10 seconds, the peak jit ter is 6.7 ppm . The average jitter is always zero. If it is att em pted
to drive either pulse generator faster than its maximum rate, it simply outputs at its maximum rate without
exhibiting any rollov er characteristi c s. The actual pulse rate, usi ng WSUM as an exam ple, is:
Hz
XFWSUMWRATE
RATE
S
46
2
⋅⋅⋅
=
,
where FS = sampling frequenc y ( 2184.53 Hz ), X = Pulse speed factor derived from the CE variables
PULSE_SLOW (CE R A M 0x2 0[0]) and PULSE_FAST (CE RAM 0x20[1]).
Table 85: CE Pulse G eneration Parameters
CE
Address Name Default Description
0x21 WRATE 227
Kh = VMAX*IMAX*K / (WRATE*NACC*X) Wh /pulse
where:
K = 76.3594 when used with local sensors (CT or shunt)
K = 54.5793 when used with 71M6xx3 r em ote sensors
0x22
KVAR
6444 Scale factor for VAR measurement.
0x23 SUM_PRE 2184
Num ber of sam ples per acc um ulati on interval, as specifi ed in
SUM_SAMPS[12:0], I/O RAM 0x2107[4:0], 0x2108[7:0] (NACC).
0x45 APULSEW 0
Wh pulse (WPULSE) generat or input to be updat ed by the MPU
when using exter nal pulse generation. T he output pulse rate is:
APULSEW * FS * 2 -32 * WRATE * X * 2-14.
This input is buffered and can be updated by the MP U during a
conversion interval. The change takes ef fect at th e beginning of
the next interval.
0x46
WPULSE_CTR
0
Counte r for WPULS E ou tpu t.
0x47 WPULSE_ F RAC 0
Unsigned numerator, c ontaining a fr ac tion of a pulse. The value
in this r egis ter always c ounts up towards the next pulse.
0x48
WSU M_ ACCUM
0
Roll-over accu mulator for WPULSE.
0x49
APULSER
0
VARh (VPULSE) pulse generator input.
0x4A
VPULSE_CTR
0
Counte r for VPULSE output.
0x4B VPULSE_ FRAC 0
Unsigned numerator, containing a fraction of a pulse. The val ue
in this regi s ter always counts up towar ds the nex t puls e.
0x4C
VSUM_ACCUM
0
Roll-over accumulator for VPULSE.
Other CE Parameters
Table 86 shows the QUANT CE par am eters used for suppressi on of noise due to scali ng and trunc ation
effects. The equations for calculating the LSB weight of each QUANT parameter are provi ded at the
bottom of Table 86.
71M6543F/H and 71M6543G /GH Data Sheet
v1.2 © 2008–2011 Teridian Sem iconduc tor Corpor ation 129
Table 86: CE Parameters for Noise Suppressi on and Code Versio n
CE
Address Name Default Description
0x26
QUANT_IA
0
Compensation factors for truncation and noise in current, real
energy and reac tive energy for phase A.
0x27
QUANT_WA
0
0x28 QUANT_VARA 0
0x2A QUANT_IB 0 Compensation factors for truncation and noise in current, real
energy and reac tive energy for phase B.
0x2B QUANT_WB 0
0x2C QUANT_VARB 0
0x2E QUANT_IC 0 Compensation factors for truncation and noise in current, real
energy and reac tive energy for phase C.
0x2F
QUANT_WC
0
0x30 QUANT_VARC 0
0x31 QUANT_ID 0 Com pensation f actor s for trunc ation and noise i n c ur r ent f or
phase D.
LSB weight s for use with the 71M6xx3 i sol ated sensors:
)(1020864.5__
2210
AmpsIMAXLSBIxQUANT ⋅⋅=
−
)(1059147.8__ 10 WattsIMAXVMAXLSBWxQUANT ⋅⋅⋅= −
)(1059147.8__
10
VarsIMAXVMAXLSBVARxQUANT ⋅⋅⋅=
−
LSB weight s for use with Cur r ent Tr ansformers (CTs):
)(1008656.5__
2213
AmpsIMAXLSBIxQUANT ⋅⋅=
−
)(1004173.1__
9
WattsIMAXVMAXLSBWxQUANT ⋅⋅⋅=
−
)(1004173.1__ 9VarsIMAXVMAXLSBVARxQUANT ⋅⋅⋅= −
71M6543F/H and 71M6543G /GH Data Sheet
130 © 2008–2011 Teridian Semi c onduc tor Corpor ation v1.2
5.4.10 CE Calibration Parameters
Table 87 lists the par ameters that ar e typic ally entered to effect calibration of meter accurac y .
Table 87: CE Calibrat ion Parameters
CE
Address Name Defau
lt Description
0x10 CAL_IA 16384
These constants contr ol the gai n of t heir r espect ive channels. The
nominal value for each para meter is 214 = 16384. The gain of each
channel is directl y pr opor tional to its CAL parameter. Thus, if the
gain of a channel is 1% low, CAL shoul d be incr eased by 1%.
0x11
CAL_VA
16384
0x13 CAL_IB 16384
0x14
CAL_VB
16384
0x16 CAL_IC 16384
0x17 CAL_VC 16384
0x19 CAL_ID 16384
0x12 PHADJ_A 0 The s e const ants c ontr ol t he CT p hase compe nsati on. No
compensation occurs when PHADJ_X = 0. As PHADJ_X is increased,
m or e compensation (lag) is i ntroduced. T he range is ± 215 – 1 . If it
is desired to del ay the c ur r ent by the angle Φ, the equat ions are:
Φ⋅−
Φ
=TAN
TAN
XPHADJ 0168.01714.0 029615.0
2_
20
at 60Hz
Φ⋅−
Φ⋅
=TAN
TAN
XPHADJ 01226.01430.0 0206.0
2_
20
at 50Hz
0x15 PHADJ_B 0
0x18 PHADJ_C 0
0x12 DLYADJ_A 0
The shunt delay com pensation is obtained using the equation
provided bel ow:
( )
+
+
∆+∆=
s
ss
reesrees
ff
c
b
ff
ab
ff
a
XDLYADJ
π
ππ
π
2
sin
2
cos2
2
cos
360
2
21.01_
22
14
degdeg
where:
Aa 2=
1
2
+= Ab
= 2+ 42
+ 2
f is the ma ins frequency
fs is the sampling frequency
The t able below provi des the v alue of A for each channel :
Channel V alue of A
(decimal)
DYADJ_A
13840
DLYADJ_B 11693
DLYADJ_C 9359
0x15 DLYADJ_B 0
0x18 DLYADJ_C 0
Note:
The cur r ent sensor inputs are not assigned t o the A, B and C phase s i n a fixed manner . T he
assignment s of phases A, B and C depends on how the IADC0-1, IADC2-3, IADC4-5, I A DC6-7 c urrent
sensing inputs are connec ted i n the meter desi gn. T he CE code must be aware of these connections.
See Figure 31 and Figure 32 for typical m eter c onfigurations. V A DC8, VA DC9 and VADC10 are
assigned t o voltage phases VA, VB and VC in a fixed manner, respect ively.
The CE addr esses listed in thi s table are assigned t o phases A, B and C as indic ated by their names.
71M6543F/H and 71M6543G /GH Data Sheet
v1.2 © 2008–2011 Teridian Sem iconduc tor Corpor ation 131
5.4.11 CE Flow Diagrams
Figure 39 through Figure 41 show the data f low through t he CE in simplified f orm. Functions not sho wn
inc lude delay c om pensation, sample interpol ation, scaling and t he pr oc essing of meter equations.
Figure 39: CE Data Flow : Multipl exer and ADC
Figure 40: CE Data Flow: Scaling, Gain Control, Intermediate Variables for one Phase
VREF
multiplexer
F
S
=
2184 Hz
∆∑
mod
Deci
-
mator
de
-
multiplexer
F
S
=
2184 Hz
IA_RAW
IA
VB
VA
IB
IC
VC
IB_RAW
VA_RAW
VB_RAW
IC_RAW
VC_RAW
I
D
I
D
_RAW
71M6543F/H and 71M6543G /GH Data Sheet
132 © 2008–2011 Teridian Semi c onduc tor Corpor ation v1.2
Figure 41: CE Data Flow : Squarin g and Summat io n Stages
v
IA
WA
SQUARE
WB
VARA
VARB
VA
IASQ
VASQ
IBSQ SUM IASQSUM_X
VASQSUM_X
ICSQSUM_X
SUM WASUM_X
WBSUM_X
VARASUM_X
VARBSUM_X
Σ
Σ
Σ
SUM_SAMPS = 2184
MPU
F0
I2
V2
WC
VARC
WCSUM_X
VARCSUM_X
IB
IC
VB
VC
ICSQ
VBSQ
VCSQ
IBSQSUM_X
VBSQSUM_X
VCSQSUM_X
F0
Σ
ID IDSQ IDSQSUM_X
71M6543F/H and 71M6543G /GH Data Sheet
v1.2 © 2008–2011 Teridian Sem iconduc tor Corpor ation 133
6 71M6543 Specifications
This sect ion prov ides the electric al specif icati ons for the 71M6543. Please refer to t he 71M 6xxx Data
Sheet for the 71M6xx 3 elec trical specif icati ons, pin-out and package m ec hanical dat a.
6.1 Absolute Maximum Ratings
Table 88 show s the abs olute maximum ratings for the device. Stresses beyond Absolute Maximum Ratings
m ay cause permanent dam age to t he dev ic e. These are stress ratings only and functional oper ation at
these or any ot her c onditi ons beyond t hose i ndicated under r ec om mended operating condit ions (See 6.3)
is not imp lied. Expos ur e to abs olute -maximum-rated conditions for extended periods m ay affect device
rel iabilit y . All voltages are wit h r espect to GNDA.
Table 88: Abso lu t e M aximu m Ratings
Voltage and Current
Supplies and Ground Pins
V3P3SYS, V3P3A −0.5 V to +4.6 V
VBAT, VB AT_RTC
-0.5 V to +4.6 V
GNDD -0.1 V to +0.1 V
A na log Output P ins
VREF -10 mA to +10 mA,
-0.5 V to V3P3A+0.5 V
VDD -10 mA to +10 mA,
-0.5 t o +3.0 V
V3P3D -10 mA to +10 mA,
-0.5 V to 4.6 V
VLCD -10 mA to +10 mA,
-0.5 V to +6 V
A na log Input Pins
IADC0, IADC1, IADC2, IADC3, IADC4, IADC5, IADC6, IADC7,
VADC8, VA DC9 and VADC10 -10 mA to +10 mA
-0.5 V to V3P3A+0.5 V
XIN, XOUT -10 mA to +10 mA
-0.5 V to +3.0 V
SEG and SEGDIO Pins
Configured as SEG or COM drivers -1 mA to +1 mA,
-0.5 V to VLCD+0.5 V
Configured as Di gital Inputs -10 mA to +10 mA,
-0.5 V to +6 V
Configured as Di gital Outputs -10 mA to +10 mA ,
-0.5 V to V3P 3D+0.5 V
Digital Pins
Inputs (PB, RESET, RX, ICE_E, TEST) -10 mA to +10 mA,
-0.5 t o 6 V
Outputs (TX) -10 mA to +10 mA,
-0.5 V to V3P 3D+0.5 V
Temperature
Operating junction temperature (peak, 100ms) 140 °C
Operating junction temperature (continuous) 125 °C
Stor age temperature −45 °C to +165 °C
Soldering temperature – 10 second duration 250 °C
71M6543F/H and 71M6543G /GH Data Sheet
134 © 2008–2011 Teridian Semi c onduc tor Corpor ation v1.2
6.2 Recommended External Components
Table 89: Recommended Extern al Co mponents
Name From To Function Value Unit
C1 V3P3A GNDA Bypass capacitor for 3.3 V suppl y ≥0.1 ±20% µF
C2 V3P3D GNDD Bypass capacit or for 3.3 V out put 0.1 ±20% µF
CSYS V3P3SYS GNDD Bypass capacitor for V3P3SYS ≥1.0 ±30% µF
CVDD VDD GNDD Bypass capacit or for VDD 0.1 ±20% µF
CVLCD VLCD GNDD Bypass capacitor for VLCD pin ≥0.1 ±20% µF
XTAL XIN XOUT 32.768 kHz crystal – electrically
equivalent to ECS .327-12.5-17X or
Vi shay XT26T , load capacitance 12. 5 pF 32.768 kHz
CXS XIN GNDA Load capacit or values for crystal depend
on crystal specifications and board
parasitics. Nominal values are based on
4 pF board c apaci tance and include an
allowance for c hip c apaci tance.
15 ±10% pF
CXL XOUT GNDA 10 ±10% pF
6.3 Recommended Operating Conditions
Unless otherwise speci fi ed, all parameters li sted under 6.4 Performance Specifications and 6.5 Timing
Specifications are valid over the Recommended Operating Conditions provided in Table 90 below.
Table 90: Recommended Operati ng Conditions
Parameter Condition Min Typ Max Unit
V3 P3SYS and V3P3 A Supply Voltage for precision
m etering operation (MSN mode). V oltages at
VBAT and VB AT_RTC need not be present.
VBAT=0 V to 3.8 V
VBAT_RTC =0 V t o
3.8 V 3.0 3.6 V
VBAT Voltage (BRN m ode). V3P3SY S i s bel ow
the 2. 8 V com par ator threshold. Either V3P3S YS
or VBAT_RTC must be high enough t o power the
RTC module.
V3P3SYS < 2.8 V
and
Max(VBAT_RTC,
V3P3SYS) > 2.0 V
2.5 3.8 V
VBAT_RTC Voltage. VB AT_RTC is not needed to
support the RTC and non-volatile memory unless
V3P3SYS<2.0 V V3P3SYS<2.0 V 2.0 3.8 V
Operating Temperature -40 +85 ºC
Notes:
1. GNDA and GNDD must be connected together.
2. V3P 3S Y S and V 3P 3A must be connected together.
71M6543F/H and 71M6543G /GH Data Sheet
v1.2 © 2008–2011 Teridian Sem iconduc tor Corpor ation 135
6.4 Performance Specifications
6.4.1 Input Logic Levels
Table 91: Input L ogic Levels
Parameter Condition Min Typ Max Unit
Digital hi gh-level input vo ltage
1
, VIH 2 V
Digital l ow-leve l input voltage
1
, V
IL
0.8 V
Input pullup current, I
IL
E_RXTX, E_ RST, E_TCLK
OPT_RX, OPT_TX
SPI _CS Z (S EGDIO 36)
Other d igital inputs
VIN=0 V,
ICE_E=3.3 V
10
10
10
-1
0
100
100
100
1
µA
µA
µA
µA
Input pull down current , I
IH
ICE_E, RESE T, TEST
Other d igital inputs
VIN=V3P3D
10
-1
0
100
1
µA
µA
Note:
1. In battery powered modes, digital i nputs s hould be below 0. 1 V or abo ve VBAT – 0.1 V to
minimize battery current.
6.4.2 Output Logic Levels
Table 92: Output Logic Levels
Parameter Condition Min Typ Max Unit
Digital hi gh-level output voltage
VOH
ILOAD = 1 mA
V3P3D–0.4
V
ILOAD = 15 mA
(see notes 1, 2) V3P3D-0.6 V
Digital l ow-leve l output voltage
VOL
ILOAD = 1 mA
0
0.4
V
ILOAD = 15 mA
(see note 1) 0 0.8 V
Note:
1. G uaranteed by design; not production tested.
2. Caution: The sum of all pull up currents must be com patible with the on-resistanc e of the
internal V3P 3D switc h. See 6.4.6 V3P3D Swi t ch on page 139.
71M6543F/H and 71M6543G /GH Data Sheet
136 © 2008–2011 Teridian Semi c onduc tor Corpor ation v1.2
6.4.3 Battery Monitor
Table 93: Bat t ery Monitor Performance Specifications (TEMP_BAT = 1)
Parameter Condition Min Typ Max Unit
BV: Battery Voltage
(definition)
MSN mode, TEMP_PWR = 1
BRN mode,
TEMP_PWR=TEMP_BSEL
 = 3.3+( 142)0.0246+ 297
 = 3.291+( 142)0.0255+ 328
V
Measurem ent Err or
−⋅ 1100 VBAT
BV
VBAT =
2.0 V
2.5 V
3.0 V
4.0 V
-7.5
-5
-3
-3
7.5
5
3
5
%
%
%
%
Input impedance in
continuous m easurement,
MSN mode.
V(VBAT_RTC)/I(VBAT_RTC)
V3P3 = 3.3 V,
TEMP_BSEL = 0,
TEMP_PER = 111,
VBAT_RTC = 3.6 V, 1 MΩ
Load applied wit h BCURR
IBAT(BCURR=1) - IBAT(BCURR=0)
V3P3 = 3 .3 V 50 100 140 µA
71M6543F/H and 71M6543G /GH Data Sheet
v1.2 © 2008–2011 Teridian Sem iconduc tor Corpor ation 137
6.4.4 Temperature Monitor
Table 94: T emperature Monitor
Parameter Condition Min Typ Max Unit
Temper ature Measurement
Equation for 71M6543F and
71M6543G
(see note s 2 and 4)
In MSN , TEMP_PWR=1:
 = 0.325  +22
In BRN, TEMP_PWR = TEMP_BSEL:
 = 0.325  + 0.00218 0.609  +64.4
°C
Temperature Measurement
Equation for 71M6543H and
71M6543GH
(see note s 3 and 4)
In MSN , TEMP_PWR=1:
If STEMP ≤ 0:
 = 0.325  +22
If STEMP > 0:
 =63 
_85 +22
In BRN, TEMP_PWR = TEMP_BSEL:
If STEMP ≤ 0:
 = 0.325  + 0.00218 0.609  +64.4
If STEMP > 0:
 =
63 
_85 + 0.00218 
0.609  +64.4
Temper ature Er r or (71M6543)
(see note 1)
TA = 22⁰C
-2
2 °C
VBAT_RTC charge per
measurement TEMP_BSEL = 0,
TEMP_PWR=0,
SLP Mode,
VBAT_RTC = 3.6 V 16 µC
Duration of tem per ature
m easurement after setti ng
TEMP_START
(see note 1)
15 60 ms
Notes:
1. G uaranteed by design; not production tested.
2. F or the 71M6543F and 71M6543G , TEMP_85 fuses read 0.
3. F or the 71M6543H and 71M6543GH, TEMP_85 fuses ≠ 0.
4. T he c oeff icients provi ded in these equations are typical.
71M6543F/H and 71M6543G /GH Data Sheet
138 © 2008–2011 Teridian Semi c onduc tor Corpor ation v1.2
6.4.5 Supply Current
The supply c ur r ents provi ded in Table 95 below include only the current consumed by the 71M6543.
Refer to the 71M6xxx Data Sheet for additional c urrent requi r ed when usi ng a 71M 6x03 remote sensor.
Table 95: Supply Current Performance Specifications
Parameter Condition Device Min Typ Max Unit
I1:
V3P3A + V3P3SYS current,
Normal Operation
Polyphase: 4 Currents, 3 Voltages
V3P3A = V3P3SYS = 3.3 V,
MPU_DIV [2:0]= 3 (614 kHz MPU clock),
No Fla sh memory write,
RTM_E=0, PRE_E=0, CE_E=1, ADC_E=1,
ADC_DIV=0, MUX_DIV[3:0]=7,
FIR_LEN[1:0]=1, PLL_FAST=1
71M6543F/H 7.2 8.5
mA
71M6543G/GH 7.5 8.8
I1a:
V3P3A + V3P3SYS current,
ADC Half Rate
(ADC_DIV=1)
S am e as I1, except ADC_DIV=1, FIR_LEN=0
71M6543F/H 6.4 7.3 mA
71M6543G/GH 6.7 7.7
I1b:
V3P3A + V3P3SYS current,
Normal Operation
PLL_FAST=0
S am e as I1, except PLL_FAST=0 71M6543F/H 2.9 3.8 mA
71M6543G/GH 3.0 3.9
I1c:
V3P3A + V3P3SYS current,
Normal Operation
PRE_E=1
S am e as I1, except PRE_E=1 71M6543F/H 7.3 8.7 mA
71M6543G/GH 7.7 9.1
I1d:
V3P3A + V3P3SYS current,
Normal Operation
PRE_E=1, ADC_DIV=1,
FIR_LEN=0.
(s ee n ote 1)
S am e as I1, except PRE_E=1, ADC_DIV=1,
FIR_LEN=0.
71M6543F/H 6.5 7.5
mA
71M6543G/GH 6.9 7.9
I1e:
V3P3A + V3P3SYS current,
Normal Operation
PLL_FAST=0, PRE_E=1.
(s ee n ote 1)
S am e as I1, except PRE_E=1, PLL_FAST=0. 71M6543F/H 3.0 3.9 mA
71M6543G/GH 3.1 3.9
I2:
V3P3A + V3P3SYS dynamic
current
Same as I1, except with variation of
MPU_DIV[2:0].
4.3
I-I 3MPU_DIV0MPU_DIV ==
71M6543F/H 0.4 0.6 mA/
MHz
71M6543G/GH 0.5 0.65
VBAT current
I3: MS N Mod e
I4: BRN M od e
I5: LCD Mode (ext. VLCD)
I6: LCD Mode (boost, DAC)
I7: LCD Mode (DAC)
I8: LCD Mode (VBAT)
I9: S LP M od e
CE_E=0
LCD_VMODE[1:0]=3, also see note 3
LCD_VMODE[1:0]=2, also see n otes 1, 2
LCD_VMODE[1:0]=1, also see n otes 1, 2
LCD_VMODE[1:0]=0, also see n otes 1, 2
SLP M od e
71M6543
71M6543F/H
71M6543G/GH
71M6543
71M6543
71M6543
71M6543
71M6543
-300
-300
0
2.4
2.6
0.4
24
3.0
1.1
0
300
3.2
3.5
108
36
11
3.4
+300
nA
mA
mA
nA
µA
µA
µA
nA
VBAT_RT C current
I10: MSN
I11: BRN
I12: LCD Mode
I13: SLP M ode
I14: SLP M ode (see note 1)
LCD_VMODE[1:0]=2, also see note 3
TA ≤ 25 °C
TA = 85 °C
71M6543
71M6543F/G
71M6543G/GH
71M6543
71M6543
71M6543
-300
0
240
260
1.8
0.7
1.5
300
410
420
4.1
1.7
3.2
nA
nA
nA
µA
µA
µA
I15:
V3P3A + V3P3SYS current,
Write Fl as h with ICE
S am e as I1, except writ e Flash at maximum rate,
CE_E=0, ADC_E=0. 71M6543F/G 7.1 8.7 mA
71M6543G/GH 7.3 8.7
Notes:
1. Guaranteed by design; not production tested.
2. LCD_DAC[4:0]=5 (2.9V), LCD_CLK[1:0]=2, LCD_MODE[2:0]=6, all LCD_MAPn bits = 0.
3. LCD_DAC[4:0]=5 (2.9V), LCD_CLK[1:0]=2, LCD_MODE[2:0]=6, LCD_BLANK=0, LCD_ON=1, all LCD_MAPn bits = 1 and VLCD pin = 3.3V.
71M6543F/H and 71M6543G /GH Data Sheet
v1.2 © 2008–2011 Teridian Sem iconduc tor Corpor ation 139
6.4.6 V3P 3D Switch
Table 96: V 3P 3D Switch Performance Specifications
Parameter Condition Min Typ Max Unit
On resi stanc e – V3P3SYS to V3P3D | I V3P3D | ≤ 1 mA 10 Ω
On resi stanc e – VBAT to V3P3D | IV3P3D | ≤ 1 mA,
VBAT>2.5V 10 Ω
V3P3D I OH, MS N V3P3SYS = 3V
V3P3D = 2. 9V 10 mA
V3P3D I OH, B RN VBAT = 2.6V
V3P3D = 2. 5V 10 mA
6.4.7 Internal Power Fault Comparators
Table 97: In t ernal Po wer F aul t Comp arat ors Performance Specifications
Parameter Condition Min Typ Max Unit
Overall response time 100mV overdrive , falling
100m V ov er drive, rising 20
200
200 µs
µ
s
Falling Thr eshol d
3.0 V Comparator
2.8 V Comparator
Diff er enc e 3.0V and 2.8V Com par ators
V3P3 falling
2.83
2.75
50
2.93
2.81
136
3.03
2.87
220
V
V
mV
Falling Thr eshol d
2.25 V Comparator
2.0 V Comparator
VDD (@VBAT=3.0V) – 2.25V Comparator
Diff er enc e 2.25V and 2.0V Com par ators
VDD falling
2.2
1.90
0.25
0.15
2.25
2.00
0.35
0.25
2.5
2.20
0.45
0.35
V
V
V
V
Hysteresis,
(Rising T h r eshold - Falling Threshold)
3.0 V Comparator
2.8 V Comparator
2.25 V Comparat or
2.0 V Comparator
TA = 22 °C
22
25
10
10
45
42
33
28
65
60
60
60
mV
mV
mV
mV
6.4.8 2.5 V Voltage Regulator – Syst em P ower
Table 98: 2.5 V Voltage Regulator P erf ormance Specification s
Parameter Condition Min Typ Max Unit
V2P5
V3P3 = 3. 0 V - 3.8 V
I
LOAD
=
0
mA
2.55 2.65 2.75 V
V2P5 load regulati on
V3P3 = 3. 3 V
ILOAD = 0 mA to 5 mA
40 mV
Vol tage overhead V 3P 3SYS-V2P5
I
LOAD
=
5 mA,
Reduce V3P3D until V2P5
drops 200 mV
440 mV
71M6543F/H and 71M6543G /GH Data Sheet
140 © 2008–2011 Teridian Semi c onduc tor Corpor ation v1.2
6.4.9 2.5 V Voltage Regulator – Battery Power
Table 99: Low-Power Voltage Regul ator P erformance Specifications
Parameter Condition Min Typ Max Unit
V2P5
VBAT = 3.0 V - 3.8 V,
V3P3 = 0 V, I
LOAD
=
0
mA
2.55 2.65 2.75 V
V2P5 load regulati on
VBAT = 3. 3 V, V3P3 = 0 V,
I
LOAD
=
0
mA to 1 mA
40 mV
Voltage Overhead 2V − VBAT-VDD
I
LOAD
=
0ma, VBAT = 2.0 V,
V3P3 = 0 V.
200 mV
6.4.10 Crystal Oscillator
Table 100: Cryst al Oscillator Performance Specifications
Parameter Condition Min Typ Max Unit
Maximum Output Power to Crystal
Crystal connected, see note 1
1
μW
XIN to XOUT Capaci tance
(see note 1)
3 pF
Capaci tance change on XOUT
RTC_ADJ = 7F to 0,
Bias voltage = unbiased
Vpp = 0.1 V
15 pF
Note:
1. G uar anteed by design; not pr oduc tion t ested.
6.4.11 Phase-Locked Loop (PLL)
Table 101: PLL Perfo rmance Specificat ions
PARAMETER
CONDITION
MIN
TYP
MAX
UNIT
PLL Power-up Set tli ng Time
PLL_FAST =0,
V3P3 = 0 t o 3.3 V step
Measured from first edge of MCK
(TM UX2OUT pin)
3 ms
PLL_FAST settling time
PLL_FA S T rise
PLL_FAST fall
V3P3=0, VBAT= 3.8 t o 2.0 V
3
3
ms
ms
PLL SLP to MSN Set tling Tim e
PLL_FAST =0
3
ms
6.4.12 LCD Drivers
Table 102: LCD Dri vers P erf ormance Speci f ications
PARAMETER
CONDITION
MIN
TYP
MAX
UNIT
VLCD Current
VLCD=3.3 , all LCD map bits=0
VLCD=5.0 , all LCD map bits=0
2
3
uA
uA
Note:
1. T hese specifi c ations apply t o all COM and SEG pi ns.
1. LCD_VMODE=3, LCD_ON=1, LCD_BLANK=0, LCD_MODE=6, LCD_CLK=2.
2. O utput load is 74 pF per SEG and COM pin.
6.4.13 VLCD Generator
Table 103: V LCD G enerator Specifications
71M6543F/H and 71M6543G /GH Data Sheet
v1.2 © 2008–2011 Teridian Sem iconduc tor Corpor ation 141
Parameter Condition Min Typ Max Unit
VSYS to VLCD switch impedance
V3P3 = 3.3 V,
RVLCD=removed, LCD_BAT=0,
LCD_VMODE[1:0]=0,
∆ILCD=10 µA
750 Ω
VBAT t o VLCD swit c h im p edance
V3P3 = 0 V, VBAT = 2.5 V,
RVLCD =removed, LCD_BAT =1,
LCD_VMODE[1:0]=0,
∆ILCD=10 µA
700 Ω
LCD Boost Frequency
LCD_VMODE[1:0] = 2,
RVLCD = removed,
CVLCD = removed
PLL_FAST=1
PLL_FAST=0
820
786
kHz
kHz
VLCD IOH current
(VLCD(0)-VLCD(IOH)<0.25)
LCD_VMODE[1:0] = 2,
LCD_CLK[1:0] = 2 ,
RVLCD = removed,
V3P3 = 3.3V,
LCD_DAC[4:0]
= 1F
10 µA
From LCDADJ0 and LCDADJ12 fu ses:
(_)= 50 + 12 0
12
_
(_)= 2.65 + 2.65 _
31 +(_)
The above equati ons descri be the nominal value of VLCD for a specifi c LCD_DAC value. The
specif ications below list t he m aximum dev iation between actual VLCD and VLCDnom . Note that when
VCC and boost are insufficient, the LCD DAC will not reach it s tar get value and a large negative error
will oc c ur .
LCD_DAC Error. VLCD-VLCDnom
Full Scale, with Boost
V3P3 =3.6 V
V3P3 =3.0 V
VBAT=4.0 V, V3P3=0, BRN Mode
VBAT=2.5 V, V3P3=0, BRN Mode
LCD_VMODE = 10,
LCD_DAC[4:0] = 1F,
LCD_CLK[1:0]=2,
LCD_MODE[2:0]=6
-0.15
-0.4
-0.15
-1.3
0.15
0.15
0.15
V
V
V
V
LCD_DAC Error. VLCD-VLCDnom
DAC=12, with Boost
V3P3 = 3.6 V
V3P3 = 3.0 V
VBAT = 2.5 V, V3 P3 = 0 V, BRN Mode
LCD_VMODE = 10,
LCD_DAC[4:0] = C,
LCD_CLK[1:0]=2,
LCD_MODE[2:0]=6
-0.15
-0.15
-0.15
0.15
0.15
0.15
V
V
V
LCD_DAC Error. VLCD-VLCDnom
Zero S cale, w ith Boost
V3P3 = 3.6 V
V3P3 = 3.0 V
VBAT = 4.0 V, V3 P3 = 0 V, BRN Mode
VBAT = 2.5 V, V3 P3 = 0 V, BRN Mode
LCD_VMODE = 2,
LCD_DAC[4:0] =0,
LCD_CLK[1:0]=2,
LCD_MODE[2:0]=6
-0.15
-0.15
-0.15
-0.15
0.15
0.15
0.15
0.15
V
V
V
V
LCD_DAC Error. VLCD-VLCDnom
Full Scale, no Boost
V3P3 = 3.6 V ( see no te 1)
V3P3 = 3.0 V ( see no te 1)
VBAT = 4.0 V, V3 P3 = 0 V, BRN Mode
VBAT = 2.5 V, V3 P3 = 0 V, BRN Mode
LCD_VMODE = 1,
LCD_DAC[4:0] = 1F,
LCD_CLK[1:0]=2,
LCD_MODE[2:0]=6
-2.1
-2.8
-1.8
-3.2
V
V
V
V
LCD_DAC Error. VLCD-VLCDnom
DAC=12, no Boost
V3P3 = 3.6 V
V3P3 = 3.0 V
VBAT = 4.0 V, V3 P3 = 0 V, BRN Mode
VBAT = 2.5 V, V3 P3 = 0 V, BRN Mode
LCD_VMODE = 1,
LCD_DAC[4:0] = C,
LCD_CLK[1:0]=2,
LCD_MODE[2:0]=6
-0.5
-1.1
-0.151
-1.51
0.151
V
V
V
V
71M6543F/H and 71M6543G /GH Data Sheet
142 © 2008–2011 Teridian Semi c onduc tor Corpor ation v1.2
Parameter Condition Min Typ Max Unit
LCD_DAC Error. VLCD-VLCDnom
Zero S cale, no Boost
V3P3 = 3.6 V
V3P3 = 3.0 V
VBAT = 4.0 V, V3 P3 = 0 V, BRN Mode
VBAT = 2.5 V, V3 P3 = 0 V, BRN Mode
LCD_VMODE = 01,
LCD_DAC[4:0] = 0,
LCD_CLK[1:0]=2,
LCD_MODE[2:0]=6
-0.15
-0.15
-0.15
-0.45
0.15
0.15
0.15
0.15
V
V
V
V
LCD_DAC Error. VLCD-VLCDnom
Full Scale, with Boost, LCD mode
VBAT = 4.0 V, V3 P3 = 0 V
VBAT = 2.5 V, V3 P3 = 0 V
LCD_VMODE = 1,
LCD_DAC[4:0] = 1F,
LCD_CLK[1:0]=2,
LCD_MODE[2:0]=6
-0.15
-1.3
0.15
V
V
Note:
1. Guaranteed by desi gn; not producti on tested.
2. The following test condit ions also apply to a ll paramet ers provided in this tab le: bypass capacitor CVLCD ≥
0.1 µF, test load RVLCD = 500 kΩ, no displ ay, all SEGDIO pins configured as DIO.
71M6543F/H and 71M6543G /GH Data Sheet
v1.2 © 2008–2011 Teridian Sem iconduc tor Corpor ation 143
6.4.14 71M6543 VREF
Table 104 shows the performanc e specif ic ations f or the 71M6543 ADC ref er enc e v oltage (VREF).
Table 104: 71M6543 VREF Performance Specifications
Parameter Condition Min Typ Max Unit
VREF output voltage,
VREF(22)
T
A
= 22 ºC
1.193 1.195 1.197 V
VREF output voltage,
VREF(22)
PLL_FAST=0
1.195 V
VREF chop step, trimmed
VREF(CHOP=01) −
VREF(CHOP=10)
-10 10 mV
VREF power supply sensitivity
ΔVREF / ΔV3P3A
V3P3A = 3.0 to 3.6 V -1.5 1.5 mV/V
VREF input impedance
VREF_DIS = 1,
VREF = 1 .3 V to 1.7 V
100 kΩ
VREF output impedance
VREF_CAL = 1,
I
LOAD
= 10 µA, -10 µA
3.2 kΩ
VNOM definition (see note 2)
2)22(1)22()22()( 2TCTTCTVREFTVNOM −+−+=
V
If temperature characterization trim information is available (71M6543H and 71M6543G H, 0.1%)
VNOM temperature
coefficients:
TC1 =
TC2 =
35.091+0.01764+1.587()
0.557 2.8 10 
µV/°C
µV/°C2
VREF(T) de viation from
VNOM(T) (see note 1):
62
10
)( )()(
6
TVNOM TVNOMTVREF −
-10 +10 ppm/°C
If temperature characterization trim information is not available (71M6543F and 71M6543G , 0. 5%)
VNOM temperature
coefficients:
TC1 =
TC2 =
TRIMT⋅− 95.4275
TRIMT⋅+− 00028.0557.0
µV/°C
µV/°C2
VREF(T) de viation from
VNOM(T) (see note 1):
62
10
)( )()(
6
TVNOM TVNOMTVREF −
-40 +40 ppm/°C
VREF aging
±25
ppm/
year
Notes:
1. G uar anteed by design; not pr oduc tion t ested.
2. T his rel ationship describes the nomi nal behav ior of VREF at dif ferent tem per atures, as
gov er ned by a second order polynomi al of 1st and 2nd or der c oeff icients TC1 and T C2.
3. F or the parameters i n this table, unless otherwise specifi ed, VREF_DIS = 0, PLL_FAST=1
71M6543F/H and 71M6543G /GH Data Sheet
144 © 2008–2011 Teridian Semi c onduc tor Corpor ation v1.2
6.4.15 ADC Converter
Table 105: ADC Con vert er P erf ormance Speci ficat io ns
Parameter Condition Min Typ Max Unit
Recommended I nput Range
(Vin - V3P3A)
-250
250
mV
peak
Vol tage to Current Cr osstal k
)cos(
*10
6
VcrosstalkVin
Vin
Vcrosstalk ∠−∠
( see no te 1)
Vin = 200 mV peak,
65 Hz, on VADC8 (VA) or
VADC9 (V B ) or V A DC10
(VC).
Vcrosstalk = largest
measurement on IADC0-1
or IADC2-3 or IADC4-5 or
IADC6-7
-10 10 μV/V
Input Impedance, no pre-amp
Vin=65 Hz
40
90
kΩ
A
DC Gain Error vs %Power Suppl y
Variation
3.3/33100 /357106
APV VnVNout INPK
∆
∆
Vin=200 mV pk, 65 Hz
V3P3A=3.0 V, 3 .6 V
50 ppm / %
Input Of fset
IADC0=IADC1=V3P3A
IADC0=V3P3A
DIFF0_E=1, PRE_E=0
DIFF0_E
=0,
PRE_E
=0
-10
-10
10
10
mV
mV
THD @ 250mVpk
Name
FIR_LEN
ADC_DIV
PLL_FAST
MUX_DIV
A
0
0
0
3
B
1
0
0
2
C
0
0
1
11
D
1
0
1
6
E
2
0
1
4
F
0
1
0
2
G 0 1 1 6
H
1
1
1
3
J
2
1
1
2
V
IN
= 65Hz, 2 5 0 mV p k,
64kpts FFT, Blackman Harris
Window.
A
B
-82
C
D
-84
E
F
-83
G
H
-86
J
A -75
B
-75
C
-75
D
-75
E -75
F
-75
G
-75
H
-75
J -75
dB
THD @ 20mVpk
Name
FIR_LEN
ADC_DIV
PLL_FAST
MUX_DIV
A
0
0
0
3
B 1 0 0 2
C
0
0
1
11
D
1
0
1
6
E
2
0
1
4
F 0 1 0 2
G
0
1
1
6
H
1
1
1
3
J
2
1
1
2
V
IN
= 65Hz, 2 0 mVp k,
64kpts FFT, Blackman Harris
Window.
A
-85
B
-91
C -85
D
-91
E
-93
F
-85
G -85
H
-91
J
-93
dB
LSB Si ze:
Name
FIR_LEN
ADC_DIV
PLL_FAST
MUX_DIV
A
0
0
0
3
B 1 0 0 2
C
0
0
1
11
D
1
0
1
6
E
2
0
1
4
F 0 1 0 2
G
0
1
1
6
H
1
1
1
3
J
2
1
1
2
Vi n=65Hz, 20mVpk,
64kpts FFT, Blac kman-
Harris window
A
3470
B
406
C
3040
D
357
E
151
F
3470
G
3040
H
357
J
151
nV
Dig ital Full -Scale:
Name
FIR_LEN
ADC_DIV
PLL_FAST
MUX_DIV
A 0 0 0 3
B 1 0 0 2
C
0
0
1
11
D
1
0
1
6
E
2
0
1
4
F 0 1 0 2
G
0
1
1
6
H
1
1
1
3
J
2
1
1
2
A: ±91125
B: ±778688
C: ±103823
D: ±884736
E: ±2097152
F: ±91125
G: ±1038 23
H: ±884736
J: ±2097152
LSB
71M6543F/H and 71M6543G /GH Data Sheet
v1.2 © 2008–2011 Teridian Sem iconduc tor Corpor ation 145
Parameter Condition Min Typ Max Unit
Note:
1. G uar anteed by design; not pr oduc tion t ested.
2. Unless stated other wise, t he foll owing test condit ions apply to all the paramet er s provided in
this tabl e: FIR_LEN[1:0]=1, VREF_DIS=0, PLL_FAST=1, ADC_DIV=0, MUX_DIV=6, LSB values
do not include t he 9-bit left shift at CE i nput.
6.4.16 Pre-Amplifier for IADC0-IADC1
Table 106: Pre-A mplifier Performance Specifications
PARAMETER
CONDITION
MIN
TYP
MAX
UNIT
Differen tia l Gain
Vin=30mV differential
Vi n=15mV diff er ential (see note 1)
T
A
= 5
⁰
C,
V3P3=3.3 V,
PRE_E=1,
FIR_LEN=2,
DIFF0_E=1,
2520Hz sample rate
7.8
7.8
7.92
7.92
8.0
8.0
V/V
V/V
Gain Varia tion vs V3P3
Vi n=30mV diff er ential (see note 1)
V3P3 =
2.97 V, 3.63 V
-100 100 ppm/%
Gain Variation vs Temp
Vi n=30mV diff er ential (see note 1)
TA = -40⁰C, 85⁰C 10 -25 -80 ppm/C
Phase Shift,
Vi n=30mV diff er ential (see note 1)
T
A
=25
⁰
C,
V3P3=3.3 V -6 6 mº
Preamp input curr ent
IADC0
IADC1
PRE_E=1,
FIR_LEN=10,
DIFF0_E=1
2520Hz sample rate,
IADC0=IADC1=V3P3
4
4
9
9
16
16
uA
uA
Preamp+ADC THD
Vi n=30mV diff er ential
Vi n=15mV diff er ential
T
A
=25
⁰
C,
V3P3=3.3 V,
PRE_E=1,
FIR_LEN=2,
DIFF0_E=1,
2520Hz sample rate.
-82
-86
dB
dB
Preamp Offset
IADC0=IADC1=V3P3+30mV
IADC0=IADC1= V3P3+15 mV
IADC0=IADC1= V3P3
IADC0=IADC1= V3P3-15mV
IADC0=IADC1= V3P3-30mV
T
A
=25
⁰
C,
V3P3=3.3 V,
PRE_E=1,
FIR_LEN=10,
DIFF0_E=1,
2520Hz sample rate
-0.63
-0.57
-0.56
-0.56
-0.55
mV
mV
mV
mV
mV
Note:
1. G uar anteed by design; not pr oduc tion t ested.
71M6543F/H and 71M6543G /GH Data Sheet
146 © 2008–2011 Teridian Semi c onduc tor Corpor ation v1.2
6.5 Timing Specifications
6.5.1 Flash Memory
Table 107: Flash Memory Timing Specifications
Parameter Condition Min Typ Max Unit
Flash wri te cycl es
-40 °C t o +85 °C
20,000
Cycles
Flash data ret ention
25 °C
85 °C
100
10
Years
Flash byte writes between page or
m ass erase operati ons
2 Cycles
Write Time per Byte
21
µs
Page Erase (1024 bytes)
21
ms
Mass Erase
21
ms
6.5.2 SPI Slave
Table 108. SPI Slave Timing Specifications
Parameter
Condition
Min
Typ
Max
Unit
SPI Setup Time
SPI _DI to SPI_CK rise
10
ns
SPI Hold Time
SPI _CK ri se to SPI _DI
10
ns
SPI Output Delay
SPI_CK fall to SPI_D0
40
ns
SPI Rec ov er y Tim e
SPI _CS Z f all to SPI_CK
10
ns
SPI Removal Time
SPI _CK to SPI_CS Z ri se
15
ns
SPI Cloc k Hi gh
40
ns
SPI Cloc k Low
40
ns
SPI Clock F req
SPI Freq/MPU Freq
2.0
MHz/MHz
SPI Transaction Space
SPI _CS Z rise to S PI_CS Z f all
4.5
MPU Cycl es
6.5.3 EEPROM Interface
Table 109: EEPROM Interface Ti ming
Parameter Condition Min Typ Max Unit
Write Clock frequenc y (I2C)
CKMPU = 4.9 MHz,
Using i nterrupts
310 kHz
CKMPU = 4.9 MHz,
bit-banging DIO2/3
PLL_FAST = 0
100 kHz
Write Clock frequenc y ( 3-wire)
CKMPU = 4.9 MHz
PLL_FAST = 0
PLL_FAST = 1
160
500
kHz
71M6543F/H and 71M6543G /GH Data Sheet
v1.2 © 2008–2011 Teridian Sem iconduc tor Corpor ation 147
6.5.4 RESET Pin
Table 110: RESET Pin Timing
Parameter Condition Min Typ Max Unit
Reset pulse width
5
µs
Reset pulse fall time (see note 1)
1
µs
Note:
1. G uar anteed by design; not pr oduc tion t ested.
6.5.5 Real-Time Cloc k (RTC)
Table 111: RTC Ran ge for Date
Parameter Condition Min Typ Max Unit
Range for date
2000
−
2255
year
71M6543F/H and 71M6543G /GH Data Sheet
148 © 2008–2011 Teridian Semi c onduc tor Corpor ation v1.2
6.6 100-Pin LQFP Package Outline Drawing
Controlling dimensions are in mm .
Figure 42: 100-pin LQFP Package Outline
1
15.7(0.618)
16.3(0.641)
15.7(0.618)
16.3(0.641)
Top View
MAX. 1.600
0.50 TYP.
14.000 +/- 0.200
0.225 +/- 0.045
0.60 TYP>
1.50 +/- 0.10
0.10 +/- 0.10
Sid e Vi ew
71M6543F/H and 71M6543G /GH Data Sheet
v1.2 © 2008–2011 Teridian Sem iconduc tor Corpor ation 149
6.7 71M6543 Pinout
1
Teridian
71M6543F
71M6543H
71M6543G
71M6543GH
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
91
92
93
94
95
96
97
98
99
10026
27
28
29
30
51
52
53
54
55
56
57
58
59
60
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
SEGDIO17
TMUXOUT/SEG47
SPI_DI/SEGDIO38
TX
V3P3D
SEGDIO1/VPULSE
SEGDIO3/SDATA
SPI_CSZ/SEGDIO36
V3P3SYS
COM1
COM2
COM3
COM0
SEGDIO45
NC
XIN
GNDD
VBAT
ICE_E
SEGDIO52
OPT_TX/SEGDIO51
VADC9
VADC10
V3P3A
GNDA
VADC8
PB
VLCD
TEST
OPT_RX/SEGDIO55
IADC5
XOUT
IADC0
IADC3
IADC4
IADC1
IADC2
IADC6
SEGDIO27/COM4
IADC7
SPI_DO/SEGDIO37
SEGDIO26/COM5
SEGDIO25
SEGDIO24
SEGDIO23
SEGDIO22
SEGDIO21
SEGDIO20
SEGDIO19
SEGDIO35
SEGDIO33
SEGDIO32
SEGDIO30
SEGDIO29
SEGDIO31
SEGDIO28
SEGDIO34
SEGDIO18
GNDA
VBAT_RTC
E_RXTX/SEG48
E_TCLK/SEG49
E_RST/SEG50
RX
SEGDIO53
RESET
TMUX2OUT/SEG46
SEGDIO44
SEGDIO43
SEGDIO42
SEGDIO41
SEGDIO40
SPI_CKI/SEGDIO39
SEGDIO16
SEGDIO15
SEGDIO14
SEGDIO13
SEGDIO10
SEGDIO11
SEGDIO12
SEGDIO9
SEGDIO8/DI
SEGDIO7/YPULSE
SEGDIO6/XPULSE
SEGDIO5
SEGDIO4
SEGDIO2/SDCK
SEGDIO0/WPULSE
SEGDIO54
VREF
NC
NC
NC
NC
VDD
NC
NC
NC
NC
NC
Figure 43: Pinout for the LQFP-100 Package
71M6543F/H and 71M6543G /GH Data Sheet
150 © 2008–2011 Teridian Semi c onduc tor Corpor ation v1.2
6.8 71M6543 Pin Descriptions
6.8.1 71M6543 Power and Ground Pins
Pin types: P = Power, O = Output, I = Input, I/O = Input/Output. The circuit number denotes the equivalent
circuit, as specified under Section 6.8.4 I/O Equivalent Circ uits.
Table 112: 71M6543 Power and Ground Pins
Pin Name Type Circuit Function
72, 80 GNDA P — Analog Ground. This pin should be connected directly to the
ground plane.
62 GNDD P — Digital Ground. This pin shoul d be c onnec ted directly to t he
ground pl ane.
85 V3P3A P — Analog Power Suppl y . A 3.3 V power suppl y shoul d be
connect ed to this pi n. V3P 3A must be the same volt age as
V3P3SYS.
69 V3P3SYS P — System 3.3 V Supply. This pin should be connected to a 3.3 V
power supply.
61 V3P3D O 13
Auxiliary Voltage Outp ut of the Chip. In mi s si on mod e, thi s
pin is connect ed to V3P3S YS by the int er nal sel ec tion switch.
In BRN mode, it is in ternally connected to VBAT. V3P3D is
floating in LCD and sl eep m ode. A by pass capaci tor t o ground
should not exc eed 0.1 µF.
60 VDD O — Output of t he 2.5 V Regulator. This pi n is powered in MSN and
BRN modes. A 0.1 µF bypass capacitor to ground should be
connect ed to this pi n.
89 VLCD O — Output of the LCD DAC. A 0.1 µF bypass capaci tor t o ground
should be connected to this pin.
70 VBAT P 12 Battery Backup Pin to Support the Battery Modes (BRN, LCD) .
A battery or super capacitor i s to be connect ed between VB A T
and GNDD. If no batt er y i s used, connect VBAT to V3P3SYS .
71 VBAT_RTC P 12 RT C and Oscillator Power Supply. A battery or super-capacitor
is to be c onnec ted between VBAT and G NDD. If no batt er y is
used, connect V B A T_RTC to V3P3SYS.
71M6543F/H and 71M6543G /GH Data Sheet
v1.2 © 2008–2011 Teridian Sem iconduc tor Corpor ation 151
6.8.2 71M6543 Analog Pins
Pi n types: P = Power, O = Out put, I = Inpu t, I/O = Inpu t/Outpu t. The ci rcuit num ber denotes the equivalent
circuit, as specified in Section 6.8.4.
Table 113: 71M6543 Analog Pins
Pin Name Type Circuit Function
87
86 IADC0
IADC1
I 6
Differ ential or Si ngle-Ended A nalog Line Current Sense
Input s. These pins are voltage inputs to t he internal A/D
convert er. Typic ally, t hey are connec ted to the outputs of
current sensors. Unus e d pi ns m us t be connected to
V3P3A.
When co nfigur ed as dif ferenti al input s (i.e., by setting the
DIFFx_E control bits, wh ere x = 0, 2, 4, 6) pins are paired t o
form differential inputs pairs: IADC0-IADC1, IADC2-IADC3,
IADC4-IADC5, and IADC6-IADC7.
IADC2-IADC3, IADC4-IADC5, a nd IA DC6-I ADC7 can be
configured for communication wi th the 71M 6xx3 remote
isol ated sensor interface (i .e., by set ting the RMTx_E
contr ol bit s, where x = 2, 4, 6). When confi gur ed as remote
sensor interf ac es, these pins form balanc ed digit al pairs f or
bidirectional digit al c ommunications with a 71M6xx3
remote isolated sensor.
68
67 IADC2
IADC3
66
65 IADC4
IADC5
64
63 IADC6
IADC7
84 VADC8 (VA)
I 6
Line V oltage Sense Input s. These pins are voltage inputs
to t he internal A/D conv er ter. Typically, they are connected
to t he outputs of resistor divider s. Unused pins must be
con nected to V3P3A.
83 VADC9 (VB)
82 VADC10 (VC)
88 VREF O 9 Volt age Reference for the ADC. T his pi n shoul d be lef t
unconnect ed ( fl oating).
75 XIN I
8
Crystal Inputs. A 32 kHz crystal should be connec ted
across these pi ns. Typically, a 15 pF capacitor is also
connected from XIN to GNDA and a 10 pF c apaci tor is
con nected from XOUT to GNDA. It is important to
minimize the capacitance between these pins. See the
crystal manufacturer data sheet for det ails. If an ex ternal
cl oc k i s used, a 150 mV (p-p) cloc k si gnal shoul d be
applied t o XIN, and XOUT should be left unconnected.
76 XOUT O
71M6543F/H and 71M6543G /GH Data Sheet
152 © 2008–2011 Teridian Semi c onduc tor Corpor ation v1.2
6.8.3 71M6543 Digital Pins
Pin types: P = Power, O = Output, I = Input, I/O = Input/Output, N/C = no connect. The circuit number
denotes the equivalent ci r c uit, as specified in Section 6.8.4.
Table 114: 71M6543 Digital Pi ns
Pin Name Type Circuit Function
12–15 COM0–COM3 O 5
LCD Common Outputs. These four pins provide the select
signal s for the LCD display .
45 SEGDIO0/WPULSE
I/O 3, 4, 5
Multiple-Use Pins. Configurable as either LCD segment
driver or DIO. Alt er native functions wi th proper sel ec tion of
associated I/O RAM register s are:
SEGDIO0 = WPULSE (45)
SEGDIO1 = VPULSE (44)
SEGDIO2 = SDCK (43)
SEGDIO3 = SDATA (42)
SEG DIO 6 = XPULSE ( 38)
SEGDIO7 = YPULSE (37)
SEG DIO 8 = DI (36)
Unused pins must be configured as outputs or
terminated to V3P3/GNDD.
44 SEGDIO1/VPULSE
43 SEGDIO2/SDCK
42 SEGDIO3/SDATA
41 SEGDIO4
39 SEGDIO5
38 SEGDIO6/XPULSE
37 SEGDIO7/YPULSE
36 SEGDIO8/DI
35–27 SEGDIO[9:17]
25–18 SEGDIO[18:25]
11–4 SEGDIO[28:35]
99–94 SEGDIO[40:45]
52 SEGDIO52
51 SEGDIO53
47 SEGDIO54
17 SEGDIO26/COM5 I/O 3, 4, 5
Multiple-Use Pins. Configurable as either LCD segment
driver or DIO with alternative func tion (LCD common
drivers).
16 SEGDIO27/COM4
3 SPI_CSZ/SEGDIO36
I/O 3, 4, 5 Multiple-Use Pins. Conf igurable as ei ther LCD segment
driver or DIO with alternative f unc tion (SPI int erfac e) .
2 SPI_DO/SEGDIO37
1 SPI_DI/SEGDIO38
100 SPI_CKI/SEGDIO39
53 OPT_TX/SEGDIO51 I/O 3, 4, 5 Multiple-Use Pi ns, c onfigurabl e as either LCD segment
driver or DIO with alternative f unc tion (optic al por t/ UA RT1)
46 OPT_RX/SEGDIO55
58
E_RXTX/SEG48
I/O 1, 4, 5 Multiuse Pins. Configurable as either emulator port pi ns
(when ICE_E pull ed high) or LCD segment drivers (when
ICE_E tied to GND).
56
E_RST/SEG50
57
E_TCLK/SEG49
O
4, 5
59 ICE_E I 2
ICE Enable. When zero, E_RST, E_TCLK, and E_RXTX
become SEG50, SEG49, and SEG48 respectively. For
production units, this pin should be pulled to GND to disable
the emulator por t.
92 TMUXOUT/SEG47 O 4, 5 Multiple-Use Pins. Configurable as either multiplexer/clock
output or LCD segment driver usi ng the I /O RAM register s.
93 TMUX2OUT/SEG46
71M6543F/H and 71M6543G /GH Data Sheet
v1.2 © 2008–2011 Teridian Sem iconduc tor Corpor ation 153
Pin Name Type Circuit Function
91 RESET I 2
Chip Reset. This input pi n is used to reset t he c hip into a
known state. For nor ma l oper at ion , this p in is pulled low. To
reset the chip, this pi n shoul d be pulled high. This pin has
an internal 30 μA (nominal) current source pulldown. No
ex ternal reset ci r c uitry i s necessary.
55 RX I 3
UART0 Input. If t his pi n is unused it m us t be ter m i nated
to V 3P 3D or GNDD.
54
TX
O
4
UART0 Output
81 TEST I 7
Enables Production Test. This pin must be grounded in
no rmal operat ion.
90 PB I 3
Pushbutton Input. This pin must be at GNDD when not active
or unused. A ri si ng edge sets the WF_PB flag. It also
causes the part to wake up if it is in S LP or LCD mode. PB
does not have an i nternal pullup or pulldown resis tor.
26, 40,
48, 49,
50, 73,
74, 77,
78, 79
NC N/C — No Connection. Do not connect this pin.
71M6543F/H and 71M6543G /GH Data Sheet
154 © 2008–2011 Teridian Semi c onduc tor Corpor ation v1.2
6.8.4 I/O Equivale nt C ircuits
Figure 44: I/O Equivalent Circuits
Oscillator Equivalent Circuit
Type 8:
Oscillator I/O
Digital Input Equivalent Circuit
Type 1:
Standard Digital Input or
pin configured as DIO Input
with Internal Pull-Up
GNDD
110K
V3P3D
CMOS
Input
V3P3D
Digital
Input
Pin
Digital Input
Type 2:
Pin configured as DIO Input
with Internal Pull-Down
GNDD
110K
GNDD
CMOS
Input
V3P3D
Digital
Input
Pin
Digital Input Type 3:
Standard Digital Input or
pin configured as DIO Input
GNDD
CMOS
Input
V3P3D
Digital
Input
Pin
CMOS
Output
GNDD
V3P3D
GNDD
V3P3D
Digital Output Equivalent Circuit
Type 4:
Standard Digital Output or
pin configured as DIO Output
Digital
Output
Pin
LCD Output Equivalent Circuit
Type 5:
LCD SEG or
pin configured as LCD SEG
LCD
Driver
GNDD
LCD SEG
Output
Pin
To
MUX
GNDA
V3P3A
Analog Input Equivalent Circuit
Typ e 6:
ADC Input
Analog
Input
Pin
Comparator Input Equivalent
Circuit Type 7:
Comparator Input
GNDA
V3P3A
To
Comparator
Comparator
Input
Pin
To
Oscillator
GNDD
Oscillator
Pin
VREF Equivalent Circuit
Type 9:
VREF
from
internal
reference
GNDA
V3P3A
VREF
Pin
V2P5 Equ ivalent Circuit
Type 10:
V2P5
from
internal
reference
GNDD
V3P3D
V2P5
Pin
VLCD Equivalent Circuit
Type 11:
VLCD Power
GNDD
LCD
Drivers
VLCD
Pin
VBAT Equivalent Circuit
Type 12:
VBAT Power
GNDD
Power
Down
Circuits
VBAT
Pin
V3P3D E qui valent Cir cuit
Type 13:
V3P3D
from
V3P3SYS
V3P3D
Pin
from
VBAT
10
40
71M6543F/H and 71M6543G /GH Data Sheet
v1.2 © 2008–2011 Teridian Sem iconduc tor Corpor ation 155
7 Ordering Information
7.1 71M6543 Ordering Guide
Ref er to the 71M6xxx data sheet for the 71M6xx3 ordering guide informat ion.
Table 115. 71M 6543 Ord ering Guide
Part Part Descript io n
(Package, Accuracy)
Flash
Size
(KB) Packaging Order Number Package Marki ng
71M6543F 100-pin LQFP
Lead(Pb)-Free, 0.5% 64 bulk 71M6543F-IGT/F 71M6543F-IGT
71M6543F 100-pin LQFP
Lead(Pb)-Free, 0.5% 64 tape and reel
71M6543F-IGTR/F 71M6543F-IGT
71M6543H* 100-pin LQFP
Lead(Pb)-Free, 0.1% 64 bulk 71M6543H-IGT/F 71M6543H-IGT
71M6543H* 100-pin LQFP
Lead(Pb)-Free, 0.1% 64 tape and reel
71M6543H-IGTR/F 71M6543H-IGT
71M6543G 100-pin LQFP
Lead(Pb)-Free, 0.5% 128 bulk 71M6543G-IGT/F 71M6543G-IGT
71M6543G 100-pin LQFP
Lead(Pb)-Free, 0.5% 128 t ape and reel
71M6543G-IGTR/F 71M6543G-IGT
71M6543GH* 100-pin LQFP
Lead(Pb)-Free, 0.1% 128 bulk 71M6543GH-IGT/F 71M6543GH-IGT
71M6543GH* 100-pin LQFP
Lead(Pb)-Free, 0.1% 128 t ape and r eel
71M6543GH-IGTR/F 71M6543GH-IGT
See 4.5.1 Distinction Between Standar d and High-P r ec is ion P ar ts (page 89).
*Future product—cont ac t f ac tory f or av a il a b ility .
8 Related Information
The following documents related to the 71M6543 and 71M6xx3 are available from Teridian Semiconductor
Corporation:
• 71M6543F/ H and 71M 6543G/GH Data S heet (this docum ent)
• 71M6xxx Data Sheet
• 71M654x Sof tware User ’s Guide (S UG)
• 71M6543 Demo Board Us er ’s M anual (DBUM)
9 Contact Information
For technical support or more in formation about Maxim products, contact techni c al support at
www.maxim-ic.com/support.
71M6543F/H and 71M6543G /GH Data Sheet
156 © 2008–2011 Teridian Semi c onduc tor Corpor ation v1.2
Appendix A: Ac ronyms
AFE Anal og Front-End
AMR Autom atic Meter Reading
ANSI American Nati onal Standar ds Institute
CE Compute Engine
DIO Di gital I /O
DSP Digital Si gnal Processor
FIR Fi nite Impulse Respon se
I2C Inter-IC Bu s
ICE In-Circuit Em ulator
IEC Int er nati onal El ectr otechnical Commission
MPU Micr opr oc essor Unit (CPU)
PLL Phase-Locked Loop
RMS Root M ean S quar e
SFR Special F unction Register
SoC System-on-Chip
SPI Serial Peripheral Interfa ce
TOU Time of U s e
UART Universal Asynchr onous Receiver/Transmitter
71M6543F/H and 71M6543G /GH Data Sheet
Appendix B: Revision History
REVISION
NUMBER REVISION
DATE DESCRIPTION PAGES
CHANGED
1.0 1/11 Initial release —
1.1 3/11 Added the 71M 6543G, 71M 6543GH All
1.2 4/11 Rem ov ed the 17mW typ consumption at 3. 3V f or sleep
mode from the Features section 1
157
Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical
Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
© 2011 Maxim Integrated The Maxim logo and Maxim Integrated are trademarks of Maxim Integrated Products, Inc.