CY8C4127AXI-S443ES - CYPRESS SEMICONDUCTOR

PSoC® 4: PSoC 4100S Plus Datasheet

Programmable System-on-Chip (PSoC)

Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600

Document Number: 002-19966 Rev. *H Revised September 14, 2018

General Description

PSoC® 4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system controllers with an

Arm® Cortex™-M0+ CPU. It combines programmable and reconfigurable analog and digital blocks with flexible automatic routing.

PSoC 4100S Plus is a member of the PSoC 4 platform architecture. It is a combination of a microcontroller with standard communi-

cation and timing peripherals, a capacitive touch-sensing system (CapSense) with best-in-class performance, programmable

general-purpose continuous-time and switched-capacitor analog blocks, and programmable connectivity. PSoC 4100S Plus products

will be upward compatible with members of the PSoC 4 platform for new applications and design needs.

Features

32-bit MCU Subsystem

■48-MHz Arm Cortex-M0+ CPU with single-cycle multiply

■Up to 128 KB of flash with Read Accelerator

■Up to 16 KB of SRAM

■8-channel DMA engine

Programmable Analog

■Two opamps with reconfigurable high-drive external and

high-bandwidth internal drive and Comparator modes and ADC

input buffering capability. Opamps can operate in Deep Sleep

low-power mode.

■12-bit 1-Msps SAR ADC with differential and single-ended

modes, and Channel Sequencer with signal averaging

■Single-slope 10-bit ADC function provided by a capacitance

sensing block

■Two current DACs (IDACs) for general-purpose or capacitive

sensing applications on any pin

■Two low-power comparators that operate in Deep Sleep

low-power mode

Programmable Digital

■Programmable logic blocks allowing Boolean operations to be

performed on port inputs and outputs

Low-Power 1.71-V to 5.5-V Operation

■Deep Sleep mode with operational analog and 2.5-A digital

system current

Capacitive Sensing

■Cypress CapSense Sigma-Delta (CSD) provides best-in-class

signal-to-noise ratio (SNR) (>5:1) and water tolerance

■Cypress-supplied software component makes capacitive

sensing design easy

■Automatic hardware tuning (SmartSense™)

LCD Drive Capability

■LCD segment drive capability on GPIOs

Serial Communication

■Five independent run-time reconfigurable Serial

Communication Blocks (SCBs) with re-configurable I2C, SPI,

or UART functionality

Timing and Pulse-Width Modulation

■Eight 16-bit timer/counter/pulse-width modulator (TCPWM)

blocks

■Center-aligned, Edge, and Pseudo-random modes

■Comparator-based triggering of Kill signals for motor drive and

other high-reliability digital logic applications

■Quadrature decoder

Clock Sources

■4 to 33 MHz external crystal oscillator (ECO)

■PLL to generate 48-MHz frequency

■32-kHz Watch Crystal Oscillator (WCO)

■±2% Internal Main Oscillator (IMO)

■32-kHz Internal Low-power Oscillator (ILO)

True Random Number Generator (TRNG)

■TRNG generates truly random number for secure key gener-

ation for Cryptography applications

CAN Block

■CAN 2.0B block with support for Time-Triggered CAN (TTCAN)

Up to 54 Programmable GPIO Pins

■44-pin TQFP (0.8-mm pitch), 48-pin TQFP (0.5-mm pitch), and

64-pin TQFP normal (0.8 mm) and Fine Pitch (0.5 mm)

packages

■Any GPIO pin can be CapSense, analog, or digital

■Drive modes, strengths, and slew rates are programmable

PSoC Creator Design Environment

■Integrated Development Environment (IDE) provides

schematic design entry and build (with analog and digital

automatic routing)

■Applications Programming Interface (API) component for all

fixed-function and programmable peripherals

Industry-Standard Tool Compatibility

■After schematic entry, development can be done with

Arm-based industry-standard development tools

PSoC® 4: PSoC 4100S Plus Datasheet

Document Number: 002-19966 Rev. *H Page 2 of 44

More Information

Cypress provides a wealth of data at www.cypress.com to help you to select the right PSoC device for your design, and to help you

to quickly and effectively integrate the device into your design. For a comprehensive list of resources, see the knowledge base article

KBA86521, How to Design with PSoC 3, PSoC 4, and PSoC 5LP. Following is an abbreviated list for PSoC 4:

■Overview: PSoC Portfolio, PSoC Roadmap

■Product Selectors: PSoC 1, PSoC 3, PSoC 4, PSoC 5LP

In addition, PSoC Creator includes a device selection tool.

■Application notes: Cypress offers a large number of PSoC

application notes covering a broad range of topics, from basic

to advanced level. Recommended application notes for getting

started with PSoC 4 are:

❐AN79953: Getting Started With PSoC 4

❐AN88619: PSoC 4 Hardware Design Considerations

❐AN86439: Using PSoC 4 GPIO Pins

❐AN57821: Mixed Signal Circuit Board Layout

❐AN81623: Digital Design Best Practices

❐AN73854: Introduction To Bootloaders

❐AN89610: Arm Cortex Code Optimization

❐AN85951: PSoC® 4 and PSoC Analog Coprocessor

CapSense® Design Guide

■Technical Reference Manual (TRM) is in two documents:

❐Architecture TRM details each PSoC 4 functional block.

❐Registers TRM describes each of the PSoC 4 registers.

■Development Kits:

❐CY8CKIT-041-41XX PSoC 4100S CapSense Pioneer Kit, is

an easy-to-use and inexpensive development platform. This

kit includes connectors for Arduino™ compatible shields.

❐CY8CKIT-149 PSoC® 4100S Plus Prototyping Kit enables

you to evaluate and develop with Cypress' fourth-generation,

low-power CapSense solution using the PSoC 4100S Plus

devices.

The MiniProg3 device provides an interface for flash

programming and debug.

■Software User Guide:

❐A step-by-step guide for using PSoC Creator. The software

user guide shows you how the PSoC Creator build process

works in detail, how to use source control with PSoC Creator,

and much more.

■Component Datasheets:

❐The flexibility of PSoC allows the creation of new peripherals

(components) long after the device has gone into production.

Component datasheets provide all the information needed to

select and use a particular component, including a functional

description, API documentation, example code, and AC/DC

specifications.

■Online:

❐In addition to print documentation, the Cypress PSoC forums

connect you with fellow PSoC users and experts in PSoC

from around the world, 24 hours a day, 7 days a week.

PSoC® 4: PSoC 4100S Plus Datasheet

Document Number: 002-19966 Rev. *H Page 3 of 44

PSoC Creator

PSoC Creator is a free Windows-based Integrated Design Environment (IDE). It enables concurrent hardware and firmware design

of PSoC 3, PSoC 4, and PSoC 5LP based systems. Create designs using classic, familiar schematic capture supported by over 100

pre-verified, production-ready PSoC Components; see the list of component datasheets. With PSoC Creator, you can:

1. Drag and drop component icons to build your hardware

system design in the main design workspace

2. Codesign your application firmware with the PSoC hardware,

using the PSoC Creator IDE C compiler

3. Configure components using the configuration tools

4. Explore the library of 100+ components

5. Review component datasheets

Figure 1. Multiple-Sensor Example Project in PSoC Creator

PSoC® 4: PSoC 4100S Plus Datasheet

Document Number: 002-19966 Rev. *H Page 4 of 44

Contents

Functional Definition........................................................ 6

CPU and Memory Subsystem ..................................... 6

System Resources ...................................................... 6

Analog Blocks.............................................................. 7

Programmable Digital Blocks ...................................... 8

Fixed Function Digital Blocks ...................................... 8

GPIO ........................................................................... 8

Special Function Peripherals....................................... 9

Pinouts ............................................................................ 10

Alternate Pin Functions ............................................. 12

Power............................................................................... 14

Mode 1: 1.8 V to 5.5 V External Supply .................... 14

Mode 2: 1.8 V ±5% External Supply.......................... 14

Electrical Specifications ................................................ 15

Absolute Maximum Ratings....................................... 15

Device Level Specifications....................................... 15

Analog Peripherals .................................................... 19

Digital Peripherals ..................................................... 26

Memory ..................................................................... 29

System Resources .................................................... 29

Ordering Information...................................................... 33

Packaging........................................................................ 35

Package Diagrams.................................................... 36

Acronyms........................................................................ 38

Document Conventions ................................................. 40

Units of Measure ....................................................... 40

Revision History ............................................................. 41

Sales, Solutions, and Legal Information ...................... 42

Worldwide Sales and Design Support....................... 42

Products .................................................................... 42

PSoC® Solutions ...................................................... 42

Cypress Developer Community................................. 42

Technical Support ..................................................... 42

PSoC® 4: PSoC 4100S Plus Datasheet

Document Number: 002-19966 Rev. *H Page 5 of 44

Figure 2. Block Diagram

PSoC 4100S Plus devices include extensive support for

programming, testing, debugging, and tracing both hardware

and firmware.

The Arm Serial-Wire Debug (SWD) interface supports all

programming and debug features of the device.

Complete debug-on-chip functionality enables full-device

debugging in the final system using the standard production

device. It does not require special interfaces, debugging pods,

simulators, or emulators. Only the standard programming

connections are required to fully support debug.

The PSoC Creator IDE provides fully integrated programming

and debug support for the PSoC 4100S Plus devices. The SWD

interface is fully compatible with industry-standard third-party

tools. PSoC 4100S Plus provides a level of security not possible

with multi-chip application solutions or with microcontrollers. It

has the following advantages:

■Allows disabling of debug features

■Robust flash protection

■Allows customer-proprietary functionality to be implemented in

on-chip programmable blocks

The debug circuits are enabled by default and can be disabled

in firmware. If they are not enabled, the only way to re-enable

them is to erase the entire device, clear flash protection, and

reprogram the device with new firmware that enables debugging.

Thus firmware control of debugging cannot be over-ridden

without erasing the firmware thus providing security.

Additionally, all device interfaces can be permanently disabled

(device security) for applications concerned about phishing

attacks due to a maliciously reprogrammed device or attempts to

defeat security by starting and interrupting flash programming

sequences. All programming, debug, and test interfaces are

disabled when maximum device security is enabled. Therefore,

PSoC 4100S Plus, with device security enabled, may not be

returned for failure analysis. This is a trade-off the PSoC 4100S

Plus allows the customer to make.

Peripherals

CPU Subsystem

System Interconnect (Single Layer AHB)

PSoC 4100S

Plus

IOSS GPIO ( 8 x p or t s)

I/O Subsystem

Peripheral Interconnect ( MMIO)

PCLK

FLASH

128 KB

Read Accelerator

SPCIF

SRAM Controller

ROM

8 KB

ROM Controller

32-bit

AHB- Lite

Up to 54 x GPIOs

DeepSleep

Active / Sleep

Power Modes

Digital DFT

Test

Analog DFT

System Resources

Lite

Power

Clock

Reset

Clock Control

IMO

Sleep Control

REFPOR

Reset Control

TestMode Entry

WIC

XRES

WDT

ILO

PWRSYS

8x TCPWM

WCO

2x LP Comparator

SAR ADC

(12-bit)

CTBm

2 x Opamp

Programmable

Analog

SARMUX

High Speed I /O Matrix & Smart I/O

SWD/TC, MTB

NVIC, IRQMUX, MPU

Cortex

M0+

48 MHz

FAST MUL

LCD

CapSense(v2)

5x SCB-I2C/SPI/UART

SRAM

16 KB

ECO (w/PLL)

CAN

DataWire/

DMA

Initiator / MMIO

TRNG

PSoC® 4: PSoC 4100S Plus Datasheet

Document Number: 002-19966 Rev. *H Page 6 of 44

Functional Definition

CPU and Memory Subsystem

CPU

The Cortex-M0+ CPU in the PSoC 4100S Plus is part of the

32-bit MCU subsystem, which is optimized for low-power

operation with extensive clock gating. Most instructions are 16

bits in length and the CPU executes a subset of the Thumb-2

instruction set. It includes a nested vectored interrupt controller

(NVIC) block with eight interrupt inputs and also includes a

Wakeup Interrupt Controller (WIC). The WIC can wake the

processor from Deep Sleep mode, allowing power to be switched

off to the main processor when the chip is in Deep Sleep mode.

The CPU subsystem includes an 8-channel DMA engine and

also includes a debug interface, the serial wire debug (SWD)

interface, which is a two-wire form of JTAG. The debug configu-

ration used for PSoC 4100S Plus has four breakpoint (address)

comparators and two watchpoint (data) comparators.

Flash

The PSoC 4100S Plus device has a flash module with a flash

accelerator, tightly coupled to the CPU to improve average

access times from the flash block. The low-power flash block is

designed to deliver two wait-state (WS) access time at 48 MHz.

The flash accelerator delivers 85% of single-cycle SRAM access

performance on average.

SRAM

16 KB of SRAM are provided with zero wait-state access at

48 MHz.

SROM

An 8-KB supervisory ROM that contains boot and configuration

routines is provided.

System Resources

Power System

The power system is described in detail in the section Power. It

provides assurance that voltage levels are as required for each

respective mode and either delays mode entry (for example, on

power-on reset (POR)) until voltage levels are as required for

proper functionality, or generates resets (for example, on

brown-out detection). PSoC 4100S Plus operates with a single

external supply over the range of either 1.8 V ±5% (externally

regulated) or 1.8 to 5.5 V (internally regulated) and has three

different power modes, transitions between which are managed

by the power system. PSoC 4100S Plus provides Active, Sleep,

and Deep Sleep low-power modes.

All subsystems are operational in Active mode. The CPU

subsystem (CPU, flash, and SRAM) is clock-gated off in Sleep

mode, while all peripherals and interrupts are active with

instantaneous wake-up on a wake-up event. In Deep Sleep

mode, the high-speed clock and associated circuitry is switched

off; wake-up from this mode takes 35 µs. The opamps can

remain operational in Deep Sleep mode.

Clock System

The PSoC 4100S Plus clock system is responsible for providing

clocks to all subsystems that require clocks and for switching

between different clock sources without glitching. In addition, the

clock system ensures that there are no metastable conditions.

The clock system for the PSoC 4100S Plus consists of the IMO,

ILO, a 32-kHz Watch Crystal Oscillator (WCO), MHz ECO and

PLL, and provision for an external clock. The WCO block allows

locking the IMO to the 32-kHz oscillator.

Figure 3. PSoC 4100S Plus MCU Clocking Architecture

The HFCLK signal can be divided down as shown to generate

synchronous clocks for the Analog and Digital peripherals. There

are 18 clock dividers for the PSoC 4100S Plus (six with fractional

divide capability, twelve with integer divide only). The twelve

16-bit integer divide capability allows a lot of flexibility in

generating fine-grained frequency. In addition, there are five

16-bit fractional dividers and one 24-bit fractional divider.

IMO Clock Source

The IMO is the primary source of internal clocking in the

PSoC 4100S Plus. It is trimmed during testing to achieve the

specified accuracy.The IMO default frequency is 24 MHz and it

can be adjusted from 24 to 48 MHz in steps of 4 MHz. The IMO

tolerance with Cypress-provided calibration settings is ±2% over

the entire voltage and temperature range.

ILO Clock Source

The ILO is a very low power, nominally 40-kHz oscillator, which

is primarily used to generate clocks for the watchdog timer

(WDT) and peripheral operation in Deep Sleep mode. ILO-driven

counters can be calibrated to the IMO to improve accuracy.

Cypress provides a software component, which does the

calibration.

ECO

IMO

PLL

LFCLK

ILO

WCO

Watchdog Counters (WDC)

WDT

Watchdog Timer (WDT)

WDC0

16-bits

WDC1

16-bits

WDC2

32-bits

External Clock

Divide By

2,4,8

HFCLK

5X 16.5-bit, 1X 24.5 bit

Integer

Dividers

Fractional

Dividers

SYSCLK

Prescaler

12X 16-bit

PSoC® 4: PSoC 4100S Plus Datasheet

Document Number: 002-19966 Rev. *H Page 7 of 44

Watch Crystal Oscillator (WCO)

The PSoC 4100S Plus clock subsystem also implements a

low-frequency (32-kHz watch crystal) oscillator that can be used

for precision timing applications.

External Crystal Oscillators (ECO)

The PSoC 4100S Plus also implements a 4 to 33 MHz crystal

oscillator.

Watchdog Timer and Counters

A watchdog timer is implemented in the clock block running from

the ILO; this allows watchdog operation during Deep Sleep and

generates a watchdog reset if not serviced before the set timeout

occurs. The watchdog reset is recorded in a Reset Cause

be used to implement a Real-Time clock using the 32-kHz WCO.

Reset

PSoC 4100S Plus can be reset from a variety of sources

including a software reset. Reset events are asynchronous and

guarantee reversion to a known state. The reset cause is

recorded in a register, which is sticky through reset and allows

software to determine the cause of the reset. An XRES pin is

reserved for external reset by asserting it active low. The XRES

pin has an internal pull-up resistor that is always enabled.

Analog Blocks

12-bit SAR ADC

The 12-bit, 1-Msps SAR ADC can operate at a maximum clock

rate of 18 MHz and requires a minimum of 18 clocks at that

frequency to do a 12-bit conversion.

The Sample-and-Hold (S/H) aperture is programmable allowing

the gain bandwidth requirements of the amplifier driving the SAR

inputs, which determine its settling time, to be relaxed if required.

It is possible to provide an external bypass (through a fixed pin

location) for the internal reference amplifier.

The SAR is connected to a fixed set of pins through an 8-input

sequencer. The sequencer cycles through selected channels

autonomously (sequencer scan) with zero switching overhead

(that is, aggregate sampling bandwidth is equal to 1 Msps

whether it is for a single channel or distributed over several

channels). The sequencer switching is effected through a state

machine or through firmware driven switching. A feature

provided by the sequencer is buffering of each channel to reduce

CPU interrupt service requirements. To accommodate signals

with varying source impedance and frequency, it is possible to

have different sample times programmable for each channel.

Also, signal range specification through a pair of range registers

(low and high range values) is implemented with a corresponding

out-of-range interrupt if the digitized value exceeds the

programmed range; this allows fast detection of out-of-range

values without the necessity of having to wait for a sequencer

scan to be completed and the CPU to read the values and check

for out-of-range values in software.

The SAR is not available in Deep Sleep mode as it requires a

high-speed clock (up to 18 MHz). The SAR operating range is

1.71 V to 5.5 V.

Figure 4. SAR ADC

Two Opamps (Continuous-Time Block; CTB)

PSoC 4100S Plus has two opamps with Comparator modes

which allow most common analog functions to be performed

on-chip eliminating external components; PGAs, Voltage

Buffers, Filters, Trans-Impedance Amplifiers, and other functions

can be realized, in some cases with external passives. saving

power, cost, and space. The on-chip opamps are designed with

enough bandwidth to drive the Sample-and-Hold circuit of the

ADC without requiring external buffering.

Low-power Comparators (LPC)

PSoC 4100S Plus has a pair of low-power comparators, which

can also operate in Deep Sleep modes. This allows the analog

system blocks to be disabled while retaining the ability to monitor

external voltage levels during low-power modes. The

comparator outputs are normally synchronized to avoid

metastability unless operating in an asynchronous power mode

where the system wake-up circuit is activated by a comparator

switch event. The LPC outputs can be routed to pins.

Current DACs

PSoC 4100S Plus has two IDACs, which can drive any of the

pins on the chip. These IDACs have programmable current

ranges.

Analog Multiplexed Buses

PSoC 4100S Plus has two concentric independent buses that go

around the periphery of the chip. These buses (called amux

buses) are connected to firmware-programmable analog

switches that allow the chip's internal resources (IDACs,

comparator) to connect to any pin on the I/O Ports.

SARMUX

SARMUX Port

(Up to 16 inputs)

vplusvminus

Data and

Status Flags

Reference

Selection

External

Reference and

Bypass

(op tio nal )

POS

NEG

SAR Sequencer

SARADC

Inputs from other Ports

VDDA /2 VDDA VREF

AHB System Bus and Programmable Logic

Interconnect

Sequencing

and Control

PSoC® 4: PSoC 4100S Plus Datasheet

Document Number: 002-19966 Rev. *H Page 8 of 44

Programmable Digital Blocks

Smart I/O Block

The Smart I/O block is a fabric of switches and LUTs that allows

Boolean functions to be performed in signals being routed to the

pins of a GPIO port. The Smart I/O can perform logical opera-

tions on input pins to the chip and on signals going out as

outputs.

Fixed Function Digital Blocks

Timer/Counter/PWM (TCPWM) Block

The TCPWM block consists of a 16-bit counter with

user-programmable period length. There is a capture register to

record the count value at the time of an event (which may be an

I/O event), a period register that is used to either stop or

auto-reload the counter when its count is equal to the period

signals that are used as PWM duty cycle outputs. The block also

provides true and complementary outputs with programmable

offset between them to allow use as dead-band programmable

complementary PWM outputs. It also has a Kill input to force

outputs to a predetermined state; for example, this is used in

motor drive systems when an over-current state is indicated and

the PWM driving the FETs needs to be shut off immediately with

no time for software intervention. Each block also incorporates a

Quadrature decoder. There are eight TCPWM blocks in

PSoC 4100S Plus.

Serial Communication Block (SCB)

PSoC 4100S Plus has five serial communication blocks, which

can be programmed to have SPI, I2C, or UART functionality.

I2C Mode: The hardware I2C block implements a full

multi-master and slave interface (it is capable of multi-master

arbitration). This block is capable of operating at speeds of up to

400 kbps (Fast Mode) and has flexible buffering options to

reduce interrupt overhead and latency for the CPU. It also

supports EZI2C that creates a mailbox address range in the

memory of PSoC 4100S Plus and effectively reduces I2C

communication to reading from and writing to an array in

memory. In addition, the block supports an 8-deep FIFO for

receive and transmit which, by increasing the time given for the

CPU to read data, greatly reduces the need for clock stretching

caused by the CPU not having read data on time.

The I2C peripheral is compatible with the I2C Standard-mode and

Fast-mode devices as defined in the NXP I2C-bus specification

and user manual (UM10204). The I2C bus I/O is implemented

with GPIO in open-drain modes.

PSoC 4100S Plus is not completely compliant with the I2C spec

in the following respect:

■GPIO cells are not overvoltage tolerant and, therefore, cannot

be hot-swapped or powered up independently of the rest of the

I2C system.

UART Mode: This is a full-feature UART operating at up to

1 Mbps. It supports automotive single-wire interface (LIN),

infrared interface (IrDA), and SmartCard (ISO7816) protocols, all

of which are minor variants of the basic UART protocol. In

addition, it supports the 9-bit multiprocessor mode that allows

addressing of peripherals connected over common RX and TX

lines. Common UART functions such as parity error, break

detect, and frame error are supported. An 8-deep FIFO allows

much greater CPU service latencies to be tolerated.

SPI Mode: The SPI mode supports full Motorola SPI, TI SSP

(adds a start pulse used to synchronize SPI Codecs), and

National Microwire (half-duplex form of SPI). The SPI block can

use the FIFO.

CAN

There is a CAN 2.0B block with support for TT-CAN.

GPIO

PSoC 4100S Plus has up to 54 GPIOs. The GPIO block imple-

ments the following:

■Eight drive modes:

❐Analog input mode (input and output buffers disabled)

❐Input only

❐Weak pull-up with strong pull-down

❐Strong pull-up with weak pull-down

❐Open drain with strong pull-down

❐Open drain with strong pull-up

❐Strong pull-up with strong pull-down

❐Weak pull-up with weak pull-down

■Input threshold select (CMOS or LVTTL).

■Individual control of input and output buffer enabling/disabling

in addition to the drive strength modes

■Selectable slew rates for dV/dt related noise control to improve

EMI

The pins are organized in logical entities called ports, which are

8-bit in width (less for Ports 5 and 6). During power-on and reset,

the blocks are forced to the disable state so as not to crowbar

any inputs and/or cause excess turn-on current. A multiplexing

network known as a high-speed I/O matrix is used to multiplex

between various signals that may connect to an I/O pin.

Data output and pin state registers store, respectively, the values

to be driven on the pins and the states of the pins themselves.

Every I/O pin can generate an interrupt if so enabled and each

I/O port has an interrupt request (IRQ) and interrupt service

routine (ISR) vector associated with it.

PSoC® 4: PSoC 4100S Plus Datasheet

Document Number: 002-19966 Rev. *H Page 9 of 44

Special Function Peripherals

CapSense

CapSense is supported in the PSoC 4100S Plus through a

CapSense Sigma-Delta (CSD) block that can be connected to

any pins through an analog multiplex bus via analog switches.

CapSense function can thus be provided on any available pin or

group of pins in a system under software control. A PSoC

Creator component is provided for the CapSense block to make

it easy for the user.

Shield voltage can be driven on another analog multiplex bus to

provide water-tolerance capability. Water tolerance is provided

by driving the shield electrode in phase with the sense electrode

to keep the shield capacitance from attenuating the sensed

input. Proximity sensing can also be implemented.

The CapSense block has two IDACs, which can be used for

general purposes if CapSense is not being used (both IDACs are

available in that case) or if CapSense is used without water

tolerance (one IDAC is available).

The CapSense block also provides a 10-bit Slope ADC function

which can be used in conjunction with the CapSense function.

The CapSense block is an advanced, low-noise, programmable

block with programmable voltage references and current source

ranges for improved sensitivity and flexibility. It can also use an

external reference voltage. It has a full-wave CSD mode that

alternates sensing to VDDA and ground to null out power-supply

related noise.

LCD Segment Drive

PSoC 4100S Plus has an LCD controller, which can drive up to

4 commons and up to 50 segments. It uses full digital methods

to drive the LCD segments requiring no generation of internal

LCD voltages. The two methods used are referred to as Digital

Correlation and PWM. Digital Correlation pertains to modulating

the frequency and drive levels of the common and segment

signals to generate the highest RMS voltage across a segment

to light it up or to keep the RMS signal to zero. This method is

good for STN displays but may result in reduced contrast with TN

(cheaper) displays. PWM pertains to driving the panel with PWM

signals to effectively use the capacitance of the panel to provide

the integration of the modulated pulse-width to generate the

desired LCD voltage. This method results in higher power

consumption but can result in better results when driving TN

displays. LCD operation is supported during Deep Sleep

refreshing a small display buffer (4 bits; one 32-bit register per

port).

PSoC® 4: PSoC 4100S Plus Datasheet

Document Number: 002-19966 Rev. *H Page 10 of 44

Pinouts

The following table provides the pin list for PSoC 4100S Plus for the 44-pin TQFP, 48-pin TQFP, and 64-pin TQFP Normal and Fine

Pitch packages.

64-TQFP 44-TQFP 48-TQFP

Pin Name Pin Name Pin Name

39 P0.0 24 P0.0 28 P0.0

40 P0.1 25 P0.1 29 P0.1

41 P0.2 26 P0.2 30 P0.2

42 P0.3 27 P0.3 31 P0.3

43 P0.4 28 P0.4 32 P0.4

44 P0.5 29 P0.5 33 P0.5

45 P0.6 30 P0.6 34 P0.6

46 P0.7 31 P0.7 35 P0.7

47 XRES 32 XRES 36 XRES

48 VCCD 33 VCCD 37 VCCD

34 VDDD

49 VSSD 38 VSSD

50 VDDD 39 VDDD

51 P5.0

52 P5.1

53 P5.2

54 P5.3

55 P5.5

56 VDDA 35 VDDA 40 VDDA

57 VSSA 36 VSSA 41 VSSA

58 P1.0 37 P1.0 42 P1.0

59 P1.1 38 P1.1 43 P1.1

60 P1.2 39 P1.2 44 P1.2

61 P1.3 40 P1.3 45 P1.3

62 P1.4 41 P1.4 46 P1.4

63 P1.5 42 P1.5 47 P1.5

64 P1.6 43 P1.6 48 P1.6

1P1.7 44 P1.7 1P1.7

1VSSD

2P2.0 2P2.0 2P2.0

3P2.1 3P2.1 3P2.1

4P2.2 4P2.2 4P2.2

5P2.3 5P2.3 5P2.3

6P2.4 6P2.4 6P2.4

7P2.5 7P2.5 7P2.5

8P2.6 8P2.6 8P2.6

9P2.7 9P2.7 9P2.7

10 VSSD

11 NC

PSoC® 4: PSoC 4100S Plus Datasheet

Document Number: 002-19966 Rev. *H Page 11 of 44

Descriptions of the Power pins are as follows:

VDDD: Power supply for the digital section.

VDDA: Power supply for the analog section.

VSSD, VSSA: Ground pins for the digital and analog sections respectively.

VCCD: Regulated digital supply (1.8 V ±5%)

VDD: Power supply to all sections of the chip

VSS: Ground for all sections of the chip

GPIOs by package:

12 P6.0 10 P6.0

13 P6.1

14 P6.2

15 P6.4

16 P6.5

17 VSSD 10 VSSD

11 NC

18 P3.0 11 P3.0 12 P3.0

19 P3.1 12 P3.1 13 P3.1

20 P3.2 13 P3.2 14 P3.2

15 NC

21 P3.3 14 P3.3 16 P3.3

22 P3.4 15 P3.4 17 P3.4

23 P3.5 16 P3.5 18 P3.5

24 P3.6 17 P3.6 19 P3.6

25 P3.7 18 P3.7 20 P3.7

26 VDDD 19 VDDD 21 VDDD

27 P4.0 20 P4.0 22 P4.0

28 P4.1 21 P4.1 23 P4.1

29 P4.2 22 P4.2 24 P4.2

30 P4.3 23 P4.3 25 P4.3

31 P4.4

32 P4.5

33 P4.6

34 P4.7

35 P5.6

36 P5.7

37 P7.0 26 P7.0

38 P7.1 27 P7.1

64 TQFP 44 TQFP 48 TQFP

Number 54 37 38

64-TQFP 44-TQFP 48-TQFP

Pin Name Pin Name Pin Name

Document Number: 002-19966 Rev. *H Page 12 of 44

PSoC® 4: PSoC 4100S Plus Datasheet

Alternate Pin Functions

Each Port pin has can be assigned to one of multiple functions; it can, for example, be an analog I/O, a digital peripheral function, an LCD pin, or a CapSense pin. The pin

assignments are shown in the following table.

Port/Pin Analog Smart I/O ACT #0 ACT #1 ACT #3 DS #2 DS #3

P0.0 lpcomp.in_p[0] tcpwm.tr_in[0] scb[2].uart_cts:0 scb[2].i2c_scl:0 scb[0].spi_select1:0

P0.1 lpcomp.in_n[0] tcpwm.tr_in[1] scb[2].uart_rts:0 scb[2].i2c_sda:0 scb[0].spi_select2:0

P0.2 lpcomp.in_p[1] scb[0].spi_select3:0

P0.3 lpcomp.in_n[1] scb[2].spi_select0:1

P0.4 wco.wco_in scb[1].uart_rx:0 scb[2].uart_rx:0 scb[1].i2c_scl:0 scb[1].spi_mosi:1

P0.5 wco.wco_out scb[1].uart_tx:0 scb[2].uart_tx:0 scb[1].i2c_sda:0 scb[1].spi_miso:1

P0.6 exco.eco_in srss.ext_clk:0 scb[1].uart_cts:0 scb[2].uart_tx:1 scb[1].spi_clk:1

P0.7 exco.eco_out tcpwm.line[0]:3 scb[1].uart_rts:0 scb[1].spi_select0:1

P5.0 tcpwm.line[4]:2 scb[2].uart_rx:1 scb[2].i2c_scl:1 scb[2].spi_mosi:0

P5.1 tcpwm.line_compl[4]:2 scb[2].uart_tx:2 scb[2].i2c_sda:1 scb[2].spi_miso:0

P5.2 tcpwm.line[5]:2 scb[2].uart_cts:1 lpcomp.comp[0]:2 scb[2].spi_clk:0

P5.3 tcpwm.line_compl[5]:2 scb[2].uart_rts:1 lpcomp.comp[1]:0 scb[2].spi_select0:0

P5.4 tcpwm.line[6]:2 scb[2].spi_select1:0

P5.5 tcpwm.line_compl[6]:2 scb[2].spi_select2:0

P1.0 ctb0_oa0+ SmartIo[2].io[0] tcpwm.line[2]:1 scb[0].uart_rx:1 scb[0].i2c_scl:0 scb[0].spi_mosi:1

P1.1 ctb0_oa0- SmartIo[2].io[1] tcpwm.line_compl[2]:1 scb[0].uart_tx:1 scb[0].i2c_sda:0 scb[0].spi_miso:1

P1.2 ctb0_oa0_out SmartIo[2].io[2] tcpwm.line[3]:1 scb[0].uart_cts:1 tcpwm.tr_in[2] scb[2].i2c_scl:2 scb[0].spi_clk:1

P1.3 ctb0_oa1_out SmartIo[2].io[3] tcpwm.line_compl[3]:1 scb[0].uart_rts:1 tcpwm.tr_in[3] scb[2].i2c_sda:2 scb[0].spi_select0:1

P1.4 ctb0_oa1- SmartIo[2].io[4] tcpwm.line[6]:1 scb[3].i2c_scl:0 scb[0].spi_select1:1

P1.5 ctb0_oa1+ SmartIo[2].io[5] tcpwm.line_compl[6]:1 scb[3].i2c_sda:0 scb[0].spi_select2:1

P1.6 ctb0_oa0+ SmartIo[2].io[6] tcpwm.line[7]:1 scb[0].spi_select3:1

P1.7 ctb0_oa1+

sar_ext_vref0

sar_ext_vref1

SmartIo[2].io[7] tcpwm.line_compl[7]:1 scb[2].spi_clk:1

P2.0 sarmux[0] SmartIo[0].io[0] tcpwm.line[4]:0 csd.comp tcpwm.tr_in[4] scb[1].i2c_scl:1 scb[1].spi_mosi:2

P2.1 sarmux[1] SmartIo[0].io[1] tcpwm.line_compl[4]:0 tcpwm.tr_in[5] scb[1].i2c_sda:1 scb[1].spi_miso:2

P2.2 sarmux[2] SmartIo[0].io[2] tcpwm.line[5]:1 scb[1].spi_clk:2

P2.3 sarmux[3] SmartIo[0].io[3] tcpwm.line_compl[5]:1 scb[1].spi_select0:2

Document Number: 002-19966 Rev. *H Page 13 of 44

PSoC® 4: PSoC 4100S Plus Datasheet

P2.4 sarmux[4] SmartIo[0].io[4] tcpwm.line[0]:1 scb[3].uart_rx:1 scb[1].spi_select1:1

P2.5 sarmux[5] SmartIo[0].io[5] tcpwm.line_compl[0]:1 scb[3].uart_tx:1 scb[1].spi_select2:1

P2.6 sarmux[6] SmartIo[0].io[6] tcpwm.line[1]:1 scb[3].uart_cts:1 scb[1].spi_select3:1

P2.7 sarmux[7] SmartIo[0].io[7] tcpwm.line_compl[1]:1 scb[3].uart_rts:1 lpcomp.comp[0]:0 scb[2].spi_mosi:1

P6.0 tcpwm.line[4]:1 scb[3].uart_rx:0 can.can_tx_enb_n:0 scb[3].i2c_scl:1 scb[3].spi_mosi:0

P6.1 tcpwm.line_compl[4]:1 scb[3].uart_tx:0 can.can_rx:0 scb[3].i2c_sda:1 scb[3].spi_miso:0

P6.2 tcpwm.line[5]:0 scb[3].uart_cts:0 can.can_tx:0 scb[3].spi_clk:0

P6.3 tcpwm.line_compl[5]:0 scb[3].uart_rts:0 scb[3].spi_select0:0

P6.4 tcpwm.line[6]:0 scb[4].i2c_scl scb[3].spi_select1:0

P6.5 tcpwm.line_compl[6]:0 scb[4].i2c_sda scb[3].spi_select2:0

P3.0 SmartIo[1].io[0] tcpwm.line[0]:0 scb[1].uart_rx:1 scb[1].i2c_scl:2 scb[1].spi_mosi:0

P3.1 SmartIo[1].io[1] tcpwm.line_compl[0]:0 scb[1].uart_tx:1 scb[1].i2c_sda:2 scb[1].spi_miso:0

P3.2 SmartIo[1].io[2] tcpwm.line[1]:0 scb[1].uart_cts:1 cpuss.swd_data scb[1].spi_clk:0

P3.3 SmartIo[1].io[3] tcpwm.line_compl[1]:0 scb[1].uart_rts:1 cpuss.swd_clk scb[1].spi_select0:0

P3.4 SmartIo[1].io[4] tcpwm.line[2]:0 tcpwm.tr_in[6] scb[1].spi_select1:0

P3.5 SmartIo[1].io[5] tcpwm.line_compl[2]:0 scb[1].spi_select2:0

P3.6 SmartIo[1].io[6] tcpwm.line[3]:0 scb[4].spi_select3 scb[1].spi_select3:0

P3.7 SmartIo[1].io[7] tcpwm.line_compl[3]:0 lpcomp.comp[1]:1 scb[2].spi_miso:1

P4.0 csd.vref_ext scb[0].uart_rx:0 can.can_rx:1 scb[0].i2c_scl:1 scb[0].spi_mosi:0

P4.1 csd.cshield scb[0].uart_tx:0 can.can_tx:1 scb[0].i2c_sda:1 scb[0].spi_miso:0

P4.2 csd.cmod scb[0].uart_cts:0 can.can_tx_enb_n:1 lpcomp.comp[0]:1 scb[0].spi_clk:0

P4.3 csd.csh_tank scb[0].uart_rts:0 lpcomp.comp[1]:2 scb[0].spi_select0:0

P4.4 scb[4].uart_rx scb[4].spi_mosi scb[0].spi_select1:2

P4.5 scb[4].uart_tx scb[4].spi_miso scb[0].spi_select2:2

P4.6 scb[4].uart_cts scb[4].spi_clk scb[0].spi_select3:2

P4.7 scb[4].uart_rts scb[4].spi_select0

P5.6 tcpwm.line[7]:0 scb[4].spi_select1 scb[2].spi_select3:0

P5.7 tcpwm.line_compl[7]:0 scb[4].spi_select2

P7.0 tcpwm.line[0]:2 scb[3].uart_rx:2 scb[3].i2c_scl:2 scb[3].spi_mosi:1

P7.1 tcpwm.line_compl[0]:2 scb[3].uart_tx:2 scb[3].i2c_sda:2 scb[3].spi_miso:1

P7.2 tcpwm.line[1]:2 scb[3].uart_cts:2 scb[3].spi_clk:1

Port/Pin Analog Smart I/O ACT #0 ACT #1 ACT #3 DS #2 DS #3

PSoC® 4: PSoC 4100S Plus Datasheet

Document Number: 002-19966 Rev. *H Page 14 of 44

Power

The following power system diagram shows the set of power

supply pins as implemented for the PSoC 4100S Plus. The

system has one regulator in Active mode for the digital circuitry.

There is no analog regulator; the analog circuits run directly from

the VDD input.

Figure 5. Power Supply Connections

There are two distinct modes of operation. In Mode 1, the supply

voltage range is 1.8 V to 5.5 V (unregulated externally; internal

regulator operational). In Mode 2, the supply range is1.8 V ±5%

(externally regulated; 1.71 to 1.89, internal regulator bypassed).

Mode 1: 1.8 V to 5.5 V External Supply

In this mode, PSoC 4100S Plus is powered by an external power

supply that can be anywhere in the range of 1.8 to 5.5 V. This

range is also designed for battery-powered operation. For

example, the chip can be powered from a battery system that

starts at 3.5 V and works down to 1.8 V. In this mode, the internal

regulator of PSoC 4100S Plus supplies the internal logic and its

output is connected to the VCCD pin. The VCCD pin must be

bypassed to ground via an external capacitor (0.1 µF; X5R

ceramic or better) and must not be connected to anything else.

Mode 2: 1.8 V ±5% External Supply

In this mode, PSoC 4100S Plus is powered by an external power

supply that must be within the range of 1.71 to 1.89 V; note that

this range needs to include the power supply ripple too. In this

mode, the VDD and VCCD pins are shorted together and

bypassed. The internal regulator can be disabled in the firmware.

Bypass capacitors must be used from VDDD to ground. The

typical practice for systems in this frequency range is to use a

capacitor in the 1-µF range, in parallel with a smaller capacitor

(0.1 µF, for example). Note that these are simply rules of thumb

and that, for critical applications, the PCB layout, lead induc-

tance, and the bypass capacitor parasitic should be simulated to

design and obtain optimal bypassing.

An example of a bypass scheme is shown in the following

diagram.

Figure 6. External Supply Range from 1.8 V to 5.5 V with Internal Regulator Active

Analog

Domain

VDDA

VSSA

VDDA

1.8 Volt

Regulator

Digital

Domain

VDDD

VSSD

VDDD

VCCD

VDDD

VSS

1.8 V to 5.5 V

0.1 F

VCCD

0.1 F

Power supply bypass connections example

1F

1.8 V to 5.5 V

0.1 F1 F

VDDA

PSoC 4100S Plus

µF

PSoC® 4: PSoC 4100S Plus Datasheet

Document Number: 002-19966 Rev. *H Page 15 of 44

Electrical Specifications

Absolute Maximum Ratings

Device Level Specifications

All specifications are valid for –40 °C  TA  105 °C and TJ  125 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,

except where noted.

Note

1. Usage above the absolute maximum conditions listed in Ta bl e 1 may cause permanent damage to the device. Exposure to Absolute Maximum conditions for extended

periods of time may affect device reliability. The Maximum Storage Temperature is 150 °C in compliance with JEDEC Standard JESD22-A103, High Temperature

Storage Life. When used below Absolute Maximum conditions but above normal operating conditions, the device may not operate to specification.

Table 1. Absolute Maximum Ratings[1]

Spec ID# Parameter Description Min Typ Max Units Details/

Conditions

SID1 VDDD_ABS Digital supply relative to VSS –0.5 – 6

–

SID2 VCCD_ABS

Direct digital core voltage input relative

to VSS

–0.5 – 1.95 –

SID3 VGPIO_ABS GPIO voltage –0.5 – VDD+0.5 –

SID4 IGPIO_ABS Maximum current per GPIO –25 – 25

–

SID5 IGPIO_injection GPIO injection current, Max for VIH >

VDDD, and Min for VIL < VSS

–0.5 – 0.5 Current injected

per pin

BID44 ESD_HBM Electrostatic discharge human body

model 2200 – –

–

BID45 ESD_CDM Electrostatic discharge charged device

model 500 – – –

BID46 LU Pin current for latch-up –140 – 140 mA –

Table 2. DC Specifications

Typical values measured at VDD = 3.3 V and 25 °C.

Spec ID# Parameter Description Min Typ Max Units

Details/

Conditions

SID53 VDD Power supply input voltage 1.8 – 5.5

Internally

regulated supply

SID255 VDD

Power supply input voltage (VCCD =

VDDD = VDDA)1.71 – 1.89

Internally

unregulated

supply

SID54 VCCD Output voltage (for core logic) – 1.8 – –

SID55 CEFC External regulator voltage bypass – 0.1 –

µF

X5R ceramic or

better

SID56 CEXC Power supply bypass capacitor – 1 – X5R ceramic or

better

Active Mode, VDD = 1.8 V to 5.5 V. Typical values measured at VDD = 3.3 V and 25 °C.

SID10 IDD5 Execute from flash; CPU at 6 MHz – 1.8 2.4

mASID16 IDD8 Execute from flash; CPU at 24 MHz – 3.0 4.6

SID19 IDD11 Execute from flash; CPU at 48 MHz – 5.4 7.1

Sleep Mode, VDDD = 1.8 V to 5.5 V (Regulator on)

SID22 IDD17 I2C wakeup WDT, and Comparators on – 1.1 1.8 mA 6 MHZ

SID25 IDD20 I2C wakeup, WDT, and Comparators on – 1.5 2.1 12 MHZ

PSoC® 4: PSoC 4100S Plus Datasheet

Document Number: 002-19966 Rev. *H Page 16 of 44

Sleep Mode, VDDD = 1.71 V to 1.89 V (Regulator bypassed)

SID28 IDD23 I2C wakeup, WDT, and Comparators on – 1.1 1.8 mA 6 MHZ

SID28A IDD23A I2C wakeup, WDT, and Comparators on – 1.5 2.1 mA 12 MHZ

Deep Sleep Mode, VDD = 1.8 V to 3.6 V (Regulator on)

SID30 IDD25 I2C wakeup and WDT on; T = –40 °C to

60 °C

–2.540µA T = –40 °C to

60 °C

SID31 IDD26 I2C wakeup and WDT on – 2.5 125 µA Max is at 3.6 V

and 85 °C

Deep Sleep Mode, VDD = 3.6 V to 5.5 V (Regulator on)

SID33 IDD28

I2C wakeup and WDT on; T = –40 °C to

60 °C – 2.5 40 µAT = –40 °C to

60 °C

SID34 IDD29 I2C wakeup and WDT on – 2.5 125 µAMax is at 5.5 V

and 85 °C

Deep Sleep Mode, VDD = VCCD = 1.71 V to 1.89 V (Regulator bypassed)

SID36 IDD31

I2C wakeup and WDT on; T = –40 °C to

60 °C – 2.5 60 µAT = –40 °C to

60 °C

SID37 IDD32 I2C wakeup and WDT on – 2.5 180 µAMax is at 1.89 V

and 85 °C

XRES Current

SID307 IDD_XR Supply current while XRES asserted – 2 5 mA –

Table 2. DC Specifications (continued)

Typical values measured at VDD = 3.3 V and 25 °C.

Spec ID# Parameter Description Min Typ Max Units

Details/

Conditions

Note

2. Guaranteed by characterization.

Table 3. AC Specifications

Spec ID# Parameter Description Min Typ Max Units Details/

Conditions

SID48 FCPU CPU frequency DC – 48 MHz 1.71 VDD 5.5

SID49[2] TSLEEP Wakeup from Sleep mode – 0 – µs

SID50[2] TDEEPSLEEP Wakeup from Deep Sleep mode – 35 –

PSoC® 4: PSoC 4100S Plus Datasheet

Document Number: 002-19966 Rev. *H Page 17 of 44

GPIO

Table 4. GPIO DC Specifications

Spec ID# Parameter Description Min Typ Max Units Details/

Conditions

SID57 VIH[3] Input voltage high threshold 0.7 VDDD ––

CMOS Input

SID58 VIL Input voltage low threshold – – 0.3 

VDDD CMOS Input

SID241 VIH[3] LVTTL input, VDDD < 2.7 V 0.7 VDDD –– –

SID242 VIL LVTTL input, VDDD < 2.7 V – – 0.3 

VDDD

–

SID243 VIH[3] LVTTL input, VDDD  2.7 V 2.0 – – –

SID244 VIL LVTTL input, VDDD  2.7 V – – 0.8 –

SID59 VOH Output voltage high level VDDD –0.6 – – IOH = 4 mA at 3 V VDDD

SID60 VOH Output voltage high level VDDD –0.5 – – IOH = 1 mA at 1.8 V

VDDD

SID61 VOL Output voltage low level – – 0.6 IOL = 4 mA at 1.8 V

VDDD

SID62 VOL Output voltage low level – – 0.6 IOL = 10 mA at 3 V VDDD

SID62A VOL Output voltage low level – – 0.4 IOL = 3 mA at 3 V VDDD

SID63 RPULLUP Pull-up resistor 3.5 5.6 8.5 kΩ –

SID64 RPULLDOWN Pull-down resistor 3.5 5.6 8.5 –

SID65 IIL

Input leakage current (absolute

value) – – 2 nA 25 °C, VDDD = 3.0 V

SID66 CIN Input capacitance – – 7 pF –

SID67[4] VHYSTTL Input hysteresis LVTTL 25 40 –

VDDD  2.7 V

SID68[4] VHYSCMOS Input hysteresis CMOS 0.05 × VDDD –– V

DD < 4.5 V

SID68A[4] VHYSCMOS5V5 Input hysteresis CMOS 200 – – VDD > 4.5 V

SID69[4] IDIODE

Current through protection diode to

VDD/VSS

– – 100 µA–

SID69A[4] ITOT_GPIO

Maximum total source or sink chip

current – – 200 mA –

Notes

3. VIH must not exceed VDDD + 0.2 V.

4. Guaranteed by characterization.

Table 5. GPIO AC Specifications

(Guaranteed by Characterization)

Spec ID# Parameter Description Min Typ Max Units

Details/

Conditions

SID70 TRISEF Rise time in fast strong mode 2 – 12

3.3 V VDDD, Cload =

25 pF

SID71 TFALLF Fall time in fast strong mode 2 – 12 3.3 V VDDD, Cload =

25 pF

SID72 TRISES Rise time in slow strong mode 10 – 60 – 3.3 V VDDD, Cload =

25 pF

PSoC® 4: PSoC 4100S Plus Datasheet

Document Number: 002-19966 Rev. *H Page 18 of 44

XRES

SID73 TFALLS Fall time in slow strong mode 10 – 60 – 3.3 V VDDD, Cload =

25 pF

SID74 FGPIOUT1 GPIO FOUT; 3.3 V  VDDD 5.5 V

Fast strong mode ––33

MHz

90/10%, 25 pF load,

60/40 duty cycle

SID75 FGPIOUT2 GPIO FOUT; 1.71 VVDDD3.3 V

Fast strong mode ––16.7 90/10%, 25 pF load,

60/40 duty cycle

SID76 FGPIOUT3 GPIO FOUT; 3.3 V VDDD 5.5 V

Slow strong mode –– 7 90/10%, 25 pF load,

60/40 duty cycle

SID245 FGPIOUT4 GPIO FOUT; 1.71 V VDDD 3.3 V

Slow strong mode. ––3.5 90/10%, 25 pF load,

60/40 duty cycle

SID246 FGPIOIN GPIO input operating frequency;

1.71 V VDDD 5.5 V – – 48 90/10% VIO

Table 5. GPIO AC Specifications (continued)

(Guaranteed by Characterization)

Spec ID# Parameter Description Min Typ Max Units

Details/

Conditions

Note

5. Guaranteed by characterization.

Table 6. XRES DC Specifications

Spec ID# Parameter Description Min Typ Max Units

Details/

Conditions

SID77 VIH Input voltage high threshold 0.7 × VDDD ––

V CMOS Input

SID78 VIL Input voltage low threshold – – 0.3  VDDD

SID79 RPULLUP Pull-up resistor – 60 – kΩ –

SID80 CIN Input capacitance – – 7 pF –

SID81[5] VHYSXRES Input voltage hysteresis – 100 – mV Typical hysteresis is

200 mV for VDD > 4.5 V

SID82 IDIODE

Current through protection diode

to VDD/VSS

––100µA

Table 7. XRES AC Specifications

Spec ID# Parameter Description Min Typ Max Units Details/

Conditions

SID83[5] TRESETWIDTH Reset pulse width 1 – – µs –

BID194[5] TRESETWAKE Wake-up time from reset release – – 2.7 ms –

PSoC® 4: PSoC 4100S Plus Datasheet

Document Number: 002-19966 Rev. *H Page 19 of 44

Analog Peripherals

CTBm Opamp

Table 8. CTBm Opamp Specifications

Spec ID# Parameter Description Min Typ Max Units Details/

Conditions

IDD Opamp block current, External load

SID269 IDD_HI power=hi – 1100 1850

µA

–

SID270 IDD_MED power=med – 550 950 –

SID271 IDD_LOW power=lo – 150 350 –

GBW Load = 20 pF, 0.1 mA

VDDA = 2.7 V

SID272 GBW_HI power=hi 6 – –

MHz

Input and output are

0.2 V to VDDA-0.2 V

SID273 GBW_MED power=med 3 – – Input and output are

0.2 V to VDDA-0.2 V

SID274 GBW_LO power=lo – 1 – Input and output are

0.2 V to VDDA-0.2 V

IOUT_MAX VDDA = 2.7 V, 500 mV from rail

SID275 IOUT_MAX_HI power=hi 10 – –

Output is 0.5 V to VDDA

-0.5 V

SID276 IOUT_MAX_MID power=mid 10 – – Output is 0.5 V to VDDA

-0.5 V

SID277 IOUT_MAX_LO power=lo – 5 – Output is 0.5 V to VDDA

-0.5 V

IOUT VDDA = 1.71 V, 500 mV from rail

SID278 IOUT_MAX_HI power=hi 4 – –

Output is 0.5 V to VDDA

-0.5 V

SID279 IOUT_MAX_MID power=mid 4–– Output is 0.5 V to

VDDA-0.5 V

SID280 IOUT_MAX_LO power=lo –2–Output is 0.5 V to

VDDA-0.5 V

IDD_Int Opamp block current Internal Load

SID269_I IDD_HI_Int power=hi –1500 1700

µA

–

SID270_I IDD_MED_Int power=med –700 900 –

SID271_I

IDD_LOW_Int power=lo –– – –

GBW VDDA = 2.7 V –– – –

SID272_I GBW_HI_Int power=hi 8 ––MHz Output is 0.25 V to

VDDA-0.25 V

General opamp specs for both

internal and external modes

SID281 VIN Charge-pump on, VDDA = 2.7 V –0.05 –VDDA-0

.2 V

–

SID282 VCM Charge-pump on, VDDA = 2.7 V –0.05 –VDDA-0

.2 –

VOUT VDDA = 2.7 V

PSoC® 4: PSoC 4100S Plus Datasheet

Document Number: 002-19966 Rev. *H Page 20 of 44

SID283 VOUT_1 power=hi, Iload=10 mA 0.5 –VDDA

-0.5

–

SID284 VOUT_2 power=hi, Iload=1 mA 0.2 –VDDA

-0.2 –

SID285 VOUT_3 power=med, Iload=1 mA 0.2 –VDDA

-0.2 –

SID286 VOUT_4 power=lo, Iload=0.1 mA 0.2 –VDDA

-0.2 –

SID288 VOS_TR Offset voltage, trimmed –1.0 0.5 1.0

High mode, input 0 V to

VDDA-0.2 V

SID288A VOS_TR Offset voltage, trimmed –1–Medium mode, input

0 V to VDDA-0.2 V

SID288B VOS_TR Offset voltage, trimmed –2–Low mode, input 0 V to

VDDA-0.2 V

SID290 VOS_DR_TR Offset voltage drift, trimmed –10 310 µV/°C High mode

SID290A VOS_DR_TR Offset voltage drift, trimmed –10 –

µV/°C Medium mode

SID290B VOS_DR_TR Offset voltage drift, trimmed –10 –Low mode

SID291 CMRR DC 70 80 –

Input is 0 V to

VDDA-0.2 V, Output is

0.2 V to VDDA-0.2 V

SID292 PSRR At 1 kHz, 10-mV ripple 70 85 –

VDDD = 3.6 V,

high-power mode, input

is 0.2 V to VDDA-0.2 V

Noise

SID294 VN2 Input-referred, 1 kHz, power = Hi –72 –

nV/rtHz

Input and output are at

0.2 V to VDDA-0.2 V

SID295 VN3 Input-referred, 10 kHz, power = Hi –28 –Input and output are at

0.2 V to VDDA-0.2 V

SID296 VN4 Input-referred, 100 kHz, power = Hi –15 –Input and output are at

0.2 V to VDDA-0.2 V

SID297 CLOAD Stable up to max. load. Performance

specs at 50 pF. ––

125 pF –

SID298 SLEW_RATE Cload = 50 pF, Power = High,

VDDA = 2.7 V 6––V/µs –

SID299 T_OP_WAKE From disable to enable, no external

RC dominating ––25 µs –

SID299A OL_GAIN Open Loop Gain –90 – dB

COMP_MODE Comparator mode; 50 mV drive,

Trise=Tfall (approx.)

Table 8. CTBm Opamp Specifications (continued)

Spec ID# Parameter Description Min Typ Max Units Details/

Conditions

PSoC® 4: PSoC 4100S Plus Datasheet

Document Number: 002-19966 Rev. *H Page 21 of 44

SID300 TPD1 Response time; power=hi –150 –

Input is 0.2 V to

VDDA-0.2 V

SID301 TPD2 Response time; power=med –500 –Input is 0.2 V to

VDDA-0.2 V

SID302 TPD3 Response time; power=lo –2500 –Input is 0.2 V to

VDDA-0.2 V

SID303 VHYST_OP Hysteresis –10 –mV –

SID304 WUP_CTB Wake-up time from Enabled to

Usable ––25 µs –

Deep Sleep

Mode

Mode 2 is lowest current range.

Mode 1 has higher GBW.

SID_DS_1 IDD_HI_M1 Mode 1, High current –1400 –

µA

25 °C

SID_DS_2 IDD_MED_M1 Mode 1, Medium current –700 –25 °C

SID_DS_3 IDD_LOW_M1 Mode 1, Low current –200 –25 °C

SID_DS_4 IDD_HI_M2 Mode 2, High current –120 –25 °C

SID_DS_5 IDD_MED_M2 Mode 2, Medium current –60 –25 °C

SID_DS_6 IDD_LOW_M2 Mode 2, Low current –15 –25 °C

SID_DS_7 GBW_HI_M1 Mode 1, High current –4–

MHz

20-pF load, no DC load

0.2 V to VDDA-0.2 V

SID_DS_8 GBW_MED_M1 Mode 1, Medium current –2–20-pF load, no DC load

0.2 V to VDDA-0.2 V

SID_DS_9 GBW_LOW_M1 Mode 1, Low current –0.5 –20-pF load, no DC load

0.2 V to VDDA-0.2 V

SID_DS_10 GBW_HI_M2 Mode 2, High current –0.5 –20-pF load, no DC load

0.2 V to VDDA-0.2 V

SID_DS_11 GBW_MED_M2 Mode 2, Medium current –0.2 –20-pF load, no DC load

0.2 V to VDDA-0.2 V

SID_DS_12 GBW_Low_M2 Mode 2, Low current –0.1 –20-pF load, no DC load

0.2 V to VDDA-0.2 V

SID_DS_13 VOS_HI_M1 Mode 1, High current –5–

With trim 25 °C, 0.2 V to

VDDA-0.2 V

SID_DS_14 VOS_MED_M1 Mode 1, Medium current –5–With trim 25 °C, 0.2 V to

VDDA-0.2 V

SID_DS_15 VOS_LOW_M1 Mode 1, Low current –5–With trim 25 °C, 0.2 V to

VDDA-0.2 V

SID_DS_16 VOS_HI_M2 Mode 2, High current –5–With trim 25 °C, 0.2V to

VDDA-0.2 V

SID_DS_17 VOS_MED_M2 Mode 2, Medium current –5–With trim 25 °C, 0.2 V to

VDDA-0.2 V

SID_DS_18 VOS_LOW_M2 Mode 2, Low current –5–With trim 25 °C, 0.2 V to

VDDA-0.2 V

Table 8. CTBm Opamp Specifications (continued)

Spec ID# Parameter Description Min Typ Max Units Details/

Conditions

PSoC® 4: PSoC 4100S Plus Datasheet

Document Number: 002-19966 Rev. *H Page 22 of 44

Comparator

SID_DS_19 IOUT_HI_M1 Mode 1, High current –10 –

Output is 0.5 V to

VDDA-0.5 V

SID_DS_20 IOUT_MED_M1 Mode 1, Medium current –10 –Output is 0.5 V to

VDDA-0.5 V

SID_DS_21 IOUT_LOW_M1 Mode 1, Low current –4–Output is 0.5 V to

VDDA-0.5 V

SID_DS_22 IOUT_HI_M2 Mode 2, High current –1–

SID_DS_23 IOUT_MED_M2 Mode 2, Medium current –1–

SID_DS_24 IOUT_LOW_M2 Mode 2, Low current –0.5 –

Table 8. CTBm Opamp Specifications (continued)

Spec ID# Parameter Description Min Typ Max Units Details/

Conditions

Note

6. Guaranteed by characterization.

Table 9. Comparator DC Specifications

Spec ID# Parameter Description Min Typ Max Units Details/

Conditions

SID84 VOFFSET1 Input offset voltage, Factory trim ––±10

SID85 VOFFSET2 Input offset voltage, Custom trim ––±4

SID86 VHYST Hysteresis when enabled –10 35

SID87 VICM1

Input common mode voltage in normal

mode 0–V

DDD-0.1

Modes 1 and 2

SID247 VICM2

Input common mode voltage in low

power mode 0–V

DDD

SID247A VICM3

Input common mode voltage in ultra

low power mode 0–V

DDD-1.15 VDDD ≥ 2.2 V at –40 °C

SID88 CMRR Common mode rejection ratio 50 – – dB VDDD ≥ 2.7V

SID88A CMRR Common mode rejection ratio 42 ––V

DDD ≤ 2.7V

SID89 ICMP1 Block current, normal mode ––400

µA

SID248 ICMP2 Block current, low power mode ––100

SID259 ICMP3 Block current in ultra low-power mode ––6 VDDD ≥ 2.2 V at –40 °C

SID90 ZCMP DC Input impedance of comparator 35 ––MΩ

Table 10. Comparator AC Specifications

Spec ID# Parameter Description Min Typ Max Units Details/

Conditions

SID91 TRESP1 Response time, normal mode, 50 mV

overdrive –38 110

SID258 TRESP2 Response time, low power mode, 50 mV

overdrive –70 200

SID92 TRESP3 Response time, ultra-low power mode,

200 mV overdrive –2.3 15 µs VDDD ≥ 2.2 V at –40 °C

PSoC® 4: PSoC 4100S Plus Datasheet

Document Number: 002-19966 Rev. *H Page 23 of 44

Temperature Sensor

SAR ADC

Table 11. Temperature Sensor Specifications

Spec ID# Parameter Description Min Typ Max Units Details /

Conditions

SID93 TSENSACC Temperature sensor accuracy –5 ±1 5 °C –40 to +85 °C

Table 12. SAR ADC Specifications

Spec ID# Parameter Description Min Typ Max Units Details/

Conditions

SAR ADC DC Specifications

SID94 A_RES Resolution – – 12 bits

SID95 A_CHNLS_S Number of channels - single ended – – 16

SID96 A-CHNKS_D Number of channels - differential – – 4 Diff inputs use

neighboring I/O

SID97 A-MONO Monotonicity – – – Yes

SID98 A_GAINERR Gain error – – ±0.1 % With external

reference

SID99 A_OFFSET Input offset voltage – – 2 mV Measured with

1-V reference

SID100 A_ISAR Current consumption – – 1 mA

SID101 A_VINS Input voltage range - single ended VSS –V

DDA V

SID102 A_VIND Input voltage range - differential VSS –V

DDA V

SID103 A_INRES Input resistance – – 2.2 KΩ

SID104 A_INCAP Input capacitance – – 10 pF

SID260 VREFSAR Trimmed internal reference to SAR 1.188 1.2 1.212 V

SAR ADC AC Specifications

SID106 A_PSRR Power supply rejection ratio 70 – – dB

SID107 A_CMRR Common mode rejection ratio 66 – – dB Measured at 1 V

SID108 A_SAMP Sample rate – – 1 Msps

SID109 A_SNR Signal-to-noise and distortion ratio (SINAD) 65 – – dB FIN = 10 kHz

SID110 A_BW Input bandwidth without aliasing – – A_samp/2 kHz

SID111 A_INL Integral non linearity. VDD = 1.71 to 5.5, 1 Msps –1.7 – 2 LSB VREF = 1 to VDD

SID111A A_INL Integral non linearity. VDDD = 1.71 to 3.6, 1 Msps –1.5 – 1.7 LSB VREF = 1.71 to

VDD

SID111B A_INL Integral non linearity. VDD = 1.71 to 5.5, 500 ksps –1.5 – 1.7 LSB VREF = 1 to VDD

SID112 A_DNL Differential non linearity. VDD = 1.71 to 5.5,

1 Msps

–1 –2.2 LSB VREF = 1 to VDD

SID112A A_DNL Differential non linearity. VDD = 1.71 to 3.6,

1 Msps

–1 –2LSBV

REF = 1.71 to

VDD

SID112B A_DNL Differential non linearity. VDD = 1.71 to 5.5,

500 ksps

–1 –2.2 LSB VREF = 1 to VDD

SID113 A_THD Total harmonic distortion – – –65 dB Fin = 10 kHz

SID261 FSARINTREF SAR operating speed without external reference

bypass –– 100 ksps 12-bit resolution

PSoC® 4: PSoC 4100S Plus Datasheet

Document Number: 002-19966 Rev. *H Page 24 of 44

CSD and IDAC

Table 13. CSD and IDAC Specifications

SPEC ID# Parameter Description Min Typ Max Units Details / Conditions

SYS.PER#3 VDD_RIPPLE Max allowed ripple on power supply,

DC to 10 MHz

– – ±50 mV VDD > 2 V (with ripple),

25 °C TA, Sensitivity =

0.1 pF

SYS.PER#16 VDD_RIPPLE_1.8 Max allowed ripple on power supply,

DC to 10 MHz

– – ±25 mV VDD > 1.75V (with ripple),

25 °C TA, Parasitic Capaci-

tance (CP) < 20 pF,

Sensitivity ≥ 0.4 pF

SID.CSD.BLK ICSD Maximum block current – – 4000 µA Maximum block current for

both IDACs in dynamic

(switching) mode including

comparators, buffer, and

reference generator

SID.CSD#15 VREF Voltage reference for CSD and

Comparator

0.6 1.2 VDDA - 0.6 VVDDA – 0.6 or 4.4,

whichever is lower

SID.CSD#15A VREF_EXT External Voltage reference for CSD

and Comparator

0.6 VDDA - 0.6 VVDDA – 0.6 or 4.4,

whichever is lower

SID.CSD#16 IDAC1IDD IDAC1 (7-bits) block current – – 1750 µA

SID.CSD#17 IDAC2IDD IDAC2 (7-bits) block current – – 1750 µA

SID308 VCSD Voltage range of operation 1.71 – 5.5 V1.8 V ±5% or 1.8 V to 5.5 V

SID308A VCOMPIDAC Voltage compliance range of IDAC 0.6 – VDDA –0.6 VVDDA – 0.6 or 4.4,

whichever is lower

SID309 IDAC1DNL DNL –1 – 1 LSB

SID310 IDAC1INL INL –2 – 2 LSB INL is ±5.5 LSB for VDDA <

SID311 IDAC2DNL DNL –1 – 1 LSB

SID312 IDAC2INL INL –2 – 2 LSB INL is ±5.5 LSB for VDDA <

SID313 SNR Ratio of counts of finger to noise.

Guaranteed by characterization

5– –Ratio Capacitance range of 5 to

35 pF, 0.1-pF sensitivity. All

use cases. VDDA > 2 V.

SID314 IDAC1CRT1 Output current of IDAC1 (7 bits) in

low range

4.2 – 5.4 µA LSB = 37.5-nA typ

SID314A IDAC1CRT2 Output current of IDAC1(7 bits) in

medium range

34 – 41 µA LSB = 300-nA typ

SID314B IDAC1CRT3 Output current of IDAC1(7 bits) in

high range

275 – 330 µA LSB = 2.4-µA typ

SID314C IDAC1CRT12 Output current of IDAC1 (7 bits) in

low range, 2X mode

8– 10.5µA LSB = 75-nA typ

SID314D IDAC1CRT22 Output current of IDAC1(7 bits) in

medium range, 2X mode

69 – 82 µA LSB = 600-nA typ.

SID314E IDAC1CRT32 Output current of IDAC1(7 bits) in

high range, 2X mode

540 – 660 µA LSB = 4.8-µA typ

SID315 IDAC2CRT1 Output current of IDAC2 (7 bits) in

low range

4.2 – 5.4 µA LSB = 37.5-nA typ

SID315A IDAC2CRT2 Output current of IDAC2 (7 bits) in

medium range

34 – 41 µA LSB = 300-nA typ

SID315B IDAC2CRT3 Output current of IDAC2 (7 bits) in

high range

275 – 330 µA LSB = 2.4-µA typ

SID315C IDAC2CRT12 Output current of IDAC2 (7 bits) in

low range, 2X mode

8– 10.5µA LSB = 75-nA typ

SID315D IDAC2CRT22 Output current of IDAC2(7 bits) in

medium range, 2X mode

69 – 82 µA LSB = 600-nA typ

SID315E IDAC2CRT32 Output current of IDAC2(7 bits) in

high range, 2X mode

540 – 660 µA LSB = 4.8-µA typ

SID315F IDAC3CRT13 Output current of IDAC in 8-bit mode

in low range

8– 10.5µA LSB = 37.5-nA typ

PSoC® 4: PSoC 4100S Plus Datasheet

Document Number: 002-19966 Rev. *H Page 25 of 44

10-bit CapSense ADC

SID315G IDAC3CRT23 Output current of IDAC in 8-bit mode

in medium range

69 – 82 µA LSB = 300-nA typ

SID315H IDAC3CRT33 Output current of IDAC in 8-bit mode

in high range

540 – 660 µA LSB = 2.4-µA typ

SID320 IDACOFFSET All zeroes input – – 1 LSB Polarity set by Source or

Sink. Offset is 2 LSBs for

37.5 nA/LSB mode

SID321 IDACGAIN Full-scale error less offset – – ±10 %

SID322 IDACMISMATCH1 Mismatch between IDAC1 and

IDAC2 in Low mode

–– 9.2

LSB LSB = 37.5-nA typ

SID322A IDACMISMATCH2 Mismatch between IDAC1 and

IDAC2 in Medium mode

–– 5.6

LSB LSB = 300-nA typ

SID322B IDACMISMATCH3 Mismatch between IDAC1 and

IDAC2 in High mode

–– 6.8

LSB LSB = 2.4-µA typ

SID323 IDACSET8 Settling time to 0.5 LSB for 8-bit IDAC – – 5 µs Full-scale transition. No

external load

SID324 IDACSET7 Settling time to 0.5 LSB for 7-bit IDAC – – 5 µs Full-scale transition. No

external load

SID325 CMOD External modulator capacitor. – 2.2 – nF 5-V rating, X7R or NP0 cap

Table 13. CSD and IDAC Specifications (continued)

SPEC ID# Parameter Description Min Typ Max Units Details / Conditions

Table 14. 10-bit CapSense ADC Specifications

Spec ID# Parameter Description Min Typ Max Units Details/

Conditions

SIDA94 A_RES Resolution – – 10 bits Auto-zeroing is required

every millisecond

SIDA95 A_CHNLS_S Number of channels - single ended – – 16 Defined by AMUX Bus

SIDA97 A-MONO Monotonicity – – – Yes

SIDA98 A_GAINERR Gain error – – ±3 % In VREF (2.4 V) mode

with VDDA bypass

capacitance of 10 µF

SIDA99 A_OFFSET Input offset voltage – – ±18 mV In VREF (2.4 V) mode

with VDDA bypass

capacitance of 10 µF

SIDA100 A_ISAR Current consumption – – 0.25 mA

SIDA101 A_VINS Input voltage range - single ended VSSA –V

DDA V

SIDA103 A_INRES Input resistance – 2.2 – KΩ

SIDA104 A_INCAP Input capacitance – 20 – pF

SIDA106 A_PSRR Power supply rejection ratio – 60 – dB In VREF (2.4 V) mode

with VDDA bypass

capacitance of 10 µF

SIDA107 A_TACQ Sample acquisition time – 1 – µs

SIDA108 A_CONV8 Conversion time for 8-bit resolution at

conversion rate = Fhclk/(2^(N+2)).

Clock frequency = 48 MHz.

– – 21.3 µs Does not include acqui-

sition time. Equivalent to

44.8 ksps including

acquisition time.

SIDA108A A_CONV10 Conversion time for 10-bit resolution at

conversion rate = Fhclk/(2^(N+2)).

Clock frequency = 48 MHz.

– – 85.3 µs Does not include acqui-

sition time. Equivalent to

11.6 ksps including

acquisition time.

PSoC® 4: PSoC 4100S Plus Datasheet

Document Number: 002-19966 Rev. *H Page 26 of 44

Digital Peripherals

Timer Counter Pulse-Width Modulator (TCPWM)

I2C

SIDA109 A_SND Signal-to-noise and Distortion ratio

(SINAD)

– 61 – dB With 10-Hz input sine

wave, external 2.4-V

reference, VREF (2.4 V)

mode

SIDA110 A_BW Input bandwidth without aliasing – – 22.4 KHz 8-bit resolution

SIDA111 A_INL Integral Non Linearity. 1 ksps – – 2 LSB VREF = 2.4 V or greater

SIDA112 A_DNL Differential Non Linearity. 1 ksps – – 1 LSB

Table 14. 10-bit CapSense ADC Specifications (continued)

Spec ID# Parameter Description Min Typ Max Units Details/

Conditions

Table 15. TCPWM Specifications

Spec ID Parameter Description Min Typ Max Units Details/Conditions

SID.TCPWM.1 ITCPWM1 Block current consumption at 3 MHz – – 45

μA

All modes (TCPWM)

SID.TCPWM.2 ITCPWM2 Block current consumption at 12 MHz – – 155 All modes (TCPWM)

SID.TCPWM.2A ITCPWM3 Block current consumption at 48 MHz – – 650 All modes (TCPWM)

SID.TCPWM.3 TCPWMFREQ Operating frequency – – Fc MHz Fc max = CLK_SYS

Maximum = 48 MHz

SID.TCPWM.4 TPWMENEXT Input trigger pulse width 2/Fc – –

For all trigger events[7]

SID.TCPWM.5 TPWMEXT Output trigger pulse widths 2/Fc – –

Minimum possible width

of Overflow, Underflow,

and CC (Counter equals

Compare value) outputs

SID.TCPWM.5A TCRES Resolution of counter 1/Fc – – Minimum time between

successive counts

SID.TCPWM.5B PWMRES PWM resolution 1/Fc – – Minimum pulse width of

PWM Output

SID.TCPWM.5C QRES Quadrature inputs resolution 1/Fc – –

Minimum pulse width

between Quadrature

phase inputs

Note

7. Guaranteed by characterization.

Table 16. Fixed I2C DC Specifications[7]

Spec ID Parameter Description Min Typ Max Units Details/Conditions

SID149 II2C1 Block current consumption at 100 kHz – – 50

µA

–

SID150 II2C2 Block current consumption at 400 kHz – – 135 –

SID151 II2C3 Block current consumption at 1 Mbps – – 310 –

SID152 II2C4 I2C enabled in Deep Sleep mode – 1 –

Table 17. Fixed I2C AC Specifications[7]

Spec ID Parameter Description Min Typ Max Units Details/Conditions

SID153 FI2C1 Bit rate – – 1 Msps –

PSoC® 4: PSoC 4100S Plus Datasheet

Document Number: 002-19966 Rev. *H Page 27 of 44

SPI

UART

Note

8. Guaranteed by characterization.

Table 18. SPI DC Specifications[8]

Spec ID Parameter Description Min Typ Max Units Details/Conditions

SID163 ISPI1 Block current consumption at 1 Mbps – – 360

µA

–

SID164 ISPI2 Block current consumption at 4 Mbps – – 560 –

SID165 ISPI3 Block current consumption at 8 Mbps – – 600 –

Table 19. SPI AC Specifications[8]

Spec ID Parameter Description Min Typ Max Units Details/Conditions

SID166 FSPI SPI Operating frequency (Master; 6X

Oversampling) –– 8MHz

Fixed SPI Master Mode AC Specifications

SID167 TDMO MOSI Valid after SClock driving edge – – 15

–

SID168 TDSI MISO Valid before SClock capturing

edge 20 – – Full clock, late MISO

sampling

SID169 THMO Previous MOSI data hold time 0 – – Referred to Slave capturing

edge

Fixed SPI Slave Mode AC Specifications

SID170 TDMI MOSI Valid before Sclock Capturing

edge 40 – –

–

SID171 TDSO MISO Valid after Sclock driving edge – – 42 +

3*Tcpu TCPU = 1/FCPU

SID171A TDSO_EXT MISO Valid after Sclock driving edge

in Ext. Clk mode ––48 –

SID172 THSO Previous MISO data hold time 0 – – –

SID172A TSSELSSCK SSEL Valid to first SCK Valid edge 100 – – ns –

Table 20. UART DC Specifications[8]

Spec ID Parameter Description Min Typ Max Units Details/Conditions

SID160 IUART1

Block current consumption at

100 Kbps – – 55 µA –

SID161 IUART2

Block current consumption at

1000 Kbps ––312µA –

Table 21. UART AC Specifications[8]

Spec ID Parameter Description Min Typ Max Units Details/Conditions

SID162 FUART Bit rate – – 1 Mbps –

PSoC® 4: PSoC 4100S Plus Datasheet

Document Number: 002-19966 Rev. *H Page 28 of 44

LCD Direct Drive

Table 22. LCD Direct Drive DC Specifications[9]

Spec ID Parameter Description Min Typ Max Units Details/Conditions

SID154 ILCDLOW Operating current in low power mode –5–µA

16  4 small segment disp.

at 50 Hz

SID155 CLCDCAP

LCD capacitance per

segment/common driver – 500 5000 pF –

SID156 LCDOFFSET Long-term segment offset – 20 – mV –

SID157 ILCDOP1 LCD system operating current Vbias

= 5 V – 2–

32  4 segments at 50 Hz

25 °C

SID158 ILCDOP2

LCD system operating current Vbias

= 3.3 V – 2– 32  4 segments at 50 Hz

25 °C

Table 23. LCD Direct Drive AC Specifications[9]

Spec ID Parameter Description Min Typ Max Units Details/Conditions

SID159 FLCD LCD frame rate 10 50 150 Hz –

Note

9. Guaranteed by characterization.

PSoC® 4: PSoC 4100S Plus Datasheet

Document Number: 002-19966 Rev. *H Page 29 of 44

Memory

System Resources

Power-on Reset (POR)

Table 24. Flash DC Specifications

Spec ID Parameter Description Min Typ Max Units Details/Conditions

SID173 VPE Erase and program voltage 1.71 – 5.5 V –

Notes

10. It can take as much as 20 milliseconds to write to Flash. During this time the device should not be Reset, or Flash operations will be interrupted and cannot be relied

on to have completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdogs.

Make certain that these are not inadvertently activated.

11. Guaranteed by characterization.

Table 25. Flash AC Specifications

Spec ID Parameter Description Min Typ Max Units Details/Conditions

SID174 TROWWRITE[10] Row (block) write time (erase and

program) – – 20

Row (block) = 256 bytes

SID175 TROWERASE[10] Row erase time – – 16 –

SID176 TROWPROGRAM[10] Row program time after erase – – 4 –

SID178 TBULKERASE[10] Bulk erase time (64 KB) – – 35 –

SID180[11] TDEVPROG[10] Total device program time – – 7 Seconds –

SID181[11] FEND Flash endurance 100 K – – Cycles –

SID182[11] FRET

Flash retention. TA  55 °C, 100 K

P/E cycles 20 – –

Year s

–

SID182A[11] –Flash retention. TA  85 °C, 10 K

P/E cycles 10 – – –

SID182B FRETQ Flash retention. TA  105 °C, 10K

P/E cycles,  three years at TA ≥

85 °C

10 – – years Guaranteed by charac-

terization.

SID256 TWS48 Number of Wait states at 48 MHz 2 – – CPU execution from

Flash

SID257 TWS24 Number of Wait states at 24 MHz 1 – – CPU execution from

Flash

Table 26. Power On Reset (PRES)

Spec ID Parameter Description Min Typ Max Units Details/Conditions

SID.CLK#6 SR_POWER_UP Power supply slew rate 1 – 67 V/ms At power-up

SID185[11] VRISEIPOR Rising trip voltage 0.80 – 1.5 V –

SID186[11] VFALLIPOR Falling trip voltage 0.70 – 1.4 –

Table 27. Brown-out Detect (BOD) for VCCD

Spec ID Parameter Description Min Typ Max Units Details/Conditions

SID190[11] VFALLPPOR BOD trip voltage in active and

sleep modes

1.48 – 1.62 V –

SID192[11] VFALLDPSLP BOD trip voltage in Deep Sleep 1.11 – 1.5 –

PSoC® 4: PSoC 4100S Plus Datasheet

Document Number: 002-19966 Rev. *H Page 30 of 44

SWD Interface

Internal Main Oscillator

Internal Low-Speed Oscillator

Note

12. Guaranteed by design.

Table 28. SWD Interface Specifications

Spec ID Parameter Description Min Typ Max Units Details/Conditions

SID213 F_SWDCLK1 3.3 V  VDD  5.5 V – – 14

MHz

SWDCLK ≤ 1/3 CPU

clock frequency

SID214 F_SWDCLK2 1.71 V  VDD  3.3 V – – 7 SWDCLK ≤ 1/3 CPU

clock frequency

SID215[12] T_SWDI_SETUP T = 1/f SWDCLK 0.25*T – –

–

SID216[12] T_SWDI_HOLD T = 1/f SWDCLK 0.25*T – – –

SID217[12] T_SWDO_VALID T = 1/f SWDCLK – – 0.5*T –

SID217A[12] T_SWDO_HOLD T = 1/f SWDCLK 1 – – –

Table 29. IMO DC Specifications

(Guaranteed by Design)

Spec ID Parameter Description Min Typ Max Units Details/Conditions

SID218 IIMO1 IMO operating current at 48 MHz – – 250 µA–

SID219 IIMO2 IMO operating current at 24 MHz – – 180 µA–

Table 30. IMO AC Specifications

Spec ID Parameter Description Min Typ Max Units Details/Conditions

SID223 FIMOTOL1

Frequency variation at 24, 32, and

48 MHz (trimmed) ––±2%

SID226 TSTARTIMO IMO startup time – – 7 µs –

SID228 TJITRMSIMO2 RMS jitter at 24 MHz – 145 – ps –

Table 31. ILO DC Specifications

(Guaranteed by Design)

Spec ID Parameter Description Min Typ Max Units Details/Conditions

SID231 IILO1 ILO operating current – 0.3 1.05 µA –

Table 32. ILO AC Specifications

Spec ID Parameter Description Min Typ Max Units Details/Conditions

SID234[12] TSTARTILO1 ILO startup time – – 2 ms –

SID236[12] TILODUTY ILO duty cycle 40 50 60 % –

SID237 FILOTRIM1 ILO frequency range 20 40 80 kHz –

PSoC® 4: PSoC 4100S Plus Datasheet

Document Number: 002-19966 Rev. *H Page 31 of 44

Watch Crystal Oscillator (WCO)

External Clock

External Crystal Oscillator and PLL

Table 35. External Crystal Oscillator (ECO) Specifications

System Clock

Table 33. WCO Specifications

Spec ID# Parameter Description Min Typ Max Units Details / Conditions

SID398 FWCO Crystal frequency – 32.768 – kHz

SID399 FTOL Frequency tolerance – 50 250 ppm With 20-ppm crystal

SID400 ESR Equivalent series resistance – 50 – kΩ

SID401 PD Drive Level – – 1 µW

SID402 TSTART Startup time – – 500 ms

SID403 CL Crystal Load Capacitance 6 – 12.5 pF

SID404 C0 Crystal Shunt Capacitance – 1.35 – pF

SID405 IWCO1 Operating Current (high power mode) – – 8 uA

Table 34. External Clock Specifications

Spec ID Parameter Description Min Typ Max Units Details/Conditions

SID305[13] ExtClkFreq External clock input frequency 0 – 48 MHz –

SID306[13] ExtClkDuty Duty cycle; measured at VDD/2 45 – 55 % –

Spec ID Parameter Description Min Typ Max Units Details/Conditions

SID316[13] IECO1 External clock input frequency – – 1.5 mA –

SID317[13] FECO Crystal frequency range 4 – 33 MHz –

Table 36. PLL Specifications

Spec ID# Parameter Description Min Typ Max Units Details / Conditions

SID410 IDD_PLL_48 In = 3 MHz, Out = 48 MHz –530 610 uA

SID411 IDD_PLL_24 In = 3 MHz, Out = 24 MHz –300 405 uA

SID412 Fpllin PLL input frequency 1 –48 MHz

SID413 Fpllint PLL intermediate frequency; prescaler out 1 –3MHz

SID414 Fpllvco VCO output frequency before post-divide 22.5 –104 MHz

SID415 Divvco

VCO Output post-divider range; PLL

output frequency is Fpplvco/Divvco 1 –8

SID416 Plllocktime Lock time at startup ––

250 µs

SID417 Jperiod_1 Period jitter for VCO ≥ 67 MHz ––

150 ps Guaranteed by design

SID416A Jperiod_2 Period jitter for VCO ≤ 67 MHz ––

200 ps Guaranteed by design

Note

13. Guaranteed by characterization.

Table 37. Block Specs

Spec ID Parameter Description Min Typ Max Units Details/Conditions

SID262[13] TCLKSWITCH System clock source switching time 3 – 4 Periods –

PSoC® 4: PSoC 4100S Plus Datasheet

Document Number: 002-19966 Rev. *H Page 32 of 44

Smart I/O

CAN

Table 38. Smart I/O Pass-through Time (Delay in Bypass Mode)

Spec ID# Parameter Description Min Typ Max Units Details / Conditions

SID252 PRG_BYPASS Max delay added by Smart I/O in

bypass mode

––1.6 ns

Table 39. CAN Specifications

Spec ID Parameter Description Min Typ Max Units Details/Conditions

SID420 IDD_CAN Block current consumption ––

200 µA

SID421 CAN_bits CAN Bit rate ––1 Mbps Min 8-MHZ clock

PSoC® 4: PSoC 4100S Plus Datasheet

Document Number: 002-19966 Rev. *H Page 33 of 44

Ordering Information

The marketing part numbers for the PSoC 4100S Plus devices are listed in the following table.