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MCS9845
PCI to Dual Serial and ISA Controller
Copyright © 2007-2012 ASIX Electronics Corporation. All rights reserved.
12.1.5 Transaction Duration
The initiator, as stated earlier, gives only the starting address during the address phase. It does
not tell the number of data transfers in a burst transfer transaction.
The target will automatically generate the addresses for subsequent Data Phase transfers. The
initiator indicates the completion of a transaction by asserting nIRDY and de-asserting nFRAME
during the last data transfer phase. The transaction does not actually complete until the target
has also asserted the nTRDY signal and the last data transfer takes place. At this point the
nTRDY and nDEVSEL are de-asserted by the target.
12.1.6 Transaction Completion
When all of nIRDY, nTRDY, nDEVSEL, and nFRAME are in the inactive state (high state), the
bus is in idle state. The bus is then ready to be claimed by another Bus Master.
12.1.7 PCI Resource Allocation
PCI devices do not have “Hard-Wired” assignments for memory or I/O Ports like ISA devices do.
PCI devices use “Plug & Play” to obtain the required resources each time the system boots up.
Each PCI device can request up to six resource allocations. These can be blocks of memory
(RAM) or blocks of I/O Registers. The size of each resource block requested can also be
specified, allowing great flexibility. Each of these resource blocks is accessed by means of a
Base-Address-Register (BAR). As the name suggests, this is a pointer to the start of the
resource. Individual registers are then addressed using relative offsets from the Base-Address-
Register contents. The important thing to note is: plugging the same PCI card into different
machines will not necessarily result in the same addresses being assigned to it. For this reason,
software (drivers, etc.) must always obtain the specific addresses for the device from the PCI
System.
Each PCI device is assigned an entry in the PCI System’s shared “Configuration Space”. Every
device is allocated 256 Bytes in the Configuration Space. The first 64 Bytes must follow the
conventions of a standard PCI Configuration “Header”. There are several pieces of information
the device must present in specific fields within the header to allow the PCI System to properly
identify it. These include the Vendor-ID, Device-ID and Class-Code. These three fields should
provide enough information to allow the PCI System to associate the correct software driver with
the hardware device. Other fields can be used to provide additional information to further refine
the needs and capabilities of the device.
As part of the Enumeration process (discovery of which devices are present in the system) the
Base-Address-Registers are configured for each device. The device tells the system how many
registers (etc.) it requires, and the system maps that number into the system’s resource space,
reserving them for exclusive use by that particular device. No guarantees are made that any two
requests for resources will have any predictable relationship to each other. Each PCI System is
free to use its own allocation strategy when managing resources.