Digital Delay Units series DDU-7J = 10 Taps (14 pins DIP) TL interfaced (Commercia! Type) Features: = Completely interfaced for TTL and DTL application @ No external components required = P.C. board space economy achieved Fits standard 14 pins DIP socket Test Conditions: u Operates aver commercial temperature a Input Pulse Width: =150% of total delay. range @ Time delay measured @ 1.5 V on rising edge. vgs gs = Unless otherwise specified all time-delays are Specifications: referenced to input of delay line. @ No. Taps: 10 equally spaced taps # Rise-time is measured from .75 V to 2.4 V of @ Tota! Delay Tolerance: +5% or better, or leading edge. 2 ns whichever is greater. # All measurements made @ V c =5V; Ta = +25C. Mi Rise-time: 4 ns typically @ Temperature coefficient: 100 PPM/C. Hi Temperature range: 0 to + 70C HM Supply voltage: 4.5 to 5.5 Vde. @ Logic 1 input current: 190 ja max. | 180 Wi Logic 0 input current: 4 ma. max. b-- M@ Logic 1 V out: 2.5 V min. F PUB + M Logic 0 V out: 0.5 V max. wax. 300 @ Logic 1 Fan-out: 20/tap max. ' |@ +. 1 i Logic 0 Fan-out: 10/tap max. 990 010 M@ Power Dissipation: 740 mw max. 830 MAX + ma 020 Tota! Delay 1 | HL Hd 020 ; Part No. Delay Per Tap , | (ns) (rs) 1G loom soo J *DDU-7J-10 9 1 4 *DDU-7J-20 18 2 5 Ta# 1 2 3 4 5 6 F 8 @Q 10 *DDU-75-25 995 25+ 7 Pin# 13 3 12 4 WW 5 WW 6 4 8 *DDU-7J-50 45 5.0415 DDU-7J-100 100 100+ 2 Wes D> 5 DDU-7J-150 150 180+ 2 o-___o ! DDU-7J-200 200. 20.0 + 2 t DDU-7J-250 250 25.0 + 2 f DDU-7J-300 300 30.0 + 3 I 3 DDU-7J-400 400 40.0 + 4 ! : DDU-7J-500 500 500+ 5 o- ! * Time delay referenced to 1st tap. Two (2) gates in parallel for input buffer. 3 Mt. Prospect Avenue, Clifton, New Jersey 07013 = (201) 773-2299 m FAX (201) 773-9672 = TWX 710-989-7008 16