3 HIGH SIDE AND 3 LOW SIDE DRIVER
Product Summary
VOFFSET 600V max.
IO+ / - 160 mA / 360 mA
VOUT 10 - 20V
ton/off (typ.) 1.3 & 0.6 µs
Deadtime (typ.) 700 ns
Packages
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Typical Connection
(Refer to Lead Assignments for correct pin configuration). This/These diagram(s) show electrical connections only.
Please refer to our Application Notes and DesignTips for proper circuit board layout.
IR2131(J)(S) & (PbF)
28-Lead PDIP
28-Lead
SOIC
44-Lead PLCC
w/o 12 Leads
Data Sheet No. PD60032 rev P
Features
•Floating channel designed for bootstrap operation
Fully operational to +600V Tolerant to negative
transient voltage dV/dt immune
•Gate drive supply range from 10 to 20V
•Undervoltage lockout for all channels
•Over-current shutdown turns off all six drivers
•Independent 3 high side & 3 low side drivers
•Matched propagation delay for all channels
•2.5V logic compatible
•Outputs out of phase with inputs
•28-Lead SOIC & 44-Lead PLCC are also
available in Lead-Free.
Description
The IR2131(J)(S) is a high voltage, high speed power
MOSFET and IGBT driver with three independent high and
low side referenced output channels. Proprietary HVIC
technology enables ruggedized monolithic construction.
Logic inputs are compatible with CMOS or LSTTL outputs,
down to 2.5V logic. A current trip function which termi-
nates all six outputs can be derived from an external cur-
rent sense resistor. A shutdown input is provided for a
customized shutdown function. An open drain
F
AUL
T
signal is provided to indicate that any of the shutdowns has
occurred. The output drivers feature a high pulse current
buffer stage designed for minimum driver cross-conduc-
tion. Propagation delays are matched to simplify use in high
frequency applications. The floating channels can be used
to drive N-channel power MOSFETs or IGBTs in the high
side configuration which operate up to 600 volts.
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Symbol Definition Min. Max. Units
VB1,2,3 High Side Floating Supply V oltage -0.3 625
VS1,2,3 High Side Floating Offset Voltage VB1,2,3 - 25 VB1,2,3 + 0.3
VHO1,2,3 High Side Floating Output V oltage VS1,2,3 - 0.3 VB1,2,3 + 0.3
VCC Low Side and Logic Fixed Supply V oltage -0.3 25
VSS Logic Ground VCC - 25 VCC + 0.3
VLO1,2,3 Low Side Output V oltage -0.3 VCC + 0.3
VIN Logic Input V oltage (
H
IN1,2
,3
,
L
IN1,2
,3
,
F
LT-CL
R
, SD & ITRIP) VSS - 0.3 (VSS + 15) or
(VCC + 0.3)
whichever
is lower
VFLT
F
AUL
T
Output V oltage VSS - 0.3 VCC + 0.3
dVS/dt Allowable Offset Supply V oltage Transient — 5 0 V/ns
PDPackage Power Dissipation @ TA ≤ +25°C (28 Lead DIP) — 1.5
(28 Lead SOIC) — 1.6 W
(44 Lead PLCC) — 2.0
RthJA Thermal Resistance, Junction to Ambient (28 Lead DIP) — 8 3
(28 Lead SOIC) — 7 8 °C/W
(44 Lead PLCC) — 63
TJJunction T emperature — 150
TSStorage T emperature -55 150
TLLead Temperature (Soldering, 10 seconds) — 300
Absolute Maximum Ratings
Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage param-
eters are absolute voltages referenced to COM. The Thermal Resistance and Power Dissipation ratings are measured under
board mounted and still air conditions. Additional Information is shown in Figures 7 through 10.
Note 1: Logic operational for VS of -5V to +600V. Logic state held for VS of -5V to -VBS. (Please refer to the Design T ip
DT97-3 for more details).
Note 2: All input pins, CA- and CAO pins are internally clamped with a 5.2V zener diode.
Recommended Operating Conditions
The Input/Output logic timing diagram is shown in Figure 1. For proper operation the device should be used within the
recommended conditions. All voltage parameters are absolute voltages referenced to COM. The VS offset rating is tested
with all supplies biased at 15V differential.
V
Symbol Definition Min. Max. Units
VB1,2,3 High Side Floating Supply V oltage VS1,2,3 + 10 VS1,2,3 + 20
VS1,2,3 High Side Floating Offset Voltage Note 1 6 00
VHO1,2,3 High Side Floating Output V oltage VS1,2,3 VB1,2,3
VCC Low Side and Logic Fixed Supply V oltage 10 2 0
VSS Logic Ground - 5 5
VLO1,2,3 Low Side Output V oltage 0 VCC
VIN Logic Input V oltage (
H
IN1,2
,3
,
L
IN1,2
,3
,
F
LT-CL
R
, SD & ITRIP) VSS VSS + 5
VFLT
F
AUL
T
Output Voltage VSS VCC
TAAmbient T emperature -40 125 °C
V
°C
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Parameter Value
Symbol Definition Min. Typ. Max. Units Test Conditions
VIH Logic “0” Input Voltage (OUT = LO) 2.2 — —
VIL Logic “1” Input Voltage (OUT = HI) — — 0.8
VFCLR,IH Logic “0” Fault Clear Input V oltage 2.2 — —
VFCLR,IL Logic “1” Fault Clear Input V oltage — — 0.8
VSD,TH+ Shutdown Input Positive Going Threshold 1.2 1.8 2.1
VSD,TH- Shutdown Input Negative Going Threshold 0.9 1.5 1.8
VIT,TH+ ITRIP Input Positive Going Threshold 250 48 5 600
VIT,TH- ITRIP Input Negative Going Threshold 200 4 00 550
VOH High Level Output V oltage, VBIAS - VO— — 100 VIN = 0V, IO = 0A
VOL Low Level Output V oltage, VO— — 100 VIN = 5V, IO = 0A
ILK Offset Supply Leakage Current — — 50 VB = VS = 600V
IQBS Quiescent VBS Supply Current — 30 100 VIN = 0V or 5V
IQCC Quiescent VCC Supply Current — 3. 0 4.5 mA VIN = 0V or 5V
IIN+ Logic “1” Input Bias Current (OUT = HI) — 190 300 VIN = 0V
IIN- Logic “0” Input Bias Current (OUT = LO) — 50 100 µAV
IN = 5V
IITRIP+ “High” ITRIP Bias Current — 75 150 ITRIP = 5V
IITRIP- “Low” ITRIP Bias Current — — 100 nA ITRIP = 0V
IFCLR+ Logic “1” Fault Clear Bias Current — 125 250
F
LT-CL
R
= 0V
IFCLR- Logic “0” Fault Clear Bias Current — 75 150 µA
F
LT-CL
R
= 5V
ISD+ Logic “1” Shutdown Bias Current — 75 150 SD = 5V
ISD- Logic “0” Shutdown Bias Current — — 100 nA SD = 0V
Parameter Value
Symbol Definition Min. Typ. Max. Units Test Conditions
ton Turn-On Propagation Delay 0.6 1.3 2.0
toff Turn-Off Propagation Delay 0.2 0.6 1.0 VIN = 0 & 5V
trTurn-On Rise Time — 80 150 VS1,2,3 = 0 to 600V
tfTurn-Of f Fall T ime — 4 0 100
titrip ITRIP to Output Shutdown Propagation Delay 4 00 700 1000 VIN, VITRIP = 0 & 5V
tbl ITRIP Blanking Time — 40 0 — VITRIP = 1V
tflt ITRIP to
F
AUL
T
Indication Delay 4 00 7 0 0 1000 ns VIN, VITRIP = 0 & 5V
tflt,in Input Filter Time (All Six Inputs) — 310 — VIN = 0 & 5V
tfltclr
F
LT-CL
R
to
F
AUL
T
Clear Time 4 00 800 1200 VIN, VIT, VFC = 0&5V
tsd SD to Output Shutdown Propagation Delay 4 00 70 0 1000 VIN, VSD = 0 & 5V
DT Deadtime 400 700 1200 VIN = 0 & 5V
Dynamic Electrical Characteristics
VBIAS (VCC, VBS1,2,3) = 15V, V S1,2,3 = VSS = COM, C L = 1000 pF and TA = 25°C unless otherwise specified. The dynamic
electrical characteristics are defined in Figures 4 through 5.
Static Electrical Characteristics
VBIAS (VCC, VBS1,2,3) = 15V, VS1,2,3 = VSS = COM and T A = 25°C unless otherwise specified. The VIN, VTH and IIN
parameters are referenced to VSS and are applicable to all six logic input leads:
IN1,2
&
L
IN1,2,
3
. The VO and IO
parameters are referenced to COM and VS1,2,3 and are applicable to the respective output leads: HO1,2,3 or LO1,2,3.
µs
µA
mV
V
NOTE: For high side PWM, HIN pulse width must be ≥ 1.5µsec
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Parameter Value
Symbol Definition Min. Typ. Max. Units Test Conditions
VBSUV+ VBS Supply Undervoltage Positive Going 8.2 8.7 9.2
Threshold
VBSUV- VBS Supply Undervoltage Negative Going 7.8 8.3 8. 8
Threshold
VCCUV+ VCC Supply Undervoltage Positive Going 8.2 8.7 9.2
Threshold
VCCUV- VCC Supply Undervoltage Negative Going 7.8 8.3 8.8
Threshold
Ron,FLT
FAULT
Low On-Resistance — 5 5 7 5 Ω
IO+ Output High Short Circuit Pulsed Current 1 60 2 50 — VO = 0V, VIN = 0V
PW ≤ 10 µs
IO- Output Low Short Circuit Pulsed Current 36 0 5 0 0 — VO = 15V, VIN = 5V
PW ≤ 10 µs
Static Electrical Characteristics -- Continued
VBIAS (VCC, VBS1,2,3) = 15V, VS1,2,3 = VSS = COM and TA = 25°C unless otherwise specified. The VIN, VTH and IIN
parameters are referenced to VSS and are applicable to all six logic input leads:
IN1,2
&
L
IN1,2
,3
. The VO and IO
parameters are referenced to COM and VS1,2,3 and are applicable to the respective output leads: HO1,2,3 or LO1,2,3.
Functional Block Diagram
mA
V
IR2131(J)(S) & (PbF)
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Lead Assignments
28 Lead DIP 44 Lead PLCC w/o 12 Leads 28 Lead SOIC (Wide Body)
IR2131 IR2131J IR2131S
Part Number
Lead
Symbol Description
Logic inputs for high side gate driver outputs (HO1,2,3), out of phase
Logic inputs for low side gate driver output (LO1,2,3), out of phase
Logic input for fault clear
SD Logic input for shutdown
Indicates over-current or undervoltage lockout (low side) has occurred, negative logic
VCC Low side and logic fixed supply
ITRIP Input for over-current shutdown
VSS Logic ground
VB1,2,3 High side floating supplies
HO1,2,3 High side gate drive outputs
VS1,2,3 High side floating supply returns
LO1,2,3 Low side gate drive outputs
COM Low side return
Lead Definitions
H
IN1,2
,3
F
AUL
T
F
LT-CL
R
L
IN1,2
,3
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Figure 1. Input/Output T iming Diagram Figure 2. Floating Supply V oltage Transient T est Circuit
Figure 4. Switching Time Waveform Definitions
Figure 6. Shutdown Waveform DefinitionsFigure 5. Deadtime Waveform Definitions
H
IN1,2
,3
L
IN1,2
,3
F
LT -CL
R
F
AUL
T
LO1,2,3
HO1,2,3
LO1,2,3
HO1,2,3
tr
ton toff tf
50% 50%
90% 90%
10% 10%
L
IN1,2
,3
H
IN1,2
,3
DT DT
50% 50%
50% 50%
ITRIP
F
AUL
T
F
LT-CL
R
LO1,2,3
L
IN1,2
,3
H
IN1,2
,3
L
IN1,2
,3
HO1,2,3
LO1,2,3
SD
ITRIP
SD
tflt
50%
50%
titrip
50%
50%
50% 50%
50%
tfltclr tsd
Figure 3. Switching Time Test Circuit
SD
FLT-CLR
C0M
SD
FLT-CLR
<50V/ns
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Figure 7. IR2131 TJ vs. Frequency (IRF820)
RGATE = 33W, V CC = 15V
Figure 9. IR2131 TJ vs. Frequency (IRF840)
RGATE = 15W, V CC = 15V Figure 10. IR2131 TJ vs. Frequency (IRF450)
RGATE = 10W, VCC = 15V
Figure 8. IR2131 TJ vs. Frequency (IRF830)
RGATE = 20W, VCC = 15V
20
25
30
35
40
45
50
1E+2 1E+3 1E+4 1E+5
Frequency (Hz)
Juncti on Tem peratur e (°C)
320V
160V
0V
480V
20
25
30
35
40
45
50
1E+2 1E+3 1E+4 1E+5
Frequency (Hz)
Juncti on Tem peratur e (°C)
320V
160V
0V
480V
20
40
60
80
100
1E+2 1E+3 1E+4 1E+5
Frequency (Hz )
Juncti on Tem peratur e (°C)
320V
160V
0V
480V
20
40
60
80
100
120
140
1E+2 1E+3 1E+4 1E+5
Frequency (Hz )
Juncti on Tem peratur e (°C)
320V
160V
0V
480V
U
tin,fil tin,fil
on on on off
offoff
high low
HIN/LIN
HO/LO
Figure 6.5 Input Filter Function
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28-Lead PDIP (wide body) 01-6011
01-3024 02 (MS-011AB)
Case outlines
28-Lead SOIC (wide body) 01-6013
01-3040 02 (MS-013AE)
IR2131(J)(S) & (PbF)
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01-6009 00
01-3004 02(mod.) (MS-018AC)
44-Lead PLCC w/o 12 leads
NOTES
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This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
Data and specifications subject to change without notice.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.
10/11/04
* PLCC Pin 1 identifier located top center
Basic Part (Non-Lead Free)
Lead-Free Part
28-Lead PD IP IR2131 order IR2131 28-Lead PD IP IR2131 ord er Not avail abl e
28-Lead SOIC I R 2131S order IR2131S 28-Lead SOIC IR2131S order IR2131 SP bF
44-Lead PLC C IR2131J order IR2131J 44-Lead PLC C IR2131J order IR2131JP bF
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