HEXFET® Power MOSFET IRFP140N
Fifth Generation HEXFETs from International Rectifier
utilize advanced processing techniques to achieve the
lowest possible on-resistance per silicon area. This benefit,
combined with the fast switching speed and ruggedized
device design that HEXFET Power MOSFETs are well
known for, provides the designer with an extremely efficient
device for use in a wide variety of applications.
The TO-247 package is preferred for commercial-industrial
applications where higher power levels preclude the use of
TO-220 devices. The TO-247 is similar but superior to the
earlier TO-218 package because of its isolated mounting
hole.
lAdvanced Process Technology
lDynamic dv/dt Rating
l175°C Operating Temperature
lFast Switching
lFully Avalanche Rated
Description
10/5/98
VDSS = 100V
RDS(on) = 0.052Ω
ID = 33A
S
D
G
Parameter Min. Typ. Max. Units
RθJC Junction-to-Case –––– –––– 1.1
RθCS Case-to-Sink, Flat, Greased Surface –––– 0.24 –––– °C/W
RθJA Junction-to-Ambient –––– –––– 40
Thermal Resistance
Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V33
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V23 A
IDM Pulsed Drain Current 110
PD @TC = 25°C Power Dissipation 140 W
Linear Derating Factor 0.91 W/°C
VGS Gate-to-Source Voltage ±20 V
EAS Single Pulse Avalanche Energy 300 mJ
IAR Avalanche Current16 A
EAR Repetitive Avalanche Energy14 mJ
dv/dt Peak Diode Recovery dv/dt 5.0 V/ns
TJOperating Junction and -55 to + 175
TSTG Storage Temperature Range °C
Soldering Temperature, for 10 seconds 300 (1.6mm from case)
Mounting torque, 6-32 or M3 screw. 10 lbf•in (1.1N•m)
Absolute Maximum Ratings
TO-247AC
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Parameter Min. Typ. Max. Units Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage 10 0 –– – –– – V VGS = 0V, ID = 250µA
∆V(BR)DSS/∆TJBreakdown Voltage Temp. Coefficient ––– 0.11 ––– V/°C Reference to 25°C, ID = 1mA
RDS(on) Static Drain-to-Source On-Resistance ––– ––– 0.052 ΩVGS = 10V, ID = 16A
VGS(th) Gate Threshold Voltage 2.0 ––– 4.0 V VDS = VGS, ID = 250µA
gfs Forward Transconductance 11 ––– ––– S VDS = 50V, ID = 16A
––– ––– 25 VDS = 100V, V GS = 0V
––– ––– 250 VDS = 80V, VGS = 0V, TJ = 150°C
Gate-to-Source Forward Leakage ––– ––– 100 VGS = 20V
Gate-to-Source Reverse Leakage ––– ––– -100 VGS = -20V
QgTotal Gate Charge –– – – – – 9 4 ID = 16A
Qgs Gate-to-Source Charge ––– ––– 15 nC VDS = 80V
Qgd Gate-to-Drain ("Miller") Charge ––– ––– 43 VGS = 10V, See Fig. 6 and 13
td(on) Turn-On Delay Time ––– 8 .2 ––– VDD = 50V
trRise Time ––– 39 ––– ID = 16A
td(off) Turn-Off Delay Time ––– 44 ––– RG = 5.1Ω
tfFall Time ––– 33 ––– RD = 3.0Ω, See Fig. 10
Between lead,
6mm (0.25in.)
from package
and center of die contact
Ciss Input Capacitance ––– 1400 ––– VGS = 0V
Coss Output Capacitance ––– 330 ––– pF VDS = 25V
Crss Reverse Transfer Capacitance ––– 170 ––– ƒ = 1.0MHz, See Fig. 5
nH
µA
nA
IDSS Drain-to-Source Leakage Current
IGSS
LSInternal Source Inductance ––– –––
ns
S
D
G
5.0
13
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
–––
LDInternal Drain Inductance –––
–––
–––
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 ) ISD ≤ 16A, di/dt ≤ 210A/µs, VDD ≤ V(BR)DSS,
TJ ≤ 175°C
Pulse width ≤ 300µs; duty cycle ≤ 2%. VDD = 25V, starting TJ = 25°C, L = 2.0mH
RG = 25Ω, IAS = 16A. (See Figure 12)
Parameter Min. Typ. Max. Units Conditions
ISContinuous Source Current MOSFET symbol
(Body Diode) showing the
ISM Pulsed Source Current integral reverse
(Body Diode) p-n junction diode.
VSD Diode Forward Voltage ––– ––– 1.3 V TJ = 25°C, IS = 16A, VGS = 0V
trr Reverse Recovery Time ––– 170 250 ns TJ = 25°C, IF = 16A
Qrr Reverse Recovery Charge ––– 1 .1 1.6 µ C di/dt = 100A/µs
Source-Drain Ratings and Characteristics
A
––– ––– 110
––– ––– 33
S
D
G
Uses IRF540N data and test conditions.
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Fig 1. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance
Vs. Temperature
Fig 2. Typical Output Characteristics
1
10
100
1000
0.1 1 10 100
I , Drain-to-S o urc e Curren t (A)
D
V , D rain-to-S ourc e Vo lta
g
e
(
V
)
DS
VG S
TOP 15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTO M 4.5V
20
µ
s PULSE W IDTH
T = 2 5°C
C
A
4.5V
1
10
100
1000
0.1 1 10 100
4.5V
I , D rain-to-Source Current (A)
D
V , Dra in-t o-So u rc e V o lta
g
e
(
V
)
DS
VGS
TOP 15V
1 0V
8 .0V
7 .0V
6 .0V
5 .5V
5 .0V
BOTTOM 4.5V
20
µ
s P ULSE WIDTH
T = 17 5°C
C
A
1
10
100
1000
45678910
T = 25°C
J
GS
V , G a te-to -S o urce Vo lta
g
e (V)
D
I , D ra in -to -S o urc e C urr en t ( A)
V = 50 V
20µs PULSE WIDTH
DS
T = 175°C
J
A
0.0
0.5
1.0
1.5
2.0
2.5
3.0
-60 -40 -20 0 20 40 60 80 100 120 140 160 180
J
T , Junction Tem perature (°C)
R , D ra in-to -S o u rc e O n R e s is ta nc e
DS(on)
(Normalized)
V = 10 V
GS
A
I = 2 7A
D
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Fig 7. Typical Source-Drain Diode
Forward Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 8. Maximum Safe Operating Area
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
0
400
800
1200
1600
2000
2400
1 10 100
C , Capacitance (pF)
DS
V , Dr ain -to -So u rc e Volt a
g
e
(
V
)
A
V = 0 V , f = 1 MHz
C = C + C , C S H O RT E D
C = C
C = C + C
GS
is s gs gd ds
rss gd
os s ds g d
C
iss
C
oss
C
rss
0
4
8
12
16
20
0 20 40 60 80 100
Q , To ta l Gate Ch a r
g
e
(
nC
)
G
V , Ga te -to- S ou r ce V o lta ge (V)
GS
V = 8 0 V
V = 5 0 V
V = 2 0 V
DS
DS
DS
A
FOR TEST CIRCUIT
SEE F IG U RE 1 3
I = 1 6 A
D
10
100
1000
0.4 0.8 1.2 1.6 2.0
T = 25°C
J
V = 0 V
GS
V , S ourc e-to-Drain Voltage (V )
I , R e ve rs e D r ain C u rre n t (A )
SD
SD
A
T = 175°C
J
1
10
100
1000
1 10 100 1000
V , Dr a in- to -S o u r ce Volta
g
e
(
V
)
DS
I , Dr ain C u rre nt (A)
O P ER A T IO N IN T HIS A RE A L IM IT E D
B Y R
D
DS(on)
10µs
100µs
1ms
10ms
A
T = 2 5 °C
T = 1 7 5° C
Sin
g
le Pulse
C
J
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Fig 9. Maximum Drain Current Vs.
Case Temperature
Fig 10a. Switching Time Test Circuit
V
DS
90%
10%
V
GS t
d(on)
t
r
t
d(off)
t
f
VDS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
Fig 10b. Switching Time Waveforms
RD
VGS
RGD.U.T.
10V
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
+
-
VDD
25 50 75 100 125 150 175
0
5
10
15
20
25
30
35
T , Case Temperature ( C)
I , Drain Current (A)
°
C
D
0.01
0.1
1
10
0.00001 0.0001 0.001 0.01 0.1 1
Notes:
1. Duty factor D = t / t
2. Peak T =P x Z + T
1 2
JDM thJC C
P
t
t
DM
1
2
t , Rectangular Pulse Duration (sec)
Thermal Response (Z )
1
thJC
0.01
0.02
0.05
0.10
0.20
D = 0.50
SINGLE PULSE
(THERMAL RESPONSE)
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Fig 12a. Unclamped Inductive Test Circuit
V
DS
L
D.U.T.
V
DD
I
AS
t
p
0.01Ω
R
G
+
-
t
p
V
DS
I
AS
V
DD
V
(BR)DSS
10 V
Fig 12b. Unclamped Inductive Waveforms
D.U.T. V
DS
I
D
I
G
3mA
V
GS
.3µF
50KΩ
.2µF
12V
Current Regulator
Same Type as D.U.T.
Current Sampling Resistors
+
-
Fig 13b. Gate Charge Test Circuit
Q
G
Q
GS
Q
GD
V
G
Charge
10 V
Fig 13a. Basic Gate Charge Waveform
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
0
100
200
300
400
500
600
700
25 50 75 100 125 150 175
J
E , Sing le Pu ls e Ava lan c he Ene rg y (mJ )
AS
A
Startin
g
T , J unc tion T em perature
(
°C
)
V = 2 5 V
I
TOP 6 .6A
1 1A
BO TTOM 16 A
DD
D
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P.W. Period
di/dt
Diode Recovery
dv/dt
Ripple ≤5%
Body Diode Forward Drop
Re-Applied
Voltage
Reverse
Recovery
Current Body Diode Forward
Current
V
GS
=10V
V
DD
I
SD
Driver Gate Drive
D.U.T. I
SD
Waveform
D.U.T. V
DS
Waveform
Inductor Curent
D = P.W.
Period
+
-
+
+
+
-
-
-
Fig 14. For N-Channel HEXFETS
* VGS = 5V for Logic Level Devices
Peak Diode Recovery dv/dt Test Circuit
RGVDD
• dv/dt controlled by RG
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
D.U.T Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
*
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Package Outline
TO-247AC Outline
Dimensions are shown in millimeters (inches)
TO-247AC
Part Marking Information
LEAD ASSIGNMENTS
NOTES:
- D - 5.30
(
.209
)
4.70
(
.185
)
2.5 0
(
.089
)
1.5 0
(
.059
)
4
3X 0.80
(
.031
)
0.40
(
.016
)
2.60
(
.102
)
2.20
(
.087
)
3.40
(
.133
)
3.00
(
.118
)
3X
0.2 5
(
.010
)
MCA
S
4.3 0
(
.170
)
3.7 0
(
.145
)
- C -
2X 5.50
(
.217
)
4.50
(
.177
)
5.50
(
.217
)
0.25
(
.010
)
1.4 0
(
.056
)
1.0 0
(
.039
)
3.65
(
.143
)
3.55
(
.140
)
D
MM
B
- A -
15.90
(
.626
)
15.30
(
.602
)
- B -
123
20.30
(
.800
)
19.70
(
.775
)
14.80
(
.583
)
14.20
(
.559
)
2.40
(
.094
)
2.00
(
.079
)
2X
2X
5.45
(
.215
)
1 DIMENSIONING & TOLERANCING
PER ANSI Y 14 .5 M, 1 9 82.
2 CONTROLLING DIMENSION : INCH.
3 CONFORMS T O J EDEC OUTL IN E
T O-24 7-AC.
1 - GATE
2 - DRAIN
3 - SOURCE
4 - DRAIN
INTERNATIONAL
R EC TIFIER
L OGO
ASSEMBLY
LOT CODE
EX AMPL E : THIS IS AN IRF PE3 0
W ITH ASSEMB LY
LOT CODE 3A 1Q PART NUMBER
DATE CODE
(YYWW)
YY = YEAR
WW WEEK
3A1Q 9302
IRFPE30
A
WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 322 3331
IR GREAT BRITAIN: Hurst Green, Oxted, Surrey RH8 9BB, UK Tel: ++ 44 1883 732020
IR CANADA: 15 Lincoln Court, Brampton, Ontario L6T3Z2, Tel: (905) 453 2200
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IR TAIWAN:16 Fl. Suite D. 207, Sec. 2, Tun Haw South Road, Taipei, 10673, Taiwan Tel: 886-2-2377-9936
http://www.irf.com/ Data and specifications subject to change without notice. 8/98
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Note: For the most current drawings please refer to the IR website at:
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