TDA5211XUMA1 - INFINEON TECHNOLOGIES AG

Wireless Components

ASK/FSK Single Conversion Receiver

TDA 5211 Version 2.0

Specification May 2001

Edition 05.01

Published by Infineon Technologies AG,

Balanstraße 73,

815 41 Mü nc he n

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Revision History

Current Version: 2 .0 as of 18.05.01

Previous Version: 1.1, Dec. 2000

Page

(in previ-

ous Ver-

sion)

Page

(in current

Version)

Subjects (major changes since last revision)

3-12 3-12 Sec. 3.4.8: max. datarate changed, Sec. 3.4.9: max. output current changed

4-4 4-4 value of a changed to 1.414

4-13 4-13 value for C2 changed to 22nF according to bill of materials, τ2 and T2 changed

5-3 5-3 min. supply current limits added, max. limits changed

5-4 5-4 supply current max. limit changed, min. limit added

5-5 5-5 3VOUT min. & max. limits changed, TAGC typ. & max. values changed

5-6 5-6 Section “SLICER” reworked, max. datarate at given load capacitance quoted,

high output voltage limits changed, precharge current: min., max. limits changed

5-7 5-7 PDO load and leakage currents limits and typ. values changed, FSK demodula-

tion gain min. limit changed

5-9 5-9 PDWN-curre nt max. l imit c hanged , supply current s min . limi ts adde d, max . limits

changed, 3VOUT min. & max. limits changed, ITAGC_out limits chan ge d

5-10 5-10 Section “SLICER” reworked, max. datarate at given load capacitance quoted,

high ou tput vo ltage lim its cha nged, prec harge cu rrent: min., max. li mits ch anged,

PDO output voltage removed

5-15 5-15 C18 value changed

Product Info

Wireless Components

Specific ation, May 2001

Package

TDA 5211

Product Info

General Description The IC is a very lo w power consump-

tion single chip FSK/ASK Superhet-

erodyne Receiver (SHR) for the

frequency band 310 to 350 MHz that is

pin comp atible with the ASK Receiv er

TDA5201. The IC offers a high level of

integration and needs only a few exter-

nal components. The device contains

a low noise amplifier (LNA), a double

balanced mixer, a fully integrated

VCO, a PLL synthesiser, a crystal

oscillator, a limiter with RSSI genera-

tor, a PLL FSK demodulator, a data fil-

ter, a data comparator (slicer) and a

peak detector. Additionally there is a

power down feature to save battery

life.

Features ■Low su pply current (Is = 5.7 mA

typ. in FSK mode, Is = 5 mA typ. in

ASK mode)

■Supply voltage range 5V ±10%

■Power down mode with very low

supply current (50nA typ.)

■FSK and ASK demodulation capa-

bility

■Fully integrated VCO and PLL

Synthesiser

■ASK sensitivity better than

-110 dBm over specified tempera-

ture range (- 40 to +105°C)

■Selectable frequency ranges 310-

330 MHz and 330-350 MHz

■Limiter with RSSI generation,

operating at 10.7MHz

■Selectable reference frequency

■2nd order low pass data filter with

external capacitors

■Data slicer with self-adjusting

threshold

■FSK sensitivity better than

-102 dBm over specified tempera-

ture range (- 40 to +105°C)

Applications ■Keyless Entry Systems

■Remote Control Systems

■Alarm Systems

■Low Bitrate Communication

Systems

Ordering Information

Type Ordering Code Package

TDA 5211 Q67037-A1147 P-TSSOP-28-1

samples available

1Table of Contents

1 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i

2 Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2.2 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2.4 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

3.1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

3.2 Pin Definition and Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

3.3 Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.4 Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.4.1 Low Noise Amplifier (LNA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.4.2 Mixer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.4.3 PLL Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.4.4 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.4.5 Limiter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.4.6 FSK Demodulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.4.7 Data Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.4.8 Data Slicer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.4.9 Peak Detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.4.10 Bandgap Reference Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

4.1 Choice of LNA Threshold Voltage and Time Constant. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

4.2 Data Filter Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

4.3 Quartz Load Capacitance Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

4.4 Quartz Frequency Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

4.5 Data Slicer Threshold Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

4.6 ASK/FSK Switch Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

4.6.1 FSK Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

4.6.2 ASK Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

4.7 Principle of the Precharge Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

5 Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

5.1 Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

5.1.2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

5.1.3 AC/DC Characteristics at TAMB = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

5.1.4 AC/DC Characteristics at TAMB = -40 to 105°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

5.2 Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5.3 Test Board Layouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

5.4 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.5 Appendix - Noise Figure and Gain Circles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2Product Description

2.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

2.2 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

2.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

2.4 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

Contents of this Chapter

Product Description

2 - 2

TDA 5211

Wireless Components

Specific ation, May 2001

2.1 Overview

The IC is a very low power consumption single chip FSK/ASK Superheterodyne

Receiv er (SHR) fo r receiv e frequenci es between 310 and 350 MHz that is pin

compatible to the ASK Receiver TDA5201. The IC offers a high level of integra-

tion and needs only a few external components. The device contains a low

noise amp lifier (L NA), a double balanc ed mixer, a full y integrated VC O, a PLL

synthesiser, a crystal oscillator, a limiter with RSSI generator, a PLL FSK

demodulator, a data filter, a data comparator (slicer) and a peak detector. Addi-

tionally there is a power down feature to save battery life.

2.2 Application

■Keyless Entry Syste ms

■Remote Control Systems

■Alarm Systems

■Low Bitrate Communication Systems

2.3 Features

■Low supply current (Is = 5.7 mA typ.FSK mode, 5mA typ. ASK mode)

■Supply voltage range 5V ±10%

■Power down mode with very low supply current (50nA typ.)

■FSK and ASK demodulation capability

■Fully integrated VCO and PLL Synthesiser

■RF input sensitivity ASK -113dBm typ. at 25°C, better than -110dBm over

complete specified operating temperature range (-40 to +105°C)

■RF input sen si tiv it y FSK -1 05d Bm typ . at 25°C, better than -102dBm over

complete specified operating temperature range (-40 to +105°C)

■Receive frequency range between 310 and 350 MHz

■Selectable reference frequency

■Limiter with RSSI generation, operating at 10.7MHz

■2nd order low pass data filter with external capacitors

■Data slicer with self-adjusting threshold

Product Description

2 - 3

TDA 5211

Wireless Components

Specific ation, May 2001

2.4 Package Outlines

P_TSSOP_28.EPS

Figure 2-1 P-TSSOP-28-1 package outlines

3Functional Description

3.1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2

3.2 Pin Definition and Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

3.3 Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9

3.4 Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9

Contents of this Chapter

Functional Description

3 - 2

TDA 5211

Wireless Components

Specific ation, May 2001

3.1 Pin Configuration

Pin_Configuration_5211.wmf

Figure 3-1 IC Pin Configur atio n

CRST2

PDWN

PDO

DATA

3VOUT

THRES

FFB

OPP

SLN

SLP

LIMX

LIM

CSEL

MSEL

CRST1

VCC

LNI

TAGC

AGND

LNO

VCC

MIX

AGND

FSEL

IFO

DGND

VDD

TDA 5211

Functional Description

3 - 3

TDA 5211

Wireless Components

Specific ation, May 2001

3.2 Pin Defini tion and Function

In the subsequent table the internal circuits connected to the pins of the device

are shown. ESD-protection circuits are omitted to ease reading.

Table 3-1 Pin Definition and Function

Pin No. Symbol Equivalent I/O-Schematic Function

1CRST1 External Crystal Connector 1

2VCC 5V Supply

3LNI LNA Input

4.15V

50uA

57uA

500uA

Functional Description

3 - 4

TDA 5211

Wireless Components

Specific ation, May 2001

4TAGC AGC Time Constant Control

5AGND Analogue Gro und Retu rn

6LNO LNA Output

7VCC 5V Supply

MIX

Mixer Input

Complementary Mixer Input

10 AGND Analogue Gro und Retu rn

11 FSEL not applicable - has to be left

open

3uA

1.4uA

1.7V

4.3V

1.7V

400uA

2k 2k

Functional Description

3 - 5

TDA 5211

Wireless Components

Specific ation, May 2001

12 IFO 10.7 MHz IF Mixer Output

13 DGND Digital Ground Return

14 VDD 5V Supply (PLL Counter Cir-

cuitry)

15 MSEL ASK/FSK Modulati on Form at

Selector

16 CSEL 6.xx or 13.xx MHz Quartz

Selector

2.2V

4.5k

300uA

1.2V

3.6k

1.2V

80k

Functional Description

3 - 6

TDA 5211

Wireless Components

Specific ation, May 2001

LIM

LIMX

Limiter Input

Complementary Limiter Input

19 SLP Data Slicer Positive Input

20 SLN Data Slicer Negative Input

21 OPP OpAmp Noninverting Input

330

15k

2.4V

75uA

80µA

15uA

100

5uA

20 10k

21 200

5uA

Functional Description

3 - 7

TDA 5211

Wireless Components

Specific ation, May 2001

22 FFB Data Filter Feedback Pin

23 THRES AGC Threshold Input

24 3VOUT 3V Reference Output

25 DATA Data Output

100k

5uA

10k

5uA

3.1V

24 20k

25 500

40k

Functional Description

3 - 8

TDA 5211

Wireless Components

Specific ation, May 2001

26 PDO Peak Detector Output

27 PDWN Power Down Input

28 CRST2 External Crystal Connector 2

26 200

220k

4.15V

50uA

Functional Description

3 - 9

TDA 5211

Wireless Components

Specific ation, May 2001

3.3 Functional Block Diagr am

Functional_diagram_5211.wmf

Figure 3-2 Main Block Diagram

3.4 Functional Blocks

3.4.1 Low Noise Amplifier (LNA)

The LNA is an on-chip cascode amplifier with a voltage gain of 15 to 20dB. The

gain fig ure i s determi ned by the exter nal m atching ne twork s situate d ahead of

LNA and between the LNA output LNO (Pin 6) and the Mixer Inputs MI and MIX

(Pins 8 and 9). The noise figure of the LNA is app roximately 3dB, the current

consum ption is 500µA. The gain can be reduc ed by approximatel y 18dB. The

swit ching point o f this AG C action can be determ ined exte rnally by applyin g a

threshold voltage at the THRES pin (Pin 23). This voltage is compared internally

with the re ceived sign al (RSSI) le vel gener ated by the li miter circui try. In case

that the RSSI level is higher than the threshold voltage the LNA gain is reduced

and vice versa. The threshold voltage can be generated by attaching a voltage

divider between the 3VOUT pin (Pi n 24) which provides a t emperature stable

3V outpu t gen er ate d fr om the int ernal ban dga p v ol tage and the THRES pin as

described in Section 4.1. The time constant of the AGC action can be deter-

PDO

: 1 / 2 VCO : 128 / 64 Φ

DET CRYSTAL

OSC

DATA

Crystal

PDWN

CSEL(FSEL)

Loop

Filter Bandgap

Reference

UREF

LNA

SLICER

TAGC

TDA 5211

VCC

VCC AGND

AGC

Reference

THRES

3VOUT

FSK

PLL Demod

OTA

PEAK

DETECTOR

LNI

DGND

MIXLNO MI OPPFFB SLP

VCC

LIM LIMX

Filter

IFO SLN

MSEL

LIMITER

68912 1718 22 21 19 20

13 2,7 5,10 11

16 1 28 27

+ASK

FSK

Functional Description

3 - 10

TDA 5211

Wireless Components

Specific ation, May 2001

mined by connecting a capacitor to the TAGC pin (Pin 4) and should be chosen

along with the appr opriate thre shold volta ge according to the intended operat-

ing cas e and interference s cenario to be expe cted during oper ation. The opti-

mum choice of AGC time constant and the threshold voltage is described in

Section 4.1.

3.4.2 Mixer

The Double Balanced Mixer downconverts the input frequency (RF) in the

range of 310-350MHz to the intermediate frequency (IF) at 10.7MHz with a vol-

tage gain of approximately 21dB by utilising either high- or low-side injection of

the local oscillator signal. In case the mixer is interfaced only single-ended, the

unused mixer input has to be tied to ground via a capacitor. The mixer is fol-

lowed by a low pass filter with a corner frequency of 20MHz in order to suppress

RF signals to appear at the IF output (IFO pin). The IF output is internally con-

sisting of an emitter follower that has a source impedance of approximately

330Ω to facilitate interfacing the pin directly to a standard 10.7MHz ceramic filter

without additional matching circuitry.

3.4.3 PLL Synthesizer

The Phase Locked Loop synthesizer consists of a VCO, an asynchronous

divide r chain, a ph ase detector wi th charge pump and a l oop filter and is fully

implemented on-chip. The VCO is including spiral inductors and varactor

diodes. The FSEL pin (Pin11) has to be left open. The tuning range of the VCO

was designed to guarantee over production spread and the specified tempera-

ture range a receive frequency range between 310 and 350MHz depending on

whethe r hi gh- or l ow- side i nj ec tio n o f the lo cal o sc ill ator is u se d. The os ci ll ator

signal is fed both to the synthesiser divider chain and to a divider that is dividing

the signal by 2 before it is applied to the downconverting mixer. Local oscillator

high side injection has to be used for receive frequencies between approxi-

mately 310 and 330 MHz, low side injection for receive frequencies between

330 and 350MHz - see also Section 4.4..

3.4.4 Crystal O scillator

The on-chip crystal oscillator circuitry allows for utilisation of quartzes both in

the 5 and 10MHz range as the overall division ratio of the PLL can be switched

between 32 and 64 via the CSEL (Pin 16 ) p i n ac co rd in g t o th e fo l lo w in g t able.

Table 3-2 CSEL Pin Operating States

CSEL Crystal Frequency

Open 5.xx MHz

Shorted to ground 10.xx MHz

Functional Description

3 - 11

TDA 5211

Wireless Components

Specific ation, May 2001

The c al cu l at i on of t he v al u e of t h e nece ss ary qu ar tz lo a d ca pa ci t a nc e i s s h ow n

in Section 4.3, the quartz frequency calculation is explained in Section 4.4.

3.4.5 Limiter

The Limiter is an AC coupled multistage amplifier with a cumulative gain of

approximately 80 dB that has a bandpass-characteristic centred around

10.7 MHz. It has a typical input impedance of 330 Ω to allow for easy interfacing

to a 10.7 MHz ceramic IF filter. The limiter circuit also acts as a Receive Signal

Strength Indicator (RSSI) generator which produces a DC voltage that is

directly proportional to the input signal level as can be seen in Figure 4-2. This

signal is used to demodulate ASK-modulated receive signals in the subsequent

baseband circuitry. The RSSI output is applied to the modulation format switch,

to the Peak Detector input and to the AGC circuitry.

In order to demodulate ASK signals the MSEL pin has to be left open as

described in the next chapter.

3.4.6 FSK Demodulator

To demodulate frequency shift keyed (FSK) signals a PLL circuit is used that is

contain ed fully on chi p. T he Li mit er outp ut d iffe renti al si gna l i s f ed to the li near

phase detector as is the output of the 10.7 MHz center frequency VCO. The

demodulator gain is typically 140µV/kHz. The passive loop filter output that is

comprised fully on chip is fed to both the VCO and the modulation format switch

described in more detail below. This signal is representing the demodulated sig-

nal with low frequencies applied to the demodulator demodulated to logic ones

and high frequencies demodulated to logic zeroes. However this is only valid in

case the lo cal osci llator is low- side injec ted to the mixer which is applic able to

receive frequencies above 330MHz (e.g. 345MHz). In case of receive frequen-

cies below 330MHz (e.g.315MHz) high frequencies are demodulated as logical

ones due to a s ign inversion in the downconv ersion mixin g process. See also

Section 4.4.

The modulation format switch is actually a switchable amplifier with an AC gain

of 11 t hat is co ntrolle d by the MSEL pin (Pin 15) as shown in the following table.

This gain was chosen to facilitate detection in the subsequent circuits. The DC

gain is 1 in order not to saturate the su bsequent Data Filt er wih the DC offset

produced by the demodulator in case of large frequency offsets of the IF signal.

The r esult ing freq uency charac teristi c and detai ls on the prin ciple o f op eration

of the switch are described in Section 4.6.

Table 3-3 MSEL Pin Operating States

MSEL Modulation Format

Open ASK

Shorted to ground FSK

Functional Description

3 - 12

TDA 5211

Wireless Components

Specific ation, May 2001

The demodulator circuit is switched off in c ase of reception of ASK signals.

3.4.7 Data Filter

The data filter comprises an OP-Amp with a bandwidth of 100kHz used as a

voltage follower and two 100kΩ on-chip resistors. Along with two external

capacitors a 2nd order Sallen-Key low pass filter is formed. The selection of the

capacitor values is described in Section 4.2.

3.4.8 Data Slicer

The da ta slicer is a fast compa rator with a b andwidth o f 100 kHz. Thi s allows

for a maximum receive data rate of up to 100kBaud. The maximum achievable

data rate also depends on the IF Filter bandwidth and the local oscillator toler-

ance v alu es . Bo th i npu ts are accessi ble. T h e ou tput del iv ers a di gi tal dat a sig-

nal (CMOS-like levels) for sbsequent circuits. The self-adjusting threshold on

pin 20 its generate d by RC-ter m or pe ak detecto r dependi ng on the baseba nd

coding scheme. The data slicer threshold generation alternatives are described

in more detail in Section 4.5.

3.4. 9 Peak Det ect or

The peak detector generates a DC voltage which is proportional to the peak

value of the receive data signal. An external RC network is necessary. The input

is co nnecte d to the output of the RSSI- output of the Limite r, the output is c on-

nec ted to t he PDO pin (Pin 26 ). This output can be used as an indicator for the

received signal strength to use in wake-up circuits and as a reference for the

data slicer in ASK mode. The output current is typically 950µA, the discharge

current is lower than 2µA. Note that the RSSI level is also output in case of FSK

mode.

3.4.10 Bandgap Reference Circuitry

A Band gap Re fer enc e Circ ui t p rovi des a te mpe rat ure st abl e r ef er ence vo ltage

for the device. A power down mode is available to switch off all subcircuits which

is controlled by the PWDN pin (Pin 27) as shown in the following table. The sup-

ply current drawn in this case is typically 50nA.

Table 3-4 PDWN Pin Operating States

PDWN Operating State

Open or tied to groun d Powerdown Mode

Tied to Vs Receiver On

4Applications

4.1 Choice of LNA Threshold Voltage and Time Constant. . . . . . . . . . . . 4-2

4.2 Data Filter Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4

4.3 Quartz Load Capacitance Calculation . . . . . . . . . . . . . . . . . . . . . . . . 4-5

4.4 Quartz Frequency Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6

4.5 Data Slicer Threshold Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7

4.6 ASK/FSK Switch Functional Description . . . . . . . . . . . . . . . . . . . . . . 4-8

4.7 Principle of the Precharge Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . .4-11

Contents of this Chapter

Applications

4 - 2

TDA 5211

Wireless Components

Specific ation, May 2001

4.1 Choice of LNA Threshold Voltage and Time Constant

In the fol lowi ng fig ur e th e in terna l c irc uit ry of the L N A a uto mati c gai n c ontr o l is

shown.

LNA_autom.wmf

Figure 4-1 LNA Automatic Gain Control Circuitry

The LNA automatic gain control circuitry consists of an operational transimped-

ance amplifier that is used to compare the received signal strength signal

(RSSI) gen erated by the Limiter with an externally provided threshold voltage

Uthres. As shown in the following figure the threshold voltage can have any

value b etween approxi mately 0.8 and 2. 8V to provide a switching poi nt within

the receive signal dynamic range.

This vo lt age Uthres is ap pl ied to the THRES pin (Pin 23) The threshol d volta ge

can be generated by attaching a voltage divider between the 3VOUT pin

(Pin 24) which provides a temperature stable 3V output generated from the

internal bandgap voltage and the THRES pin. If the RSSI level generated by the

Limiter is hig her than Uthres, the OTA ge nerates a positiv e current Iload. This

yields a voltage rise on the TAGC pin (Pin 4). Otherwise, the OTA generates a

negative current. These currents do not have the same values in order to

achieve a fast-attack and slow-release action of the AGC and are used to

charg e an ex te rnal c apa ci tor whi ch fin all y g ene ra tes t he LN A ga in c ont ro l v olt-

age.

LNA

RSSI (0.8 - 2.8V)

VCC

Gain control

voltage

OTA

+3 .1 V

load

RSS I > U

threshold

: I

load

=4.2µA

RSS I < U

threshold

: I

load

= -1. 5 µA

:< 2.6V : Gain high

:> 2.6V : Gain low

cmax

= V

- 0.7V

cmin

= 1.67V

R1 R2

Pins: 24 23

th re s hold

20k

Ω

Applications

4 - 3

TDA 5211

Wireless Components

Specific ation, May 2001

RSSI-AGC.wmf

Figure 4-2 RSSI Level and Permissive AGC Threshold Levels

The switching point should be chosen according to the intended operating sce-

nario. The determination of the optimum point is described in the accompanying

Application Note, a threshold voltage level of 1.8V is apparently a viable choice.

It sh ould be note d that the out put of the 3VOUT pin is capabl e of dr ivin g up to

50µA, but that the THRES pin input current is only in the region of 40nA. As the

current drawn out of the 3VOUT pin is directly related to the receiver power con-

sumption, the power divider resistors should have high impedance values. The

sum of R1 and R2 has to b e 600k Ω in or der to y ield 3V at the 3VOUT pin. R1

can thus be chos en as 240kΩ, R2 as 360k Ω to yield an ov erall 3VOUT output

current of 5µA1 and a threshold voltage of 1.8V

Note: If the LNA gain sha ll b e ke pt in eith er h igh or low gain m ode t his has to

be accomplished by tying the THRES pin to a fixed voltage. In order to achieve

high gain mode operation, a voltage higher than 2.8V shall be applied to the

THRES pin, such as a short to the 3VOLT pin. In order to achieve low gain

mode operation a voltage lower than 0.7V shall be applied to the THRES, such

as a short to ground.

As stated above the capacitor connected to the TAGC pin is generating the gain

contro l volt age of the LNA due to the c hargi ng and di scharg ing cu rren ts of the

OTA and thus is al so responsi ble for the AGC time cons tant. As the ch arging

and disc harging currents are not equal two di fferent time constants will resul t.

The time constant corresponding to the charging process of the capacitor shall

be cho sen accordi ng to the data rate. Ac cording to measurements performed

at Infineon the capacitor value should be greater than 47nF.

1. note the 20kΩ resistor in series with the 3.1V internal voltage source

LNA always

in high gain mode

0.5

1.5

2.5

-120 -110 -100 -90 -80 -70 -60 -50 -40 -30

Input Level at LNA Input [dBm]

THRES

Voltage Range

RSSI Level Range LNA always

in low gain mode

RSSI Level

Applications

4 - 4

TDA 5211

Wireless Components

Specific ation, May 2001

4.2 Data Filter Design

Utilising the on-board voltage follower and the two 100kΩ on-chip resistors a

2nd order Sallen-Key low pass data filter can be constructed by adding 2 exter-

nal capacitors between pins 19 (SLP) and 22 (FFB) and to pin 21 (OPP) as

depicted in the following figure and described in the following formulas1.

Filter_Design.wmf

Figure 4 -3 Data Filter Design

(1)(2)

with

(3)the quality factor of the poles

where

in case of a Bessel filter a = 1.3617, b = 0.618

and thus Q = 0.577

and in case of a Butterworth filtera = 1.414, b = 1

and thus Q = 0.71

Example: Butterworth fil ter with f3dB = 5kHz and R = 100kΩ:

C1 = 450pF, C2 = 225pF

1. taken from Tietze/Schenk: Halbleiter sch altu ngstechnik, Springer Berlin, 1999

Pins: 22 21 19

100k 100k

C12Q b

R2Πf3dB

----------------------=C2 b

4QRΠf3dB

---------------------------=

-------=

Applications

4 - 5

TDA 5211

Wireless Components

Specific ation, May 2001

4.3 Quartz Load Capacitance Calculation

The value of the capacitor necessary to achieve that the quartz oscillator is

operating at the intended frequency is determined by the reactive part of the

negative resistance of the oscillator circuit as shown in Section 5.1.3 and by the

quartz specifications given by the quartz manufacturer.

Quartz_load_5211.wmf

Figure 4-4 Determina tion of Se ries Capacitance Value for the Quartz Oscillat or

Crystal specified with load capacitance

with Cl the load capacitance (refer to the quartz crystal specification).

Example:

10.18 MHz: CL = 12 pF XL=870 ΩCS = 7.2 pF

This value may be obtained by putting two capacitors in series to the quartz,

such as 18pF and 22pF in the 5.1MHz case and 18pF and 12pF in the 10.2MHz

case.

Crystal Input

impedance

1-28

TDA5211

Pin 28

Pin 1

SXf

Applications

4 - 6

TDA 5211

Wireless Components

Specific ation, May 2001

4.4 Quartz Frequency Calculation

As des cribed in Section 3.4.3 the operat ing range of the on-chip VCO is wi de

enough to guarantee a receive frequency range between 310 and 350MHz. The

VCO signal is divided by 2 before applied to the mixer . This local oscillator sig-

nal can be used to downconvert the RF signals both with high- or low-side injec-

tion at the mixer. High-side injection of the local oscillator has to be used for

receive frequencies between 310 and 330 MHz. In this case the local oscillator

frequency is calculated by adding the IF frequency (10.7 MHz) to the RF fre-

quency. In this case the higher frequency of a FSK-modulated signal is

demodulated as a logical one (high).

Low-side injection has to be used for receive frequencies between 330 and

350 MHz. The local osc illator frequenc y is ca lculated by subt racting th e IF fre-

quency (10.7 M Hz) from the R F frequency then. Pleas e note that in this cas e

sign-inversion occurs and the higher frequency of a FSK-modulated signal is

demo dulated as a logical zer o (low). The overal l division ratios in the PLL ar e

64 or 32 depending on whether the CSEL-pin is left open or tied to ground.

Therefore the quartz frequency may be calculated by using the following for-

mula:

ƒQU = (ƒRF ± 10.7) / r

with ƒRF receive frequency

ƒLO local oscillator (PLL) frequency (ƒRF ± 10.7)

ƒQU quartz oscillator frequency

r ratio of local oscillator (PLL) frequency and quartz frequency as

shown in the subse que nt table

This yields the following examples:

CSEL tied to GND:

CSEL open:

Table 4-1 PLL Division Ratio Dependence on States of CSEL

CSEL Ratio r = (fLO/fQU)

open 64

GND 32

()

MHzMHzMHzf 1781.1032/7.10315

QU =+=

()

MHzMHzMHzf 4469.1032/7.10345

QU =−=

()

MHzMHzMHzf 0891.564/7.10315

QU =+=

()

MHzMHzMHzf 2234.564/7.10345

QU =−=

Applications

4 - 7

TDA 5211

Wireless Components

Specific ation, May 2001

4.5 D ata Slicer Threshold Generation

The thre shold of the data slicer can be generate d using an ext ernal R-C inte-

grator as shown in Figure 4- 5. The cut-off frequ ency of the R-C int egrator has

to be lower than the lowest fr equ enc y appear i ng in the data signal . In order to

keep distortion low, the minimum value for R is 20kΩ.

Data_slice1.wmf

Figure 4-5 Data Slicer Threshold Generation with External R-C Integrator

In case of ASK op eration a nother poss ibility for thr eshold generation i s to use

the peak detector in connection with two resistors and one capacitor as shown

in the following figure. The component values are depending on the coding

scheme and the protocol used.

Data_slice2.wmf

Figure 4-6 Data Slicer Threshold Generation Utilising the Peak Detector

Pins: 2019

data out

threshold

data slicer

data

filter

Pins: 20

19 25

data out

threshold

data slicer

data

filter

peak detector

Applications

4 - 8

TDA 5211

Wireless Components

Specific ation, May 2001

4.6 ASK/FSK Switch Functional Description

The TDA5211 is containing an ASK/FSK switch which can be controlled via

Pin 15 (MSEL). This switch is actually consisting of 2 operational amplifiers that

are hav ing a g ain of 1 i n cas e of the A SK am plifie r and a gai n of 11 i n case of

the FSK amplifier in order to achieve an appropriate demodulation gain charac-

teristic . In order to c ompensate for the DC-o ffset generat ed especi ally in case

of the FSK PLL demodulator there is a feedback connection between the

threshold voltage of the bit slicer compa rator (Pin 20) to the negative input of

the FSK switch amplifier. This is shown in the following figure.

ask_fsk_datapath.WMF

Figure 4-7 ASK/FSK mode datapath

4.6.1 FSK Mode

The FSK datapath has a bandpass characterisitc due to the feedback shown

above (highpass) and the data filter (lowpass). The lower cutoff frequency f2 is

determined by the external RC-combination. The upper cutoff frequency f3 is

determined by the data filter bandwidth.

The demodulation gain of the FSK PLL demodulator is 140µV/kHz. This gain is

increased by the gain v of the FSK switch, which is 11. Therefore the resulting

dynamic gain of this circuit is 1.5mV/kHz within the bandpass. The gain for the

DC content of FS K signal remains at 140µV /kHz. The cutoff fr equ enc ie s of the

bandp ass have to be chosen su ch that the spe ctr um of the da ta si gn al is in flu-

enced in an acceptable amount.

In case that the user data is containing long sequences of logical zeroes the

effect of the drift-off of the bit slicer threshold voltage can be lowered if the offset

voltage inher ent at the negativ e inpu t of the sl icer co mparator (Pin2 0) is use d.

The co mparator has no hysteresis bu ilt in .

=100k R

=100k

v = 1

=30k

=300k

DATA O u t

AC DC

typ. 2 V

1.5 V......2.5 V

0.18 mV/kHz

FSK PLL Demodulator

RSSI (ASK signal)

ASK/FSK Switch

ASK

FSK

ASK mode : v=1

FSK mode : v=11

15 MSEL

FFB OPP SLP SLN

Comp

Data Filter

Applications

4 - 9

TDA 5211

Wireless Components

Specific ation, May 2001

This offs et v oltage is gen erate d by the bia s c urr ent o f the neg ati ve inp ut of t he

comparator (i.e. 20nA) running over the external resistor R. This voltage raises

the volt age appearing at pin 20 (e.g. 1mV wi th R = 100kΩ). In order to obtain

benefit of this asymmetrical offset for the demodulation of long zeros the lower

of the two FSK frequencies should be chosen in the transmitter as the zero-

symbol frequency.

In the following figure the shape of the above mentioned bandpass is shown.

frequenzgang.WMF

Figure 4-8 Frequency characterstic in case of FSK mode

The cutoff frequencies are calculated with the following formulas:

f3 is the 3dB cutoff frequency of the data filter - see Section 4.2.

Example:

R = 100kΩ, C = 47nF

This leads tof1 = 44Hz and f2 = 485Hz

0dB

3dB

v-3dB

20dB/dec -40dB/dec

f1 f2 f3

gain (pin19)

0.18mV/kHz 2mV/kHz

f⋅

Ω+ Ω⋅

330

112 11 ffvf ⋅=⋅=

ff 33 =

Applications

4 - 10

TDA 5211

Wireless Components

Specific ation, May 2001

4.6.2 ASK Mode

In ca se the rece iver is operated in ASK m ode the data path frequ ency cha rac-

tersitic is dominated by the data filter alone, thus it is lowpass shaped.The cutoff

frequency is determined by the external capacitors C12 and C14 and the inter-

nal 100k resistors as described in Section 4.2

freq_ask.WMF

Figure 4-9 Frequency charcteristic in case of ASK mode

0dB

-3dB

-40dB/dec

f3dB

Applications

4 - 11

TDA 5211

Wireless Components

Specific ation, May 2001

4.7 Principle of the Precharge Circuit

In case the data slicer threshold shall be generated with an external RC network

as described in Section 4.5 it is necessary to use large values for the capacitor

C attached to the SLN pin (pin 20) in order to achieve long time constants. This

results also fro m the fact that the choic e of the v alue for R connec ted betwe en

the SLP and SLN pins (pins 19 and 20) is limited by the 330kΩ resistor appear-

ing in parallel to R as can be seen in Figure 4-7. Apart from this a resistor value

of 100 k Ω leads to a voltage offset of 1mv at the comparator input as described

in Section 4.6.1. The resulting startup time constant τ1 can be calculated with:

τ1 = (R // 330kΩ) · C

In case R is chosen to be 100kΩ and C is chosen as 47nF this leads to

τ1 = (100kΩ // 330kΩ) · 47nF = 77kΩ · 47nF = 3.6ms

When the device is turned on this time constant dominates the time necessary

for the device to be able to demodulate data properly. In the powerdown mode

the capacitor is only discharged by leakage currents.

In order to r educe the turn-on time in the presen ce of larg e values of C a pr e-

charge circuit was included in the TDA5211 as shown in the following figure.

precharge.WMF

Figure 4-10 Principle of the precharge circuit

load

+3.1V

20k

OTA

+2.4V

R1 R2

24 23 U

threshold

0 / 240uA +

20 19

Da ta Filter ASK/FSK Sw itch

Uc<UsUc>Us

U2<2.4V : I=240uA

U2 >2 .4 V : I=0

R1+R2=600k

Applications

4 - 12

TDA 5211

Wireless Components

Specific ation, May 2001

This circuit charges the capacitor C with an inrush current Iload of typically

220µA for a duration of T2 until the voltage Uc appearing on the capacitor is

equal to the voltage Us at the input of the data filter. This voltage is li mited to

2.5V. A s soon a s these vo ltages are equal or the dura tion T2 is exceeded t he

precharge circuit is disabled.

τ2 is the time constant of the charging process of C which can be calculated as

τ2 ≈ 20kΩ · C2

as the sum of R1 and R2 is sufficiently large and thus can be neglected. T2 can

then be calculated according to the following formula:

The voltage transient during the charging of C2 is shown in the following figure:

e-fkt1.WMF

Figure 4-11 Voltage appearing on C2 during precharging process

The v oltage appear ing on t he capacito r C c onnec ted to pin 20 is sho wn in t he

followi ng figure. It can b e seen that due to the fact that it is charged by a con-

stant current source it exhibits is a linear increase in voltage which is limited to

USmax = 2.5V which is also the approximate operating point of the data filter

input. The time constant appearing in this case can be denoted as T3, which

can be calcula ted with

6.1

34.2

ln 222 ⋅≈

−

ττ

2.4V

T3 USmax C⋅

220µA

------------------------2.5V

220µA

-----------------C⋅==

Applications

4 - 13

TDA 5211

Wireless Components

Specific ation, May 2001

e-Fkt2.WMF

Figure 4-12 Voltage transient on capacitor C attached to pin 20

As an example the choice of C2 = 22nF and C = 47nF yields

τ2 = 0.44ms

T2 = 0.71ms

T3 = 0.53ms

This means that in this case the inrush current could flow for a duration of

0.64ms but stops already after 0.49ms when the USmax limit has been reached.

T3 should always be chosen to be shorter than T2.

It has t o be noted finally that dur ing the turn-o n duratio n T2 the overall device

power consumption is increased by the 220µA needed to charge C.

The pr echarge circ uit may be dis abled if C2 is not equi pped. This y ields a T2

close to zero. Note that the sum of R4 and R5 has to be 600kΩ in order to pro-

duce 3V at the THRES p in as this vol tage is inter nally used als o as the refer-

ence for the FSK demodulator.

5Reference

5.1 Electrical Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2

5.2 Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11

5.3 Test Board Layouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-12

5.4 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14

Contents of this Chapter

Reference

5 - 2

TDA 5211

preliminary

Wireless Components

Specific ation, May 2001

5.1 Electrical Data

5.1.1 Absolute Maximum Ratings

WARNING

The maximum ratings may not be exceeded under any circumstances, not even

momentarily and individually, as permanent damage to the IC will result.

Table 5-1 Absolute Maximum Ratings, Ambient temperature TAMB=-40°C ... + 105°C

#Parameter Symbol Limit Va lues Unit Remarks

min max

1Supply Voltage Vs-0.3 5.5 V

2Junction Temperature Tj-40 +150 °C

3Storage Temperature Ts-40 +125 °C

4Thermal Re si st anc e RthJA 114 K/W

5ESD integrity, all pins excl. Pins 1,3, 6, 28

ESD integrity Pins 1,3,6,28 VESD +2

+1.5 kV

kV HBM

accordin g to

MIL STD

883D,

method

3015.7

Reference

5 - 3

TDA 5211

preliminary

Wireless Components

Specific ation, May 2001

5.1.2 Operating Range

Within the operational range the IC operates as explained in the circuit descrip-

tion. The AC/DC characteristic limits are not guaranteed. Currents flowing into

the device are denoted as positive currents and v.v.

Supply voltage: VCC = 4.5V .. 5.5V

Table 5-2 Operating Rang e, Am bient temperatu re TAMB= -40°C ... + 105°C

#Parameter Symbol Limit Values Unit Test Conditions L Item

min max

1Supply Current ISF

ISA

3.9

3.2 7.5

6.8 mA

mA fRF = 315MHz, FSK Mode

fRF = 315MHz, ASK Mode

2Receiver Inp ut Leve l

ASK

FSK, frequ. dev. ± 50kHz RFin -110

-102 -13

-13 dBm

dBm

@ source impedance 50Ω,

BER 2E-3, average power

level, Manchester encoded

datarate 4kBit, 280kHz IF

Bandwidth

■

3LNI Input Frequenc y fRF 310 350 MHz

4MI/X Input Frequency fMI 310 350 MHz

53dB IF Frequency Range

ASK

FSK fIF -3dB 5

10.4 23

11 MHz ■

6Powerdown Mode On PWDNON 00.8 V

7Powerdown Mode Off PWDNOFF 2 VSV

8Gain Control Voltage,

LNA high gain state VTHRES 2.8 VSV

9Gain Control Voltage,

LNA low gain state VTHRES 00.7 V

■ This value is guarante ed by design.

Reference

5 - 4

TDA 5211

preliminary

Wireless Components

Specific ation, May 2001

5.1. 3 AC/D C Cha rac teristi cs at TAMB = 25°C

AC/DC char a cte ris tic s inv ol ve the s pread of v alu es guar a ntee d wit hin the s pe-

cified voltage and ambient temperature range. Typical characteristics are the

median o f the produ ction. Cur rents flowi ng into the device are denoted as po-

sitive currents and vice versa.

The device performance parameters marked with ■ were measured on an

Infineon evaluation board as described in Section 5.2.

Table 5-3 AC/DC Characteristics with TA 25 °C, VVCC = 4.5 ... 5.5 V

Parameter Symbol Limit Values Unit Test Conditions L Item

min typ max

Supply

Supply Current

1Supply current,

standby mode IS PDWN 50 100 nA Pin 27 (PDWN)

open or tied to 0 V

2Supply current, devi ce

operating in FSK mode ISF 4.9 5.7 6.5 mA Pin 11 (FSEL)

open, Pin 15

(MSEL) tied to GND

3Supply current, devi ce

operating in ASK mode ISA 4.2 5 5.8 mA Pin 11 (FSEL)

open, Pin 15

(MSEL) open

LNA

Signal Input LNI (PIN 3), VTHRES > 2.8V, high gain mode

1Average Power Level

at BER = 2E-3

(Sensitivity)

RFin -113 dBm Manchester

encoded datarate

4kBit, 280kHz IF

Bandwidth

■

2Average Power Level

at BER = 2E-3

(Sensitivity) FSK

RFin -105 dBm Manchester enc.

datarate 4kBit,

280kHz IF Bandw.,

± 50kH z pk. dev.

■

3Input imped anc e,

fRF = 315 MHz S11 LNA 0.895 / -25.5 deg ■

4Input level @ 1dB C.P.

fRF=315 MHz P1dBLNA -14 dBm ■

5Input 3rd order intercept

point fRF = 315 MHz IIP3LNA -10 dBm fin = 315 & 317MHz ■

6LO signal feedthrough

at antenna port LOLNI -119 dBm ■

Signal Output LNO (PIN 6), VTHRES > 2.8V, high gain mode

1Gain fRF = 315 MHz S21 LNA 1.577 / 150.3 deg ■

2Output impedance,

fRF = 315 MHz S22 LNA 0.897 / -10.3 deg ■

Reference

5 - 5

TDA 5211

preliminary

Wireless Components

Specific ation, May 2001

Table 5-3 AC/DC Characteristics with TA 25 °C, VVCC = 4.5 ... 5.5 V (continued)

Parameter Symbol Limit Values Unit Test Conditions L Item

min typ max

3Voltage Gain Antenna

to MI fRF = 315 MHz GAntMI 21 dB ■

4Noise Figure NFLNA 2dB excluding matching

network loss - see

Appendix

■

Signal Input LNI, VTHRES = GND, low gain mode

1Input imped anc e,

fRF = 315 MHz S11 LNA 0.918 / -25.2 deg ■

2Input level @ 1dB C. P.

fRF = 315 MHz P1dBLNA -7 dBm matched input ■

3Input 3rd order intercept

point fRF = 315 MHz IIP3LNA -13 dBm fin = 315 & 317MHz ■

Signal Output LNO, VTHRES = GND, low gain mode

1Gain fRF = 315 MHz S21 LNA 0.193 / 153.7 deg ■

2Output impedance,

fRF = 315 MHz S22 LNA 0.907 / -10.5 deg ■

3Voltage Gain Antenna

to MI fRF = 315 MHz GAntMI 2dB ■

Signal 3VOUT (PIN 24)

1Output voltage V3VOUT 2.9 3.1 3.3 V 3VOUT Pin open

2Current out I3VOUT -3 -5 -10 µA see Section 4.1

Signal THRES (PIN 23)

1Input Voltage range VTHRES 0 VSVsee Section 4.1

2LNA low gain mode VTHRES 00.3 V

3LNA high gain mode VTHRES 3.3 VSVor shorted to VCC

4Current in ITHRES_in 5nA

Signal TAGC (PIN 4)

1Current out,

LNA low gain state ITAGC_out -3.6 -4.2 -5 µA RSSI > VTHRES

2Current in,

LNA high gain state ITAGC_in 11.62.2 µA RSSI < VTHRES

MIXER

Signal Input MI/MIX (PINS 8/9)

1Input imped anc e,

fRF = 315 MHz S11 MIX 0.954 / -10.9 deg ■

2Input 3rd order intercept

point IIP3MIX -25 dBm ■

Reference

5 - 6

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Specific ation, May 2001

Table 5-3 AC/DC Characteristics with TA 25 °C, VVCC = 4.5 ... 5.5 V (continued)

Parameter Symbol Limit Values Unit Test Conditions L Item

min typ max

Signal Output IFO (PIN 12)

1Output impedance ZIFO 330 Ω■

2Conversion Voltage

Gain fRF = 315 MHz GMIX 21 dB ■

3Noise Figure, SSB

(~DSB NF+3dB) NFMIX 13 dB ■

4RF to IF isolation ARF-IF 46 dB ■

LIMITER

Signal Input LIM/X (PINS 17/18)

1 Input Impedance ZLIM 264 330 396 Ω■

2RSSI dyna mic ra nge DRRSSI 60 80 dB

3RSSI linearity LINRSSI ±1dB ■

4Operating frequency

(3dB points) fLIM 510.723 MHz ■

DATA FILTER

1Useable bandwidth BWBB FILT 100 kHz ■

2RSSI Level at Data Fil-

ter Output SLP,

RFIN=-103dBm

RSSIlow 0.3 1VLNA in high gain

mode

3RSSI Level at Data Fil-

ter Output SLP,

RFIN=-30dBm

RSSIhigh 1.8 3VLNA in high gain

mode

SLICER

Signal Output DATA (PIN 25)

1Maxi mu m Da tar a te DRmax 100 kBps NRZ, 20pF capaci-

tive loadin g ■

2LOW output voltage VSLIC_L 00.1 V

3HIGH output voltage VSLIC_H VS-

1.3V VS-1V VS-

0.7V V

Slicer, Signal Output DATA (PIN 20)

1Precharge Curren t Out IPCH_SLN -100 -220 -300 µA see Section 4.7

Reference

5 - 7

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Table 5-3 AC/DC Characteristics with TA 25 °C, VVCC = 4.5 ... 5.5 V (continued)

Parameter Symbol Limit Values Unit Test Conditions L Item

min typ max

PEAK DETECTOR

Signal Output PDO (PIN 26)

1Load curr ent Iload -600 -950 -1300 µA

2Leakage current Ileakage 02001000 nA

CRYSTAL OSCILLATOR

Signals CRSTL1, CRISTL 2, (PINS 1/28)

1Operating frequency fCRSTL 511 MHz fundamental mode,

series resonance

2Input Impeda nc e

@ ~5MHz Z1-28 -850 +

j 625 Ω■

3Input Impeda nc e

@ ~10MHz Z1-28 -7 00 +

j 865 Ω■

4Serial Capa ci ty

@ ~5MHz CS 5=C1 9.7 pF

5Serial Capa ci ty

@ ~10MHz CS10=C1 7.2 pF

ASK/FSK Signal Switch

Signal MSEL (PIN 15)

1ASK Mode VMSEL 1.4 4Vor open

2FSK Mode VMSEL 00.2 V or tied to ground

FSK DEMODULATOR

1Demo dulation Gain GFMDEM 85 140 225 µV/

kHz

2Useable IF Bandwidth BWIFPLL 10.2 10.7 11.2 MHz

POWER DOWN MODE

Signal PDWN (PIN 27)

1Powerdown Mode On PWDNON 00.8 V

2Powerdown Mode Off PWDNOff 2.8 VSV

3Input bias current

PDWN IPDWN 19 µA Power On Mode

4Start-up Time until va lid

IF signal is de tected TSU 1ms

Reference

5 - 8

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Table 5-3 AC/DC Characteristics with TA 25 °C, VVCC = 4.5 ... 5.5 V (continued)

Parameter Symbol Limit Values Unit Test Conditions L Item

min typ max

PLL DIVIDER

Signal CSEL (PIN 16)

1fCRSTL range 5.xxMHz VCSEL 1.4 4Vor open

2 fCRSTL range

10.xxMHz VCSEL 00.2 V

3Input bias current

CSEL ICSEL -3 -5 -7 µA CSEL tied to GND

■ Measured only in lab.

Reference

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5.1. 4 AC/D C Cha rac teristi cs at TAMB = -40 to 105°C

Currents flowing into the device are denoted as positive currents and vice

versa.

Table 5-4 AC/DC Characteristics with TAMB= -40°C ... + 105°C, VVCC = 4.5 ... 5.5 V

Parameter Symbol Limit Values Unit Test Conditions L Item

min typ max

Supply

Supply Current

1Supply current,

standby mode IS PDWN 50 400 nA Pin 27 (PDWN)

open or tied to 0 V

2Supply current, devi ce

operating in FSK mode ISF 3.9 5.7 7.5 mA Pin 11 (FSEL) tied

to GND, Pin 15

(MSEL) tied to GND

3Supply current, devi ce

operating in ASK mode ISA 3.2 5 6.8 mA Pin 11 (FSEL)

open, Pin 15

(MSEL) open

Signal 3VOUT (PIN 24)

1Output voltage V3VOUT 2.9 3.1 3.3 V 3VOUT Pin open

2Current out I3VOUT -3 -5 -10 µA see Sect ion 4.1

Signal THRES (PIN 23)

1Input Voltage range VTHRES 0 VS-1V V see Section 4.1

2LNA low gain mode VTHRES 00.3 V

3LNA high gain mode VTHRES 3 VSVor shorted to Pin 24

4Current in ITHRES_in 5nA

Signal TAGC (PIN 4)

1Current out,

LNA low gain state ITAGC_out -1 -4.2 -8 µA RSSI > VTHRES

2Current in, LNA high

gain stat e VTAGC_in 0.5 1.5 5µARSSI < VTHRES

MIXER

1Conversion Voltage

Gain fRF = 315 MHz GMIX +19 dB

LIMITER

Signal Input LIM/X (PINS 17/18)

1RSSI dyna mic ra nge DRRSSI 60 80 dB

2RSSI Level at Data Fil-

ter Output SLP,

RFIN= -103dBm

RSSIlow 0.3 1VLNA i n high gain

mode

3RSSI Level at Data Fil-

ter Output SLP,

RFIN= -30dB m

RSSIhigh 1.8 3VLNA in high gain

mode

Reference

5 - 10

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Specific ation, May 2001

Table 5-4 AC/DC Characteristics with TAMB= -40°C ... + 105°C, VVCC = 4.5 ... 5.5 V

Parameter Symbol Limit Values Unit Test Conditions L Item

min typ max

DATA FILTER

Slicer, Signal Output DATA (PIN 25)

1Maxi mu m Da tar a te DRmax 100 kBps NRZ, 20pF capa ci -

tive loading ■

2LOW output voltage VSLIC_L 00.1 V

3HIGH output voltage VSLIC_H VS-

1.5V VS-1V VS-

0.5V V

Slicer, Signal Output DATA (PIN 20)

1Precharge Curren t Out IPCH_SLN -100 -220 -300 µA see Section 4.7

PEAK DETECTOR

Signal Output PDO (PIN 26)

1Load curr ent Iload -400 -850 -1400 µA

2Leakage current Ileakage 07002000 nA

CRYSTAL OSCILLATOR

Signals CRSTL1, CRSTL 2, (PINS 1/28)

1Operating frequency fCRSTL 511 MHz fundamental mode,

series resonance

ASK/FSK Signal Switch

Signal MSEL (PIN 15)

1ASK Mode VMSEL 1.4 4Vor open

2FSK Mode VMSEL 00.2 V

FSK DEMODULATOR

1Demo dulation Gain GFMDEM 105 140 245 µV/

kHz

2Useable IF Bandwidth BWIFPLL 10.4 10.7 11 MHz

POWER DOWN MODE

Signal PDWN (PIN 27)

1Powerdown Mode On PWDNON 00.8 V

2Powerdown Mode Off PWDNOff 2.8 VSV

3Start-up Time until va lid

signal is detected at IF TSU 1ms

PLL DIVIDER

Signal CSEL (PIN 16)

1fCRSTL range 5.xxMHz VCSEL 1.4 4Vor open

2 fCRSTL range

10.xxMHz VCSEL 00.2 V

3Input bias current

CSEL ICSEL -3 -5 -7 µA CSEL tied to GND

Reference

5 - 11

TDA 5211

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Specific ation, May 2001

5.2 Test Circuit

The device performance parameters marked with ■ in Section 5.1.3 were mea-

sured on an Infineon evaluati on board. This evaluation boar d can be obtain ed

together with evaluation boards of the accompanying transmitter device

TDA5101 in an evaluation kit that may be ordered on the INFINEON RKE

Webpage www.infineon.com/rke. In case a matching codeword is received,

decoded and accepted by the decoder the on-board LED will turn on. This sig-

nal is also accessible on a 2-pole pin connector and can be used for simple

remote-control applications. More information on the kit is available on request.

TDA521x_testboard_20_schematic.WMF

Figure 5-1 Schematic of the Evaluation Board

Reference

5 - 12

TDA 5211

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5.3 Test Board Layouts

tda521x_testboard_20_top.WMF

Figure 5-2 Top Side of the Evaluation Board

tda521x_testboard_20_bot.WMF

Figure 5-3 Bottom Side of the Evaluation Board

Reference

5 - 13

TDA 5211

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Specific ation, May 2001

tda521x_testboard_20_plc.EMF

Figure 5-4 Component Placement on the Evaluation Board

Reference

5 - 14

TDA 5211

preliminary

Wireless Components

Specific ation, May 2001

5.4 Bill of Materials

The following components are necessary for evaluation of the TDA5211 at

315 MHz without use of a Microchip HCS512 decoder.

Table 5-5 Bill of Materials

Ref Value Specification

R1 100kΩ0805, ± 5%

R2 100kΩ0805, ± 5%

R3 820kΩ0805, ± 5%

R4 240kΩ0805, ± 5%

R5 360kΩ0805, ± 5%

R6 10kΩ0805, ± 5%

L1 15nH Toko, PTL2012 -F15 N 0G

L2 12pF 0805,COG, ± 2%

C1 3.3 pF 0805, COG, ± 0.1pF

C2 10pF 0805, COG, ± 0.1pF

C3 6.8pF 0805, COG, ± 0.1pF

C4 100pF 0805, COG, ± 5%

C5 47nF 1206, X7R, ± 10%

C6 15nH Toko, PTL2012 -F15 N 0G

C7 100pF 0805, COG, ± 5%

C8 33pF 0805, COG, ± 5%

C9 100pF 0805, COG, ± 5%

C10 10nF 0805, X7R, ± 10%

C11 10nF 0805, X7R, ± 10%

C12 220pF 0805, COG, ± 5%

C13 47nF 0805, X7R, ± 10%

C14 470pF 0805, COG, ± 5%

C15 47nF 0805, COG, ± 5%

C16 12pF 0805, COG, ± 1%

C17 18pF 0805, COG, ± 1%

C18 22nF 0805, X7R, ± 5%

Q1 (315 + 10.7MHz)/32 HC49/U, fundamental mode, CL = 12pF,

e.g. 315 MHz: Jauch Q 10,178130-S11-1017-12-10/20

Q2 SFE10.7MA5-A Murata

X2, X3 142-0701-801 Johnson

Reference

5 - 15

TDA 5211

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Specific ation, May 2001

Pleas e note th at a ca pacit or has to be solde red in pl ace L 2 and a n induc tor i n

place C6.

The following components are necessary in addition to the above mentioned

ones for evaluation of the TDA5211 in conjunction with a Microchip HCS512

decoder.

S1-S3, S6

X1 2-pole pin connector

S4 3-pole pin connector, or not equipped

IC1 TDA 5211 Infineon

Table 5-6 Bill of Materials Addendum

Ref Value Specification

R7 100kΩ0805, ± 5%

R8 10kΩ0805, ± 5%

R9 100kΩ0805, ± 5%

R10 22kΩ0805, ± 5%

R11 100Ω0805, ± 5%

R12 100Ω0805, ± 5%

R13 100Ω0805, ± 5%

R14 100Ω0805, ± 5%

R21 22kΩ0805, ± 5%

R22 10kΩ0805, ± 5%

R23 22kΩ0805, ± 5%

R24 820kΩ0805, ± 5%

R25 560Ω0805, ± 5%

C19 10pF 0805, COG, ± 5%

C21 100nF 1206, X7R, ± 10%

C22 100nF 1206, X7R, ± 10%

IC2 HCS512 Microchip

S5, X4-X9 2-pole pin connector

T1, T2 BC 847B Infineon

D1 LS T670-JL Infineon

Reference

5 - 16

TDA 5211

preliminary

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Specific ation, May 2001

5.5 Appendi x - Noise Figure and Gain Circles

The following gain and noise figure circles were measured utilizing Microlab

Stub Stretchers and a HP8514 network analyser. Maximum gain is shown at

point 1 at 18.5 dB, minimum noise figure ist 1.9dB at point 2, step size of circles

is 0.5dB.

Figure 5-5 Gain and Noise Circles of the TDA5211 at 315 MHz.

Reference

5 - 17

TDA 5211

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Wireless Components

Specific ation, May 2001

List of Figures

List of Figures - 1

TDA 5211

Wireless Components

Specific ation, May 2001

List of Figures

Figure 2-1 P-TSSOP-28-1 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

Figure 3-1 IC Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2

Figure 3-2 M ain Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9

Figure 4-1 L NA Automatic Gain Control Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2

Figure 4-2 RSSI Level and Permissive AGC Threshold Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

Figure 4-3 Data Filter Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4

Figure 4-4 Determination of Series Capacitance Value for the Quartz Oscillator . . . . . . . . . . . . . . 4-5

Figure 4-5 Data Slicer Threshold Generation with External R-C Integrator . . . . . . . . . . . . . . . . . . 4-7

Figure 4-6 Data Slicer Threshold Generation Utilising the Peak Detector . . . . . . . . . . . . . . . . . . . 4-7

Figure 4-7 ASK/FSK mode datapath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8

Figure 4-8 Frequency characterstic in case of FSK mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9

Figure 4-9 Frequency charcteristic in case of ASK mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10

Figure 4-10 Principle of the precharge circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-11

Figure 4-11 Voltage appearing on C2 during precharging process . . . . . . . . . . . . . . . . . . . . . . . . . 4-12

Figure 4-12 Voltage transient on capacitor C attached to pin 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13

Figure 5-1 Schematic of the Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12

Figure 5-2 Top Side of the Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13

Figure 5-3 Bottom Side of the Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13

Figure 5-4 Component Placement on the Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14

Figure 5-5 Gain and Noise Circles of the TDA5211 at 315 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17

List of Tables

List of Tables - 1

TDA 5211

Wireless Components

Specific ation, May 2001

List of Tables

Table 3-1 Pin Definition and Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-3

Table 3-2 CSEL Pin Operating States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10

Table 3-3 MSEL Pin Operating States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11

Table 3-4 PDWN Pin Operating States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12

Table 4-1 PLL Division Ratio Dependence on States of CSEL . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6

Table 5-1 Absolute Maximum Ratings, Ambient temperature TAMB=-40°C ... + 105°C . . . . . . . . 5-2

Table 5-2 Operating Range, Ambient temperature TAMB= -40°C ... + 105°C . . . . . . . . . . . . . . . . 5-3

Table 5-3 AC/DC Characteristics with TA 25 °C, VVCC = 4.5 ... 5.5 V . . . . . . . . . . . . . . . . . . . . . 5-4

Table 5-4 AC/DC Characteristics with TAMB= -40°C ... + 105°C, VVCC = 4.5 ... 5.5 V . . . . . . . . . 5-9

Table 5-5 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15

Table 5-6 Bill of Materials Addendum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-16