ASAHI KASEI [AK 435 6]
M0072-E-03 2004/09
- 1 -
GENERAL DESCRIPTION
T he AK4356 is a high performance six channe ls DAC co rresponding to 9 6kHz sampling mode of DVD.
Two chann els of them can opera te up to 192kHz sampling fully correspond to DVD-Aud io stand ards. The
AK 43 56 int rod uce s the advanced multi-bit a rchitectu re for ∆Σ modulator. T his new architecture achieves
the wider dynamic range, while keeping much the same su perior distortion chara cteristics as conventional
Single B it way. In th e AK435 6, the an alog output s are filtered in the ana log domain by switched-capacitor
filter (SCF) with high tole ran ce t o cloc k jitte r. The analog outputs are full different ial out put, s o th e device
is suitable for hi-end applications.
FEATURES
128x Oversampling
Sampling Rate up to 192kHz for 2 channels mode,
96kHz for 6 channels mode
24 Bit 8 times Digital Filter with Sl o w roll -off opti on
Ripple: ±0.005dB, Attenuation: 75dB
THD+N: -94dB
DR, S/N: 112 dB
High Tolerance to Clock Jitter
Low Distortion Differential Output
Channel Independent Digital De-emphasis for 32, 44.1 & 48kHz sampling
Channel Independent Zero Detect Pin
Channel Indep e n d en t Digital A tten uator with soft-tran sition
Soft Mute
3-wire Seria l Interface for Volume Control
I/F format: MSB justified, LSB justified, I2S
TTL Level Digital I/F
Master Cloc k
Normal Speed: 256fs, 384fs, 512fs or 768fs
Double S pe ed: 128fs, 192fs, 256fs or 384fs
Power Supply: 4.75 to 5.25V
44pin LQFP Package
Ta: -40 to 85°C
192kHz 24Bit Six-Channel DAC for DVD-Audio
A
K
4356
ASAHI KASEI [AK 435 6]
M0072-E-03 2004/09
- 2 -
Bloc k Diagra m
SCF DA
C
DAT
T
DZFL1
LOUT1+
LOUT1-
SCF DA
C
DAT
T
DZFR1
ROUT1+
ROUT1-
SCF DA
C
DAT
T
DZFL2
LOUT2+
LOUT2-
SCF DA
C
DAT
T
DZFR2
ROUT2+
ROUT2-
SCF DA
C
DAT
T
DZFL3
LOUT3+
LOUT3-
SCF DA
C
DAT
T
DZFR3
ROUT3+
ROUT3-
Audio
I/F
Control
Register
AK4356
MCLK
LRCK
BICK
MCKO
LRCK
BICK
XTI
XTO
Controller
CS
CCLK
CDTI
LRCK
BICK
SDOUT1
SDOUT2
SDOUT3
AC3
SDTI1
SDTI2
SDTI3
ASAHI KASEI [AK 435 6]
M0072-E-03 2004/09
- 3 -
Ordering Guide
AK4356VQ -40∼+85°C 44pin LQFP(0.8mm pitch)
AKD4356 Evaluation Board
Pin Layout
LOUT1-
ROUT1+
1
LOUT1+
44
2
DZFL2 3
DZFR1 4
DZFL1 5
C
AD0 6
C
AD1 7
PDN 8
BICK 9
MCLK 10
DVDD 11
ROUT1-43
LOUT2+42
LOUT2-41
ROUT2+40
ROUT2-39
LOUT3+38
LOUT3-
37
ROUT3+36
ROUT3-35
A
VSS34
DVSS 12
SDTI1 13
SDTI2 14
SDTI3 15
LRCK 16
SMUTE 17
CCLK 18
CDTI 19
CSN 20
DFS0 21
CKS0 22
33
32
31
30
29
28
27
26
25
24
23
AVDD
VREFH
DZFR2
DZFL3
DZFR3
DZFE
DIF2
DIF1
DIF0
CKS2
CKS1
AK4356VQ
Top View
ASAHI KASEI [AK 435 6]
M0072-E-03 2004/09
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PIN/FUNCTION
No. Pin Name I/O Function
1 LOUT1- O DAC1 Lch Negative An alog Output Pin
2 LOUT1+ O DAC1 Lch Positive Analog Output Pin
3 DZFL2 O DAC2 Lch Zero Input Detect Pin
4 DZFR1 O DAC1 Rch Zero Input Detect Pin
5 DZFL1 O DAC1 Lch Zero Input Detect Pin
6 CAD0 I Chip Address 0 Pin
7 CAD1 I Chip Address 1 Pin
8 PDN I Power-Down & Reset P in
When “L”, the AK4356 is powered-down a nd the control registers ar e reset to
def ault state. If the s tate of CA D 0-1 c hange s, then the AK4 356 must be re se t by PDN .
9 BICK I Audio Seri al Dat a Cl ock Pin
10 MCLK I Master Clock Input Pin
11 DVDD - Digital Power Supply Pin , +4.75∼+5.25V
12 DVSS - Digital Ground Pin
13 SDTI1 I DAC1 Audio Serial Data Input Pin
14 SDTI2 I DAC2 Audio Serial Data Input Pin
15 SDTI3 I DAC3 Audio Serial Data Input Pin
16 LRCK I Audio Input Chann el Clock Pi n
17 SMUTE I Soft Mut e Pin (N ote)
When th is pi n goes to “H”, soft mute cycle is in itial iz ed.
When returning to “L”, the outpu t mute releases.
18 CCLK I C ontrol Data Clock Pin
19 CD TI I Control Da ta Input Pin
20 CSN I Chip Select Pin
T his pin sh ould be held to “H” except for access.
ASAHI KASEI [AK 435 6]
M0072-E-03 2004/09
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No. Pin Name I/O Function
21 DFS0 I Double Speed Sampling Mode 0 Pin (Note)
“ L”: Normal Speed, “H”: Double Speed at DFS1 bit = “0”.
22 CKS0 I Input Clock Select 0 Pin (Note)
23 CKS1 I Input Clock Select 1 Pin (Note)
24 CKS2 I Input Clock Select 2 Pin (Note)
25 DI F0 I Audio Data Interface For mat 0 Pi n (Note)
26 DIF1 I Aud io Da ta In t er face For m at 1 Pi n (Note)
27 DI F2 I Audio Data Interface For mat 2 Pi n (Note)
28 DZFE I Zero Input Detect Enable Pin (Not e)
29 DZFR3 O DAC3 Rch Zero Input Detect Pin
30 DZFL3 O DAC3 Lch Zero Input Detect Pin
31 DZFR2 O DAC2 Rch Zero Input Detect Pin
32 VREFH I Positi ve Voltage Reference Input Pin , AVDD
33 AVDD - Analog Power Supply Pi n
34 AVSS - Ana log Ground Pin, + 4 .75∼+5.25V
35 ROUT3- O DAC3 Rch Negative An alog Output Pin
36 ROUT3+ O DAC3 Rch Positive Analog Output Pin
37 LOUT3- O DAC3 Lch Negative Analog Output Pin
38 LOUT3+ O DAC3 Lch Positive Analog Output Pin
39 ROUT2- O DAC2 Rch Negative An alog Output Pin
40 ROUT2+ O DAC2 Rch Positive Analog Output Pin
41 LOUT2- O DAC2 Lch Negative Analog Output Pin
42 LOUT2+ O DAC2 Lch Positive Analog Output Pin
43 ROUT1- O DAC1 Rch Negative An alog Output Pin
44 ROUT1+ O DAC1 Rch Positive Analog Output Pin
Note: SMUTE , DFS0, CKS0, CKS1, CKS2, DIF0, DIF1, DIF2, DZFE pins are ORed with serial control register.
ASAHI KASEI [AK 435 6]
M0072-E-03 2004/09
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ABSOLUTE MAXIMUM RATINGS
(AVSS, DVSS=0V; Note 1)
Parameter Symbol min max Units
Power Supplies
Analog
Digital
|AVSS-DVSS| (Note 2)
AVDD
DVDD
∆GND
-0.3
-0.3
-
6.0
6.0
0.3
V
V
V
Input Current (any pins except for supplies) IIN - ±10 mA
An a l og In put Volt a ge VIN A -0. 3 AVDD +0 . 3 V
Digital Input Voltag e VIND -0.3 DVDD+0.3 V
Ambi ent Temperature Ta -4 0 85 °C
St or age T emp er a t ure Ts tg -6 5 150 °C
Note: 1. All voltages with respect to gr ound.
2. AVSS an d DVSS must be conn ected to the same analog ground plan e.
WARNING: Operation at or beyond these limits may resul t in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIO NS
(AVSS, DVSS=0V; Note 1)
Parameter Symbol min typ max Units
Power Supplies
(Note 3) Analog
Digital AVDD
DVDD 4.75
4.75 5.0
5.0 5.25
5.25 V
V
Note: 1. All voltages with respect to gr ound.
3. The power up sequence between AVDD and DVDD is not critical.
*AKM assumes no responsi bility for the usage beyond the conditions in thi s datash eet.
ASAHI KASEI [AK 435 6]
M0072-E-03 2004/09
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ANAL O G CHARACT E RIS T ICS
(Ta=25°C ; AVDD, DVDD= 5V; AVSS, DVSS=0 V; VREFH=AV DD; fs=44 . 1k Hz; BICK =6 4fs;
Signal Frequen cy = 1kHz ; 24bit Data; RL≥2kΩ; Mea s urement Frequency=20Hz ∼20kHz at 44.1kHz,
20Hz~40kHz at fs=96kHz, 20Hz~ 80kHz at fs=192kHz; un less ot herwise specified)
Parameter min typ max Units
Dynamic Characteristi cs (Note 4)
Resolution 24 Bits
S/(N+D)
fs=44.1kHz
fs=96kHz 88
86 94
92
dB
dB
DR (-60dBFS)
fs=4 4.1kHz, A-weighted
fs=96kHz 106
- 112
105
dB
dB
S/ N (Note 5,6)
fs=4 4.1kHz, A-weighted
fs=96kHz 106
- 112
105
dB
dB
Interchannel Isolation 90 110 dB
DC Accuracy
Interchannel Gain Mismatch 0.2 0.5 dB
Gain Drift (Note 7) 20 - ppm/°C
Output Vol tage (AOUT+) - (AOUT-) (Note 8) ±2.55 ±2.75 ±2.95 Vpp
Load Resistance (Note 9) 2 kΩ
Load Capacitance 25 pF
Power Supply Rejection (Note 10) 50 dB
Power Sup pl i e s
Power Supply Current
Norm al Operation (PDN = “H”)
AVDD
DVDD (fs=44.1kHz)
(fs=96kHz )
(fs=192kHz )
Power-Down-Mode (PDN = “L”)
AVDD+DVDD ( Note 11)
60
15
20
15
10
90
30
40
30
100
mA
mA
mA
mA
µA
Note: 4. Measured by UPD(ROHDE & SCHWARZ). Refer to t he evaluation board manual.
5. 107dB at CCIR-ARM weight ed
6. S/N is independen t of input bit length.
7. VREFH is constantly +5.0V.
8. Full scale voltage (0dB). Outpu t voltage scales with the voltage of VREFH pin.
AOUT(typ.@0 dB)=(AOUT+)-(AOUT-)=±2.75Vpp*VREFH/5.0
9. AC load
10. PSR is applied to AVDD, DVDD with 1kHz, 10 0mVp p. VREFH pin is held a constant volta ge.
11. All digital i nput pins including clock pins (MCLK, BICK an d LRCK) a re connected to DVSS.
ASAHI KASEI [AK 435 6]
M0072-E-03 2004/09
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FILTER CHARACTERISTICS (fs=4 4. 1kHz)
(Ta=25°C ; AVDD, DVDD=4.7 5∼5.25V; fs=44.1kHz; DFS1 = DFS0 = “0”; DEM=OFF)
Parameter Symbol min typ max Units
Digital Filter
Passban d (Note 12) ±0.01dB
-6.0dB PB 0
-
22.05 20.0
- kHz
kHz
Stopband ( N ote 12) SB 24.1 kHz
Passband Ripple PR ±0.005 dB
St opba nd Att enua t ion SA 75 d B
Group Delay (Note 13) GD - 27.2 - 1/fs
Digital Filter + SCF
Frequency Response: 0∼20.0kHz FR - ±0.2 - dB
Note: 12 . The passba nd and stopba nd fre quencie s scale with fs.
For exampl e, PB=0.4535*fs(@±0.01dB), SB=0.546*fs.
13. The calculating delay time which occurred by digital filtering. This t ime is from settin g the 16/20/24bit data
of both channels on the input r egister to the output of analog signal.
FILTER CHARACT E RIS T ICS (fs=9 6 kHz)
(Ta=25°C ; AVDD, DVDD=4.7 5∼5.25V; fs=96kHz; DFS1 = “0”; DFS0 = “1”; DEM=OFF)
Parameter Symbol min typ max Units
Digital Filter
Passban d (Note 14) ±0.01dB
-6.0dB PB 0
-
48.0 43.5
- kHz
kHz
Stopband ( N ote 14) SB 52.5 kHz
Passband Ripple PR ±0.005 dB
St opba nd Att enua t ion SA 75 d B
Group Delay (Note 13) GD - 27.2 - 1/fs
Digital Filter + SCF
Frequency Response: 0∼40.0kHz FR - ±0.3 - dB
Note: 14 . The passba nd and stopba nd fre quencie s scale with fs.
For exampl e, PB=0.4535*fs(@±0.01dB), SB=0.546*fs.
ASAHI KASEI [AK 435 6]
M0072-E-03 2004/09
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FILTER CHA RACTERIS T I CS (fs=192kHz)
(Ta=25°C ; AVDD, DVDD=4.7 5∼5.25V; fs=192kHz; DFS1 = “1”; DFS0 = “0”; D EM=OFF)
Parameter Symbol min typ max Units
Digital Filter
Passban d (Note 15) ±0.01dB
-6.0dB PB 0
-
96.0 87.0
- kHz
kHz
Stopband ( N ote 15) SB 105 kHz
Passband Ripple PR ±0.005 dB
St opba nd Att enua t ion SA 75 d B
Group Delay ( Note 13) GD - 27.2 - 1/fs
Digital Filter + SCF
Frequency Response: 0∼80.0kHz FR - ±0.5 - dB
Note: 15 . The passba nd and stopba nd fre quencie s scale with fs.
For exampl e, PB=0.4535*fs(@±0.01dB), SB=0.546*fs.
DIGIT AL CHARACTERIST ICS
(Ta=25°C ; AVDD, DVDD=4.7 5∼5.25V)
Parameter Symbol min typ max Units
Hig h -Level Input Voltag e
Low-Level Input Voltage VIH
VIL 2.2
- -
- -
0.8 V
V
Hight-Level Output Voltage (Iout= -100µA)
Low-Level Output Voltage (Iout= 100µA) VOH
VOL DVDD-0.5
- -
- -
0.5 V
V
Input Leakage Curr ent Iin - - ±10 µA
ASAHI KASEI [AK 435 6]
M0072-E-03 2004/09
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SWIT CHING CHARACTERIST ICS
(Ta=25°C ; AVDD, DVDD=4.7 5∼5.25V; CL=20pF)
Parameter Symbol min typ max Units
Master Clock Timing ( Not e 16 )
Frequency
Duty
fCLK
Duty
8.192
40
36.864
60
MHz
%
LRCK f requency (Note 17)
Normal Speed Mode (DFS1-0 = “00”)
Double Spe e d Mode (DFS1 -0 = “0 1”)
4 times Speed Mode (DFS1-0 = “10”)
Duty Cycle
fsn
fsd
fsq
Duty
32
64
128
45
48
96
192
55
kHz
kHz
kHz
%
Serial Interface Timing
BICK Period
Normal Speed Mode
Double Speed Mode
4 times Speed Mode
BICK Pulse Width Low
Pulse Width High
BICK “↑” to LRCK Edge (Note 18)
LRCK Edge to BICK “↑” (Note 18)
SDTI Hold Time
SDTI Setup Time
tBCK
tBCK
tBCK
tBCKL
tBCKH
tBLR
tLRB
tSDH
tSDS
1/128fs
1/64fs
1/64fs
33
33
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
Control Interface Timing
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN “↓” to CCLK “↑”
CCLK “↑” t o CSN “↑”
Rise Time of CSN
Fall Time of CSN
Rise Time of CCLK
Fall Time of CCLK
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
tCSH
tR1
tF1
tR2
tF2
200
80
80
40
40
150
50
50
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Power-d own/Reset Ti mi ng
PDN Pulse Width (Note 19)
tPDW
150
ns
Note: 16. For Double and 4 t imes Speed mode s please see Appendix A for relat ionship of MCLK and BCLK/LRC K.
17. If sampling speed mode (DFS0-1) changes, please reset by PDN pin or RSTN bit.
18. BICK ri sing edge must not occur at the same time as LRCK edge.
19. The AK4356 can be reset by PDN pin “L” upon power up.
If CKS0-2 or DFS0-1 changes, the AK4356 should be reset by PDN pin or RSTN bit.
ASAHI KASEI [AK 435 6]
M0072-E-03 2004/09
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Timing Diagram
VIH
MCLK VIL
tCLK
VIH
LRCK VIL
1/fs
tBCK
tBCKL
VIH
tBCKH
BICK VIL
Clock Timing
For Double and 4 times Speed modes timing p le ase see Ap pend ix A for relati onship of MCLK and BCLK/LRCK.
tLRB
LRCK
VIH
BICK VIL
tSDS
VIH
SDTI VIL
tSDH
VIH
VIL
tBLR
Audi o In t er face T im ing
ASAHI KASEI [AK 435 6]
M0072-E-03 2004/09
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tCSS
CSN
VIH
CCLK VIL
VIH
CDTI VIL
VIH
VIL
C1 C0 R/W A4
tCCKL tCCKH
tCDS tCDH
WRITE Comma nd Input T iming
CSN
VIH
CCLK VIL
VIH
CDTI VIL
VIH
VIL
D3 D2 D1 D0
tCSW
tCSH
WRITE Data Input Timing
tPDW
VIL
PDN
Power- down & Reset Timing
ASAHI KASEI [AK 435 6]
M0072-E-03 2004/09
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OPERATION OVERVIEW
S yste m Clock I nput
The ext e rnal clo c k s which are re quired to op e rate the A K4 356 are MC LK , L RC K and BICK . The mas ter clock (M CL K)
should be synchronized with sampling clock (LR CK) but the phase is not critical. However, in Double and 4 times Speed
Modes, the ph ase relatio n sh ip between MCLK an d LRCK/BICK is lim ited. (Refer to Appendix A). MCLK is used to
operate the digital interpolation f ilter and the delta-sigma modulator. The frequency of MCLK can be set by CKS0-2, and
can be selected to normal, do uble o r 4 times speed mode by DFS0-1 (See Table 1). 4 times speed mode can be used for only
DAC1. If DAC1 is in 4 times speed mode, DAC2 and DAC3 are automatically powered down. When the states of SLOW,
DIF2-0, DFS1-0 or CKS2-0 chan ges, the AK4356 should be reset by PDN pin or RSTN bit.
All external clocks ( MCLK, BICK and LRCK) shou ld al ways be p resent whenever the AK43 56 is i n normal opera tion
mode (PD N = “H” ) . If these c locks are not provide d, the A K4 356 may draw exce s s c urrent and may not po ss ibly op e rate
properly because the device utilizes dynamic refreshed lo gic internally. If the external clo cks are not present, the AK4356
should be in the power-down mode (PDN = “L” or all DACs a re set in th e power-down mode by PW1-3 bits) or in the
reset mode (R STN = “0” ). Afte r e xiting reset at power-up etc., the AK4356 is in the po w e r-dow n mode until MCLK and
LRCK ar e in p ut .
DFS1-0
Mode
CKS2
CKS1
CKS0 “00”
(Nor m a l Speed ) “01”
( Doubl e Sp eed ) “10”
( 4 tim es Speed)
0 0 0 0 256fs 128fs N/A default (DFS1-0 = “00”)
1 0 0 1 256fs 256fs N/A
2 0 1 0 384fs 192fs N/A
3 0 1 1 384fs 384fs N/A
4 1 0 0 512fs 256fs 128fs
5 1 0 1 512fs N/A N/A
6 1 1 0 768fs 384fs 192fs
7 1 1 1 768fs N/A N/A
Table 1. System Clock (DFS1-0 = “11”: reserved)
fs [kHz] Mode 128fs 192fs 256fs 384fs 512fs 768fs
32
64
128
Normal
Double
4 times
-
8.1920
16.3840
-
12.2880
24.5760
8.1920
16.3840
-
12.2880
24.5760
-
16.3840
-
-
24.5760
-
-
44.1
88.2
176.4
Normal
Double
4 times
-
11.2896
22.5792
-
16.9344
33.8688
11.2896
22.5792
-
16.9344
33.8688
-
22.5792
-
-
33.8688
-
-
48
96
192
Normal
Double
4 times
-
12.2880
24.5760
-
18.4320
36.8640
12.2880
24.5760
-
18.4320
36.8640
-
24.5760
-
-
36.8640
-
-
Table 2. Example of System Clock [MHz]
ASAHI KASEI [AK 435 6]
M0072-E-03 2004/09
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A udio Serial Interface Format
Audio data is input to the AK4356 via the SDTI1-3 pins using BICK and LRCK inputs. 5 serial data formats are
supported and selected by DIF2-0 pins or DIF2-0 bits (See Table 3, compatible with the AK4324/4393). In all modes the
se rial da ta is M S B -first, 2’s c o mp liment format and is latc hed o n t he ris ing e dge o f B ICK . M o de 2 c a n b e u s e d f or 20 and
16 MSB justified formats by zer oing the un used LSBs.
Mode DIF2 DIF1 DIF0 SDTI L/R BICK Figure
0 0 0 0 16bit, LSB justified H/L ≥32fs Figure 1 default
1 0 0 1 20bit, LSB justified H/L ≥40fs Figure 2
2 0 1 0 24bit, MSB justified H/L ≥48fs Figure 3
3 0 1 1 I2S L/H ≥48fs Figure 4
4 1 0 0 24bit, LSB justified H/L ≥48fs Figure 2
Table 3. Audio data format
SDTI
BICK
LRCK
SDTI 15 14 6 5 4
BICK
0 1 10 11 12 13 14 15 0 1 10 11 12 13 14 15 0 1
3 2 1 0 15 14
(
32fs
)
(
64fs
)
014
115 16 17 31 0 1 14 15 16 17 31 0 1
15 14 0 15 14 0
Mo de 0 Don ’ t care Don’t care
15:MSB, 0:LSB
M ode 0 1514 6543210
Lch Data Rch Data
Figure 1. Mode 0 Timing
ASAHI KASEI [AK 435 6]
M0072-E-03 2004/09
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SDTI
LRCK
BICK
(
64fs
)
091 10 11 12 31 0 1 9 10 11 12 31 0 1
19 0 19 0
M ode 1 D on’t care Don’t care
19:MSB, 0:L SB
SDTI
Mode 4 23:MSB, 0:LSB
20 19 0 20 19 0Don ’ t care Don’t care22 21 22 21
Lch D ata Rch Data
8
23 23
8
Figure 2. Mode 1,4 Timin g
LRCK
BICK
(
64fs
)
SDTI
0221 2 24 31 0 1 31 0 1
23:MSB, 0:LSB
22 1 0 Don’t care23
Lch Data Rch Data
23 30 2222423 30
22 1 0Don’t care
23 2223
Figure 3. Mode 2 Timing
ASAHI KASEI [AK 435 6]
M0072-E-03 2004/09
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LRCK
BICK
(
64fs
)
SDTI
031 2 24 31 0 1 31 0 1
23:MSB, 0:LSB
22 10Don’t care
23
Lch Data Rch Data
23 25 322423 25
22 1 0 Do n’t care23
BICK
(
32fs
)
SDTI
031 2 12 15 0 1 0 1
23 22 138
11 14 2
12 11 10 9
13 3 12 1511 1413
23 22 13812 11 10 9238
23
Figure 4. Mode 3 Timing
Output Volume
The AK4356 includes channel independent digital output volumes (ATT) with 256 levels at 0.5dB steps including
MUTE. Th es e volumes are in fr on t of the DA C a nd can atten uate the in put data from 0dB to –127dB and mute. Wh en
changing levels, transitions are ex ecuted via soft changes; thus no switching noise occurs during these tr ansitions.
De-emphasis filte r
A digital de-emphasis filter is available for 32, 44.1 or 48kHz sampling rates (tc=50/15µs). It can be set for DAC1
(SDTI1), DAC2 (SD TI2) a nd DAC3 (SDTI3) independen tly. It is ena bled or disabled wit h th e con trol r egister data of
DEM1-0 and DFS1-0. The de-emphasis filter is disabled a t double or 4 times sampling mode (except for DFS0 = DFS1
= “0”).
DEM1 DEM0 De-emphasis
0 0 44.1kHz
0 1 OFF default
1 0 48kHz
1 1 32kHz
Table 4. De-emphasis filter con trol with DEM1-0 (DFS1-0 = “00”)
DFS1 DFS0 De-emphasis
0 0 See Table 4. default
0 1 OFF
1 0 OFF
1 1 OFF
Table 5. De-emphasis filter control with DFS1-0
ASAHI KASEI [AK 435 6]
M0072-E-03 2004/09
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Zero detection
The AK4356 has channel-indepen dent zeros detect function. Wh en the input data at each channel is continuously z ero
for 8192 LRCK cycles, DZF pin of ea ch channel goes to “H”. DZF pin of each chan nel immediately goes to “L” if in put
data of each channel is not zero after going DZF “H”. If RSTN bit is “0”, DZF pins of all channels go to “H”. DZF pins
of all channels go to “L” 4/f s af ter R STN bit returns to “1” . If DZ F M b it is set to “1”, DZF pins of all channels go to “H ”
only when the input data at all channels are continuously zeros for 8192 LRCK cycles. Zero detect function can be
disabled by DZFE bit. In this case, DZF pins of all cha n nels are always “L” (except for the case of RSTN = “0”).
S oft mute operation
So ft mute o p eration is p erformed at digital domain. When the SMUTE pin go es to “H ” , the o utput signal is attenuated b y
-∞ d uring 1024 L R C K cycles. When the SM UTE pin is returned to “L” , the mute is cance lled and the ou tput attenuation
gradually changes t o 0 dB during 1024 LRCK c ycle s . I f the s o ft mute i s c anc e lled within 10 24 LRCK cyc le s af ter starting
the operation, the attenuation is discontinued and returned to 0dB. The soft mute is effective for changin g the signal
source without stopping the signal transmission.
SMUTE
Attenuation
DZF
1024/fs
0dB
-∞
AOUT
1024/fs
8192/fs
GD GD
(1)
(2)
(3)
(4)
Notes:
(1) Th e out put signal is at tenuat ed by -∞ during 1024 LRCK cycles (1024/ fs).
(2) Analog output cor responding to digi tal input have the group delay (GD).
(3) If the soft mute is cancelled within 1024 LRCK cycl es, the attenuation is discon tinued and return ed to 0dB.
(4) When t he input data at e ach c hannel is c o ntinuou sly zero s for 8 192 LRCK c ycle s , D Z F pin o f e ach c hannel go e s to
“H”. DZF pin immediately goes to “L ” if i nput data are n ot zero after going DZF “H”.
Figure 5. Soft mut e and zero detection
System Reset
The AK4 356 s hou ld be res et o nce by b ringing PDN = “L” upo n po w e r-up. The AK43 56 is powe red up and the inte rnal
timing starts clocking by LRCK “↑” after exiting reset and power down state by MCLK. The AK4356 is in the
power-down mode until MCLK and LRCK are input .
ASAHI KASEI [AK 435 6]
M0072-E-03 2004/09
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Power-down
All DACs are p laced i n the power-down mode by bringing PDN pin “L” and each digital fil ter is also reset a t the same
time. The i nterna l register values are initializ ed by PDN “L”. This reset should always be done after power-up. Beca use
some click n oise occurs at th e edge of PDN, t he an a log output should be muted extern ally if the cl ick noi se influences
system application. Figure 6 shows th e power-down/up sequen ce.
Each DAC can be powered down by each power-down bit (PW1-3) “ 0”. In this case, the internal register values are not
initialized and the analog output is Hi-Z. Because some click noise occurs, the analo g output should be muted externally
if th e click noise influences system a p plication.
If DAC1 is in 4 times speed mode (DFS1=1, DFS0=0), DAC2 and DAC3 are automatica lly powered down. Both analog
out put s go to a n a l og com m on volta ge (A VDD/ 2).
N or ma l Op er ati o n
Internal
State
PDN
Power- do wn No rmal O pe ra tion
GD GD
“0” data
D/A Out
(Analog)
D/A In
(Digital)
Clock In
M CLK , LR CK, BI CK
(1) (3)
(6)
DZF
External
MUTE (5)
(3) (1)
Mute ON
(2)
(4)
Don’t car e
Notes:
(1) The analog output corresponding to digita l input h as the group delay (GD).
(2) A nalog outputs are fl oating (Hi -Z) at the power-down mode.
(3) Click noise occurs at the edge of PDN signal. This n oise is output even if “0” data is input.
(4) The external clocks (MCLK, BICK and LRCK) can be st opped in th e power-down mode (PDN = “L”).
(5) Please mute the analog output externally if the click noise (3) influences system application.
The timing example is shown in this figure.
(6 ) DZF pins of all channel s are “L” in the power-down mode (PDN = “L”).
Fi gur e 6. Power-down /u p sequence ex am pl e
ASAHI KASEI [AK 435 6]
M0072-E-03 2004/09
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Reset Function
When RS TN=0, all DA Cs are po w e red down but the internal re gister v alues are not initialized. The analog o utputs go to
VCOM voltage and DZF pins of all channels go to “H”. Figure 7 s hows the sequenc e of reset by RSTN bi t.
Internal
State
RST N bi t
Digital Block Power-down Normal Operation
GD GD
“0” data
D/A Out
(Analog)
D/A In
(Digital)
Clock In
MCLK,LRCK,BICK
(1) (3)
DZFL/DZFR
(3) (1)
(2)
Nor mal O p er ation
2/fs(5)
Internal
RST N bi t
2~3/fs (6)
Don’t care
(4)
Notes:
(1) The analog output corresponding to digita l input h as the group delay (GD).
(2) A nalog outputs go to VCOM voltage.
(3 ) Click noise occurs at the edges(“↑ ↓”) of the int ernal timing of RSTN bit. This noise is output even if “0” data
is input.
(4) The extern al cl ocks (MCLK, BICK and LRCK) can be stopped in the reset mode (RSTN = “L”).
(5 ) DZF pins go to “H” when the RSTN bit becomes “ 0”, and go t o “L” at 4~5/fs after RST N bit becomes “1”.
(6 ) There i s a delay, 2~3/fs from RSTN bit “1” to the i nterna l RSTN “1”.
Fi gur e 7. Reset sequen ce exa m pl e
ASAHI KASEI [AK 435 6]
M0072-E-03 2004/09
- 20 -
Seri al Control Interface
The AK4356 can control its fun ctions via both pins and registers. CKS2-0, DIF2-0, DFS0, DZFE and SMUTE pins are
ORed with t heir registers.
Internal registers may b e w ritten to the 3 wire uP interface pins: CSN, CCLK & CDTI. The data on this interface c onsists
of Chip address (2bits, CAD0/1), Read/Write (1bit), Register address (MSB first, 5bits) and Control data (MSB first,
8bits) . A ddress and data is clo c ked in on the rising ed ge o f CC LK . Data is latched af ter a low - to -high transit io n of C SN .
The clock speed of CC LK is 5MHz(ma x). The CSN pin should be held to “H” ex cept for access.
The ch ip address is deter min ed by th e sta te of th e CAD0 and CAD1 i nputs. PDN = “L” in itia l izes the registers to their
def ault values . Writing “0” to the RSTN bit c an initialize the internal timing circ uit. But in this case , the register data is
not be init ialized.
CDTI
CCLK
CSN
C1
012345678 9 10 11 12 13 14 15
D4D5D6D7
A
1
A
2
A3
A
4R/WC0
A
0D0D1D2D3
C1-C0: Chip Address (C1=CAD1, C0=CAD0)
R/W: Read/Write (Fi xed to “1” : Write only)
A4-A0: Register Address
D7-D0: Control Data
Figure 7. Control I/F Timing
Function Pin set-up Register set-up
Double Spe ed O O
4 tim es Speed X O
De-emphasis X O
DZFE O O
DZFM X O
SMUTE O O
Attenuator X O
Slow roll-off response X O
Table 6. Function Table (O: Sup ported, X: Not su pported)
Note: Wr iting to control register is inhibited when PDN = “L” or the MCLK is not fed .
ASAHI KASEI [AK 435 6]
M0072-E-03 2004/09
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Mappi ng of Program R egist ers
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
00H Control 1 0 SLOW DZFM DZFE DIF2 DIF1 DIF0 RSTN
01H Control 2 0 0 0 CKS2 CKS1 CKS0 SMUTE RSTN
02H Speed & Pow er Down Co ntro l 0 0 DFS1 DFS0 PW3 PW2 PW1 RSTN
03H De-emphasis Control 0 0 DEMC1 DEMC0 DEMB1 DEMB0 DEMA1 DEMA0
04H LOUT1 ATT Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
05H ROUT1 ATT Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
06H LOUT2 ATT Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
07H ROUT2 ATT Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
08H LOUT3 ATT Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
09H ROUT3 ATT Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
0AH Test Mode 0 0 0 TEST4 TEST3 TEST2 TEST1 TEST0
Note: For addresses fr om 0BH to 1FH, data is not wri tten.
When PDN goes to “L”, the registers are initialized to their default values.
When RST N bit goes to “0”, the inter n al timin g is reset , DZF pins of a ll cha n n els go to “H” but registers ar e not
initialized to thei r default values.
DZFE, DIF2-0, CKS2-0, SMUTE and DFS0 are ORed with pins.
ASAHI KASEI [AK 435 6]
M0072-E-03 2004/09
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Register Definitions
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
00H Control 1 0 SLOW DZFM DZFE DIF2 DIF1 DIF0 RSTN
Default 0 0 0 0 0 0 0 1
RSTN: Internal timing reset
0: Reset. DZF p ins of all channels go to “H” and registers ar e not initialized.
1: Normal operation
When the states of SLOW, DIF2-0, CKS2-0 or DFS0-1 changes, th e AK4356 should be reset
by PDN pin or RSTN bit. Some clic k noi se occurs at that timing.
D IF2-0: Audio dat a in terface modes (See T able 3.)
Initial: “000”, Mode 0
Register bit s of DIF2-0 are ORed with t he DFS2-0 p ins.
DZFE: Data Zero Detect Enable
0: Disable
1: Enable
Zero detect function can be d isabled by DZFE bit. In this case, the DZF pins of all channels
are a l ways “L”. Regist er bit of DZF E i s ORed wi t h the DZ FE pi n .
DZFM: Data Zero Detect Mode
0: Channel Separated Mode
1: Channel ANDed Mode
If the DZFM bit is set to “1”, the DZF pins of all channels go to “H” only when the input data
at all channels are continuously zeros for 8192 LRCK cycl es.
SL OW: Slow roll-off respons e enable
0: Disable
1: Enable
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
01H Control 2 0 0 0 CKS2 CKS1 CKS0 SMUTE RSTN
Default 0 0 0 0 0 0 0 1
RSTN: Internal timing reset
0: Reset. DZF p ins of all channels go to “H” and registers ar e not initialized.
1: Normal operation
When the states of SLOW, DIF2-0, CKS2-0 or DFS0-1 changes, th e AK4356 should be reset
by PDN pin or RSTN bit. Some click noise occurs at that timing.
SMUTE: Soft Mute Enable
0: Normal operation
1: All DAC outputs soft-muted
Register bit of SMUTE is ORed with the SMUTE pin.
C KS2-0 : M as ter Cl ock Fr eq u ency S elect (See Ta ble 2.)
Initial: “000”, Mode 0
Register bits of CKS2-0 are ORed with the CKS2-0 pi ns.
ASAHI KASEI [AK 435 6]
M0072-E-03 2004/09
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Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
02H Speed & Pow er Down Co ntro l 0 0 DFS1 DFS0 PW3 PW2 PW1 RSTN
Default 0 0 0 0 1 1 1 1
RSTN: Internal timing reset
0: Reset. DZF p ins of all channels go to “H” and registers ar e not initialized.
1: Normal operation
When the states of SLOW, DIF2-0, CKS2-0 or DFS0-1 changes, th e AK4356 should be reset
by PDN pin or RSTN bit. Some clic k noi se occurs at that timing.
PW3-1: Power-down control (0: Power-down, 1: Power-up)
PW1: Power down control of DAC1
PW2: Power down control of DAC2
PW3: Power down control of DAC3
All sections are powered-down by PW1=PW2=PW3=0.
D FS1 -0 : Sa m pl ing speed con trol (See Tabl e 1.)
00: Normal speed
01: Double speed
10: 4 times speed (DAC2 and DAC3 are automatically powered down.)
Register bit of DFS0 is ORed with the DFS0 pin.
When sampling s pee d mode i s changed between normal and double /4 times speed mode , DFS 1-0 bit
should be changed after changing MCLK frequency (figure below). Some click noise occurs at this
timing.
Sampling
speed
MCLK
normal 4 times
/double normal
Whe n s ampling sp eed mode is changed b etw ee n doub le and 4 times s peed mod e, sampling mode s hou ld
be changed to normal speed mode after ch anging MC LK frequency, and then it should be cha nged to
double/ 4 times speed mode (figure below). Som e click noise occurs at those changing timing.
Sampling
speed
MCLK
double/
4 times normal 4 times
/double
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
03H De-emphasis Control 0 0 DEMC1 DEMC0 DEMB1 DEMB0 DEMA1 DEMA0
Default 0 0 0 1 0 1 0 1
DEMA 1-0: De-emphasis response control for DAC1 data on S D TI1 (See T able 4,5.)
Initial: “01”, OFF
DEMB1-0: De -emphasis response control for DAC2 data on SD TI2 (S ee Table 4,5.)
Initial: “01”, OFF
DEMC1-0: De-emphasis response control for DAC3 data on SDTI3 (See T able 4,5.)
Initial: “01”, OFF
ASAHI KASEI [AK 435 6]
M0072-E-03 2004/09
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Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
04H LOUT1 ATT Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
05H ROUT1 ATT Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
06H LOUT2 ATT Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
07H ROUT2 ATT Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
08H LOUT3 ATT Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
09H ROUT3 ATT Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
Default 1 1 1 1 1 1 1 1
ATT7-0: Attenuation Level
256 levels, 0.5dB step
ATT7-0 Attenuation
FFH 0dB
FEH -0.5dB
FDH -1.0dB
: :
: :
02H -126.5dB
01H -127.0dB
00H MUTE (-∞)
The tra n sition between set val ues is soft tra n sition of 7425 levels. It takes 7424/fs (168ms@fs=44.1kHz) fr om
FFH(0dB) to 00H(MUTE).
If PDN p in g oes to “L”, the ATTs are in itialized to FFH.
The ATTs are FFH when RSTN = “0”. When RSTN return to “1 ”, the ATTs fade to their current value.
Digital atten uator is i ndependent of soft mute function.
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
0AH Test Mode 0 0 0 TEST4 TEST3 TEST2 TEST1 TEST0
Default 0 0 0 0 0 0 0 0
TEST4-0: Test mode
ASAHI KASEI [AK 435 6]
M0072-E-03 2004/09
- 25 -
SYSTEM DESIGN
Figure 8 shows the system connection diagram. An evaluation bo ard is available which demonstrates application circuits,
the optimum layout, power supply arrangements and measurement results.
Condition: Chip Address=”00”
DVSS
DVDD
12
SDTI1
11
13
SDTI214
SDTI315
LRCK
16
SMUTE17
CCLK18
CDTI19
CSN
20
DFS021
CKS022
MCLK 10
BICK
9
PDN 8
CAD1
7
CAD0 6
DZFL1
5
DZFR1
4
DZFL2
3
LOUT1+ 2
LOUT1
-
1
CKS123
CKS224
DIF0
25
DIF126
DIF227
DZFE
28
DZFR3
29
DZFL3
30
DZFR231
VREFH32
AVDD
33
44
43
42
41
40
39
38
37
36
35
34
ROUT1+
ROUT1-
LOUT2+
LOUT2-
ROUT2+
ROUT2-
LOUT3+
LOUT3-
ROUT3+
ROUT3-
A
VSS
AK4356
Top View
DIR
DSP
uP
+
Mode C ontr ol
R3ch
LPF
L3ch
LPF
R2ch
LPF
L2ch
LPF
R1ch
LPF
L1ch
LPF L 1ch MUTE L1ch
OUT
R1ch MUTE R1ch
OUT
L2ch MUTE L2ch
OUT
R2ch MUTE R2ch
OUT
L3ch MUTE L3ch
OUT
R3ch MUTE R3ch
OUT
+Analog 5V
Digital 5V
System Ground An alog Ground
Reset
10u 0.1u
0.1u 10u
Figure 8. Typical Connection Diagram
ASAHI KASEI [AK 435 6]
M0072-E-03 2004/09
- 26 -
Analog GroundD igital Ground
System
Controller
DVSS
DVDD
12
SDTI1
11
13
SDTI214
SDTI315
LRCK
16
SMUTE17
CCLK18
CDTI19
CSN
20
DFS021
CKS022
CKS123
44ROUT1+
AK4356
24
25
26
27
28
29
30
31
32
33
CKS2
DIF0
DIF1
DIF2
DZFE
DZFR3
DZFL3
DZFR2
VREFH
A
VDD
43ROUT1-
42LOUT2+
41LOUT2-
40ROUT2+
39ROUT2-
38LOUT3+
37LOUT3-
36ROUT3+
35ROUT3-
34
A
VSS
MCLK 10
BICK 9
PDN 8
CAD1 7
CAD0 6
DZFL1 5
DZFR1 4
DZFL2 3
LOUT1+ 2
LOUT1- 1
Figure 9. Ground Layout
Note: AVSS a nd DVSS must be connected to the same anal og ground p la ne.
1. Grounding and Power Supply Decoupling
The AK4356 requires careful attention to power supply and groundin g arr angements. AVDD and DVDD are usually
supp li ed fr om ana l og suppl y in system. Al ter nat ively if AVDD and DVDD ar e sup pl ied separ a t ely, th e power up
sequence is n ot cr i tical. AVSS and DVSS of the AK4356 must be connected to analog ground pl ane. System analog
groun d and digital gr ound should be connected together near to where the supplies are brought onto the printed circuit
bo ard. Decoupling capacito rs should be near to the AK4356 as po ssible, with the small value ceramic capacitors b eing the
nearest.
2. Voltage Reference Inputs
VREFH sets the analog output range. VREFH pin is normally connected to AVDD with a 0.1µF ceramic capacitor. All
signals, especially clocks, should be kept away from the VRE FH pin in ord er to avoid unwanted coupling into the
AK4356.
3. A nal og Outputs
The a na log output s are ful l-differential outputs an d 0.55 x VREF H Vp p (typ) centere d around the internal common
voltage (about AVDD/2). The differential outputs are summed externally , VAOUT= ( AOUT+) - (AOUT- ) between AOUT+
and AOUT-. If the summing gain is 1, the output range is 5.5Vpp (typ @VREFH=5V). The bi as voltage of the external
summing circuit is s u pplied e xte rnally. The input data format is 2 ’s c o mplement. The o utput vo ltage(VAOUT) is a positive
full scale for 7FFFFF(@24bit) an d a negative full sca le for 800000H(@24bit). The ideal VAOUT is 0V for
000000H(@24bit).
The internal switched-capacitor filter and external low pa ss filter attenuate the noise generated by the delta -sigma
modulator be yond the audi o passband.
DC offset on A OUT+/- is eliminated without AC coupling since the analog outputs a re differen tial. Figure 10 and 11
show the example of external op-amp circuit sum ming the differential outputs.
ASAHI KASEI [AK 435 6]
M0072-E-03 2004/09
- 27 -
4.7k 4.7k
R1
4.7k R1
4.7k 470p
Vop
470p
Vop
1k
1k47u
0.1u
BIAS
AOUT-
AOUT+
3300p
W hen R1=200Ω
W hen R1=180Ω
fc=93.2kHz, Q=0.712, g= -0. 1dB at 40kH z
fc=98.2kHz, Q=0.681, g= -0. 2dB at 40kH z
Analog
Out
Figure 10. External 2nd or der LPF Circuit Example (using op-amp with single power supply)
4.7k 4.7k
R1
4.7k R1
4.7k 470p
+Vop
470p
-Vop
AOUT-
AOUT+
3300p
W hen R1=200Ω
W hen R1=180Ω
fc=93.2kHz, Q=0.712, g= -0. 1dB at 40kHz
fc=98.2kHz, Q=0.681, g= -0. 2dB at 40kHz
Analog
Out
Figure 11. External 2nd ord er L P F Ci r cu i t E x a m p le (usi ng op- a m p wit h du a l power su pp lies)
ASAHI KASEI [AK 435 6]
M0072-E-03 2004/09
- 28 -
PACKAGE
0.15
0.17
±
0.05
0.37±0.10
10.00
1.70max
111
23
33
44
p
in LQ F P
(
Unit: mm
)
10.00
12.80±0.30
34
44
0.80
22
12
12.80±0.30
0∼0.2
0°
∼
10°
0.60
±
0.20
P ackage & Le ad frame material
Package molding compound: Epoxy
Lead frame material: Cu
Lead frame surface treatment: Solder plate
ASAHI KASEI [AK 435 6]
M0072-E-03 2004/09
- 29 -
MARKING
A
KM
A
K4356VQ
XXXXXX
X
JAPAN
1
1) Pi n #1 i ndication
2) Dat e Code: XXXX XXX(7 dig its)
3) Mar kin g Code: AK4356VQ
4) Count ry of Or i gin
5) Asa h i Kasei Logo
IM PORTANT NOTICE
• These products and thei r specif ications are subject to change w it hout noti ce. Before considering
any use or application, consul t the Asahi Kasei Microsystems Co., Ltd. (AKM) sales of f ice or
authorized dist ributor concerni ng their current status.
• AKM assumes no li abili ty f or inf ri ngement of any patent, intel lectual property, or other right i n the
appl ication or use of any inf ormation contai ned herein.
• A ny export o f these pro du cts, or de v ice s or s y ste ms con taining them, may req uire a n export licen se
or other off icial approval under the l aw and regulations of t he country of export pertaining to
cust oms and tarif fs, currenc y exchange, or strategi c materi al s.
• AKM products are neither intended nor authorized for use as cri tical components in any safety, life
support, or ot he r hazard related device or syst em, and AKM assumes no responsibili ty rel ati ng to
any such use, except wi th the express written consent of t he Representative Director of AKM. As
used here:
(a) A hazard related devi ce or system i s one designed or i ntended for li f e support or mai ntenance
of s afety o r for app lication s in medicine , aero spa ce , nuc le ar e ner gy, or oth er fields , in which its
failure to function or perform may reasonably be expected to result in loss of life or in significant
injury or damage to person or property.
(b) A critical compo ne nt is one whose failure to func tion or p erform may rea s o na bly be exp ected to
result, w hether directly or i ndi rectl y, in the loss of the saf ety or ef fecti veness of the device or
system c ontaining it, and which must therefore meet very hi gh standards of performance and
reli abili ty.
• It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or
otherwise places the product with a third party to notify that party in advance of the above content
and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability
for and hol d AKM harml ess f rom any and al l claims arising f rom the use of said product in the
absence of such noti fic ation.
ASAHI KASEI [AK 435 6]
M0072-E-03 2004/09
- 30 -
Appendix A
In D o uble and 4 times Speed Mo des, the phase relationship betwee n MCLK and LR CK/B ICK is limited (Table 7). If the
phase relationship happens during this prohibited period, it is poss ib le to o cc ur the inverse o f o u tput channel. The phase
relationship must be set to avoid the prohib ited period when the AK4356 operates at Double Speed Mode or 4 times Speed
Mode. T he pro hibit ed period i s s pe c ified by the c o mbinatio n of di gital power supply v o lt age ( DVDD), MCLK frequency
and audio data format (Table 3). When the audio data formats are 16/20/24b it LSB Justified (Mode 0,1,4) and 24bit MSB
Justified (Mode 2), the phase relati onship (tLRM: Figure 12) between the rising edge of LRCK and the rising edge of
MCL K has the prohibited pe rio d of min to max in Table 7. In case of I2S Compatible (Mode 3), the relationship be tw ee n
the falling edge of BICK and the rising edge of MCLK has the prohibited period (tBCM: Figure 13)
Mode Setting Prohibited Period
Sampling
Mode Digital Power
Supply, DVDD MCLK
Frequency CKS2 CKS1 CKS0 DFS1 DFS0 min max
Units
Double Speed 4.75 to 5.25V 128fs 0 0 0 0 1 0.1 0.6 ns
Double Speed 4.75 to 5.25V 192fs 0 1 0 0 1 -0.6 -0.1 ns
Double Speed 4.75 to 5.25V 256fs 0 0 1 0 1 -0.7 -0.2 ns
Double Speed 4.75 to 5.25V 256fs 1 0 0 0 1 -0.7 -0.2 ns
Double Speed 4.75 to 5.25V 384fs 0 1 1 0 1 -1.4 -0.9 ns
Double Speed 4.75 to 5.25V 384fs 1 1 0 0 1 -1.4 -0.9 ns
4 times Speed 4. 75 to 5.25V 128fs 1 0 0 1 0 -0.7 -0.2 ns
4 times Speed 4.75 to 5.25V 192fs 1 1 0 1 0 -1.4 -0 .9 ns
Table 7. Prohibited Period
tLRM
LRCK
MCLK
1.5V
1.5V
Figure 12. 16/20/24bit LSB Justi fied, 24bit MSB Justified
tBCM
BICK
MCLK
1.5V
1.5V
Figure 13. I2S Compatible
