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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

DS90LV048A

SNLS045C –JULY 1999–REVISED JULY 2016

DS90LV048A 3-V LVDS Quad CMOS Differential Line Receiver

1 Features

1• > 400-Mbps (200-MHz) Switching Rates

• Flow-Through Pinout Simplifies PCB Layout

• 150-ps Channel-to-Channel Skew (Typical)

• 100-ps Differential Skew (Typical)

• 2.7-ns Maximum Propagation Delay

• 3.3-V Power Supply Design

• High Impedance LVDS Inputs on Power Down

• Low Power Design (40 mW at 3.3-V Static)

• Interoperable With Existing 5-V LVDS Drivers

• Accepts Small Swing (350 mV Typical) Differential

Signal Levels

• Supports Input Failsafe

– Open, Short, and Terminated

• 0 V to −100 mV Threshold Region

• Conforms to ANSI/TIA/EIA-644 Standard

• Operating Temperature Range: –40°C to +85°C

• Available in SOIC and TSSOP Package

2 Applications

• Multifunction Printers

• LVDS - LVCMOS Translation

3 Description

The DS90LV048A device is a quad CMOS flow-

through differential line receiver designed for

applications requiring ultra-low power dissipation and

high data rates. The device is designed to support

data rates in excess of 400 Mbps (200 MHz) using

Low Voltage Differential Signaling (LVDS)

technology.

The DS90LV048A accepts low voltage (350 mV

typical) differential input signals and translates them

to 3-V CMOS output levels. The receiver supports a

TRI-STATE function that may be used to multiplex

outputs. The receiver also supports open, shorted,

and terminated (100-Ω) input fail-safe. The receiver

output is HIGH for all fail-safe conditions. The

DS90LV048A has a flow-through pinout for easy PCB

layout.

The EN and EN* inputs are ANDed together and

control the TRI-STATE outputs. The enables are

common to all four receivers. The DS90LV048A and

companion LVDS line driver (for example,

DS90LV047A) provide a new alternative to high-

power PECL/ECL devices for high-speed point-to-

point interface applications.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)

DS90LV048A SOIC (16) 9.90 mm × 3.91 mm

TSSOP (16) 5.00 mm × 4.40 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Functional Diagram

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Table of Contents

1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description............................................................. 1

4 Revision History..................................................... 2

5 Pin Configuration and Functions......................... 3

6 Specifications......................................................... 3

6.1 Absolute Maximum Ratings ...................................... 3

6.2 ESD Ratings.............................................................. 4

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 4

6.5 Electrical Characteristics........................................... 4

6.6 Switching Characteristics.......................................... 5

6.7 Typical Characteristics.............................................. 6

7 Parameter Measurement Information .................. 9

8 Detailed Description............................................ 10

8.1 Overview................................................................. 10

8.2 Functional Block Diagram....................................... 10

8.3 Feature Description................................................. 11

8.4 Device Functional Modes........................................ 11

9 Application and Implementation ........................ 12

9.1 Application Information............................................ 12

9.2 Typical Application ................................................. 12

10 Power Supply Recommendations ..................... 13

11 Layout................................................................... 13

11.1 Layout Guidelines ................................................. 13

11.2 Layout Example .................................................... 14

12 Device and Documentation Support................. 15

12.1 Documentation Support ........................................ 15

12.2 Receiving Notification of Documentation Updates 15

12.3 Community Resources.......................................... 15

12.4 Trademarks........................................................... 15

12.5 Electrostatic Discharge Caution............................ 15

12.6 Glossary................................................................ 15

13 Mechanical, Packaging, and Orderable

Information........................................................... 15

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision B (April 2013) to Revision C Page

• Added ESD Ratings table, Thermal Information table, Feature Description section, Device Functional Modes,

Application and Implementation section, Power Supply Recommendations section, Layout section, Device and

Documentation Support section, and Mechanical, Packaging, and Orderable Information section....................................... 1

Changes from Revision A (April 2013) to Revision B Page

• Changed layout of National Semiconductor Data Sheet to TI format .................................................................................... 8

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5 Pin Configuration and Functions

D or PW Package

16-Pin SOIC or TSSOP

Top View

Pin Functions

PIN I/O DESCRIPTION

NAME NO.

EN 16 I Receiver enable pin: When EN is low, the receiver is disabled. When EN is high and EN* is low

or open, the receiver is enabled. If both EN and EN* are open circuit, then the receiver is

disabled.

EN* 9 I Receiver enable pin: When EN* is high, the receiver is disabled. When EN* is low or open and

EN is high, the receiver is enabled. If both EN and EN* are open circuit, then the receiver is

disabled.

GND 12 — Ground pin

RIN+ 2, 3, 6, 7 I Noninverting receiver input pin

RIN−1, 4, 5, 8 I Inverting receiver input pin

ROUT 10, 11, 14,

15 OReceiver output pin

VCC 13 — Power supply pin, +3.3V ± 0.3V

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and

specifications.

6 Specifications

6.1 Absolute Maximum Ratings

See (1)(2)

MIN MAX UNIT

Supply voltage (VCC) –0.3 4 V

Input voltage (RIN+, RIN−) –0.3 3.6 V

Enable input voltage (EN, EN*) –0.3 VCC + 0.3 V

Output voltage (ROUT) –0.3 VCC + 0.3 V

Maximum package power dissipation

at +25°C

D0016A package 1025 mW

PW0016A package 866

Derate D0016A

package above +25°C 8.2 mW/°C

Derate PW0016A

package above +25°C 6.9

Lead temperature soldering (4 s) 260 °C

Maximum junction temperature 150 °C

Storage temperature, Tstg –65 150 °C

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(1) ESD Rating:

HBM (1.5 kΩ, 100 pF)

EIAJ (0 Ω, 200 pF)

6.2 ESD Ratings VALUE UNIT

V(ESD) Electrostatic discharge(1) Human-body model (HBM) ±10000 V

Machine model ±1200

6.3 Recommended Operating Conditions MIN NOM MAX UNIT

Supply voltage, VCC 3 3.3 3.6 V

Receiver input voltage GND 3 V

Operating free air temperature, TA−40 25 85 °C

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.4 Thermal Information

THERMAL METRIC(1) DS90LV048A

UNITPW (TSSOP)

16 PINS

RθJA Junction-to-ambient thermal resistance 110.2 °C/W

RθJC(top) Junction-to-case (top) thermal resistance 47 °C/W

RθJB Junction-to-board thermal resistance 54.7 °C/W

ψJT Junction-to-top characterization parameter 6.1 °C/W

ψJB Junction-to-board characterization parameter 54.2 °C/W

(1) Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground

unless otherwise specified.

(2) All typicals are given for: VCC = 3.3 V, TA= 25°C.

(3) VCC is always higher than RIN+ and RIN−voltage. RIN−and RIN+ are allowed to have a voltage range −0.2 V to VCC−VID/2. However, to

be compliant with AC specifications, the common voltage range is 0.1 V to 2.3 V.

(4) The VCMR range is reduced for larger VID. Example: if VID = 400 mV, the VCMR is 0.2 V to 2.2 V. The fail-safe condition with inputs

shorted is not supported over the common-mode range of 0 V to 2.4 V, but is supported only with inputs shorted and no external

common-mode voltage applied. A VID up to VCC – 0 V may be applied to the RIN+/ RIN−inputs with the Common-Mode voltage set to

VCC/2. Propagation delay and Differential Pulse skew decrease when VID is increased from 200 mV to 400 mV. Skew specifications

apply for 200 mV ≤VID ≤800 mV over the common-mode range.

(5) Output short-circuit current (IOS) is specified as magnitude only; minus sign indicates direction only. Only one output should be shorted

at a time; do not exceed maximum junction temperature specification.

6.5 Electrical Characteristics

Over Supply Voltage and Operating Temperature ranges, unless otherwise specified.(1)(2)

PARAMETER TEST CONDITIONS PIN MIN TYP MAX UNIT

VTH Differential input high threshold VCM = +1.2 V, 0.05 V, 2.95 V(3)

RIN+,

RIN−

−35 0 mV

VTL Differential input low threshold −100 −35 mV

VCMR Common-mode voltage range VID = 200 mV peak to peak?(4) 0.1 2.3 V

IIN Input current VIN = +2.8 V VCC = 3.6 V or 0 V −10 ±5 10

μAVIN = 0 V −10 ±1 10

VIN = +3.6 V VCC = 0 V –20 ±1 20

VOH Output high voltage IOH =−0.4 mA, VID = +200 mV

ROUT

2.7 3.3 VIOH =−0.4 mA, input terminated 2.7 3.3

IOH =−0.4 mA, input shorted 2.7 3.3

VOL Output low voltage IOL = 2 mA, VID =−200 mV 0.05 0.25 V

IOS Output short-circuit current Enabled, VOUT = 0 V(5) −15 −47 −100 mA

IOZ Output TRI-STATE current Disabled, VOUT = 0 V or VCC −10 ±1 10 μA

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Electrical Characteristics (continued)

Over Supply Voltage and Operating Temperature ranges, unless otherwise specified.(1)(2)

PARAMETER TEST CONDITIONS PIN MIN TYP MAX UNIT

VIH Input high voltage

EN,

EN*

2 VCC V

VIL Input low voltage GND 0.8 V

IIInput current VIN = 0 V or VCC, other Input = VCC or GND −10 ±5 10 μA

VCL Input clamp voltage ICL =−18 mA −1.5 −0.8 V

ICC No load supply current

receivers enabled EN = VCC, inputs open VCC

9 15 mA

ICCZ No load supply current

receivers disabled EN = GND, inputs open 1 5 mA

(1) All typicals are given for: VCC = 3.3 V, TA= 25°C.

(2) Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO= 50 Ω, trand tf(0% to 100%) ≤3 ns for RIN.

(3) tSKD2, channel-to-channel skew is defined as the difference between the propagation delay of one channel and that of the others on the

same chip with any event on the inputs.

(4) tSKD3, part-to-part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices

at the same VCC, and within 5°C of each other within the operating temperature range.

(5) tSKD1 is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of

the same channel

(6) tSKD4, part-to-part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices

over recommended operating temperature and voltage ranges, and across process distribution. tSKD4 is defined as |Max−Min| differential

propagation delay.

(7) fMAX generator input conditions: tr= tf< 1 ns (0% to 100%), 50% duty cycle, differential (1.05-V to 1.35-V peak to peak). Output criteria:

60 / 40% duty cycle, VOL (maximum 0.4 V), VOH (minimum 2.7 V), Load = 15 pF (stray plus probes).

6.6 Switching Characteristics

Over Supply Voltage and Operating Temperature ranges, unless otherwise specified.(1)(2)(3)(4)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

tPHLD Differential propagation delay high to low

CL= 15 pF

VID = 200 mV

(Figure 15 and Figure 16)

1.2 2 2.7 ns

tPLHD Differential propagation delay low to high 1.2 1.9 2.7 ns

tSKD1 Differential pulse skew |tPHLD −tPLHD|(5) 0 0.1 0.4 ns

tSKD2 Differential channel-to-channel skew; same

device(3) 0 0.15 0.5 ns

tSKD3 Differential part-to-part skew(4) 1 ns

tSKD4 Differential part-to-part skew(6) 1.5 ns

tTLH Rise time 0.5 1 ns

tTHL Fall time 0.35 1 ns

tPHZ Disable time high to Z RL= 2 kΩ

CL= 15 pF

(Figure 17 and Figure 18)

8 14 ns

tPLZ Disable time low to Z 8 14 ns

tPZH Enable time Z to high 9 14 ns

tPZL Enable time Z to low 9 14 ns

fMAX Maximum operating frequency(7) All channels switching 200 250 MHz

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6.7 Typical Characteristics

Figure 1. Output High Voltage vs Power Supply Voltage Figure 2. Output Low Voltage vs Power Supply Voltage

Figure 3. Output Short-Circuit Current vs Power Supply

Voltage Figure 4. Output TRI-STATE Current vs Power Supply

Voltage

Figure 5. Differential Transition Voltage vs Power Supply

Voltage Figure 6. Power Supply Current vs Ambient Temperature

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Typical Characteristics (continued)

Figure 7. Differential Propagation Delay vs Power Supply

Voltage Figure 8. Differential Propagation Delay vs Ambient

Temperature

Figure 9. Differential Propagation Delay vs Differential Input

Voltage Figure 10. Differential Propagation Delay vs Common-Mode

Voltage

Figure 11. Differential Skew vs Power Supply Voltage Figure 12. Differential Skew vs Ambient Temperature

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Typical Characteristics (continued)

Figure 13. Transition Time vs Power Supply Voltage Figure 14. Transition Time vs Ambient Temperature

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7 Parameter Measurement Information

Figure 15. Receiver Propagation Delay and Transition Time Test Circuit

Figure 16. Receiver Propagation Delay and Transition Time Waveforms

CLincludes load and test jig capacitance.

S1= VCC for tPZL and tPLZ measurements.

S1= GND for tPZH and tPHZ measurements.

Figure 17. Receiver TRI-STATE Delay Test Circuit

Figure 18. Receiver TRI-STATE Delay Waveforms

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8 Detailed Description

8.1 Overview

LVDS drivers and receivers are intended to be primarily used in an uncomplicated point-to-point configuration as

shown in Figure 19. This configuration provides a clean signaling environment for the fast edge rates of the

drivers. The receiver is connected to the driver through a balanced media which may be a standard twisted pair

cable, a parallel pair cable, or simply PCB traces. Typically, the characteristic impedance of the media is in the

range of 100 Ω. A termination resistor of 100 Ω(selected to match the media) is located as close to the receiver

input pins as possible. The termination resistor converts the driver output (current mode) into a voltage that is

detected by the receiver. Other configurations are possible such as a multi-receiver configuration, but the effects

of a mid-stream connector(s), cable stub(s), and other impedance discontinuities as well as ground shifting, noise

margin limits, and total termination loading must be considered.

The DS90LV048A differential line receiver is capable of detecting signals as low as 100 mV, over a ±1-V

common-mode range centered around +1.2 V. This is related to the driver offset voltage which is typically +1.2 V.

The driven signal is centered around this voltage and may shift ±1 V around this center point. The ±1-V shifting

may be the result of a ground potential difference between the ground reference of the driver and the ground

reference of the receiver, the common-mode effects of coupled noise, or a combination of the two. The AC

parameters of both receiver input pins are optimized for a recommended operating input voltage range of 0 V to

+2.4 V (measured from each pin to ground). The device operates for receiver input voltages up to VCC, but

exceeding VCC turns on the ESD protection circuitry, which clamps the bus voltages.

The DS90LV048A has a flow-through pinout that allows for easy PCB layout. The LVDS signals on one side of

the device easily allows for matching electrical lengths of the differential pair trace lines between the driver and

the receiver as well as allowing the trace lines to be close together to couple noise as common-mode. Noise

isolation is achieved with the LVDS signals on one side of the device and the TTL signals on the other side.

8.2 Functional Block Diagram

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8.3 Feature Description

8.3.1 Fail-Safe Feature

The LVDS receiver is a high-gain, high-speed device that amplifies a small differential signal (20 mV) to CMOS

logic levels. Due to the high gain and tight threshold of the receiver, take care to prevent noise from appearing as

a valid signal.

The internal fail-safe circuitry of the receiver is designed to source or sink a small amount of current, providing

fail-safe protection (a stable known state of HIGH output voltage) for floating, terminated or shorted receiver

inputs.

1. Open Input Pins. The DS90LV048A is a quad receiver device, and if an application requires only 1, 2, or 3

receivers, the unused channel(s) inputs must be left OPEN. Do not tie unused receiver inputs to ground or

any other voltages. The input is biased by internal high value pullup and pulldown resistors to set the output

to a HIGH state. This internal circuitry ensures a HIGH, stable output state for open inputs.

2. Terminated Input. If the driver is disconnected (cable unplugged), or if the driver is in a TRI-STATE or

power-off condition, the receiver output is again in a HIGH state, even with the end of cable 100-Ω

termination resistor across the input pins. The unplugged cable can become a floating antenna which can

pick up noise. If the cable picks up more than 10 mV of differential noise, the receiver may see the noise as

a valid signal and switch. To ensure that any noise is seen as common-mode and not differential, a balanced

interconnect should be used. Twisted pair cable offers better balance than flat ribbon cable.

3. Shorted Inputs. If a fault condition occurs that shorts the receiver inputs together, thus resulting in a 0-V

differential input voltage, the receiver output remains in a HIGH state. Shorted input fail-safe is not supported

across the common-mode range of the device (GND to 2.4 V). It is only supported with inputs shorted and no

external common-mode voltage applied.

External lower value pullup and pulldown resistors (for a stronger bias) may be used to boost fail-safe in the

presence of higher noise levels. The pullup and pulldown resistors must be in the 5-kΩto 15-kΩrange to

minimize loading and waveform distortion to the driver. The common-mode bias point must be set to

approximately 1.2 V (less than 1.75 V) to be compatible with the internal circuitry.

Additional information on fail-safe biasing of LVDS devices may be found in AN-1194 Failsafe Biasing of LVDS

Interfaces (SNLA051).

8.4 Device Functional Modes

Table 1 lists the functional modes of the DS90LV048A.

Table 1. Truth Table

ENABLES INPUT OUTPUT

EN EN* RIN+ −RIN−ROUT

H L or Open

VID ≥0 V H

VID ≤ −0.1 V L

Full Fail-safe

OPEN/SHORT or

Terminated H

All other combinations of ENABLE inputs X Z

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9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The DS90LV048A has a flow-through pinout that allows for easy PCB layout. The LVDS signals on one side of

the device easily allows for matching electrical lengths of the differential pair trace lines between the driver and

the receiver as well as allowing the trace lines to be close together to couple noise as common-mode. Noise

isolation is achieved with the LVDS signals on one side of the device and the TTL signals on the other side.

9.2 Typical Application

Figure 19. Balanced System Point-to-Point Application

9.2.1 Design Requirements

When using LVDS devices, it is important to remember to specify controlled impedance PCB traces, cable

assemblies, and connectors. All components of the transmission media must have a matched differential

impedance of about 100 Ω. They must not introduce major impedance discontinuities.

Balanced cables (for example, twisted pair) are usually better than unbalanced cables (ribbon cable) for noise

reduction and signal quality. Balanced cables tend to generate less EMI due to field canceling effects and also

tend to pick up electromagnetic radiation as common-mode (not differential mode) noise which is rejected by the

LVDS receiver.

For cable distances < 0.5 M, most cables can be made to work effectively. For distances 0.5 M ≤d≤10 M,

CAT5 (Category 5) twisted pair cable works well, is readily available, and relatively inexpensive.

9.2.2 Detailed Design Procedure

9.2.2.1 Probing LVDS Transmission Lines

Always use high impedance (> 100kΩ), low capacitance (< 2 pF) scope probes with a wide bandwidth (1 GHz)

scope. Improper probing gives deceiving results.

9.2.2.2 Threshold

The LVDS Standard (ANSI/TIA/EIA-644) specifies a maximum threshold of ±100 mV for the LVDS receiver. The

DS90LV048A supports an enhanced threshold region of −100 mV to 0 V. This is useful for fail-safe biasing. The

threshold region is shown in the Voltage Transfer Curve (VTC) in Figure 20. The typical DS90LV048A LVDS

receiver switches at about −35 mV.

NOTE

With VID = 0 V, the output is in a HIGH state. With an external fail-safe bias of +25 mV

applied, the typical differential noise margin is now the difference from the switch point to

the bias point.

In the following example, this would be 60 mV of Differential Noise Margin (+25 mV −(−35 mV)). With the

enhanced threshold region of −100 mV to 0 V, this small external fail-safe biasing of +25 mV (with respect to

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Typical Application (continued)

0 V) gives a DNM of a comfortable 60 mV. With the standard threshold region of ±100 mV, the external fail-safe

biasing would need to be +25 mV with respect to +100 mV or +125 mV, giving a DNM of 160 mV which is

stronger fail-safe biasing than is necessary for the DS90LV048A. If more DNM is required, then a stronger fail-

safe bias point can be set by changing resistor values.

Figure 20. VTC of the DS90LV048A LVDS Receiver

9.2.3 Application Curve

Figure 21. Power Supply Current vs Frequency

10 Power Supply Recommendations

Although the DS90LV047A draws very little power while at rest, its overall power consumption increases due to a

dynamic current component. The DS90LV048A power supply connection must take this additional current

consumption into consideration for maximum power requirements.

11 Layout

11.1 Layout Guidelines

• Use at least 4 PCB layers (top to bottom): LVDS signals, ground, power, and TTL signals.

• Isolate TTL signals from LVDS signals, otherwise the TTL may couple onto the LVDS lines. Best practice is to

put TTL and LVDS signals on different layers which are isolated by a power/ground plane(s).

• Keep drivers and receivers as close to the (LVDS port side) connectors as possible.

11.1.1 Power Decoupling Recommendations

Bypass capacitors must be used on power pins. Use high-frequency ceramic (surface mount is recommended)

0.1-μF and 0.001-μF capacitors in parallel at the power supply pin with the smallest value capacitor closest to the

device supply pin. Additional scattered capacitors over the printed-circuit board improves decoupling. Multiple

vias must be used to connect the decoupling capacitors to the power planes. A 10-μF (35-V) or greater solid

tantalum capacitor must be connected at the power entry point on the printed-circuit board between the supply

and ground.

Decoupling Cap

VCC

DIN2

DIN1

DIN3

DIN4

EN*

GND

DOUT4-

DOUT4+

DOUT3+

DOUT3-

DOUT2-

DOUT2+

DOUT1+

DOUT1-

DS90LV047A

ROUT2

ROUT1

ROUT3

ROUT4

EN*

GND

DS90LV048A

RIN4-

RIN4+

RIN3+

RIN3-

RIN2-

RIN2+

RIN1+

RIN1-

LVCMOS

Inputs

VCC Decoupling Cap

Series Termination (optional)

LVCMOS

Outputs

Input Termination

(Required)

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Layout Guidelines (continued)

11.1.2 Differential Traces

Use controlled impedance traces that match the differential impedance of your transmission medium (that is,

cable) and termination resistor. Run the differential pair trace lines as close together as possible as soon as they

leave the IC (stubs must be < 10 mm long). This helps eliminate reflections and ensure noise is coupled as

common-mode. In fact, we have seen that differential signals which are 1 mm apart radiate far less noise than

traces 3 mm apart because magnetic field cancellation is much better with the closer traces. In addition, noise

induced on the differential lines is much more likely to appear as common-mode which is rejected by the

receiver.

Match electrical lengths between traces to reduce skew. Skew between the signals of a pair means a phase

difference between signals, which destroys the magnetic field cancellation benefits of differential signals and

EMI, results. Remember the velocity of propagation, v = c/Er where c (the speed of light) = 0.2997 mm/ps or

0.0118 in/ps.

Do not rely solely on the autoroute function for differential traces. Carefully review dimensions to match

differential impedance and provide isolation for the differential lines. Minimize the number or vias and other

discontinuities on the line.

Avoid 90° turns (these cause impedance discontinuities). Use arcs or 45° bevels.

Within a pair of traces, the distance between the two traces should be minimized to maintain common-mode

rejection of the receivers. On the printed-circuit board, this distance must remain constant to avoid discontinuities

in differential impedance. Minor violations at connection points are allowable.

11.1.3 Termination

Use a termination resistor that best matches the differential impedance or your transmission line. The resistor

must be between 90 Ωand 130 Ω. Remember that the current mode outputs need the termination resistor to

generate the differential voltage. LVDS does not work without resistor termination. Typically, connecting a single

resistor across the pair at the receiver end will suffice.

Surface mount 1% to 2% resistors are best. PCB stubs, component lead, and the distance from the termination

to the receiver inputs must be minimized. The distance between the termination resistor and the receiver must be

< 10 mm (12 mm maximum).

11.2 Layout Example

Figure 22. Layout Recommendation

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12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

For related documentation, see the following:

•LVDS Owner's Manual (SNLA187)

•AN-808 Long Transmission Lines and Data Signal Quality (SNLA028)

•AN-977 LVDS Signal Quality: Jitter Measurements Using Eye Patterns Test Report #1SNLA166)

•AN-971 An Overview of LVDS Technology (SNLA165)

•AN-916 A Practical Guide to Cable Selection (SNLA219)

•AN-805 Calculating Power Dissipation for Differential Line Drivers (SNOA233)

•AN-903 A Comparison of Differential Termination Techniques (SNLA034)

•AN-1194 Failsafe Biasing of LVDS Interfaces (SNLA051)

12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

12.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

12.4 Trademarks

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

12.5 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

12.6 Glossary

SLYZ022 —TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OPTION ADDENDUM

www.ti.com 8-Feb-2016

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

DS90LV048ATM NRND SOIC D 16 48 TBD Call TI Call TI -40 to 85 DS90LV048A

DS90LV048ATM/NOPB ACTIVE SOIC D 16 48 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 DS90LV048A

DS90LV048ATMTC NRND TSSOP PW 16 92 TBD Call TI Call TI -40 to 85 DS90LV

048AT

DS90LV048ATMTC/NOPB ACTIVE TSSOP PW 16 92 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 DS90LV

048AT

DS90LV048ATMTCX NRND TSSOP PW 16 2500 TBD Call TI Call TI -40 to 85 DS90LV

048AT

DS90LV048ATMTCX/NOPB ACTIVE TSSOP PW 16 2500 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 DS90LV

048AT

DS90LV048ATMX/NOPB ACTIVE SOIC D 16 2500 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 DS90LV048A

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

PACKAGE OPTION ADDENDUM

www.ti.com 8-Feb-2016

Addendum-Page 2

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

DS90LV048ATMTCX TSSOP PW 16 2500 330.0 12.4 6.95 5.6 1.6 8.0 12.0 Q1

DS90LV048ATMTCX/NO

PB TSSOP PW 16 2500 330.0 12.4 6.95 5.6 1.6 8.0 12.0 Q1

DS90LV048ATMX/NOPB SOIC D 16 2500 330.0 16.4 6.5 10.3 2.3 8.0 16.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 8-Feb-2016

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

DS90LV048ATMTCX TSSOP PW 16 2500 367.0 367.0 35.0

DS90LV048ATMTCX/NOP

BTSSOP PW 16 2500 367.0 367.0 35.0

DS90LV048ATMX/NOPB SOIC D 16 2500 367.0 367.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 8-Feb-2016

Pack Materials-Page 2

IMPORTANT NOTICE

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Mouser Electronics

Authorized Distributor

Click to View Pricing, Inventory, Delivery & Lifecycle Information:

Texas Instruments:

DS90LV048ATM DS90LV048ATM/NOPB DS90LV048ATMTC DS90LV048ATMTC/NOPB DS90LV048ATMTCX

DS90LV048ATMTCX/NOPB DS90LV048ATMX/NOPB