SST39VF200A-70-4C-Y1QE - Silicon Storage Technology

S71117-10-000 08/07

The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.

MPF is a trademark of Silicon Storage Technology, Inc.

These specifications are subject to change without notice.

Data Sheet

FEATURES:

• Organized as 128K x16 / 256K x16 / 512K x16

• Single Voltage Read and Write Operations

– 3.0-3.6V for SST39LF200A/400A/800A

– 2.7-3.6V for SST39VF200A/400A/800A

• Superior Reliability

– Endurance: 100,000 Cycles (typical)

– Greater than 100 years Data Retention

• Low Power Consumption

(typical values at 14 MHz)

– Active Current: 9 mA (typical)

– Standby Current: 3 µA (typical)

• Sector-Erase Capability

– Uniform 2 KWord sectors

• Block-Erase Capability

– Uniform 32 KWord blocks

• Fast Read Access Time

– 45 and 55 ns for SST39LF200A

– 55 ns for SST39LF400A/800A

– 70 ns for SST39VF200A/400A/800A

• Latched Address and Data

• Fast Erase and Word-Program

– Sector-Erase Time: 18 ms (typical)

– Block-Erase Time: 18 ms (typical)

– Chip-Erase Time: 70 ms (typical)

– Word-Program Time: 14 µs (typical)

– Chip Rewrite Time:

2 seconds (typical) for SST39LF/VF200A

4 seconds (typical) for SST39LF/VF400A

8 seconds (typical) for SST39LF/VF800A

• Automatic Write Timing

– Internal VPP Generation

• End-of-Write Detection

– Toggle Bit

– Data# Polling

• CMOS I/O Compatibility

• JEDEC Standard

– Flash EEPROM Pinouts and command sets

• Packages Available

– 48-lead TSOP (12mm x 20mm)

– 48-ball TFBGA (6mm x 8mm)

– 48-ball WFBGA (4mm x 6mm)

– 48-bump XFLGA (4mm x 6mm) – 4 and 8Mbit

• All non-Pb (lead-free) devices are RoHS compliant

PRODUCT DESCRIPTION

The SST39LF200A/400A/800A and SST39VF200A/400A/

800A devices are 128K x16 / 256K x16 / 512K x16 CMOS

Multi-Purpose Flash (MPF) manufactured with SST propri-

etary, high-performance CMOS SuperFlash technology.

The split-gate cell design and thick oxide tunneling injector

attain better reliability and manufacturability compared with

alternate approaches. The SST39LF200A/400A/800A

write (Program or Erase) with a 3.0-3.6V power supply.

The SST39VF200A/400A/800A write (Program or Erase)

with a 2.7-3.6V power supply. These devices conform to

JEDEC standard pinouts for x16 memories.

Featuring high-performance Word-Program, the

SST39LF200A/400A/800A and SST39VF200A/400A/

800A devices provide a typical Word-Program time of 14

µsec. The devices use Toggle Bit or Data# Polling to detect

the completion of the Program or Erase operation. To pro-

tect against inadvertent write, they have on-chip hardware

and software data protection schemes. Designed, manu-

factured, and tested for a wide spectrum of applications,

these devices are offered with a guaranteed typical endur-

ance of 100,000 cycles. Data retention is rated at greater

than 100 years.

The SST39LF200A/400A/800A and SST39VF200A/400A/

800A devices are suited for applications that require con-

venient and economical updating of program, configura-

tion, or data memory. For all system applications, they

significantly improve performance and reliability, while low-

ering power consumption. They inherently use less energy

during Erase and Program than alternative flash technolo-

gies. When programming a flash device, the total energy

consumed is a function of the applied voltage, current, and

time of application. Since for any given voltage range, the

SuperFlash technology uses less current to program and

has a shorter erase time, the total energy consumed dur-

ing any Erase or Program operation is less than alternative

flash technologies. These devices also improve flexibility

while lowering the cost for program, data, and configura-

tion storage applications.

The SuperFlash technology provides fixed Erase and Pro-

gram times, independent of the number of Erase/Program

cycles that have occurred. Therefore the system software

or hardware does not have to be modified or de-rated as is

necessary with alternative flash technologies, whose

Erase and Program times increase with accumulated

Erase/Program cycles.

2 Mbit / 4 Mbit / 8 Mbit (x16) Multi-Purpose Flash

SST39LF200A / SST39LF400A / SST39LF800A

SST39VF200A / SST39VF400A / SST39VF800A

SST39LF/VF200A / 400A / 800A3.0 & 2.7V 2Mb / 4Mb / 8Mb (x16) MPF memories

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Data Sheet

2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash

SST39LF200A / SST39LF400A / SST39LF800A

SST39VF200A / SST39VF400A / SST39VF800A

To meet surface mount requirements, the SST39LF200A/

400A/800A and SST39VF200A/400A/800A are offered in

48-lead TSOP packages and 48-ball TFBGA packages as

well as Micro-Packages. See Figures 2, 3, and 4 for pin

assignments.

Device Operation

Commands are used to initiate the memory operation func-

tions of the device. Commands are written to the device

using standard microprocessor write sequences. A com-

mand is written by asserting WE# low while keeping CE#

low. The address bus is latched on the falling edge of WE#

or CE#, whichever occurs last. The data bus is latched on

the rising edge of WE# or CE#, whichever occurs first.

Read

The Read operation of the SST39LF200A/400A/800A and

SST39VF200A/400A/800A is controlled by CE# and OE#,

both have to be low for the system to obtain data from the

outputs. CE# is used for device selection. When CE# is

high, the chip is deselected and only standby power is con-

sumed. OE# is the output control and is used to gate data

from the output pins. The data bus is in high impedance

state when either CE# or OE# is high. Refer to the Read

cycle timing diagram for further details (Figure 5).

Word-Program Operation

The SST39LF200A/400A/800A and SST39VF200A/400A/

800A are programmed on a word-by-word basis. Before

programming, the sector where the word exists must be

fully erased. The Program operation is accomplished in

three steps. The first step is the three-byte load sequence

for Software Data Protection. The second step is to load

word address and word data. During the Word-Program

operation, the addresses are latched on the falling edge of

either CE# or WE#, whichever occurs last. The data is

latched on the rising edge of either CE# or WE#, whichever

occurs first. The third step is the internal Program operation

which is initiated after the rising edge of the fourth WE# or

CE#, whichever occurs first. The Program operation, once

initiated, will be completed within 20 µs. See Figures 6 and

7 for WE# and CE# controlled Program operation timing

diagrams and Figure 18 for flowcharts. During the Program

operation, the only valid reads are Data# Polling and Tog-

gle Bit. During the internal Program operation, the host is

free to perform additional tasks. Any commands issued

during the internal Program operation are ignored.

Sector/Block-Erase Operation

The Sector- (or Block-) Erase operation allows the system

to erase the device on a sector-by-sector (or block-by-

block) basis. The SST39LF200A/400A/800A and

SST39VF200A/400A/800A offers both Sector-Erase and

Block-Erase mode. The sector architecture is based on

uniform sector size of 2 KWord. The Block-Erase mode is

based on uniform block size of 32 KWord. The Sector-

Erase operation is initiated by executing a six-byte com-

mand sequence with Sector-Erase command (30H) and

sector address (SA) in the last bus cycle. The Block-Erase

operation is initiated by executing a six-byte command

sequence with Block-Erase command (50H) and block

address (BA) in the last bus cycle. The sector or block

address is latched on the falling edge of the sixth WE#

pulse, while the command (30H or 50H) is latched on the

rising edge of the sixth WE# pulse. The internal Erase

operation begins after the sixth WE# pulse. The End-of-

Erase operation can be determined using either Data#

Polling or Toggle Bit methods. See Figures 11 and 12 for

timing waveforms. Any commands issued during the Sec-

tor- or Block-Erase operation are ignored.

Chip-Erase Operation

The SST39LF200A/400A/800A and SST39VF200A/400A/

800A provide a Chip-Erase operation, which allows the

user to erase the entire memory array to the “1” state. This

is useful when the entire device must be quickly erased.

The Chip-Erase operation is initiated by executing a six-

byte command sequence with Chip-Erase command (10H)

at address 5555H in the last byte sequence. The Erase

operation begins with the rising edge of the sixth WE# or

CE#, whichever occurs first. During the Erase operation,

the only valid read is Toggle Bit or Data# Polling. See Table

4 for the command sequence, Figure 10 for timing diagram,

and Figure 21 for the flowchart. Any commands issued dur-

ing the Chip-Erase operation are ignored.

Write Operation Status Detection

The SST39LF200A/400A/800A and SST39VF200A/400A/

800A provide two software means to detect the completion

of a write (Program or Erase) cycle, in order to optimize the

system write cycle time. The software detection includes

two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6).

The End-of-Write detection mode is enabled after the rising

edge of WE#, which initiates the internal Program or Erase

operation.

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Data Sheet

2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash

SST39LF200A / SST39LF400A / SST39LF800A

SST39VF200A / SST39VF400A / SST39VF800A

The actual completion of the nonvolatile write is asynchro-

nous with the system; therefore, either a Data# Polling or

Toggle Bit read may be simultaneous with the completion

of the write cycle. If this occurs, the system may possibly

get an erroneous result, i.e., valid data may appear to con-

flict with either DQ7 or DQ6. In order to prevent spurious

rejection, if an erroneous result occurs, the software routine

should include a loop to read the accessed location an

additional two (2) times. If both reads are valid, then the

device has completed the write cycle, otherwise the rejec-

tion is valid.

Data# Polling (DQ7)

When the SST39LF200A/400A/800A and SST39VF200A/

400A/800A are in the internal Program operation, any

attempt to read DQ7 will produce the complement of the

true data. Once the Program operation is completed, DQ7

will produce true data. Note that even though DQ7 may

have valid data immediately following the completion of an

internal Write operation, the remaining data outputs may

still be invalid: valid data on the entire data bus will appear

in subsequent successive Read cycles after an interval of

1 µs. During internal Erase operation, any attempt to read

DQ7 will produce a ‘0’. Once the internal Erase operation

is completed, DQ7 will produce a ‘1’. The Data# Polling is

valid after the rising edge of fourth WE# (or CE#) pulse for

Program operation. For Sector-, Block- or Chip-Erase, the

Data# Polling is valid after the rising edge of sixth WE# (or

CE#) pulse. See Figure 8 for Data# Polling timing diagram

and Figure 19 for a flowchart.

Toggle Bit (DQ6)

During the internal Program or Erase operation, any con-

secutive attempts to read DQ6 will produce alternating 1s

and 0s, i.e., toggling between 1 and 0. When the internal

Program or Erase operation is completed, the DQ6 bit will

stop toggling. The device is then ready for the next opera-

tion. The Toggle Bit is valid after the rising edge of fourth

WE# (or CE#) pulse for Program operation. For Sector-,

Block- or Chip-Erase, the Toggle Bit is valid after the rising

edge of sixth WE# (or CE#) pulse. See Figure 9 for Toggle

Bit timing diagram and Figure 19 for a flowchart.

Data Protection

The SST39LF200A/400A/800A and SST39VF200A/400A/

800A provide both hardware and software features to pro-

tect nonvolatile data from inadvertent writes.

Hardware Data Protection

Noise/Glitch Protection: A WE# or CE# pulse of less than

5 ns will not initiate a write cycle.

VDD Power Up/Down Detection: The Write operation is

inhibited when VDD is less than 1.5V.

Write Inhibit Mode: Forcing OE# low, CE# high, or WE#

high will inhibit the Write operation. This prevents inadvert-

ent writes during power-up or power-down.

Software Data Protection (SDP)

The SST39LF200A/400A/800A and SST39VF200A/400A/

800A provide the JEDEC approved Software Data Protec-

tion scheme for all data alteration operations, i.e., Program

and Erase. Any Program operation requires the inclusion of

the three-byte sequence. The three-byte load sequence is

used to initiate the Program operation, providing optimal

protection from inadvertent Write operations, e.g., during

the system power-up or power-down. Any Erase operation

requires the inclusion of six-byte sequence. This group of

devices are shipped with the Software Data Protection per-

manently enabled. See Table 4 for the specific software

command codes. During SDP command sequence, invalid

commands will abort the device to Read mode within TRC.

The contents of DQ15-DQ8 can be VIL or VIH, but no other

value, during any SDP command sequence.

Common Flash Memory Interface (CFI)

The SST39LF200A/400A/800A and SST39VF200A/400A/

800A also contain the CFI information to describe the char-

acteristics of the device. In order to enter the CFI Query

mode, the system must write three-byte sequence, same

as Software ID Entry command with 98H (CFI Query com-

mand) to address 5555H in the last byte sequence. Once

the device enters the CFI Query mode, the system can

read CFI data at the addresses given in Tables 5 through 9.

The system must write the CFI Exit command to return to

Read mode from the CFI Query mode.

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Data Sheet

2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash

SST39LF200A / SST39LF400A / SST39LF800A

SST39VF200A / SST39VF400A / SST39VF800A

Product Identification

The Product Identification mode identifies the devices as

the SST39LF/VF200A, SST39LF/VF400A and SST39LF/

VF800A and manufacturer as SST. This mode may be

accessed by software operations. Users may use the

Software Product Identification operation to identify the part

(i.e., using the device ID) when using multiple

manufacturers in the same socket. For details, see Table 4

for software operation, Figure 13 for the Software ID Entry

and Read timing diagram, and Figure 20 for the Software

ID Entry command sequence flowchart.

Product Identification Mode Exit/

CFI Mode Exit

In order to return to the standard Read mode, the Software

Product Identification mode must be exited. Exit is accom-

plished by issuing the Software ID Exit command

sequence, which returns the device to the Read mode.

This command may also be used to reset the device to the

Read mode after any inadvertent transient condition that

apparently causes the device to behave abnormally, e.g.,

not read correctly. Please note that the Software ID Exit/

CFI Exit command is ignored during an internal Program or

Erase operation. See Table 4 for software command

codes, Figure 15 for timing waveform, and Figure 20 for a

flowchart.

FIGURE 1: Functional Block Diagram

TABLE 1: Product Identification

Address Data

Manufacturer’s ID 0000H 00BFH

Device ID

SST39LF/VF200A 0001H 2789H

SST39LF/VF400A 0001H 2780H

SST39LF/VF800A 0001H 2781H

T1.3 1117

Y-Decoder

I/O Buffers and Data Latches

1117 B1.2

Address Buffer & Latches

X-Decoder

DQ15 - DQ0

Memory Address

OE#

CE#

WE#

SuperFlash

Memory

Control Logic

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Data Sheet

2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash

SST39LF200A / SST39LF400A / SST39LF800A

SST39VF200A / SST39VF400A / SST39VF800A

FIGURE 2: Pin Assignments for 48-Lead TSOP

FIGURE 3: Pin Assignments for 48-Ball TFBGA

A15

A14

A13

A12

A11

A10

WE#

A16

VSS

DQ15

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

VDD

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

OE#

VSS

CE#

1117 48-tsop P01.2

Standard Pinout

Top View

Die Up

SST39LF/VF200A

A15

A14

A13

A12

A11

A10

WE#

A17

SST39LF/VF400A

A15

A14

A13

A12

A11

A10

WE#

A18

A17

SST39LF/VF800A SST39LF/VF200A

A16

VSS

DQ15

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

VDD

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

OE#

VSS

CE#

SST39LF/VF400A

A16

VSS

DQ15

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

VDD

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

OE#

VSS

CE#

SST39LF/VF800A

A13

WE#

A12

A14

A10

A15

A11

A16

DQ7

DQ5

DQ2

DQ0

DQ14

DQ12

DQ10

DQ8

CE#

DQ15

DQ13

VDD

DQ11

DQ9

OE#

VSS

DQ6

DQ4

DQ3

DQ1

VSS

1117 48-tfbga P02_2.0

SST39LF/VF200A

TOP VIEW (balls facing down)

A B C D E F G H

A13

WE#

A12

A17

A14

A10

A15

A11

A16

DQ7

DQ5

DQ2

DQ0

DQ14

DQ12

DQ10

DQ8

CE#

DQ15

DQ13

VDD

DQ11

DQ9

OE#

VSS

DQ6

DQ4

DQ3

DQ1

VSS

1117 48-tfbga P02_4.0

SST39LF/VF400A

TOP VIEW (balls facing down)

A B C D E F G H

A13

WE#

A12

A17

A14

A10

A18

A15

A11

A16

DQ7

DQ5

DQ2

DQ0

DQ14

DQ12

DQ10

DQ8

CE#

DQ15

DQ13

VDD

DQ11

DQ9

OE#

VSS

DQ6

DQ4

DQ3

DQ1

VSS

1117 48-tfb

a P02_8.0

SST39LF/VF800A

TOP VIEW (balls facing down)

A B C D E F G H

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Data Sheet

2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash

SST39LF200A / SST39LF400A / SST39LF800A

SST39VF200A / SST39VF400A / SST39VF800A

FIGURE 4: Pin Assignments for 48-Ball WFBGA and 48-Bump XFLGA

CE#

DQ8

OE#

DQ0

DQ10

DQ9

DQ1

A17

DQ2

DQ3

WE#

DQ12

DQ13

A10

DQ4

DQ5

DQ14

A11

A13

A12

DQ11

DQ6

DQ15

A14

A15

A16

DQ7

TOP VIEW (balls facing down)

A B C D E F G H J K L

1117 48-xflga P03_4.0

SST39LF/VF400A

CE#

DQ8

OE#

DQ0

A18

DQ10

DQ9

DQ1

A17

DQ2

DQ3

WE#

DQ12

DQ13

A10

DQ4

DQ5

DQ14

A11

A13

A12

DQ11

DQ6

DQ15

A14

A15

A16

DQ7

TOP VIEW (balls facing down)

A B C D E F G H J K L

1117 48-xflga P03_8.0

SST39LF/VF800A

CE#

DQ8

OE#

DQ0

DQ10

DQ9

DQ1

DQ2

DQ3

WE#

DQ12

DQ13

A10

DQ4

DQ5

DQ14

A11

A13

A12

DQ11

DQ6

DQ15

A14

A15

A16

DQ7

TOP VIEW (balls facing down)

A B C D E F G H J K L

1117 48-xflga P03_2.0

SST39VF200A

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Data Sheet

2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash

SST39LF200A / SST39LF400A / SST39LF800A

SST39VF200A / SST39VF400A / SST39VF800A

TABLE 2: Pin Description

Symbol Pin Name Functions

AMS1-A0Address Inputs To provide memory addresses. During Sector-Erase AMS-A11 address lines will select the

sector. During Block-Erase AMS-A15 address lines will select the block.

DQ15-DQ0Data Input/output To output data during Read cycles and receive input data during Write cycles.

Data is internally latched during a Write cycle.

The outputs are in tri-state when OE# or CE# is high.

CE# Chip Enable To activate the device when CE# is low.

OE# Output Enable To gate the data output buffers.

WE# Write Enable To control the Write operations.

VDD Power Supply To provide power supply voltage: 3.0-3.6V for SST39LF200A/400A/800A

2.7-3.6V for SST39VF200A/400A/800A

VSS Ground

NC No Connection Unconnected pins.

T2.2 1117

1. AMS = Most significant address

AMS = A16 for SST39LF/VF200A, A17 for SST39LF/VF400A, and A18 for SST39LF/VF800A

TABLE 3: Operation Modes Selection

Mode CE# OE# WE# DQ Address

Read VIL VIL VIH DOUT AIN

Program VIL VIH VIL DIN AIN

Erase VIL VIH VIL X1

1. X can be VIL or VIH, but no other value.

Sector or Block address,

XXH for Chip-Erase

Standby VIH X X High Z X

Write Inhibit X VIL X High Z/ DOUT X

XXV

IH High Z/ DOUT X

Product Identification

Software Mode VIL VIL VIH See Table 4

T3.4 1117

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Data Sheet

2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash

SST39LF200A / SST39LF400A / SST39LF800A

SST39VF200A / SST39VF400A / SST39VF800A

TABLE 4: Software Command Sequence

Command

Sequence

1st Bus

Write Cycle

2nd Bus

Write Cycle

3rd Bus

Write Cycle

4th Bus

Write Cycle

5th Bus

Write Cycle

6th Bus

Write Cycle

Addr1Data2Addr1Data2Addr1Data2Addr1Data2Addr1Data2Addr1Data2

Word-Program 5555H AAH 2AAAH 55H 5555H A0H WA3Data

Sector-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H SAX430H

Block-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H BAX450H

Chip-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H

Software ID Entry5,6 5555H AAH 2AAAH 55H 5555H 90H

CFI Query Entry55555H AAH 2AAAH 55H 5555H 98H

Software ID Exit7/

CFI Exit

XXH F0H

Software ID Exit7/

CFI Exit

5555H AAH 2AAAH 55H 5555H F0H

T4.3 1117

1. Address format A14-A0 (Hex), Addresses AMS-A15 can be VIL or VIH, but no other value, for the Command sequence.

AMS = Most significant address

AMS = A16 for SST39LF/VF200A, A17 for SST39LF/VF400A, and A18 for SST39LF/VF800A

2. DQ15-DQ8 can be VIL or VIH, but no other value, for the Command sequence

3. WA = Program word address

4. SAX for Sector-Erase; uses AMS-A11 address lines

BAX for Block-Erase; uses AMS-A15 address lines

5. The device does not remain in Software Product ID mode if powered down.

6. With AMS-A1 = 0; SST Manufacturer’s ID = 00BFH, is read with A0 = 0,

SST39LF/VF200A Device ID = 2789H, is read with A0 = 1.

SST39LF/VF400A Device ID = 2780H, is read with A0 = 1.

SST39LF/VF800A Device ID = 2781H, is read with A0 = 1.

7. Both Software ID Exit operations are equivalent

TABLE 5: CFI Query Identification String1 for SST39LF200A/400A/800A and SST39VF200A/400A/800A

1. Refer to CFI publication 100 for more details.

Address Data Data

10H 0051H Query Unique ASCII string “QRY”

11H 0052H

12H 0059H

13H 0001H Primary OEM command set

14H 0007H

15H 0000H Address for Primary Extended Table

16H 0000H

17H 0000H Alternate OEM command set (00H = none exists)

18H 0000H

19H 0000H Address for Alternate OEM extended Table (00H = none exits)

1AH 0000H

T5.0 1117

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Data Sheet

2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash

SST39LF200A / SST39LF400A / SST39LF800A

SST39VF200A / SST39VF400A / SST39VF800A

TABLE 6: System Interface Information for SST39LF200A/400A/800A and SST39VF200A/400A/800A

Address Data Data

1BH 0027H1VDD Min (Program/Erase)

0030H1DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts

1CH 0036H VDD Max (Program/Erase)

DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts

1DH 0000H VPP min (00H = no VPP pin)

1EH 0000H VPP max (00H = no VPP pin)

1FH 0004H Typical time out for Word-Program 2N µs (24 = 16 µs)

20H 0000H Typical time out for min size buffer program 2N µs (00H = not supported)

21H 0004H Typical time out for individual Sector/Block-Erase 2N ms (24 = 16 ms)

22H 0006H Typical time out for Chip-Erase 2N ms (26 = 64 ms)

23H 0001H Maximum time out for Word-Program 2N times typical (21 x 24 = 32 µs)

24H 0000H Maximum time out for buffer program 2N times typical

25H 0001H Maximum time out for individual Sector/Block-Erase 2N times typical (21 x 24 = 32 ms)

26H 0001H Maximum time out for Chip-Erase 2N times typical (21 x 26 = 128 ms)

T6.2 1117

1. 0030H for SST39LF200A/400A/800A and 0027H for SST39VF200A/400A/800A

TABLE 7: Device Geometry Information for SST39LF/VF200A

Address Data Data

27H 0012H Device size = 2N Byte (12H = 18; 218 = 256 KByte)

28H 0001H Flash Device Interface description; 0001H = x16-only asynchronous interface

29H 0000H

2AH 0000H Maximum number of bytes in multi-byte write = 2N (00H = not supported)

2BH

2CH 0002H Number of Erase Sector/Block sizes supported by device

2DH 003FH Sector Information (y + 1 = Number of sectors; z x 256B = sector size)

2EH 0000H y = 63 + 1 = 64 sectors (003FH = 63)

2FH 0010H

30H 0000H z = 16 x 256 Bytes = 4 KByte/sector (0010H = 16)

31H 0003H Block Information (y + 1 = Number of blocks; z x 256B = block size)

32H 0000H y = 3 + 1 = 4 blocks (0003H = 3)

33H 0000H

34H 0001H z = 256 x 256 Bytes = 64 KByte/block (0100H = 256)

T7.2 1117

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Data Sheet

2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash

SST39LF200A / SST39LF400A / SST39LF800A

SST39VF200A / SST39VF400A / SST39VF800A

TABLE 8: Device Geometry Information for SST39LF/VF400A

Address Data Data

27H 0013H Device size = 2N Byte (13H = 19; 219 = 512 KByte)

28H 0001H Flash Device Interface description; 0001H = x16-only asynchronous interface

29H 0000H

2AH 0000H Maximum number of bytes in multi-byte write = 2N (00H = not supported)

2BH 0000H

2CH 0002H Number of Erase Sector/Block sizes supported by device

2DH 007FH Sector Information (y + 1 = Number of sectors; z x 256B = sector size)

2EH 0000H y = 127 + 1 = 128 sectors (007FH = 127)

2FH 0010H

30H 0000H z = 16 x 256 Bytes = 4 KByte/sector (0010H = 16)

31H 0007H Block Information (y + 1 = Number of blocks; z x 256B = block size)

32H 0000H y = 7 + 1 = 8 blocks (0007H = 7)

33H 0000H

34H 0001H z = 256 x 256 Bytes = 64 KByte/block (0100H = 256)

T8.1 1117

TABLE 9: Device Geometry Information for SST39LF/VF800A

Address Data Data

27H 0014H Device size = 2N Bytes (14H = 20; 220 = 1 MByte)

28H 0001H Flash Device Interface description; 0001H = x16-only asynchronous interface

29H 0000H

2AH 0000H Maximum number of bytes in multi-byte write = 2N (00H = not supported)

2BH 0000H

2CH 0002H Number of Erase Sector/Block sizes supported by device

2DH 00FFH Sector Information (y + 1 = Number of sectors; z x 256B = sector size)

2EH 0000H y = 255 + 1 = 256 sectors (00FFH = 255)

2FH 0010H

30H 0000H z = 16 x 256 Bytes = 4 KByte/sector (0010H = 16)

31H 000FH Block Information (y + 1 = Number of blocks; z x 256B = block size)

32H 0000H y = 15 + 1 = 16 blocks (000FH = 15)

33H 0000H

34H 0001H z = 256 x 256 Bytes = 64 KByte/block (0100H = 256)

T9.0 1117

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Data Sheet

2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash

SST39LF200A / SST39LF400A / SST39LF800A

SST39VF200A / SST39VF400A / SST39VF800A

Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum

Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation

of the device at these conditions or conditions greater than those defined in the operational sections of this data

sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)

Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C

D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V

Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V

Voltage on A9 Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 13.2V

Package Power Dissipation Capability (TA = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W

Surface Mount Solder Reflow Temperature1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C for 10 seconds

Output Short Circuit Current2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

1. Excluding certain with-Pb 32-PLCC units, all packages are 260°C capable in both non-Pb and with-Pb solder versions.

Certain with-Pb 32-PLCC package types are capable of 240°C for 10 seconds; please consult the factory for the latest information.

2. Outputs shorted for no more than one second. No more than one output shorted at a time.

Operating Range: SST39LF200A/400A/800A

Range Ambient Temp VDD

Commercial 0°C to +70°C 3.0-3.6V

Operating Range: SST39VF200A/400A/800A

Range Ambient Temp VDD

Commercial 0°C to +70°C 2.7-3.6V

Industrial -40°C to +85°C 2.7-3.6V

AC Conditions of Test

Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns

Output Load . . . . . . . . . . . . . . . . . . . . CL = 30 pF for SST39LF200A/400A/800A

Output Load . . . . . . . . . . . . . . . . . . . . CL = 100 pF for SST39VF200A/400A/800A

See Figures 16 and 17

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Data Sheet

2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash

SST39LF200A / SST39LF400A / SST39LF800A

SST39VF200A / SST39VF400A / SST39VF800A

TABLE 10: DC Operating Characteristics

VDD = 3.0-3.6V for SST39LF200A/400A/800A and 2.7-3.6V for SST39VF200A/400A/800A1

Symbol Parameter

Limits

Test ConditionsMin Max Units

IDD Power Supply Current Address input=VILT/VIHT, at f=1/TRC Min,

VDD=VDD Max

Read230 mA CE#=VIL, OE#=WE#=VIH, all I/Os open

Program and Erase 30 mA CE#=WE#=VIL, OE#=VIH

ISB Standby VDD Current 20 µA CE#=VIHC, VDD=VDD Max

ILI Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max

ILO Output Leakage Current 10 µA VOUT=GND to VDD, VDD=VDD Max

VIL Input Low Voltage 0.8 VDD=VDD Min

VIH Input High Voltage 0.7VDD VV

DD=VDD Max

VIHC Input High Voltage (CMOS) VDD-0.3 V VDD=VDD Max

VOL Output Low Voltage 0.2 V IOL=100 µA, VDD=VDD Min

VOH Output High Voltage VDD-0.2 V IOH=-100 µA, VDD=VDD Min

T10.7 1117

1. Typical conditions for the Active Current shown on page 1 are average values at 25°C (room temperature),

and VDD = 3V for VF devices. Not 100% tested.

2. Values are for 70 ns conditions. See the Multi-Purpose Flash Power Rating application note for further information.

TABLE 11: Recommended System Power-up Timings

Symbol Parameter Minimum Units

TPU-READ1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Power-up to Read Operation 100 µs

TPU-WRITE1Power-up to Program/Erase Operation 100 µs

T11.0 1117

TABLE 12: Capacitance (TA = 25°C, f=1 Mhz, other pins open)

Parameter Description Test Condition Maximum

CI/O1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

I/O Pin Capacitance VI/O = 0V 12 pF

CIN1Input Capacitance VIN = 0V 6 pF

T12.0 1117

TABLE 13: Reliability Characteristics

Symbol Parameter Minimum Specification Units Test Method

NEND1,2

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

2. NEND endurance rating is qualified as a 10,000 cycle minimum for the whole device. A sector- or block-level rating would result in a

higher minimum specification.

Endurance 10,000 Cycles JEDEC Standard A117

TDR1Data Retention 100 Years JEDEC Standard A103

ILTH1Latch Up 100 + IDD mA JEDEC Standard 78

T13.2 1117

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Data Sheet

2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash

SST39LF200A / SST39LF400A / SST39LF800A

SST39VF200A / SST39VF400A / SST39VF800A

AC CHARACTERISTICS

TABLE 14: Read Cycle Timing Parameters VDD = 3.0-3.6V

Symbol Parameter

SST39LF200A-45 SST39LF200A/400A/800A-55

UnitsMinMaxMinMax

TRC Read Cycle Time 45 55 ns

TCE Chip Enable Access Time 45 55 ns

TAA Address Access Time 45 55 ns

TOE Output Enable Access Time 30 30 ns

TCLZ1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

CE# Low to Active Output 0 0 ns

TOLZ1OE# Low to Active Output 0 0 ns

TCHZ1CE# High to High-Z Output 15 15 ns

TOHZ1OE# High to High-Z Output 15 15 ns

TOH1Output Hold from Address Change 0 0 ns

T14.7 1117

TABLE 15: Read Cycle Timing Parameters VDD = 2.7-3.6V

Symbol Parameter

SST39VF200A/400A/800A-70

UnitsMin Max

TRC Read Cycle Time 70 ns

TCE Chip Enable Access Time 70 ns

TAA Address Access Time 70 ns

TOE Output Enable Access Time 35 ns

TCLZ1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

CE# Low to Active Output 0 ns

TOLZ1OE# Low to Active Output 0 ns

TCHZ1CE# High to High-Z Output 20 ns

TOHZ1OE# High to High-Z Output 20 ns

TOH1Output Hold from Address Change 0 ns

T15.7 1117

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Data Sheet

2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash

SST39LF200A / SST39LF400A / SST39LF800A

SST39VF200A / SST39VF400A / SST39VF800A

TABLE 16: Program/Erase Cycle Timing Parameters

Symbol Parameter Min Max Units

TBP Word-Program Time 20 µs

TAS Address Setup Time 0 ns

TAH Address Hold Time 30 ns

TCS WE# and CE# Setup Time 0 ns

TCH WE# and CE# Hold Time 0 ns

TOES OE# High Setup Time 0 ns

TOEH OE# High Hold Time 10 ns

TCP CE# Pulse Width 40 ns

TWP WE# Pulse Width 40 ns

TWPH1WE# Pulse Width High 30 ns

TCPH1CE# Pulse Width High 30 ns

TDS Data Setup Time 30 ns

TDH1Data Hold Time 0 ns

TIDA1Software ID Access and Exit Time 150 ns

TSE Sector-Erase 25 ms

TBE Block-Erase 25 ms

TSCE Chip-Erase 100 ms

T16.0 1117

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

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Data Sheet

2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash

SST39LF200A / SST39LF400A / SST39LF800A

SST39VF200A / SST39VF400A / SST39VF800A

FIGURE 5: Read Cycle Timing Diagram

FIGURE 6: WE# Controlled Program Cycle Timing Diagram

1117 F03.2

ADDRESS AMS-0

DQ15-0

WE#

OE#

CE#

TCE

TRC TAA

TOE

TOLZ

VIH

HIGH-Z

TCLZ TOH TCHZ

HIGH-Z

DATA VALIDDATA VALID

TOHZ

Note: AMS = Most significant address

MS = A16 for SST39LF/VF200A, A17 for SST39LF/VF400A and A18 for SST39LF/VF800A

1117 F04.4

ADDRESS AMS-0

DQ15-0

TDH

TWPH TDS

TWP

TAH

TAS

TCH

TCS

CE#

SW0 SW1 SW2

5555 2AAA 5555 ADDR

XXAA XX55 XXA0 DATA

INTERNAL PROGRAM OPERATION STARTS

WORD

(ADDR/DATA)

OE#

WE#

TBP

Note: AMS = Most significant address

MS = A16 for SST39LF/VF200A, A17 for SST39LF/VF400A and A18 for SST39LF/VF800A

X can be VIL or VIH, but no other value.

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Data Sheet

2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash

SST39LF200A / SST39LF400A / SST39LF800A

SST39VF200A / SST39VF400A / SST39VF800A

FIGURE 7: CE# Controlled Program Cycle Timing Diagram

FIGURE 8: Data# Polling Timing Diagram

1117 F05.4

ADDRESS AMS-0

DQ15-0

TDH

TCPH TDS

TCP

TAH

TAS

TCH

TCS

WE#

SW0 SW1 SW2

5555 2AAA 5555 ADDR

XXAA XX55 XXA0 DATA

INTERNAL PROGRAM OPERATION STARTS

WORD

(ADDR/DATA)

OE#

CE#

TBP

Note: AMS = Most significant address

MS = A16 for SST39LF/VF200A, A17 for SST39LF/VF400A and A18 for SST39LF/VF800A

X can be VIL or VIH, but no other value.

1117 F06.3

ADDRESS AMS-0

DQ7DATA DATA# DATA# DATA

WE#

OE#

CE#

TOEH

TOE

TCE

TOES

Note: AMS = Most significant address

MS = A16 for SST39LF/VF200A, A17 for SST39LF/VF400A and A18 for SST39LF/VF800A

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Data Sheet

2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash

SST39LF200A / SST39LF400A / SST39LF800A

SST39VF200A / SST39VF400A / SST39VF800A

FIGURE 9: Toggle Bit Timing Diagram

FIGURE 10: WE# Controlled Chip-Erase Timing Diagram

1117 F07.3

ADDRESS AMS-0

DQ6

WE#

OE#

CE#

TOE

TOEH

TCE

TOES

TWO READ CYCLES

WITH SAME OUTPUTS

Note: AMS = Most significant address

MS = A16 for SST39LF/VF200A, A17 for SST39LF/VF400A and A18 for SST39LF/VF800A

1117 F08.7

ADDRESS AMS-0

DQ15-0

WE#

SW0 SW1 SW2 SW3 SW4 SW5

5555 2AAA 2AAA5555 5555

XX55 XX10XX55XXAA XX80 XXAA

5555

OE#

CE#

SIX-BYTE CODE FOR CHIP-ERASE

TSCE

TWP

Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are

interchageable as long as minimum timings are met. (See Table 16)

AMS = Most significant address

MS = A16 for SST39LF/VF200A, A17 for SST39LF/VF400A and A18 for SST39LF/VF800A

X can be VIL or VIH, but no other value.

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Data Sheet

2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash

SST39LF200A / SST39LF400A / SST39LF800A

SST39VF200A / SST39VF400A / SST39VF800A

FIGURE 11: WE# Controlled Block-Erase Timing Diagram

FIGURE 12: WE# Controlled Sector-Erase Timing Diagram

1117 F17.9

ADDRESS AMS-0

DQ15-0

WE#

SW0 SW1 SW2 SW3 SW4 SW5

5555 2AAA 2AAA5555 5555

XX55 XX50XX55XXAA XX80 XXAA

BAX

OE#

CE#

SIX-BYTE CODE FOR BLOCK-ERASE

TBE

TWP

Note: This device also supports CE# controlled Block-Erase operation. The WE# and CE# signals are

interchageable as long as minimum timings are met. (See Table 16)

BAX = Block Address

MS = Most significant address

MS = A16 for SST39LF/VF200A, A17 for SST39LF/VF400A and A18 for SST39LF/VF800A

X can be VIL or VIH, but no other value.

1117 F18.8

ADDRESS AMS-0

DQ15-0

WE#

SW0 SW1 SW2 SW3 SW4 SW5

5555 2AAA 2AAA5555 5555

XX55 XX30XX55XXAA XX80 XXAA

SAX

OE#

CE#

SIX-BYTE CODE FOR SECTOR-ERASE

TSE

TWP

Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are

interchageable as long as minimum timings are met. (See Table 16)

SAX = Sector Address

MS = Most significant address

MS = A16 for SST39LF/VF200A, A17 for SST39LF/VF400A and A18 for SST39LF/VF800A

X can be VIL or VIH, but no other value.

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Data Sheet

2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash

SST39LF200A / SST39LF400A / SST39LF800A

SST39VF200A / SST39VF400A / SST39VF800A

FIGURE 13: Software ID Entry and Read

FIGURE 14: CFI Query Entry and Read

1117 F09.4

ADDRESS A14-0

TIDA

DQ15-0

WE#

SW0 SW1 SW2

5555 2AAA 5555 0000 0001

OE#

CE#

THREE-BYTE SEQUENCE FOR

SOFTWARE ID ENTRY

TWP

TWPH TAA

00BF

Device ID

XX55XXAA XX90

Device ID = 2789H for SST39LF/VF200A, 2780H for SST39LF/VF400A and 2781H for SST39LF/VF800A

Note: X can be VIL or VIH, but no other value.

1117 F20.1

ADDRESS A14-0

TIDA

DQ15-0

WE#

SW0 SW1 SW2

5555 2AAA 5555

OE#

CE#

THREE-BYTE SEQUENCE FOR

CFI QUERY ENTRY

TWP

TWPH TAA

XX55XXAA XX98

Note: X can be V

or V

, but no other value.

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Data Sheet

2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash

SST39LF200A / SST39LF400A / SST39LF800A

SST39VF200A / SST39VF400A / SST39VF800A

FIGURE 15: Software ID Exit/CFI Exit

1117 F10.1

ADDRESS A14-0

DQ15-0

TIDA

TWP

TWHP

WE#

SW0 SW1 SW2

5555 2AAA 5555

THREE-BYTE SEQUENCE FOR

SOFTWARE ID EXIT AND RESET

OE#

CE#

XXAA XX55 XXF0

Note: X can be VIL or VIH, but no other value.

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Data Sheet

2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash

SST39LF200A / SST39LF400A / SST39LF800A

SST39VF200A / SST39VF400A / SST39VF800A

FIGURE 16: AC Input/Output Reference Waveforms

FIGURE 17: A Test Load Example

1117 F11.1

REFERENCE POINTS OUTPUTINPUT VIT

VIHT

VILT

VOT

AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference points

for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% ↔ 90%) are <5 ns.

Note: VIT - VINPUT Te s t

VOT - VOUTPUT Tes t

VIHT - VINPUT HIGH Test

VILT - VINPUT LOW Test

1117 F12.1

TO TESTER

TO DUT

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Data Sheet

2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash

SST39LF200A / SST39LF400A / SST39LF800A

SST39VF200A / SST39VF400A / SST39VF800A

FIGURE 18: Word-Program Algorithm

1117 F13.4

Start

Load data: XXAAH

Address: 5555H

Load data: XX55H

Address: 2AAAH

Load data: XXA0H

Address: 5555H

Load Word

Address/Word

Data

Wait for end of

Program (TBP,

Data# Polling

bit, or Toggle bit

operation)

Program

Completed

Note: X can be VIL or VIH, but no other value.

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Data Sheet

2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash

SST39LF200A / SST39LF400A / SST39LF800A

SST39VF200A / SST39VF400A / SST39VF800A

FIGURE 19: Wait Options

1117 F14.0

Wait TBP,

TSCE, TSE

or TBE

Program/Erase

Initiated

Internal Timer Toggle Bit

Ye s

Program/Erase

Completed

Does DQ6

match?

Read same

word

Data# Polling

Program/Erase

Completed

Program/Erase

Completed

Read word

Is DQ7 =

true data?

Read DQ7

Program/Erase

Initiated

Program/Erase

Initiated

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Data Sheet

2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash

SST39LF200A / SST39LF400A / SST39LF800A

SST39VF200A / SST39VF400A / SST39VF800A

FIGURE 20: Software ID/CFI Command Flowcharts

1117 F15.4

Load data: XXAAH

Address: 5555H

Software ID Entry

Command Sequence

Load data: XX55H

Address: 2AAAH

Load data: XX90H

Address: 5555H

Wait TIDA

Read Software ID

Load data: XXAAH

Address: 5555H

CFI Query Entry

Command Sequence

Load data: XX55H

Address: 2AAAH

Load data: XX98H

Address: 5555H

Wait TIDA

Read CFI data

Load data: XXAAH

Address: 5555H

Software ID Exit/CFI Exit

Command Sequence

Load data: XX55H

Address: 2AAAH

Load data: XXF0H

Address: 5555H

Load data: XXF0H

Address: XXH

Return to normal

operation

Wait TIDA

Return to normal

operation

Note: X can be VIL or VIH, but no other value.

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Data Sheet

2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash

SST39LF200A / SST39LF400A / SST39LF800A

SST39VF200A / SST39VF400A / SST39VF800A

FIGURE 21: Erase Command Sequence

1117 F16.5

Load data: XXAAH

Address: 5555H

Chip-Erase

Command Sequence

Load data: XX55H

Address: 2AAAH

Load data: XX80H

Address: 5555H

Load data: XX55H

Address: 2AAAH

Load data: XX10H

Address: 5555H

Load data: XXAAH

Address: 5555H

Wait TSCE

Chip erased

to FFFFH

Load data: XXAAH

Address: 5555H

Sector-Erase

Command Sequence

Load data: XX55H

Address: 2AAAH

Load data: XX80H

Address: 5555H

Load data: XX55H

Address: 2AAAH

Load data: XX30H

Address: SAX

Load data: XXAAH

Address: 5555H

Wait TSE

Sector erased

to FFFFH

Load data: XXAAH

Address: 5555H

Block-Erase

Command Sequence

Load data: XX55H

Address: 2AAAH

Load data: XX80H

Address: 5555H

Load data: XX55H

Address: 2AAAH

Load data: XX50H

Address: BAX

Load data: XXAAH

Address: 5555H

Wait TBE

Block erased

to FFFFH

Note: X can be VIL or VIH, but no other value.

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Data Sheet

2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash

SST39LF200A / SST39LF400A / SST39LF800A

SST39VF200A / SST39VF400A / SST39VF800A

PRODUCT ORDERING INFORMATION

Environmental Attribute

E1 = non-Pb

Package Modifier

K = 48 leads or balls

Q = 48 balls or bumps (66 possible positions)

Package Type

B3 = TFBGA (0.8mm pitch, 6mm x 8mm)

C1 = XFLGA (0.5mm pitch, 4mm x 6mm)

E = TSOP (type 1, die up, 12mm x 20mm)

M1 = WFBGA (0.5mm pitch, 4mm x 6mm)

Y1 = WFBGA (panel-based, 0.5mm pitch,

4mm x 6mm)”

Temperature Range

C = Commercial = 0°C to +70°C

I = Industrial = -40°C to +85°C

Minimum Endurance

4 = 10,000 cycles

Read Access Speed

45 = 45 ns

55 = 55 ns

70 = 70 ns

Version

A = Special Feature Version

Device Density

800 = 8 Mbit

400 = 4 Mbit

200 = 2 Mbit

Voltag e

L = 3.0-3.6V

V = 2.7-3.6V

Product Series

39 = Multi-Purpose Flash

1. Environmental suffix “E” denotes non-Pb solder.

SST non-Pb solder devices are “RoHS Compliant”.

SST 39 VF 200A - 70 - 4C - B3K E

XX XX XXXX - XXX -XX-XXX X

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Data Sheet

2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash

SST39LF200A / SST39LF400A / SST39LF800A

SST39VF200A / SST39VF400A / SST39VF800A

Valid combinations for SST39LF200A

SST39LF200A-45-4C-EKE SST39LF200A-45-4C-B3KE

SST39LF200A-55-4C-EKE SST39LF200A-55-4C-B3KE

Valid combinations for SST39VF200A

SST39VF200A-70-4C-EKE SST39VF200A-70-4C-B3KE SST39VF200A-70-4C-M1QE SST39VF200A-70-4C-Y1QE

SST39VF200A-70-4I-EKE SST39VF200A-70-4I-B3KE SST39VF200A-70-4I-M1QE SST39VF200A-70-4I-Y1QE

Valid combinations for SST39LF400A

SST39LF400A-55-4C-EKE SST39LF400A-55-4C-B3KE

Valid combinations for SST39VF400A

SST39VF400A-70-4C-EKE SST39VF400A-70-4C-B3KE SST39VF400A-70-4C-C1QE SST39VF400A-70-4C-M1QE

SST39VF400A-70-4I-EKE SST39VF400A-70-4I-B3KE SST39VF400A-70-4I-C1QE SST39VF400A-70-4I-M1QE

Valid combinations for SST39LF800A

SST39LF800A-55-4C-EKE SST39LF800A-55-4C-B3KE

Valid combinations for SST39VF800A

SST39VF800A-70-4C-EKE SST39VF800A-70-4C-B3KE SST39VF800A-70-4C-C1QE SST39VF800A-70-4C-M1QE

SST39VF800A-70-4C-Y1QE

SST39VF800A-70-4I-EKE SST39VF800A-70-4I-B3KE SST39VF800A-70-4I-C1QE SST39VF800A-70-4I-M1QE

SST39VF800A-70-4I-Y1QE

Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales

representative to confirm availability of valid combinations and to determine availability of new combinations.

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Data Sheet

2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash

SST39LF200A / SST39LF400A / SST39LF800A

SST39VF200A / SST39VF400A / SST39VF800A

PACKAGING DIAGRAMS

FIGURE 22: 48-Lead Thin Small Outline Package (TSOP) 12mm x 20mm

SST Package Code: EK

1.05

0.95

0.70

0.50

18.50

18.30

20.20

19.80

0.70

0.50

12.20

11.80

0.27

0.17

0.15

0.05

48-tsop-EK-8

Note: 1. Complies with JEDEC publication 95 MO-142 DD dimensions,

although some dimensions may be more stringent.

2. All linear dimensions are in millimeters (max/min).

3. Coplanarity: 0.1 mm

4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads.

1.20

max.

1mm

0°- 5°

DETAIL

Pin # 1 Identifier

0.50

BSC

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Data Sheet

2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash

SST39LF200A / SST39LF400A / SST39LF800A

SST39VF200A / SST39VF400A / SST39VF800A

FIGURE 23: 48-Ball Thin-Profile, Fine-pitch Ball Grid Array (TFBGA) 6mm x 8mm

SST Package Code: B3K

FIGURE 24: 48-Ball Very-Very-Thin-Profile, Fine-Pitch Ball Grid Array (WFBGA) 4mm x 6mm

SST Package Code: M1Q

A1 CORNER

H G F E D C B A

A B C D E F G H

BOTTOM VIEWTOP VIEW

SIDE VIEW

SEATING PLANE

0.35 ± 0.05

1.10 ± 0.10

0.12

6.00 ± 0.20

0.45 ± 0.05

(48X)

A1 CORNER

8.00 ± 0.20

0.80

4.00

0.80

5.60

48-tfbga-B3K-6x8-450mic-4

Note: 1. Complies with JEDEC Publication 95, MO-210, variant 'AB-1', although some dimensions may be more stringent.

2. All linear dimensions are in millimeters.

3. Coplanarity: 0.12 mm

4. Ball opening size is 0.38 mm (± 0.05 mm)

1mm

L K J H G F E D C B A

ABCDEFGHJKL

0.50

BOTTOM VIEW

4.00

±0.08

0.32

±0.05

(48X)

A1 INDICATOR4

6.00

±0.08

2.50

5.00

A1 CORNER

TOP VIEW

48-wfbga-M1Q-4x6-32mic-6.0

Note: 1. Complies with JEDEC Publication 95, MO-207, Variant C2B-4, dimensions except nominal ball width is larger.

2. All linear dimensions are in millimeters.

3. Coplanarity: 0.08 mm.

4. No ball is present in position A1; a gold-colored indicator is present.

5. Ball opening size is 0.29 mm (± 0.05 mm).

1mm

DETAIL SIDE VIEW

SEATING PLANE

0.20

0.63 ± 0.10

0.08

±0.06

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Data Sheet

2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash

SST39LF200A / SST39LF400A / SST39LF800A

SST39VF200A / SST39VF400A / SST39VF800A

FIGURE 25: 48-Bump Extremely-Thin-Profile, Fine-Pitch Land Grid Array (XFLGA) 4mm x 6mm

SST Package Code: C1Q

FIGURE 26: 48-Ball Very-Very-Thin-Profile, Fine-Pitch Ball Grid Array (WFBGA) 4mm x 6mm (Panel-based)

SST Package Code: Y1Q

L K J H G F E D C B A

ABCDEFGHJKL

0.50

BOTTOM VIEW

4.00

±0.08

0.29

±0.05

(48X)

A1 INDICATOR

6.00

±0.08

2.50

5.00

A1 CORNER

TOP VIEW

48-xflga-C1Q-4x6-29mic-6.0

Note: 1. Complies with JEDEC Publication 95, MO-207, variant CZB-4, dimensions except bump height is much less.

2. All linear dimensions are in millimeters.

3. Coplanarity: 0.05 mm.

4. No ball is present at A1; a gold-colored indicator is present.

5. Bump opening size is 0.29 (±0.05 mm).

1mm

DETAIL SIDE VIEW

SEATING PLANE

0.04

0.52 max.

0.473 nom.

0.05

+0.025/-0.015

L K J H G F E D C B A

ABCDEFGHJKL

0.50

BOTTOM VIEW

0.32

±0.05

(48X)

A1 INDICATOR4

2.50

5.00

A1 CORNER

TOP VIEW

48-wfbga-Y1Q-4x6-320mic-5-2.0

Note: 1. Complies with JEDEC Publication 95, MO-207, variant CZB-4, dimensions except nominal ball width

is larger.

2. All linear dimensions are in millimeters.

3. Coplanarity: 0.08 mm

4. No ball is present in position A1; a gold-colored indicator is present.

5. Ball width at interface to package body surface is 0.29 mm.

1mm

DETAIL SIDE VIEW

SEATING PLANE

0.23 ±0.06

0.61 ±0.10

0.08

4.00

±0.08

6.00

±0.08

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Data Sheet

2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash

SST39LF200A / SST39LF400A / SST39LF800A

SST39VF200A / SST39VF400A / SST39VF800A

TABLE 17: Revision History

Number Description Date

04 •2002 Data Book May 2002

05 •Added footnotes for MPF power usage and Typical conditions to Table 10 on page 12

•Clarified the Test Conditions for Power Supply Current and Read parameters in Table

10 on page 12

•Part number changes - see page 27 for additional information

•New Micro-Package part numbers added for SST39VF400A and SST39VF800A

Mar 2003

06 •New Micro-Package part numbers added for SST39VF400A / 800A (see page 27) Oct 2003

07 •2004 Data Book

•Updated the B3K, M1Q, and C1Q package diagrams

•Added non-Pb MPNs and removed footnote (see page 27)

Nov 2003

08 •Added M1Q/M1QE MPNs for the SSTVF200A device on page 27

•Removed 90ns MPNs and footnote for the SSTVFx00A devices on page 27

•Added RoHS compliance information on page 1 and in the “Product Ordering Informa-

tion” on page 26

•Clarified the solder temperature profile under “Absolute Maximum Stress Ratings” on

page 11.

Apr 2005

09 •Removed valid combinations SST39LF400A-45-4C-EK, SST39LF400A-45-4C-B3K,

SST39LF400A-45-4C-EKE, and SST39LF400A-45-4C-B3KE due to EOL

•Applied new format styles.

Feb 2007

10 •Add Y1QE package

•Removed all pb parts

Aug 2007

Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036

www.SuperFlash.com or www.sst.com

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