19-5182; Rev 1; 5/11 TION KIT EVALUA BLE AVAILA 1Gbps to 11.3Gbps, SFP+ Laser Driver with Laser Impedance Mismatch Tolerance The MAX3946 is a +3.3V, multirate, low-power laser diode driver designed for Ethernet and Fibre Channel transmission systems at data rates up to 11.3Gbps. This device is optimized to drive a differential transmitter optical subassembly (TOSA) with a 25I flex circuit. The unique design of the output stage enables use of unmatched TOSAs, greatly reducing headroom limitations and lowering power consumption. The device receives differential CML-compatible signals with on-chip line termination. It can deliver laser modulation current of up to 80mA, at an edge speed of 22ps (20% to 80%), into a 5I to 25I external differential load. The device is designed to have a symmetrical output stage with on-chip back terminations integrated into its outputs. A high-bandwidth, fully differential signal path is implemented to minimize deterministic jitter. An equalization block can be activated to compensate for the SFP+ connector. The integrated bias circuit provides programmable laser bias current up to 80mA. Both the laser bias generator and the laser modulator can be disabled from a single pin. A 3-wire digital interface reduces the pin count and permits adjustment of input equalization, pulse-width adjustment, Tx polarity, Tx deemphasis, modulation current, and bias current without the need for external components. The MAX3946 is available in a 4mm x 4mm, 24-pin TQFN package. Applications 4x/8x FC SFP+ Optical Transceivers 10GFC SFP+ Optical Transceivers 10GBASE-LR SFP+ Optical Transceivers 10GBASE-LRM SFP+ Optical Transceivers Features S 225mW Power Dissipation Enables < 1W SFP+ Modules S Up to 100mW Power Consumption Reduction by Enabling the Use of Unmatched FP/DFB TOSAs S Supports SFF-8431 SFP+ MSA and SFF-8472 Digital Diagnostic S 225mW Power Dissipation at 3.3V (IMOD = 40mA, IBIAS = 60mA Assuming 25I TOSA) S Single +3.3V Power Supply S Up to 11.3Gbps (NRZ) Operation S Programmable Modulation Current from 10mA to 100mA (5I Load) S Programmable Bias Current from 5mA to 80mA S Programmable Input Equalization S Programmable Output Deemphasis S 25I Output Back Termination at TOUT+ and TOUTS DJ Performance 7psP-P with Mismatched Differential Load (5I) S DJ Performance 5psP-P with Mismatched Differential Load (25I) S DJ Performance 5psP-P with 50I Differential Load S Programmable Pulse Width S Edge Transition Times of 22ps S Bias Current Monitor S Integrated Eye Safety Features S 3-Wire Digital Interface S -40C to +95C Operation Ordering Information OC192-SR XFP/SFP+ SDH/SONET Transceivers PART MAX3946ETG+ TEMP RANGE PIN-PACKAGE -40C to +85C 24 TQFN-EP* Note: Parts are guaranteed by design and characterization to operate over the -40C to +95C ambient temperature range (TA) and are tested up to +85C. +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. ________________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. MAX3946 General Description MAX3946 1Gbps to 11.3Gbps, SFP+ Laser Driver with Laser Impedance Mismatch Tolerance ABSOLUTE MAXIMUM RATINGS VCC, VCCT, VCCD .................................................-0.3V to +4.0V Current Into TOUT+ and TOUT-..................................... +100mA Current Into TIN+ and TIN-.............................. -20mA to +20mA Voltage Range at TIN+, TIN-, DISABLE, SDA, SCL, CSEL, FAULT, BMAX, and BMON................................. -0.3V to (VCC + 0.3V) Voltage Range at BIAS.........................................................-0.3V to VCC Voltage Range at TOUT+ and TOUT-.....(VCC - 1.3V) to (VCC + 1.3V) Current into BIAS..........................................................................+130mA Continuous Power Dissipation (TA = +70NC) TQFN (derate 27.8mW/NC above +70NC)..................2222mW Storage Temperature Range ........................... -55NC to +150NC Die Attach Temperature . ................................................+400NC Lead Temperature (soldering, 10s).................................+300NC Soldering Temperature (reflow).......................................+260NC Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. PACKAGE THERMAL CHARACTERISTICS (Note 1) TQFN Junction-to-Ambient Thermal Resistance (qJA)...........36C/W Junction-to-Case Thermal Resistance (qJC)..................3C/W Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial. ELECTRICAL CHARACTERISTICS (VCC = +2.85V to +3.63V, TA = -40C to +85C, and Figure 1. Guaranteed by design and characterization from TA = -40C to +95C. Typical values are at VCC = +3.3V, IBIAS = 60mA, IMOD = 40mA, 25I differential output load, and TA = +25C, unless otherwise noted.) (Note 2) PARAMETER SYMBOL CONDITIONS Power-Supply Current ICC Excludes output current through the external pullup inductors (Note 3) Power-Supply Voltage VCC MIN TYP MAX UNITS 68 90 mA 3.63 V POWER SUPPLY Power-Supply Noise 2.85 DC to 10MHz 100 10MHz to 20MHz 10 mVP-P POWER-ON RESET VCC for Enable High 2.55 VCC for Enable Low 2.3 2.45 1 10 2.75 V V DATA INPUT SPECIFICATION Input Data Rate TXEQ_EN = high, launch amplitude into FR4 transmission line P 5.5in 0.19 TXEQ_EN = low 0.15 11.3 0.7 Gbps Differential Input Voltage VIN Differential Input Resistance RIN Differential Input Return Loss SDD11 Part powered on, f P 10GHz 12 dB Common-Mode Input Return Loss SCC11 Part powered on, 1GHz P f P 10GHz 10 dB 75 VP-P 1.0 100 125 I BIAS GENERATOR Maximum Bias Current IBIASMAX Current into BIAS pin, DISABLE = low, and TX_EN = high 80 2 _______________________________________________________________________________________ mA 1Gbps to 11.3Gbps, SFP+ Laser Driver with Laser Impedance Mismatch Tolerance (VCC = +2.85V to +3.63V, TA = -40C to +85C, and Figure 1. Guaranteed by design and characterization from TA = -40C to +95C. Typical values are at VCC = +3.3V, IBIAS = 60mA, IMOD = 40mA, 25I differential output load, and TA = +25C, unless otherwise noted.) (Note 2) PARAMETER SYMBOL CONDITIONS Minimum Bias Current IBIASMIN Current into BIAS pin, DISABLE = low, and TX_EN = high Bias-Off Current IBIAS-OFF Current into BIAS pin, DISABLE = high or TX_EN = low or SET_IBIAS[8:0] = H0x00; BIAS pin voltage at VCC BMON Current Gain MAX UNITS 5 mA 100 FA 1 3 % 0.9 1.5 2.1 V 9 10 11 mA/A 5mA P IBIAS P 80mA, VBIAS = VCC - 1.5V (Notes 2, 4) Bias Current DAC Stability Instantaneous Compliance Voltage at BIAS MIN VBIAS GBMON GBMON = IBMON/IBIAS, external resistor to ground defines voltage Compliance Voltage at BMON TYP 0 BMON Current Gain Stability 1.2 5mA P IBIAS P 80mA (Notes 2, 4) 1.8 V 4 % VCC + 1.0 V LASER MODULATOR TOUT+ and TOUTInstantaneous Output Compliance Voltage Maximum Modulation Current VCC 1.0 IMODMAX Minimum Modulation Current IMODMIN Differential Output Resistance 2 x ROUT Modulation-Off Maximum Current IMOD-OFF Modulation Current DAC Stability Modulation Current Edge Speed (Note 2) Deterministic Jitter (Notes 2, 5) tR, tF DJ Current into external 25I differential termination, output common-mode voltage = VCC 80 Current into external 50I differential termination, output common-mode voltage = VCC 60 mAP-P 10 50 Current between TOUT+ and TOUT- when DISABLE = high or TX_EN = low or SET_IMOD[8:0] = H0x00 mAP-P I 100 FA % 10mA P IMOD P 80mA (Notes 2, 4) 1.5 3 20% to 80%, 20mA P IMOD P 80mA 22 30 20% to 80%, 10mA P IMOD P 80mA, TXDE_MD[1:0] = 3d 22 30 10mA P IMOD P 60mA, 11.3Gbps, output differential load = 50I 5 12 10mA P IMOD P 80mA, 11.3Gbps, output differential load = 25I 5 12 10mA P IMOD P 80mA, 11.3Gbps, output differential load = 5I 7 10mA P IMOD P 60mA, 10.7Gbps, output differential load = 50I (K28.5 pattern) 5 ps psP-P 10.5 _______________________________________________________________________________________ 3 MAX3946 ELECTRICAL CHARACTERISTICS (continued) MAX3946 1Gbps to 11.3Gbps, SFP+ Laser Driver with Laser Impedance Mismatch Tolerance ELECTRICAL CHARACTERISTICS (continued) (VCC = +2.85V to +3.63V, TA = -40C to +85C, and Figure 1. Guaranteed by design and characterization from TA = -40C to +95C. Typical values are at VCC = +3.3V, IBIAS = 60mA, IMOD = 40mA, 25I differential output load, and TA = +25C, unless otherwise noted.) (Note 2) PARAMETER Random Jitter Differential Output Return Loss SYMBOL RJ SDD22 CONDITIONS MIN 10mA P IMOD P 80mA, output differential load = 25I (Note 2) TYP MAX UNITS 0.19 0.55 psRMS Part powered on, f P 5GHz 8 Part powered on, f P 10GHz 6 dB SAFETY FEATURES Threshold Voltage at BMAX VBMAX FAULT always occurs for VBMAX R 1.3V, FAULT never occurs for VBMAX < 1.1V (Note 2, Figure 1) 1.1 1.2 1.3 V Threshold Voltage at BIAS VBIAS FAULT never occurs for VBIAS R 0.57V, FAULT always occurs for VBIAS < 0.44V 0.44 0.48 0.57 V Warning always occurs for VBMON R VCC - 0.5V, warning never occurs for VBMON < VCC - 0.7V VCC 0.7 VCC 0.6 VCC 0.5 V Threshold Voltage at BMON VBMON SFP TIMING REQUIREMENTS DISABLE Assert Time t_OFF Time from rising edge of DISABLE input signal to IBIAS < IBIAS-OFF and IMOD < IMOD-OFF 0.05 1 Fs DISABLE Negate Time t_ON Time from falling edge of DISABLE to IBIAS and IMOD at 90% of steady state 0.5 5 Fs FAULT Reset Time of Power-On Time t_INIT Time from power-on or negation of FAULT using DISABLE 50 200 Fs Time from fault to FAULT on, CFAULT P 20pF, RFAULT = 4.7kI 0.5 2 Fs FAULT Reset Time t_FAULT DISABLE to Reset Time DISABLE must be held high to reset FAULT 0.5 SET_IBIAS[8:1] = HxFF 80 Fs BIAS CURRENT DAC Full-Scale Current IBIAS-FS LSB Size 100 mA 190 FA Integral Nonlinearity INL 5mA P IBIAS P 80mA 0.5 %FS Differential Nonlinearity DNL 5mA P IBIAS P 80mA, guaranteed monotonic at 8-bit resolution SET_IBIAS[8:1] 0.5 LSB 105 mA MODULATION CURRENT DAC (25I DIFFERENTIAL LOAD) Full-Scale Current IMOD-FS SET_IMOD[8:1] = HxFF LSB Size Integral Nonlinearity INL 10mA P IMOD P 80mA Differential Nonlinearity DNL 10mA P IMOD P 80mA, guaranteed monotonic at 9-bit resolution SET_IMOD[8:0] 80 200 FA Q1 %FS Q0.5 LSB 4 _______________________________________________________________________________________ 1Gbps to 11.3Gbps, SFP+ Laser Driver with Laser Impedance Mismatch Tolerance (VCC = +2.85V to +3.63V, TA = -40C to +85C, and Figure 1. Guaranteed by design and characterization from TA = -40C to +95C. Typical values are at VCC = +3.3V, IBIAS = 60mA, IMOD = 40mA, 25I differential output load, and TA = +25C, unless otherwise noted.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX 500 800 UNITS CONTROL I/O SPECIFICATIONS DISABLE Input Current DISABLE Input High Voltage IIH IIL 12 Depends on pullup resistance VIH DISABLE Input Low Voltage VIL DISABLE Input Resistance RPULL 1.8 VCC 0 Internal pullup resistor 4.7 7.5 FA V 0.8 V 10 kI VCC V 0.8 V 3-WIRE DIGITAL I/O SPECIFICATIONS (SDA, SCL, CSEL) Input High Voltage VIH Input Low Voltage VIL Input Hysteresis 2.0 VHYST Input Leakage Current IIL, IIH Output High Voltage VOH Output Low Voltage VOL 80 VIN = 0V or VCC, internal pullup or pulldown is 75kI typical External pullup is (4.7kI to 10kI) to VCC External pullup is (4.7kI to 10kI) to VCC mV 150 VCC - 0.5 FA V 0.4 V 1000 kHz 3-WIRE DIGITAL INTERFACE TIMING CHARACTERISTICS (Figure 5) SCL Clock Frequency fSCL SCL Pulse-Width High tCH 0.5 SCL Pulse-Width Low tCL 0.5 SDA Setup Time tDS 100 ns SDA Hold Time tDH 100 ns tD 5 ns SCL Rise to SDA Propagation Time CSEL Pulse-Width Low 400 tCSW Fs Fs 500 ns CSEL Leading Time Before the First SCL Edge tL 500 ns CSEL Trailing Time After the Last SCL Edge tT 500 ns SDA, SCL Load CB Total bus capacitance on one line with 4.7kI pullup to VCC 20 pF Note 2: Guaranteed by design and characterization (TA = -40NC to +95NC). Note 3: BIAS is connected to 2.0V. TOUT+/TOUT- are connected through pullup inductors to a separate supply that is equal to VCCT. Note 4: Stability is defined as [(I_measured) - (I_reference)]/(I_reference) over the listed current range, temperature, and VCC = VCCREF Q5%. VCCREF = 3.0V to 3.45V. Reference current measured at VCCREF, TA = +25NC. Note 5: Measured with K28.5 data pattern at 10.7Gbps and with a (27 - 1 PRBS + 72 zeros + 27 - 1 PRBS (inverted) + 72 ones) pattern at 11.3Gbps. _______________________________________________________________________________________ 5 MAX3946 ELECTRICAL CHARACTERISTICS (continued) MAX3946 1Gbps to 11.3Gbps, SFP+ Laser Driver with Laser Impedance Mismatch Tolerance VCCD 0.01F VCC + - VCCT 2.0V 4.7kI 0.1F VCCT BIAS VCCD VEET CSEL SCL VCC SDA 0.01F VCCT VCC VCC 0.01F 0.01F 0.1F 35I Z0 = 50I TIN+ 25I TOUT+ MAX3946 50I 75I 0.01F Z0 = 50I TIN- 0.1F 50I 25I TOUT- SAMPLING OSCILLOSCOPE 35I VCC VCC EP VEET VCCT 50I VCCT BMON BMAX FAULT DISABLE VCCD 0.01F VCCT VCC 4.7kI 0.01F 1kI 0.01F 0.1F 1kI Figure 1. AC Test Setup 6 _______________________________________________________________________________________ 50I 1Gbps to 11.3Gbps, SFP+ Laser Driver with Laser Impedance Mismatch Tolerance 10.3Gbps OPTICAL EYE DIAGRAM 10.3Gbps ELECTRICAL EYE DIAGRAM MAX3946 toc01 MAX3946 toc02 223 - 1 PRBS 20ps/div -5 -5 0 -10 -15 -20 -15 -20 -25 -25 -30 -30 -35 SCD11 (dB) -10 SCC11 (dB) -35 100 1000 10,000 100,000 -30 -50 10,000 1000 100,000 1000 100 10,000 100,000 FREQUENCY (MHz) FREQUENCY (MHz) OUTPUT DIFFERENTIAL RETURN LOSS vs. FREQUENCY OUTPUT COMMON-MODE RETURN LOSS vs. FREQUENCY RANDOM JITTER vs. MODULATION CURRENT (AT LOAD) MAX3946 toc06 0 -10 1.0 -5 0.8 0.7 RJ (psRMS) SCC22 (dB) -30 -15 -20 1000 10,000 FREQUENCY (MHz) 100,000 0.4 0.1 0 -35 100 0.5 0.2 -30 -50 0.6 0.3 -25 -40 11.3Gbps, 25 DIFFERENTIAL LOAD 1111 0000 PATTERN 0.9 -10 -20 MAX3946 toc08 FREQUENCY (MHz) 0 SDD22 (dB) -20 -40 MAX3946 toc07 SDD11 (dB) -10 INPUT DIFFERENTIAL TO COMMON-MODE RETURN LOSS vs. FREQUENCY MAX3946 toc04 0 MAX3946 toc03 0 INPUT COMMON-MODE RETURN LOSS vs. FREQUENCY MAX3946 toc05 INPUT DIFFERENTIAL RETURN LOSS vs. FREQUENCY 100 1000 10,000 FREQUENCY (MHz) 100,000 0 10 20 30 40 50 60 70 80 MODULATION CURRENT (mAP-P) _______________________________________________________________________________________ 7 MAX3946 Typical Operating Characteristics (VCC = +3.3V, TA = +25C, data pattern = 27 - 1 PRBS + 72 zeros + 27 - 1 PRBS (inverted) +72 ones, unless otherwise noted.) Typical Operating Characteristics (continued) (VCC = +3.3V, TA = +25C, data pattern = 27 - 1 PRBS + 72 zeros + 27 - 1 PRBS (inverted) +72 ones, unless otherwise noted.) 70 60 70 65 200 60 190 25 LOAD 180 170 5 LOAD 20 35 50 65 80 95 5 20 35 50 65 80 BIAS CURRENT vs. DAC SETTING MODULATION CURRENT (AT LOAD) vs. DAC SETTING 40 20 0 RLOAD = 25 DIFFERENTIAL 60 50 40 RLOAD = 50 DIFFERENTIAL 30 10 8 200 400 7 6 5 4 3 20 2 10 1 0 0 600 SET_IMOD[8:0] = 230d TXDE_MD[1:0] = 2d 9 DEEMPHASIS (%) 60 MODULATION CURRENT DEEMPHASIS vs. MANUAL DEEMPHASIS SETTING MAX3946 toc13 MAX3946 toc12 80 80 70 25 95 SET_PWCTRL[3:0] 90 MODULATION CURRENT (mAP-P) 0 0 200 400 600 10 20 30 SET_IMOD[8:0] SET_TXDE[5:0] BIAS MONITOR CURRENT vs. TEMPERATURE EDGE SPEED vs. MODULATION CURRENT EDGE SPEED vs. DEEMPHASIS SETTING 40 MAX3946 toc15 700 600 25 LOAD, 20% TO 80% 10Gbps, 11111 00000 PATTERN 35 40 SET_IMOD[8:0] = 230d 25 LOAD, 20% TO 80% 10Gbps, 1111 0000 PATTERN 35 40 MAX3946 toc17 SET_IBIAS[8:0] MAX3946 toc16 EDGE SPEED (ps) IBIAS = 60mA IBIAS = 30mA 400 300 IBIAS = 10mA 200 30 FALL TIME 25 20 0 -40 -25 -10 5 20 35 50 TEMPERATURE (C) 65 80 95 20 40 60 IMOD (mA) FALL TIME 25 20 15 10 0 30 RISE TIME RISE TIME 15 100 EDGE SPEED (ps) BIAS CURRENT (mA) -40 -25 -10 TEMPERATURE (C) 100 500 30 TEMPERATURE (C) 120 45 1001 1010 1011 1100 1101 1110 1111 0000 0001 0010 0011 0100 0101 0110 0111 5 50 35 140 -40 -25 -10 55 40 160 150 50 MAX3946 toc11 75 MAX3946 toc14 SUPPLY CURRENT (mA) 80 CURRENT INTO VCC, VCCT, AND VCCD PINS PLUS MODULATION AND BIAS CURRENT 210 EYE CROSSING PERCENT vs. SET_PWCTRL CROSSING (%) CURRENT INTO VCC, VCCT, AND VCCD PINS 90 SUPPLY CURRENT (mA) 220 MAX3946 toc09 100 TOTAL CURRENT vs. TEMPERATURE (IMOD AT LOAD = 40mAP-P, IBIAS = 60mA) MAX3946 toc10 SUPPLY CURRENT vs. TEMPERATURE (IMOD = 40mAP-P, IBIAS = 60mA) BMON CURRENT (A) MAX3946 1Gbps to 11.3Gbps, SFP+ Laser Driver with Laser Impedance Mismatch Tolerance 80 100 10 10 20 30 SET_TXDE[5:0] 8 _______________________________________________________________________________________ 40 1Gbps to 11.3Gbps, SFP+ Laser Driver with Laser Impedance Mismatch Tolerance TRANSMITTER DISABLE TRANSMITTER ENABLE MAX3946 toc18 VCC VCC 3.3V RESPONSE TO FAULT MAX3946 toc19 3.3V EXTERNAL FAULT VBIAS t_ON = 600ns FAULT DISABLE LOW HIGH HIGH DISABLE LOW HIGH FAULT LOW FAULT MAX3946 toc20 LOW LOW DISABLE OUTPUT OUTPUT OUTPUT 100ns/div 1s/div FAULT RECOVERY VBIAS DISABLE MAX3946 toc22 VBIAS LOW HIGH LOW OUTPUT FREQUENT ASSERTION OF DISABLE MAX3946 toc21 EXTERNAL FAULT REMOVED FAULT 1s/div FAULT DISABLE EXTERNAL FAULT HIGH LOW HIGH LOW OUTPUT 4s/div 4s/div _______________________________________________________________________________________ 9 MAX3946 Typical Operating Characteristics (continued) (VCC = +3.3V, TA = +25C, data pattern = 27 - 1 PRBS + 72 zeros + 27 - 1 PRBS (inverted) +72 ones, unless otherwise noted.) MAX3946 1Gbps to 11.3Gbps, SFP+ Laser Driver with Laser Impedance Mismatch Tolerance SDA CSEL VCCD BIAS VCCT TOP VIEW SCL Pin Configuration 18 17 16 15 14 13 VEET 19 12 VCCT VCC 20 11 TOUT+ TIN+ 21 10 TOUT+ 9 TOUT- 8 TOUT- 7 VCCT MAX3946 TIN- 22 VCC 23 *EP + 1 2 3 4 5 6 VCCD DISABLE FAULT BMAX BMON VCCT VEET 24 THIN QFN (4mm x 4mm) *EXPOSED PAD CONNECTED TO GROUND. Pin Description PIN NAME 1, 15 VCCD 2 DISABLE FUNCTION Power Supply. Provides supply voltage to the digital block. Disable Input, CMOS. Set to logic-low for normal operation. Logic-high or open disables both the modulation current and the bias current. Internally pulled up by a 7.5kI resistor to VCCD. 3 FAULT Fault Output, Open Drain. Logic-high indicates a fault condition. FAULT remains high even after the fault condition has been removed. A logic-low occurs when the fault condition has been removed and the fault latch has been cleared by toggling the DISABLE pin. FAULT should be pulled up to VCC by a 4.7kI to 10kI resistor. 4 BMAX Analog Laser Bias-Current Limit. A resistive voltage-divider connected among BMON, BMAX, and ground sets the maximum allowed laser bias current limit. The voltage at BMAX is internally compared to 1.2V bandgap reference voltage. 5 BMON Bias Current-Monitor Output. Current out of this pin develops a ground-referenced voltage across external resistor(s) that is proportional to the laser bias current. The current sourced by this pin is typically 1/100th the BIAS pin current. 6, 7, 12, 13 VCCT Power Supply. Provides supply voltage to the output block. 8, 9 TOUT- Inverted Modulation Current Output. Internally pulled up by a 25I resistor to VCCT. 10, 11 TOUT+ 14 BIAS Noninverted Modulation Current Output. Internally pulled up by a 25I resistor to VCCT. Laser Bias Current Connection. This pin requires a 0.1F capacitor to VEET for proper operation. 16 CSEL Chip-Select Input, CMOS. Setting CSEL to logic-high starts a cycle. Setting CSEL to logic-low ends the cycle and resets the control state machine. Internally pulled down by a 75kI resistor to VEET. 17 SDA Serial-Data Bidirectional Input, CMOS. Open-drain output. This pin has a 75kI internal pullup, but it requires an external 4.7kI to 10kI pullup resistor. (Data line-collision protection is implemented.) 10 1Gbps to 11.3Gbps, SFP+ Laser Driver with Laser Impedance Mismatch Tolerance PIN NAME FUNCTION 18 SCL Serial-Clock Input, CMOS. This pin has a 75kI internal pulldown. 19, 24 VEET Ground 20, 23 VCC Power-Supply Connections. Provides supply voltage to the core circuitry. 21 TIN+ Noninverted Data Input 22 TIN- Inverted Data Input -- EP Exposed Pad. Ground. Must be soldered to circuit board ground for proper thermal and electrical performance (see the Exposed-Pad Package and Thermal Considerations section). VCCD 7.5kI TOUT+ DISABLE EYE SAFETY AND OUTPUT CONTROL TX_EN FAULT BMAX 25I VCCT LASER BIAS CURRENT LIMITER VCM 25I POWER-ON RESET 50I 50I TIN+ EQ TIN- TOUT- TX_POL 1 IBIAS PW CONTROL 0 IBIAS IMOD_DAC + IDE_DAC VCCD BIAS VCC 100 BMON CONTROL LOGIC 75kI SDA 3-WIRE INTERFACE SCL CSEL 75kI 75kI REGISTER SET_TXEQ MAX3946 SET_PWCTRL VEET VEET 9b DAC SET_IMOD 6b DAC SET_TXDE 9b DAC SET_IBIAS Figure 2. Functional Diagram ______________________________________________________________________________________ 11 MAX3946 Pin Description (continued) MAX3946 1Gbps to 11.3Gbps, SFP+ Laser Driver with Laser Impedance Mismatch Tolerance Detailed Description The MAX3946 SFP+ laser driver is designed to drive 5I to 50I TOSAs from 1Gbps to 11.3Gbps. The device contains an input buffer with programmable equalization, pulse-width adjustment, bias current and modulation current DACs, output driver with programmable deemphasis, power-on reset circuitry, bias monitor, laser current limiter, and eye-safety circuitry. A 3-wire digital interface is used to control the transmitter functions. The registers that control the device's functionality are TXCTRL, SET_IMOD, SET_IBIAS, IMODMAX, IBIASMAX, MODINC, BIASINC, SET_TXEQ, SET_PWCTRL, and SET_TXDE. Input Buffer with Programmable Equalization The input is internally biased and terminated with 50I to a common-mode voltage. The first amplifier stage features a programmable equalizer for high-frequency losses including SFP connector. Equalization is controlled by the SET_TXEQ register and TXEQ_EN bit, TXCTRL[3] (Table 1). The TX_POL bit in the TXCTRL register controls the polarity of TOUT+ and TOUT- vs. TIN+ and TIN-. The SET_PWCTRL register controls the output eye crossing (Table 5). A status indicator bit (TXED) monitors the presence of an AC input signal. Bias Current DAC The device's bias current is optimized to provide up to 80mA of bias current into a 5I to 50I laser load with 200FA resolution. The bias current is controlled through the 3-wire digital interface using the SET_IBIAS, IBIASMAX, and BIASINC registers. For laser operation, the laser bias current can be set using the 9-bit SET_IBIAS DAC. The upper 8 bits are set by the SET_IBIAS[8:1] register, commonly used during the initialization procedure after POR. The LSB (bit 0) of SET_IBIAS is initialized to zero after POR and can be updated using the BIASINC register. The IBIASMAX register should be programmed to a desired maximum bias current value (up to 96mA) to protect the laser. The IBIASMAX register limits the maximum SET_IBIAS[8:1] DAC code. After initialization the value of the SET_IBIAS DAC register should be updated using the BIASINC register to optimize cycle time and enhance laser safety. The BIASINC register is an 8-bit register where the first 5 bits contain the increment information in two's complement notation. Increment values range from -16 to +15 LSBs. If the updated value of SET_IBIAS[8:1] exceeds IBIASMAX[7:0], the IBIASERR warning flag is set and SET_IBIAS[8:0] remains unchanged. Modulation Current DAC The modulation current from the device is optimized to provide up to 80mA of modulation current into a 5I to 25I differential laser load (60mA for 50I laser load) with 300FA to 200FA resolution. The modulation current is controlled through the 3-wire digital interface using the SET_IMOD, IMODMAX, MODINC, and SET_TXDE registers. For laser operation, the laser modulation current can be set using the 9-bit SET_IMOD DAC. The upper 8 bits are set by the SET_IMOD[8:1] register, commonly used during the initialization procedure after POR. The LSB (bit 0) of SET_IMOD is initialized to zero after POR and can be updated using the MODINC register. The IMODMAX register should be programmed to a desired maximum modulation current value (up to 96mA) to protect the laser. The IMODMAX register limits the maximum SET_IMOD[8:1] DAC code. Table 1. Input Equalization Control Register Settings TXCTRL[3] TXEQ_EN SET_TXEQ[2:1] DESCRIPTION 0 X X 150mVP-P to 1000mVP-P differential input amplitude (default setting) 1 0 0 Optimized for 1in to 4in FR4, 190mVP-P to 450mVP-P differential launch amplitude from source 1 0 1 Optimized for 4in to 6in FR4, 190mVP-P to 450mVP-P differential launch amplitude from source 1 1 0 Optimized for 1in to 4in FR4, 450mVP-P to 700mVP-P differential launch amplitude from source 1 1 1 Optimized for 4in to 6in FR4, 450mVP-P to 700mVP-P differential launch amplitude from source 12 1Gbps to 11.3Gbps, SFP+ Laser Driver with Laser Impedance Mismatch Tolerance MAX3946 0.6V IBIAS + - 100 OR WARNING BMON IF BMAX IS NOT USED R1 100kI OR IF BMON IS NOT USED R1 OR IF BMAX AND BMON ARE NOT USED 1kI BMAX FAULT 1.2V R2 1kI R2 Figure 3. BMON and BMAX Circuitry After initialization the value of the SET_IMOD DAC register should be updated using the MODINC register to optimize cycle time and enhance laser safety. The MODINC register is an 8-bit register where the first 5 bits contain the increment information in two's complement notation. Increment values range from -16 to +15 LSBs. If the updated value of SET_IMOD[8:1] exceeds IMODMAX[7:0], the IMODERR warning flag is set and SET_IMOD[8:0] remains unchanged. Modulation current sent to the laser is actually the combination of the current generated by the SET_IMOD register and current subtracted from this by the SET_TXDE register. Output Driver The output driver is optimized for a 5I to 50I differential load. The output stage also features programmable deemphasis that can be set as a percentage of the modulation current. The deemphasis function is controlled by the TXDE_MD[1] and TXDE_MD[0] bits (TXCTRL[5:4]) and SET_TXDE[5:0]. Power-On Reset (POR) POR ensures that the laser is off until supply voltage has reached a specified threshold (2.75V). After POR, bias current and modulation current ramps are controlled to avoid overshoot. In the case of a POR, all registers are reset to their default values. BMON and BMAX Functions Current out of the BMON pin is typically 1/100th the value of the current at the BIAS pin. The total resistance to ground at BMON sets the voltage gain. An internal comparator at the BMAX pin latches a fault if the voltage on BMAX exceeds the value of 1.2V. The BMAX voltagesense pin is connected by means of a voltage-divider to the BMON pin and ground. The full-scale range of the BMON voltage is 1.2V x (R1/R2 + 1) (Figure 3). The analog bias-current limit is determined by (1.2V/R2) x 100. Eye Safety and Output Control Circuitry The safety and output control circuitry includes the disable pin (DISABLE) and disable bit (TX_EN), along with a fault indicator and fault detectors (Figure 4). The device has two types of faults, HARD FAULT and SOFT FAULT. A HARD FAULT triggers the FAULT pin, and the output to the laser is disabled. A SOFT FAULT operates as a warning, and the outputs are not disabled. Both types of faults are stored in the TXSTAT1 and TXSTAT2 registers. The FAULT pin is a latched output that can be cleared by toggling the DISABLE pin. Toggling the DISABLE pin also clears the TXSTAT1 and TXSTAT2 registers. A single-point fault can be a short to VCC or ground. Table 2 shows the circuit response to various single-point faults. ______________________________________________________________________________________ 13 MAX3946 BIAS VCC MAX3946 1Gbps to 11.3Gbps, SFP+ Laser Driver with Laser Impedance Mismatch Tolerance FAULT REGISTERS VCCT TOUTTOUT+ VEET <0> FAULT IMOD 0.44V <1> VEET BIAS VCC - 2V <2> FAULT REGISTER TXSTAT1 <3> VCC - 1.3V IBIAS ADDR = H0x06 BMAX <4> 1.3V IBIAS 100 UNUSED <5> VEET BMON <6> VCC - 0.5V POR 2.3V <7> VCCD RESET 7.5kI DISABLE UNUSED LOSS-OF-SIGNAL CIRCUIT WARNING REGISTER TXSTAT2 <0> ADDR = H0x07 <1> SET_IBIAS IBIASMAX SET_IMOD IMODMAX <2> <3> Figure 4. Eye Safety Circuitry 14 1Gbps to 11.3Gbps, SFP+ Laser Driver with Laser Impedance Mismatch Tolerance PIN NAME 1 VCCD 2 DISABLE 3 4 SHORT TO VCC SHORT TO GROUND OPEN Normal Disabled--HARD FAULT Normal (Note 3)--Redundant path Disabled Normal (Note 1). Can only be disabled by other means. Disabled FAULT Normal (Note 1) Normal (Note 1) Normal (Note 1) BMAX Disabled--HARD FAULT Normal (Note 1) Disabled--HARD FAULT 5 BMON Disabled--HARD FAULT Normal (Note 1) Disabled--HARD FAULT 6 VCCT Normal Disabled--Fault (external supply shorted) (Note 2) Normal (Note 3)--Redundant path 7 VCCT Normal Disabled--Fault (external supply shorted) (Note 2) Normal (Note 3)--Redundant path 8 TOUT- IMOD is reduced Disabled--HARD FAULT IMOD is reduced 9 TOUT- IMOD is reduced Disabled--HARD FAULT IMOD is reduced 10 TOUT+ IMOD is reduced Disabled--HARD FAULT IMOD is reduced 11 TOUT+ IMOD is reduced Disabled--HARD FAULT IMOD is reduced Normal (Note 3)--Redundant path 12 VCCT Normal Disabled--Fault (external supply shorted) (Note 2) 13 VCCT Normal Disabled--Fault (external supply shorted) (Note 2) Normal (Note 3)--Redundant path 14 BIAS IBIAS is on--No fault Disabled--HARD FAULT Disabled--HARD FAULT 15 VCCD Normal Disabled--Fault (external supply shorted) (Note 2) Normal (Note 3)--Redundant path 16 CSEL Normal (Note 1) Normal (Note 1) Normal (Note 1) 17 SDA Normal (Note 1) Normal (Note 1) Normal (Note 1) 18 SCL Normal (Note 1) Normal (Note 1) Normal (Note 1) 19 VEET Disabled--Fault (external supply shorted) (Note 2) Normal Normal (Note 3)--Redundant path 20 VCC Normal Disabled--HARD FAULT (external supply shorted) (Note 2) Normal (Note 3)--Redundant path 21 TIN+ SOFT FAULT SOFT FAULT Normal (Note 1) 22 TIN- SOFT FAULT SOFT FAULT Normal (Note 1) Normal (Note 3)--Redundant path Normal (Note 3)--Redundant path 23 VCC Normal Disabled--HARD FAULT (external supply shorted) (Note 2) 24 VEET Disabled--Fault (external supply shorted) (Note 2) Normal Note 1: Normal--Does not affect laser power. Note 2: S upply-shorted current is assumed to be primarily on the circuit board (outside this device), and the main supply is collapsed by the short. Note 3: Normal in functionality, but performance could be affected. Warning: Shorted to VCC or shorted to ground on some pins can violate the Absolute Maximum Ratings. ______________________________________________________________________________________ 15 MAX3946 Table 2. Circuit Response to Single-Point Faults MAX3946 1Gbps to 11.3Gbps, SFP+ Laser Driver with Laser Impedance Mismatch Tolerance 3-Wire Interface Read Mode (RWN = 1) The master generates 16 total clock cycles at SCL. The master outputs a total of 8 bits (MSB first) to the SDA line at the falling edge of the clock. The SDA line is released after the RWN bit has been transmitted. The slave outputs 8 bits of data (MSB first) at the rising edge of the clock. The master closes the transmission by setting CSEL to 0. Figure 5 shows the interface timing. The device implements a proprietary 3-wire digital interface. An external controller generates the clock. The 3-wire interface consists of an SDA bidirectional data line, an SCL clock signal input, and a CSEL chip-select input (active high). The external master initiates a data transfer by asserting the CSEL pin. The master starts to generate a clock signal after the CSEL pin has been set to a logic-high. All data transfers are most significant bit (MSB) first. Mode Control Normal mode allows read-only instruction for all registers except MODINC and BIASINC. The MODINC and BIASINC registers can be updated during normal mode. Doing so speeds up the laser control update through the 3-wire interface by a factor of two. The normal mode is the default mode. Protocol Each operation consists of 16-bit transfers (15-bit address/data, 1-bit RWN). The bus master generates 16 clock cycles to SCL. All operations transfer 8 bits to the device. The RWN bit determines if the cycle is read or write. See Table 3. Setup mode allows the master to write unrestricted data into any register except the status (TXSTAT1, TXSTAT2) registers. To enter the setup mode, the MODECTRL register (address = H0x0E) must be set to H0x12. After the MODECTRL register has been set to H0x12, the next operation is unrestricted. The setup mode is automatically exited after the next operation is finished. This sequence must be repeated if further unrestricted settings are necessary. Register Addresses The device contains 13 registers available for programming. Table 4 shows the registers and addresses. Write Mode (RWN = 0) The master generates 16 total clock cycles at SCL. The master outputs a total of 16 bits (MSB first) to the SDA line at the falling edge of the clock. The master closes the transmission by setting CSEL to 0. Figure 5 shows the interface timing. Table 3. Digital Communication Word Structure BIT 15 14 13 12 11 10 Register Address 9 8 7 6 RWN 5 4 3 2 Data that is written or read Table 4. Register Descriptions and Addresses ADDRESS NAME H0x05 TXCTRL Transmitter Control Register FUNCTION H0x06 TXSTAT1 Transmitter Status Register 1 H0x07 TXSTAT2 Transmitter Status Register 2 H0x08 SET_IBIAS Bias Current Setting Register H0x09 SET_IMOD Modulation Current Setting Register H0x0A IMODMAX Maximum Modulation Current Setting Register H0x0B IBIASMAX Maximum Bias Current Setting Register H0x0C MODINC Modulation Current Increment Setting Register H0x0D BIASINC Bias Current Increment Setting Register H0x0E MODECTRL H0x0F SET_PWCTRL Pulse-Width Control Register H0x10 SET_TXDE Deemphasis Control Register H0x11 SET_TXEQ Equalization Control Register Mode Control Register 16 1 0 1Gbps to 11.3Gbps, SFP+ Laser Driver with Laser Impedance Mismatch Tolerance MAX3946 WRITE MODE CSEL tL tT tCH SCL 0 tCL 1 2 3 4 5 6 7 8 9 A4 A3 A2 A1 A0 RWN D7 D6 10 11 12 13 14 15 tDS SDA A6 A5 D5 D4 D3 D2 D1 D0 tDH READ MODE CSEL tL tCH SCL 0 tT tCL 1 2 3 4 5 6 7 8 9 10 tDS SDA A6 A5 A4 11 12 13 14 15 tD A3 A2 A1 A0 RWN D7 D6 D5 D4 D3 D2 D1 D0 tDH Figure 5. Timing for 3-Wire Digital Interface Transmitter Control Register (TXCTRL) Bit # 7 6 Name X X Default Value X X 5 4 TXDE_MD[1] TXDE_MD[0] 0 3 2 1 0 TXEQ_EN SOFTRES TX_POL TX_EN 0 0 1 1 0 ADDRESS H0x05 Bits 5 and 4: TXDE_MD[1:0]. Controls the mode of the transmit output deemphasis circuitry. 00 = deemphasis is fixed at 6.25% of the modulation amplitude 01 = deemphasis is fixed at 3.125% of the modulation amplitude 10 = deemphasis is programmed by the SET_TXDE register setting 11 = deemphasis is at its maximum of approximately 9% Bit 3: TXEQ_EN. Enables or disables the input equalization circuitry. 0 = disabled 1 = enabled Bit 2: SOFTRES. Resets all registers to their default values (the DISABLE pin must be at a logic 1 during a write to SOFTRES for the registers to be set to their default values). 0 = normal 1 = reset Bit 1: TX_POL. Controls the polarity of the signal path. 0 = inverse 1 = normal Bit 0: TX_EN. Enables or disables the output circuitry. 0 = disabled 1 = enabled ______________________________________________________________________________________ 17 MAX3946 1Gbps to 11.3Gbps, SFP+ Laser Driver with Laser Impedance Mismatch Tolerance Transmitter Status Register 1 (TXSTAT1) Bit # Name Default Value 7 (STICKY) 6 (STICKY) 5 (STICKY) 4 (STICKY) 3 (STICKY) 2 (STICKY) 1 (STICKY) 0 (STICKY) FST[7] FST[6] X FST[4] FST[3] FST[2] FST[1] TX_FAULT X X X X X X X X ADDRESS H0x06 Bit 7: FST[7]. When the VCCT supply voltage is below 2.3V, the POR circuitry reports a fault. Once the VCCT supply voltage is above 2.75V, the POR resets all registers to their default values and the fault is cleared. Bit 6: FST[6]. When the voltage at BMON is above VCC - 0.5V, a SOFT FAULT is reported. Bit 4: FST[4]. When the voltage at BMAX goes above 1.3V, a HARD FAULT is reported. Bit 3: FST[3]. When the common-mode voltage at VTOUTQ goes below VCC - 1.3V, a SOFT FAULT is reported. Bit 2: FST[2]. When the voltage at VTOUTQ goes below VCC - 0.8V, a HARD FAULT is reported. Bit 1: FST[1]. When the BIAS voltage goes below 0.44V, a HARD FAULT is reported. Bit 0: TX_FAULT. Copy of a FAULT signal in FST[7:6] and FST[4:1]. A POR resets the FST bits to 0. Transmitter Status Register 2 (TXSTAT2) Bit # 7 6 5 4 3 (STICKY) 2 (STICKY) 1 (STICKY) 0 (STICKY) Name X X X X IMODERR IBIASERR TXED X Default Value X X X X X X X X ADDRESS H0x07 Bit 3: IMODERR. Any attempt to modify SET_IMOD[8:1] above IMODMAX[7:0] flags a warning at IMODERR. (See the Programming Modulation Current section.) Bit 2: IBIASERR. Any attempt to modify SET_IBIAS[8:1] above IBIASMAX[7:0] flags a warning at IBIASERR. (See the Programming Bias Current section.) Bit 1: TXED. This indicates the absence of an AC signal at the transmit input. Bias Current Setting Register (SET_IBIAS) Bit # Name Default Value 7 6 5 4 3 2 1 0 SET_IBIAS SET_IBIAS SET_IBIAS SET_IBIAS SET_IBIAS SET_IBIAS SET_IBIAS SET_IBIAS [8] (MSB) [7] [6] [5] [4] [3] [2] [1] 0 0 0 0 0 0 0 ADDRESS H0x08 1 Bits 7 to 0: SET_IBIAS[8:1]. The bias current DAC is controlled by a total of 9 bits. The SET_IBIAS[8:1] bits are used to set the bias current with even denominations from 0 to 510 bits. The LSB (SET_IBIAS[0]) is controlled by the BIASINC register and is used to set the odd denominations in the SET_IBIAS[8:0]. Any direct write to SET_IBIAS[8:1] resets the LSB. 18 1Gbps to 11.3Gbps, SFP+ Laser Driver with Laser Impedance Mismatch Tolerance Bit # Name Default Value 7 6 5 4 3 2 1 0 SET_IMOD SET_IMOD SET_IMOD SET_IMOD SET_IMOD SET_IMOD SET_IMOD SET_IMOD [8] (MSB) [7] [6] [5] [4] [3] [2] [1] 0 0 0 0 0 1 0 ADDRESS H0x09 0 Bits 7 to 0: SET_IMOD[8:1]. The modulation current DAC is controlled by a total of 9 bits. The SET_IMOD[8:1] bits are used to set the modulation current with even denominations from 0 to 510 bits. The LSB (SET_IMOD[0]) is controlled by the MODINC register and is used to set the odd denominations in the SET_IMOD[8:0]. Any direct write to SET_IMOD[8:1] resets the LSB. Maximum Modulation Current Setting Register (IMODMAX) Bit # Name Default Value 7 6 5 4 3 2 1 0 IMODMAX IMODMAX IMODMAX IMODMAX IMODMAX IMODMAX IMODMAX IMODMAX [7] (MSB) [6] [5] [4] [3] [2] [1] [0] (LSB) 0 0 1 0 0 0 0 ADDRESS H0x0A 0 Bits 7 to 0: IMODMAX[7:0]. The IMODMAX register is an 8-bit register that can be used to limit the maximum modulation current. IMODMAX[7:0] is continuously compared to SET_IMOD[8:1]. Any attempt to modify SET_IMOD[8:1] above IMODMAX[7:0] is ignored and flags a warning at IMODERR. Maximum Bias Current Setting Register (IBIASMAX) Bit # Name Default Value 7 6 5 4 3 2 1 0 ADDRESS IBIASMAX [7] (MSB) IBIASMAX [6] IBIASMAX [5] IBIASMAX [4] IBIASMAX [3] IBIASMAX [2] IBIASMAX [1] IBIASMAX [0] (LSB) H0x0B 0 0 1 0 0 0 0 0 Bits 7 to 0: IBIASMAX[7:0]. The IBIASMAX register is an 8-bit register that can be used to limit the maximum bias current. IBIASMAX[7:0] is continuously compared to SET_IBIAS[8:1]. Any attempt to modify SET_IBIAS[8:1] above IBIASMAX[7:0] is ignored and flags a warning at IBIASERR. Modulation Current Increment Setting Register (MODINC) Bit # Name Default Value 7 SET_IMOD [0] (LSB) 0 6 5 4 3 2 1 0 ADDRESS X X MODINC [4] (MSB) MODINC [3] MODINC [2] MODINC [1] MODINC [0] (LSB) H0x0C 0 0 0 0 0 0 0 Bit 7: SET_IMOD[0]. This is the LSB of the SET_IMOD[8:0] bits. This bit can only be updated by the use of MODINC[4:0]. Bits 4 to 0: MODINC[4:0]. This string of bits is used to increment or decrement the modulation current. When written to, the SET_IMOD[8:0] bits are updated. MODINC[4:0] are a two's complement string. ______________________________________________________________________________________ 19 MAX3946 Modulation Current Setting Register (SET_IMOD) MAX3946 1Gbps to 11.3Gbps, SFP+ Laser Driver with Laser Impedance Mismatch Tolerance Bias Current Increment Setting Register (BIASINC) Bit # Name 7 SET_IBIAS [0] (LSB) 0 Default Value 6 5 4 3 2 1 0 ADDRESS X X BIASINC [4] (MSB) BIASINC [3] BIASINC [2] BIASINC [1] BIASINC [0] (LSB) H0x0D 0 0 0 0 0 0 0 Bit 7: SET_IBIAS[0]. This is the LSB of the SET_IBIAS[8:0] bits. This bit can only be updated by the use of BIASINC[4:0]. Bits 4 to 0: BIASINC[4:0]. This string of bits is used to increment or decrement the bias current. When written to, the SET_IBIAS[8:0] bits are updated. BIASINC[4:0] are a two's complement string. Mode Control Register (MODECTRL) Bit # Name 7 6 5 4 3 2 1 0 MODECTRL MODECTRL MODECTRL MODECTRL MODECTRL MODECTRL MODECTRL MODECTRL [7] (MSB) [6] [5] [4] [3] [2] [1] [0] (LSB) 0 0 0 0 0 0 0 0 Default Value ADDRESS H0x0E Bits 7 to 0: MODECTRL[7:0]. The MODECTRL register enables the user to switch between normal and setup modes. The setup mode is achieved by setting this register to H0x12. MODECTRL must be updated before each write operation. Exceptions are MODINC and BIASINC, which can be updated in normal mode. Pulse-Width Control Register (SET_PWCTRL) Bit # 7 6 5 4 Name X X X X Default Value X X X X 3 2 1 0 ADDRESS SET_PWCTRL SET_PWCTRL SET_PWCTRL SET_PWCTRL [3] (MSB) [2] [1] [0] (LSB) 0 0 0 0 H0x0F Bits 3 to 0: SET_PWCTRL[3:0]. This is a 4-bit register used to control the eye crossing by adjusting the pulse width. Deemphasis Control Register (SET_TXDE) Bit # 7 6 Name X X Default Value X X 5 4 3 2 1 0 SET_TXDE SET_TXDE SET_TXDE SET_TXDE SET_TXDE SET_TXDE [5] (MSB) [4] [3] [2] [1] [0] (LSB) 0 0 0 0 0 ADDRESS H0x10 1 Bits 5 to 0: SET_TXDE[5:0]. This is a 6-bit register used to control the amount of deemphasis on the transmitter output. When calculating the total modulation current, the amount of deemphasis must be taken into account. The deemphasis is set as a percentage of modulation current. Equalization Control Register (SET_TXEQ) Bit # 7 6 5 4 3 Name X X X X X Default Value X X X X X 2 1 SET_TXEQ SET_TXEQ [2] [1] 0 0 0 X ADDRESS H0x11 X Bits 2 to 1: SET_TXEQ[2:1]. These 2 bits are used to control the amount of equalization on the transmitter input. See Table 1 for more information. 20 1Gbps to 11.3Gbps, SFP+ Laser Driver with Laser Impedance Mismatch Tolerance Programming Bias Current 1) IBIASMAX[7:0] = Maximum_Bias_Current_Value 2) SET_IBIASi[8:1] = Initial_Bias_Current_Value Note: The total bias current is calculated using the SET_IBIAS[8:0] DAC value. SET_IBIAS[8:1] are the bits that can be manually written. SET_IBIAS[0] can only be updated using the BIASINC register. When implementing an APC loop it is recommended to use the BIASINC register, which guarantees the fastest bias current update. 3) BIASINCi[4:0] = New_Increment_Value 4) If (SET_IBIASi[8:1] P IBIASMAX[7:0]), then (SET_ IBIASi[8:0] = SET_IBIASi-1[8:0] + BIASINCi[4:0]) 5) Else (SET_IBIASi[8:0] = SET_IBIASi-1[8:0]) The total bias current can be calculated as follows: 6) IBIAS = [SET_IBIASi[8:0] + 16] x 200FA Programming Modulation Current 1) IMODMAX[7:0] = Maximum_Modulation_Current_Value 2) SET_IMODi[8:1] = Initial_Modulation_Current_Value x 1.06 Note: The total modulation laser current is calculated using the SET_IMOD[8:0] DAC value and the SET_TXDE register value. SET_IMOD[8:1] are the bits that can be manually written. SET_IMOD[0] can only be updated using the MODINC register. When implementing modulation compensation, it is recommended to use the MODINC register, which guarantees the fastest modulation current update. 3) MODINCi[4:0] = New_Increment_Value 4) If (SET_IMODi[8:1] P IMODMAX[7:0]), then (SET_ IMODi[8:0] = SET_IMODi-1[8:0] + MODINCi[4:0]) 5) Else (SET_IMODi[8:0] = SET_IMODi-1[8:0]) The following equations give the modulation current (peak-to-peak) seen at the laser when driven differentially. REXTD is the differential load impedance of the laser plus any added series resistance. 6a) TXDE_MD[1:0] = 00, then 0.3mA(SET_IMOD[8 : 0] + 16) 50 x IMOD = 50 + R LD - 0.15mA(SET_IMOD[8 : 3] + 2) 6b) TXDE_MD[1:0] = 01, then 0.3mA(SET_IMOD[8 : 0] + 16) 50 x IMOD = - 0.15mA(SET_IMOD[8 : 4] + 1) 50 + R LD 6c) T XDE_MD[1:0] = 10, then set SET_TXDE[5:0] can be set to any value SET_IMOD[8:4] and 0.3mA(SET_IMOD[8 : 0] + 16) 50 x IMOD = - 0.15mA(SET_TXDE[5:0] + 1) 50 + R LD When SET_TXDE[5:0] is increased, the deemphasis current increases and the overall peak-to-peak modulation current decreases. This effect saturates when SET_TXDE[5:0] = 0.2 x (SET_IMOD[8:0] + 16) - 1, and further increases to SET_TXDE[5:0] do not increase the deemphasis current. 6d) TXDE_MD[1:0] = 11, then IMOD = 0.9 x 0.3mA(SET_IMOD[8 : 0] + 16) x 50 50 + RLD Note: When TXDE_MD[1:0] = 10 and the SET_TXDE register is set by the user, the minimum allowed deemphasis is 3% and the maximum is 10%. These limits are internally set by the MAX3946. Programming Transmit Output Deemphasis 1) TXDE_MD[1:0] = Transmit_Deemphasis_Mode 2) S ET_TXDE[5:0] = Transmit_Deemphasis_Value. If TXDE_MD[1:0] = 00, 01, or 11, the value of SET_TXDE is automatically set by the device and there is no need to enter data to SET_TXDE. For Transmit_Deemphasis_Mode: 00 = deemphasis is fixed at 6% of the modulation amplitude (the device controls the SET_TXDE value), default setting 01 = deemphasis is fixed at 3% of the modulation amplitude (the device controls the SET_TXDE value) 10 = deemphasis is programmed by the SET_TXDE register setting 11 = deemphasis is at its maximum of approximately 9% (the device controls the SET_TXDE value) ______________________________________________________________________________________ 21 MAX3946 Design Procedure MAX3946 1Gbps to 11.3Gbps, SFP+ Laser Driver with Laser Impedance Mismatch Tolerance Programming Pulse-Width Control pulse-width distortion. The code of 1111 corresponds to a balanced state for differential output. The pulse-width distortion is bidirectional around the balanced state (see the Typical Operating Characteristics section). The eye crossing at the Tx output can be adjusted using the SET_PWCTRL register. Table 5 shows these settings. The sign of the number specifies the direction of Applications Information Table 5. Eye-Crossing Settings for SET_PWCTRL Laser Safety and IEC 825 SET_PWCTRL[3:0] PWD SET_PWCTRL[3:0] PWD 1000 -7 0111 8 1001 -6 0110 7 1010 -5 0101 6 1011 -4 0100 5 1100 -3 0011 4 1101 -2 0010 3 1110 -1 0001 2 1111 0 0000 1 Using the MAX3946 laser driver alone does not ensure that a transmitter design is compliant with IEC 825. The entire transmitter circuit and component selections must be considered. Each user must determine the level of fault tolerance required by the application, recognizing that Maxim products are neither designed nor authorized for use as components in systems intended for surgical implant into the body, for applications intended to support or sustain life, or for any other application in which the failure of a Maxim product could create a situation where personal injury or death could occur. Table 6. Register Summary REGISTER FUNCTION/ ADDRESS Transmitter Control Register Address = H0x05 Transmitter Status Register 1 Address = H0x06 REGISTER NAME TXCTRL TXSTAT1 NORMAL MODE SETUP MODE BIT NUMBER/ TYPE BIT NAME DEFAULT VALUE R RW 5 TXDE_MD[1] 0 MSB deemphasis mode R RW 4 TXDE_MD[0] 0 LSB deemphasis mode R RW 3 TXEQ_EN 0 Input equalization 0: disabled, 1: enabled R RW 2 SOFTRES 0 Global digital reset R RW 1 TX_POL 1 Tx polarity 0: inverse, 1: normal R RW 0 TX_EN 1 Tx control 0: disabled, 1: enabled R R 7 (sticky) FST[7] X TX_PORaTX_VCC lowlimit violation R R 6 (sticky) FST[6] X BMON open/shorted to VCC R R 4 (sticky) FST[4] X BMAX current exceeded or open/short to ground R R 3 (sticky) FST[3] X VTOUT+/- common-mode low-limit R R 2 (sticky) FST[2] X VTOUT+/- low-limit violation R R 1 (sticky) FST[1] X BIAS open or shorted to ground R R 0 (sticky) TX_FAULT X Copy of FAULT signal in case POR bits 6 to 1 reset to 0 NOTES 22 1Gbps to 11.3Gbps, SFP+ Laser Driver with Laser Impedance Mismatch Tolerance REGISTER FUNCTION/ ADDRESS Transmitter Status Register 2 Address = H0x07 Bias Current Setting Register Address = H0x08 REGISTER NAME TXSTAT2 SET_IBIAS NORMAL MODE SETUP MODE BIT NUMBER/ TYPE BIT NAME DEFAULT VALUE NOTES R R 3 (sticky) IMODERR X Warning increment result > IMODMAX R R 2 (sticky) IBIASERR X Warning increment result > IBIASMAX R R 1 (sticky) TXED X Tx edge detection R RW 7 SET_IBIAS[8] 0 MSB bias DAC R RW 6 SET_IBIAS[7] 0 R RW 5 SET_IBIAS[6] 0 R RW 4 SET_IBIAS[5] 0 R RW 3 SET_IBIAS[4] 0 R RW 2 SET_IBIAS[3] 0 R RW 1 SET_IBIAS[2] 0 R RW 0 SET_IBIAS[1] 1 7 SET_IBIAS[0] 0 LSB bias DAC MSB modulation DAC Accessible through REG_ADDR = H0x0D Modulation Current Setting Register Address = H0x09 SET_IMOD R RW 7 SET_IMOD[8] 0 R RW 6 SET_IMOD[7] 0 R RW 5 SET_IMOD[6] 0 R RW 4 SET_IMOD[5] 0 R RW 3 SET_IMOD[4] 0 R RW 2 SET_IMOD[3] 1 R RW 1 SET_IMOD[2] 0 R RW 0 SET_IMOD[1] 0 7 SET_IMOD[0] 0 LSB modulation DAC MSB modulation limit Accessible through REG_ADDR = H0x0C Maximum Modulation Current Setting Register Address = H0x0A Maximum Bias Current Setting Register Address = H0x0B IMODMAX IBIASMAX R RW 7 IMODMAX[7] 0 R RW 6 IMODMAX[6] 0 R RW 5 IMODMAX[5] 1 R RW 4 IMODMAX[4] 0 R RW 3 IMODMAX[3] 0 R RW 2 IMODMAX[2] 0 R RW 1 IMODMAX[1] 0 R RW 0 IMODMAX[0] 0 LSB modulation limit R RW 7 IBIASMAX[7] 0 MSB bias limit R RW 6 IBIASMAX[6] 0 R RW 5 IBIASMAX[5] 1 R RW 4 IBIASMAX[4] 0 R RW 3 IBIASMAX[3] 0 R RW 2 IBIASMAX[2] 0 R RW 1 IBIASMAX[1] 0 R RW 0 IBIASMAX[0] 0 LSB bias limit ______________________________________________________________________________________ 23 MAX3946 Table 6. Register Summary (continued) MAX3946 1Gbps to 11.3Gbps, SFP+ Laser Driver with Laser Impedance Mismatch Tolerance Table 6. Register Summary (continued) REGISTER FUNCTION/ ADDRESS Modulation Current Increment Setting Register Address = H0x0C Bias Current Increment Setting Register Address = H0x0D Mode Control Register Address = H0x0E Pulse-Width Control Register Address = H0x0F Deemphasis Control Register Address = H0x10 Equalization Control Register Address = H0x11 REGISTER NAME MODINC BIASINC MODECTRL SET_ PWCTRL SET_TXDE SET_TXEQ NORMAL MODE SETUP MODE BIT NUMBER/ TYPE BIT NAME DEFAULT VALUE NOTES R R 7 SET_IMOD[0] 0 LSB of SET_IMOD DAC register address = H0x09 RW RW 4 MODINC[4] 0 MSB MOD DAC two's complement RW RW 3 MODINC[3] 0 RW RW 2 MODINC[2] 0 RW RW 1 MODINC[1] 0 RW RW 0 MODINC[0] 0 LSB MOD DAC two's complement R R 7 SET_IBIAS[0] 0 LSB of SET_IBIAS DAC register address = H0x08 RW RW 4 BIASINC[4] 0 MSB bias DAC two's complement RW RW 3 BIASINC[3] 0 RW RW 2 BIASINC[2] 0 RW RW 1 BIASINC[1] 0 RW RW 0 BIASINC[0] 0 LSB bias DAC two's complement RW RW 7 MODECTRL[7] 0 MSB mode control RW RW 6 MODECTRL[6] 0 RW RW 5 MODECTRL[5] 0 RW RW 4 MODECTRL[4] 0 RW RW 3 MODECTRL[3] 0 RW RW 2 MODECTRL[2] 0 RW RW 1 MODECTRL[1] 0 RW RW 0 MODECTRL[0] 0 LSB mode control R RW 3 SET_PWCTRL[3] 0 MSB Tx pulse-width control R RW 2 SET_PWCTRL[2] 0 R RW 1 SET_PWCTRL[1] 0 R RW 0 SET_PWCTRL[0] 0 LSB Tx pulse-width control R RW 5 SET_TXDE[5] 0 MSB Tx deemphasis R RW 4 SET_TXDE[4] 0 R RW 3 SET_TXDE[3] 0 R RW 2 SET_TXDE[2] 0 R RW 1 SET_TXDE[1] 0 R RW 0 SET_TXDE[0] 1 R RW 2 SET_TXEQ[2] 0 R RW 1 SET_TXEQ[1] 0 LSB Tx deemphasis Tx equalization 24 1Gbps to 11.3Gbps, SFP+ Laser Driver with Laser Impedance Mismatch Tolerance DEEMPHASIS CONTROL 25I 25I TOUT+ TIN+ TOUT50I CONTROL LOOP 50I TIN- VEET VCCD VEET VCCD VCCD FAULT 7.5kI 75kI CLAMP DISABLE SDA SCL, CSEL 75kI VEET VEET VEET VEET Figure 6. Simplified I/O Structures Layout Considerations The data inputs and outputs are the most critical paths for the device and great care should be taken to minimize discontinuities on these transmission lines between the connector and the IC. Here are some suggestions for maximizing the performance of the IC: * T he data inputs should be wired directly between the module connector and IC without stubs. * T he data transmission lines to the laser should be kept as short as possible and be designed for 50I differential or 25I single-ended characteristic impedance. * A n uninterrupted ground plane should be positioned beneath the high-speed I/Os. * G round path vias should be placed close to the IC and the input/output interfaces to allow a return current path to the IC and the laser. * M aintain 100I differential transmission line impedance into the IC. * U se good high-frequency layout techniques and multilayer boards with an uninterrupted ground plane to minimize EMI and crosstalk. Refer to the schematic and board layers of the MAX3946 Evaluation Kit (MAX3946EVKIT) for more information. Exposed-Pad Package and Thermal Considerations The exposed pad on the 24-pin TQFN provides a very low-thermal resistance path for heat removal from the IC. The pad is also electrical ground on the IC and must be soldered to the circuit board ground for proper thermal and electrical performance. Refer to Application Note 862: HFAN-08.1: Thermal Considerations of QFN and Other Exposed-Paddle Packages for additional information. ______________________________________________________________________________________ 25 MAX3946 VCCT VCCT MAX3946 1Gbps to 11.3Gbps, SFP+ Laser Driver with Laser Impedance Mismatch Tolerance Typical Application Circuit for 10GBASE-LRM HOST BOARD SFP+ OPTICAL TRANSCEIVER SFP CONNECTOR HOST FILTER VCC (3.3V) SUPPLY FILTER VCC VCCD ZDIFF = 100I VCCT 0.1F TOUTTIN+ TIN- FR4 MICROSTRIP UP TO 5.5in TOUT+ 0.1F 10G FP-TOSA BIAS MAX3946 BMAX BMON 3-WIRE INTERFACE FAULT 0.1F R2 R1 SCL SDA CSEL DISABLE VEET VCC SerDes 4.7kI TO 10kI TX_FAULT DS1878 SFP CONTROLLER TX_DISABLE RATE SELECT MODE_DEF1 (SCL) MODE_DEF2 (SDA) SOFTWARE 3-WIRE INTERFACE ADC I2C RPD VCC HOST FILTER VCC (3.3V) ZDIFF = 100I 0.1F FR4 MICROSTRIP UP TO 12in 0.1F 10G LINEAR PIN ROSA SUPPLY FILTER RMON 26 1Gbps to 11.3Gbps, SFP+ Laser Driver with Laser Impedance Mismatch Tolerance SFP CONNECTOR HOST BOARD HOST FILTER SFP+ OPTICAL TRANSCEIVER VCC (3.3V) SUPPLY FILTER VCC VCCD ZDIFF = 100I VCCT 0.1F TOUTTIN+ TIN- FR4 MICROSTRIP UP TO 5.5in TOUT+ 0.1F 10G DFBTOSA BIAS MAX3946 11.3G FP/DFB LDD 0.1F BMAX BMON R2 3-WIRE INTERFACE FAULT R1 SCL SDA CSEL DISABLE VEET VCC SerDes 4.7kI TO 10kI TX_FAULT SOFTWARE 3-WIRE INTERFACE DS1878 SFP CONTROLLER RATE SELECT TX_DISABLE MODE_DEF1 (SCL) MODE_DEF2 (SDA) ADC I2C RPD VCC HOST FILTER VCC (3.3V) SUPPLY FILTER VCCR CAZ VCC 3-WIRE INTERFACE 4.7kI TO 10kI SCL SDA CSEL RPMIN LOS ZDIFF = 100I LOS 0.1F MAX3945 11.3G LAM ROUT+ 0.1F RMON RIN0.1F ROUTFR4 MICROSTRIP UP TO 12in 0.1F RIN+ VEE 10G PIN ROSA ______________________________________________________________________________________ 27 MAX3946 Typical Application Circuit for 10GBASE-LR MAX3946 1Gbps to 11.3Gbps, SFP+ Laser Driver with Laser Impedance Mismatch Tolerance Chip Information PROCESS: SiGe BiPOLAR Package Information For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 24 TQFN-EP T2444+3 21-0139 90-0021 28 1Gbps to 11.3Gbps, SFP+ Laser Driver with Laser Impedance Mismatch Tolerance REVISION NUMBER REVISION DATE 0 3/10 Initial release 5/11 Changed the title from 1.0625Gbps to 1Gbps; changed the edge speed from 20ps to 22ps in the General Description and Features; added the Package Thermal Characteristics section; updated graphs 2, 10, 16, and 17 and replaced graphs 6 and 7 in the Typical Operating Characteristics section; updated the BIAS (requires a 0.1F capacitor to VEET) and CSEL (pulled down to VEET rather than GND) pin descriptions in the Pin Description table; updated Figure 2 SCL and CSEL connections; changed the increment value range from -8 to +7 LSBs to -16 to +15 LSBs in the Bias Current DAC and Modulation Current DAC sections; changed the ground symbols to VEET in Figure 4; updated the Transmitter Control Register (TXCTRL) bit 2 (SOFTRES) description; updated Figure 6, Typical Application Circuit for 10GBASE-LRM, and Typical Application Circuit for 10GBASE-LR; added the land pattern no. to the Package Information table 1 DESCRIPTION PAGES CHANGED -- 1, 2, 7, 8, 10, 11, 12, 14, 17, 25-28 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2011 Maxim Integrated Products 29 Maxim is a registered trademark of Maxim Integrated Products, Inc. MAX3946 Revision History Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Maxim Integrated: MAX3946ETG+ MAX3946ETG+T