PRODUCT PREVIEW 4-MBIT (512 KB x 8) SmartVoltage Flash MEMORY M@ SmartVoltage Technology m@ SRAM-Compatible Write Interface 2.7V(Read-Only), 3.3V or 5V Voc 3.3V, 5V or 12V Vpp @ High-Density Symmetrically-Blocked Architecture M@ High-Performance eight 64-Kbyte Erasable Blocks 85 ns Read Access Time Mm Extended Cycling Capability Mm Enhanced Automated Suspend Options 100,000 Block Erase Cycles Byte Write Suspend to Read 0.8 Million Block Erase Cycles/Chip Block Erase Suspend to Byte Write Block Erase Suspend to Read Mm Low Power Management Deep Power-Down Mode @ Enhanced Data Protection Features Automatic Power Savings Mode Absolute Protection with Vpp=GND Decreases Icc in Static Mode Flexible Block Locking . Block Erase/Byte Write Lockout @ Automated Byte Write and Block Erase during Power Transitions Command User Interface Status Register @ Industry-Standard Packaging 40-Lead TSOP, 44-Lead PSOP m ETOX V Nonvolatile Flash Technology M@ Chip Size Packaging 48-Lead CSP M Not designed or rated as radiation hardened SHARPs LH28FO04SCH-L Flash memory with SmartVoltage technology is a high-density, low-cost, nonvolatile, read/write storage solution for a wide range of applications. Its symmetrically-blocked architecture, flexible voltage and extended cycling provide for highly flexible component suitable for resident flash arrays, SIMMs and memory cards. Its enhanced suspend capabilities provide for an ideal solution for code + data storage applications. For secure code storage applications, such as networking, where code is either directly executed out of flash or downloaded to DRAM, the LH28F004SCH-L offers three levels of protection: absolute protection with Vpp at GND, selective hardware block locking, or flexible software block locking. These alternatives give designers ultimate control of their code security needs. The LH28FO04SCH-L is manufactured on SHARPs 0.4um ETOX V process technology. It comes in industry-standard packages: the 40-lead TSOP and 48-Lead CSP, ideal for board constrained applications, and the rugged 44-lead PSOP. Based on the 28F008SA architecture, the LH28FOO4SCH-L enables quick and easy upgrades for designs demanding the state-of-the-art. *ETOX is a trademark of Intel Corporation.SHARP LH28F004SCH-L SmartVoltage Flash MEMORY @Handle this document carefully for it contains material protected by international copyright law. Any reproduction, full or in part, of this material is prohibited without the express written permission of the company. @When using the products covered herein, please observe the conditions written herein and the precautions outlined in the following paragraphs. In no event shall the company be liable for any damages resulting from failure to strictly adhere to these conditions and precautions. (1) The products covered herein are designed and manufactured for the following application areas. When using the products covered herein for the equipment listed in Paragraph (2), even for the following application areas, be sure to observe the precautions given in Paragraph (2). Never use the products for the equipment listed in Paragraph (3). eOffice electronics elnstrumentation and measuring equipment eMachine tools eAudiovisual equipment eHome appliance Communication equipment other than for trunk lines (2) Those contemplating using the products covered herein for the following equipment which demands high reliability, should first contact a sales representative of the company and then accept responsibility for incorporating into the design fail-safe operation, redundancy, and other appropriate measures for ensuring reliability and safety of the equipment and the overall system. eControl and safety devices for airplanes, trains, automobiles, and other transportation equipment Mainframe computers eTraffic control systems eGas leak detectors and automatic cutoff devices eRescue and security equipment eOther safety devices and safety equipment,etc. (3) Do not use the products covered herein for the following equipment which demands extremely high performance in terms of functionality, reliability, or accuracy. eAerospace equipment eCommunications equipment for trunk lines eControl equipment for the nuclear power industry eMedical equipment related to life support, etc. (4) Please direct all queries and comments regarding the interpretation of the above three Paragraphs to a sales representative of the company. @Please direct all queries regarding the products covered herein to a sales representative of the company. ~ 2 PRODUCT PREVIEWSHARP LH28FO04SCH-L SmartVoltage Flash MEMORY CONTENTS PAGE PAGE 1.0 INTRODUCTION .......... cee cecessssseserseessseesseesseeerens 4 5.0 DESIGN CONSIDERATIONS ............cccceeeseeee 25 1.1 New Features............cccccccsssssssecessneeeeecseseesenessenecs 4 5.1 Three-Line Output Control ooo... cceceseeteesee ees 25 1.2 Product OVErVieW ...........cesccccsseesssseeessneesseseneeees 4 5.2 RY/BY# and Block Erase, Byte Write and Lock-Bit Configuration Polling... eeeseecneceneeeneeseeens 25 2.0 PRINCIPLES OF OPERATION ..............:::cccssereee 9 5.3 Power Supply Decoupling... ecesesseseneeenes 25 2.1 Data Protection 0... ccc ceeescsecseeeteseereeereaees 9 5.4 Vpp Trace on Printed Circuit Boards... 25 5.5 Voc, Vep, RP# Transitions... cece 26 3.0 BUS OPERATION ....0..........c cc ceseeccssersssreressneeeas 10 5.6 Power-Up/Down Protection............cccccccsseeens 26 B.1 REA oo... eeccccseeeceecececcecensususcusesetescenensnsnaeeess 10 5.7 Power Dissipation ............cccsessecceeseesssseeseeeeensanes 26 3.2 Output Disable occ cceeccssessseeeseeesssesseeses 10 B13 StANGDY .... eee ceeeceeeteesssseeeeseesseesseeeeeesesseaessons 10 6.0 ELECTRICAL SPECIFICATIONS..........00.000. 27 3.4 Deep Power-DOwn .........c::cccccssscesscceccssssensenerses 10 6 1 Absolute Maximum RatingS ...........cecccecsseeseees 27 3.5 Read identifier Codes Operation... 11 6.2 Operating Conditions ........ cc ccecesscesseesscessssesseees 27 B.6 WYitC oo. eeceeceecesncceecesnenateseessaeessesseecenteseesuneenss 11 6.2.1 Capacitance 200... ieccceeccseecsesessseseeseseeeseneees 27 . . 6.2.2 AC Input/Output Test Conditions................. 28 4.0 COMMAND DEFINITIONS. ..........0... eee 1 6.2.3 DC Characteristics... ccccccccssessseesteesneees 29 4.1 Read Array COMMANG..........ccescecseessesssseeeseeees 14 6.2.4 AC Characteristics - Read-Only Operations .31 4.2 Read Identifier Codes Command............ccee 14 6.2.5 AC Characteristics - Write Operations.......... 34 4.3 Read Status Register Command...........ccce 14 6.2.6 Alternative CE#-Controlled Writes... 37 4.4 Clear Status Register Commanid............:cecees 14 6.2.7 Reset Operations 20... cece eseseseseereeentaeees 40 4.5 Block Erase COMMANG...........ccccccesseseessrseeseeres 14 6.2.8 Block Erase, Byte Write and Lock-Bit 4.6 Byte Write Command ..........ccessessecessecstseseeeeees 15 Configuration Performance..........ccccseseseees 41 4.7 Block Erase Suspend Commani..........cccccees 15 4.8 Byte Write Suspend Command............cceuseeees 16 7.0 ADDITIONAL INFORMATION .............c:ccccecceeee 42 4.9 Set Block and Master Lock-Bit Commands....... 16 7.1 Ordering Information ...... ce ceeeseeseecsteeseteneenees 42 4.10 Clear Block Lock-Bits Commanid.............c0008 17 PRODUCT PREVIEW 3SHARP LH28FO04SCH-L SmartVoltage Flash MEMORY 1 INTRODUCTION This datasheet contains LH28F004SCH-L specifications. Section 1 provides a flash memory overview. Sections 2, 3, 4, and 5 describe the memory organization and functionality. Section 6 covers electrical specifications. LH28FO04SCH-L Flash memory documentation also includes application notes and design tools which are referenced in Section 7. 1.1 New Features The LH28FO04SCH-L SmartVoltage Flash memory maintains backwards-compatibility with SHARPs - 28FOO8SA. Key enhancements over the 28FOQ08SA include: eSmartVoltage Technology eEnhanced Suspend Capabilities eln-System Block Locking Both devices share a compatible pinout, status register, and. software command set. These- similarities enable a clean upgrade from the 28F008SA to LH28FO04SCH-L. When upgrading, it is important to note the following differences: Because of new feature support, the two devices have different device codes. This allows for software optimization. *Vpp_ has been lowered from 6.5V to 1.5V to support 3.3V and 5V block erase, byte write, and lock-bit configuration operations. Designs that switch Vpp off during read operations should make sure that the Vpp voltage transitions to GND. eTo take advantage of SmartVoltage technology, allow Vpp connection to 3.3V or 5V. 1.2 Product Overview The LH28F004SCH-L is a high-performance 4-Mbit SmartVoitage Flash memory organized as 512 Kbyte of 8 bits. The 512 Kbyte of data is arranged in eight 64-Kbyte blocks which are individually erasable, lockable, and unlockable in-system. The memory map is shown in Figure 6. ws SmartVoltage technology provides a choice of Voc and Vpp combinations, as shown in Table 1, to meet system performance and power expectations. 2.7V Voc consumes approximately one-fifth the power of 5V Vcc. But, 5V Vee provides the highest read performance. Vpp at 3.3V and SV eliminates the need for a separate 12V converter, while Vpp=12V maximizes block erase and byte write performance. In addition to flexible erase and program voltages, the dedicated Vpp pin gives complete data protection when Vep $ Vept x: Table 1. Vec and Vpp Voltage Combinations Offered by SmartVoltage Technology Ver Voltage Vpp Voltage 2.7V") _ 3.3V 3.3V, 5V, 12V 5V 5V, 12V NOTE: 1. Block erase, byte write and lock-bit configuration operations with Voec<3.0V are not supported. Internal Veg and Vpp_ detection Circuitry automatically configures the device for optimized read and write operations. A Command User Interface (CUI) serves as the interface between the system processor and internal operation of the device. A valid command sequence written to the CUI initiates device automation. An internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for block erase, byte write, and lock-bit configuration operations. A block erase operation erases one of the devices 64-Kbyte blocks typically within 1 second (5V Veco, 12V Vpp) independent of other blocks. Each block can be independently erased 100,000 times (0.8 million block erases per device). Block erase suspend mode allows system software to suspend block erase to read or write data from any other block. Writing memory data is performed in byte increments typically within 6 us (5V Voc, 12V Vpp). Byte write suspend mode enables the system to read data or. execute code from any other flash memory array location. PRODUCT PREVIEWSHARP Individual block locking uses a combination of bits, sixteen block lock-bits and a master lock-bit, to lock and unlock blocks. Block lock-bits gate block erase and byte write operations, while the master lock-bit gates block lock-bit modification. Lock-bit configuration operations (Set Block Lock-Bit, Set Master Lock-Bit, and Clear Block Lock-Bits commands) set and cleared lock-bits. The status register indicates when the WSMs block erase, byte write, or lock-bit configuration operation is finished. The RY/BY# output gives an additional indicator of WSM activity by providing both a hardware signal of status (versus software polling) and status masking (interrupt masking for background block erase, for example). Status polling using RY/BY# minimizes both CPU overhead and system power consumption. When low, RY/BY# indicates that the WSM is performing a block erase, byte write, or lock-bit configuration. RY/BY#-high indicates that the WSM is ready for a new command, block erase is suspended (and byte write is inactive), byte write is suspended, or the device is in deep power-down mode. The access time is 85ns (tayay) Over the commercial temperature range (-25C to +85C) and Vo, supply LH28FO004SCH-L SmartVoltage Flash MEMORY voltage range of 4.75V-5.25V. At lower Voc voltages, the access times are 90ns or 120ns (4.5V-5.5V), 120ns or 150ns (3.0V-3.6V) and 150ns or 170ns (2.7V-3.6V). The Automatic Power Savings (APS) feature substantially reduces active current when the device is in static mode (addresses not switching). In APS mode, the typical Icg_ current is 1 MA at 5V Voo. When CE# and RP# pins are at Voc, the log CMOS standby mode is enabled. When the RP# pin is at GND, deep power-down mode is enabled which minimizes power consumption and provides write protection during reset. A reset time (toyqy) is required from RP# switching high until outputs are valid. Likewise, the device has a wake time (tey,) from RP#-high until writes to the CUI are recognized. With RP# at GND, the WSM is reset and the status register is cleared. The device is available in 40-lead TSOP (Thin Smal! Outline Package, 1.2 mm thick), 44-lead PSOP (Plastic Small Outline Package) and 48-lead CSP (Chip Size Package). Pinouts are shown in Figures 2, 3,4 and 5. Output Buffer DQo-DQ, VO Logic Identifier Register Output Multiplexer Status Register Command Register Data Comparator RY/BY# Input Buffer Deodder Y Gating Ar Aig Write State Vep Machine ProgranvErase vi Switch Xx Decoder Vee << and Address Latch Address Counter Figure 1. Block Diagram PRODUCT PREVIEW 5SHARP LH28FO004SCH-L SmartVoltage Flash MEMORY Table 2. Pin Descriptions Type Name and Function INPUT ADDRESS INPUTS: Inputs for addresses during read and write operations. Addresses are internally latched during a write cycle. INPUT/ OUTPUT DATA INPUT/OUTPUTS: inputs data and commands during CUI write cycles; outputs data during memory array, status register, and identifier code read cycles. Data pins float to high-impedance when the chip is deselected or outputs are disabled. Data is internally latched during a write cycle. CE# INPUT CHIP ENABLE: Activates the devices control logic, input buffers, decoders, and sense amplifiers. CE#-high deselects the device and reduces power consumption to standby levels. RP# INPUT RESET/DEEP POWER-DOWN: Puts the device in deep power-down mode and resets internal automation. RP#-high enables normal operation. When driven low, RP# inhibits write operations which provides data protection during power transitions. Exit from deep power-down sets the device to read array mode. RP# at Vii, enables setting of the master lock-bit and enables configuration of block lock-bits when the master lock-bit is set. RP#=V/,4,, overrides block lock-bits thereby enabling block erase and byte write operations to locked memory blocks. Block erase, byte write, or lock-bit configuration with V).<RP#<V.4, produce spurious results and should not be attempted. OE# INPUT OUTPUT ENABLE: Gates the devices outputs during a read cycle. WE# INPUT WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data are latched on the rising edge of the WE# pulse. RY/BY# OUTPUT READY/BUSY#: Indicates the status of the internal WSM. When low, the WSM is performing an internal operation (block erase, byte write, or lock-bit configuration). RY/BY#-high indicates that the WSM is ready for new commands, block erase is suspended, and byte write is inactive, byte write is suspended, or the device is in deep power-down mode. RY/BY# is always active and does not float when the chip is deselected or data outputs are disabled. SUPPLY BLOCK ERASE, BYTE WRITE, LOCK-BIT CONFIGURATION POWER SUPPLY: For erasing array blocks, writing bytes, or configuring lock-bits. With VppsVpp;, memory contents cannot be altered. Block erase, byte write, and lock-bit configuration with an invalid Vpp (see DC Characteristics) produce spurious results and should not be attempted. SUPPLY DEVICE POWER SUPPLY: Internal detection configures the device for 2.7V, 3.3V or 5V operation. To switch from one voltage to another, ramp Voc down to GND and then ramp Voc to the new voltage. Do not float any power pins. With VecSV_ Ko, all write attempts to the flash memory are inhibited. Device operations at invalid Vcc voltage (see DC Characteristics) produce spurious results and should not be attempted. Block erase, byte write and lock-bit configuration operations with V--<3.0V are not supported. GND SUPPLY GROUND: Do not float any ground pins. NC NO CONNECT: Lead is not internal connected; it may be driven or floated. PRODUCT PREVIEWSHARP LH28F004SCH-L SmartVoltage Flash MEMORY NC C1 40 = ~ NC Ai C2 C) 39 == NC Ay Coo )3 38 |=_SCWE# Aig Com4 37 E= ~=SsOCOE# Ais Cos 36 E ~=O?RYI/BY# Ass co 6 35 C4 DQ? Ay Co 7 . 34 _-DG, a LH28FO004SCHT-L 33 == 00. ce# com 9 40-LEAD TSOP 32 === ~0a, Veo Cou 10 31 Co ~Vec Vee esa STANDARD PINOUT 30 a an RP# Coy 12 10mm x 20mm 29 =_=GND Ay, O13 23 ~1DQ; Avo coo 14 TOP VIEW 27 [ ~DA Ag [wm 15 26F 0a, A, C16 25 J DQ A, Co i7 24 Ay A, Co 18 23 _ A, As Cu 19 22 Ap A, CO 20 21 A; Figure 2. TSOP(Normai Bend) 40-Lead Pinout NC [ 40 {oo NC NC 39 . C) 22 Ass WE# Co 38 3E= 5 Ay O&# 7 37 47 As RY/BY# = 36 5 Ais DQ, CT 35 6 Ana DQ, ( 34 . 7S Ag Da, 33 LH28FO004SCHR-L gE Ap DQ, 32 40-LEAD TSOP 9 (== CE# Veo 31 10 =" Vec GND C 30 STANDARD PINOUT 11 = ~Vpp GNO C= 29 10mm x 20mm 12(= ~pP# DQ; I 28 13 Ay, DQ, 27 TOP VIEW 14-4 Avo pa, C 26 15(==7 Ay DQ) (=) 25 16-7 Ag A, [J 24 7] A A; Co 23 18[=7 As A, Co 22 19[=7 As Ag; Coo 21 20 [== Ay Figure 3. TSOP(Reverse Bend) 40-Lead Pinout PRODUCT PREVIEW 7SHARP LH28F004SCH-L SmartVoitage Flash MEMORY Vpp COAT O 44 Tr RP# CUT 2 43 0m Aiz C3 42 [To Aigo COml4 41 [rr Ag cor5 40 = Ag Ci6 39 FT A7 C7 38 [oI Ag Co 8 37 =o As Cm9 36 [7 Ag com 10 LH28FO04SCHN-L35 =o NC coi11 44-LEAD PSOP 34> NC codi2 0.525"x 1.110" 33 =m A3 0113 TOP VIEW 32 cor Ao om14 31 Ay coms 30 FT Ao coni6 29 = DQo 17 28 TO DQ; o7 18 27 co DQ. 7119 26 oOo DQ3 C1) 20 . 25 GND Cr) 21 24 CIT GND CT 22 23 M1 Vee CE# A12 Ai3 Ai4 Ais A16 Ai7 Ais NC NC NC NC Nc WE# OE# RY/BY# DQ7 DQs DQs DQ4 Voc Figure 4. PSOP 44-Lead Pinout > OOOO @- OOOO SOOOO- GEOROROROROE @O@OOO&@- CRORORORORGE @OOOee- a @@@@ LH28FO004SCHB-L 48-LEAD CSP STANDARD PINOUT 8mm x 6mm TOP VIEW Figure 5. TSOP 48-Lead Pinout PRODUCT PREVIEWSHARP 2 PRINCIPLES OF OPERATION The LH28FO04SCH-L SmartVoltage Flash memory includes an on-chip WSM to manage block erase, byte write, and lock-bit configuration functions. It allows for: 100% TTL-level contro! inputs, fixed power supplies during block erasure, byte write, and lock-bit configuration, and minimal processor overhead with RAM-Like interface timings. Alter initial device power-up or return from deep power-down mode (see Bus Operations), the device defaults to read array mode. Manipulation of external memory contro! pins allow array read, standby, and output disable operations. Status register and identifier codes can be accessed through the CUI independent of the Vpp voltage. High voltage On Vpp enables successful block erasure, byte writing, and lock-bit configuration. Ail functions associated with altering memory contentsblock erase, byte write, Lock-bit configuration, status, and identifier codes-are accessed via the CUI and verified through the status register. Commands are written using standard microprocessor write timings. The CUI contents serve as input to the WSM, which controls the block erase, byte write, and fock-bit configuration. The internal algorithms are regulated by the WSM, including pulse repetition, internal verification, and margining of data. Addresses and data are internally latch during write cycles. Writing the appropriate command outputs array data, accesses the identifier codes, or outputs Status register data. Interface software that initiates and polls progress of block erase, byte write, and lock-bit configuration can be stored in any block. This code is copied to and executed from system RAM during flash memory updates. After successful completion, reads are again possible via the Read Array command. Block erase suspend allows system software to suspend a block erase to read or write data from any other PRODUCT PREVIEW LH28FO04SCH-L SmartVoltage Flash MEMORY biock. Byte write suspend allows system software to suspend a byte write to read data from any other flash memory array location. mere 64-Kbyte Block 7 70000 ort 64-Kbyte Block 6 60000 SFP 64-Kbyte Block 5 50000 sneer 64-Kbyte Block 4 40000 SFFFF 64-Kbyte Block 3 30000 arerr 64-Kbyte Block 2 20000 FFFF 64-Kbyte Block 1 10000 OFFER 64-Kbyte Block 0 eoce0 Figure 6. Memory Map 2.1 Data Protection Depending on the application, the system designer may choose to make the Vpp power supply switchable (available only when memory block erases, byte writes, or lock-bit configurations are required) or hardwired to Vppyy/o/3. The device accommodates either design practice and encourages optimization of the processor-memory interface. When VoepSVppix, memory contents cannot be aitered. The CUI, with two-step block erase, byte write, or lock-bit configuration command sequences, provides protection from unwanted operations even when high voltage is applied to Vpp. All write functions are disabled when Vcc is below the write lockout voltage Vixg or when RP# is at V,. The devices block locking capability provides additional protection from inadvertent code or data alteration by gating erase and byte write operations.SHARP LH28FO04SCH-L SmartVoltage Flash MEMORY 3 BUS OPERATION The local CPU reads and writes flash memory in-system. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles. 3.1 Read Information can be read from any block, identifier codes, or status register independent of the Vpp voltage. RP# can be at either V,., or Vin. The first task is to write the appropriate read mode command (Read Array, Read Identifier Codes, or Read Status Register) to the CUI. Upon initial device power-up or after exit from deep power-down mode, the device automatically resets to read array mode. Four control pins dictate the data flow in and out of the component: CE#, OE#, WE#, and RP#. CE# and OE&# must be driven active to obtain data at the outputs. CE# is the device selection control, and when active enables the selected memory device. OE# is the data output (DQ9-DQ,) control and when active drives the selected memory data onto the I/O bus. WE# must be at V;,, and RP# must be at Vj, or Vun- Figure 18 illustrates a read cycle. 3.2 Output Disable With OE# at a logic-high level (Vj), the device outputs are disabled. Output pins DQ)-DQ; are placed in a high-impedance state. 3.3 Standby CE# at a logic-high level (Vj,,) places the device in Standby mode which substantially reduces device power consumption. DQ9-DQ, outputs are placed in a high-impedance state independent of OE#. If deselected during block erase, byte write, or lock-bit 10 configuration, the device continues functioning, and consuming active power until the operation completes. 3.4 Deep Power-Down RP# at V,, initiates the deep power-down mode. In read modes, RP#-low deselects the memory, places output drivers in a high-impedance state and turns off all internal circuits. RP# must be held low for a minimum of 100 ns. Time tpyoy is required after return from power-down until initial memory access outputs are valid. After this wake-up interval, normal operation is restored. The CUI is reset to read array mode and status register is set to 80H. During block erase, byte write, or lock-bit configuration modes, RP#-low will abort the operation. RY/BY# remains low until the reset operation is complete. Memory contents being altered are no longer valid; the data may be partially erased or written. Time toyy, is required after RP# goes to logic-high (V\,) before another command can be written. As with any automated device, it is important to assert RP# during system reset. When the system comes out of reset, it expects to read from the flash memory. Automated flash memories provide status information when accessed during block erase, byte write, or lock-bit configuration modes. If a CPU reset occurs with no flash memory reset, proper CPU initialization may not occur because the flash memory may be providing status information instead of array data. SHARPs flash memories allow proper CPU initialization following a system reset through the use of the RP# input. In this application, RP# is controlled by the same RESET# signal that resets the system CPU. PRODUCT PREVIEWSHARP 3.5 Read Identifier Codes Operation The read identifier codes operation outputs the manufacturer code, device code, block lock configuration codes for each block, and the master lock configuration code (see Figure 7). Using the manufacturer and device codes, the system CPU can automatically match the device with its proper algorithms. The block lock and master lock configuration codes identify locked and unlocked blocks and master lock-bit setting. 7FFFFE Ess Reserved for 70004, .. Future Implementation 70003} 70002 Block 7 Lock Configuration Code 70001 Reserved for Po Buture implementation 70000 as a Block 7 we : (Blocks 2 through:6) 1FFFFE va Reserved for 100044 = Future Implementation 10003F 10002 Block 1 Lock Configuration Code 10001] = Reserved for eo Future Implementation 10000F : wesc: Block 1 OFFFF Reserved for OEE Future Implementation 00004] eee 00003 Master Lock Configuration Code 00002 Block 0 Lock Configuration Code 00001 Device Code 90000 Manufacturer Code = Biggk 0 Figure 7. Device Identifier Code Memory Map PRODUCT PREVIEW LH28FO004SCH-L SmartVoitage Flash MEMORY 3.6 Write Writing commands to the CUI enable reading of device data and identifier codes. They also control inspection and clearing of the status register. When Vec=Vecaaa aNd = Vep=VppH1ja3, the = CUI additionally controls block erasure, byte write, and lock-bit configuration. The Block Erase command requires appropriate command data and an address within the block to be erased. The Byte Write command requires the command and address of the location to be written. Set Master and Block Lock-Bit commands require the command and address within the device (Master Lock) or block within the device (Block Lock) to be locked. The Clear Block Lock-Bits command requires the command and address within the device. The CUil does not occupy an addressable memory location. It is written when WE# and CE# are active. The address and data needed to execute a command are latched on the rising edge of WE# or CE# (whichever goes high first). Standard microprocessor write timings are used. Figures 19 and 20 illustrate WE# and CE#-controlled write operations. 4 COMMAND DEFINITIONS When the Vpp voltage < Vpp.x, Read operations from the status register, identifier codes, or blocks are enabied. Placing Vppy4/2;3 ON Vpp enables successful block erase, byte write and lock-bit configuration operations. Device operations are selected by writing specific commands into the CUl. Table 4 defines these commands. ilSHARP LH28F004SCH-L SmartVolitage Flash MEMORY Table 3. Bus Operations Mode Notes RP# CE# | OE# | WE# | Address | Vpp DQ,7 | RY/BY# Read 1,2,3,8 | Viayor | Vip Vit Vie X X Dout X Via Output Disable 3 Vin or Vit Vin Vin x x High Z Xx Vu Standby 3 Vin OF) Vig xX X X X High 2 X Vii Deep Power-Down 4 Vi X X Xx x xX High Z Vou Read Identifier Codes Vin or Vit Vir Vin See x Note 5 Vou Vig Figure 7 Write 3,6,7,8 Vin or Vie Vin Vit X Xx Din Xx Vis NOTES: 1. Refer to DC Characteristics. When Vpp<Vpp; x, Memory contents can be read, but not altered. 2. X can be V), or Vj, for control pins and addresses, and Vpp_ OF VepH4/2/3 for Vpp. See DC Characteristics for Veeck 4d Vppy4/9/3 voltages. 3. RY/BY# is Vo, when the WSM is executing internal block erase, byte write, or lock-bit configuration algorithms. It is Voy during when the WSM is not busy, in block erase suspend mode (with byte write inactive), byte write suspend mode, or deep power-down mode. DO RP# at GND+0.2V ensures the lowest deep power-down current. See Section 4.2 for read identifier code data. Command writes involving block erase, write, or lock-bit configuration are reliably executed when Vpp=Vppy44/9/3 and Voc=Vec2/3/4. Block erase, byte write, or lock-bit configuration with Voc<3.0V or Viy<RP#<Vi4, produce spurious results and should not be attempted. . 7. Refer to Table 4 for valid D,, during a write operation. 8. Dont use the timing both OE# and WE# are V\,. 12 PRODUCT PREVIEWSHARP LH28FO004SCH-L SmartVoltage Flash MEMORY Table 4. Command Definitions) Bus Cycles First Bus Cycle Second Bus Cycle Command | Req'd. |Notes! Oper() | Addr(2) | Data(3) | Oper) | Addr(2) | Data(3) Read Array/Reset 1 Write X FFH Read Identifier Codes 22 4 Write x 90H Read IA iD Read Status Register 2 Write X 70H Read Xx SRD Clear Status Register : 1 Write x 50H Block Erase 2 5 Write BA 20H Write BA DOH Byte Write 2 5,6 Write WA 40H Write WA WD or 10H Block Erase and Byte Write . 1 5 Write X BOH Suspend | Block Erase and Byte Write : 1 5 Write X DOH Resume Set Block Lock-Bit 2 7 Write BA 60H Write BA 01H Set Master Lock-Bit 2 | 7 Write Xx 60H Write Xx F1H Clear Block Lock-Bits 2 | 8 Write xX 60H Write x DOH NOTES: 1. 2. BUS operations are defined in Table 3. X=Any valid address within the device. |A=Identifier Code Address: see Figure 7. BA=Address within the block being erased or locked. WA=Address of memory location to be written. SRD=Daia read from status register. See Tabie 7 for a description of the status register bits. WD=Data to be written at location WA. Data is latched on the rising edge of WE# or CE# (whichever goes high first). ID=Data read from identifier codes. . Following the Read Identifier Codes command, read operations access manufacturer, device, block lock, and master lock codes. See Section 4.2 for read identifier code data. . If the block is locked, RP# must be at V4 to enable block erase or byte write operations. Attempts to issue a block erase or byte write to a locked block while RP# is V)4. . Either 40H or 10H are recognized by the WSM as the byte write setup. . If the master lock-bit is set, RP# must be at Vi, to set a block lock-bit. RP# must be at V4, to set the master lock-bit. If the master lock-bit is not set, a block lock-bit can be set while RP# is Vj. If the master lock-bit is set, RP# must be at Vi to clear block lock-bits. The clear block lock-bits operation simultaneously clears all block lock-bits. If the master lock-bit is not set, the Clear Block Lock-Bits command can be done while RP# is Vj44,. Commands other than those shown above are reserved by SHARP for future device implementations and should not be used. - PRODUCT PREVIEW 13SHARP LH28F004SCH-L SmartVoitage Flash MEMORY 4.1 Read Array Command Upon initial device power-up and after exit from deep power-down mode, the device defaults to read array mode. This operation is also initiated by writing the Read Array command. The device remains enabled for reads until another command is written. Once the internal WSM has started a block erase, byte write or lock-bit configuration, the device will not recognize the Read Array command until the WSM completes its operation unless the WSM is suspended via an Erase Suspend or Byte Write Suspend command. The Read Array command functions independently of the Vpp voltage and RP# can be Viy or Vi. 4.2 Read Identifier Codes Command The identifier code operation is initiated by writing the Read Identifier Codes command. Following the command write, read cycles from addresses shown in Figure 7 retrieve the manufacturer, device, block lock configuration and master lock configuration codes (see Table 5 for identifier code values). To terminate the operation, write another valid commana. Like the Read Array command, the Read Identifier Codes command functions independently of the Vpp voltage and RP# can be V,, or Vuy. Following the Read Identifier Codes command, the following information can be read: Table 5. Identifier Codes Code Address Data Manufacture Code 00000 Device Code 00001 Block Lock Configuration | x0002) Block is Unlocked DQ ,=0 Block is Locked DQp=1 Reserved for Future Use Master Lock Configuration 00003 eDevice is Unlocked DQ)=0 eDevice is Locked DQo=1 *Reserved for Future Use DQ,_7 NOTE: 1. X selects the specific block lock configuration code to be read. See Figure 7 for the device identifier code memory map. 14 4.3 Read Status Register Command The status register may be read to determine when a block erase, byte write, or lock-bit configuration is: complete and whether the operation completed successfully. It may be read at any time by writing the Read Status Register command. After writing this command, all subsequent read operations output data from the status register until another valid command is written. The status register contents are latched on the falling edge of OE# or CE#, whichever occurs. OE# or CE# must toggle to Vj), before further reads to update the status register latch. The Read Status Register command functions independently of the Vpp voltage. RP# can be Vj or Vit. 4.4 Clear Status Register Command Status register bits SR.5, SR.4, SR.3, and SR.1 are set to "1"s by the WSM and can only be reset by the Clear Status Register command. These bits indicate various failure conditions (See Table 7). By allowing system software to reset these bits, several operations (such as cumulatively erasing or locking multiple blocks or writing several bytes in sequence) may be performed. The status register may be polled to determine if an error occurre during the sequence. To clear the status register, the Clear Status Register command (50H) is written. It functions independently of the applied Vpp Voitage. RP# can be Vi4 or Vin. This command is not functional during block erase or byte write suspend modes. 4.5 Block Erase Command Erase is executed one block at a time and initiated by a two-cycie command. A block erase setup is first written, followed by an block erase confirm. This command sequence requires appropriate sequencing and an address within the block to be erased (erase changes all block data to FFH). Block preconditioning, erase, and verify are handled internally by the WSM (invisible to the system). After the two-cycle block erase sequence is written, the device automatically outputs status register data when read (see Figure 8). The CPU can detect block erase completion by anaiyzing the output data of the RY/BY# pin or status register bit SR.7. PRODUCT PREVIEWSHARP When the block erase is complete, status register bit SR.5 should be checked. If a block erase error is detected, the status register should be cleared before system software attempts corrective actions. The CUI remains in read status register mode until a new command is issued. This two-step command sequence of set-up followed by execution ensures that block contents are not accidentally erased. An invalid Block Erase command sequence will result in both status register bits SR.4 and SR.5 being set to "1". Also, reliable block erasure can only occur when Voc=Veco234 and Vpp=Vppy4/7/3- In the absence of this high voltage, block contents are protected against erasure. If block erase is attempted while VepsVpp, x, SR.3 and SR.5 will be set to "1". Successful block erase requires that the corresponding block lock-bit be cleared or, if set, that RP#=V.4,. If block erase is attempted when the corresponding block lock-bit is set and RP#=VjW, SR.1 and SR.5 will be set to "1". Block erase operations with Vj4y<RP#<V.4, produce spurious results and should not be attempted. 4.6 Byte Write Command Byte write is executed by a two-cycle command sequence. Byte write setup (standard 40H or alternate 10H) is written, followed by a second write that specifies the address and data (latched on the rising edge of WE#). The WSM then takes over, controlling the byte write and write verify algorithms internally. After the byte write sequence is written, the device automaticaily outputs status register data when read (see Figure 9). The CPU can detect the compietion of the byte write event by analyzing the RY/BY# pin or status register bit SR.7. When byte write is complete, status register bit SR.4 should be checked. If byte write error is detected, the status register should be cleared. The internal WSM verify only detects errors for "1"s that do not successfully write to "O"s. The CUI remains in read status register mode until it receives another command. Reliable byte writes can only occur when Voc=Vec2/a/4 and Vpp=VppyH1/2/3: In the absence of this high voltage, memory contents are protected against byte writes. If byte write is attempted while VppSVpp,x, Status register bits SR.3 and SR.4 will be PRODUCT PREVIEW LH28FO04SCH-L SmartVoltage Flash MEMORY set to "1". Successful byte write requires that the corresponding block lock-bit be cleared or, if set, that RP#=Vii. If byte write is attempted when the corresponding block lock-bit is set and RP#=Vj,,, SR.1 and SR.4 will be set to "1". Byte write operations with Vj4<RP#<V,,, produce spurious results and should not be attempted. 4.7 Block Erase Suspend Command The Block Erase Suspend command allows block-erase interruption to read or byte-write data in another block of memory. Once the biock-erase process starts, writing the Block Erase Suspend command requests that the WSM suspend the block erase sequence at a predetermined point in the algorithm. The device outputs status register data when read after the Block Erase Suspend command is written. Polling status register bits SR.7 and SR.6 can determine when the biock erase operation has been suspended (both will be set to "1"). RY/BY# will also transition to Voy. Specification twupys defines the block erase suspend latency. At this point, a Read Array command can be written to read data from blocks other than that which is suspended. A Byte Write command sequence can also be issued during erase suspend to program data in other blocks. Using the Byte Write Suspend command (see Section 4.8), a byte write operation can also be suspended. During a byte write operation with block erase suspended, status register bit SR.7 will return to O" and the RY/BY# output will transition to Vo.. However, SR.6 will remain "1" to indicate block erase suspend status. The only other valid commands while block erase is suspended are Read Status Register and Block Erase Resume. After a Block Erase Resume command is written to the flash memory, the WSM will continue the block erase process. Status register bits SR.6 and SR.7 will automatically clear and RY/BY# will return to Vo,. After the Erase Resume command is written, the device automatically outputs status register data when read (see Figure 10). Vop must remain at Vppry4/9/3 (the same Vpp level. used for block erase) while block erase is suspended. RP# must also remain at V\,4 or Vij (the same RP# level used for block erase). Block erase cannot resume until byte write operations initiated during block erase suspend have completed. he uiSHARP LH28FO004SCH-L SmartVoitage Flash MEMORY 4.8 Byte Write Suspend Command The Byte Write Suspend command allows byte write interruption to read data in other flash memory locations. Once the byte write process starts, writing the Byte Write Suspend command requests that the WSM suspend the byte write sequence at a predetermined point in the algorithm. The device continues to output status register data when read after the Byte Write Suspend command is written. Polling status register bits SR.7 and SR.2 can determine when the byte write operation has been suspended (both will be set to "1"). RY/BY# will also transition to Voy. Specification twury, defines the byte write suspend latency. At this point, a Read Array command can be written to read data from locations other than that which is suspended. The only other valid commands while byte write is suspended are Read Status Register and Byte Write Resume. After Byte Write Resume command is written to the flash memory, the WSM will continue the byte write process. Status register bits SR.2 and SR.7 will automatically clear and RY/BY# will return to Vo,. After the Byte Write Resume command is written, the device automatically outputs status register data when read (see Figure 11). Vpp must remain at Vppy1/9/3 (the Same Vpp level used for byte write) while in byte write suspend mode. RP# must also remain at V4 or Vu (the same RP# level used for byte write). 4.9 Set Block and Master Lock-Bit Commands A flexible block locking and unlocking scheme is enabled via a combination of block lock-bits and a master lock-bit. The block lock-bits gate program and erase operations while the master lock-bit gates block-lock bit modification. With the master lock-bit not set, individual block lock-bits can be set using the Set Block Lock-Bit command. The Set Master Lock-Bit command, in conjunction with RP#=Vi4,4, sets the master lock-bit. After the master lock-bit is set, subsequent setting of block lock-bits requires both the Set Block Lock-Bit command and V,4, on 16 the RP# pin. See Table 6 for a summary of hardware and software write protection options. Set block lock-bit and master lock-bit are executed by a two-cycle command sequence. The set block or master lock-bit setup along with appropriate block or device address is written followed by either the set block lock-bit confirm (and an address within the block to be locked) or the set master lock-bit confirm (and any device address). The WSM then controls the set lock-bit algorithm. After the sequence is written, the device automatically outputs status register data when read (see Figure 12). The CPU can detect the completion of the set lock-bit event by analyzing the RY/BY# pin output or status register bit SR.7. When the set lock-bit operation is complete, status register bit SR.4 should be checked. If an error is detected, the status register should be cleared. The CUI will remain in read status register mode until a new command is issued. This two-step sequence of set-up followed by execution ensures that lock-bits are not accidentally set. An invalid Set Block or Master Lock-Bit command will result in status register bits SR.4 and SR.5 being set to "1". Aiso, reliable operations occur absence of this high voltage, lock-bit contents are protected against alteration. A successful set block lock-bit operation requires that the master lock-bit be cleared or, if the master lock-bit is set, that RP#=V,,,,. If it is attempted with the master lock-bit set and RP#=V)4, SR.1 and SR.4 will be set to 1" and the operation will fail. Set block lock-bit operations while V,4<RP#<Viij, produce spurious results and should not be attempted. A successful set master lock-bit operation requires that RP#=ViU,. If it is attempted with RP#=V,,, SR.1 and SR.4 will be set to "1" and the operation will fail. Set master lock-bit operations with V,4<RP#<V.), produce spurious results and should not be attempted. PRODUCT PREVIEWSHARP 4.10 Clear Block Lock-Bits Command All set block lock-bits are cleared in parallel via the Clear Block Lock-Bits command. With the master lock-bit not set, block lock-bits can be cleared using only the Clear Block Lock-Bits command. If the master lock-bit is set, clearing block lock-bits requires both the Clear Block Lock-Bits command and V,, on the RP# pin. See Table 6 for a summary of hardware and software write protection options. Clear block lock-bits operation is executed by a two-cycle command sequence. A clear block lock-bits setup is first written. After the command is written, the device automatically outputs status register data when read (see Figure 13). The CPU can detect completion of the clear block lock-bits event by analyzing the RY/BY# Pin output or status register bit SR.7. When the operation is complete, status register bit SR.5 should be checked. If a clear block lock-bit error is detected, the status register should be cleared. The CU will remain in read status register mode until another.command is issued. LH28FO04SCH-L SmartVoltage Flash MEMORY This two-step sequence of set-up followed by execution ensures that block lock-bits are not accidentally cleared. An invalid Clear Block Lock-Bits command sequence will result in status register bits SR.4 and SR.5 being set to "1". Also, a reliable clear block lock-bits operation can only occur when Voc=Veca2a4 and Vep=VppH1/2/3: lf a clear block lock-bits operation is attempted while VppsVpp, x, SR.3 and SR.5 will be set to "1". In the absence of this high voltage, the block lock-bits content are protected against alteration. A successful clear block lock-bits operation requires that the master lock-bit is not set or, if the master lock-bit is set, that RP#=V,,,. lf it is attempted with the master lock-bit set and RP#=Vi4, SR.1 and SR.5 will be set to "1" and the operation will fail. A clear block lock-bits operation with Viy<RP#<Vi, produce spurious results and should not be attempted. If a clear block lock-bits operation is aborted due to Vpp or Veg transitioning out of valid range or RP# active transition, block lock-bit values are left in an undetermined state. A repeat of clear block lock-bits is required to initialize block lock-bit contents to known values. Once the master lock-bit is set, it cannot be cleared. Table 6. Write Protection Alternatives Master Block | Operation Lock-Bit | Lock-Bit RP# Effect Block Erase or 0 Vin or Ving | Block Erase and Byte Write Enabled Byte Write Xx 1 Vig Block is Locked. Block Erase and Byte Write Disabled Via Block Lock-Bit Override. Block Erase and Byte Write Enabled Set Block 0 X Vin Or Ving | Set Block Lock-Bit Enabled Lock-Bit 1 x Vig Master Lock-Bit is Set. Set Block Lock-Bit Disabled Vig Master Lock-Bit Override. Set Block Lock-Bit Enabled Set Master X x Vig Set Master Lock-Bit Disabled Lock-Bit Vio Set Master Lock-Bit Enabled Clear Block 0 x Vin Or Vi | Clear Block Lock-Bits Enabled Lock-Bits 1 Xx Vow Master Lock-Bit is Set. Clear Block Lock-Bits Disabled Van Master Lock-Bit Override. Clear Block Lock-Bits Enabled PRODUCT PREVIEW 17SHARP LH28FO004SCH-L SmartVoltage Flash MEMORY Table 7. Status Register Definition L_wsms {| ESS | ECLBS | BWSLBS | vPPS | BWSS [ DPS | R 7 6 5 4 3 2 1 0 NOTES: SR.7 = WRITE STATE MACHINE STATUS 1 = Ready 0 = Busy SR.6 = ERASE SUSPEND STATUS 1 = Block Erase Suspended O = Block Erase in Progress/Completed SR.5 = ERASE AND CLEAR LOCK-BITS STATUS 1 = Error in Block Erasure or Clear Lock-Bits O = Successful Block Erase or Clear Lock-Bits SR.4 = BYTE WRITE AND SET LOCK-BIT STATUS 1 = Error in Byte Write or Set Master/Block Lock-Bit O = Successful Byte Write or Set Master/Block Lock-Bit SR.3 = Vpp STATUS 1 = Vpp Low Detect, Operation Abort ) = Voep OK SR.2 = BYTE WRITE SUSPEND STATUS 1 = Byte Write Suspended 0 = Byte Write in Progress/Completed SR.1 = DEVICE PROTECT STATUS 1 = Master Lock-Bit, Block Lock-Bit and/or RP# Lock Detected, Operation Abort 0 = Unlock SR.0 = RESERVED FOR FUTURE ENHANCEMENTS Check RY/BY# or SR.7 to determine biock erase, byte write, or jock-bit configuration completion. SR.6-0 are invalid while SR.7="0". lf both SR.5 and SR.4 are "1"s after a block erase or lock-bit configuration attempt, an improper command sequence was entered. SR.3 does not provide a continuous indication of Vpp level. The WSM interrogates and indicates the Vpp level only after Block Erase, Byte Write, Set Block/Master Lock-Bit, or Clear Block Lock-Bits command sequences. SR.3 is not guaranteed to reports accurate feedback only when Vpp=VapH1/2/3- SR.1 does not provide a continuous indication of master and block lock-bit values. The WSM interrogates the master lock-bit, block lock-bit, and RP# only after Block Erase, Byte Write, or Lock-Bit configuration command sequences. It informs the system, depending on the attempted operation, if the block lock-bit is set, master lock-bit is set, and/or RP# is not Vi. Reading the block lock and master lock configuration codes after writing the Read Identifier Codes command indicates master and block !ock-bit status. SR.0 is reserved for future use and should be masked out when polling the status register. 18 PRODUCT PREVIEWSHARP LH28FO04SCH-L SmartVoltage Flash MEMORY Start Bus Command Comments Operation . Oata=20H Write 20H, Write Erase Setup Addr=Within Block to be Erased Block Address v Writ Erase Data=D0H Tite nage: Wiita DOH, Confirm Addr=Within Block to be Erased Block Address Vv Read Status Register Data Read Status Regist Check SR.7 i Suspend Block Erase Loo Standby 1=aWSM Ready P a=WSM Busy Repeat for subsequent block erasures. Full status check can be done after each block erase or after a sequence of block erasures. White FFH after the last operation to place devica in read array mode. Bus . Command Comments Operation Stancby Check SR.3 12Vop Error Detect Check SA.1 1=Device Protect Detect Standby RP #=V iy, Block Lock-Bit is Set Only required for systems implementing lock-bit configuration tandby Both 1=Command Sequence Error Standby Check SR.5 1=Block Erase Error Command Sequence $A.5,SA.4,SR.3 and SR.1 are only claared by the Clear Status Register Command in cases where multiple blocks are erased before full status is checked. If error is detected, clear the Status Register before attempting ratry or other error recovery. Block Erase Error Block Erase Successful Figure 8. Automated Block Erase Flowchart PRODUCT PREVIEW 19SHARP LH28F004SCH-L SmartVoltage Flash MEMORY Vv White 40H, Address Wnhite Byte Data and Address Vv Read Status Register Full Status Check if Desired Byte Write Complete Write Loop FULL STATUS CHECK PROCEDURE Read Status Register Data(See Above) Byte Write Successful Vpp Range Error Device Protect Error Byte Write Error Suspend Byte Bus Command Comments Operation Data=40H i Setup Byte Writ Wate emp eye Wnt AddraLocation to Be Written Wat Byte Wri Data=Data to Be Written ne yte Write AddrsLocation to Be Written Read Status Register Data Check SR.7 Standby 1=WSM Ready O=WSM Busy Repeat for subsequent byte writes.. SR full status check can be done after each byte write, or after a sequence of byte wnites. Write FFiH after the last byte write operation to place davice in ead array mode. Bus . Command Comments Operation 3 Standby Check SR 1=Vpp Error Datect Check SR.1 1=Device Protect Detect Standby RP#H=V,,,Block Lock-Bitis Set Only required for systems implementing lock-bit configuration 4 Standby Check SR. t=Data Waite Error SR.4,SA.3 and SR.1 are only cleared by the Clear Status Register command in cases where multiple locations ara written before fuil status is checked. if error is datected, clear the Status Register betore attamptng retry or other arror racovery. 20 Figure 9. Automated Byte Write Flowchart PRODUCT PREVIEWSHARP LH28F004SCH-L SmartVoltage Flash MEMORY Bus Command Comments Operation Writ Erase DatasB0H Write BOH Suspend AddreX Status Ragister Data AddraX Read Status Regist Chack SR.7 Standby 1=WSM Ready O=WSM Busy Check SA.6 Standby 1=Block Erase Suspended O=Block Erase Completed Writ Erase DatazDOoH me Resume Addr=X Block Erase Completed | Read Byte Write Byte Write 7 Read Array Data Byta Write Loop . No Done? Yes v v Write DOH | Write FFH v I (ae Erase Resume) Read Array Data Figure 10. Block Erase Suspend/Resume Flowchart PRODUCT PREVIEW 21SHARP LH28F004SCH-L SmartVoltage Flash MEMORY Com) ue Command Comments Operation " Write Byte Write Data=BoH Write BOR Suspend AddraX Status Register Data Read AddreX Read rs Status Register Check SR.7 Standby 1=WSM Ready O=WSM Busy Check SR.2 Standby 1=Byte Write Suspended O=Byte Write Completed Write Read Array DatamFFH AddraX Byta Writa Compieted Read Read Array locations other than that being wnitten. 1 + . Byte Write Data=DOH White FFH Write Resume Addr=X Read Array Data Done Reading Yes Vv Write DOH Write FFH v v (ene Write Resumed ) Read Aray Data Figure 11. Byte Write Suspend/Resume Flowchart 22 PRODUCT PREVIEWSHARP LH28FO004SCH-L SmartVoitage Flash MEMORY Operation Write sor) Set Dataz60H : Write Block/Master Addr=Btock Addrass(Block), Block/Device Address . , Lock-Bit Setup Device Address(Master) Data=01H(Block), Write O1H/F1H, Set einidtasten ) i i i Mast Block/Device Addrass Write Block or Master | rmBlock Address(Block), Lock-Bit Confirm Device Addrass(Master) Regist Status Ragister Read Status Register Data Check SR.7 Standby 1=wWSM Ready O=WSM Busy 1 Repeat for subsequent lock-bit set operations. Full status check can be done after each lock-bit set operation or after a sequence of lock-bit set operations. Write FFH after the last lock-bit set operation to place device in tead array mode. Fuil Status Check if Desired Set Lock-Bit Complete FULL STATUS CHECK PROCEDURE - Read Status Register Bus Data(See Above) . Command Comments Operation Standby Check SR.3 1=Vppe Error Detect Check SR.1 1=Devica Protect Detect RP#aV iy, Standby (Set Master Lock-Blt Operation) AP#2V 4, Master Lock-Bit is Sat (Set Block Lock-Blt Operation) Check SA.4,5 Standby Both tz=Command Sequence Error Command Sequence ore stancby Check SA.4 1=Set Lock-Bit Error SR.5,SR.4,SR.3 and SR.1 are only cleared by tha Clear Status Register command in cases where multiple lock-bits are set before full status is checked, Set Lock-Bit Error If error is detected, clear the Status Register bafore attampting retry or other arror recovery. Set Lock-Bit Successful Figure 12. Set Block and Master Lock-Bit Flowchart PRODUCT PREVIEW 23SHARP LH28F004SCH-L SmartVoltage Flash MEMORY Co) out | command cama Operation v White Clear Block Oata=60H Write 60H Lock-Bits Setup AddraX Oata=D0H AddraX Writ Clear Block me Lock-Bits Confirm Writa DOH Vv Read Read Status Register Data Status Register Standby Check SR.7 1a WSM Ready OQ=zWSM Busy place device in read array mode. Write FFH after the Clear Block Lock-Bits operation to Full Status Check if Desired Clear Block Lock-Bits Complete FULL STATUS CHECK PROCEDURE - Comments Check SR.3 1=Vpp Error Detect Check SR.1 1=Devica Protect Detect RP#=Vy4, Master Lock-Bit is Set Check SR.4,5 Both 1=Command Sequence Error Check SA.5 t=Clear Block Lock-Bits Error Read Status Register Bus Data(See Above) . Command Operation Standby Vep Range Error Standby Device Protect Error Standby Standby Command S ni co <8 $R.5,SR.4,SA.3 and SR.1 are only cleared by the Clear Status Ragister command. , {f arror is detected, clear the Status Register befora attempting retry or other error recovery. Clear Block Lock-Bits Error Clear Block Lock-Bits Successful Figure 13. Clear Block Lock-Bits Flowchart PRODUCT PREVIEWSHARP 5 DESIGN CONSIDERATIONS 5.1 Three-Line Output Control The device will often be used in large memory arrays. SHARP provides three control inputs to accommodate multiple memory connections. Three-line contro! provides for: a. Lowest possible memory power dissipation. b. Complete assurance that data bus contention will not occur. To use these control inputs efficiently, an address decoder should enable CE# while OE# should be connected to all memory devices and the systems READ# control line. This assures that only selected memory devices have active outputs while deselected memory devices are in standby mode. RP# should be connected to the system POWERGOOD signal to prevent unintended writes during system power transitions. POWERGOOD should also toggle during system reset. 5.2 RY/BY# and Block Erase, Byte Write, and Lock-Bit Configuration Polling RY/BY# is a full CMOS output that provides a hardware method of detecting block erase, byte write and lock-bit configuration completion. !t transitions low after block erase, byte write, or lock-bit configuration commands and returns to Vo, when the WSM_ has finished executing the internal algorithm. RY/BY# can be connected to an interrupt input of the system CPU or controller. It is active at all times. PRODUCT PREVIEW LH28F004SCH-L SmartVoltage Flash MEMORY RY/BY# is also Voy when the device is in block erase suspend (with byte write inactive), byte write suspend or deep power-down modes. 5.3 Power Supply Decoupling Flash memory power switching characteristics require careful device decoupling. System designers are interested in three supply current issues; standby current levels, active current leveis and transient peaks produced by falling and rising edges of CE# and OE#. Transient current magnitudes depend on the device outputs capacitive and inductive loading. Two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. Each device should have a 0.1 uF ceramic capacitor connected between its Vag and GND and between its Vpp and GND. These high-frequency, low inductance capacitors should be placed as close as possible to package leads. Additionally, for every eight devices, a 4.7 UF electrolytic capacitor should be placed at the array's power supply connection between Vcc and GND. The bulk capacitor will overcome voltage slumps caused by PC board trace inductance. 5.4 Vpp Trace on Printed Circuit Boards Updating flash memories that reside in the target system requires that the printed circuit board designer pay attention to the Vpp Power supply trace. The Vpp pin supplies the memory cell current for byte writing and block erasing. Use similar trace widths and tayout considerations given to the Voc power bus. Adequate Vpp supply traces and decoupling will decrease Vpp voltage spikes and overshoots. 25SHARP LH28FO04SCH-L SmartVoltage Flash MEMORY 5.5 Vcc, Vpp, RP# Transitions Block erase, byte write and lock-bit configuration are not guaranteed if Vpp falls outside of a valid Vopy4/2/3 range, Voc falls outside of a valid Voge/a/4 range, or RP#4Vi4, or Vuy. if Vpp error is detected, status register bit SR.3 is set to "1" along with SR.4 or SR.5, depending on the attempted operation. If RP# transitions to V\, during block erase, byte write, or lock-bit configuration, RY/BY# will remain low until the reset operation is complete. Then, the operation will abort and the device will enter deep power-down. The aborted operation may leave data partially altered. Therefore, the command sequence must be repeated after normal operation is restored. Device power-off or RP# transitions to V;, clear the status register. The CUI latches commands issued by system software and is not altered by Vep or CE# transitions or WSM actions. Its state is read array mode upon power-up, after exit from deep power-down or after Voc transitions below Vi xo. After block erase, byte write, or lock-bit configuration; even after Vpp transitions down to Vpp x, the CUl must be placed in read array mode via the Read Array command if subsequent access to the memory array is desired. 5.6 Power-Up/Down Protection The device is designed to offer protection against accidental block erasure, byte writing, or lock-bit configuration during power transitions. Upon power-up, the device is indifferent as to which power 26 supply (Vpp or Voc) powers-up first. Internal circuitry resets the CUI to read array mode at power-up. A system designer must guard against spurious writes for Voc voltages above Ving when Vpp is active. Since both WE# and CE# must be low for a command write, driving either to Vj, will inhibit writes. The CUls two-step command sequence architecture provides added level of protection against data alteration. In-system block lock and uniock capability prevents inadvertent data alteration. The device is disabled while RP#=V,, regardless of its control inputs state. 5.7 Power Dissipation When designing portabie systems, designers must consider battery power consumption not only during device operation, but also for data retention during system idle time. Flash memorys nonvoiatility increases usable battery life because data is retained when system power is removed. In addition, deep power-down mode ensures extremely low power consumption even when system power is applied. For example, portable computing products and other power sensitive applications that use an array of devices for solid-state storage can consume negligible power by lowering RP# to Vj standby or sleep modes. if access is again needed, the devices can be read following the tpyqy and tpyw_ Wake-up cycles required after RP# is first raised to V4. See AC Characteristics- Read Only and Write Operations and Figures 18, 19 and 20 for more information. PRODUCT PREVIEWSHARP 6 ELECTRICAL SPECIFICATIONS 6.1 Absolute Maximum Ratings* Commercial Operating Temperature During Read, Block Erase, Byte Write and Lock-Bit Configuration ........ -25C to +85C() Temperature under Bias............... -25C to +85C Storage Temperature.............ccceceeee -65C to +125C Voltage On Any Pin (except Voc, Vpp, and RP#).......-2.0V to +7.0V@) Voc Supply Voltage ...... eee -2.0V to +7.0V) LH28FO04SCH-L SmartVoltage Flash MEMORY NOTICE: This datasheet contains information on products in the design phase of development. Do not! finalize a design with this information. Revised! information will be published when the product is: available. Verify with your local SHARP Sales office: that you have the latest datasheet before finalizing al design: | *WARNING: Stressing the device beyond the Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the Operating Conditions" may affect device reliability. Vpp Update Voltage during Block Erase, Byte Write and Lock-Bit Configuration ........... -2.0V to +14.0V(2.3) RP# Voltage with Respect to GND during Lock-Bit Configuration Operations ...... -2.0V to +14.0V(2.9) Output Short Circuit Current ...... cesses 6.2 Operating Conditions Temperature and V- NOTES: 1. 2. 3. 4. Operating temperature is for commercial product defined by this specification. All specified voltages are with respect to GND. Minimum DC voltage is -0.5V on input/output pins and -0.2V on Vee and Vpp pins. During transitions, this level may undershoot to -2.0V for periods <20ns. Maximum DC voltage on input/output pins and Vee is Vee+0.5V which, during transitions, may overshoot to Vog+2.0V for periods <20ns. Maximum DC voltage on Vpp and RP# may overshoot to +14.0V for periods <20ns. Output shorted for no more than one second. No more than one output shorted at a time. Operating Conditions Symbol Parameter Notes Min Max Unit Test Condition Ta Operating Temperature -25 +85 C Ambient Temperature Very Ver Supply Voltage (2.7V-3.6V) 1 2.7 3.6 V Vero Ver Supply Voltage (3.3V+0.3V) 3.0 3.6 V | Vera Ver Supply Voltage (5V+5%) 4.75 5.25 Vv Vera Ver Supply Voltage (5V+10%) 4.50 5.50 Vv NOTE: 1. Block erase, byte write and lock-bit configuration operations with Veo<3.0V should not be attempted. 6.2.1. CAPACITANCE() T,=+25C, f=1MHz Symbol Parameter Typ Max Unit Condition Ci input Capacitance 6 8 pF Vin=O.0V Cautr Output Capacitance 8 12 pF Ve 7=0.0V NOTE: 1. Sampled, not 100% tested. - PRODUCT PREVIEW 27SHARP | LH28F004SCH-L SmartVoltage Flash MEMORY 6.2.2 AC INPUT/OUTPUT TEST CONDITIONS 27 5 INPUT Xe TEST POINTS _> 1.35 OUTPUT 0.0 5G AC test inputs are driven at 2.7V for a Logic "1" and 0.0V for a Logic "0." Input timing begins, and output timing ends, at 1.35V. Input rise and fall times (10% to 90%) <10 ns. Figure 14. Transient Input/Output Reference Waveform for Voc=2.7V-3.6V 3.0 5 INPUT Xs <?#__ TEST POINTS _> 1.5 OUTPUT 0.0 S AC test inputs are driven at 3.0V for a Logic "1" and 0.0V for a Logic "0." Input timing begins, and output timing ends, at 1.5V. Input rise and fall times (10% to 90%) <10 ns. Figure 15. Transient Input/Output Reference Waveform for Vo9=3.3V20.3V and Voc=5Vz5% (High Speed Testing Configuration) 2.4 55 INPUT oS rest TEST POINTS <C OUTPUT 0.8 0.8 0.45 AC test inputs are driven at Voy (2.4 Vr) for a Logic "1" and Vo. (0.45 Vrr_) for a Logic 0." Input timing begins at Vin (2.0 Vrt_) and Vy_ (0.8 Vrr_). Output timing ends at Viq and V\,. Input rise and fall times (10% to 90%) <10 ns. Figure 16. Transient Input/Output Reference Waveform for Vo=5V210% (Standard Testing Configuration) Test Configuration Capacitance Loading Value Test Configuration C, (pF) 1.3V Ven=3.3V+40.3V, 2.7V-3.6V 50 *k Vec=5V+5% 30 1N914 Ven=5V+10% 100 R=3.3kQ DEVICE UNDER OUT TEST C, Includes Jig 7 O, Capacitance Figure 17. Transient Equivalent Testing Load Circuit - 28 PRODUCT PREVIEWSHARP 6.2.3 DC CHARACTERISTICS LH28F004SCH-L SmartVoltage Flash MEMORY DC Characteristics Ver=2.7V Ver=3.3V Ver=5V Test Sym Parameter Notes| Typ | Max | Typ | Max | Typ | Max | Unit Conditions Wy input Load Current 1 +0.5 +0.5 +1 WA | Vec=VecMax VineVer or GND lo Output Leakage Current| 1 +0.5 +0.5 #10 | YA | Vog=VecMax VouteVer or GND locs | Voc Standby Current 1,3,6| 20 | 100 | 20 | 100 | 25 | 100 | PA | CMOS Inputs Vec=VecMax CE#=RP#=Vn-+0.2V 0.1 2 0.2 2 0.4 2 mA | TTL Inputs Vec=VocMax CE#=RP#=V, leep | Veco Deep Power-Down 1 20 20 20 | pA | RP#=GND+0.2V Current lonc(RY/BY#)=0mMA loca | Vcc Read Current 15,6; 6 12 7 12 17 35 | mA | CMOS Inputs Vec=VecMax, CE#=GND f=5MHz(3.3V, 2.7V), 8MHz(5V) lour=OMA 7 18 8 18 20 50 | mA | TTL Inputs Veo=VecMax, CE#=GND f=5MHz(3.3V, 2.7V), 8MHz(5V) lorr=OMA locw Voc Byte Write or 1,7 _ _ 17 _ _ mA Vpp=3.3V+0.3V Set Lock-Bit Current _ 17 35 | MA | Vpp=5.0V+10% 12 30 | MA | Vpp=12.0V25% loce | Voc Block Erase or 1,7), 17 | | | MA | Vpp=3.3V+0.3V Clear Block Lock-Bits ~ | 17 30 | MA | Vep=5.0V+10% Current |= 12 25 | MA | Vep=12.0V25% locws Vec Byte Write or Block 1,2 1 6 1 10 mA CE#=V iy leces | Erase Suspend Current lppg =| Vpp Standby or Read 1 #2 | #15 | #2 | #15 | #2 | +15 | WA | VppsVoc Ipp_ _| Current 10 | 200 | 10 | 200; 10 | 200 | PA | Vpp>Vern ippp | Vpp Deep Power-Down 1 0.1 5 0.1 5 0.4 5 yA | RP#=GND=+0.2V Current lppw Vpp Byte Write or Set 1,7 _ _ 40 _ _ mA Vpp=3.3V+0.3V Lock-Bit Current _ _ 40 40 | MA | Vpp=5.0V+10% _ 15 15 | mA | Vpp=12.0V+5% Ippe | Vpp Block Erase or 1,7 | _ 20 | MA | Vpp=3.3V+0.3V - Clear Lock-Bit Current 20 20 7; MA | Vep=5.0V+10% 15 15 | MA | Vep=12.0V25% Ippws Vpp Byte Write or Block 1 _ 10 200 10 200 pA Vep=VppH1/2/3 ippeg | Erase Suspend Current PRODUCT PREVIEW 29LH28F004SCH-L SmartVoltage Flash MEMORY OC Characteristics (Continued) Vep=2.7V Veap=3.3V Vec=5V Test Sym Parameter Notes! Min | Max | Min | Max | Min | Max | Unit Conditions Vi Input Low Voltage 7 05 | 08 | -05 | 08 | -05 | 08 V Vin Input High Voltage 7 2.0 | Veo | 2.0 | Veco | 2.0 | Veo | V +0.5 +0.5 +0.5 Vo. | Output Low Voltage 3,7 0.4 0.4 0.45 | Vi | Veco=VecMin, lo, =5.8MA(5V), lq, =2.0MA(3.3V) Vou1 | Output High Voltage 3,7 | 2.4 2.4 2.4 Vo | Vec=VecMin, (TTL) Iqu=-2.5mA(5V), lay=-2.0MA(3.3V) Vou2 | Output High Voitage 3,7 | 0.85 0.85 0.85 V | Vec=VecMin (CMOS) Ver Ver Ver lqy=-2.5A Voc Vee Voc Ve | Vec=VecMin -0.4 -0.4 -0.4 lay=-100UA VpPLK Vep Lockout during 4,7 41.5 1.5 1.5 V Normal Operations VepHy Vep during Byte Write, _ _ 3.0 3.6 _ _- V Block Erase or Lock-Bit Operations VepHo Vpp during Byte Write, _ 4.5 5.5 4.5 5.5 V Block Erase or Lock-Bit Operations VepH3 | Vpp during Byte Write, | 11.4) 12.6) 114/126] V Block Erase or Lock-Bit Operations Vixog | Ver Lockout Voitage 2.0 2.0 2.0 V Vu | RP# Uniock Voltage 8,9 | | 114) 12.6) 11.4] 12.6] Vj Set master lock-bit Override master and block lock-bit NOTES: 1. All currents are in RMS unless otherwise noted. These currents are valid for all product versions (packages and speeds). Contact your local sales office for information about typical specifications. 2. locws and Ioces are specified with the device de-selected. If read or byte written while in erase suspend mode, the devices current draw is the sum of Iogws OF loces and log OF lecw, respectively. 3. Includes RY/BY#. 4. Block erases, byte writes, and lock-bit configurations are inhibited when VppSVpp;,, and not guaranteed in the range between Vpp, (max) and Vppy4(min), between Vpp.4,(max) and Vppyo(min), between Vppyjo(max) and Vppey3(min), and above Vpp,,3(max). 5. Automatic Power Savings (APS) reduces typical Iogp to 1MA at 5V Veg and 3mA at 3.3V Veg in static operation. CMOS inputs are either Veo+0.2V or GND+0.2V. TTL inputs are either V,, or Vi. Sampled, not 100% tested. Master lock-bit set operations are inhibited when RP#=V,,,. Block lock-bit configuration operations are inhibited when the master lock-bit is set and RP#=V),,. Block erases and byte writes are inhibited when the corresponding - block-lock bit is set and RP#=V,,,. Block erase, byte write, and lock-bit configuration operations are not guaranteed with Voc <3.0V or Vi,4<RP#<V\4, and should not be attempted. 9. RP# connection to a Vii, supply is allowed for a maximum cumulative period of 80 hours. OND 30 PRODUCT PREVIEWSHARP LH28F004SCH-L SmartVoitage Flash MEMORY 6.2.4 AC CHARACTERISTICS - READ-ONLY OPERATIONS() Vep=2.7V-3.6V, T,=-25C to +85C Versions(4) LH28F004SCH- LH28F004SCH- L150 L170 Sym Parameter Notes Min Max Min Max Unit tavay Read Cycle Time 150 170 ns tavony Address to Output Delay 150 170 ns te ay CE# to Output Delay 2 150 170 ns teyov RP# High to Output Delay 600 600 ns taray | OE# to Output Delay 2 50 55 ns ter ny CE# to Output in Low Z 3 0 0 ns tepaz | CE# High to Output in High Z 3 55 55 ns tar ay OE# to Output in Low Z 3 0 0 ns__| texoz | OE# High to Output in High Z 3 20 25 ns tou Output Hold from Address, CE# or 3 0 0 ns OE# Change, Whichever Occurs First NOTE: See 5.0V Vog Read-Only Operations for notes 1 through 4. Vep=3.3V20.3V, Ta=-25C to +85C Versions(4) LH28F004SCH- LH28F004SCH- L120 L150 Sym Parameter Notes Min Max Min Max Unit tavav __ | Read Cycle Time : 120 150 ns tavay Address to Output Delay 120 150 ns ter ny CE# to Output Delay 2 120 150 ns toyiay RP# High to Output Delay 600 600 ns tarayv OE# to Output Delay 2 50 55 ns ter ay CE# to Output in Low Z 3 0 0 ns teyinz _ | CE# High to Output in High Z 3 55 55 ns tar ay OE# to Output in Low Z 3 0 0 ns taunz | OE# High to Output in High Z 3 20 25 ns tou Output Hold from Address, CE# or 3 0 0 ns OE# Change, Whichever Occurs First NOTE: See 5.0V Veg Read-Only Operations for notes 1 through 4. PRODUCT PREVIEW 31SHARP LH28F004SCH-L SmartVoltage Flash MEMORY Vec=5V20.5V, 5Vt0.25V, T,=-25C to +85C Vect5% LH28F004SCH- L35(5) Versions(4) Vect#10% LH28FO004SCH- | LH28F004SCH- L90(6) L120(6) Sym Parameter Notes| Min Max Min Max Min Max { Unit tavay Read Cycle Time 85 90 120 ns tavoy Address to Output Delay 85 90 120 ns te: av CE# to Output Delay 2 85 90 120 ns touoay RP# High to Output Delay 400 400 400 ns ter ov OE# to Output Delay 2 40 45 50 ns te: ay CE# to Output in Low Z 3 0 0 0 ns teyig7z | CE# High to Output in High Z 3 55 55 55 ns tar ax OE# to Output in Low Z 3 0 0 0 ns tepoz | OE# High to Output in High Z 3 10 10 15 ns ton Output Hold from Address, 3 0 0 0 ns CE# or OE#-Change, Whichever Occurs First NOTES: 1. See AC Input/Output Reference Waveform for maximum allowable input slew rate. 2. OE# may be delayed up to te, qy-tg_ay after the falling edge of CE# without impact on te, ay. 3. Sampled, not 100% tested. 4. See Ordering Information for device speeds (valid operational combinations). 5. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (High Speed Configuration) for testing characteristics. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (Standard Configuration) for testing characteristics. > 32 PRODUCT PREVIEWSHARP LH28FO04SCH-L SmartVoltage Flash MEMORY Device : V Standby Address Selection Data Valid Vit Creeeeruas 4 tavav Vi CE#(E) / \ / : \ Vm 1188 8 rT] aq GHOZ,, taveL [+> Vin OEKG) JS \ / ; \ Vim 4 SHOZ, Vin peouenauea WE#(W) S tetav \ Viv __eLavl | tacax, toH>} _tELox | pata HIGH Z Fats out AK HIGH Z (DQ -DQ7) \ i alt utpu | 7 Vor / tavay re rscesess vee /S \ tpyav Vi 13330565 RP#(P) \ Vie Figure 18. AC Waveform for Read Operations PRODUCT PREVIEW 33SHARP LH28FO004SCH-L SmartVoltage Flash MEMORY 6.2.5 AC CHARACTERISTICS - WRITE OPERATION() Vpp=2.7V-3.6V, Ty=-25C to +85C Versions) LH28F004SCH- LH28F004SCH- L150 L170 Sym Parameter Notes Min Max Min Max Unit tavay Write Cycle Time 150 170 ns tpywL | RP# High Recovery to WE# Going 2 1 1 us Low terwi CE# Setup to WE# Going Low 10 10 ns twiwiy | WE# Pulse Width 50 50 ns tavwi _| Address Setup to WE# Going High 3 50 50 ns t y | Data Setup to WE# Going High 3 50 50 ns twunx | Data Hold from WE# High 5 5 ns twuax | Address Hold from WE# High 5 5 ns twHew | CE# Hold from WE# High 10 10 ns twew | WE# Pulse Width High 30 30 ns twucy Write Recovery before Read | 0 0 ns NOTE: See 5.0V Voc WE#-Controlled Writes for notes 1 through 5. V-p=3.3V#0.3V, T,=-25C to +85C Versions(5) LH28F004SCH- LH28F004SCH- L120 L150 Sym : Parameter Notes Min Max Min Max Unit tavay Write Cycle Time 120 150 ns tpuwe | RP# High Recovery to WE# Going 2 1 1 Us Low tenwe CE# Setup to WE# Going Low 10 10 ns twiwiy | WE# Pulse Width 50 50 ns teyywy | RP# Vii, Setup to WE# Going High 2 100 100 ns tveweH Vop Setup to WE# Going High 2 100 100 ns tavwyH | Address Setup to WE# Going High 3 50 50 ns tovwy | Data Setup to WE# Going High 3 50 50 ns twunx | Data Hold from WE# High 5 5 ns twuax | Address Hold from WE# High 5 5 ns twee CE# Hold from WE# High 10 10 ns twiw | WE# Pulse Width High 30 30 ns twee! WE# High to RY/BY# Going Low 100 100 ns twucr Write Recovery before Read 0 0 ns tovwvL | Vpp Hold from Valid SRD, RY/BY# 2,4 0 0 ns High tovey | RP# Vi Hold from Valid SRD, 2,4 0 0 ns RY/BY# High NOTE: See 5V Voc AC Characteristics - Write Operations for Notes 1 through 5. 34 PRODUCT PREVIEWSHARP LH28FO04SCH-L SmartVoltage Flash MEMORY Vee =5V20.5V, 5V+20.25V, T,=-25C to +85C Vece5% LH28F004SCH- Lg5(6) Versions() Voct10% LH28F004SCH- | LH28F004SCH- L90(7) L120(7) Sym Parameter Notes; Min Max Min Max Min Max | Unit | tavav Write Cycle Time 85 90 120 ns | tpywe | RP# High Recovery to WE# 2 1 1 1 Us | Going Low ter wi CE# Setup to WE# Going Low 10 10 10 ns_!| twiwe | WE# Pulse Width 40 40 40 ns: tpyHwH | RP# Vun Setup to WE# Going | 2 100 100 100 ns High tvpwy | Vpp Setup to WE# Going High 2 100 100 100 ns taywH | Address Setup to WE# Going 3 40 40 40 ns High tovwy_ | Data Setup to WE# Going 3 40 40 40 ns | High twunx | Data Hold from WE# High 5 5 5 ns twiax | Address Hold from WE# High 5 5 5 ns twuen | CE# Hold from WE# High 10 10 10 ns twin) | WE# Pulse Width High 30 30 30 ns twura. | WE# High to RY/BY# Going 90 90 90 ns Low twuer | Write Recovery before Read ; 0 0 0 ns tov Vpp Hold from Valid SRD, 2,4 0 0 0 ns i RY/BY# High tovey | RP# Vy Hold from Valid 2,4 0 0 0 ns SRD, RY/BY# High NOTES: 1. Read timing characteristics during block erase, byte write and lock-bit configuration operations are the same as during read-onry operations. Refer to AC Characteristics for read-only operations. 2. Sampled, not 100% tested. 3. 4. Vpp should be held at Vopy4/2/3 (and if necessary RP# should be held at V,4,) until determination of block erase, Refer to Table 4 for valid Aj and Diy for block erase, byte write, or lock-bit configuration. byte write, or lock-bit configuration success (SR.1/3/4/5=0). See Ordering Information for device speeds (valid operational combinations). See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (High Seed Configuration) for testing characteristics. . See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (Standard Configuration) for testing characteristics. ~ PRODUCT PREVIEW 35SHARP LH28F004SCH-L SmartVoltage Flash MEMORY ADDRESSES(A) CE#(E) OE G) WEH(W) DATA(D/Q) RY/BY4(R) RP#(P) Vpp(V) NOTES: . Veo power-up and standby. . Read status register data. . Write Read Array command. Qa han 1 2 5 6 3 4 (a gerne, guinea, geome gysrensrenstt camara, gerry, Vint Ir Ir i. Vit w _ tavav tavwH wt yf) tee tale twoen LALA XARA LS LS twet, | UW Vit tw. tweevi236 Vin / 5 J 1) \ fT Vit te Lr OVWH twHox Vid High Z >. WHO Co.) Eivaia\\y (om \ SRD Me (On) (hs80 774 28) vm PHL Leann, | Vit + teunwe | toven VuH E \ Vin } vw t " jeter + tov an Kn, = NR) . Write block erase or byte write setup. . Write block erase confirm or valid address and data. . Automated erase or program delay. A A Figure 19. AC Waveform for WE#-Controlled Write Operations 36 PRODUCT PREVIEWSHARP LH28FO04SCH-L SmartVoltage Flash MEMORY 6.2.6 ALTERNATIVE CE#-CONTROLLED WRITES() Vep22.7V-3.6V, Ta=-25C to +85C Versions() LH28F004SCH- LH28F004SCH- L150 L170 Sym Parameter Notes Min Max Min Max Unit tavay Write Cycle Time 150 170 ns tower RP# High Recovery to CE# Going Low 2 1 1 us tw 5 WE# Setup to CE# Going Low 0 0 ns te) ey CE# Pulse Width 70 70 ns tavern Address Setup to CE# Going High 3 50 50 ns tovew Data Setup to CE# Going High 3 50 50 ns teuny Data Hold from CE# High 5 5 ns teway Address Hold from CE# High 5 5 ns tenwey | WE# Hold from CE# High 0 0 ns tee) CE# Pulse Width High 25 25 ns tena: Write Recovery before Read 0 0 ns NOTE: See 5.0V Veg Alternative CE#-Controlled Writes for notes 1 through 5. Veg=3.3V20.3V, T,=-25C to +85C Versions) LH28F004SCH- LH28F004SCH- 1120 L150 sym Parameter Notes Min Max Min Max Unit tavay | Write Cycle Time , 120 150 ns toe) RP# High Recovery to CE# Going Low 2 1 1 us twee WE# Setup to CE# Going Low 0 0 ns te ey CE# Pulse Width 70 70 ns tonne | RP# Vig Setup to CE# Going High 2 100 100 ns type _| Vpp Setup to CE# Going High 2 100 100 ns tavew Address Setup to CE# Going High 3 50 50 ns tover Data Setup to CE# Going High 3 50 50 ns teuny Data Hold from CE# High 5 5 ns teuay Address Hold from CE# High 5 5 ns tepwiy | WE# Hold from CE# High 0 0 ns tee! CE# Pulse Width High 25 25 ns teu) CE# High to RY/BY# Going Low 100 100 ns teu: Write Recovery before Read 0 0 ns tevv. | Vpp Hold from Valid SRD, RY/BY# 2,4 0 0 ns High taveH | RP# Vi Hold from Valid SRD, 2,4 0 0 ns RY/BY# High NOTE: See SV Vc Alternative CE#-Controlled Writes for Notes 1 through 5. PRODUCT PREVIEW 37SHARP LH28FO004SCH-L SmartVoltage Flash MEMORY Vec=5V20.5V, 5V20.25V, T,=-25C to +85C Vec+5% LH28F004SCH- L35(6) Versions(5) Vec210% LH28FO004SCH- | LH28F004SCH- L90(7) L120(7) sym Parameter Notes! Min Max Min Max Min Max Unit tavay Write Cycle Time 85 90 120 ns tpyeL | RP# High Recovery to CE# 2 1 1 1 us Going Low twee! WE# Setup to CE# Going Low 0 QO 0 ns ter eu CE# Pulse Width 50 50 50 ns teHHEH nee Vu Setup to CE# Going 2 100 100 100 ns ig typey Vpp Setup to CE# Going High 2 100 100 100 ns taveH padres Setup to CE# Going 3 40 40 40 ns 1G toveu Data Setup to CE# Going High| 3 40 40 40 ns teunx _| Data Hold from CE# High 5 5 5 ns teuay Address Hold from CE# High 5 5 5 ns tenwH | WE# Hold from CE# High 0 0 0 ns teye) CE# Pulse Width High 25 25 25 ns teHRL vee High to RY/BY# Going 90 90 90 ns ow teua: Write Recovery before Read 0 0 0 ns tovvL Vep Hold from Valid SRD, 2,4 0 0 0 ns RY/BY# High tavpH | RP# Vi Hold from Valid 2,4 0 0 0 ns SRD, RY/BY# High NOTES: 1. In systems where CE# defines the write pulse width (within a longer WE# timing waveform), all setup, hold, and inactive WE# times should be measured relative to the CE# waveform. 2. Sampled, not 100% tested. 3. Refer to Table 4 for valid Ajj and Diy for block erase, byte write, or lock-bit configuration. 4. Vpp should be held at Vppy1/2/3 (and if necessary RP# should be held at V,,,,) until determination of block erase, byte write, or lock-bit configuration success (SR.1/3/4/5=0). 5. See Ordering information for device speeds (valid operational combinations). 6. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (High Seed Configuration) for testing characteristics. 7. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (Standard Configuration) for testing characteristics. 38 PRODUCT PREVIEWSHARP LH28F004SCH-L SmartVoltage Flash MEMORY wo 2 2 . 4 5 6 ADDRESSES(A) = | OO OOO tavav taven r Neaax em LE + hts tent G Vin | O&# Vit J L/ teyovi2z4 Vin . 4 L CE#(E) y / i \_/ . Ge i . EHOX {| pray 1 Se eek ms) ed) Ve teHeL 4 tena RY/BY #(R) / Vit , . Vit f RP#(P) Vy + : pees h}+ tow. < f_ ce STTETET AACN vom IO TSI Vegan . Read status register data. . Write Read Array command. Aanprand + Figure 20. Alternate AC Waveform for CE#-Controlled Write Operations PRODUCT PREVIEW 39SHARP LH28F004SCH-L SmartVoitage Flash MEMORY 6.2.7 RESET OPERATIONS Vin RY/BY#(R) Vit Vin RP#(P) Vie tpLeH Vin RY/BY#(R) Vit (A)Reset During Read Array Mode Vie RP#(P) Vi | tPLpH (B)Reset During Block Erase, Byte Write, or Lock-Bit Configuretion 2.7V/3.3V/5V tPLRH Voc Vit tagsvPH Viw RP#(P} Vit (C)RP# rising Timing Figure 21. AC Waveform for Reset Operation Reset AC Specifications() Vepn=2.7V Ver=3.3V Ver=5V Sym Parameter Notes; Min Max Min Max Min Max Unit teLeH RP# Pulse Low Time 100 100 100 ns (If RP# is tied to Voc, this specification is not applicable) tpLRH RP# Low to Reset during 2,3 20 12 us Block Erase, Byte Write or Lock-Bit Configuration teasven | Voc 2.7V to RP# High 4 100 100 100 ns Veco 3.0V to RP# High Ver 4.5V to RP# High NOTES: 1. These specifications are valid for all product versions (packages and speeds). 2. If RP# is asserted while a block erase, byte write, or lock-bit configuration operation is not executing, the reset will complete within 100ns. 3. A reset time, tpygy, is required from the latter of RY/BY# or RP# going high until outputs are valid. 4. When the device power-up, holding RP# low minimum 100ns is required after Voc has been in predefined range and also has been in stable there. 40 PRODUCT PREVIEWSHARP LH28F004SCH-L SmartVoltage Flash MEMORY 6.2.8 BLOCK ERASE, BYTE WRITE AND LOCK-BIT CONFIGURATION PERFORMANCE(4) Vee=3.3V20.3V, T,=-25C to +85C Vpp=3.3V Vpp=5V Vpp=1 2V Sym Parameter Notes| Min |Typ{| Max | Min |Typ()| Max | Min [Typ] Max | Unit twHav1 | Byte Write Time 2 15 17 | TBO | 82 | 93 | TBD| 67 |) 7.6 | TBD] us tenovs Block Write Time 2 1 1.1) TBD! 0.5 | 05 | TBD | 0.4 | 05 | TBD| sec twrave | Block Erase Time 2 1.5) 18} TBD] 1 1.2 ; TBD; 0.8 | 1.1 | TBD | sec tenave twHovg | Set Lock-Bit Time 2 18 21 | TBD | 11.2 | 13.3] TBD; 9.7 | 11.6] TBD] us EHOV3 twHavea | Clear Block Lock-Bits 2 1.5 ] 1.8 | TBD 1 1.2 | TBD | 08 | 1.1 | TBD | sec texova | Time twurHi | Byte Write Suspend 7A 10 6.6 | 9.3 7.4 | 10.4; us teyau, | Latency Time to Read twury2 | Erase Suspend Latency 15.2 | 21.1 12.3 | 17.2 12.3 | 17.2 | us teunyo | Time to Read Voep25V20.5V, 5V+0.25V, Ta=-25C to +85C Vpp=5V | Vpp=12V | Sym Parameter Notes} Min | Typ[ | Max | Min | Typ()) Max | Unit | twHovi | Byte Write Time 2 6.5 8 TBD | 4.8 6 TBD Us teyavi | Block Write Time : 2 0.4 0.5 | TBD 0.3 0.4 | TBD | sec twHave | Block Erase Time 2 0.9 1.4 | TBD | 0.3 1.0 | TBD | sec tenqve teyava twHavea | Clear Block Lock-Bits Time 2 0.9 1.1 | TBD | 0.3 1.0 | TBD | sec tenqva twHrHi | Byte Write Suspend Latency Time to 5.6 7 5.2 7.5 Us teyaus, | Read twHru2 | Erase Suspend Latency Time to Read 9.4 | 13.1 98 | 12.6 | us teymue NOTES: 1. Typical values measured at T,=+25C and nominal voltages. Assumes corresponding lock-bits are not set. Subject to change based on device characterization. 2. Excludes system-level overhead. 3. These performance numbers are valid for al! speed versions. 4. Sampled but not 100% tested. PRODUCT PREVIEW AlSHARP LH28F004SCH-L SmartVoltage Flash MEMORY 7 ADDITIONAL INFORMATION 7.1 Ordering Information Product line designator for all SHARP Flash products _ LIH}2,8/F|0)0)4, S/C/H|T|-|L18/5 Lo Ld Device Density Access Speed (ns) 004 = 4M-bit e85ns(5V,30pF), 90ns(5V), . - 120ns(3.3V), 150ns(2.7V) Architecture 120ns(5V), 150ns(3.3V), S = Regular Block | 170ns(2.7V) Power Supply Type Low Voltage Option C = SmartVoitage Technology | blank = Not use 2.7V Vcc Operating Temperature | L = 2.7V Vcc (Read only) blank = 0C ~ +70C Package H = -40C ~ +85C T = 40-Lead TSOP R = 40-Lead TSOP(Reverse Bend) N = 44-Lead PSOP B = 48-Lead CSP Valid Operational Combinations Vec=2.7-3.6V Voc=3.3+0.3V Vep=5.0210% Vog=5.025% 50pF load, 50pF load, 100pF load, 30pF load, Option Order Code 1.35V VO Levels 1.5V 1/0 Levels TTL I/O Levels 1.5V I/O Levels 1 | LH28FO04SCHX- LH28FO04SCH- = | LH28FO04SCH- LH28FO04SCH- =| LH28F004SCH- L85 L150 L120 L90 L85 2. | LH28FO04SCHX- LH28F004SCH- | LH28F004SCH- LH28F004SCH- Li2 L170 L150 L120 42 PRODUCT PREVIEWLH28Fxxx FLASH MEMORY FLASH NON-VOLATILE MEMORY FLASH E2ROM FLASH ROM READ ONLY MEMORY ETOX LH28F004SCH-L 4M (512Kx8) Smart Voltage