TECHNOLOGY FEATURES = Allows Safe Board Insertion and Removal from a Live Backplane System Reset and Power Good Control Outputs Programmable Electronic Circuit Breaker User Programmable Supply Voltage Power-Up Rate High Side Driver for Two External N-Channels Controls Supply Voltages from 3V to 12V Connection Inputs Detect Board Insertion or Removal Undervoltage Lockout Power-On Reset Input APPLICATIONS = Hot Board Insertion = Electronic Circuit Breaker 7 LTC and LT are registered trademarks of Linear Technology Corporation. Hot Swap is a trademark of Linear Technology Corporation. } \D LTC 1421/LTC1421-2.5 Hot Swap Controller DESCRIPTION The LTC1421/LTC1421-2.5 are Hot Swap controllers that allow a board to be safely inserted and removed froma live backplane. Using external N-channel pass transistors, the board supply voltages can be ramped up at a program- mable rate. Two high side switch drivers control the N- channel gates for supply voltages ranging from 3V to 12V. Aprogrammable electronic circuit breaker protects against shorts. Warning signals indicate that the circuit breaker has tripped, a power failure has occurred orthat the switch drivers are turned off. The reset output can be used to generate a system reset when the power cycles or a fault occurs. The two connect inputs can be used with stag- gered connector pins to indicate board insertion or re- moval. The power-on reset input can be used to cycle the board power or clear the circuit breaker. The trip point of the ground sense comparator is set at 0.1V for LTC1421 and 2.5V for LTC1421-2.5. The LTC1421/LTC1421-2.5 are available in 24-pin SO and SSOP packages. I I ir} = I Vee TT I I Vp T= I I Rt at l 0.0052 MTBSONOBE \o= ac 1) 23 |22 I) '| 8 I 3 1| 8 1| 1] I B FAULT +- = I POR =| I I GND py= | | = I I DATA J I Bus I gy | | tT I I I BACKPLANE PC BOARD Q3 1/2 Si4936DY 0. aut Ra 5 sa A 20k 220uF R2 Q2 5% a 0.025Q 1/2 Si4936DY = +1 63 A 220uF Re ot 20k I> 220uF yn 3 BEA Voc BEB GND OS3884 QuickSwitch IS A REGISTERED TRADEMARK OF QUALITY SEMICONDUCTOR CORPORATION. L) TECHNOLOGYLTC 1421/LTC1421-2.5 ABSOLUTE MAXIMUM RATINGS (Note 1) Supply Voltage (Vecio, Vecu!, AUXVc) eee 13.2V Input Voltage (Analog Pins) ..... - 0.3V to (Veg) + 0.3V) Input Voltage (Digital Pins) ................ 0.3V to 13.2V Output Voltage (Digital Pins) .. 0.3V to (Vec_g + 0.3V) Output Voltage (CPON)......... 13.2V to (Vec_o + 0.3V) Output Voltage (VoytLo, VouTHI) +: 0.3V to 13.2V Output Voltage (GATELO, GATEHI)............ 0.3V to 20V Operating Temperature Range..............006 0C to 70C Storage Temperature Range ................ 65C to 150C Lead Temperature (Soldering, 10 sec)................. 300C PACKAGC/ORDER INFORMATION TOP VIEW cont [4 24] cone [2 23] POR [3] 22] FAULT [4] 24] DISABLE [5 | 20] pwreo [6 | 9] RESET [7 | 18] rer [8] 7] cpon [9] 76] RAMP [10] 15] FB [1] 4] GND. [12] 73] G PACKAGE 24-LEAD PLASTIC SSOP SW PACKAGE 24-LEAD PLASTIC SO Tymax = 125C, Oya = 100C/W (G) Tymax = 125C, Oj, = 85C/W (SW) AUXVec VecLo SETLO GATELO VouTLo Vechi SETHI GATEHI VoUuTHI COMPOUT COMP~ cOMPt ORDER PART NUMBER LTC1421CG LTC1421CSW LTC1421-2.50G LTC1421-2.5CSW Consult factory for Industrial and Military grade parts. ELECTRICAL CHARACTERISTICS Vecut = 12V, Vecio = 5V, Ta = 25C unless otherwise noted (Note 2). SYMBOL | PARAMETER | CONDITIONS MIN TYP MAX | UNITS DC Characteristics lecto Veco Supply Current CONT = CON? = GND, POR = Vecio e 1.5 3 mA lecHi Vocu! Supply Current CON1 = CON2 = GND, POR = Vecio e 0.6 1 mA VLKO Undervoltage Lockout Veco and Vccu 2.28 2.45 2.60 V VLKH Undervoltage Lockout Hysteresis VecLo and VecH) 100 mV VRer Reference Output Voltage No Load @; 1.220 1.232 1.244 V AVLNR Reference Line Regulation 3V <VecLo < 12V, No Load e 4 8 mV AVLDR Reference Load Regulation Io =0mA to 5mA, Sourcing Only e 1 3 mV lasc Reference Short-Circuit Current Vper = OV -45 mA Voor Comparator Offset Voltage OV < Vem <(VecLo 1.3V) e +10 mV Vopsr Comparator Power Supply Rejection OV < Vem <(Veclo 1.3V), 8V < Vecto < 12V e 1 mv/V Veust Comparator Hysteresis OV < Vom <(VecLo 1.3V) rf mV Vast Reset Voltage Threshold (VoutLo) FB = VouTLo @| 2.80 2.90 3.00 V FB = Floating @| 4.50 4.65 4.75 V FB = GND @| 575 5.88 6.01 V VeHsT Reset Threshold Hysteresis (VoytLo) FB = VouTLo rf mV FB = Floating 12 mV FB = GND 15 mV Rrg FB Pin Input Resistance OV < Veg <VecLo 95 kQ Vop Circuit Breaker Trip Voltage Vep = (Vecto-Vsetto) or Veg = (VecHi-VsetHi) | @ 40 50 60 mV VrRIP Output Voltage for Re-Power-Up LTC1421 (Note 3) 0.1 V LTC1421-2.5 (Note 4) 2.5 V 2LTC 1421/LTC1421-2.5 ELECTRICAL CHARACTERISTICS Vecu = 12V, Vecio = 5V, Ta = 25C unless otherwise noted (Note 2). SYMBOL | PARAMETER CONDITIONS MIN TYP MAX UNITS RAMP RAMP Pin Output Current Charge Pump On, Vaamp=0.4V e 11 17 23 pA lop Charge Pump Output Current Charge Pump On, GATEHI = 0V -600 yA GATELO = 0V -300 pA AVeaten! | GATEHI N-Channel Gate Drive VoaTen! VouTHl 6 16 V AVeateLo | GATELO N-Channel Gate Drive VeateLo VouTLo 10 16 V Vauxyec | Auxiliary Vcc Output Voltage VecLo = 5V, Unloaded 4.5 V Vib Input Low Voltage CONT, CON2, POR e 0.8 V Vin Input High Voltage CON1, CON2, POR e 2 Vv lin Input Current CONT, CON2, POR = GND e| -30 -60 -90 yA VoL Output Low Voltage RESET, COMPOUT, PWRGD, DISABLE, FAULT, | @ 0.4 Vv Igp=3mA CPON, Ip = 3mA e 1.45 V Vou Output High Voltage DISABLE, Ip =-3mA e 4 V CPON, Ip=-1mA e 3.4 V ly Logic Output Pull-Up Current RESET, PWRGD, FAULT = GND -15 yA AC CHARACTERISTICS ty CON1 or CON2, to CPONT Figure 1, C, = 15pF @e| 15 20 30 ms to PWRGDT to RESETT Figure 1, Ry = 10k to Vegio, Cy = 15pF 160 200 240 ms @| 140 200 280 ms ty PWRGDT to DISABLEL Figure 1, C, = 15pF 160 200 240 ms @| 140 200 280 ms ty POR! to CPONL Figure 1, C, = 15pF e 15 20 30 ms ts PWRGDJ to RESETL Figure 1, Ry = 10k to Voc, C, = 15pF 32 Us tg PORT to CPONT Figure 1, C, = 15pF 50 ns ty CON1 or CON2T to CPONL Figure 1, C, = 15pF 50 ns tg Short-Circuit Detectto FAULTJ Figure 1, Ry = 10k to Voc, C, = 15pF 20 Us Vecto SETLO = OmV to 100mV to Short-Circuit Detect to CPONL Figure 2, C, = 15pF 20 us Vecto SETLO = OmV to 100mV ty PORT to FAULTT Figure 2, Ry = 10k to Veco, CL = 15pF 20 ns ToHL Comparator High to Low COMP = 1.232V, 10mV Overdrive e 0.25 0.5 us R, = 10k to Vecio, C. = 15pF teLH Comparator Low to High COMP = 1.232V, 10mV Overdrive e 1 1.5 us R, = 10k to Vecio, C. = 15pF The @ denotes specifications which apply overthe full operating temperature range. Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All currents into device pins are positive; all currents out of device pins are negative. All voltages are reference to ground unless otherwise specified. Vtaip point before the charge pump is restarted. before the charge pump is restarted. Note 3: After power-on reset, the Voytio and VoutH) have to drop below the Note 4: After power-on reset, the Voytio has to drop below the Vypjp pointLTC 1421/LTC1421-2.5 TYPICAL PERFORMANCE CHARACTERISTICS Reference Voltage vs Temperature 1.238 Vecio = 5V Vechi = 12V 1.236 = <= 4934 1.232 1.230 = Nm nm co REFERENCE VOLTAG 1.226 1.224 -60 -25 0 2 50 765 TEMPERATURE (C) 100 125 1421 G04 GATELO Voltage vs Veco Voltage Vecu! = 12V = lu oO i? 5 Oo > S jz << oO 0 2 4 6 8 1 12 14 Veco VOLTAGE (V) 1421 G04 lecu) Supply Current vs Temperature 555 Veco = 5V 550 Vecui = 12V = & 545 a a < 540 Qo 71 535 a a = 530 8 on Nm on 100 20 -50 -25 0 2 50 75 125 TEMPERATURE (C) 1421 GO7 Gate Voltage vs Temperature VecLo = 5V Voecui = 12V S lu GATEHI oO i? 5 Oo > lu = oO GATELO 7 -50 -25 0 2 50 75 100 125 TEMPERATURE (C) 1421 GO2 GATEHI Voltage vs Vccy Voltage Vecio = 5V = lu oO 5 Oo > = Lu = oO 0 2 4 6 8 0 12 14 Vecu VOLTAGE (V) 1421 GOS Vor VS Isink 600 yest OY CCHI = 500 Y _. 400 COMPOUT 4A w S Sa VOLTAGE (m | Cc 5 200 [44 = 100 A lL 0 0 2 4 6 8 10 SINK CURRENT (mA) 1421 GOB 1.245 1.240 REFERENCE VOLTAGE (V. 1.235 1.230 1.225 1.220 0 1500 IocLo SUPPLY CURRENT (yA 1400 1300 1200 CPON VOLTAGE (V) -50 -25 0 25 50 75 2.5 N Oo a a 4 Oo 0.5 Reference Voltage vs Source Current VecLo = 5V Vecu = 12V 2 4 6 8 10 SOURCE CURRENT (mA) 1421 GN3 lcetp Supply Current vs Temperature Vecio = 5V L Vecui = 12V Ny, N\ Nm. lh 100 125 TEMPERATURE (C) 1421 GOS CPON Voltage vs Sink Current (Charge Pump Off) VecLo = 5V Vecu! = 12V 0 05 1.0 15 2.0 25 3.0 SINK CURRENT (mA) 1421 GNgLTC 1421/LTC1421-2.5 TYPICAL PERFORMANCE CHARACTERISTICS CPON Voltage vs Source Current (Charge Pump On) VecLo = 5V Vecu| = 12V Ls NY PNY PNY CPON VOLTAGE (V) 0 0 -05 -1.0 -15 -20 -25 -3.0 SOURCE CURRENT (mA) 1421 G10 lecLo Supply Current VS Vec_o Voltage 7 Vechi = 12V 6 = E KE 5 = lu & 3S 4 F Qo a SF a a S| g ? 7 8 1 O74 0 0 2 4 6 8 10 12 14 Vecio VOLTAGE (V) 1421G14 PIN FUNCTIONS CON1 (Pin 1): TTL Level Input with a Pull-Up to Vec_o. Together with CON2, it is used to indicate board connec- tion. The pin must be tied to ground on the host side of the connector. When using staggered connector pins, CON1 and CON2 must be the shortest and must be placed at Opposite corners of the connector. Board insertion is assumed after CON1 and CON2 are both held low for 20ms after power-up. CON2 (Pin 2): TTL Level Input with a Pull-Up to Vecio. Together with CON1 it is used to indicate board connec- tion. POR (Pin 3): TTL Level Input with a Pull-Up to Vecio. When the pin is pulled low for at least 20ms, a hard reset is generated. Both Voytio and Voyty) will turn off at a controlled rate. A power-up sequence will not start until the POR pin is pulled high. If POR is pulled high before VoutLo and Voyty) are fully discharged, a power-up sequence will not begin until the voltage at Voytio and VourtHi are below Vrpip. The electronic circuit breaker will be reset by pulling POR low. FAULT (Pin 4): Open Drain Output to GND with a Weak Pull-Up to Veco. The pin is pulled low when an overcur- rent fault is detected at Voytio Or VouTHI- DISABLE (Pin 5): CMOS Output. The signal is used to disable the boards data bus during insertion or removal. PWRGD (Pin 6): Open Drain Output to GND with a Weak Pull-Up to Veco. The pin is pulled low immediately after Voutto falls below its reset threshold voltage. The pin is pulled high immediately after Voyt_o rises above its reset threshold voltage. RESET (Pin 7): Open Drain Output to GND with a Weak Pull-Up to Vecig. The pin is pulled low when a reset condition is detected. A reset will be generated when any of the following conditions are met: Either CON1 or CON2 is high, POR is pulled low, Vecig or VecH) are below their respective undervoltage lockout thresholds, PWRGD goes low or an overcurrent fault is detected at Voytio or VoutH. RESET will go high 200ms after PWRGD goes high. On power failure, RESET will go low 32us after PWRGD goes low. REF (Pin 8): The Reference Voltage Output. Voyt =1.232V +1%. The reference can source up to 5mA of current. A 1pF bypass capacitor is recommended. CPON (Pin 9): CMOS Output That Can Be Pulled Below Ground. CPON is pulled high when the internal charge pumps for GATELO and GATEHI are turned on. CPON is pulled low when the charge pumps are turned off. The pin can be used to control an external MOSFET for a 5V to 12V supply. LI Wee oLTC 1421/LTC1421-2.5 PIN FUNCTIONS RAMP (Pin 10): Analog Power-Up Ramp Control Pin. By connecting an external capacitor between the RAMP and GATEHI, a positive linear voltage ramp on GATEHI and GATELO is generated on power-up with a slope equal to 20pA/CRampe. FB (Pin 11): Analog Feedback Input. FB is used to set the reset threshold voltage on Vec__p. For a 5V supply leave FB floating. For a 3.3V supply, short FB to Vogio. GND (Pin 12): Ground COMP?* (Pin 13): Noninverting Comparator Input. COMP (Pin 14): Inverting Comparator Input. COMPOUT (Pin 15): Open Drain Comparator Output. Voutui (Pin 16): High Supply Voltage Output. This must be the higher of the two supply voltage outputs. GATEHI (Pin 17): The High Side Gate Drive for the High Supply N-Channel. An internal charge pump guarantees at least 6V of gate drive. The slope of the voltage rise at GATEHI is set by the external capacitor connected between GATEHI and RAMP. When the circuit breakertrips, GATEHI is immediately pulled to GND. SETHI (Pin 18): The Circuit Breaker Set Pin for the High Supply. With a sense resistor placed in the supply path between Vocy) and SETHI, the circuit breaker will trip when the voltage across the resistor exceeds 50mV for more than 20us. To disable the circuit breaker, Vecy) and SETHI should be shorted together. Vecui (Pin 19): The Positive Supply Input. This must be the higher of the two input supply voltages. An undervoltage lockout circuit disables the chip until the voltage at Vocu) is greater than 2.45V. Voutio (Pin 20): Low Supply Voltage Output. This must be the lower of the two supply voltage outputs. GATELO (Pin 21): The High Side Gate Drive for the Low Supply N-Channel Pass Transistor. An internal charge pump guarantees at least 10V of gate drive. The slope of the voltage rise at GATELO is set by the external capacitor connected between GATEHI and RAMP. When the circuit breaker trips GATELO is immediately pulled to GND. SETLO (Pin 22): The Circuit Breaker Set Pin for the Low Supply. With a sense resistor placed in the supply path between Vec_o and SETLO, the circuit breaker will trip when the voltage across the resistor exceeds 50mvV for more than 20us. To disable the circuit breaker, Vocio and SETLO should be shorted together. Vecio (Pin 23): The Positive Supply Input. Veco must be equal to or lower voltage than Vocy). An undervoltage lockout circuit disables the chip until the voltage at Vecio is greater than 2.45V. AUXV cc (Pin 24): The supply input for the GATELO and GATEHI discharge circuitry. Connect a 1uF capacitor to ground. AUXVc is powered from Vec_g via an internal Schottky diode and series resistor.LTC 1421/LTC1421-2.5 BLOCK DIAGRAM 23 22 19 18 24 10 17 16 20 Vec VecLo SETLO VecHI SETHI GATELO | RAMP | GATEHI | VoutHi VouTLO 24 | AUXVc f | AUXVep J CHARGE 50mV 5omv ( + ) PUMP N2] = 1] BS oe | CPt cP2 CP3 = = + [f+ > Vee | - 735k ~e2e UNDERVOLTAGE ? >> > LOCKOUT VIRIP I cP4 = h | = 115k FRY 41 VV 9 | cPON I $26.7 4.232 | REF | 8 } REFERENCE "Veg _ 20pA 20 4 | FAULT vA pwrep 6 _________| Voc DIGITAL CONTROL mL 1 | CONt = = 20uA _ 2 | coNn2 RESET | 7 __ RESET 3 | POR TIMING 5 | DISABLE o<| COMPOUT | 15 12 eno 14 comet | 13 1421 BD | ty ~< ti <__| th ~< | ty 4 j<_ t <_ ~ to <-> pts ey t7 < 9 2 com | . VecLo- SETLO | CON2 FAULT | CPON | | cpon || | PWRED | | [ PWRGD | a RESET | | RESET | ._ DISABLE Li POR | 1421 FO2 POR 1421 FO1 ae tio < te < ! tg be ! ty a tg Figure 1. Nominal Operation Switching Waveforms Figure 2. Fault Detection Switching LI WeeLTC 1421/LTC1421-2.5 APPLICATIONS INFORMATION Hot Circuit Insertion When circuit boards are inserted into alive backplane, the supply bypass capacitors on the board can draw huge transient currents from the backplane power bus as they charge up. The transient currents can cause permanent damage to the connector pins and cause glitches on the system supply, causing other boards in the system to reset. At the same time, the system data bus can be disrupted when the boards data pins make or break connection. The LTG1421 is designed to turn aboards supply voltages on and offina controlled manner, allowing the board to be safely inserted or removed from alive backplane. The chip also provides a disable signal for the boards data bus buffer during insertion or removal and provides all the necessary supply supervisory functions for the board. Power Supply Ramping The power supplies on a board are controlled by placing external N-channel pass transistors in the power path (Figure 3). R1 and R2 provide current fault detection. By ramping the gate of the pass transistor up at a controlled rate, the transient surge current (I =C dV/dt) drawn from the main backplane supply can be limited to a safe value when the board makes connection. R2 Q2 12V WW 1 Yt VoUuTHI + c3 R1 at x= VouTLo Figure 3: Supply Control Circuitry When power is first applied to the chip, the gates of both N-channels, GATELO and GATEHI are pulled low. After the connection sense pins, CON1 and CON2 are both held low for at least 20ms, a 20uA reference current is connected from the RAMP pin to GND. The voltage at GATEHI begins to rise with a slope equal to 20UA/Cramp (Figure 4), where Cramp is an external capacitor connected between the 12 VouTHI SLOPE = 20nA/CRamp 5V-- VouTLo ty to 1421 Fda Figure 4. Supplies Turning On RAMP and GATEHI pins. The voltage at the GATELO pinis clamped one Schottky diode drop below GATEHI. The ramp time for each supply is equal to: t = (Voc) (Cramp)/20uA. During power down the gates are actively pulled down by two internal NFETs. A negative supply voltage can be controlled using the CPON pin as shown in Figure 5. When the board makes connection, the transistor Q3 is turned off because its gate is pulled low to -12V by R4. CPON is also pulled to -12V. When the charge pump is turned on, CPON is pulled to Vcc, 9 and the gate of Q3 will ramp up with a time constant determined by R4, R5 and C2. When the charge pump is turned off, CPON goes into ahigh impedance state, the gate of Q3 is discharged to Ver with a time constant determined by R4 and C2, and Q3 turns off. Q3 1/2 MMDF3NOHD Ver 12V FROM -12V CONNECTOR To . te Ty [ta i > 20k 5% TL 0.047 pF ; +] 220uF 5V CPON -12V OV B 4Ne -12V e v L Vee \ -12V ~ims ~Ims 1421 FOS Figure 5. Negative Supply Control 8LTC 1421/LTC1421-2.5 APPLICATIONS INFORMATION PWRGD and RESET The LTC1421 uses a 1.232V bandgap reference, internal resistive divider and a precision voltage comparator to monitor Voytio (Figure 6). The reset threshold voltage for Voytio is determined by the FB pin connection as summarized in Table 1. VouTLo Veco Vv 73.5k 20uA comp 715k PWRGD - FB vi CPLO ff 26.7k v ' 20pA " RESET RESET REE H TIMING 128eV 1421 FOG Figure 6. Supply Monitor Block Diagram Table 1 FEEDBACK PIN Voutio RESET VOLTAGE Floating 4.65V VouTLo 2.90V GND 5.88V When the Voytio voltage rises above its reset threshold voltage, the comparator output goes low, and PWRGD is immediately pulled high to Vegio by a weak pull-up Current source or external resistor (Figure 7, time points 1 and 4). After a 200ms delay, RESET is pulled high. The weak pull-up current source to Vocio on PWRGD and RESET have aseries diode so the pins can be pulled above Veco by an external pull-up resistor without forcing current back into Vecyo. 1 2 3 4 5 we Ni ve vw vex v2\ VM VouTLo / PWRGD | | 64use| j< | <64us>! |e >| RESET ___200ms | <200ms 200ms senenr Figure 7. Power Monitor Waveforms When VoutLo drops below its reset threshold, the com- parator output goes high, and PWRGD is immediately pulled low (time point 2). After a 32us delay, RESET is pulled low. The RESET delay allows the PWRGD signal to be used as an early warning that a reset is about to occur. lf the PWRGD signal is used as a interrupt input to a microprocessor, a short power-down routine can be run before the reset occurs. If VoutLo rises above the reset threshold for less than 200ms, the PWRGD output will trip, butthe RESET output is not affected (time point 3). If Vout drops below the reset threshold forless than 32us, the PWRGD output will trip, but again the RESET output will not be affected (time point 5). Voltage Comparator The uncommitted voltage comparator (COMP2) can be used to monitor output voltages other than Voyr_o. Figure 8a shows how the comparator can be used to monitor a 12V supply (VoutH)), while the 5V supply (VoutLo) gener- ates a reset when it dips below 4.65V. When the 12V supply drops below 10.8V, COMPOUT will pull low. The FB pin is left floating. Figure 8b shows how the comparator can be used to monitor the 5V supply (Voyti) while the 3.3V supply (VouTLo) generates a reset when it dips below 2.9V. When the 5V supply drops below 4.65V, COMPOUT will pull low. The FB pin is tied to Voytio. 5V 12V Figure 8a. Monitor 12V, Reset 5V at 4.65V L) TECHNOLOGYLTC 1421/LTC1421-2.5 APPLICATIONS INFORMATION Figure 8c shows how the comparator can be used to generate a reset when the 12V supply (Voyt)) drops below 10.8V. The 5V supply (VoutLo) also generates a reset when it dips below 4.65V. When the 12V supply drops below 10.8V, COMPOUT will pull the FB pin low setting the internal threshold voltage for comparator 1 to 5.88V. Since Vout_o is less than 5.88V, PWRGD immedi- ately goes low and a reset is generated 200ms later. Figure 8d shows how the comparator can be used to override the internal reset voltage for a 5V supply on VouTLO: A vvv 6 Figure 8b. Monitor 5V, Reset 3.3V at 2.9V 12V Figure 8c. Reset 12V at 10.8V, Reset 5V at 4.65V A 5k resistor is tied from the FB pin to Voytzo, setting the internal threshold to about 2.9V. The new reset threshold voltage is set by the external resistive divider connected to COMP2. When Voyt_o drops below the new threshold, COMPOUT pulls FB to ground, changing the internal threshold at COMP1 to 5.88V and generating a reset. Finally, the comparator may be used to monitor a negative Supply as shown in Figure 8e. The external resistor divider < 102k > 1% g$ 38.3k > 1% LAA r \V-o-" Figure 8d. Reset 5V at 4.5V 5V 210k 35% 13.7k 1% 1421 FO8e 107k 1% -12V Figure 8e. Monitor -12V at -10.8V, Reset 5V at 4.65V 10LTC 1421/LTC1421-2.5 APPLICATIONS INFORMATION is connected between REF (Pin 8) and the negative supply and the trip point of Comparator 2 set to GND. Soft Reset Generation A soft reset that doesnt cycle the supply voltage can be generated externally using Pin 11 (FB) as shown in Figure 9. For a 5V supply the FB pin is left floating to set the internal supply monitor trip voltage to 4.65V. However, if the FB pinis pulled to ground for more than 64us viaa push button or open-collector logic gate, the internal trip point will go to 5.88V and the RESET pin will pull low. RESET will remain low for 200ms after the FB pin is released. The RESET signal will also be pulled low when the voltage at the VoutLo pin dips below 4.65V for more than 32us. When using a 3.3V supply, a 1k resistor must be con- nected from the FB pin to Vcc_oto set the internal trip point to 2.90V. 3.3V IC Ri USED FOR 3.3V Aa SUPPLY ONLY 1/6 LS7404 OPEN | COLLECTOR 5V O] RESET LOGIC | 64us jx RESET 1421 FOG Figure 9. Generating a Soft Reset Undervoltage Lockout On power-up, an undervoltage lockout circuit prevents the GATELO and GATEHI charge pumps from turning on until Vocio and Vecu) have both exceeded 2.45V. Electronic Circuit Breaker The LTC1421 features an electronic circuit breaker func- tion that protects against short circuits or excessive cur- rents on the supplies. By placing a sense resistor between the supply input and set pin of either supply, the circuit breaker will be tripped whenever the voltage across the sense resistor is greater than 50mV for more than 20us. When the circuit breaker trips, both N-channel MOSFETs are quickly turned off, FAULT and PWRGD go low and RESET is pulled low 32us later. FAULT can be connected toaLED oralogic signal back to the host to indicate a faulty board. The chip will remain in the tripped state until a power-on reset is generated, or the power on Vecy) and Vecto is cycled. If the circuit breaker feature is not used, short Vec_g to SETLO and Vocy) to SETHI. If more than 20us of response time is needed to reject Supply noise, an external resistor and capacitor can be added to the sense circuit as shown in Figure 10. RSENSE at AAA. eS 1yI Figure 10. Short-Circuit Protection Circuit Auxiliary Voc When a short circuit occurs on the board, it is possible to draw enough current to cause the backplane supply voltage to collapse. Ifthe input supply voltage collapses to alow enough voltage and the LTC1421 gate drive circuitry is unable to shut off the N-channel pass transistors, the system might freeze up in a permanent short condition. To prevent this from occurring, the gate discharge cir- cuitry inside the LTC1421 is powered from AUXVc, which is in turn powered from Vec_g through an internal Schottky diode and current limiting resistor (Figure 11). Veco GATELO GATEHI AUXVec Figure 11. AUXVg Circuitry LI Wee 11LTC 1421/LTC1421-2.5 APPLICATIONS INFORMATION When Vec_g collapses, there is enough energy stored on the 1pF capacitor connected to AUXVec to keep the gate discharge circuitry alive long enough to fully turn off the external N-channels. Power N-Channel Selection The Rpgion) of the external pass transistor must be low enough so that the voltage drop across it is about 200mV or less at full current. If the Rosin) is too high, the voltage drop across the transistor might cause the output voltage to trip the reset circuit. Table 2 lists the transistors that are recommended for use with the LTC1421. Table 2. N-Channel Selection Guide CURRENT PART LEVEL (A) NUMBER MANUFACTURER | DESCRIPTION Oto 1 MMDF2N02E Motorola Dual N-Channel SO-8 Rps(on) = 9.12 1to2 MMDF3NO2HD Motorola Dual N-Channel SO-8 Ros(on) = 0.09 2to5 MTB30N06 Motorola Single 30A N-Channel DD Pak Ros(on) = 0.050 5 to 10 MTBDbONOG6E Motorola Single N-Channel DD Pak Ros(on) = 9.0250 10 to 20 MTB75NO5HD Motorola Single N-Channel DD Pak Ros(on) = 0.00952 Data Bus When a board is inserted or removed from the host, care must be given to prevent the system data bus from being corrupted when the data pins make or break contact. One problem is thatthe fully discharged input or output capaci- tance of the logic gates on the board will draw an inrush current when the data bus pins first make contact. The inrush current can temporarily corrupt the data bus, but usually will not cause long term damage. The problem can be minimized by insuring the input or output data bus capacitance is kept as small as possible. The second, and more serious problem involves the diodes to Voc at the input and output of most logic families (Figure 12). DATA BUS CONNECTOR BACKPLANE Figure 12. Typical Logic Gate Loading the Data Bus R14 ai 0.005 MTBSONOGE 5V Vec +) 4 23 22_ [21 |20 [> 2200uF I 083384 Vee 13 SYSTEM 4 BOARD DATA BUS r DATA BUS CONNECTOR 1421 F13 Figure 13: Buffering the Data Bus With the board initially unpowered, the Vcc input to the logic gate is at ground potential. When the data bus pins make contact, the bus line is clamped to ground through the input diode D1 to Voc. Large amounts of current can flow through the diode and cause the logic gate to latch up and destroy itself when the power is finally applied. This 12LTC 1421/LTC1421-2.5 APPLICATIONS INFORMATION can usually be prevented by using logic that does not include the clamping diodes such as the QSI 74FCTT family from Quality Semiconductor, or by using adata bus switch such as the 10-bit Q$3384 QuickSwitch also from Quality Semiconductor (Tel: 408-450-8000). The QuickSwitch bus switch contains an N-channel placed in series with the data bus. The switch is turned off when the board is inserted and then enabled after the power is stable. The switch inputs and outputs do not have a parasitic diode back to Voc and have very low capacitance. The LTC1421 is designed to work directly with the QuickSwiich bus switch as shown in Figure 13. The DISABLE signal is connected to the enable pins of the QS3384, and each switch is placed in series with a data bus signal. When the board is inserted, the DISABLE signal is pulled high, turning off the switches. After the board supply voltage ramps up and RESET goes high, DISABLE will pull low enabling the switches. Board Insertion Timing When the board is inserted, GND pin makes contact first, followed by Vecu) and Vccio (Figure 14, time point 1). DISABLE is immediately pulled high, so the data bus switch is disabled. Atthe same time CON1 and CON2 make contact and are shorted to ground on the host side (time point 3). Since most boards need to be rocked back and forth to get them in place, there is a period of time when only one side of the connector is making contact. CON1 and CON2 should be located at opposite ends of the connector. ao] 1 2 00 4 5 6 <_os 200ms > VecLo y VocHi | DISABLE y CONT Wi CON2 CPON GATEHI VouTHI GATELO _ VouTLo ee TH PWRGD RESET FAULT POR 1421 P14 Figure 14. Board Insertion Timing 13LTC 1421/LTC1421-2.5 APPLICATIONS INFORMATION When CON1 and CON2 are both forced to ground for more than 20ms, the LTC1421 assumes that the board is fully connected to the host and power-up can begin. When Vecto and Vcc; exceed the 2.45V undervoltage lockout threshold, the 20yA current reference is connected from RAMP ito GND, the charge pumps are turned on and CPON is forced high (time point 4). VoytH) and Voytio begin to ramp up. When Voytio exceeds the reset threshold volt- age, PWRGD will immediately be forced high (time point 5). After a 200ms delay, RESET will be pulled high and DISABLE will be pulled low, enabling the data bus (time point 6). Ground Sense Comparator When POR is pulled low for more than 20ms, GATELO and GATEHI are pulled to ground and Voutio and Voyty) will be discharged. If POR is pulled back high while VoytLo and VoytH) are still ramping down, the discharge will continue. When they drop below the Vp jp point, a power- up sequence will begin automatically. The trip point poten- tial for LTC1421 is set at 0.1V and 2.5V for LTC1421-2.5, In applications, where either Voytio Or VoutH) might be forced above 100mV before power-up, the LTC1421-2.5 should be used. This could occur when leakage through the body diode of the logic chips keeps Voyt_o high or in the case where logic lines are precharged. In other applications, where outputs need to drop to near ground potential before ramping up again to ensure proper initial state for the logic chips, the LTC1421 should be used. Power-On Reset Timing The POR input is used to completely cycle the power supplies on the board or to reset the electronic circuit breaker feature. The POR pin can be connected to a grounded push button, toggle switch or a logic signal from the host. When POR is pulled low for more than 20ms, a power-on reset sequence begins (Figure 15, 1 2 3 5 6 7 20ms 200ms | 32us Voc! VecLo DISABLE CON1 CON2 CPON Le GATEHI | VoutHI NM Le | GATELO I Ls VoutLo Vino TQ TH PWRGD RESET FAULT POR W NW | | Figure 15. Power-On Reset Timing 14LTC 1421/LTC1421-2.5 APPLICATIONS INFORMATION time point 2). Pulses less than 20ms on POR are ignored. CPON goes low. Both GATEHI and GATELO will be actively pulled down to GND. When Voytio drops below its reset threshold voltage, PWRGD will immediately pull low (time point 3) followed by RESET and DISABLE 32us later (time point 4). Both supplies will be discharged to ground and stay there until POR is pulled high. The circuit breaker can be reset by pulling POR low. After POR is low for more than 20ms, the chip will immediately try to power up the supplies. Circuit Breaker Timing The waveforms for the circuit when a short occurs on either supply during board insertion are shown in Figure 16. Time points 1 to 4 are the same as the board insertion example, but at time point 5, a short circuit is detected on one of the supplies. The charge pumps are immediately turned off, the outputs VoytH) and VoytLo are actively pulled to GND and the CPON and FAULT pins are pulled low. At time point 6, the circuit breaker is reset by pulling POR low. After POR has been low for 20ms (time point 7), CPON and FAULT are pulled high, the 20uA reference current is connected to RAMP and the charge pumps are enabled. Voyty) and Vout_o ramp up at a controlled rate. When Voytio has exceeded its reset threshold, the PWRGD signal is pulled high (time point 8). After a 200ms delay, RESET is pulled high and DISABLE goes low. 1 2 4 5 7 8 9 20ms 20ms 200ms VecLo y VecHI | DISABLE y CON1 Wi CON2 CPON GATEHI \ L VouTHI oN GATELO NN | VouTLo | \ Vtu4 PWRGD RESET FAULT POR Mi Ml Figure 16. Circuit Breaker Timing 15LTC 1421/LTC1421-2.5 APPLICATIONS INFORMATION Board Removal Timing When the board is removed from the host, the sequence happens in reverse (Figure 17). Since CON1 and CON2 are the shortest pins, they break connection first and are internally pulled high (time point 1). The charge pumps are turned off, CPON is pulled low. Voyt_o and Vout) are actively pulled down. When Voyt_o falls below its reset threshold (time point 2) PWRGD is pulled low. To allow 1 2 8 >| 32us |j Vecto \ time for power fail information to be stored in nonvolatile memory, the falling edge of RESET (time point 3) is delayed by 32us from the falling edged of PWRGD. Finally, the input supply pins Vocy; and Vecio break contact (time point 4). If staggered pins are not used, the board may be powered down prior to removal by switch- ing the POR pin to ground with a toggle switch. VecHi \ DISABLE \ Cont NW om | MW CPON GATEHI | VouTHI /-_] GATELO \ oo VoutLo Vio PS PWRGD RESET FAULT | POR | 1421 7 Figure 17. Board Removal Timing 16LTC 1421/LTC1421-2.5 APPLICATIONS INFORMATION 5V Only Applications The LTC1421 may be used in 5V only applications as shown in Figure 18. A soft reset can be generated from the backplane via an open-collector inverter driving the FB (Pin 11) or by a push button to ground. A hard power reset is generated from the backplane viaan open-collector inverter driving the POR (Pin 3). A hard reset cycles the power on the board or resets the electronic circuit breaker. The comparatoris used to monitorthe board supply voltage and R1 It. = v= 0.0052 1W = MTBSONOGE will pull the POWERGOOD signal low as long as the supply remains above 4.65V. Note that a soft reset will not affect the POWERGOOD signal. The FAULT signal is also moni- tored to determine that the circuit breaker has tripped. -48V and 24V Applications The LTC1421 may be used in 48V applications as shown in Figure 19. The LTC1421 provides the hot insertion protection, while the 5V supply is generated by a power ai POWERGOOD an =e 5V LOGIC RESET i SOFT RESET a 16 LS7004 HARD RESET a ] a i o 1421 F18 se | | = BACKPLANE | PC BOARD Figure 18. 5V Only Application with Soft Reset ai ev Th IRFR9110 1 3 sy [Tr = Tl +IN +OUT OA ASTRODYNE +] 04 ASD 10-4885 100uF -IN -OUT tev CONTROL 6 LS be] 1 00,F 100V 1421 F19 48 4 oe STAGGERED CONNECTOR BACKPLANE PC BOARD Figure 19. -48V to 5V Hot Swappable Supply L) TECHNOLOGY 1/7LTC 1421/LTC1421-2.5 APPLICATIONS INFORMATION module. The ground pin for the LTC1421 is connected to 48V: Zener diode D1 and resistor R1 provide the positive supply for the chip. Bypass capacitor C4 is protected against inrush current by P-channel Q1. When the board is inserted into the backplane, transistor Q1 is turned off by resistor R2. When the connection sense pins, CON1 and CON2 have been connected to 48V for more than 20ms, CPON pulls high turning on Q2 and the gate of Q1 Starts to pull low with a time constant determined by R2, R3 and C3. Atthe same time, the voltage at the input to the power module starts to ramp up. When the voltage across the inputs to the power module reaches the comparator trip level set by R5 and R6, in this case 32V, the comparator output pulls high and turns on the 5V supply. A cheaper solution is shown in Figure 20 using the LT1170HV switcher. Again P-channel transistor Q1 pro- tects the bypass capacitors against inrush current and resistors R5 and R6 set the comparator trip voltage. The LT1170HV is turned on via the V pin. Resistors R11, R14 and transistor Q4 provide a monitoring path forthe RESET signal which is level shifted up to 5V through an optoiso- lator. The P-channel power FET is being replaced by an N-channel FET in Figure 21 for the 48V application. Again, Zener Diode D1 and resistor R1 provide the positive supply for the chip. Capacitor C1 is to insure Q1 stays off when the board is being hot inserted into the backplane. The resistor divider R1 and R2, along with the internal comparator, perform the undervoltage lock out function. Q1 would only be turned on when the input supply voltage is lower than 42V. The power module would then be turned on by the optoisolator, 4N25, when the modules input voltage reaches 47V. Figure 22 shows how to use the LTC1421 with a 24V supply andaLT1074CT step-down switcher. Resistors R5 and R6 set the turn-on threshold to 22V. All of the Supervisory signals can be used without level shifting. Figure 23 shows how to use the LTC1421 with a5V supply and an LTC1430CS8 synchronous step-down switching regulator to generate 3.3V output at up to 10A for micro- processors. Resistors R4, R8 and R9 set the turn-on voltage at 4.8V and the turn-off at 4.25V. Pushbutton switch $1 provides users a way to reset the output while S2 is used to soft-reset the microprocessor only. Figure 24 shows how to use the LTC1421 with a5V supply and a48V supply that is used to generate a+12V supply using a supply module. Resistors R3 and R4 are used to monitor the input voltage to the supply module. The module is prevented from turning on via the optoisolator until the input voltage reaches 36V. Zener diode D2 prevents the CPON pin of the LTC1421 from being dam- aged by excessive voltage. Figure 25 shows how to use the LTC1421 to do overvolt- age protection. Resistors R3 and R4 set the trip point at 7\V. When the input supply voltage rises above 7V, Q2 is turned on and Q1 turned off while Q3 helps to discharge the output voltage. Figure 26 shows how to use the LTC1421 to control both the power-up and power-down sequence of the outputs. The 5V output would be powered up first followed by the 3V output. At power-down sequence, the 3V output would go down first followed by the 5V supply. Figure 27 shows how to use the LTC1421 to switch 3.3V, 5V, 12V and -12V supplies for PCI application. The ramp- up rate for 3.3V, 5V and 12V is determined by the ramp capacitor C2 while the 12V supply is controlled by R7 and C3. The internal comparator is being used to do the overcurrent protection for Q4 with the trip point set by resistors R6 and R8. The -12V supply does not have overcurrent protection. R10 is used to set the power good signal trip point at 10V. When the 12V output rises above 10V, the PCI controller gets a power good signal followed by RESET after 200ms. 18LTC 1421/LTC1421-2.5 APPLICATIONS INFORMATION LOAHOLLLLT 84) Guisp Ajddng ajqeddems oH AS 0} ASP- Oz aun, ANV1dyOVa YOLOANNOD C4YINNVLS ed ber nos dnge'9 = 69 | MS/L& MEL Ma/L & = HOPS Wels S| re mel & rly clu 6u Rz G00r hf Me/L = | ILS 90VSdIN ou) Mat zy 10LS cue MZ/L On L- os S Mel g a aNd + ey gt] Zt] et Ol > = Lopsne OOLeYaIN g * < zu Tt ; ror ra LOAHOZLLLT AGZ | o-fte-e ius $9001 S>* sriogor MBIT Melt J vl 09, 90 15 z WeerS xe VE 9 Ly ool F AOOL mart ASZ My coleuaw | ASZ 4001 = > Lye Se snez A ed cd 99 | vo [+ JI ZH > + 9 Hv190 | OLLGHSYI H 10 VV m- A8v- mw Acv- Ln tt 19LTC 1421/LTC1421-2.5 APPLICATIONS INFORMATION l l -48) - i : tr" | !'|s = l 5V 5 10A ! 545k = Gt + IP]. 5 VICOR i & 100,F == VI-J30-CY 100,F 1/8 I S ~ GATEIN I I ira I & oO ! = I a | l ! 14148 wet ANOS l a : -48V sun I : I 1421 F21 BACKPLANE PG BOARD Figure 21. 48V to 5V Hot Swappable Supply l I ai Lt CT Tey IRFRO110 5 4 50H 5V = 24V-H l i VIN Vow > I C3 +] 2 Re itl +] C4 vane ek 5A L Rt hy Z vaw T~ 50v LT1O74CT MBR745$ 4% +) 65 I 25k Wc FB 500pF I rs GND bane 25V I 2 2.21k I D1 py + 3 J 1% 1 | || 2 I S brs brs = I a = R44 BHCK 10k I 2 3002 1e8Ww F 1/2W 1 8 VEW p99 I 9 MPSAQ6 1 | & + I} 2 I ue 26 _ I a = 26202 FAULT | I = 7 1/38w _ l Porm | Fo I O > 27k I St 4 +L cB = n i T 0.01 pF 1421 F22 HH. I 7 = l BACKPLANE PC BOARD Figure 22. 24V to 5V Hot Swappable Supply Using the LT1074CT 20LTC 1421/LTC1421-2.5 WGI. = XVI] VOL AGE APPLICATIONS INFORMATION 8S90E71917 91 Guisy Ajddng ajqeddems joH Age 0} AG Ez aanbi4 F AC = I 440 ASZ'P NO AS"? :CIOHSAYHL dN-W3MOd OSPLOLT GuvOd od 4 aNVTdNOvE cain LaS3Y L408 2S I = LASTY YANVING LINOUIO/YAMOd GVH :1S [a i Pe . e l a = AgL I gy dT, oH I ans Lao ove | 9 | os I 13834 foo Te see sdozz == ob I = 89 I fl d THeowozan BIL ounvua0 | 29, ddoosy 4 I WSL Zz eSO0EPLOLI 19 =| | 25 aNd 8 & LY a ai diN0D + 2 THEONOZCLW Pot | Z eD > I rp i? NGHS Fe - Ww & I sto ah SA e2 | 001 3] 1 99 4) agi AOL ou I ang ano %S & I Ly avin or 9 101 S I pop 9 | yw Jo i Fixeonozaiw usb ASL % zd oS srozz 1292 J ut 0 [* 6u | : : MW a| | THEONOZGLW | ML'%S I LD g00'0 . i LY I AAA wv ME%S GL00 zu 21LTC 1421/LTC1421-2.5 APPLICATIONS INFORMATION Rt Ls 0.0052 a [ I : iw MTB5ONO6E = V-e I n A 5V xi 4 5 200uF " l R7 rn je I Sik =" 16V ? 1/3w . rin sours tv +/+] co +[_ c7 (042A = 220uF ASTRODYNE 100uF 1 Tov | ASD10-48D12 <= iv I] -IN -ouT Rae oun 1} CONTROL tc i |e 100,F 1/2 +] tev oO I 3S = 1 | 8 wet I & I < I ih l l l i ee = l I L Rd I > 10k I > 1/8W -48V I | | 1421 F24 I IRF530 cr |! * = l BACKPLANE 4 PC BOARD Figure 24. 5V and 48V to +12V Hot Swappable Supply I Rt I 0.0052 a Cc. I . 1/2 MTBSONO6E SV _ AAA a o a. = = 5-H I a VV L l 8A =" ; | yN2200 eye s 16V i 0 1203 Ftr000 al ; T . I vN2222 = 2R3 = I rm $475k l tc ft | + 1 | s ae I a = I S S | Oo Voc 1) 2 l o uP I | 2 ho RESET l a I GND | , l I e RA I > 10k l a I = j 1421 F25 ey]. = l BACKPLANE PC BOARD Figure 25. Hot Swappable 5V Supply with Overvoltage Protection 22 LY WyeLTC 1421/LTC1421-2.5 APPLICATIONS INFORMATION | R2 0.005 Q2 Cc. * 7 1W MTBSONOBE 5V = 5-H a AWW | | dvt +] ca BA I 2200uF 1 i | LBs Die I 0.005 ai 1M iW MTBSONO6E O.047HF $ oo, saw ay Vvs : W* . a BA I 4 2200yF i Liev +] 5 = O1uF | pg fn | C2 a 24V , I} e Oipe} | = 3 30k 1 | 2 , RA 1 iiew I 5 2tk Voc I 3G 25% I 8 16w uP I 3 Oy RESET lle I a GND l ! e S 200k | 5% a} | ie 1ew a I : el l 1421 F26 BACKPLANE PC BOARD Figure 26. Power-Up and Power-Down Sequence Controller PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted. G Package 24-Lead Plastic SSOP (0.209) (LTC DWG # 05-08-1640) 0.319 - 0.328" 0.205 - 0.212** (8.07 8.33) (6.20 - 6.38) 7 ee toar 24 23 22 24 f aa 17 16 15 4 18 | Ly ATT : i Sy 0.301 - 0.311 0,005 - 0,009 0.022 - 0,037 | Le t pozse | |e (7-65 7-90) (0.13- 0.22) (0.55 0.95) bse o.oo? - 0.008 0.010 0.015 yf ig (0.06 0.21) O DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH (0.25 0.38) SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSIONS DO NOT INGLUDE INTERLEAD FLASH. INTERLEAD d ul Hq d q q ql q q br ql br ~ FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE G24 SSOP 0595 SW Package 24-Lead Plastic Small Outline (Wide 0.300) (LTC DWG # 05-08-1620) 0.291 0.299** 0.598 0.614* (7.391 7.595) (15.190 15.600) - 0.037 0.045 0.010 0,029 0.093 0,104 decor (2.362 2.642) (0.940 1.143) 20 19 18 17 16 15 14 13 ore) 4 HOHE EHHHHE EY L 4 TYR Eee eee eee eae eS J ms, wot Ay i \ 0.050 _s| le NOTE 1 tLe _0394-0.419_ 1 vp \ / 10.007 - 10.643 0,009 - 0.013 Vo - (10. 643) (0.229 - 0.330) 0.014-0.019 Ny | (0408-1 270) toon : 70) (0.356 0.482) 0.004 0,012 ( NOTE: TYP (0.102 0,305) - 1. PIN 1 IDENT, NOTGH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS, THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS O O O *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXGEED 0.006" (0.152mm) PER SIDE 7 2 3 **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 824 (WIDE) 0995 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. f y | INEAR However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- TECHNOLOGY tation that the interconnection ofits circuits as described herein will not infringe on existing patent rights. CY oT ~CO CT 7 iN)LTC 1421/LTC1421-2.5 TYPICAL APPLICATION PCI Q3 CONNECTOR 1/2 IRF7101 12V 12V 500mA 3.3A CIRCUIT BREAKER R4 302 R11 109 5% a4 IRF7413 3.3V 75A 3.3V 11.5A CIRCUIT BREAKER 5V 10A CIRCUIT BREAKER 5V 5A Qi IRF7413 R12 10Q 21 22 20 419 FAULT ON/OFF PCI POWER CONTROLLER POWER GOOD RST # SELECT BITS BUS ENABLE QuickSwitch DATA BUS 5 ALL RESISTORS 5%, 1/16W EXCEPT WHERE NOTED teoetoT 12V NO CIRCUIT BREAKER -12V 100mA Q2 1/2 IRF7101 MOTHERBOARD OR BACKPLANE PCI PERIPHERAL 1421 F27 Figure 27. PC] Power Controller RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1155 Dual High Side Switch Driver Short-Circuit Protection and Micropower Standby Operation LTC1477/LTC1478 Single and Dual Protected High Side Switches Inrush Current Limited, Built-In 2A Short-Circuit Protection 142125fa LT/TP 1098 2K REV A+ PRINTED IN USA 2 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 AL) LINGAR (408)432-1900FAX: (408) 434-0507 www.linear-tech.com @ LINEAR TECHNOLOGY CORPORATION 1996