AFBR-5805Z/5805TZ/5805AZ/5805ATZ
ATM Transceivers for SONET OC-3 / SDH STM-1
in Low Cost 1 x 9 Package Style
Data Sheet
Features
Full compliance with ATM forum UNI SONET OC-3 mul-
timode ber physical layer speci cation
Multisourced 1 x 9 package style with choice of duplex
SC or duplex ST* receptacle
Wave solder and aqueous wash process compatibility
Manufactured in an ISO 9002 certi ed facility
Single +3.3 V or +5.0 V power supply
RoHS Compliance
Applications
Multimode ber ATM backbone links
Multimode ber ATM wiring closet to desktop links
Description
The AFBR-5800Z family of trans ceivers from Avago Tech-
nologies provide the system designer with products
to implement a range of solutions for multimode ber
SONET OC-3 (SDH STM-1) physical layers for ATM and
other services.
The transceivers are all supplied in the industry standard
1 x 9 SIP package style with either a duplex SC or a duplex
ST* connector interface.
ATM 2 km Backbone Links
The AFBR-5805Z/-5805TZ are 1300 nm products with
optical performance compliant with the SONET STS-3c
(OC-3) Physical Layer Interface Speci cation. This physical
layer is de ned in the ATM Forum User-Network Inter face
(UNI) Speci cation Version 3.0. This document references
the ANSI T1E1.2 speci cation for the details of the inter-
face for 2 km multimode ber backbone links.
The ATM 100 Mb/s-125 MBd Physical Layer interface is
best implemented with the AFBR-5803 family of Fast Eth-
ernet and FDDI Transceiv ers which are speci ed for use in
this 4B/5B encoded physical layer per the FDDI PMD stan-
dard.
2
Transmitter Sections
The transmitter section of the AFBR-5803Z and AFBR-
5805Z series utilize 1300 nm InGaAsP LEDs. These LEDs
are packaged in the optical subassembly portion of the
transmitter section. They are driven by a custom silicon IC
which converts di erential PECL logic signals, ECL refer-
enced (shifted) to a +3.3 V or +5.0 V supply, into an analog
LED drive current.
Receiver Sections
The receiver section of the AFBR-5803Z and AFBR-
5805Z series utilize InGaAs PIN photo diodes coupled to
a custom silicon transimpedance preampli er IC. These
are packaged in the optical subassem bly portion of the
receiver.
These PIN/preampli er combina tions are coupled to
a custom quantizer IC which provides the nal pulse
shaping for the logic output and the Signal Detect func-
tion. The data output is dif-ferential. The signal detect
output is single-ended. Both data and signal detect
outputs are PECL compat ible, ECL referenced (shifted) to
a 3.3 V or +5.0 V power supply.
Package
The overall package concept for the Avago Technologies
transceivers consists of three basic elements; the two
optical subassemblies, an electrical subassembly and the
housing as illustrated in Figure 1a and Figure 1b.
The package outline drawing and pin out are shown in
Figures 2a, 2b and 3. The details of this package outline
and pin out are compliant with the multi source de nition
of the 1 x 9 SIP. The low pro le of the Avago Technologies
transceiver design complies with the maximum height
allowed for the duplex SC connector over the entire
length of the package.
The optical subassemblies utilize a high volume assem-
bly process together with low cost lens elements which
result in a cost e ective building block.
The electrical subassembly con sists of a high volume
multilayer printed circuit board on which the IC chips and
various surface-mounted passive circuit elements are at-
tached.
The package includes internal shields for the electrical
and optical subassemblies to ensure low EMI emissions
and high immunity to external EMI elds.
The outer housing including the duplex SC connector or
the duplex ST ports is molded of lled nonconductive
plastic to provide mechanical strength and electrical iso-
lation. The solder posts of the Avago Technologies design
are isolated from the circuit design of the transceiver
and do not require connection to a ground plane on the
circuit board.
The transceiver is attached to a printed circuit board with
the nine signal pins and the two solder posts which exit
the bottom of the housing. The two solder posts provide
the primary mechanical strength to withstand the loads
imposed on the trans ceiver by mating with duplex or
simplex SC or ST connectored ber cables.
Figure 1a. SC Connector Block Diagram
TOP VIEW
PIN PHOTODIODE
DUPLEX SC
RECEPTACLE
OPTICAL
SUBASSEMBLIES
LED
PREAMP IC
DATA OUT
SIGNAL
DETECT OUT
DATA IN
ELECTRICAL SUBASSEMBLY
QUANTIZER IC
DRIVER IC
DIFFERENTIAL
SINGLE-ENDED
DIFFERENTIAL
3
Figure 2a. Package Outline Drawing
DATA OUT
SIGNAL
DETECT OUT
DATA IN
ELECTRICAL SUBASSEMBLY
QUANTIZER IC
DRIVER IC
TOP VIEW
PIN PHOTODIODE
DUPLEX ST
RECEPTACLE
OPTICAL
SUBASSEMBLIES
LED
PREAMP IC
DIFFERENTIAL
SINGLE-ENDED
DIFFERENTIAL
39.12
(1.540) MAX.
AREA
RESERVED
FOR
PROCESS
PLUG
12.70
(0.500)
25.40
(1.000) MAX. 12.70
(0.500)
10.35
(0.407) MAX.
3.30 ± 0.38
(0.130 ± 0.015)
2.92
(0.115)
20.32
(0.800) [8x(2.54/.100)]
23.55
(0.927)
16.70
(0.657)
0.46
(0.018)
NOTE 1
(9x)Ø
NOTE 1
0.87
(0.034) 23.24
(0.915)
15.88
(0.625)
Note 1: Phosphor bronze is the base material for the posts & pins. For lead-free soldering, the solder posts
have Tin Copper over Nickel plating, and the electrical pins have pure Tin over Nickel plating.
DIMENSIONS ARE IN MILLIMETERS (INCHES).
+ 0.08
– 0.05
+ 0.003
– 0.002
0.75
(0.030 )
)
6.35
(0.250)
5.93 ± 0.1
(0.233 ± 0.004)
20.32
(0.800)
17.32
(0.682
23.32
(0.918)
18.52
(0.729)
4.14
(0.163
+ 0.25
– 0.05
+ 0.010
– 0.002
1.27
(0.050
Case Temperature
Measurement Point
Figure 1b. ST Connector Block Diagram.
4
25.4
(1.000) MAX.
24.8
(0.976)
42
(1.654) MAX.
5.99
(0.236)
12.7
(0.500)
12.0
(0.471) MAX.
0.5
(0.020)
3.3 ± 0.38
(0.130 ± 0.015)
+ 0.08
- 0.05
+ 0.003
- 0.002
+ 0.25
- 0.05
+ 0.010
- 0.002
20.32 ± 0.38
(± 0.015)
2.6 ±0.4
(0.102 ± 0.016)
2.6
(0.102)
Ø
22.86
(0.900)
20.32
(0.800) [(8x (2.54/0.100)] 17.4
(0.685)
21.4
(0.843)
20.32
(0.800)
3.6
(0.142) 1.3
(0.051)
23.38
(0.921)
18.62
(0.733)
Note 1: Phosphor bronze is the base material for the posts & pins. For lead-free soldering, the solder posts
have Tin Copper over Nickel plating, and the electrical pins have pure Tin over Nickel plating.
DIMENSIONS IN MILLIMETERS (INCHES).
(
(
( )
0.46
(0.018)
NOTE 1
Ø
1.27
(0.050)
Case Temperature
Measurement Point
1 = VEE
2 = RD
3 = RD
4 = SD
5 = VCC
6 = VCC
7 = TD
8 = TD
9 = VEE
TOP VIEW
N/C
N/C
Rx
Tx
Figure 3. Pin Out Diagram.
Figure 2b. ST Package Outline Drawing
5
Figure 4. Optical Power Budget at BOL versus
Fiber Optic Cable Length.
Application Information
The Applications Engineering group in the Avago Tech-
nologies Fiber Optics Communication Division is avail-
able to assist you with the technical under standing and
design trade-o s associated with these trans ceivers. You
can contact them through your Avago Technologies sales
representative.
The following information is provided to answer some of
the most common questions about the use of these parts.
Transceiver Optical Power Budget versus Link Length
Optical Power Budget (OPB) is the available optical power
for a ber optic link to accommodate ber cable losses
plus losses due to in-line connectors, splices, optical
switches, and to provide margin for link aging and un-
planned losses due to cable plant recon guration or
repair.
Figure 4 illustrates the pre dicted OPB associated with the
transceiver series speci ed in this data sheet at the Begin-
ning of Life (BOL). These curves represent the attenuation
and chromatic plus modal dispersion losses associated
with the 62.5/125 μm and 50/125 μm ber cables only.
The area under the curves represents the remaining OPB
at any link length, which is available for overcoming non-
ber cable related losses.
Avago Technologies’ LED technol ogy has produced 1300
nm LED devices with lower aging characteristics than nor-
mally associated with these technologies in the industry.
The industry conven tion is 1.5 dB aging for 1300 nm LEDs.
The Avago Technologies 1300 nm LEDs are speci ed to
experience less than 1 dB of aging over normal commeri-
cal equipment mission life periods. Contact your Avago
Technologies sales repre sentative for additional details.
Figure 4 was generated for the 1300 nm transceivers with
a Avago Technologies ber optic link model containing
the current industry conventions for ber cable speci ca-
tions and the draft ANSI T1E1.2. These optical parameters
are re ected in the guaranteed performance of the trans-
ceiver speci cations in this data sheet. This same model
has been used extensively in the ANSI and IEEE commit-
tees, including the ANSI T1E1.2 committee, to establish
the optical performance require ments for various ber
optic interface standards. The cable parameters used
come from the ISO/IEC JTC1/SC 25/WG3 Generic Cabling
for Customer Premises per DIS 11801 docu ment and the
EIA/TIA-568-A Commercial Building Telecom munications
Cabling Standard per SP-2840.
OPTICAL POWER BUDGET (dB)
0
FIBER OPTIC CABLE LENGTH (km)
0.5 1.5 2.0 2.5
12
10
8
6
4
2
1.00.3
AFBR-5805Z, 62.5/125 μm
AFBR-5805Z
50/125 μm
6
Figure 6. Bit Error Rate vs. Relative Receiver Input
Optical Power.
Transceiver Jitter Performance
The Avago Technologies 1300 nm transceivers are de-
signed to operate per the system jitter allocations stated
in Table B1 of Annex B of the draft ANSI T1E1.2 Revision 3
standard.
The Avago Technologies 1300 nm transmitters will toler-
ate the worst case input electrical jitter allowed in Annex
B without violating the worst case output jitter require-
ments.
The Avago Technologies 1300 nm receivers will toler-
ate the worst case input optical jitter allowed in Annex
B without violating the worst case output electrical jitter
allowed.
The jitter speci cations stated in the following 1300 nm
transceiver speci cation tables are derived from the
values in Tables B1 of Annex B. They represent the worst
case jitter contribution that the trans ceivers are allowed
to make to the overall system jitter without violating the
Annex B allocation example. In practice the typical con-
tribution of the Avago Technologies trans ceivers is well
below these maximum allowed amounts.
Transceiver Signaling Operating Rate Range and BER
Performance
For purposes of de nition, the symbol (Baud) rate, also
called signaling rate, is the reciprocal of the symbol time.
Data rate (bits/sec) is the sym bol rate divided by the en-
coding factor used to encode the data (symbols/bit).
When used in 155 Mb/s SONET OC-3 applications the
perform ance of the 1300 nm transceivers, AFBR-5805 is
guaranteed to the full conditions listed in product speci-
cation tables.
The transceivers may be used for other applications at
signal ing rates di erent than 155 Mb/s with some varia-
tion in the link optical power budget. Figure 5 gives an
indication of the typical performance of these products at
di erent rates.
These transceivers can also be used for applications
which require di erent Bit Error Rate (BER) performance.
Figure 6 illustrates the typical trade-o between link BER
and the receivers input optical power level.
Figure 5. Transceiver Relative Optical Power Budget
at Constant BER vs. Signaling Rate.
TRANSCEIVER RELATIVE OPTICAL POWER BUDGET
AT CONSTANT BER (dB)
0 200
0
SIGNAL RATE (MBd)
25 75 100 125
2.5
2.0
1.5
1.0
175
0.5
50 150
CONDITIONS:
1. PRBS 2
7
-1
2. DATA SAMPLED AT CENTER OF DATA SYMBOL.
3. BER = 10
-6
4. T
A
= +25° C
5. V
CC
= 3.3 V to 5 V dc
6. INPUT OPTICAL RISE/FALL TIMES = 1.0/2.1 ns.
0.5
BIT ERROR RATE
-6 4
1 x 10 -2
RELATIVE INPUT OPTICAL POWER - dB
-4 2-2 0
1 x 10 -4
1 x 10 -6
1 x 10 -8
1 x 10 -10
1 x 10 -11
CONDITIONS:
1. 155 MBd
2. PRBS 2 7-1
3. CENTER OF SYMBOL SAMPLING
4. T A = +25°C
5. V CC = 3.3 V to 5 V dc
6. INPUT OPTICAL RISE/FALL TIMES = 1.0/2.1 ns.
1 x 10 -12
1 x 10 -9
1 x 10 -7
1 x 10 -5
1 x 10 -3
CENTER OF SYMBOL
AFBR-5805Z SERIES
7
Figure 7. Recommended Decoupling and Termination Circuits
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NO INTERNAL CONNECTION NO INTERNAL CONNECTION
AFBR-5805Z
TOP VIEW
V
EE
RD RD SD V
CC
V
CC
TD TD V
EE
123456789
C1 C2
L1 L2 R2 R3
R1 R4
C5
C3 C4
R9
R10
V
CC
FILTER
AT V
CC
PINS
TRANSCEIVER
R5 R7
R6 R8
C6
RD RD SD V
CC
TD TD
TERMINATION
AT PHY
DEVICE
INPUTS
NOTES:
THE SPLIT-LOAD TERMINATIONS FOR ECL SIGNALS NEED TO BE LOCATED AT THE INPUT
OF DEVICES RECEIVING THOSE ECL SIGNALS. RECOMMEND 4-LAYER PRINTED CIRCUIT
BOARD WITH 50 OHM MICROSTRIP SIGNAL PATHS BE USED.
R1 = R4 = R6 = R8 = R10 = 130 OHMS FOR +5.0 V OPERATION, 82 OHMS FOR +3.3 V OPERATION.
R2 = R3 = R5 = R7 = R9 = 82 OHMS FOR +5.0 V OPERATION, 130 OHMS FOR +3.3 V OPERATION.
C1 = C2 = C3 = C5 = C6 = 0.1 µF.
C4 = 10 µF.
L1 = L2 = 1 µH COIL OR FERRITE INDUCTOR.
TERMINATION
AT TRANSCEIVER
INPUTS
Rx Rx Tx Tx
V
CC
V
CC
Rx Tx
Recommended Handling Precautions
Avago Technologies recommends that normal static pre-
cautions be taken in the handling and assembly of these
transceivers to prevent damage which may be induced
by electrostatic discharge (ESD). The AFBR-5800Z series
of transceivers meet MIL-STD-883C Method 3015.4 Class
2 products.
Care should be used to avoid shorting the receiver data or
signal detect outputs directly to ground without proper
current limiting impedance.
Solder and Wash Process Compatibility
The transceivers are delivered with protective process
plugs inserted into the duplex SC or duplex ST connector
receptacle. This process plug protects the optical subas-
semblies during wave solder and aqueous wash process-
ing and acts as a dust cover during shipping.
These transceivers are compat ible with either industry
standard wave or hand solder processes.
Shipping Container
The transceiver is packaged in a shipping container de-
signed to protect it from mechanical and ESD damage
during shipment or storage.
Board Layout - Decoupling Circuit and Ground Planes
It is important to take care in the layout of your circuit
board to achieve optimum perform ance from these trans-
ceivers. Figure 7 provides a good example of a schematic
for a power supply decoupling circuit that works well
with these parts. It is further recommended that a con-
tiguous ground plane be provided in the circuit board di-
rectly under the transceiver to provide a low inductance
ground for signal return current. This recommen da tion is
in keeping with good high frequency board layout prac-
tices.
8
Figure 8b. Recommended Common Mechanical Layout for SC and ST 1 x 9
Connectored Transceivers.
25.4
42.0
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24.8
9.53
(NOTE 1)
39.12
6.79
25.4
12.09
11.1
0.75
12.0
0.51
NOTE 1: MINIMUM DISTANCE FROM FRONT
OF CONNECTOR TO THE PANEL FACE.
Figure 8a. Recommended Board Layout Hole Pattern
20.32
(0.800)
TOP VIEW
2 x Ø 1.9 ± 0.1
(0.075 ± 0.004)
20.32
(0.800)
2.54
(0.100)
9 x Ø 0.8 ± 0.1
(0.032 ± 0.004)
DIMENSIONS ARE IN MILLIMETERS (INCHES)
Board Layout - Hole Pattern
The Avago Technologies trans ceiver complies with the
circuit board “Common Transceiver Footprint” hole
pattern de ned in the original multisource announce-
ment which de ned the 1 x 9 package style. This drawing
is repro duced in Figure 8 with the addition of ANSI
Y14.5M compliant dimensioning to be used as a guide in
the mechani cal layout of your circuit board.
Board Layout - Mechanical
For applications interested in providing a choice of either
a duplex SC or a duplex ST connector interface, while uti-
lizing the same pinout on the printed circuit board, the ST
port needs to protrude from the chassis panel a minimum
of 9.53 mm for su cient clearance to install the ST con-
nector.
Please refer to Figure 8a for a mechanical layout detailing
the recommended location of the duplex SC and duplex
ST trans ceiver packages in relation to the chassis panel.
9
Regulatory Compliance
These transceiver products are intended to enable com-
mercial system designers to develop equipment that
complies with the various international regulations gov-
erning certi ca tion of Information Technology Equip-
ment. See the Regulatory Compliance Table for details.
Additional information is available from your Avago Tech-
nologies sales representative.
Electrostatic Discharge (ESD)
There are two design cases in which immunity to ESD
damage is important.
The rst case is during handling of the transceiver prior
to mount ing it on the circuit board. It is important to
use normal ESD handling precautions for ESD sensitive
devices. These precautions include using grounded wrist
straps, work benches, and oor mats in ESD controlled
areas.
The second case to consider is static discharges to the
exterior of the equipment chassis con taining the trans-
ceiver parts. To the extent that the duplex SC connector
is exposed to the outside of the equipment chassis it may
be subject to whatever ESD system level test criteria that
the equipment is intended to meet.
Regulatory Compliance Table
Feature Test Method Performance
Electrostatic Discharge
(ESD) to the Electrical Pins
MIL-STD-883C
Method 3015.4
Class 2 (2000 to 3999 Volts)
Withstand up to 2200 V applied between electrical pins
Electrostatic Discharge
(ESD) to the Duplex SC
Receptacle
Variation of
IEC 801-2
Typically withstand at least 25 kV without damage when the Duplex
SC Connector Receptacle is contacted by a Human Body Model
probe.
Electromagnetic
Interference (EMI)
FCC Class B
CENELEC CEN55022
Class B (CISPR 22B)
VCCI Class 2
Transceivers typically provide a 13 dB margin (with duplex SC
receptacle) or a 9 dB margin (with duplex ST receptacles) to the
noted standard limits. However, it should be noted that nal margin
depends on the customer’s board and chassis design.
Immunity Variation of IEC 61000-4-3 Typically show no measurable e ect from a 10 V/m eld swept from
10 to 450 MHz applied to the transceiver when mounted to a circuit
card without a chassis enclosure.
Electromagnetic Interference (EMI)
Most equipment designs utilizing these high speed trans-
ceivers from Avago Technologies will be required to meet
the require ments of FCC in the United States, CENELEC
EN55022 (CISPR 22) in Europe and VCCI in Japan.
These products are suitable for use in designs ranging
from a desktop computer with a single transceiver to a
concentrator or switch product with large number of
transceivers.
In all well-designed chassis, the two 0.5” holes required
for ST connectors to pro trude through will provide 4.6 dB
more shielding than one 1.2” duplex SC rectangular
cutout. Thus, in a well-designed chassis, the duplex ST 1 x
9 transceiver emissions will be identical to the duplex SC
1 x 9 transceiver emissions.
Figure 9. Transmitter Output Optical Spectral Width (FWHM) vs.
Transmitter Output Optical Center Wavelength and Rise/Fall Times.
200
100
l
C
– TRANSMITTER OUTPUT OPTICAL RISE/FALL TIMES – ns
1280 1300 1320
180
160
140
120
13601340
D
l - TRANSMITTER OUTPUT OPTICAL
SPECTRAL WIDTH (FWHM) - nm
1.0
1.5
2.5
3.0
2.0
AFBR-5805 TRANSMITTER TEST RESULTS OF I
C
, DI AND
t
r/f
ARE CORRELATED AND COMPLY WITH THE ALLOWED
SPECTRAL WIDTH AS A FUNCTION OF CENTER WAVELENGTH
FOR VARIOUS RISE AND FALL TIMES.
1260
t
r/f
– TRANSMITTER
OUTPUT OPTICAL
RISE/FALL TIMES – ns
3.0
10
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause catastrophic damage to the device. Limits apply to
each parameter in isolation, all other parameters having values within the recommended operating conditions. It
should not be assumed that limiting values of more than one parameter can be applied to the product at the same
time. Exposure to the absolute maximum ratings for extended periods can adversely a ect device reliability.
Parameter Symbol Min. Typ. Max. Unit Reference
Storage Temperature TS -40 +100 °C
Lead Soldering Temperature TSOLD +260 °C
Lead Soldering Time tSOLD 10 sec.
Supply Voltage VCC -0.5 7.0 V
Data Input Voltage VI-0.5 VCC V
Di erential Input Voltage VD1.4 V Note 1
Output Current IO50 mA
Figure 10. Relative Input Optical Power vs. Eye
Sampling Time Position.
Immunity
Equipment utilizing these transceivers will be subject to
radio-frequency electromagnetic elds in some environ-
ments. These transceivers have a high immunity to such
elds.
Transceiver Reliability and Performance Quali cation
Data
The 1 x 9 transceivers have passed Avago Technologies’
reliabil ity and performance quali cation testing and are
undergoing ongoing quality monitoring. Details are avail-
able from your Avago Technologies sales representative.
Ordering Information
The AFBR-5805Z/-5805TZ 1300 nm products are avail able
for production orders through the Avago Technologies
Component Field Sales O ces and Auth orized Distribu-
tors world wide.
RELATIVE INPUT OPTICAL POWER (dB)
0
EYE SAMPLING TIME POSITION (ns)
-3 -1 0 1
5
4
3
2
3
1
-2 2
CONDITIONS:
1. TA = +25° C
2. VCC = 3.3 V to 5 V dc
3. INPUT OPTICAL RISE/FALL TIMES = 1.0/2.1 ns.
4. INPUT OPTICAL POWER IS NORMALIZED TO
CENTER OF DATA SYMBOL.
5. NOTE 16 AND 17 APPLY.
AFBR-5805Z SERIES
11
Recommended Operating Conditions
Parameter Symbol Min. Typ. Max. Unit Reference
Ambient Operating Temperature
AFBR-5805Z/5805TZ
AFBR-5805AZ/5805ATZ
TA
TA
0
-10
+70
+85
°C
°C
Note A
Note B
Supply Voltage VCC
VCC
3.135
4.75
3.5
5.25
V
V
Data Input Voltage - Low VIL - VCC -1.810 -1.475 V
Data Input Voltage - High VIH - VCC -1.165 -0.880 V
Data and Signal Detect Output Load RL50 W Note 2
Notes:
A. Ambient Operating Temperature corresponds to transceiver case temperature of 0°C mininum to +85 °C maximum with necessary air ow
applied. Recommended case temperature measurement point can be found in Figure 2.
B. Ambient Operating Temperature corresponds to transceiver case temperature of -10 °C mininum to +100 °C maximum with necessary air ow
applied. Recommended case temperature measurement point can be found in Figure 2.
Transmitter Electrical Characteristics
(AFBR-5805Z/5805TZ: TA = 0°C to +70°C, VCC = 3.135 V to 3.5 V or 4.75 V to 5.25 V)
(AFBR-5805AZ/5805ATZ: TA = -10°C to +85°C, VCC = 3.135 V to 3.5 V or 4.75 V to 5.25 V)
Parameter Symbol Min. Typ. Max. Unit Reference
Supply Current ICC 135 175 mA Note 3
Power Dissipation at VCC = 3.3 V PDISS 0.45 0.6 W
at VCC = 5.0 V PDISS 0.67 0.9 W
Data Input Current - Low IIL -350 -2 μA
Data Input Current - High IIH 18 350 μA
Receiver Electrical Characteristics
(AFBR-5805Z/5805TZ: TA = 0°C to +70°C, VCC = 3.135 V to 3.5 V or 4.75 V to 5.25 V)
(AFBR-5805AZ/5805ATZ: TA = -10°C to +85°C, VCC = 3.135 V to 3.5 V or 4.75 V to 5.25 V
Parameter Symbol Min. Typ. Max. Unit Reference
Supply Current ICC 87 120 mA Note 4
Power Dissipation at VCC = 3.3 V PDISS 0.15 0.25 W Note 5
at VCC = 5.0 V PDISS 0.3 0.45 W
Data Output Voltage - Low VOL - VCC -1.83 -1.55 V Note 6
Data Output Voltage - High VOH - VCC -1.085 -0.88 V Note 6
Data Output Rise Time tr0.35 2.2 ns Note 7
Data Output Fall Time tf0.35 2.2 ns Note 7
Signal Detect Output Voltage - Low VOL - VCC -1.83 -1.55 V Note 6
Signal Detect Output Voltage - High VOH - VCC -1.085 -0.88 V Note 6
Signal Detect Output Rise Time tr0.35 2.2 ns Note 7
Signal Detect Output Fall Time tf0.35 2.2 ns Note 7
12
Transmitter Optical Characteristics
(AFBR-5805Z/5805TZ: TA = 0°C to +70°C, VCC = 3.135 V to 3.5 V or 4.75 V to 5.25 V)
(AFBR-5805AZ/5805ATZ: TA = -10°C to +85°C, VCC = 3.135 V to 3.5 V or 4.75 V to 5.25 V)
Parameter Symbol Min. Typ. Max. Unit Reference
Output Optical Power
62.5/125 μm, NA = 0.275 Fiber
BOL
EOL
PO-19
-20
-14 dBm avg. Note 8
Output Optical Power
50/125 μm, NA = 0.20 Fiber
BOL
EOL
PO-22.5
-23.5
-14 dBm avg. Note 8
Optical Extinction Ratio 10 dB Note 9
Output Optical Power at
Logic “0” State
PO (“0”) -45 dBm avg. Note 10
Center Wavelength lC1270 1310 1380 nm Note 22
Spectral Width - FWHM Dl 137 nm Note 22
Optical Rise Time tr0.6 1.9 3.0 ns Note 11, 22
Figure 9
Optical Fall Time tf0.6 1.6 3.0 ns Note 11, 22
Figure 9
Systematic Jitter Contributed
by the Transmitter
SJ 1.2 ns p-p Note 12
Random Jitter Contributed
by the Transmitter
RJ 0.69 ns p-p Note 13
Receiver Optical and Electrical Characteristics
(AFBR-5805Z/5805TZ: TA = 0°C to +70°C, VCC = 3.135 V to 3.5 V or 4.75 V to 5.25 V)
(AFBR-5805AZ/5805ATZ: TA = -10°C to +85°C, VCC = 3.135 V to 3.5 V or 4.75 V to 5.25 V)
Parameter Symbol Min. Typ. Max. Unit Reference
Input Optical Power
Minimum at Window Edge
PIN Min. (W) -34 -30 dBm avg. Note 14
Figure 10
Input Optical Power
Minimum at Eye Center
PIN Min. (C) -35 -31 dBm avg. Note 15
Figure 10
Input Optical Power Maximum PIN Max. -14 dBm avg. Note 14
Operating Wavelength l 1270 1380 nm
Systematic Jitter Contributed
by the Receiver
SJ 1.2 ns p-p Note 16
Random Jitter Contributed
by the Receiver
RJ 1.91 ns p-p Note 17
Signal Detect - Asserted PAPD +1.5 dB -31 dBm avg. Note 18
Signal Detect - Deasserted PD-45 dBm avg. Note 19
Signal Detect - Hysteresis PA - PD1.5 dB
Signal Detect Assert Time
(o to on)
0 2 100 μs Note 20
Signal Detect Deassert Time
(on to o )
0 8 350 μs Note 21
13
Notes:
1. This is the maximum voltage that can be applied across the Di eren-
tial Transmitter Data Inputs to prevent damage to the input ESD pro-
tection circuit.
2. The outputs are terminated with 50 connected to VCC -2 V.
3. The power supply current needed to operate the transmitter is pro-
vided to di erential ECL circuitry. This circuitry maintains a nearly
con stant current ow from the power supply. Constant current op-
eration helps to prevent unwanted electrical noise from being gen-
erated and conducted or emitted to neighboring circuitry.
4. This value is measured with the out puts terminated into 50
W connected to VCC - 2 V and an Input Optical Power level of
-14 dBm average.
5. The power dissipation value is the power dissipated in the receiver
itself. Power dissipation is calcu lated as the sum of the products of
supply voltage and currents, minus the sum of the products of the
output voltages and currents.
6. This value is measured with respect to VCC with the output termi-
nated into 50 connected to VCC - 2 V.
7. The output rise and fall times are measured between 20% and 80%
levels with the output connected to VCC -2 V through 50 .
8. These optical power values are measured with the following condi-
tions:
• The Beginning of Life (BOL) to the End of Life (EOL) optical
power degradation is typically 1.5 dB per the industry con-
vention for long wavelength LEDs. The actual degradation
observed in Avago Technologies’ 1300 nm LED products is
< 1 dB, as speci ed in this data sheet.
• Over the speci ed operating voltage and temperature ranges.
• With 25 MBd (12.5 MHz square-wave), input signal.
• At the end of one meter of noted optical ber with cladding
modes removed.
The average power value can be converted to a peak power value by
adding 3 dB.
9. The Extinction Ratio is a measure of the modulation depth of
the optical signal. The data “1” output optical power is com-
pared to the data “0” peak output optical power and expressed
in decibels. With the transmitter driven by a 25 MBd (12.5 MHz
square-wave) input signal, the average optical power is mea-
sured. The data “1” peak power is then calculated by adding
3 dB to the measured average optical power. The data “0” output
optical power is found by measuring the optical power when the
transmitter is driven by a logic “0” input. The extinc tion ratio is the
ratio of the optical power at the “1” level compared to the optical
power at the “0” level expressed in decibels.
10. The transmitter will provide this low level of Output Optical Power
when driven by a logic “0” input. This can be useful in link trouble-
shooting.
11. The relationship between Full Width Half Maximum and RMS values
for Spectral Width is derived from the assumption of a Gaussian
shaped spectrum which results in a 2.35 X RMS = FWHM relation-
ship. The optical rise and fall times are measured from 10% to 90%
when the transmitter is driven by a 25 MBd (12.5 MHz square-wave)
input signal. The ANSI T1E1.2 committee has designated the pos-
sibility of de ning an eye pattern mask for the transmitter optical
output as an item for further study. Avago Technologies will incor-
porate this requirement into the speci cations for these products if
it is de ned. The AFBR-5805 products typically comply with the tem-
plate require ments of CCITT (now ITU-T) G.957 Section 3.2.5, Figure
2 for the STM-1 rate, excluding the optical receiver lter normally
associated with single mode ber measurements which is the likely
source for the ANSI T1E1.2 committee to follow in this matter.
12. Systematic Jitter contributed by the transmitter is de ned as the
com bination of Duty Cycle Distortion and Data Dependent Jitter.
Systematic Jitter is measured at 50% threshold using a 155.52 MBd
(77.5 MHz square-wave), 27 -1 psuedo random data pattern input
signal.
13. Random Jitter contributed by the transmitter is speci ed with a
155.52 MBd (77.5 MHz square-wave) input signal.
14. This speci cation is intended to indicate the performance of the
receiver section of the transceiver when Input Optical Power signal
characteristics are present per the following de nitions. The Input
Optical Power dynamic range from the minimum level (with a
window time-width) to the maximum level is the range over which
the receiver is guaranteed to provide output data with a Bit Error
Ratio (BER) better than or equal to 1 x 10-10.
• At the Beginning of Life (BOL)
• Over the speci ed operating temperature and voltage ranges
• Input is a 155.52 MBd, 223 - 1 PRBS data pattern with 72 “1”s and
72 “0”s inserted per the CCITT (now ITU-T) recommenda tion G.958
Appendix I.
• Receiver data window time-width is 1.23 ns or greater for the
clock recovery circuit to operate in. The actual test data window
time-width is set to simulate the e ect of worst case optical input
jitter based on the transmitter jitter values from the speci cation
tables. The test window time-width is AFBR-5805 3.32 ns.
• Transmitter operating with a 155.52 MBd, 77.5 MHz square-wave,
input signal to simulate any cross-talk present between the trans-
mitter and receiver sections of the transceiver.
15. All conditions of Note 14 apply except that the measurement is
made at the center of the symbol with no window time-width.
16. Systematic Jitter contributed by the receiver is de ned as the
combina tion of Duty Cycle Distortion and Data Dependent Jitter.
Systematic Jitter is measured at 50% threshold using a 155.52 MBd
(77.5 MHz square-wave), 27 - 1 psuedo random data pattern input
signal.
17. Random Jitter contributed by the receiver is speci ed with a 155.52
MBd (77.5 MHz square-wave) input signal.
18. This value is measured during the transition from low to high levels
of input optical power.
19. This value is measured during the transition from high to low levels
of input optical power.
20. The Signal Detect output shall be asserted within 100 μs after a step
increase of the Input Optical Power.
21. Signal detect output shall be de-asserted within 350 μs after a step
decrease in the Input Optical Power.
22. The AFBR-5805 transceiver complies with the requirements for the
trade-o s between center wavelength, spectral width, and rise/fall
times shown in Figure 9. This gure is derived from the FDDI PMD
standard (ISO/IEC 9314-3 : 1990 and ANSI X3.166 - 1990) per the de-
scription in ANSI T1E1.2 Revision 3. The interpretation of this gure is
that values of Center Wavelength and Spectral Width must lie along
the appropriate Optical Rise/Fall Time curve.
Ordering Information
The AFBR-5805Z/5805TZ/5805AZ/5805ATZ 1300 nm
products are avail able for production orders through the
Avago Technologies Component Field Sales O ces and
Authorized Distributors world wide.
0 °C to +70 °C
AFBR-5805Z/5805TZ
-10 °C to +85 °C
AFBR-5805AZ/5805ATZ
*ST is a registered trademark of AT&T Lightguide Cable Connectors.
Note:
The “T” in the product numbers indicates a transceiver with a duplex
ST connector receptacle. Product numbers without a “T” indicate
transceivers with a duplex SC connector receptacle.
For product information and a complete list of distributors, please go to our web site: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2012 Avago Technologies. All rights reserved. Obsoletes 5989-3433EN
AV02-0433EN - April 9, 2012
