FN3976 Rev.5.00 Page 1 of 10
Feb 8, 2019
FN3976
Rev.5.00
Feb 8, 2019
HIP4020
Half Amp Full Bridge Power Driver for Small 3V, 5V, and 12V DC Motors
DATASHEET
In the Functional Block Diagram of the HIP4020, the four
switches and a load are arranged in an H-configuration so
that the drive voltage from terminals OUTA and OUTB can
be cross-switched to change the direction of current flow in
the load. This is commonly known as 4-quadrant load
control. As shown Figure 1, switches Q1 and Q4 are
conducting or in an ON state when current flows from VDD
through Q1 to the load, and then through Q4 to terminal
VSSB; where load terminal OUTA is at a positive potential
with respect to OUTB. Switches Q1 and Q4 are operated
synchronously by the control logic. The control logic
switches Q3 and Q2 to an open or OFF state when Q1 and
Q4 are switched ON. To reverse the current flow in the load,
the switch states are reversed where Q1 and Q4 are OFF
while Q2 and Q3 are ON. Consequently, current then flows
from VDD through Q3, through the load, and through Q2 to
terminal VSSA, and load terminal OUTB is then at a positive
potential with respect to OUTA.
Terminals ENA and ENB are ENABLE inputs for the Logic A
and B Input Controls. The ILF output is an Overcurrent Limit
Fault Flag Output and indicates a fault condition for either
Output A or B or both. The VDD and VSS are the Power
Supply reference terminals for the A and B Control Logic
Inputs and ILF Output. While the VDD positive power supply
terminal is internally connected to each bridge driver, the
VSSA and VSSB power supply terminals are separate and
independent from VSS and may be more negative than the
VSS ground reference terminal. The use of level shifters in
the gate drive circuitry to the NMOS (low-side) output stages
allows controlled level shifting of the output drive relative to
ground.
Features
• Two independent controlled complementary MOS power
output half H-drivers (full-bridge) for nominal 3V to 12V
power supply operation
• Split ±voltage power supply option for output drivers
• Load switching capabilities to 0.5A
• Single supply range +2.5V to +15V
• Low standby current
• CMOS/TTL compatible input logic
• Over-temperature shutdown protection
• Overcurrent limit protection
• Overcurrent fault flag output
• Direction, braking and PWM control
• Pb-free plus anneal (RoHS compliant)
Applications
• DC motor driver
• Relay and solenoid drivers
• Stepper motor controller
• Air core gauge instrument driver
• Speedometer displays
• Tachometer displays
• Remote power switch
• Battery operated switch circuits
• Logic and microcontroller operated switch
Related Literature
For a full list of related documents, visit our website:
•HIP4020 device page
FIGURE 1. BLOCK DIAGRAM
VSSB
VDD
OUTB
LOAD
OUTA
B1
B2
ENB
A1
A2
ENA
ILF
VSS VSSA
Q1
Q3
Q2Q4
CONTROL
LOGIC B
CONTROL
LOGIC A
ISENSE
TSENSE
ISENSE
ISENSE
ISENSE
OVER TEMP. AND CURRENT LIMIT,
LEVEL SHIFT, DRIVE CONTROL
HIP4020
FN3976 Rev.5.00 Page 2 of 10
Feb 8, 2019
Ordering Information
PART NUMBER
(Notes 2, 3)
PART
MARKING
TEMP.
RANGE (°C)
TAPE AND REEL
(UNITS) (Note 1)
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
HIP4020IBZ HIP4020IBZ -40 to 85 - 20 Ld SOIC M20.3
HIP4020IBZT HIP4020IBZ -40 to 85 1k 20 Ld SOIC M20.3
NOTES:
1. See TB347 for details about reel specifications.
2. Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination
finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Pb-free products are MSL classified at
Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), see the HIP4020 device page. For more information about MSL, see TB363.
Pinout
SOIC
TOP VIEW
11
12
13
14
15
16
17
18
20
19
10
9
8
7
6
5
4
3
2
1
NC
ILF
B2
ENB
B1
VSS
A1
ENA
A2
NC
NC
NC
OUTB
VSSB
VDD
VSSA
OUTA
NC
VDD
NC
Pin Descriptions
PIN NUMBER SYMBOL DESCRIPTION
12, 19 VDD Positive power supply pins; internally common and externally connect to the same positive supply (V+).
15 VSSA Negative power supply pin; negative or ground return for Switch Driver A; externally connect to the supply (V-).
16 VSSB Negative power supply pin; negative or Ground return for Switch Driver B; externally connect to the supply (V-).
6V
SS Common ground pin for the Input Logic Control circuits. It can be used as a common ground with VSSA and
VSSB.
8, 5 A1, B1 Input pins used to control the direction of output load current to/from OUTA and OUTB, respectively. When
connected, A1 and B1 can be controlled from the same logic signal to change the directional rotation of a motor.
9, 3 A2, B2 Input pins used to force a low state on OUTA and OUTB, respectively. When connected, A2 and B2 can be
controlled from the same logic signal to activate dynamic braking of a motor.
7, 4 ENA, ENB Input pins used to enable Switch Driver A and Switch Driver B, respectively. When low, the respective output is
in a high impedance (Z) off-state. Since each switch driver is independently controlled, OUTA and OUTB can
be separately PWM controlled as half H-switch drivers.
14, 17 OUTA, OUTB Respectively, Switch Driver A and Switch Driver B output pins.
2 ILF Current limiting fault output flag pin; when in a high logic state, signifies that Switch Driver A or B, or both are in
a Current Limiting Fault mode.
HIP4020
FN3976 Rev.5.00 Page 3 of 10
Feb 8, 2019
Absolute Maximum Ratings Thermal Information
Supply Voltage; VDD to VSS or VSSA or VSSB . . . . . . . . . . . . .+15V
Negative Output Supply Voltage, (VSSA, VSSB) . . . . . . . . . (Note 4)
DC Logic Input Voltage (Each Input) . . . (VSS -0.5V) to (VDD +0.5V)
DC Logic Input Current (Each Input)  15mA
ILF Fault Output Current  15mA
Output Load Current, (Self Limiting, see Elec. Spec.)IO(LIMIT)
Operating ConditionsTA = 25°C
Typical Operating Supply Voltage Range, VDD . . . . . . . +3 to +12V
Low Voltage Logic Retention, Minimum VDD. . . . . . . . . . . . . . . .+2V
Idle Supply Current; No Load, VDD = +5V. . . . . . . . . . . . . . . .0.8mA
Typical P+N Channel rDS(ON), VDD = +5V, 0.5A Load . . . . . . . . 2Ω
Thermal Resistance (Typical, Note 5)JA (°C/W)
Plastic SOIC Package . . . . . . . . . . . . . . . . . . . . . . . 105
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” can cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
4. VSS is the required common ground reference for the logic input switching. The load currents may be switched positive and negative in reference
to the VSS common ground by using a split supply for VDD (positive) to VSSA and VSSB (negative). For an uneven split in the supply voltage,
the maximum negative output supply voltage for VSSA and VSSB is limited by the maximum VDD to VSSA or VSSB ratings. Since the VDD pins
are internally tied together, the voltage on each VDD pins must be equal and common.
5. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications TA = 25°C, VDD = +5V, VSSA = VSSB = VSS = 0V, unless otherwise specified
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
Input Leakage Current ILEAK VDD = +15V - - 25 nA
Low Level Input Voltage VIL VSS -0.8V
High Level Input Voltage VIH 2-V
DD V
ILF Output Low, Sink Current IOH VOUT = 0.4V, VDD = +12V 15 - - mA
ILF Output High, Source Current IOL VOUT = 11.6V, VDD = +12V - - -15 mA
Input Capacitance CIN -2-pF
P-Channel rDS(ON), Low Supply Voltage rDS(ON) VDD = +3V, ISOURCE = 250mA - 1.6 2.5 Ω
N-Channel rDS(ON), Low Supply Voltage rDS(ON) VDD = +3V, ISINK = 250mA - 1 1.5 Ω
P-Channel rDS(ON), High Supply Voltage rDS(ON) VDD = +12V, ISOURCE = 400mA - 0.6 1.2 Ω
N-Channel rDS(ON), High Supply Voltage rDS(ON) VDD = +12V, ISINK = 400mA - 0.5 1.1 Ω
OUTA, OUTB Source Current Limiting IO(LIMIT) VDD = +6V, VSS = 0V, VSSA = VSSB = -6V 480 625 1500 mA
OUTA, OUTB Sink Current Limiting -IO(LIMIT) VDD = +6V, VSS = 0V, VSSA = VSSB = -6V 480 800 1500 mA
Idle Supply Current; No Load IDD -0.81.5mA
OUTA, OUTB Voltage High VOH ISOURCE = 450mA 4.2 4.5 - V
OUTA, OUTB Voltage Low VOL ISINK = 450mA - 0.4 0.6 V
OUTA, OUTB Voltage High VOH VDD = +3V, ISOURCE = 250mA 2.415 2.6 - V
OUTA, OUTB Voltage Low VOL VDD = +3V, ISINK = 250mA - 0.25 0.375 V
OUTA, OUTB Source Current Limiting IO(LIMIT) VDD = +12V 480 625 1500 mA
OUTA, OUTB Sink Current Limiting -IO(LIMIT) VDD = +12V 480 800 1500 mA
OUTA, OUTB Source Current Limiting IO(LIMIT) VDD = +3V 480 625 1500 mA
OUTA, OUTB Sink Current Limiting -IO(LIMIT) VDD = +3V 480 800 1500 mA
Thermal Shutdown TSD - 145 - °C
HIP4020
FN3976 Rev.5.00 Page 4 of 10
Feb 8, 2019
Response Time: VEN to VOUT
Turn-On: Prop Delay
tPLH IO = 0.5A (Note 6)-2.5-µs
Rise Time tr-4-µs
Turn-Off: Prop Delay tPHL -0.1- µs
Fall Time tf-0.1- µs
NOTE:
6. See the Truth Table and the VEN to VOUT Switching Waveforms. Current IO refers to IOUTA or IOUTB as the output load current. Note that ENA
controls OUTA and ENB controls OUTB. Each Half H-switch has independent control from the respective A1, A2, ENA or B1, B2, ENB inputs.
See the terminal Information table for external pin connections to establish mode control switching. Figure 2 on page 4 shows a typical
application circuit used to control a DC Motor.
Electrical Specifications TA = 25°C, VDD = +5V, VSSA = VSSB = VSS = 0V, unless otherwise specified (Continued)
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
FIGURE 2. TYPICAL MOTOR CONTROL APPLICATION CIRCUIT SHOWING DIRECTIONAL AND BRAKING CONTROL
B1
B2
ENB
A1
A2
ENA
VDD
VSS VSSB
VSSA
V+
OUTA OUTB
BRAKE
ON
OFF
DIRECTION
ENABLE
(LOGIC
GROUND) LOAD
ILF
Q1Q3
Q2Q4
D1D3
D4
D2
CONTROL
LOGIC A
V-
LEVEL SHIFTER
AND OC/OT LIMITER
LEVEL SHIFTER
AND OC/OT LIMITER
OVER-TEMP LIMIT
CONTROL
LOGIC B
FIGURE 3. SWITCHING WAVEFORMS
TRUTH TABLE
SWITCH DRIVER A SWITCH DRIVER B
INPUTS OUTPUT INPUTS OUTPUT
A1 A2 ENA OUTA B1 B2 ENB OUTB
HL H OH LL H OH
LL H OL HL H OL
HH H OL LH H OL
LH H OL HH H OL
XX L Z XX L Z
L = Low logic level; H = High logic level
Z = High Impedance (off state)
OH = Output High (sourcing current to the output terminal)
OL = Output Low (sinking current from the output terminal)
X = Do not Care
tPLH
50%
50%
VEN
VOUT
tPHL
50%
50%
VEN
VOUT
tr
tf
10%
90%
10%
90%
HIP4020
FN3976 Rev.5.00 Page 5 of 10
Feb 8, 2019
Application
The HIP4020 is designed to detect load current feedback from
sampling resistors of low value in the source connections of
the output drivers to VDD, VSSA and VSSB (see Figure 2).
When the sink or source current at OUTA or OUTB exceeds
the preset OC (Overcurrent) limiting value of 550mA typical,
the current is held at the limiting value. If the Over-Temperature
(OT) Shutdown Protection limit is exceeded, temperature
sensing BiMOS circuits limit the junction temperature to 150°C
typical.
Figure 2 shows the Full H-switch in a small motor-drive
application. The left (A) and right (B) H-switch’s are controlled
from the A and B inputs using the A and B control logic to the
MOS output transistors Q1, Q2, Q3, and Q4. The circuit is
intended to safely start, stop, and control rotational direction for a
motor requiring no more than 0.5A of supply current. The stop
function includes a dynamic braking feature.
With the enable inputs low, the MOS transistors Q1 and Q3 are
OFF; which cuts-off supply current to OUTA and OUTB. With the
brake terminal low and enable inputs high, either Q1 and Q4 or
Q3 and Q2 are driven into conduction by the direction input
control terminal. The MOS output transistor pair chosen for
conduction is determined by the logic level applied to the direction
control; resulting in either Clockwise (CW) or Counter-Clockwise
(CCW) shaft rotation.
When the brake terminal is switched high (while holding the
enable input high), the gates of both Q2 and Q4 are driven
high. Current flowing through Q2 (from the motor terminal
OUTA) at the moment of dynamic braking continues to flow
through Q2 to the VSSA and VSSB external connection, and
then continues through diode D4 to the motor terminal OUTB.
As such, the resistance of the motor winding (and the
series-connected path) dissipates the kinetic energy stored in
the system. Reversing rotation, current flowing through Q4
(from the motor terminal OUTB), at the moment of dynamic
braking, would continue to flow through Q4 to the VSSB and
VSSA tie, and then continue through diode D2 to the motor
terminal OUTA, to dissipate the stored kinetic energy as
previously described.
Where VDD to VSS are the power supply reference terminals
for the control logic, the lowest practical supply voltage for
proper logic control should be no less than 2.0V. The VSSA and
VSSB terminals are separate and independent from VSS and
may be more negative than the VSS ground reference terminal.
However, the maximum supply level from VDD to VSSA or
VSSB must not be greater than the absolute maximum supply
voltage rating.
Terminals A1, B1, A2, B2, ENA, and ENB are internally
connected to protection circuits intended to guard the CMOS
gate-oxides against damage due to electrostatic discharge. (See
Figure 4) Inputs ENA, ENB, A1, B1, A2, and B2 have protection
and level converters for TTL or CMOS Input Logic. These inputs
are designed to typically provide ESD protection up to 2kV.
However, these devices are sensitive to electrostatic discharge.
Proper IC handling procedures should be followed.
INPUT LEVEL
CONV.
VDD
FIGURE 4. LOGIC INPUT ESD INTERFACE PROTECTION
A1
A2
ENA
(DIR)
(BRAKE)
(ENABLE)
OT AND OC
PROTECT
N-DR
LIMIT
P-DR
LIMIT
Q2D2
Q1
D1
VDD
VSSA
OUTA
B1
B2
ENB
(DIR)
(BRAKE)
(ENABLE)
OT AND OC
PROTECT
N-DR
LIMIT
P-DR
LIMIT
Q4D4
Q3
D3
VDD
VSSB
OUTB
FIGURE 5. EQUIVALENT CONTROL LOGIC A AND B SHOWN DRIVING THE OUTA AND OUTB OUTPUT DRIVERS
HIP4020
FN3976 Rev.5.00 Page 6 of 10
Feb 8, 2019
Typical Performance Curves
FIGURE 6. TYPICAL CHARACTERISTIC OF THE P-MOSFET OUTPUT DRIVER DRAIN CURRENT vs DRAIN-TO-SOURCE VOLTAGE,
TAMBIENT = 25°C
FIGURE 7. TYPICAL CHARACTERISTIC OF THE N-MOSFET OUTPUT DRIVER DRAIN CURRENT vs DRAIN-TO-SOURCE VOLTAGE,
TAMBIENT = 25°C
FIGURE 8. TYPICAL CHARACTERISTIC OF THE P AND N OUTPUT DRIVER SHORT CIRCUIT CURRENT vs SUPPLY VOLTAGE,
TAMBIENT = 25°C
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0
0
50
100
150
200
250
300
350
400
450
500
550
600
650
700
750
800
DRAIN-TO-SOURCE VOLTAGE (V)
VDD = 3V
VDD = 5V
VDD = 12V
P-CHANNEL DRAIN CURRENT (mA)
TYPICAL CURRENT
LIMITING
1Ω0.5Ω 2Ω
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0
0
50
100
150
200
250
300
350
400
450
500
550
600
650
700
750
800
1Ω0.5Ω 2Ω
DRAIN-TO-SOURCE VOLTAGE (V)
N-CHANNEL DRAIN CURRENT (mA)
VDD = 3V
VDD = 5V
VDD = 12V
TYPICAL CURRENT
LIMITING
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 10.5 11.0 11.5 12.0
0
50
100
150
200
250
300
350
400
450
500
550
600
650
700
750
800
SHORT CIRCUIT CURRENT (mA)
VDD SUPPLY VOLTAGE (V)
N-CHANNEL
P-CHANNEL
HIP4020
FN3976 Rev.5.00 Page 7 of 10
Feb 8, 2019
FIGURE 9. TYPICAL CHARACTERISTIC OF SATURATION VOLTAGE vs OUTPUT CURRENT USING A +5V SUPPLY, TAMBIENT = 25°C
FIGURE 10. TYPICAL CHARACTERISTIC OF SATURATION VOLTAGE vs OUTPUT CURRENT USING A ±3V SPLIT SUPPLY, OUTPUT
REFERENCE EQUAL LOGIC GROUND, TAMBIENT = 25°C
FIGURE 11. TYPICAL CHARACTERISTIC OF SATURATION VOLTAGE vs OUTPUT CURRENT USING A ±6V SPLIT SUPPLY, OUTPUT
REFERENCE EQUAL LOGIC GROUND, TAMBIENT = 25°C
Typical Performance Curves (Continued)
OUTPUT CURRENT, IO (A)
SATURATION VOLTAGE, VDD - VOUT (V)
HIGH
LOW
VDD = +5V
VSS = VSSA = VSSB = GND
0100 200 300 400 500
0.00
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
0.55
0.60
0.65
HIP4020 SPLIT 5V COMMON GROUND
VSAT(P)
VSAT(N)
VSAT vs LOAD CURRENT
OUTPUT CURRENT, IO (A)
SATURATION VOLTAGE, VDD - VOUT (V)
HIGH
LOW
VDD = +3V
VSS = GND
VSSA = VSSB = -3V
0100 200 300 400 500 600 700
0.00
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
0.55
0.60
0.65
0.70
HIP4020 SPLIT 3V
VSAT(P)
VSAT(N)
VSAT vs LOAD CURRENT
OUTPUT CURRENT, IO (A)
SATURATION VOLTAGE, VDD - VOUT (V)
VDD = +6V
VSS = GND
VSSA = VSSB = -6V
0100 200 300 400 500 600
0.00
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
0.55
0.60
0.65
0.70
HIP4020 SPLIT ±6V
VSAT(P)
VSAT(N)
VSAT vs LOAD CURRENT
HIGH
LOW
HIP4020
FN3976 Rev.5.00 Page 8 of 10
Feb 8, 2019
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make
sure that you have the latest revision.
DATE REVISION CHANGE
Feb 8, 2019 FN3976.5 Added Related Literature section.
Updated Ordering information table by removing retired part, added new notes, and moved to page 2.
Moved Pin Descriptions below Pinout section.
Added TB493 reference under Thermal Information section.
Moved Note 6 to end of EC table.
Updated P-Channel rDS(ON), Low Supply Voltage maximum specification from 2.1 to 2.5.
Removed About Intersil section.
Updated disclaimer.
Sep17, 2015 FN3976.4 - Updated Ordering Information Table on page 2.
- Added Revision History.
- Added About Intersil Verbiage.
- Updated POD M20.3 to latest revision changes are as follow:
Top View:
Corrected "7.50 BSC" to "7.60/7.40" (no change from rev 2; error was introduced in conversion)
Changed "10.30 BSC" to "10.65/10.00" (no change from rev 2; error was introduced in conversion)
Side View:
Changed "12.80 BSC" to "13.00/12.60" (no change from rev 2; error was introduced in conversion)
Changed "2.65 max" to "2.65/2.35" (no change from rev 2; error was introduced in conversion)
Changed Note 1 from "ANSI Y14.5M-1982." to "ASME Y14.5M-1994"
HIP4020
FN3976 Rev.5.00 Page 9 of 10
Feb 8, 2019
Package Outline Drawing
M20.3
20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE (SOIC)
Rev 3, 2/11
7. The lead width as measured 0.36mm (0.14 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm
DETAIL "X"
SIDE VIEW
TYPICAL RECOMMENDED LAND PATTERN
TOP VIEW
13.00
0.75
0.25 x 45°
0.32
0.23
MAX
8°
1.27
0.40
10.65
10.00
7.60
7.40
20
123
INDEX
AREA
2.65
2.35
0.30
MAX
BSC
1.27
0.35
0.49
0.25 (0.10) MC SBMA 0.10 (0.004)
0.25 (0.10) MB
M
12
1.27 BSC
(9.40mm)
SEATING PLANE
(0.60)
(2.00)
2
20
3
3
5
7
NOTES:
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Dimension does not include mold flash, protrusions or gate
3. Dimension does not include interlead lash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
4. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
5. Dimension is the length of terminal for soldering to a substrate.
6. Terminal numbers are shown for reference only.
8. Controlling dimension: MILLIMETER.
9. Dimensions in ( ) for reference only.
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
(0.024 inch)
10. JEDEC reference drawing number: MS-013-AC.
12.60
For the most recent package outline drawing, see M20.3.
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