DC1300A-C - Linear Technology

LTC3725

3725fa

FEATURES

DESCRIPTIO

APPLICATIO S

TYPICAL APPLICATIO

■

Isolated 48V Telecommunication Systems

■

Internet Servers and Routers

■

Distributed Power Step-Down Converters

■

Automotive and Heavy Equipment

■

High Speed Gate Driver for Forward Converter

■

On-Chip Rectifier and Self-Starting Architecture

Eliminates Need for Separate Gate Drive Bias

Supply

■

Wide Input Voltage Supply Range: 9V and Up

■

Linear Regulator Controller for Fast Start-Up

■

Precision UVLO with Adjustable Hysteresis

■

Overcurrent Protection

■

Volt-Second Limit Prevents Transformer Core

Saturation

■

Voltage Feedforward for Fast Transient Response

■

Available in 10-Lead MSOP Package

Single-Switch Forward

Controller and Gate Driver

The LTC

3725 is a controller for a single-switch forward

converter and includes an on-chip gate driver.

For secondary-side control, combine the LTC3725 with

the LTC3706 PolyPhase

secondary-side synchronous

forward controller to create a complete forward converter

using a minimum of discrete parts. A proprietary scheme

is used to multiplex gate drive signals across the isolation

barrier through a tiny pulse transformer. The on-chip

rectifier and the same pulse transformer provide gate drive

bias power.

Alternatively, the LTC3725 can be used as a standalone

voltage mode controller in a primary-side control architec-

ture with optoisolator feedback. Voltage feedforward pro-

vides excellent line regulation and transient response.

36V-72V to 3.3V/30A Isolated Single-Switch Forward Converter

, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.

PolyPhase is a registered trademark of Linear Technology Corporation. All other

trademarks are the property of their respective owners. Patent Pending

FB/IN

1µF

100V

×2

IN+

36V TO 72V

IN–

2.2nF

200V

10µF

100µF

6.3V

×2

220µF

6.3V

OUT+

3.3V

30A

OUT–

47nF

470pF

33nF

B0540W

Si7450DP

33nF

15k

1µF

0.1µF

0.030Ω

1µF

2.2µF

0.0012Ω

HAT2165

×2

HAT2165

×2

0.85µH

••

162k

L1: PULSE PA1294.910

T1: PULSE PA0815

T2: PULSE PA0297

5.1k

3.3k

100k

2.74k

604Ω

3725 TA01

1.2Ω

1/4W

100k

FS/IN

–

UVLO

SSFLT

GATE

LTC3725

NDRV

GNDPGND

SLMT

365k

FDC2512

•

FG SW I

S–

S+

SG V

MODENDRV

GND PGND RUN/SS SLP REGSD FS/SYNC I

PHASE

FCX491A

–

FBLTC3706

•

LTC3725

3725fa

Power Supply (V

) ...................................–0.3V to 15V

External NMOS Drive (NDRV) ....................– 0.3V to 20V

NDRV to V

CC ...........................................................

–0.3V to 5V

Soft-Start Fault, Feedback,

Frequency Set, Transformer

Inputs (SSFLT, FB/IN

, FS/IN

–

) ..................–0.3V to 15V

All Other Pins (V

SLMT

, I

, UVLO) .................–0.3V to 5V

Peak Output Current <1µs (GATE) ............................. 2A

Operating Ambient Temperature Range .. –40°C to 85°C

Operating Junction Temperature (Note 2) ............ 125°C

Storage Temperature Range ................. – 65°C to 150°C

Lead Temperature (Soldering, 10 sec).................. 300°C

ORDER PART NUMBER

JMAX

= 125°C, θ

= 45°C/W, θ

= 10°C/W

EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB

LTC3725EMSE

LTC3725IMSE

ABSOLUTE AXI U RATI GS

PACKAGE/ORDER I FOR ATIO

UUW

(Note 1)

ELECTRICAL CHARACTERISTICS

The ● denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. VCC = 12V, GND = PGND = 0V, TA = 25°C, unless otherwise noted.

MSE PART MARKING

UVLO

SSFLT

NDRV

FB/IN

FS/IN

–

SLMT

GATE

PGND

TOP VIEW

MSE PACKAGE

10-LEAD PLASTIC MSOP

LTBSV

LTBSW

Order Options Tape and Reel: Add #TR

Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF

Lead Free Part Marking: http://www.linear.com/leadfree/

Consult LTC Marketing for parts specified with wider operating temperature ranges.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Supply, Linear Regulator and Trickle Charger Shunt Regulator

CCOP

Operating Voltage Range 7 12 15 V

CCLR

Output Voltage Linear Regulator in Operation 8 V

NDRV

Current into NDRV Pin Linear Regulator in Operation 0.1 1 mA

r(VCC)

Rise Time of V

Linear Regulator Charging (0.5V to 7.5V) 45 µs

NDRVTO

Linear Regulator Time Out Current Threshold Primary-Side Operation 0.27 mA

Supply Current V

UVLO

= 1.5V, Linear Regulator in 1.4 2.1 mA

Operation (Note 3)

CCM

Maximum Supply Current V

UVLO

= 1.5V, Trickle Charger in Operation, 1.7 2.5 mA

= 13.2V (Note 3)

CCSR

Maximum Supply Voltage Trickle Charger Shunt Regulator 14.25 15 V

CCSR

Minimum Current into NDRV/V

Trickle Charger Shunt Regulator, V

= 15V 10 mA

(Note 3)

Internal Undervoltage

CCUV

Internal Undervoltage Threshold V

Rising 5.3 V

Falling 4.7 V

Gate Drive Undervoltage

GDUV

Gate Drive Undervoltage Threshold V

Rising (Linear Regulator) ●7.2 7.4 7.7 V

Rising (Trickle Charger) ●13.1 13.4 14 V

Falling ●6.8 7.0 7.2 V

Undervoltage Lockout (UVLO)

UVLOR

Undervoltage Lockout Threshold Rising Rising ●1.220 1.242 1.280 V

UVLOF

Undervoltage Lockout Threshold Falling Falling ●1.205 1.226 1.265 V

LTC3725

3725fa

The ● denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. VCC = 12V, GND = PGND = 0V, TA = 25°C, unless otherwise noted.

ELECTRICAL CHARACTERISTICS

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: Operating junction temperature T

(in °C) is calculated from the

ambient temperature T

and the average power dissipation PD (in watts)

by the formula: T

= T

+ θ

• PD. Refer to the Applications Information

section for details.

Note 3: I

is the sum of current into NDRV and V

Note 4: The LTC3725EMSE is guaranteed to meet performance

specifications from 0°C to 85°C. Specifications over the –40°C to 85°C

operating temperature range are assured by design, characterization and

correlation with statistical process controls. The LTC3725IMSE is

guaranteed and tested over the – 40°C to 85°C operating temperature

range.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

HUVLO

Hysteresis Current V

UVLO

= 1V ●4.2 4.9 5.6 µA

UVLOOP

Voltage Feedforward Operating Range Primary-Side Control V

UVLOF(MIN)

3.75 V

Gate Driver (GATE)

Output Pull-Down Resistance I

OUT

= 100mA 1.9 Ω

High Output Voltage I

OUT

= –100mA 11 V

Peak Pull-Up Current 1.7 A

Output Rise Time 10% to 90%, C

OUT

= 4.7nF 40 ns

Output Fall Time 10% to 90%, C

OUT

= 4.7nF 70 ns

Rectifier

RECT

Maximum Rectifier DC Output Current 25 mA

Oscillator

OSC(P)

Oscillator Frequency Primary-Side Control, R

FS(P)

= 100kΩ200 kHz

Primary-Side Control, R

FS(P)

= 25kΩ700 kHz

Primary-Side Control, R

FS(P)

= 300kΩ70 kHz

∆f

RFS(P)

Oscillator Resistor Set Accuracy Primary-Side Control

25k < R

FSET

< 300k ±15 %

OSC(S)

Oscillator Frequency Secondary-Side Control (During Start-Up), 300 kHz

FS(S)

= 100kΩ

Soft-Start/Fault (SSFLT)

SS(C)

Soft-Start Charge Current Primary-Side Control, V

SSFLT

= 2V –5.2 µA

Secondary-Side Control, V

UVLO

= 1.3V, –4 µA

SSFLT

= 2V

Secondary-Side Control, V

UVLO

= 3.75V, –1.6 µA

SSFLT

= 2V

LRTO

Linear Regulator Time Out-Threshold 3.9 V

FLTH

Fault Output High V

= 8V 6.7 V

SS(D)

Soft-Start Discharge Current Timing Out After Fault, V

SSFLT

= 2V 1 µA

Current Sense Input (I

)

IS(MAX)

Overcurrent Threshold 300 mV

Volt Second Limit (V

SLMT

)

VSL(MAX)

Volt-Second Limit Threshold 1.26 V

VSLMT(MAX)

Maximum Volt-Second Limit Resistor Current 0.25 mA

Optoisolator Bias Current

OPTO

Open Circuit Optoisolator Voltage Primary-Side Control I

= 0V 3.3 V

OPTO

Optoisolator Bias Current Primary-Side Control V

= 2.5V 0.5 mA

Primary-Side Control V

= 0V 1.6 mA

LTC3725

3725fa

Supply Current vs VCC

UVLO Voltage Threshold vs

Temperature

UVLO Hysteresis Current vs

Temperature

Oscillator Frequency

fOSC vs RFSET

Oscillator Frequency vs

Temperature

Shunt Regulator Current ICC

vs VCC

Shunt Regulator Current vs

Temperature VGDUV vs Temperature

TYPICAL PERFOR A CE CHARACTERISTICS

Optoisolator Bias VFB/IN+ vs

IFB/IN+

VCC (V)

CURRENT (mA)

1.0

1.5

3725 G01

0.5

010

2.0

TRICKLE CHARGER

LINEAR REGULATOR

TEMPERATURE (°C)

–60

UVLO THRESHOLD (V)

1.240

1.235

1.230

1.225

100

3725 G02

1.220 40 60 80

0–20 20–40

1.245

UVLOF

UVLOR

TEMPERATURE (°C)

–60

HUVLO

(µA)

5.00

4.95

4.90

4.85

100

3725 G03

4.80 40 60 80

0–20 20–40

5.05

RFSET (kΩ)

fOSC (kHz)

300

200

100

400300200100

3725 G04

800

700

400

500

600

SECONDARY-SIDE CONTROL

PRIMARY-SIDE CONTROL

TEMPERATURE (°C)

–60

OSCILLATOR FREQUENCY f

OSC(P)

(kHz)

202

201

200

199

100

3725 G05

197

198

40 60 80

0–20 20–40

203

PRIMARY-SIDE CONTROL

FS(P)

= 100kΩ

(V)

14.00

(mA)

15.0014.7514.5014.25

3725 G06

TEMPERATURE (°C)

–60

CCSR

(mA)

100

3725 G07

40 60 80

0–20 20–40

TEMPERATURE (°C)

–60

GDUV

(V)

100

3725 G08

40 60 80

0–20 20–40

RISING (TRICKLE CHARGER)

RISING (LINEAR REGULATOR)

FALLING (BOTH)

–I

FB/IN

+ (mA)

FB/IN

+ (V)

1.5

1.0

0.5

2.01.51.00.5

3725 G09

3.5

2.0

2.5

3.0

LTC3725

3725fa

TYPICAL PERFOR A CE CHARACTERISTICS

Gate Drive Pull-Down Resistance

vs Temperature

Gate Drive Peak Pull-Up Current

vs Temperature

Linear Regulator Start-Up Gate Drive Encoding Fault Operation

TEMPERATURE (°C)

–60

GATE DRIVE RESISTANCE R

(Ω)

2.25

2.00

1.75

100

3725 G10

1.50 40 60 80

0–20 20–40

2.50

TEMPERATURE (°C)

–60

(A)

1.9

1.8

1.7

1.6

100

3725 G11

1.5 40 60 80

0–20 20–40

2.0

5V/DIV

25µs/DIV 3725 G12

NDRV

10V/DIV

1µs/DIV 3705 G13

GATE

FB/IN

FS/IN–

2V/DIV

10V/DIV

40ms/DIV 3725 G14

GATE

SSFLT

LTC3725

3725fa

PI FU CTIO S

UVLO (Pin 1): Undervoltage Lockout. Connect to a resis-

tive voltage divider to monitor input voltage V

. Enables

converter operation for V

UVLO

> 1.242V. Hysteresis is a

fixed 16mV hysteresis voltage with a 4.9µA hysteresis

current that combines with the Thevenin resistance of the

divider to set the total UVLO hysteresis voltage. This input

also senses V

for voltage feedforward. Finally, this pin

can be used for external run/stop control.

SSFLT (Pin 2): Combination Soft-Start and Fault Indica-

tor. A capacitor to GND sets the duty cycle ramp-up rate

during start-up. To indicate a fault, the SSFLT pin is

momentarily pulled up to within 1.3V of V

NDRV (Pin 3): Drive for the External NMOS Linear Regu-

lator. Connect to the gate of the NMOS and connect a pull

up resistor to the input voltage (V

). Optionally, to create

a trickle charger omit the NMOS device and connect NDRV

to V

FB/IN

(Pin 4): This pin has several functions. One wind-

ing of a pulse transformer is connected to the FB/IN

and

FS/IN

–

pins. The other pulse transformer winding is con-

nected to the LTC3706. The LTC3725 automatically de-

tects when the LTC3706 applies a pulse-encoded signal to

the FB/IN

and FS/IN

–

pins and decodes duty cycle infor-

mation for control of the primary-side gate drive (see

Operation below). In secondary-side control, primary-

side gate drive bias power is also extracted from the FB/IN

and FS/IN

–

pins using an on-chip full-wave rectifier.

For primary-side control connect this pin to an optoisolator

for feedback control of converter output voltage using an

internal optoisolator biasing network.

FS/IN

–

(Pin 5): This pin has several functions. Place a

resistor from this pin to GND to set the oscillator fre-

quency. For secondary-side control with the LTC3706,

connect one winding of the pulse transformer for opera-

tion as described for the FB/IN

pin above.

PGND (Pin 6): Supply Return for the Bottom Gate Driver

and the On-Chip Bridge Rectifier.

GATE (Pin 7): Gate Drive. Connect to the gate of the

external MOSFET.

(Pin 8): Main V

Power for All Driver and Control

Circuitry.

SLMT

(Pin 9): Volt-Second Limit. Form an R-C integrator

by connecting a resistor from V

to V

SLMT

and a capacitor

from V

SLMT

to ground. The gate drive is turned off when

the voltage on the V

SLMT

pin exceeds 1.26V.

(Pin 10): Input to the Overcurrent Comparator. Connect

to the positive terminal of a current-sense resistor in

series with the source of the ground-referenced bottom

MOSFET.

GND (Pin 11): Signal Ground.

LTC3725

3725fa

BLOCK DIAGRA

–

7.4V/7V

LINEAR

REGULATOR

13.4V/7V

TRICKLE

CHARGER

–

5.3V/4.7V

14.25V

SOFT-START

FAULT

REGULATOR

–

0.27mA LINE OFF

TIME

4.9µA

0.66

VFF

1.242V

1.226V

UVINT

UVGD

300mV

210

NDRV

SSFLT

UVLO

GND

(PAD)

FB/IN+

FS/IN–

FREQUENCY

SET

OPTO

BIAS

RECTIFIER

PWM

RECEIVER

CONDITION SW

DET

IN+

IN–

VCC

SHUNT REGULATOR

7GATE

8VCC

6PGND

VCC

PGND

TRICKLE

CHARGE

0.6V

400mV

INDRV

UVVIN

PWM

PRIMARY

CONTROL

DRIVE

LOGIC

9VSLMT

OSCILLATOR

N/C

VP-P

IOSC

PRIMARY

SIDE CONTROL

PWM SECONDARY CONTROL

SECONDARY SIDE CONTROL

3.3V

CLOCK

RAMP

VP-P

SWITCH

1.26V

3725 BD

DET

LTC3725

3725fa

Mode Setting

The LTC3725 is a controller and gate driver designed

for use in a single-switch forward converter. When used

in conjunction with the LTC3706 PolyPhase secondary-

side synchronous forward controller, it forms a complete

forward converter with secondary-side regulation, gal-

vanic isolation between input and output, and synchro-

nous rectification. In this mode, upon start-up, the FB/

and FS/IN

–

pins are effectively shorted by one winding

of the pulse transformer. The LTC3725 detects this short

circuit to determine that it is in secondary-side control

mode. Operation in this mode is confirmed when the

LTC3706 begins switching the pulse transformer.

Alternately, the LTC3725 can be used as a standalone

primary-side controller. In this case, the FB/IN

and FS/IN

–

pins operate independently. The FB/IN

pin is connected to

the collector of an optoisolator to provide feedback and the

FS/IN

–

pin is connected to the frequency set resistor.

Gate Drive Encoding

In secondary-side control with the LTC3706, after a start-

up sequence, the LTC3706 transmits multiplexed PWM

information through a pulse transformer to the FB/IN

and

FS/IN

–

inputs of the LTC3725. In the LTC3725, the PWM

receiver extracts the duty cycle and uses it to control the

gate driver.

Figure 1 shows that the LTC3706 drives the pulse trans-

former in a complementary fashion, with a duty cycle of

approximately 75%. At the appropriate time during the posi-

tive half cycle, the LTC3706 applies a short (150ns) zero-

voltage pulse across the pulse transformer, indicating the

end of the “on” time. Although this scheme allows the trans-

mission of 0% to 75% duty cycle, it is necessary to estab-

lish a minimum controllable “on” time of approximately

100ns. This ensures that 0% duty cycle can be reliably dis-

tinguished from 75% duty cycle.

On-Chip Rectifier

Simultaneously with duty-cycle decoding, and through

the same pulse transformer, the wave generated by the

LTC3706 provides primary-side V

gate drive bias power

by way of the LTC3725’s on-chip full-wave bridge rectifier.

No auxiliary bias supply is necessary and forward con-

verter design and circuitry are considerably simplified.

External Series Pass Linear Regulator

The LTC3725 features an external series pass linear regu-

lator that eliminates the long start-up time associated with

the conventional trickle charger. The drain of an external

NMOS is connected to the input voltage and the source is

connected to V

. The gate of the NMOS is connected to

NDRV. To power the gate, an external pull-up resistor is

connected from the input voltage to NDRV. The NMOS

must be a standard 3V threshold type (i.e. not logic level).

An on-chip circuit manages the start up and operation of

the linear regulator. It takes approximately 45µs for the

linear regulator to charge V

to its target value of 8V

(unless limited by a slower rise of V

). The LTC3725

begins operating the gate drives when V

reaches 7.4V.

Often, the thermal rating of the NMOS prevents it from

operating continuously, and the LTC3725 “times out” the

linear regulator to prevent overheating. This is accom-

plished using the capacitor connected to the SSFLT pin as

described subsequently.

Trickle Charger Shunt Regulator

Alternately, a trickle charger can be implemented by

eliminating the external NMOS and connecting NDRV to

and using the pull-up resistor to charge V

. To allow

extra headroom for starting, the LTC3725 detects this

mode and increases the threshold for starting the gate

drives to 13.4V. An internal shunt regulator limits the

voltage on the trickle charger to 15V.

OPERATIO

Figure 1. Gate Drive Multiplexing Scheme

DUTY CYCLE = 15% DUTY CYCLE = 0%

150ns

150ns 150ns

3725 F01

1 CLK PER 1 CLK PER

+7V

–7V

PT1+

– V

PT1–

LTC3725

3725fa

Self-Starting Architecture

The LTC3725 is combined with the LTC3706 to form a

complete self-starting DC isolated power supply. When

power is first applied, and when V

for the LTC3725 is

above the appropriate threshold, the LTC3725 begins

open-loop operation using its own internal oscillator.

Power is supplied to the secondary by switching the gate

driver with a gradually increasing duty cycle as controlled

by the rate of rise of the voltage on the SSFLT pin. A peak

detector power supply for the LTC3706 allows it to begin

operation even for small duty cycles. Once adequate

voltage is available for the LTC3706, it provides duty cycle

information and gate drive bias power using the pulse

transformer as shown in Figure 1. The LTC3725 detects

the appearance of this signal and transfers control of the

gate drivers to the LTC3706. Simultaneously, the LTC3725

also enables the on-chip rectifier and turns off the linear

regulator.

Alternately, when the LTC3725 is used as a standalone

primary-side controller, the gradually increasing duty cycle

powers up a secondary-side reference and optoisolator and

feedback is accomplished when the output of the

optoisolator begins pulling down in the FB/IN

pin.

Soft-Start and Fault

These two functions are implemented using the SSFLT

pin. (This pin is also used for linear regulator timeout as

described in the following section.)

Initiating soft-start requires that: 1) the gate drive

undervoltage (UVGD) goes low meaning that adequate

voltage is available on the V

pin (7.4V for the linear

regulator or 13.4V for the trickle charger) and 2) the input

undervoltage (UVV

) goes low meaning that the voltage

on the UVLO pin has reached the 1.242V rising threshold.

During soft-start, the LTC3725 gradually charges the soft-

start capacitor to ramp up the converter duty cycle. Soft-

start is over when the voltage on the SSFLT pin reaches 2.8V.

In normal operation, at some point before this, the LTC3725

makes a transition to controlling duty cycle using closed-

loop regulation of the converter output voltage.

The SSFLT pin is also used to indicate a fault. The LTC3725

recognizes faults from four origins: 1) an overcurrent fault

caused by the current sense voltage on the IS pin exceed-

ing the 300mV overcurrent threshold, 2) an input

undervoltage fault caused by the UVLO pin falling below

the 1.226V falling threshold, 3) a gate drive undervoltage

fault caused by the voltage on the V

pin falling below the

7V threshold, or 4) loss of the gate drive encoding signal

from the LTC3706.

Upon sensing a fault, the LTC3725 immediately turns off

the gate drive and indicates a fault by quickly pulling the

voltage on the SSFLT pin to within 1.3V of the voltage on

the V

pin. After indicating the fault, the LTC3725 quickly

ramps down the voltage on the SSFLT pin to approxi-

mately 2.8V. Then, to allow complete discharge of the

secondary-side circuit, the LTC3725 slowly ramps down

the voltage on the SSFLT pin to about 200mV. The LTC3725

then attempts a restart.

Linear Regulator Timeout

The thermal rating of the linear regulator’s external NMOS

often cannot allow it to indefinitely supply bias current to

the primary-side gate drives. The LTC3725 has a linear

regulator timeout mechanism that also uses the SSFLT

capacitor.

As described in the prior section, soft-start is over once the

voltage on the SSFLT pin reaches 2.8V. However, the

SSFLT capacitor continues to charge and the linear regu-

lator is turned off when the voltage on the SSFLT pin

reaches 3.9V. The “Applications Information” section de-

scribes linear regulator timeout in more detail.

Volt-Second Limit

The volt-second limit ensures that the power transformer

core does not saturate for any combination of duty cycle

and input voltage. The input of an R-C integrator is

connected to V

and its output is connected to the V

SLMT

pin. While the gate drive is “off,” the LTC3725 grounds the

SLMT

pin. When the gate drive is turned “on” the V

SLMT

pin is released and the capacitor is allowed to charge in

proportion to V

. If the capacitor voltage on the V

SLMT

OPERATIO

LTC3725

3725fa

exceeds 1.26V the gate drive is immediately turned “off.”

Note that this is not considered a fault condition and the

LTC3725 can run indefinitely with the switch duty cycle

being determined by the volt-second limit circuit. The duty

cycle is always limited to 75% to ensure that the power

transformer flux always has time to reset before the start

of the next cycle.

In an alternate application, the volt-second limit can be

used for open-loop regulation of the output against changes

in V

Current Limit

Current limit for the LTC3725 is principally a safety feature

to protect the converter and is not part of a control

function. The current that flows in series through the

transformer primary and the switch is sensed by a resistor

connected between the source of the switch and GND. If

the voltage across this resistor exceeds 300mV, the

LTC3725 initiates a fault.

Voltage Feedforward

The LTC3725 uses voltage feedforward to properly modu-

late the duty cycle as a function of the input voltage. For

secondary-side control with the LTC3706, voltage

feedforward is used during start-up only. The duty cycle

during start up is determined by comparison of the voltage

on the SSFLT pin to a 75% duty cycle triangle wave with

an amplitude of 2V. To implement voltage feedforward, the

charging current for the soft-start capacitor is reduced in

proportion to the input voltage. As a result, the initial rate

of rise of the converter output voltage is held approxi-

mately constant regardless of the input voltage. At some

point during start-up, the LTC3706 begins to switch the

pulse transformer and take over the soft-start.

For operation with standalone primary-side control and

optoisolator feedback, voltage feedforward is used during

both start-up and normal operation. The duty cycle is

determined by using a 75% duty cycle triangle wave with

an amplitude equal to 66% of the voltage on the UVLO pin

which is, in turn, proportional to V

. The charging current

for the soft-start capacitor is a constant 5.2µA. During

soft-start, the duty cycle is determined by comparing the

voltage on the SSFLT pin to the triangle wave. Soft-start is

concluded when the voltage on the SSFLT pin exceeds the

voltage on the FB/IN

pin. After the conclusion of soft-

start, the duty cycle is determined by comparison of the

voltage on the FB/IN

pin to the triangle wave.

Optoisolator Bias

When the LTC3725 is used in standalone primary-side

mode, feedback is provided by an optoisolator connected

to the FB/IN

pin. The LTC3725 has a built optoisolator

bias circuit which eliminates the need for external

components.

OPERATIO

LTC3725

3725fa

Note that a trickle charger usually requires a large capaci-

tor to provide holdup for the V

pin while the converter

attempts to start. The linear regulator in the LTC3725 can

both charge the capacitor connected to the V

pin and

provide primary-side gate-drive bias current. Therefore,

with the linear regulator, the capacitor need only be large

enough to cope with the ripple current from driving the gate

of the primary FET and holdup need not be considered.

The external NMOS for the linear regulator should be a

standard 3V threshold type (i.e. not a logic level thresh-

old). The rate of charge of V

from 0V to 8V is controlled

by the LTC3725 to be approximately 45µs regardless of

the size of the capacitor connected to the V

pin. The

charging current for this capacitor is approximately:

=µ

The safe operating area (SOA) for the external NMOS

should be chosen so that capacitor charging does not

damage the NMOS. Excessive values of capacitor are

unnecessary and should be avoided.

Start-Up Considerations

When used in a self-starting converter with the LTC3706,

the LTC3725 initially begins the soft-start of the converter

in an open-loop fashion. After bias is obtained on the

secondary side, the LTC3706 assumes control and com-

pletes the soft-start interval. In order to ensure that control

is properly transferred from the LTC3725 (primary-side)

to the LTC3706 (secondary-side), it is necessary to limit

the rate of rise on the primary-side soft-start ramp so that

the LTC3706 has adequate time to wake up and assume

control before the output voltage gets too high. This

condition is satisfied for many applications if the following

relationship is maintained:

SS,SEC

≤ C

SS_PRI

APPLICATIO S I FOR ATIO

WUUU

Figure 2. Resistive Voltage Divider for

UVLO and Optional Run/Stop Control

UVLO

The UVLO pin is connected to a resistive voltage divider

connected to V

as shown in Figure 2. The voltage

threshold on the UVLO pin for V

rising is 1.242V. To

introduce hysteresis, the LTC3725 draws 4.9µA from the

UVLO pin when V

is rising. The hysteresis is therefore

user adjustable and depends on the value of R1. The UVLO

threshold for V

rising is:

RRA

IN UVLO RISING(, )

(. ) (. )=++µ1 242 12

2149

The LTC3725 also has 16mV of voltage hysteresis on the

UVLO pin so that the UVLO threshold for V

falling is:

IN UVLO FALLING(, )

(. )=+

1 226 12

To implement external Run/Stop control, connect a small

NMOS to the UVLO pin as shown in Figure 2. Turning the

NMOS on grounds the UVLO pin and prevents the LTC3725

from running.

RUN/STOP

CONTROL

(OPTIONAL)

UVLO

GND

LTC3725

3725 F02

Linear Regulator

The linear regulator eliminates the long start-up times

associated with a conventional trickle charger by using an

external NMOS to quickly charge the capacitor connected

to the V

pin.

LTC3725

3725fa

However, care should be taken to ensure that soft-start

transfer from primary-side to secondary-side is com-

pleted well before the output voltage reaches its target

value. A good design goal is to have the transfer completed

when the output voltage is less than one-half of its target

value. Note that the fastest output voltage rise time during

primary-side soft-start mode occurs with minimum load

current.

The open-loop start-up frequency on the LTC3725 is set

by placing a resistor R

FS(S)

from the FS/IN

–

pin to GND.

Although the exact start-up frequency on the primary side

is not critical, it is generally a good practice to set it

approximately equal to the operating frequency on the

secondary side.

In this mode the start-up frequency of the LTC3725 is

approximately:

PRI FS S

34 10

10 000

•

()

In the event that the LTC3706 fails to start up properly and

assume control of switching, there are several fail-safe

mechanisms to help avoid overvoltage conditions. First,

the LTC3725 implements a volt-second clamp that may be

used to keep the primary-side duty cycle at a level that

does not produce an excessive output voltage. Second,

the timeout of the linear regulator (described in the follow-

ing section) means that, unless the LTC3706 starts and

supports the LTC3725 gate drive through the pulse trans-

former and on-chip rectifier, the LTC3725 eventually suf-

fers a gate drive undervoltage fault. Finally, the LTC3706

has an independent overvoltage detection circuit that

crowbars the output of the DC/DC converter using the

synchronous secondary-side MOSFET switch.

In the event that a short-circuit is applied to the output of

the converter prior to start-up, the LTC3706 generally

does not receive enough bias voltage to operate. In this

case, the LTC3725 detects a FAULT for one of two reasons:

1) since the LTC3706 never sends pulse encoding to the

LTC3725, the linear regulator times out resulting in a gate

drive undervoltage fault, or 2) the primary-side overcurrent

circuit is tripped because of current buildup in the output

inductor. In either case, the LTC3725 initiates a shutdown

followed by a soft-start retry.

Linear Regulator Timeout

After start-up, the LTC3725 times out the linear regulator

to prevent overheating of the external NMOS. The timeout

interval is set by further charging the soft-start capacitor

SSFLT

from the end-of-soft-start voltage of approximately

2.8V to the timeout threshold of 3.9V. Linear regulator

timeout behaves differently depending on mode.

In primary-side standalone mode, the LTC3725 generally

requires that an auxiliary gate drive bias supply take over

from the linear regulator. (See the subsequent section for

more detail on the auxiliary supply.) During linear regula-

tor timeout, the rate of rise of the soft-start capacitor

voltage depends on the current into the NDRV pin as

controlled by the pull-up resistor R

PULLUP

, the value of V

and the value of V

NDRV

IVV

NDRV IN NDRV

PULLUP

=–

The value of V

NDRV

is V

= 8V plus the value of the gate-

to-source voltage (V

NDRV

– V

) of the external NMOS in

the linear regulator. The gate-to-source voltage depends

on the actual device but is approximately the threshold

voltage of the external NMOS.

For I

NDRV

> 0.27mA, the capacitor on the SSFLT pin is

charged in proportion to (I

NDRV

– 0.27mA) until the linear

regulator times out. Thus, since V

NDRV

is very nearly

constant, the timeout interval for the linear regulator is

inversely proportional to the input voltage and a higher

input voltage produces a shorter timeout.

tCVV

RmA

TIMEOUT SSFLT

IN NDRV

PULLUP

=−

⎡

⎣

⎢⎤

⎦

⎥

66 39 28

027

(. – . )

–.

APPLICATIO S I FOR ATIO

WUUU

LTC3725

3725fa

APPLICATIO S I FOR ATIO

WUUU

Since the power dissipation of the linear regulator is

proportional to the input voltage, this strategy of making

the timeout inversely proportional to the input voltage

produces an approximately constant temperature excur-

sion for the external NMOS of the linear regulator regard-

less of the input voltage.

In situations for which the continuous operation of the

linear regulator does not exceed the thermal limitations of

the external NMOS (i.e. converters with low V

or with

minimal gate drive bias requirements), the auxiliary sup-

ply can be omitted and the linear regulator allowed to

operate continuously. If I

NDRV

is less than 0.27mA the

linear regulator never times out and the voltage on the

SSFLT pin stays at approximately 2.8V after start-up is

completed. To accomplish this set:

RVV

PULLUP IN MAX NDRV

()

–

.027

where V

IN(MAX)

is the maximum expected continuous

input voltage. Note that once the linear regulator is turned

off it locks out. Therefore when using this strategy, care

should be taken to ensure that a transient higher than

IN(MAX)

does not persist longer than t

TIMEOUT

In secondary-side operation with the LTC3706, there is

never any need for continuous operation of the linear

regulator since gate drive bias power is provided by the

LTC3706 through the pulse transformer and on-chip

rectifier. The LTC3725 shuts down the linear regulator

once the LTC3706 begins switching the pulse trans-

former. If the LTC3706 fails to start, the LTC3725 quickly

times out the linear regulator once the voltage on the

SSFLT pin reaches 2.8V.

Fault Lockout

The LTC3725 indicates a fault by pulling the SSFLT pin to

within 1V of V

. The LTC3725 subsequently attempts a

restart. Optionally, the user can prevent restart and “lock

out” the converter by clamping the voltage on the SSFLT

pin with a 4.3V zener diode. Once the converter has locked

out it can only be restarted by the removal of the input

voltage or by release of the zener diode clamp.

Pulse Transformer

The pulse transformer that connects the LTC3706 to the

LTC3725 performs the dual functions of gate drive duty

cycle encoding and gate drive bias supply for the LTC3725

by way of the on-chip full-wave rectifier. The designs of the

LTC3725 and LTC3706 have been coordinated so that the

transformer turn ratio is:

LTC3725

= 2N

LTC3706

where N

LTC3725

is the number of turns in the winding

connected to the FB/IN

and FS/IN

–

pins of the LTC3725

and N

LTC3706

is the number of turns in the winding

connected to the PT

and PT

–

pins of the LTC3706. The

winding connected to the LTC3706 must be able to with-

stand volt-seconds equal to:

(–)Vs V

MAX CC

where V

is the maximum supply voltage for the LTC3706

and f is the operating frequency of the LTC3706.

LTC3725

3725fa

former from their corresponding LTC3706. To synchro-

nize operation, the SSFLT and V

pins of the master are

connected to the corresponding pins of all the slaves. The

master is designated by connection of the frequency set

resistor to the FS/IN

–

pin while this resistor is omitted from

the slaves. For the slaves the NDRV pin is connected to the

pin. See the following section on PolyPhase Applica-

tions for more detail.

PolyPhase Applications

Figure 4 shows the basic connections for using the LTC3725

and LTC3706 in PolyPhase applications. One of the phases

is always identified as the “master,” while all other phases

are “slaves.” For the LTC3725 (primary side), the master

performs the open-loop start-up and supplies the initial

voltage for the master and all slaves. The LTC3725

slaves are put into that mode by omitting the resistor on

FS/IN–. The LTC3725 slaves simply stand by and wait for

PWM signals from their respective pulse transformers.

Since the SSFLT pins of master and slave LTC3725s are

interconnected, a FAULT (overcurrent, etc.) on any one of

the phases will perform a shutdown/restart on all phases

together.

For the LTC3706, the master performs soft-start and

voltage-loop regulation by driving all slaves to the same

current as the master using the I

pins. Faults and

shutdowns are communicated via the interconnection of

the RUN/SS pins. The LTC3706 is put into slave mode by

tying the FB pin to V

Auxiliary Supply

When used with the LTC3706, the LTC3725 does not

require an auxiliary supply to provide primary-side gate-

drive bias current. After start-up, primary-side gate drive

current is provided by the LTC3706 through a small pulse

transformer and the LTC3725’s on-chip rectifier.

However, when used as a standalone primary-side con-

troller, the LTC3725 may require a conventional gate-drive

bias supply as shown in Figure 3. The bias supply must be

designed to keep the voltage on the V

pin between the

absolute maximum of 15V and the gate-drive undervoltage

lockout of 7V.

The auxiliary supply is connected in parallel with V

. The

linear regulator maintains V

at 8V. If the auxiliary supply

produces more than 8V, it turns off the external NMOS

before the LTC3725 can time out the linear regulator. If the

auxiliary supply produces less than 8V, the linear regulator

times out and then the voltage on the V

pin declines to

the voltage produced by the auxiliary supply.

Slave Mode Operation

When the LTC3725 is paired with the LTC3706, multiple

pairs can be used to form a PolyPhase converter. In

PolyPhase operation, one LTC3725 becomes the “master”

while the remainder become “slaves.” The master con-

trols start-up in the same manner as for the single-phase

converter, while the slaves do not begin switching until

receiving PWM information through their own pulse trans-

APPLICATIO S I FOR ATIO

WUUU

Figure. 3. Auxiliary Supply for Primary-Side Control

POWER

TRANSFORMER

2.2µF

PRIMARY

WINDING N

SECONDARY

WINDING N

BAS21

1mH

LTC3725

3725 F03

NDRV

GND

AUXILIARY

WINDING N

LTC3725

3725fa

APPLICATIO S I FOR ATIO

WUUU

Figure 4. Connections for PolyPhase

NDRV

UVLO

LTC3725

(MASTER)

VCC

SS/FLT

FB/IN+

FS/IN–

VIN–

VIN+

VIN NDRV VCC

PT+

PT–

RUN/SS

LTC3706

(MASTER)

ITH

3725 F04

VOUT+

VBIAS

FS/SYNC

••

NDRV

SS/FLT

LTC3725

(SLAVE)

VCC

UVLO

FB/IN+

FS/IN–

VIN NDRV VCC

PT+

PT–

RUN/SS

LTC3706

(SLAVE)

ITH

PHASE

FS/SYNC

••

Standalone Primary-Side Operation

The LTC3725 can be used to implement a standalone

forward converter using optoisolator feedback and a

secondary-side voltage reference. Alternately the LTC3725

can be used to implement an open-loop forward converter

using the V

SLMT

pin to regulate against changes in V

. In

either case, the LTC3725 oscillator determines the fre-

quency as found from:

OSC FS P

21 10

4200

•

()

Note that polyphase operation is not possible in the stand-

alone configuration.

Grounding Considerations

The LT3725 is typically used in high current converter

designs that involve substantial switching transients. Fig-

ure 5 illustrates these currents. The switch driver on the IC

is designed to drive a large capacitance and, as such,

generate significant transient currents. Careful consider-

ation must be made regarding input and local power

supply bypassing to avoid corrupting the ground refer-

ences used by the UVLO and frequency set circuitry.

Typically, high current paths and transients from the input

supply and any local drive supplies must be kept isolated

from GND. By virtue of the topologies used in LT3725

applications, the large currents from the primary switch,

as well as the switch drive transients, pass through the

sense resistor to ground. This defines the ground connec-

tion of the sense resistor as the reference point for both

GND and PGND.

LTC3725

3725fa

Figure 5. High Current Transient Return Paths

APPLICATIO S I FOR ATIO

WUUU

LTC3725

FS/IN–

GND

SIGNAL GROUND PLANE

POWER GROUND PLANE

VIN

GATE

VCC

PGND

UVLO

3725 F05

Effective grounding can be achieved by considering the

return current paths from the sense resistor to each

respective bypass capacitor. Don’t be tempted to run small

traces to separate the grounds. A power ground plane is

important as always in high power converters, but care

must be taken to keep high current paths away from the

GND reference. An effective approach is to use a 2-layer

ground plane, reserving an entire layer for GND and an

entire layer for PGND. The UVLO and frequency set

resistors can then be directly connected to the GND plane.

LTC3725

3725fa

TYPICAL APPLICATIO S

Figure 6. 36V-72V to 3.3V/30A Isolated Forward Converter Using LTC3706

Efficiency

FB/IN

470pF

1µF

100V

×2

1µF

100V

IN+

IN–

100Ω

2.2nF

200V

2.2nF

50V

2.2nF

50V

10µF

100µF

6.3V

×2

220µF

6.3V

OUT+

3.3V

30A

OUT–

47nF

470pF

33nF

B0540W

Si7450DP

33nF

470pF

1µF, 100V TDK C3225X7R2A105M (1210)

100µF, 6.3V TDK C3225X5R0J107M (1210)

220µF, 6.3V SANYO 6TPE220M

2.2nF, 250V AC MURATA GA343QR7GD222KW01L (1210)

L1: COILCRAFT DO1813P-331HC

L2: PULSE PA1294.910

T1: PULSE PA0815 6:6:2:1

T2: PULSE PA0297 2(1.4mH):1:1

15k

1µF

0.1µF1µF

2.2nF

250V

OUT–

68pF

2.2µF

5.1k

0.0012

HAT2165

×2

HAT2165

×2

0.85µH

100Ω

0.030Ω

5.1Ω

1/2W

5.1Ω

1/2W

680pF

1T2

••

100Ω

162k

100Ω

3.3k100k

2.74k

604Ω

3725 F06a

1.2Ω

1/4W

100k

FS/IN

–

UVLO

SSFLT

GATE

LTC3725

NDRV

GNDPGNDVSLMT

365k

FDC2512

23.4 × 20.1 × 9.4mm PLANAR

••

FG SW I

S–

S+

SG V

MODENDRV

GND PGND RUN/SS SLP REGSD FS/SYNC I

PHASE

FCX491A

–

FBLTC3706

0.33µH

36V TO 72V

LOAD CURRENT (A)

EFFICIENCY (%)

48V

72V

36V

3725 F06b

84 10 15 20 30

LTC3725

3725fa

TYPICAL APPLICATIO S

Figure 7. 12VIN to 48V/1.5A Isolated Forward Converter Using Optoisolator

FB/IN+

10µF

25V

10µF

25V

VIN+

VIN–

33nF

470pF

MOC207

105k

470pF

10µF, 25V TDK C3225X7R1E106M (1210)

27µF, 100V SANYO MV-AX

1.5µF, 63V FILM WIMA MKS2

2.2nF, 250V AC MURATA GA343QR7GD222KW01L

L1: PULSE PE-53911

L2, L3: TDK SLF12575T-101M1R9

T1: PULSE PA0700 3T(16µH):11:11

15k

115k

1µF

100Ω

0.010Ω

1.5W

1nF

100V

100pF

1kV

100µH

1nF

2.2nF

250V AC

110Ω

0.5W

27µF

100V

1.5mH

3710

9.1V

10nF

100V

2.4k

0.25W

2.4k

0.25W

1k 1k

2.49k

45.3k

252

9611

FS/IN–

VCC

UVLO

SSFLT

GATE

LTC3725

NDRV

GNDPGNDVSLMT

MMBD914

EFD25

12V 10µF

25V

Si7370DP

×2

100µH

–VS

MURHB860CT

•

27µF

100V

1.5µF

63V

FILM

VOUT+

VOUT–

GND-F GND-S

V+

LT1431

COLL REF

47nF

48V

1.5A

LTC3725

3725fa

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

PACKAGE DESCRIPTIO

MSE Package

10-Lead Plastic MSOP

(Reference LTC DWG # 05-08-1663)

MSOP (MSE) 0603

0.53 ± 0.152

(.021 ± .006)

SEATING

PLANE

0.18

(.007)

1.10

(.043)

MAX

0.17 – 0.27

(.007 – .011)

TYP

0.127 ± 0.076

(.005 ± .003)

0.86

(.034)

REF

0.50

(.0197)

BSC

12345

4.90 ± 0.152

(.193 ± .006)

0.497 ± 0.076

(.0196 ± .003)

REF

8910

3.00 ± 0.102

(.118 ± .004)

(NOTE 3)

3.00 ± 0.102

(.118 ± .004)

(NOTE 4)

NOTE:

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

0.254

(.010) 0° – 6° TYP

DETAIL “A”

GAUGE PLANE

5.23

(.206)

MIN

3.20 – 3.45

(.126 – .136)

0.889 ± 0.127

(.035 ± .005)

RECOMMENDED SOLDER PAD LAYOUT

0.305 ± 0.038

(.0120 ± .0015)

TYP

2.083 ± 0.102

(.082 ± .004)

2.794 ± 0.102

(.110 ± .004)

0.50

(.0197)

BSC

BOTTOM VIEW OF

EXPOSED PAD OPTION

1.83 ± 0.102

(.072 ± .004)

2.06 ± 0.102

(.081 ± .004)

LTC3725

3725fa

PART NUMBER DESCRIPTION COMMENTS

LTC1693 High Speed Single/Dual N-Channel MOSFET Drivers CMOS Compatible Input, V

Range: 4.5V to 12V

LTC1698 Secondary Synchronous Rectifier Controller Use with the LT1681, Optocoupler Driver, Pulse Transformer

Synchronization

LT1950 Single Switch Controller Used for 20W to 500W Forward Converters

LTC3705 2-Switch Forward Controller and Gate Driver 2-Switch Version of LTC3725

LTC3706 Polyphase Secondary-Side Synchronous Fast Transient Response, Self-Starting Architecture, Current Mode Control

Forward Controller

LT3710 Secondary-Side Synchronous Post Regulator For Regulated Auxiliary Output in Isolated DC/DC Converters

LTC3726 Secondary-Side Synchronous Forward Controller Similar to the LTC3706

LT3781 “Bootstrap” Start Dual Transistor Synchronous 72V Operation, Synchronous Switch Output

Forward Controller

LT3804 Secondary Side Dual Output Controller Regulates Two Secondary Outputs, Optocoupler Feedback Driver

with Opto Driver and Second Output Synchronous Driver Controller

LTC3901 Secondary-Side Synchronous Driver for Similar Function to LTC3900, Used in Full-Bridge and Push-Pull Converter

Push-Pull and Full-Bridge Converter

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900

●

FAX: (408) 434-0507

●

www.linear.com

LT 1006 REV A • PRINTED IN USA

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