PRELIMINARY CY7C1018DV33 1-Mbit (128K x 8) Static RAM Functional Description[1] Features * Pin- and function-compatible with CY7C1018CV33 * High speed -- tAA = 8 ns * Low Active Power -- Icc = 75 mA @ 8 ns * Low CMOS Standby Power The CY7C1018DV33 is a high-performance CMOS static RAM organized as 131,072 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and tri-state drivers. This device has an automatic power-down feature that significantly reduces power consumption when deselected. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A16). -- Isb2 = 3 mA * CMOS for optimum speed/power * Center power/ground pinout * Data retention at 2.0V * Automatic power-down when deselected * Easy memory expansion with CE and OE options * Available in Pb-Free 300-mil-wide 32-pin SOJ Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1018DV33 is available in a standard Pb-Free 300-mil-wide 32-Lead SOJ. Logic Block Diagram Pin Configurations SOJ Top View A0 A1 A2 A3 I/O0 INPUT BUFFER CE I/O0 I/O1 VCC V SS I/O1 I/O2 512 x 256 x 8 ARRAY SENSE AMPS ROW DECODER A0 A1 A2 A3 A4 A5 A6 A7 A8 I/O3 I/O2 I/O3 WE A4 A5 A6 A7 I/O4 I/O5 CE COLUMN DECODER I/O6 POWER DOWN I/O7 OE A9 A 10 A 11 A 12 A 13 A 14 A 15 A 16 WE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A16 A15 A14 A13 OE I/O7 I/O6 VSS VCC I/O5 I/O4 A12 A11 A10 A9 A8 Selection Guide CY7C1018DV33-8 CY7C1018DV33-10 Unit Maximum Access Time 8 10 ns Maximum Operating Current 75 60 mA Maximum Standby Current 3 3 mA Note: 1. For guidelines on SRAM system designs, please refer to the `System Design Guidelines' Cypress application note, available on the internet at www.cypress.com Cypress Semiconductor Corporation Document #: 38-05465 Rev. *C * 3901 North First Street * San Jose, CA 95134 * 408-943-2600 Revised January 11, 2005 PRELIMINARY Maximum Ratings CY7C1018DV33 Current into Outputs (LOW)......................................... 20 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Static Discharge Voltage........................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current..................................................... > 200 mA Operating Range Range Supply Voltage on VCC to Relative GND[2] ... -0.5V to + 4.6V Commercial DC Voltage Applied to Outputs[2] in High-Z State .......................................-0.5V to VCC + 0.5V Industrial Ambient Temperature VCC 0C to +70C 3.3V 10% -40C to +85C 3.3V 10% DC Input Voltage[2] .................................-0.5V to VCC + 0.5V Electrical Characteristics Over the Operating Range 7C1018DV33 -8 Parameter Description Test Conditions VOH Output HIGH Voltage VCC = Min., IOH = -4.0 mA VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA VIH Input HIGH Voltage VIL Input LOW Voltage[2] IIX Input Load Current GND < VI < VCC IOZ Output Leakage Current GND < VI < VCC, Output Disabled IOS[3] Output Short Circuit Current VCC = Max., VOUT = GND ICC VCC Operating Supply Current ISB1 ISB2 Min. Max. 2.4 7C1018DV33 -10 Min. Max. Unit 2.4 V 0.4 0.4 V V 2.0 VCC + 0.3 2.0 VCC + 0.3 -0.3 0.8 -0.3 0.8 V -1 +1 -1 +1 A -1 +1 -1 +1 A -300 -300 mA VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC 75 60 mA Automatic CE Power-down Current --TTL Inputs Max. VCC, CE > VIH VIN > VIH or VIN < VIL, f = fMAX 10 10 mA Automatic CE Power-down Current --CMOS Inputs Max. VCC, CE > VCC - 0.3V, VIN > VCC - 0.3V, or VIN < 0.3V, f = 0 3 3 mA Capacitance[4] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 3.3V Max. Unit 8 pF 8 pF Thermal Resistance[4] Parameter Description JA Thermal Resistance (Junction to Ambient)[4] JC Thermal Resistance (Junction to Case)[4] Test Conditions Still Air, soldered on a 3 x 4.5 inch, two-layer printed circuit board All-Packages Unit TBD C/W TBD C/W Notes: 2. VIL (min.) = -2.0V and VIH(max) = VCC + 2V for pulse durations of less than 20 ns. 3. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. 4. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05465 Rev. *C Page 2 of 8 PRELIMINARY CY7C1018DV33 AC Test Loads and Waveforms[6] 10 -ns devices: 8-ns devices: Z = 50 50 * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT R2 351 30 pF Equivalent to: THEVENIN EQUIVALENT 167 OUTPUT 1.73V ALL INPUT PULSES 90% (b) High-Z characteristics: R 317 3.3V Commercial 90% OUTPUT 10% 10% GND OUTPUT 30 pF* 1.5V (a) 3.0V R 317 3.3V OUTPUT Rise Time: 1 V/ns (c) R2 351 5 pF Fall Time: 1 V/ns (d) Switching Characteristics Over the Operating Range [7] 7C1018DV33-8 Parameter 7C1018DV33-10 Description Min. Max. Min. Max. Unit tpower[5] VCC(typical) to the first access 100 100 s tRC Read Cycle Time 8 10 ns tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE LOW to Data Valid 8 10 ns tDOE OE LOW to Data Valid 5 5 ns tLZOE OE LOW to Low-Z Read Cycle 8 3 0 High-Z[8, 9] tHZOE OE HIGH to tLZCE CE LOW to Low-Z[9] tHZCE CE HIGH to High-Z[8, 9] tPU[10] tPD[10] CE LOW to Power-up 10 3 0 4 3 0 CE HIGH to Power-down ns 5 3 4 ns ns 5 ns 10 ns 0 8 ns ns ns Write Cycle[11, 12] tWC Write Cycle Time 8 10 ns tSCE CE LOW to Write End 7 8 ns tAW Address Set-up to Write End 7 8 ns tHA Address Hold from Write End 0 0 ns tSA Address Set-up to Write Start 0 0 ns tPWE WE Pulse Width 6 7 ns tSD Data Set-up to Write End 5 5 ns Notes: 5. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed. 6. AC characteristics (except High-Z) for all 8-ns parts are tested using the load conditions shown in Figure (a). All other speeds are tested using the Thevenin load shown in Figure (b). High-Z characteristics are tested for all speeds using the test load shown in Figure (d). 7. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V. 8. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in (d) of AC Test Loads. Transition is measured 200 mV from steady-state voltage. 9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 10. This parameter is guaranteed by design and is not tested. 11. The internal Write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a Write, and the transition of any of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write. 12. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document #: 38-05465 Rev. *C Page 3 of 8 PRELIMINARY CY7C1018DV33 Switching Characteristics Over the Operating Range (continued)[7] 7C1018DV33-8 Parameter Description Min. 7C1018DV33-10 Max. Min. Max. Unit tHD Data Hold from Write End 0 0 ns tLZWE WE HIGH to Low-Z[9] 3 3 ns tHZWE WE LOW to High-Z[8, 9] 4 5 ns Data Retention Characteristics (Over the Operating Range) Parameter Description Conditions VDR VCC for Data Retention ICCDR Data Retention Current Non-L, Com'l / Ind'l tCDR tR[13] Max. Unit 3 mA 1.2 mA 2.0 VCC = VDR = 2.0V, CE > VCC - 0.3V, VIN > VCC - 0.3V or VIN < 0.3V L-Version Only Chip Deselect to Data Retention Time [4] Min. Operation Recovery Time V 0 ns tRC ns Data Retention Waveform DATA RETENTION MODE 4.5V VCC VDR > 2V 4.5V tR tCDR CE Switching Waveforms Read Cycle No. 1[14, 15] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Notes: 13. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 50 s or stable at VCC(min.) > 50 s. 14. Device is continuously selected. OE, CE = VIL. 15. WE is HIGH for Read cycle. Document #: 38-05465 Rev. *C Page 4 of 8 PRELIMINARY CY7C1018DV33 Switching Waveforms (continued) Read Cycle No. 2 (OE Controlled)[15, 16] ADDRESS tRC CE tACE OE tHZOE tDOE DATA OUT tHZCE tLZOE HIGH IMPEDANCE DATA VALID tLZCE VCC SUPPLY CURRENT HIGH IMPEDANCE tPD tPU ICC 50% 50% ISB Write Cycle No. 1 (CE Controlled)[17, 18] tWC ADDRESS tSCE CE tSA tSCE tAW tHA tPWE WE tSD DATA I/O tHD DATA VALID Notes: 16. Address valid prior to or coincident with CE transition LOW. 17. Data I/O is high impedance if OE = VIH. 18. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. Document #: 38-05465 Rev. *C Page 5 of 8 PRELIMINARY CY7C1018DV33 Switching Waveforms (continued) Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[17, 18] tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE OE tSD DATA I/O tHD DATAIN VALID NOTE 19 tHZOE Write Cycle No. 3 (WE Controlled, OE LOW)[12, 18] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE tSD NOTE 19 DATA I/O tHD DATA VALID tLZWE tHZWE Truth Table CE OE WE I/O0-I/O7 Mode Power H X X High-Z Power-down Standby (ISB) X X X High-Z Power-down Standby (ISB) L L H Data Out Read Active (ICC) L X L Data In Write Active (ICC) L H H High-Z Selected, Outputs Disabled Active (ICC) Note: 19. During this period the I/Os are in the output state and input signals should not be applied. Document #: 38-05465 Rev. *C Page 6 of 8 PRELIMINARY CY7C1018DV33 Ordering Information Speed (ns) 8 Package Name Ordering Code Operating Range Package Type CY7C1018DV33-8VXC V32 32-lead 300-mil Molded SOJ (Pb-Free) Commercial CY7C1018DV33-8VXI V32 32-lead 300-mil Molded SOJ (Pb-Free) Industrial 10 CY7C1018DV33-10VXC V32 32-lead 300-mil Molded SOJ (Pb-Free) Commercial 10 CY7C1018DV33-10VXI V32 32-lead 300-mil Molded SOJ (Pb-Free) Industrial Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts. Package Diagram 32-Lead (300-Mil) Molded SOJ V32 PIN 1 I.D DIMENSIONS IN INCHES 0.330 0.292 0.340 0.305 MIN. MAX. LEAD COPLANARITY 0.004 MAX. 0.810 0.830 0.128 * 0.140 0.050 TYP. 0.026 0.032 0.014 * 0.025 MIN. 0.006 0.012 0.260 * 0.275 51-85041-*A 0.020 All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05465 Rev. *C Page 7 of 8 (c) Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. PRELIMINARY CY7C1018DV33 Document History Page Document Title: CY7C1018DV33 1-Mbit (128K x 8) Static RAM (Preliminary) Document Number: 38-05465 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 201560 See ECN SWI Advance Information data sheet for C9 IPP *A 238471 See ECN RKF DC parameters modified as per EROS (Spec # 01-02165) Pb-free Offering in the Ordering Information *B 262950 See ECN RKF Added Data Retention Characteristics table Added Tpower Spec in Switching Characteristics table Shaded Ordering Information *C 307598 See ECN RKF Reduced Speed bins to -8 and -10 ns Document #: 38-05465 Rev. *C Page 8 of 8