EPF10K10A-TQFP100 - Altera Corporation

Altera Corporation 1

FLEX 10K

Embedded Programmable

Logic Device Family

March 2001, ver. 4.1 Data Sheet

A-DS-F10K-04.1

Includes

FLEX 10KA

Features...

■

The industry’s first embedded programmable logic device (PLD)

family, providing System-on-a-Programmable-Chip (SOPC)

integration

– Embedded array for implementing megafunctions, such as

efficient memory and specialized logic functions

– Logic array for general logic functions

■

High density

– 10,000 to 250,000 typical gates (see Tables 1 and 2)

– Up to 40,960 RAM bits; 2,048 bits per embedded array block

(EAB), all of which can be used without reducing logic capacity

■

System-level features

– MultiVolt

I/O interface support

– 5.0-V tolerant input pins in FLEX

10KA devices

– Low power consumption (typical specification less than 0.5 mA

in standby mode for most devices)

– FLEX 10K and FLEX 10KA devices support peripheral

component interconnect Special Interest Group (PCI SIG)

PCI

Local Bus Specification, Revision 2.2

– FLEX 10KA devices include pull-up clamping diode, selectable

on a pin-by-pin basis for 3.3-V PCI compliance

– Select FLEX 10KA devices support 5.0-V PCI buses with eight or

fewer loads

– Built-in Joint Test Action Group (JTAG) boundary-scan test

(BST) circuitry compliant with IEEE Std. 1149.1-1990, available

without consuming any device logic

Table 1. FLEX 10K Device Features

Feature EPF10K10

EPF10K10A EPF10K20 EPF10K30

EPF10K30A EPF10K40 EPF10K50

EPF10K50V

Typical gates (logic and RAM)

(1)

10,000 20,000 30,000 40,000 50,000

Maximum system gates 31,000 63,000 69,000 93,000 116,000

Logic elements (LEs) 576 1,152 1,728 2,304 2,880

Logic array blocks (LABs) 72 144 216 288 360

Embedded array blocks (EABs) 366810

Total RAM bits 6,144 12,288 12,288 16,384 20,480

Maximum user I/O pins 150 189 246 189 310

2 Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Note to tables:

(1) The embedded IEEE Std. 1149.1 JTAG circuitry adds up to 31,250 gates in addition to the listed typical or maximum

system gates.

...and More

Features

– Devices are fabricated on advanced processes and operate with

a 3.3-V or 5.0-V supply voltage (see Table 3

– In-circuit reconfigurability (ICR) via external configuration

device, intelligent controller, or JTAG port

– ClockLock

and ClockBoost

options for reduced clock

delay/skew and clock multiplication

– Built-in low-skew clock distribution trees

– 100

functional testing of all devices; test vectors or scan chains

are not required

Table 2. FLEX 10K Device Features

Feature EPF10K70 EPF10K100

EPF10K100A EPF10K130V EPF10K250A

Typical gates (logic and

RAM)

(1)

70,000 100,000 130,000 250,000

Maximum system gates 118,000 158,000 211,000 310,000

LEs 3,744 4,992 6,656 12,160

LABs 468 624 832 1,520

EABs 9 12 16 20

Total RAM bits 18,432 24,576 32,768 40,960

Maximum user I/O pins 358 406 470 470

Table 3. Supply Voltages for FLEX 10K & FLEX 10KA Devices

5.0-V Devices 3.3-V Devices

EPF10K10

EPF10K20

EPF10K30

EPF10K40

EPF10K50

EPF10K70

EPF10K100

EPF10K10A

EPF10K30A

EPF10K50V

EPF10K100A

EPF10K130V

EPF10K250A

Altera Corporation 3

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

■

Flexible interconnect

– FastTrack

Interconnect continuous routing structure for fast,

predictable interconnect delays

– Dedicated carry chain that implements arithmetic functions such

as fast adders, counters, and comparators (automatically used by

software tools and megafunctions)

– Dedicated cascade chain that implements high-speed,

high-fan-in logic functions (automatically used by software tools

and megafunctions)

– Tri-state emulation that implements internal tri-state buses

– Up to six global clock signals and four global clear signals

■

Powerful I/O pins

– Individual tri-state output enable control for each pin

– Open-drain option on each I/O pin

– Programmable output slew-rate control to reduce switching

noise

– FLEX 10KA devices support hot-socketing

■

Peripheral register for fast setup and clock-to-output delay

■

Flexible package options

– Available in a variety of packages with 84 to 600 pins (see

Tables 4 and 5)

– Pin-compatibility with other FLEX 10K devices in the same

package

– FineLine BGA

packages maximize board space efficiency

■

Software design support and automatic place-and-route provided by

Altera development systems for Windows-based PCs and Sun

SPARCstation, HP 9000 Series 700/800 workstations

■

Additional design entry and simulation support provided by EDIF

2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM),

DesignWare components, Verilog HDL, VHDL, and other interfaces

to popular EDA tools from manufacturers such as Cadence,

Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity,

VeriBest, and Viewlogic

4 Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 4. FLEX 10K Package Options & I/O Pin Count

Note (1)

Device 84-Pin

PLCC 100-Pin

TQFP 144-Pin TQFP 208-Pin

PQFP

RQFP

240-Pin

PQFP

RQFP

EPF10K10 59 102 134

EPF10K10A 66 102 134

EPF10K20 102 147 189

EPF10K30 147 189

EPF10K30A 102 147 189

EPF10K40 147 189

EPF10K50 189

EPF10K50V 189

EPF10K70 189

EPF10K100

EPF10K100A 189

EPF10K130V

EPF10K250A

Table 5. FLEX 10K Package Options & I/O Pin Count (Continued)

Note (1)

Device 503-Pin

PGA 599-Pin

PGA 256-Pin

FineLine BGA 356-Pin

BGA 484-Pin

FineLine BGA 600-Pin

BGA 403-Pin

PGA

EPF10K10

EPF10K10A 150 150

(2)

EPF10K20

EPF10K30 246

EPF10K30A 191 246 246

EPF10K40

EPF10K50 274 310

EPF10K50V 274

EPF10K70 358

EPF10K100 406

EPF10K100A 274 369 406

EPF10K130V 470 470

EPF10K250A 470 470

Altera Corporation 5

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Notes to tables:

(1) FLEX 10K and FLEX 10KA device package types include plastic J-lead chip carrier (PLCC), thin quad flat pack

(TQFP), plastic quad flat pack (PQFP), power quad flat pack (RQFP), ball-grid array (BGA), pin-grid array (PGA),

and FineLine BGA

packages.

(2) This option is supported with a 256-pin FineLine BGA package. By using SameFrame pin migration, all FineLine

BGA packages are pin compatible. For example, a board can be designed to support both 256-pin and 484-pin

FineLine BGA packages. The Altera software automatically avoids conflicting pins when future migration is set.

General

Description

Altera’s FLEX 10K devices are the industry’s first embedded PLDs. Based

on reconfigurable CMOS SRAM elements, the Flexible Logic Element

MatriX (FLEX) architecture incorporates all features necessary to

implement common gate array megafunctions. With up to 250,000 gates,

the FLEX 10K family provides the density, speed, and features to integrate

entire systems, including multiple 32-bit buses, into a single device.

FLEX 10K devices are reconfigurable, which allows 100

testing prior to

shipment. As a result, the designer is not required to generate test vectors

for fault coverage purposes. Additionally, the designer does not need to

manage inventories of different ASIC designs; FLEX 10K devices can be

configured on the board for the specific functionality required.

Table 6 shows FLEX 10K performance for some common designs. All

performance values were obtained with Synopsys DesignWare or LPM

functions. No special design technique was required to implement the

applications; the designer simply inferred or instantiated a function in a

Verilog HDL, VHDL, Altera Hardware Description Language (AHDL), or

schematic design file.

Notes:

(1) The speed grade of this application is limited because of clock high and low specifications.

(2) This application uses combinatorial inputs and outputs.

(3) This application uses registered inputs and outputs.

Table 6. FLEX 10K & FLEX 10KA Performance

Application Resources

Used Performance Units

LEs EABs -1 Speed

Grade -2 Speed

Grade -3 Speed

Grade -4 Speed

Grade

16-bit loadable

counter

(1)

16 0 204 166 125 95 MHz

16-bit accumulator

(1)

16 0 204 166 125 95 MHz

16-to-1 multiplexer

(2)

10 0 4.2 5.8 6.0 7.0 ns

256

8 RAM read

cycle speed

(3)

0 1 172 145 108 84 MHz

256

8 RAM write

cycle speed

(3)

0 1 106 89 68 63 MHz

6 Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

The FLEX 10K architecture is similar to that of embedded gate arrays, the

fastest-growing segment of the gate array market. As with standard gate

arrays, embedded gate arrays implement general logic in a conventional

“sea-of-gates” architecture. In addition, embedded gate arrays have

dedicated die areas for implementing large, specialized functions. By

embedding functions in silicon, embedded gate arrays provide reduced

die area and increased speed compared to standard gate arrays. However,

embedded megafunctions typically cannot be customized, limiting the

designer’s options. In contrast, FLEX 10K devices are programmable,

providing the designer with full control over embedded megafunctions

and general logic while facilitating iterative design changes during

debugging.

Each FLEX 10K device contains an embedded array and a logic array. The

embedded array is used to implement a variety of memory functions or

complex logic functions, such as digital signal processing (DSP),

microcontroller, wide-data-path manipulation, and data-transformation

functions. The logic array performs the same function as the sea-of-gates

in the gate array: it is used to implement general logic, such as counters,

adders, state machines, and multiplexers. The combination of embedded

and logic arrays provides the high performance and high density of

embedded gate arrays, enabling designers to implement an entire system

on a single device.

FLEX 10K devices are configured at system power-up with data stored in

an Altera serial configuration device or provided by a system controller.

Altera offers the EPC1, EPC2, EPC16, and EPC1441 configuration devices,

which configure FLEX 10K devices via a serial data stream. Configuration

data can also be downloaded from system RAM or from Altera’s

BitBlaster

serial download cable or ByteBlasterMV

parallel port

download cable. After a FLEX 10K device has been configured, it can be

reconfigured in-circuit by resetting the device and loading new data.

Because reconfiguration requires less than 320 ms, real-time changes can

be made during system operation.

FLEX 10K devices contain an optimized interface that permits

microprocessors to configure FLEX 10K devices serially or in parallel, and

synchronously or asynchronously. The interface also enables

microprocessors to treat a FLEX 10K device as memory and configure the

device by writing to a virtual memory location, making it very easy for the

designer to reconfigure the device.

Altera Corporation 7

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

For more information, see the following documents:

■

Configuration Devices for APEX & FLEX Devices Data Sheet

■

BitBlaster Serial Download Cable Data Sheet

■

ByteBlasterMV Parallel Port Download Cable Data Sheet

■

Application Note 116 (Configuring APEX 20K, FLEX 10K & FLEX 6000

Devices)

FLEX 10K devices are supported by Altera development systems; single,

integrated packages that offer schematic, text (including AHDL), and

waveform design entry, compilation and logic synthesis, full simulation

and worst-case timing analysis, and device configuration. The Altera

software provides EDIF 2 0 0 and 3 0 0, LPM, VHDL, Verilog HDL, and

other interfaces for additional design entry and simulation support from

other industry-standard PC- and UNIX workstation-based EDA tools.

The Altera software works easily with common gate array EDA tools for

synthesis and simulation. For example, the Altera software can generate

Verilog HDL files for simulation with tools such as Cadence Verilog-XL.

Additionally, the Altera software contains EDA libraries that use device-

specific features such as carry chains which are used for fast counter and

arithmetic functions. For instance, the Synopsys Design Compiler library

supplied with the Altera development systems include DesignWare

functions that are optimized for the FLEX 10K architecture.

The Altera development systems run on Windows-based PCs and Sun

SPARCstation, and HP 9000 Series 700/800 workstations.

See the

MAX+PLUS II Programmable Logic Development System & Software

Data Sheet

for more information.

Functional

Description

Each FLEX 10K device contains an embedded array to implement

memory and specialized logic functions, and a logic array to implement

general logic.

The embedded array consists of a series of EABs. When implementing

memory functions, each EAB provides 2,048 bits, which can be used to

create RAM, ROM, dual-port RAM, or first-in first-out (FIFO) functions.

When implementing logic, each EAB can contribute 100 to 600 gates

towards complex logic functions, such as multipliers, microcontrollers,

state machines, and DSP functions. EABs can be used independently, or

multiple EABs can be combined to implement larger functions.

8 Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

The logic array consists of logic array blocks (LABs). Each LAB contains

eight LEs and a local interconnect. An LE consists of a 4-input look-up

table (LUT), a programmable flipflop, and dedicated signal paths for carry

and cascade functions. The eight LEs can be used to create medium-sized

blocks of logic—8-bit counters, address decoders, or state machines—or

combined across LABs to create larger logic blocks. Each LAB represents

about 96 usable gates of logic.

Signal interconnections within FLEX 10K devices and to and from device

pins are provided by the FastTrack Interconnect, a series of fast,

continuous row and column channels that run the entire length and width

of the device.

Each I/O pin is fed by an I/O element (IOE) located at the end of each row

and column of the FastTrack Interconnect. Each IOE contains a

bidirectional I/O buffer and a flipflop that can be used as either an output

or input register to feed input, output, or bidirectional signals. When used

with a dedicated clock pin, these registers provide exceptional

performance. As inputs, they provide setup times as low as 1.6 ns and

hold times of 0 ns; as outputs, these registers provide clock-to-output

times as low as 5.3 ns. IOEs provide a variety of features, such as JTAG

BST support, slew-rate control, tri-state buffers, and open-drain outputs.

Figure 1 shows a block diagram of the FLEX 10K architecture. Each group

of LEs is combined into an LAB; LABs are arranged into rows and

columns. Each row also contains a single EAB. The LABs and EABs are

interconnected by the FastTrack Interconnect. IOEs are located at the end

of each row and column of the FastTrack Interconnect.

Altera Corporation 9

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Figure 1. FLEX 10K Device Block Diagram

FLEX 10K devices provide six dedicated inputs that drive the flipflops’

control inputs to ensure the efficient distribution of high-speed, low-skew

(less than 1.5 ns) control signals. These signals use dedicated routing

channels that provide shorter delays and lower skews than the FastTrack

Interconnect. Four of the dedicated inputs drive four global signals. These

four global signals can also be driven by internal logic, providing an ideal

solution for a clock divider or an internally generated asynchronous clear

signal that clears many registers in the device.

Embedded Array Block

The EAB is a flexible block of RAM with registers on the input and output

ports, and is used to implement common gate array megafunctions. The

EAB is also suitable for functions such as multipliers, vector scalars, and

error correction circuits, because it is large and flexible. These functions

can be combined in applications such as digital filters and

microcontrollers.

I/O Element

(IOE)

Logic Array

Block (LAB)

Row

Interconnect

IOEIOE

IOE

Local Interconnect

IOEIOE

IOEIOE IOEIOE

IOEIOE

Logic Element (LE)

Column

Interconnect

IOE

EAB

Logic

Array

IOEIOE

IOEIOE IOEIOE

Embedded Array Block (EAB)

Embedded Array

IOE

Logic Array

IOE

10 Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Logic functions are implemented by programming the EAB with a read-

only pattern during configuration, creating a large LUT. With LUTs,

combinatorial functions are implemented by looking up the results, rather

than by computing them. This implementation of combinatorial functions

can be faster than using algorithms implemented in general logic, a

performance advantage that is further enhanced by the fast access times

of EABs. The large capacity of EABs enables designers to implement

complex functions in one logic level without the routing delays associated

with linked LEs or field-programmable gate array (FPGA) RAM blocks.

For example, a single EAB can implement a 4

4 multiplier with eight

inputs and eight outputs. Parameterized functions such as LPM functions

can automatically take advantage of the EAB.

The EAB provides advantages over FPGAs, which implement on-board

RAM as arrays of small, distributed RAM blocks. These FPGA RAM

blocks contain delays that are less predictable as the size of the RAM

increases. In addition, FPGA RAM blocks are prone to routing problems

because small blocks of RAM must be connected together to make larger

blocks. In contrast, EABs can be used to implement large, dedicated

blocks of RAM that eliminate these timing and routing concerns.

EABs can be used to implement synchronous RAM, which is easier to use

than asynchronous RAM. A circuit using asynchronous RAM must

generate the RAM write enable (

) signal, while ensuring that its data

and address signals meet setup and hold time specifications relative to the

signal. In contrast, the EAB’s synchronous RAM generates its own

signal and is self-timed with respect to the global clock. A circuit using the

EAB’s self-timed RAM need only meet the setup and hold time

specifications of the global clock.

When used as RAM, each EAB can be configured in any of the following

sizes: 256

8, 512

4, 1,024

2, or 2,048

1. See Figure 2.

Figure 2. EAB Memory Conﬁgurations

256 × 8 512 × 4 1,024 × 2 2,048 × 1

Altera Corporation 11

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Larger blocks of RAM are created by combining multiple EABs. For

example, two 256

8 RAM blocks can be combined to form a

256

16 RAM block; two 512

4 blocks of RAM can be combined to form

a 512

8 RAM block. See Figure 3.

Figure 3. Examples of Combining EABs

If necessary, all EABs in a device can be cascaded to form a single RAM

block. EABs can be cascaded to form RAM blocks of up to 2,048 words

without impacting timing. Altera’s software automatically combines

EABs to meet a designer’s RAM specifications.

EABs provide flexible options for driving and controlling clock signals.

Different clocks can be used for the EAB inputs and outputs. Registers can

be independently inserted on the data input, EAB output, or the address

and

inputs. The global signals and the EAB local interconnect can drive

the

signal. The global signals, dedicated clock pins, and EAB local

interconnect can drive the EAB clock signals. Because the LEs drive the

EAB local interconnect, the LEs can control the

signal or the EAB clock

signals.

Each EAB is fed by a row interconnect and can drive out to row and

column interconnects. Each EAB output can drive up to two row channels

and up to two column channels; the unused row channel can be driven by

other LEs. This feature increases the routing resources available for EAB

outputs. See Figure 4.

512 × 4

256 × 8

256 × 16 512 × 8

12 Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Figure 4. FLEX 10K Embedded Array Block

Note:

(1) EPF10K10, EPF10K10A, EPF10K20, EPF10K30, EPF10K30A, EPF10K40, EPF10K50, and EPF10K50V devices have

22 EAB local interconnect channels; EPF10K70, EPF10K100, EPF10K100A, EPF10K130V, and EPF10K250A devices

have 26.

Column

Interconnect

Row Interconnect

RAM/ROM

256 × 8

512 × 4

1,024 × 2

2,048 × 1

Address

Data

8, 4, 2, 1

EAB Local Interconnect (1)

Dedicated Inputs &

Global Signals

(1)

Data

Out

Chip-Wide

Reset

8, 9, 10, 11

2, 4, 8, 16

Altera Corporation 13

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Logic Array Block

Each LAB consists of eight LEs, their associated carry and cascade chains,

LAB control signals, and the LAB local interconnect. The LAB provides

the coarse-grained structure to the FLEX 10K architecture, facilitating

efficient routing with optimum device utilization and high performance.

See Figure 5.

Figure 5. FLEX 10K LAB

Notes:

(1) EPF10K10, EPF10K10A, EPF10K20, EPF10K30, EPF10K30A, EPF10K40, EPF10K50, and EPF10K50V devices have

22 inputs to the LAB local interconnect channel from the row; EPF10K70, EPF10K100, EPF10K100A, EPF10K130V,

and EPF10K250A devices have 26.

(2) EPF10K10, EPF10K10A, EPF10K20, EPF10K30, EPF10K30A, EPF10K40, EPF10K50, and EPF10K50V devices have

30 LAB local interconnect channels; EPF10K70, EPF10K100, EPF10K100A, EPF10K130V, and EPF10K250A devices

have 34 LABs.

Carry-In &

Cascade-In

LE1

LE8

LE2

LE3

LE4

LE5

LE6

LE7

Column

Interconnect

Row Interconnect

(1)

LAB Local

Interconnect (2)

Column-to-Row

Interconnect

Carry-Out &

Cascade-Out

LAB Control

Signals

See Figure 11

for details.

Dedicated Inputs &

Global Signals

428

14 Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Each LAB provides four control signals with programmable inversion

that can be used in all eight LEs. Two of these signals can be used as

clocks; the other two can be used for clear/preset control. The LAB clocks

can be driven by the dedicated clock input pins, global signals, I/O

signals, or internal signals via the LAB local interconnect. The LAB preset

and clear control signals can be driven by the global signals, I/O signals,

or internal signals via the LAB local interconnect. The global control

signals are typically used for global clock, clear, or preset signals because

they provide asynchronous control with very low skew across the device.

If logic is required on a control signal, it can be generated in one or more

LEs in any LAB and driven into the local interconnect of the target LAB.

In addition, the global control signals can be generated from LE outputs.

Logic Element

The LE, the smallest unit of logic in the FLEX 10K architecture, has a

compact size that provides efficient logic utilization. Each LE contains a

four-input LUT, which is a function generator that can quickly compute

any function of four variables. In addition, each LE contains a

programmable flipflop with a synchronous enable, a carry chain, and a

cascade chain. Each LE drives both the local and the FastTrack

Interconnect. See Figure 6.

Figure 6. FLEX 10K Logic Element

To LAB Local

Interconnect

Carry-In

Clock

Select

Carry-Out

Look-Up

Table

(LUT)

Clear/

Preset

Logic

Carry

Chain

Cascade

Chain

Cascade-In

Cascade-Out

To FastTrack

Interconnect

Programmable

PRN

CLRN

ENA

Chip-Wide

Reset

data1

data2

data3

data4

labctrl1

labctrl2

labctrl3

labctrl4

Altera Corporation 15

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

The programmable flipflop in the LE can be configured for D, T, JK, or SR

operation. The clock, clear, and preset control signals on the flipflop can

be driven by global signals, general-purpose I/O pins, or any internal

logic. For combinatorial functions, the flipflop is bypassed and the output

of the LUT drives the output of the LE.

The LE has two outputs that drive the interconnect; one drives the local

interconnect and the other drives either the row or column FastTrack

Interconnect. The two outputs can be controlled independently. For

example, the LUT can drive one output while the register drives the other

output. This feature, called register packing, can improve LE utilization

because the register and the LUT can be used for unrelated functions.

The FLEX 10K architecture provides two types of dedicated high-speed

data paths that connect adjacent LEs without using local interconnect

paths: carry chains and cascade chains. The carry chain supports high-

speed counters and adders; the cascade chain implements wide-input

functions with minimum delay. Carry and cascade chains connect all LEs

in an LAB and all LABs in the same row. Intensive use of carry and

cascade chains can reduce routing flexibility. Therefore, the use of these

chains should be limited to speed-critical portions of a design.

Carry Chain

The carry chain provides a very fast (as low as 0.2 ns) carry-forward

function between LEs. The carry-in signal from a lower-order bit drives

forward into the higher-order bit via the carry chain, and feeds into both

the LUT and the next portion of the carry chain. This feature allows the

FLEX 10K architecture to implement high-speed counters, adders, and

comparators of arbitrary width efficiently. Carry chain logic can be

created automatically by the Compiler during design processing, or

manually by the designer during design entry. Parameterized functions

such as LPM and DesignWare functions automatically take advantage of

carry chains.

Carry chains longer than eight LEs are automatically implemented by

linking LABs together. For enhanced fitting, a long carry chain skips

alternate LABs in a row. A carry chain longer than one LAB skips either

from even-numbered LAB to even-numbered LAB, or from odd-

numbered LAB to odd-numbered LAB. For example, the last LE of the

first LAB in a row carries to the first LE of the third LAB in the row. The

carry chain does not cross the EAB at the middle of the row. For instance,

in the EPF10K50 device, the carry chain stops at the eighteenth LAB and a

new one begins at the nineteenth LAB.

16 Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Figure 7 shows how an

-bit full adder can be implemented in

+ 1 LEs

with the carry chain. One portion of the LUT generates the sum of two bits

using the input signals and the carry-in signal; the sum is routed to the

output of the LE. The register can either be bypassed for simple adders or

be used for an accumulator function. The carry chain logic generates the

carry-out signal, which is routed directly to the carry-in signal of the next-

higher-order bit. The final carry-out signal is routed to an LE, where it can

be used as a general-purpose signal.

Figure 7. Carry Chain Operation (n-bit Full Adder)

LUT

Carry Chain

LE1

Carry Chain

LE2

Carry Chain

LEn

Carry Chain

Carry-Out

LEn + 1

Carry-In

LUT

Altera Corporation 17

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Cascade Chain

With the cascade chain, the FLEX 10K architecture can implement

functions that have a very wide fan-in. Adjacent LUTs can be used to

compute portions of the function in parallel; the cascade chain serially

connects the intermediate values. The cascade chain can use a logical

AND

or logical

(via De Morgan’s inversion) to connect the outputs of

adjacent LEs. Each additional LE provides four more inputs to the

effective width of a function, with a delay as low as 0.7 ns per LE. Cascade

chain logic can be created automatically by the Compiler during design

processing, or manually by the designer during design entry.

Cascade chains longer than eight bits are implemented automatically by

linking several LABs together. For easier routing, a long cascade chain

skips every other LAB in a row. A cascade chain longer than one LAB

skips either from even-numbered LAB to even-numbered LAB, or from

odd-numbered LAB to odd-numbered LAB (e.g., the last LE of the first

LAB in a row cascades to the first LE of the third LAB). The cascade chain

does not cross the center of the row (e.g., in the EPF10K50 device, the

cascade chain stops at the eighteenth LAB and a new one begins at the

nineteenth LAB). This break is due to the EAB’s placement in the middle

of the row.

Figure 8 shows how the cascade function can connect adjacent LEs to form

functions with a wide fan-in. These examples show functions of 4

variables implemented with

LEs. The LE delay is as low as 1.6 ns; the

cascade chain delay is as low as 0.7 ns. With the cascade chain, 3.7 ns is

needed to decode a 16-bit address.

Figure 8. Cascade Chain Operation

LE1

LUT

LE2

LUT

d[3..0]

d[7..4]

d[(4

-1)..(4

-4)]

d[3..0]

d[7..4]

d[(4

-1)..(4

-4)]

LE1

LE2

LUT

AND Cascade Chain OR Cascade Chain

18 Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

LE Operating Modes

The FLEX 10K LE can operate in the following four modes:

■Normal mode

■Arithmetic mode

■Up/down counter mode

■Clearable counter mode

Each of these modes uses LE resources differently. In each mode, seven

available inputs to the LE—the four data inputs from the LAB local

interconnect, the feedback from the programmable register, and the

carry-in and cascade-in from the previous LE—are directed to different

destinations to implement the desired logic function. Three inputs to the

LE provide clock, clear, and preset control for the register. The Altera

software, in conjunction with parameterized functions such as LPM and

DesignWare functions, automatically chooses the appropriate mode for

common functions such as counters, adders, and multipliers. If required,

the designer can also create special-purpose functions which use a specific

LE operating mode for optimal performance.

The architecture provides a synchronous clock enable to the register in all

four modes. The Altera software can set DATA1 to enable the register

synchronously, providing easy implementation of fully synchronous

designs.

Figure 9 shows the LE operating modes.

Altera Corporation 19

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Figure 9. FLEX 10K LE Operating Modes

Note:

(1) Packed registers cannot be used with the cascade chain.

ENA

PRN

CLRN

4-Input

LUT

Carry-In

Cascade-Out

Cascade-In

(1)

LE-Out to FastTrack

Interconnect

LE-Out to Local

Interconnect

ENA

Normal Mode

PRN

CLRN

Cascade-Out

LE-Out

Cascade-In

3-Input

LUT

Carry-In

3-Input

LUT

Carry-Out

Arithmetic Mode

Up/Down Counter Mode

data1 (ena)

data2 (u/d)

PRN

CLRN

3-Input

LUT

Carry-In Cascade-In

LE-Out

3-Input

LUT

Carry-Out

data3 (data)

data4 (nload)

Cascade-Out

Clearable Counter Mode

data1 (ena)

data2 (nclr) PRN

CLRN

3-Input

LUT

Carry-In

LE-Out

3-Input

LUT

Carry-Out

data3 (data)

data4 (nload)

Cascade-Out

ENA

data1

data2

data3

data4

data1

data2

20 Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Normal Mode

The normal mode is suitable for general logic applications and wide

decoding functions that can take advantage of a cascade chain. In normal

mode, four data inputs from the LAB local interconnect and the carry-in

are inputs to a four-input LUT. The Compiler automatically selects the

carry-in or the DATA3 signal as one of the inputs to the LUT. The LUT

output can be combined with the cascade-in signal to form a cascade chain

through the cascade-out signal. Either the register or the LUT can be used

to drive both the local interconnect and the FastTrack Interconnect at the

same time.

The LUT and the register in the LE can be used independently; this feature

is known as register packing. To support register packing, the LE has two

outputs; one drives the local interconnect and the other drives the

FastTrack Interconnect. The DATA4 signal can drive the register directly,

allowing the LUT to compute a function that is independent of the

registered signal; a three-input function can be computed in the LUT, and

a fourth independent signal can be registered. Alternatively, a four-input

function can be generated, and one of the inputs to this function can be

used to drive the register. The register in a packed LE can still use the

clock enable, clear, and preset signals in the LE. In a packed LE, the

local interconnect, or vice versa.

Arithmetic Mode

The arithmetic mode offers 2 three-input LUTs that are ideal for

implementing adders, accumulators, and comparators. One LUT

computes a three-input function, and the other generates a carry output.

As shown in Figure 9 on page 19, the first LUT uses the carry-in signal and

two data inputs from the LAB local interconnect to generate a

combinatorial or registered output. For example, in an adder, this output

is the sum of three signals: a, b, and carry-in. The second LUT uses the

same three signals to generate a carry-out signal, thereby creating a carry

chain. The arithmetic mode also supports simultaneous use of the cascade

chain.

Altera Corporation 21

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Up/Down Counter Mode

The up/down counter mode offers counter enable, clock enable,

synchronous up/down control, and data loading options. These control

signals are generated by the data inputs from the LAB local interconnect,

the carry-in signal, and output feedback from the programmable register.

The Up/down counter mode uses 2 three-input LUTs: one generates the

counter data, and the other generates the fast carry bit. A 2-to-1

multiplexer provides synchronous loading. Data can also be loaded

asynchronously with the clear and preset register control signals, without

using the LUT resources.

Clearable Counter Mode

The clearable counter mode is similar to the up/down counter mode, but

supports a synchronous clear instead of the up/down control. The clear

function is substituted for the cascade-in signal in the up/down counter

mode. Clearable counter mode uses 2 three-input LUTs: one generates the

counter data, and the other generates the fast carry bit. Synchronous

loading is provided by a 2-to-1 multiplexer. The output of this multiplexer

is ANDed with a synchronous clear signal.

Internal Tri-State Emulation

Internal tri-state emulation provides internal tri-stating without the

limitations of a physical tri-state bus. In a physical tri-state bus, the

tri-state buffers’ output enable (OE) signals select which signal drives the

bus. However, if multiple OE signals are active, contending signals can be

driven onto the bus. Conversely, if no OE signals are active, the bus will

float. Internal tri-state emulation resolves contending tri-state buffers to a

low value and floating buses to a high value, thereby eliminating these

problems. The Altera software automatically implements tri-state bus

functionality with a multiplexer.

Clear & Preset Logic Control

Logic for the programmable register’s clear and preset functions is

controlled by the DATA3, LABCTRL1, and LABCTRL2 inputs to the LE. The

clear and preset control structure of the LE asynchronously loads signals

into a register. Either LABCTRL1 or LABCTRL2 can control the

asynchronous clear. Alternatively, the register can be set up so that

LABCTRL1 implements an asynchronous load. The data to be loaded is

driven to DATA3; when LABCTRL1 is asserted, DATA3 is loaded into the

22 Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

During compilation, the Compiler automatically selects the best control

signal implementation. Because the clear and preset functions are active-

low, the Compiler automatically assigns a logic high to an unused clear or

preset.

The clear and preset logic is implemented in one of the following six

modes chosen during design entry:

■Asynchronous clear

■Asynchronous preset

■Asynchronous clear and preset

■Asynchronous load with clear

■Asynchronous load with preset

■Asynchronous load without clear or preset

In addition to the six clear and preset modes, FLEX 10K devices provide a

chip-wide reset pin that can reset all registers in the device. Use of this

feature is set during design entry. In any of the clear and preset modes, the

chip-wide reset overrides all other signals. Registers with asynchronous

presets may be preset when the chip-wide reset is asserted. Inversion can

be used to implement the asynchronous preset. Figure 10 shows examples

of how to enter a section of a design for the desired functionality.

Altera Corporation 23

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Figure 10. LE Clear & Preset Modes

Asynchronous Clear

The flipflop can be cleared by either LABCTRL1 or LABCTRL2. In this mode,

the preset signal is tied to VCC to deactivate it.

Asynchronous Clear Asynchronous Preset Asynchronous Clear & Preset

Asynchronous Load without Clear or Preset

PRN

CLRN

NOT

Asynchronous Load with Clear

PRN

CLRN

NOT

Asynchronous Load with Preset

NOT

PRN

CLRN

PRN

CLRN

VCC

Chip-Wide Reset

PRN

CLRN

PRN

CLRN

VCC

Chip-Wide Reset

labctrl1 or

labctrl2

labctrl1 or

labctrl2

labctrl1

(Asynchronous

Load)

labctrl1

(Asynchronous

Load)

labctrl1

(Asynchronous

Load)

data3

(Data)

labctrl2

(Clear)

labctrl2

(Preset)

data3

(Data)

data3

(Data)

labctrl2

labctrl1

24 Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Asynchronous Preset

An asynchronous preset is implemented as either an asynchronous load,

or with an asynchronous clear. If DATA3 is tied to VCC, asserting LABCTRL1

asynchronously loads a one into the register. Alternatively, the Altera

software can provide preset control by using the clear and inverting the

input and output of the register. Inversion control is available for the

inputs to both LEs and IOEs. Therefore, if a register is preset by only one

of the two LABCTRL signals, the DATA3 input is not needed and can be used

for one of the LE operating modes.

Asynchronous Preset & Clear

When implementing asynchronous clear and preset, LABCTRL1 controls

the preset and LABCTRL2 controls the clear. DATA3 is tied to VCC, therefore,

asserting LABCTRL1 asynchronously loads a one into the register,

effectively presetting the register. Asserting LABCTRL2 clears the register.

Asynchronous Load with Clear

When implementing an asynchronous load in conjunction with the clear,

LABCTRL1 implements the asynchronous load of DATA3 by controlling the

the register clear; LABCTRL2 does not have to feed the preset circuits.

Asynchronous Load with Preset

When implementing an asynchronous load in conjunction with preset, the

Altera software provides preset control by using the clear and inverting

the input and output of the register. Asserting LABCTRL2 presets the

inverts the signal that drives DATA3 to account for the inversion of the

Asynchronous Load without Preset or Clear

When implementing an asynchronous load without preset or clear,

LABCTRL1 implements the asynchronous load of DATA3 by controlling the

FastTrack Interconnect

In the FLEX 10K architecture, connections between LEs and device I/O

pins are provided by the FastTrack Interconnect, which is a series of

continuous horizontal and vertical routing channels that traverse the

device. This global routing structure provides predictable performance,

even in complex designs. In contrast, the segmented routing in FPGAs

requires switch matrices to connect a variable number of routing paths,

increasing the delays between logic resources and reducing performance.

Altera Corporation 25

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

The FastTrack Interconnect consists of row and column interconnect

channels that span the entire device. Each row of LABs is served by a

dedicated row interconnect. The row interconnect can drive I/O pins and

feed other LABs in the device. The column interconnect routes signals

between rows and can drive I/O pins.

A row channel can be driven by an LE or by one of three column channels.

These four signals feed dual 4-to-1 multiplexers that connect to two

specific row channels. These multiplexers, which are connected to each

LE, allow column channels to drive row channels even when all eight LEs

in an LAB drive the row interconnect.

Each column of LABs is served by a dedicated column interconnect. The

column interconnect can then drive I/O pins or another row’s

interconnect to route the signals to other LABs in the device. A signal from

the column interconnect, which can be either the output of an LE or an

input from an I/O pin, must be routed to the row interconnect before it

can enter an LAB or EAB. Each row channel that is driven by an IOE or

EAB can drive one specific column channel.

Access to row and column channels can be switched between LEs in

adjacent pairs of LABs. For example, an LE in one LAB can drive the row

and column channels normally driven by a particular LE in the adjacent

LAB in the same row, and vice versa. This routing flexibility enables

routing resources to be used more efficiently. See Figure 11.

26 Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Figure 11. LAB Connections to Row & Column Interconnect

From Adjacent LAB

Row Channels

Column

Channels

Each LE can drive two

row channels.

LE 2

LE 8

LE 1 To Adjacent LAB

Each LE can switch

interconnect access

with an LE in the

adjacent LAB.

At each intersection,

four row channels can

drive column channels.

To Other Rows

To LAB Local

Interconnect

To Other

Columns

Altera Corporation 27

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

For improved routing, the row interconnect is comprised of a combination

of full-length and half-length channels. The full-length channels connect

to all LABs in a row; the half-length channels connect to the LABs in half

of the row. The EAB can be driven by the half-length channels in the left

half of the row and by the full-length channels. The EAB drives out to the

full-length channels. In addition to providing a predictable, row-wide

interconnect, this architecture provides increased routing resources. Two

neighboring LABs can be connected using a half-row channel, thereby

saving the other half of the channel for the other half of the row.

Table 7 summarizes the FastTrack Interconnect resources available in

each FLEX 10K device.

In addition to general-purpose I/O pins, FLEX 10K devices have six

dedicated input pins that provide low-skew signal distribution across the

device. These six inputs can be used for global clock, clear, preset, and

peripheral output enable and clock enable control signals. These signals

are available as control signals for all LABs and IOEs in the device.

The dedicated inputs can also be used as general-purpose data inputs

because they can feed the local interconnect of each LAB in the device.

However, the use of dedicated inputs as data inputs can introduce

additional delay into the control signal network.

Table 7. FLEX 10K FastTrack Interconnect Resources

Device Rows Channels per

Row Columns Channels per

Column

EPF10K10

EPF10K10A 3 144 24 24

EPF10K20 6 144 24 24

EPF10K30

EPF10K30A 6 216 36 24

EPF10K40 8 216 36 24

EPF10K50

EPF10K50V 10 216 36 24

EPF10K70 9 312 52 24

EPF10K100

EPF10K100A 12 312 52 24

EPF10K130V 16 312 52 32

EPF10K250A 20 456 76 40

28 Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Figure 12 shows the interconnection of adjacent LABs and EABs with

row, column, and local interconnects, as well as the associated cascade

and carry chains. Each LAB is labeled according to its location: a letter

represents the row and a number represents the column. For example,

LAB B3 is in row B, column 3.

Figure 12. Interconnect Resources

I/O Element (IOE)

Row

Interconnect

IOE

Column

Interconnect

LAB

See Figure 15

for details.

See Figure 14

for details.

LAB

IOE

Cascade &

Carry Chains

To LAB B4

To LAB A4

To LAB B5

To LAB A5

IOE IOEIOE IOE

IOE IOE

IOEIOE IOEIOE IOEIOE

IOE

Altera Corporation 29

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

I/O Element

An I/O element (IOE) contains a bidirectional I/O buffer and a register

that can be used either as an input register for external data that requires

a fast setup time, or as an output register for data that requires fast clock-

to-output performance. In some cases, using an LE register for an input

can be used as input, output, or bidirectional pins. For bidirectional

registered I/O implementation, the output register should be in the IOE

and, the data input and output enable register should be LE registers

placed adjacent to the bidirectional pin. The Compiler uses the

programmable inversion option to invert signals from the row and

column interconnect automatically where appropriate. Figure 13 shows

the bidirectional I/O registers.

30 Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Figure 13. Bidirectional I/O Registers

VCC

OE[7..0]

CLK[1..0]

ENA[5..0]

CLRN[1..0]

Peripheral

Control Bus

CLRN

ENA

VCC

2 Dedicated

Clock Inputs

Slew-Rate

Control

Open-Drain

Output

Chip-Wide

Output Enable

CLK[3..2]

212

VCC

Chip-Wide

Reset

4 Dedicated

Inputs

Row and Column

Interconnect

VCC

CLRN

ENA

Chip-Wide

Reset

CLRN

ENA

Chip-Wide

Reset

VCC

Input Register

Output Register

OE Register

Altera Corporation 31

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Each IOE selects the clock, clear, clock enable, and output enable controls

from a network of I/O control signals called the peripheral control bus.

The peripheral control bus uses high-speed drivers to minimize signal

skew across devices; it provides up to 12 peripheral control signals that

can be allocated as follows:

■Up to eight output enable signals

■Up to six clock enable signals

■Up to two clock signals

■Up to two clear signals

If more than six clock enable or eight output enable signals are required,

each IOE on the device can be controlled by clock enable and output

enable signals driven by specific LEs. In addition to the two clock signals

available on the peripheral control bus, each IOE can use one of two

dedicated clock pins. Each peripheral control signal can be driven by any

of the dedicated input pins or the first LE of each LAB in a particular row.

In addition, an LE in a different row can drive a column interconnect,

which causes a row interconnect to drive the peripheral control signal.

The chip-wide reset signal will reset all IOE registers, overriding any

other control signals.

Tables 8 and 9 list the sources for each peripheral control signal, and the

rows that can drive global signals. These tables also show how the output

enable, clock enable, clock, and clear signals share 12 peripheral control

signals.

32 Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 8. EPF10K10, EPF10K20, EPF10K30, EPF10K40 & EPF10K50 Peripheral Bus Sources

Peripheral

Control Signal EPF10K10

EPF10K10A EPF10K20 EPF10K30

EPF10K30A EPF10K40 EPF10K50

EPF10K50V

OE0 Row A Row A Row A Row A Row A

OE1 Row A Row B Row B Row C Row B

OE2 Row B Row C Row C Row D Row D

OE3 Row B Row D Row D Row E Row F

OE4 Row C Row E Row E Row F Row H

OE5 Row C Row F Row F Row G Row J

CLKENA0/CLK0/GLOBAL0 Row A Row A Row A Row B Row A

CLKENA1/OE6/GLOBAL1 Row A Row B Row B Row C Row C

CLKENA2/CLR0 Row B Row C Row C Row D Row E

CLKENA3/OE7/GLOBAL2 Row B Row D Row D Row E Row G

CLKENA4/CLR1 Row C Row E Row E Row F Row I

CLKENA5/CLK1/GLOBAL3 Row C Row F Row F Row H Row J

Table 9. EPF10K70, EPF10K100, EPF10K130V & EPF10K250A Peripheral Bus Sources

Peripheral

Control Signal EPF10K70 EPF10K100

EPF10K100A EPF10K130V EPF10K250A

OE0 Row A Row A Row C Row E

OE1 Row B Row C Row E Row G

OE2 Row D Row E Row G Row I

OE3 Row I Row L Row N Row P

OE4 Row G Row I Row K Row M

OE5 Row H Row K Row M Row O

CLKENA0/CLK0/GLOBAL0 Row E Row F Row H Row J

CLKENA1/OE6/GLOBAL1 Row C Row D Row F Row H

CLKENA2/CLR0 Row B Row B Row D Row F

CLKENA3/OE7/GLOBAL2 Row F Row H Row J Row L

CLKENA4/CLR1 Row H Row J Row L Row N

CLKENA5/CLK1/GLOBAL3 Row E Row G Row I Row K

Altera Corporation 33

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Signals on the peripheral control bus can also drive the four global signals,

referred to as GLOBAL0 through GLOBAL3 in Tables 8 and 9. The internally

generated signal can drive the global signal, providing the same

low-skew, low-delay characteristics for an internally generated signal as

for a signal driven by an input. This feature is ideal for internally

generated clear or clock signals with high fan-out. When a global signal is

driven by internal logic, the dedicated input pin that drives that global

signal cannot be used. The dedicated input pin should be driven to a

known logic state (such as ground) and not be allowed to float.

When the chip-wide output enable pin is held low, it will tri-state all pins

on the device. This option can be set in the Global Project Device Options

menu. Additionally, the registers in the IOE can be reset by holding the

chip-wide reset pin low.

Row-to-IOE Connections

When an IOE is used as an input signal, it can drive two separate row

channels. The signal is accessible by all LEs within that row. When an IOE

is used as an output, the signal is driven by a multiplexer that selects a

signal from the row channels. Up to eight IOEs connect to each side of

each row channel. See Figure 14.

Figure 14. FLEX 10K Row-to-IOE Connections

Each IOE is driven by an

m-to-1 multiplexer.

Each IOE can drive up to two

row channels.

IOE8

IOE1

Row FastTrack

Interconnect

The values for m and n are provided in Table 10.

34 Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 10 lists the FLEX 10K row-to-IOE interconnect resources.

Column-to-IOE Connections

When an IOE is used as an input, it can drive up to two separate column

channels. When an IOE is used as an output, the signal is driven by a

multiplexer that selects a signal from the column channels. Two IOEs

connect to each side of the column channels. Each IOE can be driven by

column channels via a multiplexer. The set of column channels that each

IOE can access is different for each IOE. See Figure 15.

Table 10. FLEX 10K Row-to-IOE Interconnect Resources

Device Channels per Row (n) Row Channels per Pin (m)

EPF10K10

EPF10K10A 144 18

EPF10K20 144 18

EPF10K30

EPF10K30A 216 27

EPF10K40 216 27

EPF10K50

EPF10K50V 216 27

EPF10K70 312 39

EPF10K100

EPF10K100A 312 39

EPF10K130V 312 39

EPF10K250A 456 57

Altera Corporation 35

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Figure 15. FLEX 10K Column-to-IOE Connections

Table 11 lists the FLEX 10K column-to-IOE interconnect resources.

Each IOE is driven by

an m-to-1 multiplexer.

Each IOE can drive up to

two column channels.

Column

Interconnect

IOE1

The values for m and n are provided in Table 11.

Table 11. FLEX 10K Column-to-IOE Interconnect Resources

Device Channels per Column (n) Column Channel per Pin (m)

EPF10K10

EPF10K10A 24 16

EPF10K20 24 16

EPF10K30

EPF10K30A 24 16

EPF10K40 24 16

EPF10K50

EPF10K50V 24 16

EPF10K70 24 16

EPF10K100

EPF10K100A 24 16

EPF10K130V 32 24

EPF10K250A 40 32

36 Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

SameFrame

Pin-Outs

FLEX 10KE devices support the SameFrame pin-out feature for

FineLine BGA packages. The SameFrame pin-out feature is the

arrangement of balls on FineLine BGA packages such that the lower-ball-

count packages form a subset of the higher-ball-count packages.

SameFrame pin-outs provide the flexibility to migrate not only from

device to device within the same package, but also from one package to

another. A given printed circuit board (PCB) layout can support multiple

device density/package combinations. For example, a single board layout

can support a range of devices from an EPF10K10A device in a 256-pin

FineLine BGA package to an EPF10K100A device in a 484-pin

FineLine BGA package.

The Altera software provides support to design PCBs with SameFrame

pin-out devices. Devices can be defined for present and future use. The

Altera software generates pin-outs describing how to lay out a board to

take advantage of this migration (see Figure 16).

Figure 16. SameFrame Pin-Out Example

Designed for 484-PinFineLine BGA Package

Printed Circuit Board

256-Pin FineLine BGA Package

(Reduced I/O Count or

Logic Requirements)

484-Pin FineLine BGA Package

(Increased I/O Count or

Logic Requirements)

256-Pin

FineLine

BGA

484-Pin

FineLine

BGA

Altera Corporation 37

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

ClockLock &

ClockBoost

Features

To support high-speed designs, selected FLEX 10K devices offer optional

ClockLock and ClockBoost circuitry containing a phase-locked loop (PLL)

that is used to increase design speed and reduce resource usage. The

ClockLock circuitry uses a synchronizing PLL that reduces the clock delay

and skew within a device. This reduction minimizes clock-to-output and

setup times while maintaining zero hold times. The ClockBoost circuitry,

which provides a clock multiplier, allows the designer to enhance device

area efficiency by sharing resources within the device. The ClockBoost

feature allows the designer to distribute a low-speed clock and multiply

that clock on-device. Combined, the ClockLock and ClockBoost features

provide significant improvements in system performance and

bandwidth.

The ClockLock and ClockBoost features in FLEX 10K devices are enabled

through the Altera software. External devices are not required to use these

features. The output of the ClockLock and ClockBoost circuits is not

available at any of the device pins.

The ClockLock and ClockBoost circuitry locks onto the rising edge of the

incoming clock. The circuit output can only drive the clock inputs of

registers; the generated clock cannot be gated or inverted.

The dedicated clock pin (GCLK1) supplies the clock to the ClockLock and

ClockBoost circuitry. When the dedicated clock pin is driving the

ClockLock or ClockBoost circuitry, it cannot drive elsewhere in the

device.

In designs that require both a multiplied and non-multiplied clock, the

clock trace on the board can be connected to GCLK1. With the Altera

software, GCLK1 can feed both the ClockLock and ClockBoost circuitry in

the FLEX 10K device. However, when both circuits are used, the other

clock pin (GCLK0) cannot be used. Figure 17 shows a block diagram of how

to enable both the ClockLock and ClockBoost circuits in the Altera

software. The example shown is a schematic, but a similar approach

applies for designs created in AHDL, VHDL, and Verilog HDL. When the

ClockLock and ClockBoost circuits are used simultaneously, the input

frequency parameter must be the same for both circuits. In Figure 17, the

input frequency must meet the requirements specified when the

ClockBoost multiplication factor is two.

38 Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Figure 17. Enabling ClockLock & ClockBoost in the Same Design

To use both the ClockLock and ClockBoost circuits in the same design,

designers must use Revision C EPF10K100GC503-3DX devices and

MAX+PLUS II software versions 7.2 or higher. The die revision is

indicated by the third digit of the nine-digit code on the top side of the

device.

Output

Conﬁguration

This section discusses the peripheral component interconnect (PCI)

pull-up clamping diode option, slew-rate control, open-drain output

option, MultiVolt I/O interface, and power sequencing for FLEX 10K

devices. The PCI pull-up clamping diode, slew-rate control, and

open-drain output options are controlled pin-by-pin via Altera logic

options. The MultiVolt I/O interface is controlled by connecting VCCIO to

a different voltage than VCCINT. Its effect can be simulated in the Altera

software via the Global Project Device Options dialog box (Assign

menu).

PCI Clamping Diodes

The EPF10K10A and EPF10K30A devices have a pull-up clamping diode

on every I/O, dedicated input, and dedicated clock pin. PCI clamping

diodes clamp the transient overshoot caused by reflected waves to the

VCCIO value and are required for 3.3-V PCI compliance. Clamping diodes

can also be used to limit overshoot in other systems.

Clamping diodes are controlled on a pin-by-pin basis via a logic option in

the Altera software. When VCCIO is 3.3 V, a pin that has the clamping

diode turned on can be driven by a 2.5-V or 3.3-V signal, but not a 5.0-V

signal. When VCCIO is 2.5 V, a pin that has the clamping diode turned on

can be driven by a 2.5-V signal, but not a 3.3-V or 5.0-V signal. However,

a clamping diode can be turned on for a subset of pins, which allows

devices to bridge between a 3.3-V PCI bus and a 5.0-V device.

aout

bout

gclk1

CLKLOCK

CLOCKBOOST=1

INPUT_FREQUENCY=50

CLOCKBOOST=2

INPUT_FREQUENCY=50

Altera Corporation 39

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Slew-Rate Control

The output buffer in each IOE has an adjustable output slew rate that can

be configured for low-noise or high-speed performance. A slower slew

rate reduces system noise and adds a maximum delay of approximately

2.9 ns. The fast slew rate should be used for speed-critical outputs in

systems that are adequately protected against noise. Designers can specify

the slew rate on a pin-by-pin basis during design entry or assign a default

slew rate to all pins on a device-wide basis. The slow slew rate setting

affects only the falling edge of the output.

Open-Drain Output Option

FLEX 10K devices provide an optional open-drain (electrically equivalent

to an open-collector) output for each I/O pin. This open-drain output

enables the device to provide system-level control signals (e.g., interrupt

and write enable signals) that can be asserted by any of several devices. It

can also provide an additional wired-OR plane. Additionally, the Altera

software can convert tri-state buffers with grounded data inputs to open-

drain pins automatically.

Open-drain output pins on FLEX 10K devices (with a pull-up resistor to

the 5.0-V supply) can drive 5.0-V CMOS input pins that require a VIH of

3.5 V. When the open-drain pin is active, it will drive low. When the pin

is inactive, the trace will be pulled up to 5.0 V by the resistor. The open-

drain pin will only drive low or tri-state; it will never drive high. The rise

time is dependent on the value of the pull-up resistor and load

impedance. The IOL current specification should be considered when

selecting a pull-up resistor.

Output pins on 5.0-V FLEX 10K devices with VCCIO = 3.3 V or 5.0 V (with

a pull-up resistor to the 5.0-V supply) can also drive 5.0-V CMOS input

pins. In this case, the pull-up transistor will turn off when the pin voltage

exceeds 3.3 V. Therefore, the pin does not have to be open-drain.

MultiVolt I/O Interface

The FLEX 10K device architecture supports the MultiVolt I/O interface

feature, which allows FLEX 10K devices to interface with systems of

differing supply voltages. These devices have one set of VCC pins for

internal operation and input buffers (VCCINT) and another set for I/O

output drivers (VCCIO).

40 Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 12 describes the FLEX 10K device supply voltages and MultiVolt

I/O support levels.

Note

(1) 240-pin QFP packages do not support the MultiVolt I/O features, so they do not have separate VCCIO pins.

Power Sequencing & Hot-Socketing

Because FLEX 10K devices can be used in a multi-voltage environment,

they have been designed specifically to tolerate any possible power-up

sequence. The VCCIO and VCCINT power supplies can be powered in any

order.

Signals can be driven into FLEX 10KA devices before and during power

up without damaging the device. Additionally, FLEX 10KA devices do

not drive out during power up. Once operating conditions are reached,

FLEX 10KA devices operate as specified by the user.

IEEE Std.

1149.1 (JTAG)

Boundary-Scan

Support

All FLEX 10K devices provide JTAG BST circuitry that complies with the

IEEE Std. 1149.1-1990 specification. All FLEX 10K devices can also be

configured using the JTAG pins through the BitBlaster serial download

cable, or ByteBlasterMV parallel port download cable, or via hardware

that uses the JamTM programming and test language. JTAG BST can be

performed before or after configuration, but not during configuration.

FLEX 10K devices support the JTAG instructions shown in Table 13.

Table 12. Supply Voltages & MultiVolt I/O Support Levels

Devices Supply Voltage (V) MultiVolt I/O Support Levels (V)

VCCINT VCCIO Input Output

FLEX 10K (1) 5.0 5.0 3.3 or 5.0 5.0

5.0 3.3 3.3 or 5.0 3.3 or 5.0

EPF10K50V (1) 3.3 3.3 3.3 or 5.0 3.3 or 5.0

EPF10K130V 3.3 3.3 3.3 or 5.0 3.3 or 5.0

FLEX 10KA (1) 3.3 3.3 2.5, 3.3, or 5.0 3.3 or 5.0

3.3 2.5 2.5, 3.3, or 5.0 2.5

Altera Corporation 41

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

The instruction register length of FLEX 10K devices is 10 bits. The

USERCODE register length in FLEX 10K devices is 32 bits; 7 bits are

determined by the user, and 25 bits are predetermined. Tables 14 and 15

show the boundary-scan register length and device IDCODE information

for FLEX 10K devices.

Table 13. FLEX 10K JTAG Instructions

JTAG Instruction Description

SAMPLE/PRELOAD Allows a snapshot of signals at the device pins to be captured and examined during

normal device operation, and permits an initial data pattern output at the device pins.

EXTEST Allows the external circuitry and board-level interconnections to be tested by forcing a

test pattern at the output pins and capturing test results at the input pins.

BYPASS Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST

data to pass synchronously through a selected device to adjacent devices during normal

device operation.

USERCODE Selects the user electronic signature (USERCODE) register and places it between the

TDI and TDO pins, allowing the USERCODE to be serially shifted out of TDO.

IDCODE Selects the IDCODE register and places it between TDI and TDO, allowing the IDCODE

to be serially shifted out of TDO.

ICR Instructions These instructions are used when configuring a FLEX 10K device via JTAG ports with a

BitBlaster, or ByteBlasterMV or MasterBlaster download cable, or using a Jam File

(.jam) or Jam Byte-Code File (.jbc) via an embedded processor.

Table 14. FLEX 10K Boundary-Scan Register Length

Device Boundary-Scan

EPF10K10, EPF10K10A 480

EPF10K20 624

EPF10K30, EPF10K30A 768

EPF10K40 864

EPF10K50, EPF10K50V 960

EPF10K70 1,104

EPF10K100, EPF10K100A 1,248

EPF10K130V 1,440

EPF10K250A 1,440

42 Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Notes:

(1) The most significant bit (MSB) is on the left.

(2) The least significant bit (LSB) for all JTAG IDCODEs is 1.

FLEX 10K devices include weak pull-ups on JTAG pins.

fFor more information, see the following documents:

■Application Note 39 (IEEE 1149.1 (JTAG) Boundary-Scan Testing in

Altera Devices)

■BitBlaster Serial Download Cable Data Sheet

■ByteBlasterMV Parallel Port Download Cable Data Sheet

■Jam Programming & Test Language Specification

Table 15. 32-Bit FLEX 10K Device IDCODE Note (1)

Device IDCODE (32 Bits)

Version

(4 Bits) Part Number

(16 Bits) Manufacturer’s Identity

(11 Bits) 1 (1 Bit)

(2)

EPF10K10, EPF10K10A 0000 0001 0000 0001 0000 00001101110 1

EPF10K20 0000 0001 0000 0010 0000 00001101110 1

EPF10K30, EPF10K30A 0000 0001 0000 0011 0000 00001101110 1

EPF10K40 0000 0001 0000 0100 0000 00001101110 1

EPF10K50, EPF10K50V 0000 0001 0000 0101 0000 00001101110 1

EPF10K70 0000 0001 0000 0111 0000 00001101110 1

EPF10K100, EPF10K100A 0000 0000 0001 0000 0000 00001101110 1

EPF10K130V 0000 0000 0001 0011 0000 00001101110 1

EPF10K250A 0000 0000 0010 0101 0000 00001101110 1

Altera Corporation 43

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Figure 18 shows the timing requirements for the JTAG signals.

Figure 18. JTAG Waveforms

Table 16 shows the timing parameters and values for FLEX 10K devices.

Table 16. JTAG Timing Parameters & Values

Symbol Parameter Min Max Unit

tJCP TCK clock period 100 ns

tJCH TCK clock high time 50 ns

tJCL TCK clock low time 50 ns

tJPSU JTAG port setup time 20 ns

tJPH JTAG port hold time 45 ns

tJPCO JTAG port clock to output 25 ns

tJPZX JTAG port high impedance to valid output 25 ns

tJPXZ JTAG port valid output to high impedance 25 ns

tJSSU Capture register setup time 20 ns

tJSH Capture register hold time 45 ns

tJSCO Update register clock to output 35 ns

tJSZX Update register high-impedance to valid output 35 ns

tJSXZ Update register valid output to high impedance 35 ns

TDO

TCK

tJPZX tJPCO

tJPH

tJPXZ

tJCP

tJPSU

t JCL

tJCH

TDI

TMS

Signal

to Be

Captured

Signal

to Be

Driven

tJSZX

tJSSU tJSH

tJSCO tJSXZ

44 Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Generic Testing Each FLEX 10K device is functionally tested. Complete testing of each

configurable SRAM bit and all logic functionality ensures 100% yield.

AC test measurements for FLEX 10K devices are made under conditions

equivalent to those shown in Figure 19. Multiple test patterns can be used

to configure devices during all stages of the production flow.

Figure 19. FLEX 10K AC Test Conditions

Operating

Conditions

Tables 17 through 21 provide information on absolute maximum ratings,

recommended operating conditions, DC operating conditions, and

capacitance for 5.0-V FLEX 10K devices.

VCC

To Test

System

C1 (includes

JIG capacitance)

Device input

rise and fall

times < 3 ns

Device

Output

250 Ω

(8.06 kΩ)

[481 Ω]

464 Ω

(703 Ω)

[521 Ω]

Power supply transients can affect AC

measurements. Simultaneous transitions of

multiple outputs should be avoided for

accurate measurement. Threshold tests must

not be performed under AC conditions.

Large-amplitude, fast-ground-current

transients normally occur as the device

outputs discharge the load capacitances.

When these transients ﬂow through the

parasitic inductance between the device

ground pin and the test system ground,

signiﬁcant reductions in observable noise

immunity can result. Numbers without

parentheses are for 5.0-V devices or outputs.

Numbers in parentheses are for 3.3-V devices

or outputs. Numbers in brackets are for

2.5-V devices or outputs.

Table 17. FLEX 10K 5.0-V Device Absolute Maximum Ratings Note (1)

Symbol Parameter Conditions Min Max Unit

VCC Supply voltage With respect to ground (2) –2.0 7.0 V

VIDC input voltage –2.0 7.0 V

IOUT DC output current, per pin –25 25 mA

TSTG Storage temperature No bias –65 150 ° C

TAMB Ambient temperature Under bias –65 135 ° C

TJJunction temperature Ceramic packages, under bias 150 ° C

PQFP, TQFP, RQFP, and BGA

packages, under bias 135 ° C

Altera Corporation 45

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 18. FLEX 10K 5.0-V Device Recommended Operating Conditions

Symbol Parameter Conditions Min Max Unit

VCCINT Supply voltage for internal logic

and input buffers (3), (4) 4.75 (4.50) 5.25 (5.50) V

VCCIO Supply voltage for output

buffers, 5.0-V operation (3), (4) 4.75 (4.50) 5.25 (5.50) V

Supply voltage for output

buffers, 3.3-V operation (3), (4) 3.00 (3.00) 3.60 (3.60) V

VIInput voltage –0.5 VCCINT + 0.5 V

VOOutput voltage 0 VCCIO V

TAAmbient temperature For commercial use 0 70 ° C

For industrial use –40 85 ° C

TJOperating temperature For commercial use 0 85 ° C

For industrial use –40 100 ° C

tRInput rise time 40 ns

tFInput fall time 40 ns

46 Altera Corporation
FLEX 10K Embedded Programmable Logic Device Family Data Sheet
Table 19. FLEX 10K 5.0-V Device DC Operating Conditions       Notes (5), (6)
Symbol Parameter Conditions Min Typ Max Unit
VIH High-level input 
voltage 2.0 VCCINT + 0.5 V
VIL Low-level input voltage –0.5 0.8 V
VOH 5.0-V high-level TTL 
output voltage IOH = –4 mA DC, VCCIO = 4.75 V 
(7) 2.4 V
3.3-V high-level TTL 
output voltage IOH = –4 mA DC, VCCIO = 3.00 V 
(7) 2.4 V
3.3-V high-level CMOS 
output voltage IOH = –0.1 mA DC, VCCIO = 3.00 V 
(7) VCCIO – 0.2 V
VOL 5.0-V low-level TTL 
output voltage IOL = 12 mA DC, VCCIO = 4.75 V 
(8) 0.45 V
3.3-V low-level TTL 
output voltage IOL = 12 mA DC, VCCIO = 3.00 V 
(8) 0.45 V
3.3-V low-level CMOS 
output voltage IOL = 0.1 mA DC, VCCIO = 3.00 V 
(8) 0.2 V
IIInput pin leakage 
current VI = VCC or ground
(9) –10 10 µA
IOZ Tri-stated I/O pin 
leakage current VO = VCC or ground
(9) –40 40 µA
ICC0 VCC supply current 
(standby) VI = ground, no load 0.5 10 mA
Table 20. 5.0-V Device Capacitance of EPF10K10, EPF10K20 & EPF10K30 Devices       Note (10)
Symbol Parameter Conditions Min Max Unit
CIN Input capacitance VIN = 0 V, f = 1.0 MHz 8 pF
CINCLK Input capacitance on dedicated 
clock pin VIN = 0 V, f = 1.0 MHz 12 pF
COUT Output capacitance VOUT = 0 V, f = 1.0 MHz 8 pF
Table 21. 5.0-V Device Capacitance of EPF10K40, EPF10K50, EPF10K70 & EPF10K100 Devices    Note (10)
Symbol Parameter Conditions Min Max Unit
CIN Input capacitance VIN = 0 V, f = 1.0 MHz 10 pF
CINCLK Input capacitance on dedicated 
clock pin VIN = 0 V, f = 1.0 MHz 15 pF
COUT Output capacitance VOUT = 0 V, f = 1.0 MHz 10 pF

Altera Corporation 47

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Notes to tables:

(1) See the Operating Requirements for Altera Devices Data Sheet.

(2) Minimum DC input voltage is –0.5 V. During transitions, the inputs may undershoot to –2.0 V for input currents

less than 100 mA and periods shorter than 20 ns.

(3) Numbers in parentheses are for industrial-temperature-range devices.

(4) Maximum VCC rise time is 100 ms. VCC must rise monotonically.

(5) Typical values are for TA = 25° C and VCC = 5.0 V.

(6) These values are specified under the Recommended Operation Condition shown in Table 18 on page 45.

(7) The IOH parameter refers to high-level TTL or CMOS output current.

(8) The IOL parameter refers to low-level TTL or CMOS output current. This parameter applies to open-drain pins as

well as output pins.

(9) This value is specified for normal device operation. The value may vary during power-up.

(10) Capacitance is sample-tested only.

Figure 20 shows the typical output drive characteristics of FLEX 10K

devices with 5.0-V and 3.3-V VCCIO. The output driver is compliant with

the 5.0-V PCI Local Bus Specification, Revision 2.2 (for 5.0-V VCCIO).

Figure 20. Output Drive Characteristics of FLEX 10K Devices

VO Output Voltage (V)

12345

150

120

IOL

IOH

3.3

VCCINT = 5.0 V

VCCIO = 3.3 V

Room Temperature

VO Output Voltage (V)

12345

150

120

IOL

IOH

VCCINT = 5.0 V

VCCIO = 5.0 V

Room Temperature

Typical IO

Output

Current (mA)

Typical IO

Output

Current (mA)

5.0-V 3.3-V

48 Altera Corporation
FLEX 10K Embedded Programmable Logic Device Family Data Sheet
Tables 22 through 25 provide information on absolute maximum ratings, 
recommended operating conditions, DC operating conditions, and 
capacitance for EPF10K50V and EPF10K130V devices.            
Table 22. EPF10K50V & EPF10K130V Device Absolute Maximum Ratings       Note (1)
Symbol Parameter Conditions Min Max Unit
VCC Supply voltage With respect to ground (2) –0.5 4.6 V
VIDC input voltage –2.0 5.75 V
IOUT DC output current, per pin –25 25 mA
TSTG Storage temperature No bias –65 150 ° C
TAMB Ambient temperature Under bias –65 135 ° C
TJJunction temperature Ceramic packages, under bias 150 ° C
RQFP and BGA packages, under 
bias 135 ° C
Table 23. EPF10K50V & EPF10K130V Device Recommended Operating Conditions
Symbol Parameter Conditions Min Max Unit
VCCINT Supply voltage for internal logic 
and input buffers (3), (4) 3.00 (3.00) 3.60 (3.60) V
VCCIO Supply voltage for output 
buffers (3), (4) 3.00 (3.00) 3.60 (3.60) V
VIInput voltage (5) -0.5 5.75 V
VOOutput voltage 0 VCCIO V
TAAmbient temperature For commercial use 0 70 ° C
For industrial use –40 85 ° C
TJOperating temperature For commercial use 0 85 ° C
For industrial use –40 100 ° C
tRInput rise time 40 ns
tFInput fall time 40 ns

Altera Corporation 49

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Notes to tables:

(1) See the Operating Requirements for Altera Devices Data Sheet.

(2) Minimum DC input voltage is –0.5 V. During transitions, the inputs may undershoot to –2.0 V or overshoot to 5.75 V

for input currents less than 100 mA and periods shorter than 20 ns.

(3) Numbers in parentheses are for industrial-temperature-range devices.

(4) Maximum VCC rise time is 100 ms. VCC must rise monotonically.

(5) EPF10K50V and EPF10K130V device inputs may be driven before VCCINT and VCCIO are powered.

(6) Typical values are for TA = 25° C and VCC = 3.3 V.

(7) These values are specified under the EPF10K50V and EPF10K130V device Recommended Operating Conditions in

Table 23 on page 48.

(8) The IOH parameter refers to high-level TTL or CMOS output current.

(9) The IOL parameter refers to low-level TTL or CMOS output current. This parameter applies to open-drain pins as

well as output pins.

(10) This value is specified for normal device operation. The value may vary during power-up.

(11) This parameter applies to -1 speed grade EPF10K50V devices, -2 speed grade EPF10K50V industrial temperature

devices, and -2 speed grade EPF10K130V devices.

(12) Capacitance is sample-tested only.

Table 24. EPF10K50V & EPF10K130V Device DC Operating Conditions Notes (6), (7)

Symbol Parameter Conditions Min Typ Max Unit

VIH High-level input voltage 2.0 5.75 V

VIL Low-level input voltage –0.5 0.8 V

VOH 3.3-V high-level TTL output

voltage IOH = –8 mA DC (8) 2.4 V

3.3-V high-level CMOS output

voltage IOH = –0.1 mA DC (8) VCCIO – 0.2 V

VOL 3.3-V low-level TTL output

voltage IOL = 8 mA DC (9) 0.45 V

3.3-V low-level CMOS output

voltage IOL = 0.1 mA DC (9) 0.2 V

IIInput pin leakage current VI = 5.3 V to –0.3 V (10) –10 10 µA

IOZ Tri-stated I/O pin leakage

current VO = 5.3 V to –0.3 V (10) –10 10 µA

ICC0 VCC supply current (standby) VI = ground, no load 0.3 10 mA

VI = ground, no load (11) 10 mA

Table 25. EPF10K50V & EPF10K130V Device Capacitance (12)

Symbol Parameter Conditions Min Max Unit

CIN Input capacitance VIN = 0 V, f = 1.0 MHz 10 pF

CINCLK Input capacitance on dedicated

clock pin VIN = 0 V, f = 1.0 MHz 15 pF

COUT Output capacitance VOUT = 0 V, f = 1.0 MHz 10 pF

50 Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Figure 21 shows the typical output drive characteristics of EPF10K50V

and EPF10K130V devices.

Figure 21. Output Drive Characteristics of EPF10K50V & EPF10K130V Devices

Tables 26 through 31 provide information on absolute maximum ratings,

recommended operating conditions, DC operating conditions, and

capacitance for 3.3-V FLEX 10K devices.

VO Output Voltage (V)

123

IOH

Vcc = 3.3 V

Room Temperature

IOL

Typical IO

Output

Current (mA)

Table 26. FLEX 10KA 3.3-V Device Absolute Maximum Ratings Note (1)

Symbol Parameter Conditions Min Max Unit

VCC Supply voltage With respect to ground (2) –0.5 4.6 V

VIDC input voltage –2.0 5.75 V

IOUT DC output current, per pin –25 25 mA

TSTG Storage temperature No bias –65 150 ° C

TAMB Ambient temperature Under bias –65 135 ° C

TJJunction temperature Ceramic packages, under bias 150 ° C

PQFP, TQFP, RQFP, and BGA

packages, under bias 135 ° C

Altera Corporation 51

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 27. FLEX 10KA 3.3-V Device Recommended Operating Conditions

Symbol Parameter Conditions Min Max Unit

VCCINT Supply voltage for internal logic

and input buffers (3), (4) 3.00 (3.00) 3.60 (3.60) V

VCCIO Supply voltage for output

buffers, 3.3-V operation (3), (4) 3.00 (3.00) 3.60 (3.60) V

Supply voltage for output

buffers, 2.5-V operation (3), (4) 2.30 (2.30) 2.70 (2.70) V

VIInput voltage (5) –0.5 5.75 V

VOOutput voltage 0 VCCIO V

TAAmbient temperature For commercial use 0 70 ° C

For industrial use –40 85 ° C

TJOperating temperature For commercial use 0 85 ° C

For industrial use –40 100 ° C

tRInput rise time 40 ns

tFInput fall time 40 ns

52 Altera Corporation
FLEX 10K Embedded Programmable Logic Device Family Data Sheet
Table 28. FLEX 10KA 3.3-V Device DC Operating Conditions       Notes (6), (7)
Symbol Parameter Conditions Min Typ Max Unit
VIH High-level input voltage 1.7 or 
0.5 × VCCINT, 
whichever is 
lower
5.75 V
VIL Low-level input voltage –0.5 0.3 × VCCINT V
VOH 3.3-V high-level TTL output 
voltage IOH = –11 mA DC, 
VCCIO = 3.00 V (8) 2.4 V
3.3-V high-level CMOS output 
voltage IOH = –0.1 mA DC, 
VCCIO = 3.00 V (8) VCCIO – 0.2 V
3.3-V high-level PCI output 
voltage IOH = –0.5 mA DC, 
VCCIO = 3.00 to 3.60 V (8) 0.9 × VCCIO V
2.5-V high-level output voltage IOH = –0.1 mA DC, 
VCCIO = 2.30 V (8) 2.1 V
IOH = –1 mA DC, 
VCCIO = 2.30 V (8) 2.0 V
IOH = –2 mA DC, 
VCCIO = 2.30 V (8) 1.7 V
VOL 3.3-V low-level TTL output 
voltage IOL = 9 mA DC, 
VCCIO = 3.00 V (9) 0.45 V
3.3-V low-level CMOS output 
voltage IOL = 0.1 mA DC, 
VCCIO = 3.00 V (9) 0.2 V
3.3-V low-level PCI output 
voltage IOL = 1.5 mA DC, 
VCCIO = 3.00 to 3.60 V (9) 0.1 × VCCIO V
2.5-V low-level output voltage IOL = 0.1 mA DC, 
VCCIO = 2.30 V (9) 0.2 V
IOL = 1 mA DC, 
VCCIO = 2.30 V (9) 0.4 V
IOL = 2 mA DC, 
VCCIO = 2.30 V (9) 0.7 V
IIInput pin leakage current VI = 5.3 V to –0.3 V (10) –10 10 µA
IOZ Tri-stated I/O pin leakage 
current VO = 5.3 V to –0.3 V (10) –10 10 µA
ICC0 VCC supply current (standby) VI = ground, no load 0.3 10 mA
VI = ground, no load (11) 10 mA

Altera Corporation 53

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Notes to tables:

(1) See the Operating Requirements for Altera Devices Data Sheet.

(2) Minimum DC voltage input is –0.5 V. During transitions, the inputs may undershoot to –2.0 V or overshoot to

5.75 V for input currents less than 100 mA and periods shorter than 20 ns.

(3) Numbers in parentheses are for industrial-temperature-range devices.

(4) Maximum VCC rise time is 100 ms, and VCC must rise monotonically.

(5) FLEX 10KA device inputs may be driven before VCCINT and VCCIO are powered.

(6) Typical values are for TA = 25° C and VCC = 3.3 V.

(7) These values are specified under the Recommended Operating Conditions shown in Table 27 on page 51.

(8) The IOH parameter refers to high-level TTL, PCI, or CMOS output current.

(9) The IOL parameter refers to low-level TTL, PCI, or CMOS output current. This parameter applies to open-drain pins

as well as output pins.

(10) This value is specified for normal device operation. The value may vary during power-up.

(11) This parameter applies to all -1 speed grade commercial temperature devices and all -2 speed grade

industrial-temperature devices.

(12) Capacitance is sample-tested only.

Table 29. 3.3-V Device Capacitance of EPF10K10A & EPF10K30A Devices Note (12)

Symbol Parameter Conditions Min Max Unit

CIN Input capacitance VIN = 0 V, f = 1.0 MHz 8 pF

CINCLK Input capacitance on dedicated

clock pin VIN = 0 V, f = 1.0 MHz 12 pF

COUT Output capacitance VOUT = 0 V, f = 1.0 MHz 8 pF

Table 30. 3.3-V Device Capacitance of EPF10K100A Devices Note (12)

Symbol Parameter Conditions Min Max Unit

CIN Input capacitance VIN = 0 V, f = 1.0 MHz 10 pF

CINCLK Input capacitance on dedicated

clock pin VIN = 0 V, f = 1.0 MHz 15 pF

COUT Output capacitance VOUT = 0 V, f = 1.0 MHz 10 pF

Table 31. 3.3-V Device Capacitance of EPF10K250A Devices Note (12)

Symbol Parameter Conditions Min Max Unit

CIN Input capacitance VIN = 0 V, f = 1.0 MHz 10 pF

CINCLK Input capacitance on dedicated

clock pin VIN = 0 V, f = 1.0 MHz 15 pF

COUT Output capacitance VOUT = 0 V, f = 1.0 MHz 10 pF

54 Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Figure 22 shows the typical output drive characteristics of EPF10K10A,

EPF10K30A, EPF10K100A, and EPF10K250A devices with 3.3-V and 2.5-V

VCCIO. The output driver is compliant with the 3.3-V PCI Local Bus

Specification, Revision 2.2 (with 3.3-V VCCIO). Moreover, device analysis

shows that the EPF10K10A, EPF10K30A, and EPF 10K100A devices can

drive a 5.0-V PCI bus with eight or fewer loads.

Figure 22. Output Drive Characteristics for EPF10K10A, EPF10K30A & EPF10K100A Devices

Figure 23 shows the typical output drive characteristics of the

EPF10K250A device with 3.3-V and 2.5-V VCCIO.

VO Output Voltage (V)

1234

IOH

VO Output Voltage (V)

1234

IOL

IOH

VCCINT = 3.3

VCCIO = 3.3

Room Temperature

VCCINT = 3.3 V

VCCIO = 2.5 V

Room Temperature

IOL

Typical IO

Output

Current (mA)

Typical IO

Output

Current (mA)

Altera Corporation 55

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Figure 23. Output Drive Characteristics for EPF10K250A Device

Timing Model The continuous, high-performance FastTrack Interconnect routing

resources ensure predictable performance and accurate simulation and

timing analysis. This predictable performance contrasts with that of

FPGAs, which use a segmented connection scheme and therefore have

unpredictable performance.

Device performance can be estimated by following the signal path from a

source, through the interconnect, to the destination. For example, the

registered performance between two LEs on the same row can be

calculated by adding the following parameters:

■LE register clock-to-output delay (tCO)

■Interconnect delay (tSAMEROW)

■LE look-up table delay (tLUT)

■LE register setup time (tSU)

The routing delay depends on the placement of the source and destination

LEs. A more complex registered path may involve multiple combinatorial

LEs between the source and destination LEs.

VCCINT = 3.3 V

VCCIO = 3.3 V

Room Temperature

VCCINT = 3.3 V

VCCIO = 2.5 V

Room Temperature

VO Output Voltage (V)

1234

VO Output Voltage (V)

1234

IOL

IOH

IOL

IOH

Typical IO

Output

Current (mA)

Typical IO

Output

Current (mA)

56 Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Timing simulation and delay prediction are available with the

MAX+PLUS II Simulator and Timing Analyzer, or with industry-

standard EDA tools. The Simulator offers both pre-synthesis functional

simulation to evaluate logic design accuracy and post-synthesis timing

simulation with 0.1-ns resolution. The Timing Analyzer provides point-

to-point timing delay information, setup and hold time analysis, and

device-wide performance analysis.

Figure 24 shows the overall timing model, which maps the possible paths

to and from the various elements of the FLEX 10K device.

Figure 24. FLEX 10K Device Timing Model

Dedicated

Clock/Input Interconnect I/O Element

Logic

Element Embedded Array

Block

Altera Corporation 57

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Figures 25 through 27 show the delays that correspond to various paths

and functions within the LE, IOE, and EAB timing models.

Figure 25. FLEX 10K Device LE Timing Model

tCGENR

tCO

tCOMB

tSU

tPRE

tCLR

Delays

LUT Delay

tLUT

tRLUT

tCLUT

Carry Chain

Delay

Carry-In Cascade-In

Data-Out

tCGEN

tCICO

Packed Register

Delay

tPACKED

Delay

tEN

Data-In

Control-In

tCASC

Cascade-Out

Carry-Out

tLABCARRY tLABCASC

58 Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Figure 26. FLEX 10K Device IOE Timing Model

Figure 27. FLEX 10K Device EAB Timing Model

Figures 28 shows the timing model for bidirectional I/O pin timing.

Data-In

I/O Register

Delays

IOCO

IOCOMB

IOSU

IOH

IOCLR

Output Data

Delay

IOD

I/O Element

Control Delay

IOC

Input Register Delay

INREG

Output

Delays

OD1

OD2

OD3

ZX1

ZX2

ZX3

I/O Register

Feedback Delay

IOFD

Input Delay

INCOMB

Clock Enable

Clear

Data Feedback

into FastTrack

Interconnect

Clock

Output Enable

EAB Data Input

Delays

tEABDATA1

tEABDATA2

Data-In

Write Enable

Input Delays

tEABWE1

tEABWE2

EAB Clock

Delay

tEABCLK

Input Register

Delays

tEABCO

tEABBYPASS

tEABSU

tEABH

tEABCH

tEABCL

RAM/ROM

Block Delays

tAA

tDD

tWP

tWDSU

tWDH

tWASU

tWAH

tWO

Output Register

Delays

tEABCO

tEABBYPASS

tEABSU

tEABH

tEABCH

tEABCL

tEABOUT

Address

Input Register

Clock

Output Register

Clock

Data-Out

EAB Output

Delay

Altera Corporation 59

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Figure 28. Synchronous Bidirectional Pin External Timing Model

Tables 32 through 36 describe the FLEX 10K device internal timing

parameters. These internal timing parameters are expressed as worst-case

values. Using hand calculations, these parameters can be used to estimate

design performance. However, before committing designs to silicon,

actual worst-case performance should be modeled using timing

simulation and analysis. Tables 37 through 38 describe FLEX 10K external

timing parameters.

PRN

CLRN

PRN

CLRN

PRN

CLRN

Dedicated

Clock

Bidirectional

Output Register

tINSUBIDIR

tOUTCOBIDIR

tXZBIDIR

tZXBIDIR

tINHBIDIR

OE Register

Input Register

Table 32. LE Timing Microparameters (Part 1 of 2) Note (1)

Symbol Parameter Conditions

tLUT LUT delay for data-in

tCLUT LUT delay for carry-in

tRLUT LUT delay for LE register feedback

tPACKED Data-in to packed register delay

tEN LE register enable delay

tCICO Carry-in to carry-out delay

tCGEN Data-in to carry-out delay

tCGENR LE register feedback to carry-out delay

tCASC Cascade-in to cascade-out delay

tCLE register control signal delay

tCO LE register clock-to-output delay

tCOMB Combinatorial delay

60 Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

tSU LE register setup time for data and enable signals before clock; LE register

recovery time after asynchronous clear, preset, or load

tHLE register hold time for data and enable signals after clock

tPRE LE register preset delay

tCLR LE register clear delay

tCH Minimum clock high time from clock pin

tCL Minimum clock low time from clock pin

Table 33. IOE Timing Microparameters Note (1)

Symbol Parameter Conditions

tIOD IOE data delay

tIOC IOE register control signal delay

tIOCO IOE register clock-to-output delay

tIOCOMB IOE combinatorial delay

tIOSU IOE register setup time for data and enable signals before clock; IOE register

recovery time after asynchronous clear

tIOH IOE register hold time for data and enable signals after clock

tIOCLR IOE register clear time

tOD1 Output buffer and pad delay, slow slew rate = off, VCCIO = VCCINT C1 = 35 pF (2)

tOD2 Output buffer and pad delay, slow slew rate = off, VCCIO = low voltage C1 = 35 pF (3)

tOD3 Output buffer and pad delay, slow slew rate = on C1 = 35 pF (4)

tXZ IOE output buffer disable delay

tZX1 IOE output buffer enable delay, slow slew rate = off, VCCIO = VCCINT C1 = 35 pF (2)

tZX2 IOE output buffer enable delay, slow slew rate = off, VCCIO = low voltage C1 = 35 pF (3)

tZX3 IOE output buffer enable delay, slow slew rate = on C1 = 35 pF (4)

tINREG IOE input pad and buffer to IOE register delay

tIOFD IOE register feedback delay

tINCOMB IOE input pad and buffer to FastTrack Interconnect delay

Table 32. LE Timing Microparameters (Part 2 of 2) Note (1)

Symbol Parameter Conditions

Altera Corporation 61

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 34. EAB Timing Microparameters Note (1)

Symbol Parameter Conditions

tEABDATA1 Data or address delay to EAB for combinatorial input

tEABDATA2 Data or address delay to EAB for registered input

tEABWE1 Write enable delay to EAB for combinatorial input

tEABWE2 Write enable delay to EAB for registered input

tEABCLK EAB register clock delay

tEABCO EAB register clock-to-output delay

tEABBYPASS Bypass register delay

tEABSU EAB register setup time before clock

tEABH EAB register hold time after clock

tAA Address access delay

tWP Write pulse width

tWDSU Data setup time before falling edge of write pulse (5)

tWDH Data hold time after falling edge of write pulse (5)

tWASU Address setup time before rising edge of write pulse (5)

tWAH Address hold time after falling edge of write pulse (5)

tWO Write enable to data output valid delay

tDD Data-in to data-out valid delay

tEABOUT Data-out delay

tEABCH Clock high time

tEABCL Clock low time

62 Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 35. EAB Timing Macroparameters Notes (1), (6)

Symbol Parameter Conditions

tEABAA EAB address access delay

tEABRCCOMB EAB asynchronous read cycle time

tEABRCREG EAB synchronous read cycle time

tEABWP EAB write pulse width

tEABWCCOMB EAB asynchronous write cycle time

tEABWCREG EAB synchronous write cycle time

tEABDD EAB data-in to data-out valid delay

tEABDATACO EAB clock-to-output delay when using output registers

tEABDATASU EAB data/address setup time before clock when using input register

tEABDATAH EAB data/address hold time after clock when using input register

tEABWESU EAB WE setup time before clock when using input register

tEABWEH EAB WE hold time after clock when using input register

tEABWDSU EAB data setup time before falling edge of write pulse when not using input

registers

tEABWDH EAB data hold time after falling edge of write pulse when not using input

registers

tEABWASU EAB address setup time before rising edge of write pulse when not using

input registers

tEABWAH EAB address hold time after falling edge of write pulse when not using input

registers

tEABWO EAB write enable to data output valid delay

Altera Corporation  63
FLEX 10K Embedded Programmable Logic Device Family Data Sheet
Table 36. Interconnect Timing Microparameters          Note (1)
Symbol Parameter Conditions
tDIN2IOE Delay from dedicated input pin to IOE control input (7)
tDCLK2LE Delay from dedicated clock pin to LE or EAB clock  (7)
tDIN2DATA Delay from dedicated input or clock to LE or EAB data (7)
tDCLK2IOE Delay from dedicated clock pin to IOE clock (7)
tDIN2LE Delay from dedicated input pin to LE or EAB control input (7)
tSAMELAB Routing delay for an LE driving another LE in the same LAB
tSAMEROW Routing delay for a row IOE, LE, or EAB driving a row IOE, LE, or EAB in the 
same row (7)
tSAMECOLUMN Routing delay for an LE driving an IOE in the same column (7)
tDIFFROW Routing delay for a column IOE, LE, or EAB driving an LE or EAB in a different 
row (7)
tTWOROWS Routing delay for a row IOE or EAB driving an LE or EAB in a different row (7)
tLEPERIPH Routing delay for an LE driving a control signal of an IOE via the peripheral 
control bus (7)
tLABCARRY Routing delay for the carry-out signal of an LE driving the carry-in signal of a 
different LE in a different LAB
tLABCASC Routing delay for the cascade-out signal of an LE driving the cascade-in 
signal of a different LE in a different LAB
Table 37. External Timing Parameters        Notes (8), (10)
Symbol Parameter Conditions
tDRR Register-to-register delay via four LEs, three row interconnects, and four local 
interconnects (9)
tINSU Setup time with global clock at IOE register
tINH Hold time with global clock at IOE register
tOUTCO Clock-to-output delay with global clock at IOE register
Table 38. External Bidirectional Timing Parameters       Note (10)
Symbol Parameter Condition
tINSUBIDIR Setup time for bidirectional pins with global clock at adjacent LE register
tINHBIDIR Hold time for bidirectional pins with global clock at adjacent LE register
tOUTCOBIDIR Clock-to-output delay for bidirectional pins with global clock at IOE register
tXZBIDIR Synchronous IOE output buffer disable delay
tZXBIDIR Synchronous IOE output buffer enable delay, slow slew rate = off

64 Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Notes to tables:

(1) Microparameters are timing delays contributed by individual architectural elements. These parameters cannot be

measured explicitly.

(2) Operating conditions: VCCIO = 5.0 V ± 5% for commercial use in FLEX 10K devices.

VCCIO = 5.0 V ± 10% for industrial use in FLEX 10K devices.

VCCIO = 3.3 V ± 10% for commercial or industrial use in FLEX 10KA devices.

(3) Operating conditions: VCCIO = 3.3 V ± 10% for commercial or industrial use in FLEX 10K devices.

VCCIO = 2.5 V ± 0.2 V for commercial or industrial use in FLEX 10KA devices.

(4) Operating conditions: VCCIO = 2.5 V, 3.3 V, or 5.0 V.

(5) Because the RAM in the EAB is self-timed, this parameter can be ignored when the WE signal is registered.

(6) EAB macroparameters are internal parameters that can simplify predicting the behavior of an EAB at its boundary;

these parameters are calculated by summing selected microparameters.

(7) These parameters are worst-case values for typical applications. Post-compilation timing simulation and timing

analysis are required to determine actual worst-case performance.

(8) External reference timing parameters are factory-tested, worst-case values specified by Altera. A representative

subset of signal paths is tested to approximate typical device applications.

(9) Contact Altera Applications for test circuit specifications and test conditions.

(10) These timing parameters are sample-tested only.

Figures 29 and 30 show the asynchronous and synchronous timing

waveforms, respectively, for the EAB macroparameters in Table 34.

Figure 29. EAB Asynchronous Timing Waveforms

EAB Asynchronous Write

EAB Asynchronous Read

d0 d3

EABRCCOMB

a1 a2 a3

EABAA

Address

Data-Out

din1 dout2

EABDD

a1 a2

din1

din0

EABWCCOMB

EABWASU

EABWAH

EABWDH

EABWDSU

EABWP

din0

Data-In

Address

Data-Out

Altera Corporation 65

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Figure 30. EAB Synchronous Timing Waveforms

CLK

EAB Synchronous Read

EABDATASU

EABRCREG

EABDATACO

a1 a2 a3

EABDATAH

CLK

dout0 din1 din2 din3 din2

EABWESU

EABWCREG

EABWEH

EABDATACO

a1 a2 a3 a2

din3

din2

din1

EABDATAH

EABDATASU

EAB Synchronous Write (EAB Output Registers Used)

dout1

Address

Data-Out

Address

Data-Out

Data-In

66 Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Tables 39 through 47 show EPF10K10 and EPF10K20 device internal and

external timing parameters.

Table 39. EPF10K10 & EPF10K20 Device LE Timing Microparameters Note (1)

Symbol -3 Speed Grade -4 Speed Grade Unit

Min Max Min Max

tLUT 1.4 1.7 ns

tCLUT 0.6 0.7 ns

tRLUT 1.5 1.9 ns

tPACKED 0.6 0.9 ns

tEN 1.0 1.2 ns

tCICO 0.2 0.3 ns

tCGEN 0.9 1.2 ns

tCGENR 0.9 1.2 ns

tCASC 0.8 0.9 ns

tC1.3 1.5 ns

tCO 0.9 1.1 ns

tCOMB 0.5 0.6 ns

tSU 1.3 2.5 ns

tH1.4 1.6 ns

tPRE 1.0 1.2 ns

tCLR 1.0 1.2 ns

tCH 4.0 4.0 ns

tCL 4.0 4.0 ns

Altera Corporation 67

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 40. EPF10K10 & EPF10K20 Device IOE Timing Microparameters Note (1)

Symbol -3 Speed Grade -4 Speed Grade Unit

Min Max Min Max

tIOD 1.3 1.6 ns

tIOC 0.5 0.7 ns

tIOCO 0.2 0.2 ns

tIOCOMB 0.0 0.0 ns

tIOSU 2.8 3.2 ns

tIOH 1.0 1.2 ns

tIOCLR 1.0 1.2 ns

tOD1 2.6 3.5 ns

tOD2 4.9 6.4 ns

tOD3 6.3 8.2 ns

tXZ 4.5 5.4 ns

tZX1 4.5 5.4 ns

tZX2 6.8 8.3 ns

tZX3 8.2 10.1 ns

tINREG 6.0 7.5 ns

tIOFD 3.1 3.5 ns

tINCOMB 3.1 3.5 ns

68 Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 41. EPF10K10 & EPF10K20 Device EAB Internal Microparameters Note (1)

Symbol -3 Speed Grade -4 Speed Grade Unit

Min Max Min Max

tEABDATA1 1.5 1.9 ns

tEABDATA2 4.8 6.0 ns

tEABWE1 1.0 1.2 ns

tEABWE2 5.0 6.2 ns

tEABCLK 1.0 2.2 ns

tEABCO 0.5 0.6 ns

tEABBYPASS 1.5 1.9 ns

tEABSU 1.5 1.8 ns

tEABH 2.0 2.5 ns

tAA 8.7 10.7 ns

tWP 5.8 7.2 ns

tWDSU 1.6 2.0 ns

tWDH 0.3 0.4 ns

tWASU 0.5 0.6 ns

tWAH 1.0 1.2 ns

tWO 5.0 6.2 ns

tDD 5.0 6.2 ns

tEABOUT 0.5 0.6 ns

tEABCH 4.0 4.0 ns

tEABCL 5.8 7.2 ns

Altera Corporation 69

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 42. EPF10K10 & EPF10K20 Device EAB Internal Timing Macroparameters Note (1)

Symbol -3 Speed Grade -4 Speed Grade Unit

Min Max Min Max

tEABAA 13.7 17.0 ns

tEABRCCOMB 13.7 17.0 ns

tEABRCREG 9.7 11.9 ns

tEABWP 5.8 7.2 ns

tEABWCCOMB 7.3 9.0 ns

tEABWCREG 13.0 16.0 ns

tEABDD 10.0 12.5 ns

tEABDATACO 2.0 3.4 ns

tEABDATASU 5.3 5.6 ns

tEABDATAH 0.0 0.0 ns

tEABWESU 5.5 5.8 ns

tEABWEH 0.0 0.0 ns

tEABWDSU 5.5 5.8 ns

tEABWDH 0.0 0.0 ns

tEABWASU 2.1 2.7 ns

tEABWAH 0.0 0.0 ns

tEABWO 9.5 11.8 ns

70 Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 43. EPF10K10 Device Interconnect Timing Microparameters Note (1)

Symbol -3 Speed Grade -4 Speed Grade Unit

Min Max Min Max

tDIN2IOE 4.8 6.2 ns

tDIN2LE 2.6 3.8 ns

tDIN2DATA 4.3 5.2 ns

tDCLK2IOE 3.4 4.0 ns

tDCLK2LE 2.6 3.8 ns

tSAMELAB 0.6 0.6 ns

tSAMEROW 3.6 3.8 ns

tSAMECOLUMN 0.9 1.1 ns

tDIFFROW 4.5 4.9 ns

tTWOROWS 8.1 8.7 ns

tLEPERIPH 3.3 3.9 ns

tLABCARRY 0.5 0.8 ns

tLABCASC 2.7 3.0 ns

Table 44. EPF10K20 Device Interconnect Timing Microparameters Note (1)

Symbol -3 Speed Grade -4 Speed Grade Unit

Min Max Min Max

tDIN2IOE 5.2 6.6 ns

tDIN2LE 2.6 3.8 ns

tDIN2DATA 4.3 5.2 ns

tDCLK2IOE 4.3 4.0 ns

tDCLK2LE 2.6 3.8 ns

tSAMELAB 0.6 0.6 ns

tSAMEROW 3.7 3.9 ns

tSAMECOLUMN 1.4 1.6 ns

tDIFFROW 5.1 5.5 ns

tTWOROWS 8.8 9.4 ns

tLEPERIPH 4.7 5.6 ns

tLABCARRY 0.5 0.8 ns

tLABCASC 2.7 3.0 ns

Altera Corporation  71
FLEX 10K Embedded Programmable Logic Device Family Data Sheet
Notes to tables:
(1) All timing parameters are described in Tables 32 through 38 in this data sheet.
(2) Using an LE to register the signal may provide a lower setup time.
(3) This parameter is specified by characterization.
Table 45. EPF10K10 & EPF10K20 Device External Timing Parameters       Note (1)
Symbol -3 Speed Grade -4 Speed Grade Unit
Min Max Min Max
tDRR 16.1 20.0 ns
tINSU (2), (3) 5.5 6.0 ns
tINH (3) 0.0 0.0 ns
tOUTCO (3) 2.0 6.7 2.0 8.4 ns
Table 46. EPF10K10 Device External Bidirectional Timing Parameters       Note (1)
Symbol -3 Speed Grade -4 Speed Grade Unit
Min Max Min Max
tINSUBIDIR 4.5 5.6 ns
tINHBIDIR 0.0 0.0 ns
tOUTCOBIDIR 2.0 6.7 2.0 8.4 ns
tXZBIDIR 10.5 13.4 ns
tZXBIDIR 10.5 13.4 ns
Table 47. EPF10K20 Device External Bidirectional Timing Parameters       Note (1)
Symbol -3 Speed Grade -4 Speed Grade Unit
Min Max Min Max
tINSUBIDIR 4.6 5.7 ns
tINHBIDIR 0.0 0.0 ns
tOUTCOBIDIR 2.0 6.7 2.0 8.4 ns
tXZBIDIR 10.5 13.4 ns
tZXBIDIR 10.5 13.4 ns

72 Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Tables 48 through 56 show EPF10K30, EPF10K40, and EPF10K50 device

internal and external timing parameters.

Table 48. EPF10K30, EPF10K40 & EPF10K50 Device LE Timing Microparameters Note (1)

Symbol -3 Speed Grade -4 Speed Grade Unit

Min Max Min Max

tLUT 1.3 1.8 ns

tCLUT 0.6 0.6 ns

tRLUT 1.5 2.0 ns

tPACKED 0.5 0.8 ns

tEN 0.9 1.5 ns

tCICO 0.2 0.4 ns

tCGEN 0.9 1.4 ns

tCGENR 0.9 1.4 ns

tCASC 1.0 1.2 ns

tC1.3 1.6 ns

tCO 0.9 1.2 ns

tCOMB 0.6 0.6 ns

tSU 1.4 1.4 ns

tH0.9 1.3 ns

tPRE 0.9 1.2 ns

tCLR 0.9 1.2 ns

tCH 4.0 4.0 ns

tCL 4.0 4.0 ns

Altera Corporation 73

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 49. EPF10K30, EPF10K40 & EPF10K50 Device IOE Timing Microparameters Note (1)

Symbol -3 Speed Grade -4 Speed Grade Unit

Min Max Min Max

tIOD 0.4 0.6 ns

tIOC 0.5 0.9 ns

tIOCO 0.4 0.5 ns

tIOCOMB 0.0 0.0 ns

tIOSU 3.1 3.5 ns

tIOH 1.0 1.9 ns

tIOCLR 1.0 1.2 ns

tOD1 3.3 3.6 ns

tOD2 5.6 6.5 ns

tOD3 7.0 8.3 ns

tXZ 5.2 5.5 ns

tZX1 5.2 5.5 ns

tZX2 7.5 8.4 ns

tZX3 8.9 10.2 ns

tINREG 7.7 10.0 ns

tIOFD 3.3 4.0 ns

tINCOMB 3.3 4.0 ns

74 Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 50. EPF10K30, EPF10K40 & EPF10K50 Device EAB Internal Microparameters Note (1)

Symbol -3 Speed Grade -4 Speed Grade Unit

Min Max Min Max

tEABDATA1 1.5 1.9 ns

tEABDATA2 4.8 6.0 ns

tEABWE1 1.0 1.2 ns

tEABWE2 5.0 6.2 ns

tEABCLK 1.0 2.2 ns

tEABCO 0.5 0.6 ns

tEABBYPASS 1.5 1.9 ns

tEABSU 1.5 1.8 ns

tEABH 2.0 2.5 ns

tAA 8.7 10.7 ns

tWP 5.8 7.2 ns

tWDSU 1.6 2.0 ns

tWDH 0.3 0.4 ns

tWASU 0.5 0.6 ns

tWAH 1.0 1.2 ns

tWO 5.0 6.2 ns

tDD 5.0 6.2 ns

tEABOUT 0.5 0.6 ns

tEABCH 4.0 4.0 ns

tEABCL 5.8 7.2 ns

Altera Corporation 75

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 51. EPF10K30, EPF10K40 & EPF10K50 Device EAB Internal Timing Macroparameters Note (1)

Symbol -3 Speed Grade -4 Speed Grade Unit

Min Max Min Max

tEABAA 13.7 17.0 ns

tEABRCCOMB 13.7 17.0 ns

tEABRCREG 9.7 11.9 ns

tEABWP 5.8 7.2 ns

tEABWCCOMB 7.3 9.0 ns

tEABWCREG 13.0 16.0 ns

tEABDD 10.0 12.5 ns

tEABDATACO 2.0 3.4 ns

tEABDATASU 5.3 5.6 ns

tEABDATAH 0.0 0.0 ns

tEABWESU 5.5 5.8 ns

tEABWEH 0.0 0.0 ns

tEABWDSU 5.5 5.8 ns

tEABWDH 0.0 0.0 ns

tEABWASU 2.1 2.7 ns

tEABWAH 0.0 0.0 ns

tEABWO 9.5 11.8 ns

76 Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 52. EPF10K30 Device Interconnect Timing Microparameters Note (1)

Symbol -3 Speed Grade -4 Speed Grade Unit

Min Max Min Max

tDIN2IOE 6.9 8.7 ns

tDIN2LE 3.6 4.8 ns

tDIN2DATA 5.5 7.2 ns

tDCLK2IOE 4.6 6.2 ns

tDCLK2LE 3.6 4.8 ns

tSAMELAB 0.3 0.3 ns

tSAMEROW 3.3 3.7 ns

tSAMECOLUMN 2.5 2.7 ns

tDIFFROW 5.8 6.4 ns

tTWOROWS 9.1 10.1 ns

tLEPERIPH 6.2 7.1 ns

tLABCARRY 0.4 0.6 ns

tLABCASC 2.4 3.0 ns

Table 53. EPF10K40 Device Interconnect Timing Microparameters Note (1)

Symbol -3 Speed Grade -4 Speed Grade Unit

Min Max Min Max

tDIN2IOE 7.6 9.4 ns

tDIN2LE 3.6 4.8 ns

tDIN2DATA 5.5 7.2 ns

tDCLK2IOE 4.6 6.2 ns

tDCLK2LE 3.6 4.8 ns

tSAMELAB 0.3 0.3 ns

tSAMEROW 3.3 3.7 ns

tSAMECOLUMN 3.1 3.2 ns

tDIFFROW 6.4 6.4 ns

tTWOROWS 9.7 10.6 ns

tLEPERIPH 6.4 7.1 ns

tLABCARRY 0.4 0.6 ns

tLABCASC 2.4 3.0 ns

Altera Corporation 77

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 54. EPF10K50 Device Interconnect Timing Microparameters Note (1)

Symbol -3 Speed Grade -4 Speed Grade Unit

Min Max Min Max

tDIN2IOE 8.4 10.2 ns

tDIN2LE 3.6 4.8 ns

tDIN2DATA 5.5 7.2 ns

tDCLK2IOE 4.6 6.2 ns

tDCLK2LE 3.6 4.8 ns

tSAMELAB 0.3 0.3 ns

tSAMEROW 3.3 3.7 ns

tSAMECOLUMN 3.9 4.1 ns

tDIFFROW 7.2 7.8 ns

tTWOROWS 10.5 11.5 ns

tLEPERIPH 7.5 8.2 ns

tLABCARRY 0.4 0.6 ns

tLABCASC 2.4 3.0 ns

Table 55. EPF10K30, EPF10K40 & EPF10K50 Device External Timing Parameters Note (1)

Symbol -3 Speed Grade -4 Speed Grade Unit

Min Max Min Max

tDRR 17.2 21.1 ns

tINSU (2), (3) 5.7 6.4 ns

tINH (3) 0.0 0.0 ns

tOUTCO (3) 2.0 8.8 2.0 11.2 ns

Table 56. EPF10K30, EPF10K40 & EPF10K50 Device External Bidirectional Timing Parameters Note (1)

Symbol -3 Speed Grade -4 Speed Grade Unit

Min Max Min Max

tINSUBIDIR 4.1 4.6 ns

tINHBIDIR 0.0 0.0 ns

tOUTCOBIDIR 2.0 8.8 2.0 11.2 ns

tXZBIDIR 12.3 15.0 ns

tZXBIDIR 12.3 15.0 ns

78 Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Notes to tables:

(1) All timing parameters are described in Tables 32 through 38 in this data sheet.

(2) Using an LE to register the signal may provide a lower setup time.

(3) This parameter is specified by characterization.

Tables 57 through 63 show EPF10K70 device internal and external timing

parameters.

Table 57. EPF10K70 Device LE Timing Microparameters Note (1)

Symbol -2 Speed Grade -3 Speed Grade -4 Speed Grade Unit

Min Max Min Max Min Max

tLUT 1.3 1.5 2.0 ns

tCLUT 0.4 0.4 0.5 ns

tRLUT 1.5 1.6 2.0 ns

tPACKED 0.8 0.9 1.3 ns

tEN 0.8 0.9 1.2 ns

tCICO 0.2 0.2 0.3 ns

tCGEN 1.0 1.1 1.4 ns

tCGENR 1.1 1.2 1.5 ns

tCASC 1.0 1.1 1.3 ns

tC0.7 0.8 1.0 ns

tCO 0.9 1.0 1.4 ns

tCOMB 0.4 0.5 0.7 ns

tSU 1.9 2.1 2.6 ns

tH2.1 2.3 3.1 ns

tPRE 0.9 1.0 1.4 ns

tCLR 0.9 1.0 1.4 ns

tCH 4.0 4.0 4.0 ns

tCL 4.0 4.0 4.0 ns

Altera Corporation 79

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 58. EPF10K70 Device IOE Timing Microparameters Note (1)

Symbol -2 Speed Grade -3 Speed Grade -4 Speed Grade Unit

Min Max Min Max Min Max

tIOD 0.0 0.0 0.0 ns

tIOC 0.4 0.5 0.7 ns

tIOCO 0.4 0.4 0.9 ns

tIOCOMB 0.0 0.0 0.0 ns

tIOSU 4.5 5.0 6.2 ns

tIOH 0.4 0.5 0.7 ns

tIOCLR 0.6 0.7 1.6 ns

tOD1 3.6 4.0 5.0 ns

tOD2 5.6 6.3 7.3 ns

tOD3 6.9 7.7 8.7 ns

tXZ 5.5 6.2 6.8 ns

tZX1 5.5 6.2 6.8 ns

tZX2 7.5 8.5 9.1 ns

tZX3 8.8 9.9 10.5 ns

tINREG 8.0 9.0 10.2 ns

tIOFD 7.2 8.1 10.3 ns

tINCOMB 7.2 8.1 10.3 ns

80 Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 59. EPF10K70 Device EAB Internal Microparameters Note (1)

Symbol -2 Speed Grade -3 Speed Grade -4 Speed Grade Unit

Min Max Min Max Min Max

tEABDATA1 1.3 1.5 1.9 ns

tEABDATA2 4.3 4.8 6.0 ns

tEABWE1 0.9 1.0 1.2 ns

tEABWE2 4.5 5.0 6.2 ns

tEABCLK 0.9 1.0 2.2 ns

tEABCO 0.4 0.5 0.6 ns

tEABBYPASS 1.3 1.5 1.9 ns

tEABSU 1.3 1.5 1.8 ns

tEABH 1.8 2.0 2.5 ns

tAA 7.8 8.7 10.7 ns

tWP 5.2 5.8 7.2 ns

tWDSU 1.4 1.6 2.0 ns

tWDH 0.3 0.3 0.4 ns

tWASU 0.4 0.5 0.6 ns

tWAH 0.9 1.0 1.2 ns

tWO 4.5 5.0 6.2 ns

tDD 4.5 5.0 6.2 ns

tEABOUT 0.4 0.5 0.6 ns

tEABCH 4.0 4.0 4.0 ns

tEABCL 5.2 5.8 7.2 ns

Altera Corporation 81

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 60. EPF10K70 Device EAB Internal Timing Macroparameters Note (1)

Symbol -2 Speed Grade -3 Speed Grade -4 Speed Grade Unit

Min Max Min Max Min Max

tEABAA 12.1 13.7 17.0 ns

tEABRCCOMB 12.1 13.7 17.0 ns

tEABRCREG 8.6 9.7 11.9 ns

tEABWP 5.2 5.8 7.2 ns

tEABWCCOMB 6.5 7.3 9.0 ns

tEABWCREG 11.6 13.0 16.0 ns

tEABDD 8.8 10.0 12.5 ns

tEABDATACO 1.7 2.0 3.4 ns

tEABDATASU 4.7 5.3 5.6 ns

tEABDATAH 0.0 0.0 0.0 ns

tEABWESU 4.9 5.5 5.8 ns

tEABWEH 0.0 0.0 0.0 ns

tEABWDSU 1.8 2.1 2.7 ns

tEABWDH 0.0 0.0 0.0 ns

tEABWASU 4.1 4.7 5.8 ns

tEABWAH 0.0 0.0 0.0 ns

tEABWO 8.4 9.5 11.8 ns

82 Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 61. EPF10K70 Device Interconnect Timing Microparameters Note (1)

Symbol -2 Speed Grade -3 Speed Grade -4 Speed Grade Unit

Min Max Min Max Min Max

tDIN2IOE 6.6 7.3 8.8 ns

tDIN2LE 4.2 4.8 6.0 ns

tDIN2DATA 6.5 7.1 10.8 ns

tDCLK2IOE 5.5 6.2 7.7 ns

tDCLK2LE 4.2 4.8 6.0 ns

tSAMELAB 0.4 0.4 0.5 ns

tSAMEROW 4.8 4.9 5.5 ns

tSAMECOLUMN 3.3 3.4 3.7 ns

tDIFFROW 8.1 8.3 9.2 ns

tTWOROWS 12.9 13.2 14.7 ns

tLEPERIPH 5.5 5.7 6.5 ns

tLABCARRY 0.8 0.9 1.1 ns

tLABCASC 2.7 3.0 3.2 ns

Table 62. EPF10K70 Device External Timing Parameters Note (1)

Symbol -2 Speed Grade -3 Speed Grade -4 Speed Grade Unit

Min Max Min Max Min Max

tDRR 17.2 19.1 24.2 ns

tINSU (2), (3) 6.6 7.3 8.0 ns

tINH (3) 0.0 0.0 0.0 ns

tOUTCO (3) 2.0 9.9 2.0 11.1 2.0 14.3 ns

Table 63. EPF10K70 Device External Bidirectional Timing Parameters Note (1)

Symbol -2 Speed Grade -3 Speed Grade -4 Speed Grade Unit

Min Max Min Max Min Max

tINSUBIDIR 7.4 8.1 10.4 ns

tINHBIDIR 0.0 0.0 0.0 ns

tOUTCOBIDIR 2.0 9.9 2.0 11.1 2.0 14.3 ns

tXZBIDIR 13.7 15.4 18.5 ns

tZXBIDIR 13.7 15.4 18.5 ns

Altera Corporation 83

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Notes to tables:

(1) All timing parameters are described in Tables 32 through 38 in this data sheet.

(2) Using an LE to register the signal may provide a lower setup time.

(3) This parameter is specified by characterization.

Tables 64 through 70 show EPF10K100 device internal and external

timing parameters.

Table 64. EPF10K100 Device LE Timing Microparameters Note (1)

Symbol -3DX Speed Grade -3 Speed Grade -4 Speed Grade Unit

Min Max Min Max Min Max

tLUT 1.5 1.5 2.0 ns

tCLUT 0.4 0.4 0.5 ns

tRLUT 1.6 1.6 2.0 ns

tPACKED 0.9 0.9 1.3 ns

tEN 0.9 0.9 1.2 ns

tCICO 0.2 0.2 0.3 ns

tCGEN 1.1 1.1 1.4 ns

tCGENR 1.2 1.2 1.5 ns

tCASC 1.1 1.1 1.3 ns

tC0.8 0.8 1.0 ns

tCO 1.0 1.0 1.4 ns

tCOMB 0.5 0.5 0.7 ns

tSU 2.1 2.1 2.6 ns

tH2.3 2.3 3.1 ns

tPRE 1.0 1.0 1.4 ns

tCLR 1.0 1.0 1.4 ns

tCH 4.0 4.0 4.0 ns

tCL 4.0 4.0 4.0 ns

84 Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 65. EPF10K100 Device IOE Timing Microparameters Note (1)

Symbol -3DX Speed Grade -3 Speed Grade -4 Speed Grade Unit

Min Max Min Max Min Max

tIOD 0.0 0.0 0.0 ns

tIOC 0.5 0.5 0.7 ns

tIOCO 0.4 0.4 0.9 ns

tIOCOMB 0.0 0.0 0.0 ns

tIOSU 5.5 5.5 6.7 ns

tIOH 0.5 0.5 0.7 ns

tIOCLR 0.7 0.7 1.6 ns

tOD1 4.0 4.0 5.0 ns

tOD2 6.3 6.3 7.3 ns

tOD3 7.7 7.7 8.7 ns

tXZ 6.2 6.2 6.8 ns

tZX1 6.2 6.2 6.8 ns

tZX2 8.5 8.5 9.1 ns

tZX3 9.9 9.9 10.5 ns

tINREG without ClockLock or

ClockBoost circuitry 9.0 9.0 10.5 ns

tINREG with ClockLock or

ClockBoost circuitry 3.0 ––ns

tIOFD 8.1 8.1 10.3 ns

tINCOMB 8.1 8.1 10.3 ns

Altera Corporation 85

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 66. EPF10K100 Device EAB Internal Microparameters Note (1)

Symbol -3DX Speed Grade -3 Speed Grade -4 Speed Grade Unit

Min Max Min Max Min Max

tEABDATA1 1.5 1.5 1.9 ns

tEABDATA2 4.8 4.8 6.0 ns

tEABWE1 1.0 1.0 1.2 ns

tEABWE2 5.0 5.0 6.2 ns

tEABCLK 1.0 1.0 2.2 ns

tEABCO 0.5 0.5 0.6 ns

tEABBYPASS 1.5 1.5 1.9 ns

tEABSU 1.5 1.5 1.8 ns

tEABH 2.0 2.0 2.5 ns

tAA 8.7 8.7 10.7 ns

tWP 5.8 5.8 7.2 ns

tWDSU 1.6 1.6 2.0 ns

tWDH 0.3 0.3 0.4 ns

tWASU 0.5 0.5 0.6 ns

tWAH 1.0 1.0 1.2 ns

tWO 5.0 5.0 6.2 ns

tDD 5.0 5.0 6.2 ns

tEABOUT 0.5 0.5 0.6 ns

tEABCH 4.0 4.0 4.0 ns

tEABCL 5.8 5.8 7.2 ns

86 Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 67. EPF10K100 Device EAB Internal Timing Macroparameters Note (1)

Symbol -3DX Speed Grade -3 Speed Grade -4 Speed Grade Unit

Min Max Min Max Min Max

tEABAA 13.7 13.7 17.0 ns

tEABRCCOMB 13.7 13.7 17.0 ns

tEABRCREG 9.7 9.7 11.9 ns

tEABWP 5.8 5.8 7.2 ns

tEABWCCOMB 7.3 7.3 9.0 ns

tEABWCREG 13.0 13.0 16.0 ns

tEABDD 10.0 10.0 12.5 ns

tEABDATACO 2.0 2.0 3.4 ns

tEABDATASU 5.3 5.3 5.6 ns

tEABDATAH 0.0 0.0 0.0 ns

tEABWESU 5.5 5.5 5.8 ns

tEABWEH 0.0 0.0 0.0 ns

tEABWDSU 5.5 5.5 5.8 ns

tEABWDH 0.0 0.0 0.0 ns

tEABWASU 2.1 2.1 2.7 ns

tEABWAH 0.0 0.0 0.0 ns

tEABWO 9.5 9.5 11.8 ns

Altera Corporation 87

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 68. EPF10K100 Device Interconnect Timing Microparameters Note (1)

Symbol -3DX Speed Grade -3 Speed Grade -4 Speed Grade Unit

Min Max Min Max Min Max

tDIN2IOE 10.3 10.3 12.2 ns

tDIN2LE 4.8 4.8 6.0 ns

tDIN2DATA 7.3 7.3 11.0 ns

tDCLK2IOE without ClockLock or

ClockBoost circuitry 6.2 6.2 7.7 ns

tDCLK2IOE with ClockLock or ClockBoost

circuitry 2.3 ––ns

tDCLK2LE without ClockLock or

ClockBoost circuitry 4.8 4.8 6.0 ns

tDCLK2LE with ClockLock or ClockBoost

circuitry 2.3 ––ns

tSAMELAB 0.4 0.4 0.5 ns

tSAMEROW 4.9 4.9 5.5 ns

tSAMECOLUMN 5.1 5.1 5.4 ns

tDIFFROW 10.0 10.0 10.9 ns

tTWOROWS 14.9 14.9 16.4 ns

tLEPERIPH 6.9 6.9 8.1 ns

tLABCARRY 0.9 0.9 1.1 ns

tLABCASC 3.0 3.0 3.2 ns

88 Altera Corporation
FLEX 10K Embedded Programmable Logic Device Family Data Sheet
Notes to tables:
(1) All timing parameters are described in Tables 32 through 38 in this data sheet.
(2) Using an LE to register the signal may provide a lower setup time.
(3) This parameter is specified by characterization.
(4) This parameter is measured without the use of the ClockLock or ClockBoost circuits.
(5) This parameter is measured with the use of the ClockLock or ClockBoost circuits.
Table 69. EPF10K100 Device External Timing Parameters       Note (1)
Symbol -3DX Speed Grade -3 Speed Grade -4 Speed Grade Unit
Min Max Min Max Min Max
tDRR 19.1 19.1 24.2 ns
tINSU (2), (3), (4) 7.8 7.8 8.5 ns
tOUTCO (3), (4) 2.0 11.1 2.0 11.1 2.0 14.3 ns
tINH (3) 0.0 0.0 0.0 ns
tINSU (2), (3), (5) 6.2 ––ns
tOUTCO (3), (5) 2.0 6.7 ––ns
Table 70. EPF10K100 Device External Bidirectional Timing Parameters       Note (1)
Symbol -3DX Speed Grade -3 Speed Grade -4 Speed Grade Unit
Min Max Min Max Min Max
tINSUBIDIR (4) 8.1 8.1 10.4 ns
tINHBIDIR (4) 0.0 0.0 0.0 ns
tOUTCOBIDIR (4) 2.0 11.1 2.0 11.1 2.0 14.3 ns
tXZBIDIR (4) 15.3 15.3 18.4 ns
tZXBIDIR (4) 15.3 15.3 18.4 ns
tINSUBIDIR (5) 9.1 ––ns
tINHBIDIR (5) 0.0 ––ns
tOUTCOBIDIR (5) 2.0 7.2 ––––ns
tXZBIDIR (5) 14.3 ––ns
tZXBIDIR (5) 14.3 ––ns

Altera Corporation 89

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Tables 71 through 77 show EPF10K50V device internal and external

timing parameters.

Table 71. EPF10K50V Device LE Timing Microparameters Note (1)

Symbol -1 Speed Grade -2 Speed Grade -3 Speed Grade -4 Speed Grade Unit

Min Max Min Max Min Max Min Max

tLUT 0.9 1.0 1.3 1.6 ns

tCLUT 0.1 0.5 0.6 0.6 ns

tRLUT 0.5 0.8 0.9 1.0 ns

tPACKED 0.4 0.4 0.5 0.7 ns

tEN 0.7 0.9 1.1 1.4 ns

tCICO 0.2 0.2 0.2 0.3 ns

tCGEN 0.8 0.7 0.8 1.2 ns

tCGENR 0.4 0.3 0.3 0.4 ns

tCASC 0.7 0.7 0.8 0.9 ns

tC0.3 1.0 1.3 1.5 ns

tCO 0.5 0.7 0.9 1.0 ns

tCOMB 0.4 0.4 0.5 0.6 ns

tSU 0.8 1.6 2.2 2.5 ns

tH0.5 0.8 1.0 1.4 ns

tPRE 0.8 0.4 0.5 0.5 ns

tCLR 0.8 0.4 0.5 0.5 ns

tCH 2.0 4.0 4.0 4.0 ns

tCL 2.0 4.0 4.0 4.0 ns

90 Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 72. EPF10K50V Device IOE Timing Microparameters Note (1)

Symbol -1 Speed Grade -2 Speed Grade -3 Speed Grade -4 Speed Grade Unit

Min Max Min Max Min Max Min Max

tIOD 1.2 1.6 1.9 2.1 ns

tIOC 0.3 0.4 0.5 0.5 ns

tIOCO 0.3 0.3 0.4 0.4 ns

tIOCOMB 0.0 0.0 0.0 0.0 ns

tIOSU 2.8 2.8 3.4 3.9 ns

tIOH 0.7 0.8 1.0 1.4 ns

tIOCLR 0.5 0.6 0.7 0.7 ns

tOD1 2.8 3.2 3.9 4.7 ns

tOD2 ––––ns

tOD3 6.5 6.9 7.6 8.4 ns

tXZ 2.8 3.1 3.8 4.6 ns

tZX1 2.8 3.1 3.8 4.6 ns

tZX2 ––––ns

tZX3 6.5 6.8 7.5 8.3 ns

tINREG 5.0 5.7 7.0 9.0 ns

tIOFD 1.5 1.9 2.3 2.7 ns

tINCOMB 1.5 1.9 2.3 2.7 ns

Altera Corporation 91

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 73. EPF10K50V Device EAB Internal Microparameters Note (1)

Symbol -1 Speed Grade -2 Speed Grade -3 Speed Grade -4 Speed Grade Unit

Min Max Min Max Min Max Min Max

tEABDATA1 1.7 2.8 3.4 4.6 ns

tEABDATA2 4.9 3.9 4.8 5.9 ns

tEABWE1 0.0 2.5 3.0 3.7 ns

tEABWE2 4.0 4.1 5.0 6.2 ns

tEABCLK 0.4 0.8 1.0 1.2 ns

tEABCO 0.1 0.2 0.3 0.4 ns

tEABBYPASS 0.9 1.1 1.3 1.6 ns

tEABSU 0.8 1.5 1.8 2.2 ns

tEABH 0.8 1.6 2.0 2.5 ns

tAA 5.5 8.2 10.0 12.4 ns

tWP 6.0 4.9 6.0 7.4 ns

tWDSU 0.1 0.8 1.0 1.2 ns

tWDH 0.1 0.2 0.3 0.4 ns

tWASU 0.1 0.4 0.5 0.6 ns

tWAH 0.1 0.8 1.0 1.2 ns

tWO 2.8 4.3 5.3 6.5 ns

tDD 2.8 4.3 5.3 6.5 ns

tEABOUT 0.5 0.4 0.5 0.6 ns

tEABCH 2.0 4.0 4.0 4.0 ns

tEABCL 6.0 4.9 6.0 7.4 ns

92 Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 74. EPF10K50V Device EAB Internal Timing Macroparameters Note (1)

Symbol -1 Speed Grade -2 Speed Grade -3 Speed Grade -4 Speed Grade Unit

Min Max Min Max Min Max Min Max

tEABAA 9.5 13.6 16.5 20.8 ns

tEABRCCOMB 9.5 13.6 16.5 20.8 ns

tEABRCREG 6.1 8.8 10.8 13.4 ns

tEABWP 6.0 4.9 6.0 7.4 ns

tEABWCCOMB 6.2 6.1 7.5 9.2 ns

tEABWCREG 12.0 11.6 14.2 17.4 ns

tEABDD 6.8 9.7 11.8 14.9 ns

tEABDATACO 1.0 1.4 1.8 2.2 ns

tEABDATASU 5.3 4.6 5.6 6.9 ns

tEABDATAH 0.0 0.0 0.0 0.0 ns

tEABWESU 4.4 4.8 5.8 7.2 ns

tEABWEH 0.0 0.0 0.0 0.0 ns

tEABWDSU 1.8 1.1 1.4 2.1 ns

tEABWDH 0.0 0.0 0.0 0.0 ns

tEABWASU 4.5 4.6 5.6 7.4 ns

tEABWAH 0.0 0.0 0.0 0.0 ns

tEABWO 5.1 9.4 11.4 14.0 ns

Altera Corporation 93

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 75. EPF10K50V Device Interconnect Timing Microparameters Note (1)

Symbol -1 Speed Grade -2 Speed Grade -3 Speed Grade -4 Speed Grade Unit

Min Max Min Max Min Max Min Max

tDIN2IOE 4.7 6.0 7.1 8.2 ns

tDIN2LE 2.5 2.6 3.1 3.9 ns

tDIN2DATA 4.4 5.9 6.8 7.7 ns

tDCLK2IOE 2.5 3.9 4.7 5.5 ns

tDCLK2LE 2.5 2.6 3.1 3.9 ns

tSAMELAB 0.2 0.2 0.3 0.3 ns

tSAMEROW 2.8 3.0 3.2 3.4 ns

tSAMECOLUMN 3.0 3.2 3.4 3.6 ns

tDIFFROW 5.8 6.2 6.6 7.0 ns

tTWOROWS 8.6 9.2 9.8 10.4 ns

tLEPERIPH 4.5 5.5 6.1 7.0 ns

tLABCARRY 0.3 0.4 0.5 0.7 ns

tLABCASC 0.0 1.3 1.6 2.0 ns

Table 76. EPF10K50V Device External Timing Parameters Note (1)

Symbol -1 Speed Grade -2 Speed Grade -3 Speed Grade -4 Speed Grade Unit

Min Max Min Max Min Max Min Max

tDRR 11.2 14.0 17.2 21.1 ns

tINSU (2), (3) 5.5 4.2 5.2 6.9 ns

tINH (3) 0.0 0.0 0.0 0.0 ns

tOUTCO (3) 2.0 5.9 2.0 7.8 2.0 9.5 2.0 11.1 ns

Table 77. EPF10K50V Device External Bidirectional Timing Parameters Note (1)

Symbol -1 Speed Grade -2 Speed Grade -3 Speed Grade -4 Speed Grade Unit

Min Max Min Max Min Max Min Max

tINSUBIDIR 2.0 2.8 3.5 4.1 ns

tINHBIDIR 0.0 0.0 0.0 0.0 ns

tOUTCOBIDIR 2.0 5.9 2.0 7.8 2.0 9.5 2.0 11.1 ns

tXZBIDIR 8.0 9.8 11.8 14.3 ns

tZXBIDIR 8.0 9.8 11.8 14.3 ns

94 Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Notes to tables:

(1) All timing parameters are described in Tables 32 through 38 in this data sheet.

(2) Using an LE to register the signal may provide a lower setup time.

(3) This parameter is specified by characterization.

Tables 78 through 84 show EPF10K130V device internal and external

timing parameters.

Table 78. EPF10K130V Device LE Timing Microparameters Note (1)

Symbol -2 Speed Grade -3 Speed Grade -4 Speed Grade Unit

Min Max Min Max Min Max

tLUT 1.3 1.8 2.3 ns

tCLUT 0.5 0.7 0.9 ns

tRLUT 1.2 1.7 2.2 ns

tPACKED 0.5 0.6 0.7 ns

tEN 0.6 0.8 1.0 ns

tCICO 0.2 0.3 0.4 ns

tCGEN 0.3 0.4 0.5 ns

tCGENR 0.7 1.0 1.3 ns

tCASC 0.9 1.2 1.5 ns

tC1.9 2.4 3.0 ns

tCO 0.6 0.9 1.1 ns

tCOMB 0.5 0.7 0.9 ns

tSU 0.2 0.2 0.3 ns

tH0.0 0.0 0.0 ns

tPRE 2.4 3.1 3.9 ns

tCLR 2.4 3.1 3.9 ns

tCH 4.0 4.0 4.0 ns

tCL 4.0 4.0 4.0 ns

Altera Corporation 95

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 79. EPF10K130V Device IOE Timing Microparameters Note (1)

Symbol -2 Speed Grade -3 Speed Grade -4 Speed Grade Unit

Min Max Min Max Min Max

tIOD 1.3 1.6 2.0 ns

tIOC 0.4 0.5 0.7 ns

tIOCO 0.3 0.4 0.5 ns

tIOCOMB 0.0 0.0 0.0 ns

tIOSU 2.6 3.3 3.8 ns

tIOH 0.0 0.0 0.0 ns

tIOCLR 1.7 2.2 2.7 ns

tOD1 3.5 4.4 5.0 ns

tOD2 –––ns

tOD3 8.2 8.1 9.7 ns

tXZ 4.9 6.3 7.4 ns

tZX1 4.9 6.3 7.4 ns

tZX2 –––ns

tZX3 9.6 10.0 12.1 ns

tINREG 7.9 10.0 12.6 ns

tIOFD 6.2 7.9 9.9 ns

tINCOMB 6.2 7.9 9.9 ns

96 Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 80. EPF10K130V Device EAB Internal Microparameters Note (1)

Symbol -2 Speed Grade -3 Speed Grade -4 Speed Grade Unit

Min Max Min Max Min Max

tEABDATA1 1.9 2.4 2.4 ns

tEABDATA2 3.7 4.7 4.7 ns

tEABWE1 1.9 2.4 2.4 ns

tEABWE2 3.7 4.7 4.7 ns

tEABCLK 0.7 0.9 0.9 ns

tEABCO 0.5 0.6 0.6 ns

tEABBYPASS 0.6 0.8 0.8 ns

tEABSU 1.4 1.8 1.8 ns

tEABH 0.0 0.0 0.0 ns

tAA 5.6 7.1 7.1 ns

tWP 3.7 4.7 4.7 ns

tWDSU 4.6 5.9 5.9 ns

tWDH 0.0 0.0 0.0 ns

tWASU 3.9 5.0 5.0 ns

tWAH 0.0 0.0 0.0 ns

tWO 5.6 7.1 7.1 ns

tDD 5.6 7.1 7.1 ns

tEABOUT 2.4 3.1 3.1 ns

tEABCH 4.0 4.0 4.0 ns

tEABCL 4.0 4.7 4.7 ns

Altera Corporation 97

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 81. EPF10K130V Device EAB Internal Timing Macroparameters Note (1)

Symbol -2 Speed Grade -3 Speed Grade -4 Speed Grade Unit

Min Max Min Max Min Max

tEABAA 11.2 14.2 14.2 ns

tEABRCCOMB 11.1 14.2 14.2 ns

tEABRCREG 8.5 10.8 10.8 ns

tEABWP 3.7 4.7 4.7 ns

tEABWCCOMB 7.6 9.7 9.7 ns

tEABWCREG 14.0 17.8 17.8 ns

tEABDD 11.1 14.2 14.2 ns

tEABDATACO 3.6 4.6 4.6 ns

tEABDATASU 4.4 5.6 5.6 ns

tEABDATAH 0.0 0.0 0.0 ns

tEABWESU 4.4 5.6 5.6 ns

tEABWEH 0.0 0.0 0.0 ns

tEABWDSU 4.6 5.9 5.9 ns

tEABWDH 0.0 0.0 0.0 ns

tEABWASU 3.9 5.0 5.0 ns

tEABWAH 0.0 0.0 0.0 ns

tEABWO 11.1 14.2 14.2 ns

98 Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 82. EPF10K130V Device Interconnect Timing Microparameters Note (1)

Symbol -2 Speed Grade -3 Speed Grade -4 Speed Grade Unit

Min Max Min Max Min Max

tDIN2IOE 8.0 9.0 9.5 ns

tDIN2LE 2.4 3.0 3.1 ns

tDIN2DATA 5.0 6.3 7.4 ns

tDCLK2IOE 3.6 4.6 5.1 ns

tDCLK2LE 2.4 3.0 3.1 ns

tSAMELAB 0.4 0.6 0.8 ns

tSAMEROW 4.5 5.3 6.5 ns

tSAMECOLUMN 9.0 9.5 9.7 ns

tDIFFROW 13.5 14.8 16.2 ns

tTWOROWS 18.0 20.1 22.7 ns

tLEPERIPH 8.1 8.6 9.5 ns

tLABCARRY 0.6 0.8 1.0 ns

tLABCASC 0.8 1.0 1.2 ns

Table 83. EPF10K130V Device External Timing Parameters Note (1)

Symbol -2 Speed Grade -3 Speed Grade -4 Speed Grade Unit

Min Max Min Max Min Max

tDRR 15.0 19.1 24.2 ns

tINSU (2), (3) 6.9 8.6 11.0 ns

tINH (3) 0.0 0.0 0.0 ns

tOUTCO (3) 2.0 7.8 2.0 9.9 2.0 11.3 ns

Table 84. EPF10K130V Device External Bidirectional Timing Parameters Note (1)

Symbol -2 Speed Grade -3 Speed Grade -4 Speed Grade Unit

Min Max Min Max Min Max

tINSUBIDIR 6.7 8.5 10.8 ns

tINHBIDIR 0.0 0.0 0.0 ns

tOUTCOBIDIR 2.0 6.9 2.0 8.8 2.0 10.2 ns

tXZBIDIR 12.9 16.4 19.3 ns

tZXBIDIR 12.9 16.4 19.3 ns

Altera Corporation 99

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Notes to tables:

(1) All timing parameters are described in Tables 32 through 38 in this data sheet.

(2) Using an LE to register the signal may provide a lower setup time.

(3) This parameter is specified by characterization.

Tables 85 through 91 show EPF10K10A device internal and external

timing parameters.

Table 85. EPF10K10A Device LE Timing Microparameters Note (1)

Symbol -1 Speed Grade -2 Speed Grade -3 Speed Grade Unit

Min Max Min Max Min Max

tLUT 0.9 1.2 1.6 ns

tCLUT 1.2 1.4 1.9 ns

tRLUT 1.9 2.3 3.0 ns

tPACKED 0.6 0.7 0.9 ns

tEN 0.5 0.6 0.8 ns

tCICO 02 0.3 0.4 ns

tCGEN 0.7 0.9 1.1 ns

tCGENR 0.7 0.9 1.1 ns

tCASC 1.0 1.2 1.7 ns

tC1.2 1.4 1.9 ns

tCO 0.5 0.6 0.8 ns

tCOMB 0.5 0.6 0.8 ns

tSU 1.1 1.3 1.7 ns

tH0.6 0.7 0.9 ns

tPRE 0.5 0.6 0.9 ns

tCLR 0.5 0.6 0.9 ns

tCH 3.0 3.5 4.0 ns

tCL 3.0 3.5 4.0 ns

Table 86. EPF10K10A Device IOE Timing Microparameters Note (1) (Part 1 of 2)

Symbol -1 Speed Grade -2 Speed Grade -3 Speed Grade Unit

Min Max Min Max Min Max

1.3 1.5 2.0 ns

tIOC 0.2 0.3 0.3 ns

tIOCO 0.2 0.3 0.4 ns

tIOCOMB 0.6 0.7 0.9 ns

tIOSU 0.8 1.0 1.3 ns

100 Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

tIOH 0.8 1.0 1.3 ns

tIOCLR 1.2 1.4 1.9 ns

tOD1 1.2 1.4 1.9 ns

tOD2 2.9 3.5 4.7 ns

tOD3 6.6 7.8 10.5 ns

tXZ 1.2 1.4 1.9 ns

tZX1 1.2 1.4 1.9 ns

tZX2 2.9 3.5 4.7 ns

tZX3 6.6 7.8 10.5 ns

tINREG 5.2 6.3 8.4 ns

tIOFD 3.1 3.8 5.0 ns

tINCOMB 3.1 3.8 5.0 ns

Table 86. EPF10K10A Device IOE Timing Microparameters Note (1) (Part 2 of 2)

Symbol -1 Speed Grade -2 Speed Grade -3 Speed Grade Unit

Min Max Min Max Min Max

Altera Corporation 101

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 87. EPF10K10A Device EAB Internal Microparameters Note (1)

Symbol -1 Speed Grade -2 Speed Grade -3 Speed Grade Unit

Min Max Min Max Min Max

tEABDATA1 3.3 3.9 5.2 ns

tEABDATA2 1.0 1.3 1.7 ns

tEABWE1 2.6 3.1 4.1 ns

tEABWE2 2.7 3.2 4.3 ns

tEABCLK 0.0 0.0 0.0 ns

tEABCO 1.2 1.4 1.8 ns

tEABBYPASS 0.1 0.2 0.2 ns

tEABSU 1.4 1.7 2.2 ns

tEABH 0.1 0.1 0.1 ns

tAA 4.5 5.4 7.3 ns

tWP 2.0 2.4 3.2 ns

tWDSU 0.7 0.8 1.1 ns

tWDH 0.5 0.6 0.7 ns

tWASU 0.6 0.7 0.9 ns

tWAH 0.9 1.1 1.5 ns

tWO 3.3 3.9 5.2 ns

tDD 3.3 3.9 5.2 ns

tEABOUT 0.1 0.1 0.2 ns

tEABCH 3.0 3.5 4.0 ns

tEABCL 3.03 3.5 4.0 ns

102 Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 88. EPF10K10A Device EAB Internal Timing Macroparameters Note (1)

Symbol -1 Speed Grade -2 Speed Grade -3 Speed Grade Unit

Min Max Min Max Min Max

tEABAA 8.1 9.8 13.1 ns

tEABRCCOMB 8.1 9.8 13.1 ns

tEABRCREG 5.8 6.9 9.3 ns

tEABWP 2.0 2.4 3.2 ns

tEABWCCOMB 3.5 4.2 5.6 ns

tEABWCREG 9.4 11.2 14.8 ns

tEABDD 6.9 8.3 11.0 ns

tEABDATACO 1.3 1.5 2.0 ns

tEABDATASU 2.4 3.0 3.9 ns

tEABDATAH 0.0 0.0 0.0 ns

tEABWESU 4.1 4.9 6.5 ns

tEABWEH 0.0 0.0 0.0 ns

tEABWDSU 1.4 1.6 2.2 ns

tEABWDH 0.0 0.0 0.0 ns

tEABWASU 2.5 3.0 4.1 ns

tEABWAH 0.0 0.0 0.0 ns

tEABWO 6.2 7.5 9.9 ns

Altera Corporation 103

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 89. EPF10K10A Device Interconnect Timing Microparameters Note (1)

Symbol -1 Speed Grade -2 Speed Grade -3 Speed Grade Unit

Min Max Min Max Min Max

tDIN2IOE 4.2 5.0 6.5 ns

tDIN2LE 2.2 2.6 3.4 ns

tDIN2DATA 4.3 5.2 7.1 ns

tDCLK2IOE 4.2 4.9 6.6 ns

tDCLK2LE 2.2 2.6 3.4 ns

tSAMELAB 0.1 0.1 0.2 ns

tSAMEROW 2.2 2.4 2.9 ns

tSAMECOLUMN 0.8 1.0 1.4 ns

tDIFFROW 3.0 3.4 4.3 ns

tTWOROWS 5.2 5.8 7.2 ns

tLEPERIPH 1.8 2.2 2.8 ns

tLABCARRY 0.5 0.5 0.7 ns

tLABCASC 0.9 1.0 1.5 ns

Table 90. EPF10K10A External Reference Timing Parameters Note (1)

Symbol -1 Speed Grade -2 Speed Grade -3 Speed Grade Unit

Min Max Min Max Min Max

tDRR 10.0 12.0 16.0 ns

tINSU (2), (3) 1.6 2.1 2.8 ns

tINH (3) 0.0 0.0 0.0 ns

tOUTCO (3) 2.0 5.8 2.0 6.9 2.0 9.2 ns

Table 91. EPF10K10A Device External Bidirectional Timing Parameters Note (1)

Symbol -2 Speed Grade -3 Speed Grade -4 Speed Grade Unit

Min Max Min Max Min Max

tINSUBIDIR 2.4 3.3 4.5 ns

tINHBIDIR 0.0 0.0 0.0 ns

tOUTCOBIDIR 2.0 5.8 2.0 6.9 2.0 9.2 ns

tXZBIDIR 6.3 7.5 9.9 ns

tZXBIDIR 6.3 7.5 9.9 ns

104 Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Notes to tables:

(1) All timing parameters are described in Tables 32 through 38 in this data sheet.

(2) Using an LE to register the signal may provide a lower setup time.

(3) This parameter is specified by characterization.

Tables 92 through 98 show EPF10K30A device internal and external

timing parameters.

Table 92. EPF10K30A Device LE Timing Microparameters Note (1)

Symbol -1 Speed Grade -2 Speed Grade -3 Speed Grade Unit

Min Max Min Max Min Max

tLUT 0.8 1.1 1.5 ns

tCLUT 0.6 0.7 1.0 ns

tRLUT 1.2 1.5 2.0 ns

tPACKED 0.6 0.6 1.0 ns

tEN 1.3 1.5 2.0 ns

tCICO 0.2 0.3 0.4 ns

tCGEN 0.8 1.0 1.3 ns

tCGENR 0.6 0.8 1.0 ns

tCASC 0.9 1.1 1.4 ns

tC1.1 1.3 1.7 ns

tCO 0.4 0.6 0.7 ns

tCOMB 0.6 0.7 0.9 ns

tSU 0.9 0.9 1.4 ns

tH1.1 1.3 1.7 ns

tPRE 0.5 0.6 0.8 ns

tCLR 0.5 0.6 0.8 ns

tCH 3.0 3.5 4.0 ns

tCL 3.0 3.5 4.0 ns

Table 93. EPF10K30A Device IOE Timing Microparameters Note (1) (Part 1 of 2)

Symbol -1 Speed Grade -2 Speed Grade -3 Speed Grade Unit

Min Max Min Max Min Max

tIOD 2.2 2.6 3.4 ns

tIOC 0.3 0.3 0.5 ns

tIOCO 0.2 0.2 0.3 ns

tIOCOMB 0.5 0.6 0.8 ns

tIOSU 1.4 1.7 2.2 ns

Altera Corporation 105

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

tIOH 0.9 1.1 1.4 ns

tIOCLR 0.7 0.8 1.0 ns

tOD1 1.9 2.2 2.9 ns

tOD2 4.8 5.6 7.3 ns

tOD3 7.0 8.2 10.8 ns

tXZ 2.2 2.6 3.4 ns

tZX1 2.2 2.6 3.4 ns

tZX2 5.1 6.0 7.8 ns

tZX3 7.3 8.6 11.3 ns

tINREG 4.4 5.2 6.8 ns

tIOFD 3.8 4.5 5.9 ns

tINCOMB 3.8 4.5 5.9 ns

Table 93. EPF10K30A Device IOE Timing Microparameters Note (1) (Part 2 of 2)

Symbol -1 Speed Grade -2 Speed Grade -3 Speed Grade Unit

Min Max Min Max Min Max

106 Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 94. EPF10K30A Device EAB Internal Microparameters Note (1)

Symbol -1 Speed Grade -2 Speed Grade -3 Speed Grade Unit

Min Max Min Max Min Max

tEABDATA1 5.5 6.5 8.5 ns

tEABDATA2 1.1 1.3 1.8 ns

tEABWE1 2.4 2.8 3.7 ns

tEABWE2 2.1 2.5 3.2 ns

tEABCLK 0.0 0.0 0.2 ns

tEABCO 1.7 2.0 2.6 ns

tEABBYPASS 0.0 0.0 0.3 ns

tEABSU 1.2 1.4 1.9 ns

tEABH 0.1 0.1 0.3 ns

tAA 4.2 5.0 6.5 ns

tWP 3.8 4.5 5.9 ns

tWDSU 0.1 0.1 0.2 ns

tWDH 0.1 0.1 0.2 ns

tWASU 0.1 0.1 0.2 ns

tWAH 0.1 0.1 0.2 ns

tWO 3.7 4.4 6.4 ns

tDD 3.7 4.4 6.4 ns

tEABOUT 0.0 0.1 0.6 ns

tEABCH 3.0 3.5 4.0 ns

tEABCL 3.8 4.5 5.9 ns

Altera Corporation 107

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 95. EPF10K30A Device EAB Internal Timing Macroparameters Note (1)

Symbol -1 Speed Grade -2 Speed Grade -3 Speed Grade Unit

Min Max Min Max Min Max

tEABAA 9.7 11.6 16.2 ns

tEABRCCOMB 9.7 11.6 16.2 ns

tEABRCREG 5.9 7.1 9.7 ns

tEABWP 3.8 4.5 5.9 ns

tEABWCCOMB 4.0 4.7 6.3 ns

tEABWCREG 9.8 11.6 16.6 ns

tEABDD 9.2 11.0 16.1 ns

tEABDATACO 1.7 2.1 3.4 ns

tEABDATASU 2.3 2.7 3.5 ns

tEABDATAH 0.0 0.0 0.0 ns

tEABWESU 3.3 3.9 4.9 ns

tEABWEH 0.0 0.0 0.0 ns

tEABWDSU 3.2 3.8 5.0 ns

tEABWDH 0.0 0.0 0.0 ns

tEABWASU 3.7 4.4 5.1 ns

tEABWAH 0.0 0.0 0.0 ns

tEABWO 6.1 7.3 11.3 ns

108 Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 96. EPF10K30A Device Interconnect Timing Microparameters Note (1)

Symbol -1 Speed Grade -2 Speed Grade -3 Speed Grade Unit

Min Max Min Max Min Max

tDIN2IOE 3.9 4.4 5.1 ns

tDIN2LE 1.2 1.5 1.9 ns

tDIN2DATA 3.2 3.6 4.5 ns

tDCLK2IOE 3.0 3.5 4.6 ns

tDCLK2LE 1.2 1.5 1.9 ns

tSAMELAB 0.1 0.1 0.2 ns

tSAMEROW 2.3 2.4 2.7 ns

tSAMECOLUMN 1.3 1.4 1.9 ns

tDIFFROW 3.6 3.8 4.6 ns

tTWOROWS 5.9 6.2 7.3 ns

tLEPERIPH 3.5 3.8 4.1 ns

tLABCARRY 0.3 0.4 0.5 ns

tLABCASC 0.9 1.1 1.4 ns

Table 97. EPF10K30A External Reference Timing Parameters Note (1)

Symbol -1 Speed Grade -2 Speed Grade -3 Speed Grade Unit

Min Max Min Max Min Max

tDRR 11.0 13.0 17.0 ns

tINSU (2), (3) 2.5 3.1 3.9 ns

tINH (3) 0.0 0.0 0.0 ns

tOUTCO (3) 2.0 5.4 2.0 6.2 2.0 8.3 ns

Table 98. EPF10K30A Device External Bidirectional Timing Parameters Note (1)

Symbol -1 Speed Grade -2 Speed Grade -3 Speed Grade Unit

Min Max Min Max Min Max

tINSUBIDIR 4.2 4.9 6.8 ns

tINHBIDIR 0.0 0.0 0.0 ns

tOUTCOBIDIR 2.0 5.4 2.0 6.2 2.0 8.3 ns

tXZBIDIR 6.2 7.5 9.8 ns

tZXBIDIR 6.2 7.5 9.8 ns

Altera Corporation 109

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Notes to tables:

(1) All timing parameters are described in Tables 32 through 38 in this data sheet.

(2) Using an LE to register the signal may provide a lower setup time.

(3) This parameter is specified by characterization.

Tables 99 through 105 show EPF10K100A device internal and external

timing parameters.

Table 99. EPF10K100A Device LE Timing Microparameters Note (1)

Symbol -1 Speed Grade -2 Speed Grade -3 Speed Grade Unit

Min Max Min Max Min Max

tLUT 1.0 1.2 1.4 ns

tCLUT 0.8 0.9 1.1 ns

tRLUT 1.4 1.6 1.9 ns

tPACKED 0.4 0.5 0.5 ns

tEN 0.6 0.7 0.8 ns

tCICO 0.2 0.2 0.3 ns

tCGEN 0.4 0.4 0.6 ns

tCGENR 0.6 0.7 0.8 ns

tCASC 0.7 0.9 1.0 ns

tC0.9 1.0 1.2 ns

tCO 0.2 0.3 0.3 ns

tCOMB 0.6 0.7 0.8 ns

tSU 0.8 1.0 1.2 ns

tH0.3 0.5 0.5 ns

tPRE 0.3 0.3 0.4 ns

tCLR 0.3 0.3 0.4 ns

tCH 2.5 3.5 4.0 ns

tCL 2.5 3.5 4.0 ns

110 Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 100. EPF10K100A Device IOE Timing Microparameters Note (1)

Symbol -1 Speed Grade -2 Speed Grade -3 Speed Grade Unit

Min Max Min Max Min Max

tIOD 2.5 2.9 3.4 ns

tIOC 0.3 0.3 0.4 ns

tIOCO 0.2 0.2 0.3 ns

tIOCOMB 0.5 0.6 0.7 ns

tIOSU 1.3 1.7 1.8 ns

tIOH 0.2 0.2 0.3 ns

tIOCLR 1.0 1.2 1.4 ns

tOD1 2.2 2.6 3.0 ns

tOD2 4.5 5.3 6.1 ns

tOD3 6.8 7.9 9.3 ns

tXZ 2.7 3.1 3.7 ns

tZX1 2.7 3.1 3.7 ns

tZX2 5.0 5.8 6.8 ns

tZX3 7.3 8.4 10.0 ns

tINREG 5.3 6.1 7.2 ns

tIOFD 4.7 5.5 6.4 ns

tINCOMB 4.7 5.5 6.4 ns

Altera Corporation 111

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 101. EPF10K100A Device EAB Internal Microparameters Note (1)

Symbol -1 Speed Grade -2 Speed Grade -3 Speed Grade Unit

Min Max Min Max Min Max

tEABDATA1 1.8 2.1 2.4 ns

tEABDATA2 3.2 3.7 4.4 ns

tEABWE1 0.8 0.9 1.1 ns

tEABWE2 2.3 2.7 3.1 ns

tEABCLK 0.8 0.9 1.1 ns

tEABCO 1.0 1.1 1.4 ns

tEABBYPASS 0.3 0.3 0.4 ns

tEABSU 1.3 1.5 1.8 ns

tEABH 0.4 0.5 0.5 ns

tAA 4.1 4.8 5.6 ns

tWP 3.2 3.7 4.4 ns

tWDSU 2.4 2.8 3.3 ns

tWDH 0.2 0.2 0.3 ns

tWASU 0.2 0.2 0.3 ns

tWAH 0.0 0.0 0.0 ns

tWO 3.4 3.9 4.6 ns

tDD 3.4 3.9 4.6 ns

tEABOUT 0.3 0.3 0.4 ns

tEABCH 2.5 3.5 4.0 ns

tEABCL 3.2 3.7 4.4 ns

112 Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 102. EPF10K100A Device EAB Internal Timing Macroparameters Note (1)

Symbol -1 Speed Grade -2 Speed Grade -3 Speed Grade Unit

Min Max Min Max Min Max

tEABAA 6.8 7.8 9.2 ns

tEABRCCOMB 6.8 7.8 9.2 ns

tEABRCREG 5.4 6.2 7.4 ns

tEABWP 3.2 3.7 4.4 ns

tEABWCCOMB 3.4 3.9 4.7 ns

tEABWCREG 9.4 10.8 12.8 ns

tEABDD 6.1 6.9 8.2 ns

tEABDATACO 2.1 2.3 2.9 ns

tEABDATASU 3.7 4.3 5.1 ns

tEABDATAH 0.0 0.0 0.0 ns

tEABWESU 2.8 3.3 3.8 ns

tEABWEH 0.0 0.0 0.0 ns

tEABWDSU 3.4 4.0 4.6 ns

tEABWDH 0.0 0.0 0.0 ns

tEABWASU 1.9 2.3 2.6 ns

tEABWAH 0.0 0.0 0.0 ns

tEABWO 5.1 5.7 6.9 ns

Altera Corporation 113

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 103. EPF10K100A Device Interconnect Timing Microparameters Note (1)

Symbol -1 Speed Grade -2 Speed Grade -3 Speed Grade Unit

Min Max Min Max Min Max

tDIN2IOE 4.8 5.4 6.0 ns

tDIN2LE 2.0 2.4 2.7 ns

tDIN2DATA 2.4 2.7 2.9 ns

tDCLK2IOE 2.6 3.0 3.5 ns

tDCLK2LE 2.0 2.4 2.7 ns

tSAMELAB 0.1 0.1 0.1 ns

tSAMEROW 1.5 1.7 1.9 ns

tSAMECOLUMN 5.5 6.5 7.4 ns

tDIFFROW 7.0 8.2 9.3 ns

tTWOROWS 8.5 9.9 11.2 ns

tLEPERIPH 3.9 4.2 4.5 ns

tLABCARRY 0.2 0.2 0.3 ns

tLABCASC 0.4 0.5 0.6 ns

Table 104. EPF10K100A Device External Timing Parameters Note (1)

Symbol -1 Speed Grade -2 Speed Grade -3 Speed Grade Unit

Min Max Min Max Min Max

tDRR 12.5 14.5 17.0 ns

tINSU (2), (3) 3.7 4.5 5.1 ns

tINH (3) 0.0 0.0 0.0 ns

tOUTCO (3) 2.0 5.3 2.0 6.1 2.0 7.2 ns

Table 105. EPF10K100A Device External Bidirectional Timing Parameters Note (1)

Symbol -1 Speed Grade -2 Speed Grade -3 Speed Grade Unit

Min Max Min Max Min Max

tINSUBIDIR 4.9 5.8 6.8 ns

tINHBIDIR 0.0 0.0 0.0 ns

tOUTCOBIDIR 2.0 5.3 2.0 6.1 2.0 7.2 ns

tXZBIDIR 7.4 8.6 10.1 ns

tZXBIDIR 7.4 8.6 10.1 ns

114 Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Notes to tables:

(1) All timing parameters are described in Tables 32 through 38 in this data sheet.

(2) Using an LE to register the signal may provide a lower setup time.

(3) This parameter is specified by characterization.

Tables 106 through 112 show EPF10K250A device internal and external

timing parameters.

Table 106. EPF10K250A Device LE Timing Microparameters Note (1)

Symbol -1 Speed Grade -2 Speed Grade -3 Speed Grade Unit

Min Max Min Max Min Max

tLUT 0.9 1.0 1.4 ns

tCLUT 1.2 1.3 1.6 ns

tRLUT 2.0 2.3 2.7 ns

tPACKED 0.4 0.4 0.5 ns

tEN 1.4 1.6 1.9 ns

tCICO 0.2 0.3 0.3 ns

tCGEN 0.4 0.6 0.6 ns

tCGENR 0.8 1.0 1.1 ns

tCASC 0.7 0.8 1.0 ns

tC1.2 1.3 1.6 ns

tCO 0.6 0.7 0.9 ns

tCOMB 0.5 0.6 0.7 ns

tSU 1.2 1.4 1.7 ns

tH1.2 1.3 1.6 ns

tPRE 0.7 0.8 0.9 ns

tCLR 0.7 0.8 0.9 ns

tCH 2.5 3.0 3.5 ns

tCL 2.5 3.0 3.5 ns

Altera Corporation 115

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 107. EPF10K250A Device IOE Timing Microparameters Note (1)

Symbol -1 Speed Grade -2 Speed Grade -3 Speed Grade Unit

Min Max Min Max Min Max

tIOD 1.2 1.3 1.6 ns

tIOC 0.4 0.4 0.5 ns

tIOCO 0.8 0.9 1.1 ns

tIOCOMB 0.7 0.7 0.8 ns

tIOSU 2.7 3.1 3.6 ns

tIOH 0.2 0.3 0.3 ns

tIOCLR 1.2 1.3 1.6 ns

tOD1 3.2 3.6 4.2 ns

tOD2 5.9 6.7 7.8 ns

tOD3 8.7 9.8 11.5 ns

tXZ 3.8 4.3 5.0 ns

tZX1 3.8 4.3 5.0 ns

tZX2 6.5 7.4 8.6 ns

tZX3 9.3 10.5 12.3 ns

tINREG 8.2 9.3 10.9 ns

tIOFD 9.0 10.2 12.0 ns

tINCOMB 9.0 10.2 12.0 ns

116 Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 108. EPF10K250A Device EAB Internal Microparameters Note (1)

Symbol -1 Speed Grade -2 Speed Grade -3 Speed Grade Unit

Min Max Min Max Min Max

tEABDATA1 1.3 1.5 1.7 ns

tEABDATA2 1.3 1.5 1.7 ns

tEABWE1 0.9 1.1 1.3 ns

tEABWE2 5.0 5.7 6.7 ns

tEABCLK 0.6 0.7 0.8 ns

tEABCO 0.0 0.0 0.0 ns

tEABBYPASS 0.1 0.1 0.2 ns

tEABSU 3.8 4.3 5.0 ns

tEABH 0.7 0.8 0.9 ns

tAA 4.5 5.0 5.9 ns

tWP 5.6 6.4 7.5 ns

tWDSU 1.3 1.4 1.7 ns

tWDH 0.1 0.1 0.2 ns

tWASU 0.1 0.1 0.2 ns

tWAH 0.1 0.1 0.2 ns

tWO 4.1 4.6 5.5 ns

tDD 4.1 4.6 5.5 ns

tEABOUT 0.1 0.1 0.2 ns

tEABCH 2.5 3.0 3.5 ns

tEABCL 5.6 6.4 7.5 ns

Altera Corporation 117

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 109. EPF10K250A Device EAB Internal Timing Macroparameters Note (1)

Symbol -1 Speed Grade -2 Speed Grade -3 Speed Grade Unit

Min Max Min Max Min Max

tEABAA 6.1 6.8 8.2 ns

tEABRCCOMB 6.1 6.8 8.2 ns

tEABRCREG 4.6 5.1 6.1 ns

tEABWP 5.6 6.4 7.5 ns

tEABWCCOMB 5.8 6.6 7.9 ns

tEABWCREG 15.8 17.8 21.0 ns

tEABDD 5.7 6.4 7.8 ns

tEABDATACO 0.7 0.8 1.0 ns

tEABDATASU 4.5 5.1 5.9 ns

tEABDATAH 0.0 0.0 0.0 ns

tEABWESU 8.2 9.3 10.9 ns

tEABWEH 0.0 0.0 0.0 ns

tEABWDSU 1.7 1.8 2.1 ns

tEABWDH 0.0 0.0 0.0 ns

tEABWASU 0.9 0.9 1.0 ns

tEABWAH 0.0 0.0 0.0 ns

tEABWO 5.3 6.0 7.4 ns

118 Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 110. EPF10K250A Device Interconnect Timing Microparameters Note (1)

Symbol -1 Speed Grade -2 Speed Grade -3 Speed Grade Unit

Min Max Min Max Min Max

tDIN2IOE 7.8 8.5 9.4 ns

tDIN2LE 2.7 3.1 3.5 ns

tDIN2DATA 1.6 1.6 1.7 ns

tDCLK2IOE 3.6 4.0 4.6 ns

tDCLK2LE 2.7 3.1 3.5 ns

tSAMELAB 0.2 0.3 0.3 ns

tSAMEROW 6.7 7.3 8.2 ns

tSAMECOLUMN 2.5 2.7 3.0 ns

tDIFFROW 9.2 10.0 11.2 ns

tTWOROWS 15.9 17.3 19.4 ns

tLEPERIPH 7.5 8.1 8.9 ns

tLABCARRY 0.3 0.4 0.5 ns

tLABCASC 0.4 0.4 0.5 ns

Table 111. EPF10K250A Device External Reference Timing Parameters Note (1)

Symbol -1 Speed Grade -2 Speed Grade -3 Speed Grade Unit

Min Max Min Max Min Max

tDRR 15.0 17.0 20.0 ns

tINSU (2), (3) 6.9 8.0 9.4 ns

tINH (3) 0.0 0.0 0.0 ns

tOUTCO (3) 2.0 8.0 2.0 8.9 2.0 10.4 ns

Table 112. EPF10K250A Device External Bidirectional Timing Parameters Note (1)

Symbol -1 Speed Grade -2 Speed Grade -3 Speed Grade Unit

Min Max Min Max Min Max

tINSUBIDIR 9.3 10.6 12.7 ns

tINHBIDIR 0.0 0.0 0.0 ns

tOUTCOBIDIR 2.0 8.0 2.0 8.9 2.0 10.4 ns

tXZBIDIR 10.8 12.2 14.2 ns

tZXBIDIR 10.8 12.2 14.2 ns

Altera Corporation 119

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Notes to tables:

(1) All timing parameters are described in Tables 32 through 37 in this data sheet.

(2) Using an LE to register the signal may provide a lower setup time.

(3) This parameter is specified by characterization.

ClockLock &

ClockBoost

Timing

Parameters

For the ClockLock and ClockBoost circuitry to function properly, the

incoming clock must meet certain requirements. If these specifications are

not met, the circuitry may not lock onto the incoming clock, which

generates an erroneous clock within the device. The clock generated by

the ClockLock and ClockBoost circuitry must also meet certain

specifications. If the incoming clock meets these requirements during

configuration, the ClockLock and ClockBoost circuitry will lock onto the

clock during configuration. The circuit will be ready for use immediately

after configuration. Figure 31 illustrates the incoming and generated clock

specifications.

Figure 31. Speciﬁcations for the Incoming & Generated Clocks

The tI parameter refers to the nominal input clock period; the tO parameter refers to the

nominal output clock period.

Table 113 summarizes the ClockLock and ClockBoost parameters.

tRtF

tCLK1 tINDUTY tI ± fCLKDEV

tItI ± tINCLKSTB

tOUTDUTY

tOtO + tJITTER tO – tJITTER

Input

Clock

ClockLock-

Generated

Clock

Table 113. ClockLock & ClockBoost Parameters (Part 1 of 2)

Symbol Parameter Min Typ Max Unit

tRInput rise time 2ns

tFInput fall time 2ns

tINDUTY Input duty cycle 45 55 %

fCLK1 Input clock frequency (ClockBoost clock multiplication factor equals 1) 30 80 MHz

tCLK1 Input clock period (ClockBoost clock multiplication factor equals 1) 12.5 33.3 ns

fCLK2 Input clock frequency (ClockBoost clock multiplication factor equals 2) 16 50 MHz

tCLK2 Input clock period (ClockBoost clock multiplication factor equals 2) 20 62.5 ns

120 Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Notes:

(1) To implement the ClockLock and ClockBoost circuitry with the MAX+PLUS II software, designers must specify the

input frequency. The MAX+PLUS II software tunes the PLL in the ClockLock and ClockBoost circuitry to this

frequency. The fCLKDEV parameter specifies how much the incoming clock can differ from the specified frequency

during device operation. Simulation does not reflect this parameter.

(2) During device configuration, the ClockLock and ClockBoost circuitry is configured before the rest of the device. If

the incoming clock is supplied during configuration, the ClockLock and ClockBoost circuitry locks during

configuration, because the tLOCK value is less than the time required for configuration.

(3) The tJITTER specification is measured under long-term observation.

Power

Consumption

The supply power (P) for FLEX 10K devices can be calculated with the

following equation:

P = PINT + PIO = (ICCSTANDBY + ICCACTIVE) × VCC + PIO

Typical ICCSTANDBY values are shown as ICC0 in the FLEX 10K device DC

operating conditions tables on pages 46, 49, and 52 of this data sheet. The

ICCACTIVE value depends on the switching frequency and the application

logic. This value is calculated based on the amount of current that each LE

typically consumes. The PIO value, which depends on the device output

load characteristics and switching frequency, can be calculated using the

guidelines given in Application Note 74 (Evaluating Power for Altera

Devices).

1Compared to the rest of the device, the embedded array

consumes a negligible amount of power. Therefore, the

embedded array can be ignored when calculating supply

current.

The ICCACTIVE value is calculated with the following equation:

ICCACTIVE = K × fMAX × N × togLC ×

The parameters in this equation are shown below:

fCLKDEV1 Input deviation from user specification in MAX+PLUS II (ClockBoost clock

multiplication factor equals 1) (1) ±1 MHz

fCLKDEV2 Input deviation from user specification in MAX+PLUS II (ClockBoost clock

multiplication factor equals 2) (1) ±0.5 MHz

tINCLKSTB Input clock stability (measured between adjacent clocks) 100 ps

tLOCK Time required for ClockLock or ClockBoost to acquire lock (2) 10 µs

tJITTER Jitter on ClockLock or ClockBoost-generated clock (3) 1ns

tOUTDUTY Duty cycle for ClockLock or ClockBoost-generated clock 40 50 60 %

Table 113. ClockLock & ClockBoost Parameters (Part 2 of 2)

Symbol Parameter Min Typ Max Unit

µA

MHz LE×

---------------------------

Altera Corporation 121

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

fMAX = Maximum operating frequency in MHz

N= Total number of logic cells used in the device

togLC = Average percent of logic cells toggling at each clock

(typically 12.5%)

K= Constant, shown in Tables 114 and 115

This calculation provides an ICC estimate based on typical conditions with

no output load. The actual ICC should be verified during operation

because this measurement is sensitive to the actual pattern in the device

and the environmental operating conditions.

To better reflect actual designs, the power model (and the constant K in

the power calculation equations) for continuous interconnect FLEX

devices assumes that logic cells drive FastTrack Interconnect channels. In

contrast, the power model of segmented FPGAs assumes that all logic

cells drive only one short interconnect segment. This assumption may

lead to inaccurate results, compared to measured power consumption for

an actual design in a segmented interconnect FPGA.

Figure 32 shows the relationship between the current and operating

frequency of FLEX 10K devices.

Table 114. FLEX 10K K Constant Values

Device K Value

EPF10K10 82

EPF10K20 89

EPF10K30 88

EPF10K40 92

EPF10K50 95

EPF10K70 85

EPF10K100 88

Table 115. FLEX 10KA K Constant Values

Device K Value

EPF10K10A 17

EPF10K30A 17

EPF10K50V 19

EPF10K100A 19

EPF10K130V 22

EPF10K250A 23

122 Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Figure 32. ICCACTIVE vs. Operating Frequency (Part 1 of 3)

EPF10K20

EPF10K10

EPF10K40

EPF10K30

EPF10K50 EPF10K70

Frequency (MHz)

500

450

400

350

300

250

200

150

100

30 60

15 45

ICC Supply

Current (mA)

Frequency (MHz)

1,000

900

800

700

600

500

400

300

200

100

30 60

15 45

Supply

Current (mA)

Frequency (MHz)

1,600

1,400

1,200

1,000

800

600

400

200

30 60

15 45

ICC Supply

Current (mA)

Frequency (MHz)

2,500

2,000

1,500

1,000

500

30 60

15 45

Supply

Current (mA)

Frequency (MHz)

3,000

2,500

2,000

1,500

1,000

500

30 6015 45

ICC Supply

Current (mA)

30 60

Frequency (MHz)

15 45

3,500

3,000

2,500

2,000

1,500

1,000

500

ICC Supply

Current (mA)

Altera Corporation 123

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Figure 32. ICCACTIVE vs. Operating Frequency (Part 2 of 3)

EPF10K50V

EPF10K100

EPF10K100A

EPF10K130V EPF10K10A

EPF10K30A

Frequency (MHz)

500

1,000

1,500

2,500

2,000

3,000

3,500

4,000

4,500

30 60

15 45

ICC Supply

Current (mA)

Frequency (MHz)

700

600

500

400

300

200

100

20 40 60 10080

ICC Supply

Current (mA)

Frequency (MHz)

20 40 60 100

500

1,000

1,500

Supply

Current (mA)

2,000

Frequency (MHz)

150

100

50 100

25 75

ICC Supply

Current (mA)

Frequency (MHz)

400

300

200

100

50 100

25 75

ICC Supply

Current (mA)

Frequency (MHz)

20 40 60 100

300

600

900

Supply

Current (mA)

1,200

124 Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Figure 32. ICCACTIVE vs. Operating Frequency (Part 3 of 3)

Conﬁguration &

Operation

The FLEX 10K architecture supports several configuration schemes. This

section summarizes the device operating modes and available device

configuration schemes.

fSee Application Note 116 (Configuring APEX 20K, FLEX 10K & FLEX 6000

Devices) for detailed descriptions of device configuration options, device

configuration pins, and for information on configuring FLEX 10K devices,

including sample schematics, timing diagrams, and configuration

parameters.

Operating Modes

The FLEX 10K architecture uses SRAM configuration elements that

require configuration data to be loaded every time the circuit powers up.

The process of physically loading the SRAM data into the device is called

configuration. Before configuration, as VCC rises, the device initiates a

Power-On Reset (POR). This POR event clears the device and prepares it

for configuration. The FLEX 10K POR time does not exceed 50 µs.

During initialization, which occurs immediately after configuration, the

device resets registers, enables I/O pins, and begins to operate as a logic

device. The I/O pins are tri-stated during power-up, and before and

during configuration. Together, the configuration and initialization

processes are called command mode; normal device operation is called user

mode.

EPF10K250A

Frequency (MHz)

3,500

3,000

2,500

2,000

1,500

1,000

500

20 40 60 100

ICC Supply

Current (mA)

Altera Corporation 125

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

SRAM configuration elements allow FLEX 10K devices to be reconfigured

in-circuit by loading new configuration data into the device. Real-time

reconfiguration is performed by forcing the device into command mode

with a device pin, loading different configuration data, reinitializing the

device, and resuming user-mode operation.

The entire reconfiguration process may be completed in less than 320 ms

using an EPF10K250A device with a DCLK frequency of 10 MHz. This

process can be used to reconfigure an entire system dynamically. In-field

upgrades can be performed by distributing new configuration files.

1Refer to the configuration device data sheet to obtain the POR

delay when using a configuration device method.

Programming Files

Despite being function- and pin-compatible, FLEX 10KA and FLEX 10KE

devices are not programming- or configuration-file compatible with

FLEX 10K devices. A design should be recompiled before it is transferred

from a FLEX 10K device to an equivalent FLEX 10KA or FLEX 10KE

device. This recompilation should be performed to create a new

programming or configuration file and to check design timing on the

faster FLEX 10KA or FLEX 10KE device. The programming or

configuration files for EPF10K50 devices can program or configure an

EPF10K50V device. However, Altera recommends recompiling a design

for the EPF10K50V device when transferring it from the EPF10K50 device.

Conﬁguration Schemes

The configuration data for a FLEX 10K device can be loaded with one of

five configuration schemes (see Table 116), chosen on the basis of the

target application. An EPC1, EPC2, EPC16, or EPC1441 configuration

device, intelligent controller, or the JTAG port can be used to control the

configuration of a FLEX 10K device, allowing automatic configuration on

system power-up.

126 Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Multiple FLEX 10K devices can be configured in any of the five

configuration schemes by connecting the configuration enable (nCE) and

configuration enable output (nCEO) pins on each device.

Device Pin-

Outs

See the Altera web site (http://www.altera.com) or the Altera Digital

Library for pin-out information.

Revision

History

The information contained in the FLEX 10K Embedded Programmable Logic

Device Family Data Sheet version 4.1 supersedes information published in

previous versions.

Version 4.1 Changes

■Updated General Description section

■Updated I/O Element section

■Updated SameFrame Pin-Outs section

■Updated Figure 16

■Updated Tables 13 and 116

■Added Note 9 to Table 19

■Added Note 10 to Table 24

■Added Note 10 to Table 28

Table 116. Data Sources for Configuration

Configuration Scheme Data Source

Configuration device EPC1, EPC2, EPC16, or EPC1441 configuration device

Passive serial (PS) BitBlaster, MasterBlaster, or ByteBlasterMV download cable, or

serial data source

Passive parallel asynchronous (PPA) Parallel data source

Passive parallel synchronous (PPS) Parallel data source

JTAG BitBlaster, MasterBlaster, or ByteBlasterMV download cable, or

microprocessor with Jam STAPL file or Jam Byte-Code file

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Altera Corporation 127

Notes:

Altera, BitBlaster, ByteBlaster, ByteBlasterMV, ClockLock, ClockBoost, EPF10K10, EPF10K10A, EPF10K20,

EPF10K30, EPF10K30A, EPF10K40, EPF10K50, EPF10K50V, EPF10K70, EPF10K100, EPF10K100A,

EPF10K130V, EPF10K250A, FastTrack, FineLine BGA, FLEX, FLEX 10K, FLEX 10KA, FLEX 10KE, MAX,

MAX+PLUS, MAX+PLUS II, MultiVolt, Quartus, and Quartus II are trademarks and/or service marks of

Altera Corporation in the United States and other countries. Altera products are protected under numerous

U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants

performance of its semiconductor products to current specifications in accordance with Altera’s standard

warranty, but reserves the right to make changes to any products and services at any time without notice.

Altera assumes no responsibility or liability arising out of the application or use of any

information, product, or service described herein except as expressly agreed to in writing by

Altera Corporation. Altera customers are advised to obtain the latest version of device

specifications before relying on any published information and before placing orders for

products or services

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FLEX 10K Embedded Programmable Logic Device Family Data Sheet

128 Altera Corporation

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