CY28SRC01ZXC - Cypress Semiconductor Corp.

PRELIMINARY

PCI-Express Clock Generato

CY28SRC01

Cypress Semiconductor Corporation • 3901 North First Street • San Jose,CA 95134 • 408-943-2600

Document #: 001-00058 Rev. *A Revised June 2, 2005

Features

• One 100-MHz differential SRC clocks

• Low-voltage frequency select input

•I

2C support with readback capabilities

• Ideal Lexmark Spread Spectrum profile for maximum

electromagnetic interference (EMI) reduction

• 3.3V power supply

• 16-pin TSSOP package

Block Diagram

Pin Configuration

VSS_SRC

VDD_SRC

SRCT0

VDD_SRC

VSS_SRC

IREF

VSSA

VDD_SRC

SDATA

VSS_REF

VDD_REF

XOUT

XIN

SCLK

XTAL

PLL Ref Freq

XOUT

XIN

OSC

SCLK

PLL

I2C

Logic

SDATA

Divider

Network

IREF

VDD_SRC

SRCT0,SRCC0

SRCC0

VDDA

16 TSSOP

PRELIMINARY CY28SRC01

Document #: 001-00058 Rev. *A Page 2 of 10

Serial Data Interface

To enhance the flexibility and function of the clock synthesizer,

a two-signal serial interface is provided. Through the Serial

Data Interface, various device functions, such as individual

clock output buffers, can be individually enabled or disabled.

The registers associated with the Serial Data Interface

initialize to their default setting upon power-up, and therefore

use of this interface is optional. Clock device register changes

are normally made upon system initialization, if any are

required. The interface cannot be used during system

operation for power management functions.

Data Protocol

The clock driver serial protocol accepts byte write, byte read,

block write, and block read operations from the controller. For

block write/read operation, the bytes must be accessed in

sequential order from lowest to highest byte (most significant

bit first) with the ability to stop after any complete byte has

been transferred. For byte write and byte read operations, the

system controller can access individually indexed bytes. The

offset of the indexed byte is encoded in the command code,

as described in Table 1.

The block write and block read protocol is outlined in Table 2

while Table 3 outlines the corresponding byte write and byte

read protocol. The slave receiver address is 11010010 (D2h).

Pin Description

Pin No. Name Type Description

7 IREF I A precision resistor (475Ω) attached to this pin is connected to the internal current

reference.

14 SCLK I,PU SMBus compatible SCLOCK.This pin has an internal pull-up, but is tri-stated in

powerdown.

15 SDATA I/O, PU SMBus compatible SDATA.This pin has an internal pull-up, but is tri-stated in

powerdown.

3,4 SRC[T/C]0 O, DIF Differential Selectable Serial reference clock.

Intel Type-X buffer.

Includes overclock support through SMBUS

12 XIN I 14.318-MHz Crystal Input

13 XOUT O 14.318-MHz Crystal Output

2, 5,16 VDD_SRC PWR 3.3V power supply for SRC outputs

1,6 VSS_SRC GND Ground for SRC outputs

9 VDDA PWR 3.3V power supply for PLL

8 VSSA GND Analog Ground

11 VDD_REF PWR Power for Xtal

10 VSS_REF GND Ground for Xtal

PRELIMINARY CY28SRC01

Document #: 001-00058 Rev. *A Page 3 of 10

Table 1. Command Code Definition

Bit Description

7 0 = Block read or block write operation, 1 = Byte read or byte write operation

(6:5) Chip select address, set to ‘00’ to access device

(4:0) Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '00000'

Table 2. Block Read and Block Write Protocol

Block Write Protocol Block Read Protocol

Bit Description Bit Description

1 Start 1 Start

8:2 Slave address – 7 bits 8:2 Slave address – 7 bits

9 Write 9 Write

10 Acknowledge from slave 10 Acknowledge from slave

18:11 Command Code – 8 bits 18:11 Command Code – 8 bits

19 Acknowledge from slave 19 Acknowledge from slave

27:20 Byte Count – 8 bits 20 Repeat start

28 Acknowledge from slave 27:21 Slave address – 7 bits

36:29 Data byte 1 – 8 bits 28 Read = 1

37 Acknowledge from slave 29 Acknowledge from slave

45:38 Data byte 2 – 8 bits 37:30 Byte Count from slave – 8 bits

46 Acknowledge from slave 38 Acknowledge

.... Data Byte /Slave Acknowledges 46:39 Data byte 1 from slave – 8 bits

.... Data Byte N – 8 bits 47 Acknowledge

.... Acknowledge from slave 55:48 Data byte 2 from slave – 8 bits

.... Stop 56 Acknowledge

.... Data bytes from slave / Acknowledge

.... Data Byte N from slave – 8 bits

.... NOT Acknowledge

Table 3. Byte Read and Byte Write Protocol

Byte Write Protocol Byte Read Protocol

Bit Description Bit Description

1Start 1Start

8:2 Slave address – 7 bits 8:2 Slave address – 7 bits

9Write 9Write

10 Acknowledge from slave 10 Acknowledge from slave

18:11 Command Code – 8 bits 18:11 Command Code – 8 bits

19 Acknowledge from slave 19 Acknowledge from slave

27:20 Data byte – 8 bits 20 Repeated start

28 Acknowledge from slave 27:21 Slave address – 7 bits

29 Stop 28 Read

29 Acknowledge from slave

37:30 Data from slave – 8 bits

38 NOT Acknowledge

39 Stop

PRELIMINARY CY28SRC01

Document #: 001-00058 Rev. *A Page 4 of 10

Control Registers

Byte 0:Control Register 0

Bit @Pup Name Description

7 0 Reserved Reserved

6 1 SRC[T/C]4 SRC[T/C]4 Output Enable- only for CY28SRC04

0 = Disable (Hi-Z),

1 = Enable

5 1 SRC[T/C]3 SRC[T/C]3 Output Enable- only for CY28SRC04

0 = Disable (Hi-Z),

1 = Enable

4 1 SRC[T/C]2 SRC[T/C]2 Output Enable- only for CY28SRC02 and CY28SRC04

0 = Disable (Hi-Z)

1 = Enable

3 1 SRC[T/C]1 SRC[T/C]1 Output Enable- only for CY28SRC02 and CY28SRC04

0 = Disable (Hi-Z), 1 = Enable

2 1 SRC [T/C]0 SRC[T/C]0 Output Enable- only for CY28SRC01

0 = Disable (Hi-Z), 1 = Enable

1 0 Reserved Reserved

0 0 Reserved Reserved

Byte 1: Control Register 1

Bit @Pup Name Description

7 0 Reserved Reserved

6 0 Reserved Reserved

5 0 Reserved Reserved

4 0 Reserved Reserved

3 0 Reserved Reserved

2 0 Reserved Reserved

1 0 Reserved Reserved

0 0 Reserved Reserved

Byte 2: Control Register 2

Bit @Pup Name Description

7 1 SRCT/C Spread Spectrum Selection

‘0’ = –0.35%

‘1’ = –0.50%

6 1 Reserved Reserved

5 1 Reserved Reserved

4 0 Reserved Reserved

3 1 Reserved Reserved

2 0 SRC SRC Spread Spectrum Enable

0 = Spread off, 1 = Spread on

1 1 Reserved Reserved

0 1 Reserved Reserved

Byte 3: Control Register 3

Bit @Pup Name Description

7 1 Reserved Reserved

6 0 Reserved Reserved

5 1 Reserved Reserved

PRELIMINARY CY28SRC01

Document #: 001-00058 Rev. *A Page 5 of 10

4 0 Reserved Reserved

3 1 Reserved Reserved

2 1 Reserved Reserved

1 1 Reserved Reserved

0 1 Reserved Reserved

Byte 3: Control Register 3 (continued)

Bit @Pup Name Description

Byte 4: Control Register 4

Bit @Pup Name Description

7 0 Reserved Reserved

6 0 Reserved Reserved

5 0 Reserved Reserved

4 0 Reserved Reserved

3 0 Reserved Reserved

2 0 Reserved Reserved

1 0 Reserved Reserved

0 1 Reserved Reserved

Byte 5: Control Register 5

Bit @Pup Name Description

7 0 Reserved Reserved

6 0 Reserved Reserved

5 0 Reserved Reserved

4 0 Reserved Reserved

3 0 Reserved Reserved

2 0 Reserved Reserved

1 0 Reserved Reserved

0 0 Reserved Reserved

Byte 6: Control Register 6

Bit @Pup Name Description

7 0 TEST_SEL REF/N or Tri-state Select

1 = REF/N Clock, 0 = Tri-state

6 0 TEST_MODE Test Clock Mode Entry Control

1 = REF/N or Tri-state mode, 0 = Normal operation

5 0 Reserved Reserved

4 1 Reserved Reserved

3 0 Reserved Reserved

2 0 Reserved Reserved

1 1 Reserved Reserved

0 1 Reserved Reserved

Byte 7: Control Register 7

Bit @Pup Name Description

7 0 Revision Code Bit 3

6 0 Revision Code Bit 2

5 1 Revision Code Bit 1

PRELIMINARY CY28SRC01

Document #: 001-00058 Rev. *A Page 6 of 10

Crystal Recommendations

The CY28SRC01 requires a Parallel Resonance Crystal.

Substituting a series resonance crystal will cause the

CY28SRC01 to operate at the wrong frequency and violate the

ppm specification. For most applications there is a 300-ppm

frequency shift between series and parallel crystals due to

incorrect loading.

Crystal Loading

Crystal loading plays a critical role in achieving low ppm perfor-

mance. To realize low ppm performance, the total capacitance

the crystal will see must be considered to calculate the appro-

priate capacitive loading (CL).

Figure 1 shows a typical crystal configuration using the two

trim capacitors. An important clarification for the following

discussion is that the trim capacitors are in series with the

crystal not parallel. It’s a common misconception that load

capacitors are in parallel with the crystal and should be

approximately equal to the load capacitance of the crystal.

This is not true.

Calculating Load Capacitors

In addition to the standard external trim capacitors, trace

capacitance and pin capacitance must also be considered to

correctly calculate crystal loading. As mentioned previously,

the capacitance on each side of the crystal is in series with the

crystal. This means the total capacitance on each side of the

crystal must be twice the specified crystal load capacitance

(CL). While the capacitance on each side of the crystal is in

series with the crystal, trim capacitors (Ce1,Ce2) should be

calculated to provide equal capacitive loading on both sides.

As mentioned previously, the capacitance on each side of the

crystal is in series with the crystal. This means the total capac-

itance on each side of the crystal must be twice the specified

load capacitance (CL). While the capacitance on each side of

the crystal is in series with the crystal, trim capacitors

(Ce1,Ce2) should be calculated to provide equal capacitance

loading on both sides.

Use the following formulas to calculate the trim capacitor

values for Ce1 and Ce2.

CL....................................................Crystal load capacitance

CLe......................................... Actual loading seen by crystal

using standard value trim capacitors

Ce..................................................... External trim capacitors

Cs ..............................................Stray capacitance (terraced)

Ci .......................................................... Internal capacitance

(lead frame, bond wires etc.)

4 1 Revision Code Bit 0

3 1 Vendor ID Bit 3

2 0 Vendor ID Bit 2

1 0 Vendor ID Bit 1

0 0 Vendor ID Bit 0

Byte 7: Control Register 7 (continued)

Bit @Pup Name Description

Table 4. Crystal Recommendations

Frequency

(Fund) Cut Loading Load Cap Drive

(max.)

Shunt Cap

(max.)

Tolerance

(max.)

Stability

(max.)

Aging

(max.)

14.31818 MHz AT Parallel 12pF - 16pF 1mW 7 pF + 50ppm + 50ppm 5 ppm

Figure 1. Crystal Capacitive Clarification

XTAL

Ce2

Ce1

Cs1 Cs2

X1 X2

Ci1 Ci2

Clock Chip

Trace

2.8pF

Trim

27pF

3 to 6p

Figure 2. Crystal Loading Example

Load Capacitance (each side)

Total Capacitance (as seen by the crystal)

Ce = 2 * CL – (Cs + Ci)

Ce1 + Cs1 + Ci1

1+Ce2 + Cs2 + Ci2

()

CLe

PRELIMINARY CY28SRC01

Document #: 001-00058 Rev. *A Page 7 of 10

Absolute Maximum Conditions

Parameter Description Condition Min. Max. Unit

VDD Core Supply Voltage –0.5 4.6 V

VDDA Analog Supply Voltage –0.5 4.6 V

VIN Input Voltage Relative to VSS –0.5 VDD + 0.5 VDC

TSTemperature, Storage Non Functional –65 +150 °C

TATemperature, Operating Ambient Functional 0 70 °C

TJTemperature, Junction Functional – 150 °C

ESDHBM ESD Protection (Human Body Model) MIL-STD-883, Method 3015 2000 – V

ØJC Dissipation, Junction to Case Mil-Spec 883E Method 1012.1 – 20 °C/W

ØJA Dissipation, Junction to Ambient JEDEC (JESD 51) – 60 °C/W

UL-94 Flammability Rating At 1/8 in. V–0

MSL Moisture Sensitivity Level 1

Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.

DC Electrical Specifications

Parameter Description Condition Min. Max. Unit

VDD_SRC,

VDDA

3.3V Operating Voltage 3.3V ± 5% 3.135 3.465 V

VILSMBUS Input Low Voltage SDATA, SCLK – 1.0 V

VIHSMBUS Input High Voltage SDATA, SCLK 2.2 – V

VIL Input Low Voltage VDD VSS – 0.3 0.8 V

VIH Input High Voltage 2.0 VDD + 0.3 V

IIL Input Leakage Current Except Pull-ups or Pull downs 0<VIN<VDD –5 5 mA

VOL Output Low Voltage IOL = 1 mA – 0.4 V

VOH Output High Voltage IOH = 1 mA 2.4 - V

IOZ High-Impedance Output Current –10 10 µA

CIN Input Pin Capacitance 3 5 pF

COUT Output Pin Capacitance 3 5 pF

LIN Pin Inductance –7nH

VXIH Xin High Voltage 0.7*VDD VDD V

VXIL Xin Low Voltage 00.3*V

DD V

IDD Dynamic Supply Current At max load and frequency – 400 mA

IPDDPower Down Supply Current PD asserted, Outputs driven – 70 mA

IPDTPower Down Supply Current PD asserted, Outputs Hi-Z - 2 mA

PRELIMINARY CY28SRC01

Document #: 001-00058 Rev. *A Page 8 of 10

Test and Measurement Set-up

The following diagram shows the test load configuration for the

differential SRC outputs.

AC Electrical Specifications

Parameter Description Condition Min. Max. Unit

Crystal

TDC XIN Duty Cycle The device will operate reliably with

input duty cycles up to 30/70 but the

REF clock duty cycle will not be within

specification

47.5 52.5 %

TPERIOD XIN Period When XIN is driven from an external

clock source

69.841 71.0 ns

TR / TFXIN Rise and Fall Times Measured between 0.3VDD and

0.7VDD

–10.0ns

SRC

TDC SRCT and SRCC Duty Cycle Measured at crossing point VOX 45 55 %

TPERIOD 100-MHz SRCT and SRCC Period Measured at crossing point VOX 9.997001 10.00300 ns

TPERIODSS 100-MHz SRCT and SRCC Period, SSC Measured at crossing point VOX 9.997001 10.05327 ns

TPERIODAbs 100-MHz SRCT and SRCC Absolute Period Measured at crossing point VOX 10.12800 9.872001 ns

TPERIODSSAbs 100-MHz SRCT and SRCC Absolute Period, SSC Measured at crossing point VOX 9.872001 10.17827 ns

TSKEW Any SRCT/C to SRCT/C Clock Skew Measured at crossing point VOX – 250 ps

TSKEW Any SRCS clock to Any SRCS clock Skew Measured at crossing point VOX - 250 ps

TCCJ SRCT/C Cycle to Cycle Jitter Measured at crossing point VOX – 125 ps

LACC SRCT/C Long Term Accuracy Measured at crossing point VOX – 300 ppm

TR / TFSRCT and SRCC Rise and Fall Times Measured from VOL = 0.175 to

VOH = 0.525V

175 700 ps

TRFM Rise/Fall Matching Determined as a fraction of

2*(TR – TF)/(TR + TF)

–20%

∆TRRise TimeVariation – 125 ps

∆TFFall Time Variation – 125 ps

VHIGH Voltage High Math averages Figure 3 660 850 mv

VLOW Voltage Low Math averages Figure 3 –150 – mv

VOX Crossing Point Voltage at 0.7V Swing 250 550 mV

VOVS Maximum Overshoot Voltage – VHIGH +

0.3

VUDS Minimum Undershoot Voltage –0.3 – V

VRB Ring Back Voltage See Figure 3. Measure SE – 0.2 V

33Ω

49.9Ω

Measurem ent

Point

2pF

475Ω

IR E F

Measurem ent

Point

2pF

100 Ω

SRCT

SRCC

ure 3. 0.7V Load Confi

uration

PRELIMINARY CY28SRC01

Document #: 001-00058 Rev. *A Page 9 of 10

of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be

used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its

products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips

I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification

as defined by Philips. All products and company names mentioned in this document may be the trademarks of their respective

holders.

Ordering Information

Part Number Package Type Product Flow

Lead-free

CY28SRC01ZXC 16-pin TSSOP Commercial, 0° to 70°C

CY28SRC01ZXCT 16-pin TSSOP - Tape and Reel Commercial, 0° to 70°C

Package Diagram

4.90[0.193]

1.10[0.043] MAX.

0.65[0.025]

0.20[0.008]

0.05[0.002]

PIN1ID

6.50[0.256]

SEATING

PLANE

0.076[0.003]

6.25[0.246]

4.50[0.177]

4.30[0.169]

BSC.

5.10[0.200]

0.15[0.006]

0.19[0.007]

0.30[0.012]

0.09[[0.003]

BSC

0.25[0.010]

0°-8°

0.70[0.027]

0.50[0.020]

0.95[0.037]

0.85[0.033]

PLANE

GAUGE

DIMENSIONS IN MM[INCHES] MIN.

MAX.

REFERENCE JEDEC MO-153

PACKAGE WEIGHT 0.05 gms

PART #

Z16.173 STANDARD PKG.

ZZ16.173 LEAD FREE PKG.

16-lead TSSOP 4.40 MM Body Z16.173

51-85091-*A

PRELIMINARY CY28SRC01

Document #: 001-00058 Rev. *A Page 10 of 10

Document History Page

Document Title: CY28SRC01 PCI-Express Clock Generator

Document Number: 001-00058

REV. ECN NO. Issue Date

Orig. of

Change Description of Change

** 358561 See ECN RGL New Data Sheet

*A 375223 See ECN RGL Byte 0 bit 7 change to RESERVED

Byte 6 bit 4 change to RESERVED

Changed shunt capacitor from 5 pF to 7 pF

Changed Cl1 and Cl 2 in figure from 33 pF to 27 pF.